MICRF505
850MHz and 950MHz ISM Band
Transceiver
General Description
The MICRF505 is a true single-chip, frequency shift
keying (FSK) transceiver intended for use in halfduplex, bidirectional RF links. The multi-channeled
FSK transceiver is intended for UHF radio
equipment in compliance with the North American
Federal Communications Commission (FCC) part
15.247 and the European Telecommunication
Standard Institute (ETSI) specification, EN300 220.
The transmitter consists of a PLL frequency
synthesizer and power amplifier. The frequency
synthesizer consists of a voltage-controlled oscillator
(VCO), a crystal oscillator, dual modulus prescaler,
programmable frequency dividers, and a phasedetector. The loop-filter is external for flexibility and
can be a simple passive circuit. The output power of
the power amplifier can be programmed to seven
levels. A lock-detect circuit detects when the PLL is
in lock. In receive mode, the PLL synthesizer
generates the local oscillator (LO) signal. The N, M,
and A values that give the LO frequency are stored
in the N0, M0, and A0 registers.
The receiver is a zero intermediate frequency (IF)
type which makes channel filtering possible with lowpower, integrated low-pass filters. The receiver
consists of a low noise amplifier (LNA) that drives a
quadrature mix pair. The mixer outputs feed two
identical signal channels in phase quadrature. Each
channel includes a pre-amplifier, a third order
Sallen-Key RC low-pass filter that protects the
following switched-capacitor filter from strong
adjacent channel signals, and a limiter. The main
channel filter is a switched-capacitor implementation
of a six-pole elliptic low pass filter. The cut-off
frequency of the Sallen-Key RC filter can be
programmed to four different frequencies: 100kHz,
150kHz, 230kHz, and 340kHz. The I and Q channel
outputs are demodulated and produce a digital data
output. The demodulator detects the relative phase
of the I and the Q channel signal. If the I channel
signal lags behind the Q channel, the FSK tone
frequency is above the LO frequency (data '1'). If the
I channel leads the Q channel, the FSK tone is
below the LO frequency (data '0'). The output of the
receiver is available on the DataIXO pin. A receive
signal strength indicator (RSSI) circuit indicates the
received signal level. All support documentation can
be found on Micrel’s web site at www.micrel.com.
October 2006
RadioWire®
Features
•
•
•
•
•
•
•
•
•
•
True single chip transceiver
Digital bit synchronizer
Received signal strength indicator (RSSI)
RX and TX power management
Power down function
Reference crystal tuning capabilities
Frequency error estimator
Baseband shaping
Three-wire programmable serial interface
Register read back function
Applications
•
•
•
•
•
•
•
1
Telemetry
Remote metering
Wireless controller
Remote data repeater
Remote control systems
Wireless modem
Wireless security system
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
General Description ................................................................................................................................................... 1
Features ..................................................................................................................................................................... 1
Applications ................................................................................................................................................................ 1
RadioWire® RF Selection Guide ............................................................................................................................... 4
Ordering Information .................................................................................................................................................. 4
Block Diagram ............................................................................................................................................................ 4
Pin Configuration........................................................................................................................................................ 5
Pin Description ........................................................................................................................................................... 5
Absolute Maximum Ratings
Operating Ratings
(2)
(1)
.................................................................................................................................... 6
................................................................................................................................................... 6
(4)
Electrical Characteristics ......................................................................................................................................... 6
Programming.............................................................................................................................................................. 9
Writing to the control registers in MICRF505 ........................................................................................................... 10
Writing to a Single Register ..................................................................................................................................... 10
Writing to All Registers............................................................................................................................................. 11
Writing to n Registers having Incremental Addresses ............................................................................................. 11
Writing to n Registers having Non-Incremental Addresses ..................................................................................... 12
Reading from the control registers in MICRF505 .................................................................................................... 12
Programming interface timing .................................................................................................................................. 12
Power on Reset........................................................................................................................................................ 13
Programming summary............................................................................................................................................ 14
Frequency Synthesizer ............................................................................................................................................ 15
Crystal Oscillator (XCO) ....................................................................................................................................... 16
VCO ...................................................................................................................................................................... 17
Charge Pump ....................................................................................................................................................... 18
PLL Filter .............................................................................................................................................................. 18
Lock Detect........................................................................................................................................................... 18
Modes of Operation .............................................................................................................................................. 18
Transceiver Sync/Non-Synchronous Mode ............................................................................................................. 19
Data Interface........................................................................................................................................................... 19
Receiver ................................................................................................................................................................... 20
Front End.............................................................................................................................................................. 20
Sallen-Key Filters ................................................................................................................................................. 20
Switched Capacitor Filter ..................................................................................................................................... 21
RSSI ..................................................................................................................................................................... 21
FEE....................................................................................................................................................................... 22
Bit Synchronizer ................................................................................................................................................... 23
Transmitter ............................................................................................................................................................... 24
Power Amplifier .................................................................................................................................................... 24
Modulator.............................................................................................................................................................. 26
Using the XCO-tune Bits .......................................................................................................................................... 28
Typical Application ................................................................................................................................................... 30
October 2006
2
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MICRF505BML/YML
MICRF505BML/YML Land pattern........................................................................................................................... 31
Layout Considerations ............................................................................................................................................. 32
Package Information MICRF505BML ...................................................................................................................... 33
Package Information MICRF505YML ...................................................................................................................... 34
Overview of programming bit ................................................................................................................................... 35
Table 1: Detailed description of programming bit .................................................................................................... 35
Table 2: Main Mode bit............................................................................................................................................. 40
Table 3: Synchronizer mode bit ............................................................................................................................... 40
Table 4: Modulation bit............................................................................................................................................. 40
Table 5: Prefilter bit .................................................................................................................................................. 40
Table 6: Power amplifier bit ..................................................................................................................................... 41
Table 7:Generation of Bitrate_clk, BitSync_clk and Mod_clk. ................................................................................. 41
Table 8: Test signals ................................................................................................................................................ 41
Table 10: Frequency Error Estimation control bit .................................................................................................... 42
Table 11: Frequency Error Estimation control bit, cont............................................................................................ 42
October 2006
3
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MICRF505BML/YML
RadioWire® RF Selection Guide
Device
MICRF500
Frequency Range
Maximum
Data Rate
Receive
Supply
Voltage
Transmit
Modulation
Type
Package
700MHz – 1.1GHz
128k Baud
12mA
2.5 to 3.4V
50mA
FSK
LQFP-44
MICRF501
300MHz – 440MHz
128k Baud
8mA
2.5 to 3.4V
45mA
FSK
LQFP-44
MICRF505
850MHz – 950MHz
200k Baud
13mA
2.0 to 2.5V
28mA
FSK
MLF™-32
MICRF506
410MHz – 450MHz
200k Baud
12mA
2.0 to 2.5V
21.5mA
FSK
MLF™-32
MICRF405
290-980MHz
200k Baud
NA
2.0-3.6V
18mA
FSK/ASK
MLF™-24
Ordering Information
Part Number
Junction Temp. Range
(1)
Package
MICRF505YML TR
–40° to +85°C
Lead free 32-Pin MLF
MICRF505BML TR
–40° to +85°C
32-Pin MLF
®
®
____________________________________________________________________________________________________
Block Diagram
SCLK
IFAMP
PA-buffer
PA
RSSI
Deviation control
DIV 2
CS
Control logic
LO-Buffer
Clock recovery
Demodulator
LNA
Main
filter
Sallen-key
ANT
LC Filter
CIBIAS
IO
Modulator
IFAMP
Main
filter
Sallen-key
DATAIXO
DATACLK
RSSI
LD
Frequency
Synthesiser
VCO
XCO
PTATBIAS
Bias
XTALIN
XTALOUT CPOUT
VARIN
Loop
filter
October 2006
4
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MICRF505BML/YML
NC
VCOVDD
VCOGND
VARIN
GND
CPOUT
DIGGND
DIGVDD
Pin Configuration
1
2
3
4
5
6
7
8
32 3130 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
XTALOUT
XTALIN
CS
SCLK
IO
DATAIXO
DATACLK
NC
CIBIAS
IFVDD
IFGND
ICHOUT
QCHOUT
RSSI
LD
NC
RFGND
PTATBIAS
RFVDD
RFGND
ANT
RFGND
GND
NC
MICRF505BML
TM
32-Pin MLF
Pin Description
Pin
Number
Pin Name
1
RFGND
2
PTATBIAS
Type
O
Pin Function
Pin
Number
Pin Name
Type
LNA and PA ground.
18
DATACLK
O
Connection for bias
resistor.
RX/TX data clock
output.
19
DATAIXO
I/O
RX/TX data
input/output.
20
IO
I/O
3-wire interface data
in/output.
21
SCLK
I
3-wire interface serial
clock.
22
CS
I
3-wire interface chip
select.
3
RFVDD
LNA and PA power
supply.
4
RFGND
LNA and PA ground.
5
ANT
6
RFGND
LNA and PA ground.
7
RFGND
LNA and PA ground.
8
NC
9
CIBIAS
10
IFVDD
I/O
O
Antenna In/Output.
No connect.
23
XTALIN
I
Connection for bias
resistor.
Crystal oscillator
input.
24
XTALOUT
O
IF/mixer power
supply.
Crystal oscillator
output.
25
DIGVDD
IF/mixer ground.
26
DIGGND
Test pin.
27
CPOUT
11
IFGND
12
ICHOUT
13
QCHOUT
O
Test pin.
14
RSSI
O
Received signal
strength indicator.
O
28
GND
29
VARIN
Digital power supply.
Digital ground.
O
PLL charge pump
output.
Substrate ground.
I
VCO varactor.
15
LD
PLL lock detect.
30
VCOGND
VCO ground.
16
NC
No connect.
31
VCOVDD
VCO power supply.
17
NC
No connect
32
NC
October 2006
O
Pin Function
5
No connect.
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Micrel
MICRF505BML/YML
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD)......................................... +2.7V
Voltage on any pin (GND = 0V)...... -0.3V to 2.7V
Storage Temperature (Ts) ................ -55°C to +150°C
(3)
ESD Rating ........................................................ 2kV
Supply voltage (VIN)............................ +2.0V to +2.5V
RF Frequencies.......................... 850MHz to 950MHz
Data Rate ................................................Rx,
915MHz to 915.5MHz
0.8
ms
3kHz bandwidth
902MHz to 927MHz
1.3
ms
915MHz to 915.5MHz
0.3
ms
Rx – Tx
0.9
ms
Switch Time , same frequency,
Tx – Rx
0.8
ms
3kHz loop bandwidth
Standby Rx
2.1
ms
Standby Tx
2.1
ms
16MHz, 9pF load, 5.6pF loading
capacitors
1.0
ms
(5)
PLL Lock Time , Rx->Rx,
20kHz bandwidth
(5)
Crystal Oscillator Start-Up Time
Charge Pump Current
VCPOUT = 1.1V, CP_HI = 0
100
125
170
µA
VCPOUT = 1.1V, CP_HI = 1
420
500
680
µA
Transmit Section
Output Power
Output Power Tolerance
Tx Current Consumption
Binary FSK Frequency
(5)
Separation
(5)
Data Rate
October 2006
RLOAD = 50Ω, Pa2-0-111
10
dBm
RLOAD = 50Ω, Pa2-0-001
-8
dBm
Over temperature range
2
dB
Over power supply range
3
dB
RLOAD = 50Ω, Pa2-0-111
28
mA
14
RLOAD = 50Ω, Pa2-0-001
mA
Birate = 200kbps
20
500
kHz
VCO modulation
20
200
kbps
20
kbps
Divider modulation
6
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Symbol
MICRF505BML/YML
Parameter
Occupied bandwidth
Condition
(5)
Max
Units
38.4kbps, β = 2, 20dBc
120
kHz
125kbps, β = 2, 20dBc
450
kHz
200kbps, β = 2, 20dBc
750
kHz
ETSI EN300 220
-54
dBm
(5)
(Using antenna matching network)
-30
dBm
-20
dBc
Spurious Emission > 1GHz
2
Typ
(5)
Spurious Emission < 1GHz
nd
Min
Harmonic
rd
3 Harmonic
FCC part 15, RLoad 50Ω
-41.2
dBm
Spurious Emission 928MHz
Receive Section
Rx Current Consumption
All functions turned on
13.5
mA
LNA bypass
10.9
mA
Switch cap filter bypass with LNA
10.9
mA
8.6
mA
4
mA
2.4kbps, β = 16, SC=50kHz, BER
-3
10
-111
dBm
4.8kbps, β = 16, SC=50kHz, BER
-3
10
-110
dBm
19.2kbps, β = 8, SC=200kHz,
-3
BER 10
-107
dBm
-3
-104
dBm
-3
-101
dBm
-3
-100
dBm
-3
200kbps, β = 2, BER 10
-97
dBm
125kbps, β = 2
-12
dBm
20kbps, β = 10
-10
dBm
4
dB
Bypass of Switch cap and LNA
Rx Current Consumption Variation
Receiver Sensitivity
Over temperature
38.4kbps, β = 4, BER 10
76.8kbps, β = 2, BER 10
125kbps, β = 2, BER 10
Receiver Maximum Input Power
Receiver Sensitivity Tolerance
Over temperature
Over power supply range
Receiver Bandwidth
Co-Channel Rejection
Adjacent Channel Rejection
Blocking
kHz
dB
500kHz spacing, 19.2kbps, Main
filter cut off frequency 133kHz
dB
1MHz ,19.2kbps, Main filter cut off
frequency 133kHz
dB
Desired signal:
19.2 kbps, β =6,
3dB above sens,
SC=133 kHz
Offset ±1MHz
55
dB
Offset ±2MHz
58
dB
Offset ±5MHz
48
dB
Offset ±10MHz
50
dB
Offset ±30MHz
60
dB
-34
dBm
2 tones with 1MHz separation
LO Leakage
October 2006
dB
350
19.2 kbps, β = 6, SC=133 kHz
1dB Compression
Input IP3
1
50
7
-25
dBm
-90
dBm
M9999-103106
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Micrel
Symbol
MICRF505BML/YML
Parameter
Condition
Spurious Emission
Min
Typ
1GHz, EN 300 220
(5)
Max
Units
-57
dBm
-47
dBm
Input Impedance
50
Ω
RSSI Dynamic Range
50
dB
Pin = -110dBm
0.9
V
Pin = -60dBm
2
V
RSSI Output Range
Digital
Inputs/
Output
s
VIH
Logic Input High
VIL
Logic Input Low
0.7VDD
VDD
0
0.3VDD
V
10
MHz
(5)
Clock/Data Frequency
V
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. Specification for packaged product only.
5. Guaranteed by design.
October 2006
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Micrel
MICRF505BML/YML
Programming
General
The MICRF505 functions are enabled through a
number of programming bits. The programming bits
are organized as a set of addressable control
registers, each register holding 8 bits.
There are 23 control registers in total in the
MICRF505, and they have addresses ranging from 0
to 22. The user can read all the control registers.
The user can write to the first 22 registers (0 to 21);
the register 22 is a read-only register.
All control registers hold 8 bits and all 8 bits must be
written to when accessing a control register, or they
will be read. Some of the registers do not utilize all 8
bits. The value of an unused bit is “don’t care.”
The control register with address 0 is referred to as
ControlRegister0, the control register with address 1
is ControlRegister1 and so on. A summary of the
control registers is given in the table below. In
addition to the unused bits (marked with”-“) there are
a number of mandatory bits (marked with “0” or “1”).
Always maintain these as shown in the table.
The control registers in MICRF505 are accessed
through a 3-wire interface; clock, data and chip
select. These lines are referred to as SCLK, IO, and
CS, respectively. This 3-wire interface is dedicated
to control register access and is referred to as the
control interface. Received data (via RF) and data to
transmit (via RF) are handled by the DataIXO and
DataClk (if enabled) lines; this is referred to as the
data interface.
The SCLK line is applied externally; access to the
control registers are carried out at a rate determined
by the user. The MICRF505 will ignore transitions on
the SCLK line if the CS line is inactive. The
MICRF505 can be put on a bus, sharing clock and
data lines with other devices.
All control registers should be written to after a
battery reset. During operation, it is sufficient to write
to one register only. The MICRF505 will
automatically enter power down mode after a battery
reset.
Adr
A6…A0
Data
D7
D6
D5
D4
D3
D2
D1
D0
0000000
LNA_by
PA2
PA1
PA0
Sync_en
Mode1
Mode0
Load_en
0000001
Modulation1
Modulation0
‘0’
‘0’
RSSI_en
LD_en
PF_FC1
PF_FC0
0000010
CP_HI
SC_by
‘0’
PA_By
OUTS3
OUTS2
OUTS1
OUTS0
0000011
‘1’
‘1’
‘0’
VCO_IB2
VCO_IB1
VCO_IB0
VCO_freq1
VCO_freq0
0000100
Mod_F2
Mod_F1
Mod_F0
Mod_I4
Mod_I3
Mod_I2
Mod_I1
Mod_I0
0000101
-
-
‘0’
‘1’
Mod_A3
Mod_A2
Mod_A1
Mod_A0
0000110
-
Mod_clkS2
Mod_clkS1
Mod_clkS0
BitSync_clkS2
BitSync_clkS1
BitSync_clkS0
BitRate_clkS2
0000111
BitRate_clkS1
BitRate_clkS0
RefClk_K5
RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
0001000
‘1’
‘1’
ScClk5
ScClk4
ScClk3
ScClk2
ScClk1
ScClk0
0001001
‘0’
‘0’
‘1’
XCOtune4
XCOtune3
XCOtune2
XCOtune1
XCOtune0
0001010
-
-
A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
0001011
-
-
-
-
N0_11
N0_10
N0_9
N0_8
0001100
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
0001101
-
-
-
-
M0_11
M0_10
M0_9
M0_8
0001110
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
0001111
-
-
A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
0010000
-
-
-
-
N1_11
N1_10
N1_9
N1_8
0010001
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
0010010
-
-
-
-
M1_11
M1_10
M1_9
M1_8
0010011
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
0010100
‘1’
‘0’
‘1’
‘1’
‘0’
‘1’
‘0’
‘1’
0010101
-
-
-
-
FEEC_3
FEEC_2
FEEC_1
FEEC_0
0010110
FEE_7
FEE_6
FEE_5
FEE_4
FEE_3
FEE_2
FEE_1
FEE_0
Names of programming bits, unused bits (“-“) and mandatory bits (“1” or “0”) are shown. Change of mandatory bits may cause malfunction.
Table 1. Control Registers in MICRF505
October 2006
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Micrel
MICRF505BML/YML
The two different ways to “program the chip” are:
Writing to the control registers in MICRF505
Writing: A number of octets are entered into
MICRF505 followed by a load-signal to activate the
new setting. Making these events is referred to as a
“write sequence.” It is possible to update all, 1, or n
control registers in a write sequence. The address to
write to (or the first address to write to) can be any
valid address (0-21). The IO line is always an input
to the MICRF505 (output from user) when writing.
The address of the control register to be
written (or if more than 1 control register
st
should be written to, the address of the 1
control register to write to).
•
A bit to enable reading or writing of the
control registers. This bit is called the R/W
bit.
•
The values
register(s).
to
write
into
the
Write to a number of control registers (0-22)
when the registers have incremental
addresses (write to 1, all or n registers)
•
Write to a number of control registers when
the
registers
have
non-incremental
addresses.
Writing to a Single Register
Writing to a control register with address “A6. A5,
…A0” is described here. During operation, writing to
1 register is sufficient to change the way the
transceiver works. Typical example: Change from
receive mode to power-down.
What to write:
•
•
What to write:
control
Field
Comments
Address:
7 bit = A6, A5, …A0 (A6 = msb. A0 = lsb)
R/W bit:
“0” for writing
Values:
8 bits = D7, D6, …D0 (D7 = msb, D0 = lsb)
Table 3.
What to write:
Field
Comments
Address:
A 7-bit field, ranging from 0 to 21. MSB is
written first.
R/W bit:
A 1-bit field, = “0” for writing
Values:
A number of octets (1-22 octets). MSB in
every octet is written first. The first octet is
written to the control register with the
specified address (=”Address”). The next
octet (if there is one) is written to the control
register with address = “Address + 1” and so
on.
“Address” and “R/W bit” together make 1 octet.
In addition, 1 octet with programming bits is entered. In
total, 2 octets are clocked into the MICRF505.
How to write:
•
Bring CS high
•
Use SCLK and IO to clock in the 2 octets
•
Bring CS low
CS
Table 2.
SCLK
How to write:
IO
Bring CS active to active to start a write sequence.
The active state of the CS line is “high.” Use the
SCLK/IO serial interface to clock “Address” and
“R/W” bit and “Values” into the MICRF505.
MICRF505 will sample the IO line at negative edges
of SCLK. Make sure to change the state of the IO
line before the negative edge. Refer to figures
below.
Bring CS inactive to make an internal load-signal
and complete the write-sequence. Note: there is an
exception to this point. If the programming bit called
“load_en” (bit0 in ControlRegister0) is “0”, then no
load pulse is generated.
October 2006
A6
A5
A0
Address of register i
RW
D7
RW
D6
D2
D1
D0
Data to write into register i
Internal load pulse made here
Figure 1.
In Figure 1, IO is changed at positive edges of SCLK. The
MICRF505 samples the IO line at negative edges. The
value of the R/W bits is always “0” for writing.
10
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Micrel
MICRF505BML/YML
Writing to All Registers
After a power-on, all writable registers should be
written. This is described here.
Writing to n Registers having Incremental
Addresses
In addition to entering all bytes, it is also possible to
enter a set of n bytes, starting from address i = “A6,
A5, … A0”. Typical example: Clock in a new set of
frequency dividers (i.e. change the RF frequency).
“Incremental addresses”. Registers to be written are
located in i, i+1, i+2.
Writing to all register can be done at any time. To
get the simplest firmware, always write to all
registers. The price to pay for the simplicity is
increased write-time, which leads to increased time
to change the way the MICRF505 works.
What to write
What to write
Field
Comments
Field
Comments
Address:
Address:
‘000000’ (address of the first register to write
to, which is 0)
7 bit = A6, A5, …A0 (A6 = msb. A0 = lsb)
(address of first byte to write to)
R/W bit:
“0” for writing
R/W bit:
“0” for writing
Values:
n* 8 bits =
D7, D6, …D0 (D7 = msb, D0 = lsb) (written
to control reg. with address ”i”)
D7, D6, …D0 (D7 = msb, D0 = lsb) (written
to control reg. with address ”i+1”)
Values:
st
1
Octet:
wanted
values
for
nd
ControlRegister0. 2 Octet: wanted values
for ControlRegister1 and so on for all of the
nd
octets. So the 22 octet wants values for
ControlRegister21. Refer to the specific
sections of this document for actual values.
D7, D6, …D0 (D7 = msb, D0 = lsb) (written
to control reg. with address ”i+n-1”)
Table 4.
“Address” and “R/W bit” together make 1 octet.
In addition, 22 octets with programming bits are entered.
In total, 23 octets are clocked into the MICRF505.
Table 5.
“Address” and “R/W bit” together make 1 octet.
In addition, n octets with programming bits are entered.
Totally, 1 +n octets are clocked into the MICRF505.
How to write:
•
Bring CS high
•
Use SCLK and IO to clock in the 23 octets
How to write:
• Bring CS low
Refer to the figure in the next section, “Writing to n
registers having incremental addresses”.
•
Bring CS high
•
Use SCLK and IO to clock in the 1 + n
octets
•
Bring CS low
In Figure 1, IO is changed at positive edges of SCLK. The
MICRF505 samples the IO line at negative edges. The
value of the R/W bits is always “0” for writing.
CS
SCLK
IO
A6
A5
A0
Address of first
register to write to,
register i
RW
D7
D6
D2
RW Data to write
into register i
D1
D0
Data to write
into register i+1
Internal load pulse made here
Figure 2.
October 2006
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MICRF505BML/YML
Reading n registers from MICRF505
Writing to n Registers having Non-Incremental
Addresses
Registers with non-incremental addresses can be
written to in one write-sequence as well. Example of
non-incremental addresses: “0,1,3”. However, this
requires more overhead, and the user should
consider the possibility to make a “continuous”
update, for example, by writing to “0,1,2,3” (writing
the present value of “2” into “2”). The simplest
firmware is achieved by always writing to all
registers. Refer to previous sections.
This write-sequence is divided into several subparts:
•
CS
SCLK
A6
IO
A5
A0
RW D7
Address of register i
D0
D6
RWData read from reg. i
Simple time
IO Input
IO Output
Figure 3.
In the figure, 1 register is read. The address is A6,
A5, … A0. A6 = msb. The data read out is D7, D6,
…D0. The value of the R/W bit is always “1” for
reading.
SCLK and IO together form a serial interface. SCLK
is applied externally for reading as well as for writing.
Disable the generation of load-signals by
clearing
bit
“load_en”
(bit0
in
ControlRegister0)
•
Repeat for each group of register having
incremental addresses:
o Bring CS active
o Enter first address for this group,
R/W bit and values
o Bring CS inactive
o Finally, enable and make a loadsignal by setting “load_en”
Refer to the previous sections for how to write to 1 or
n (with incremental addresses) registers in the
MICRF505.
Reading from the control registers in MICRF505
The “read-sequence” is:
1. Enter address and R/W bit
2. Change direction of IO line
3. Read out a number of octets and change IO
direction back again.
It is possible to read all, 1 or n registers. The
address to read from (or the first address to read
from) can be any valid address (0-22). Reading is
not destructive, i.e. values are not changed. The IO
line is output from the MICRF505 (input to user) for a
part of the read-sequence. Refer to procedure
description below.
A read-sequence is described for reading n
registers, where n is number 1-23.
•
Bring CS active
•
Enter address to read from (or the first
address to read from) (7 bits) and
•
The R/W bit = 1 to enable reading
•
Make the IO line an input to the user (set pin
in tristate)
•
Read n octets. The first rising edge of SCLK
will set the IO as an output from the
MICRF505. MICRF will change the IO line at
positive edges. The user should read the IO
line at the negative edges.
•
Make the IO line an output from the user
again.
Programming interface timing
Figure 4 and Table 6 shows the timing specification
for the 3-wire serial programming interface.
Tcsr
traise
tfall
Tper
Thigh Tread
Tlow
Tscl
Twrite
SCLK
CS
IO
A6
A5
A0
RW
Address Register
D7
D6
D2
D1
D0
Data Register
LOAD
Figure 4.
October 2006
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Symbol
MICRF505BML/YML
Parameter
Values
Min.
50
Typ.
Max.
Units
Tper
Min. period of
SCLK
Thigh
Min. high time of
SCLK
20
ns
Tlow
Min. low time of
SCLK
20
ns
tfall
Max. time of
falling edge of
SCLK
1
µs
trise
Max. time of rising
edge of SCLK
1
µs
Tcsr
Max. time of rising
edge of CS to
falling edge of
SCLK
0
ns
Tcsf
Min. delay from
rising edge of CS
to rising edge of
SCLK
5
ns
Twrite
Min. delay from
valid IO to falling
edge of SCLK
during a write
operation
0
ns
Tread
Min. delay from
rising edge of
SCLK to valid IO
during a read
operation
(assuming load
capacitance of IO
is 25pF)
75
ns
POR
Power on Reset
delay from voltage
is supplied to he
device until POR
completed
Power on Reset
When applying voltage to the MICRF505 a power on
reset state is entered. During the time period of
power on reset, the MICRF505 should be
considered to be in an unknown state and the user
should wait until completed (See Table 6). The
power on reset timing given in Table 6 is covering all
conditions and should be treated as a maximum
delay time. In some application it might be beneficial
to minimize the power on reset time. In these cases
we recommend to follow below procedure:
ns
Program
address 0x00
Word:0x03
Read back
programmed
address 0x00
Value=0x03?
4.6
9
NO
YES
ms
End of Power on
Reset
Table 6. Timing Specification for the 3-wire
Programming Interface
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MICRF505BML/YML
Programming summary
•
Use CS, SCLK, and IO to get access to the
control registers in MICRF505.
•
SCLK is user-controlled.
•
Write to the MICRF505 at positive edges
(MICRF505 reads at negative edges).
•
Read from the MICRF505 at negative edges
(MICRF505 writes at positive edges)
•
After power-on: Write to the complete set of
control registers.
•
Address field is 7 bits long. Enter msb first.
•
R/W bit is 1 bit long (“1” for read, “0” for
write)
•
Address and R/W bit together make 1 octet
•
All control registers are 8 bits long.
Enter/read msb in every octet first.
October 2006
14
•
Always write 8 bits to/read 8 bits from a
control register. This is the case for registers
with less than 8 used programming bits as
well.
•
Writing: Bring CS high, write address and
R/W bit followed by the new values to fill into
the addressed control register(s) and bring
CS low for loading, i.e. activation of the new
control register values (“load_en” = 1).
•
Reading: Bring CS high, write address and
R/W bit, set IO as an input, read present
contents of the addressed control
register(s), bring CS low and set IO an
output.
M9999-103106
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MICRF505BML/YML
Frequency Synthesizer
derived from a crystal oscillator, which is very stable
in frequency. The block diagram below shows the
basic elements and arrangement of a PLL-based
frequency synthesizer. The MICRF505 has a dual
modulus prescaler for increased frequency
resolution. In a dual modulus prescaler the main
divider is split into two parts, the main part N and an
additional divider A, where A < N. Both dividers are
clocked from the output of the dual-modulus
prescaler, but only the output of the N divider is fed
into the phase detector. The prescaler will first divide
by 16. Both N and A count down until A reaches
zero, at which point the prescaler is switched to a
division ratio 16+1. At this point, the divider N has
completed A counts. Counting continues until N
reaches zero, which is an additional N-A counts. At
this point the cycle repeats.
The MICRF505 frequency synthesizer consists of a
voltage-controlled oscillator (VCO), a crystal
oscillator, dual modulus prescaler, programmable
frequency dividers and a phase-detector. The loopfilter is external for flexibility and can be a simple
passive circuit. The phase detector compares
frequencies of two signals and produces an error
signal which is proportional to the difference
between the input frequencies. The error signal is
used to control a voltage-controlled oscillator (VCO)
which creates an output frequency. The output
frequency is fed through a frequency divider back to
the input of the phase detector, producing a
feedback loop. If the output frequency drifts, the
error signal will increase, driving the frequency in the
opposite direction so as to reduce the error. Thus,
the output is locked to the frequency at the other
input. This input is called the reference and is
A6…A0
D7
D6
D5
D4
D3
D2
D1
D0
0001010
-
-
A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
0001011
-
-
-
-
N0_11
N0_10
N0_9
N0_8
0001100
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
0001101
-
-
-
-
M0_11
M0_10
M0_9
M0_8
0001110
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
0001111
-
-
A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
0010000
-
-
-
-
N1_11
N1_10
N1_9
N1_8
0010001
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
0010010
-
-
-
-
M1_11
M1_10
M1_9
M1_8
0010011
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
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MICRF505BML/YML
The lengths of the N, M, and A registers are 12, 12
and 6 respectively The values can be calculated
from the following formula:
CL =
The parasitic capacitance is the pin input
capacitance and PCB stray capacitance. Typically,
the total parasitic capacitance is around 6pF. For
instance, for a 9pF load crystal the recommended
values of the external load capacitors are 5.6pF.
It is also possible to tune the crystal oscillator
internally by switching in internal capacitance using
5 tune bits XCOtune4 – XCOtun0. When XCOtune4
– XCOtune0 = 0 no internal capacitors are
connected to the crystal pins. When XCOtune4 –
XCOtune0 = 1 all of the internal capacitors are
connected to the crystal pins. Figure 6 shows the
tuning range for two different capacitor values, 1.5pF
and no capacitors.
The crystal used is a TN4-26011 from Toyocom.
Specification: Package TSX-10A, Nominal frequency
16.000000 MHz, frequency tolerance ±10ppm,
frequency stability ±9ppm, load capacitance 9pF,
pulling sensitivity 15ppm/pF. When the external
capacitors are set to 1.5pF and the XCOtune=16,
the total capacitance will normally be ~9pF.
fVCO 2
f XCO
fRF
=
=
M
(16 × N + A ) (16 × N + A )
fPhD =
M≠0
1≤A38.4
0.8
56
100
10nF
100nF 6.2kΩ
0
VCO
>125
3.2
56
100
680pF
6.8nF
22kΩ
0
NC
Divider
Mod_lb
Figure 23. Modulator Waveform with and without
Filtering
Figure 21. Two Different Modulator Current Settings
Mod_F=0 disables the modulator filter and Mod_F=7
gives most filtering. Figure 23 shows a waveform
with and without the filter.
Modulator Attenuator
A third way to set the deviation is by programming
the modulator attenuator, Mod_A2..Mod_A0, the last
being LSB. The purpose of the attenuator is to allow
small deviations when the bit rate is small and/or the
BT is small (these settings will give a relatively slow
modulator clock, and therefore long rise- and fall
times, which in turn results in large frequency
deviations). In addition, the attenuator will improve
the resolution of the modulator.
Calculation of the Frequency Deviation
The parameters influencing the frequency deviation
can be summarized in the following equations:
f MOD_CLK =
f XCO
Refclk_K ⋅ 2(7-Mod_clkS)
Mod_Aa
f DEV =
Mod_Ab
Mod_I
f MOD_CLK
⋅
1
⋅ ( C1 + C2 ⋅ f RF )
1 + Mod_A
Mod_Ab > Mod_Ab
Where:
fDEV:
Figure 22. Two Different Modulator Attenuator
Settings
fXCO:
fRF:
Refclk_K:
The effect of the attenuator is given by:
f DEVIATION
Mod_clkS:
1
∝
1 + Mod_A
fMOD_CLK:
Figure 22 shows two waveforms with different
attenuator setting: Mod _ Aa < Mod _ Ab . If Mod_A is
increased, the frequency deviation is lowered and
vice versa.
Mod_I:
Mod_A:
Modulator Filter
To reduce the high-frequency components in the
generated waveform, a filter with programmable cutoff frequency can be enabled. This is done using
Mod_F2..Mod_F0, the least one being LSB. The
Mod_F should be set according to the formula:
MOD _ F =
October 2006
Single sided frequency deviation
[Hz].
Crystal oscillator frequency [Hz].
Center frequency [Hz].
6 bit divider, values between 1
and 63.
Modulator clock setting, values
between 0 and 7.
Modulator
clock
frequency,
derived
from
the
crystal
frequency,
Refclk_K
and
Mod_clkS.
Modulator
current
setting,
values between 0 and 31.
Modulator attenuator setting,
values between 0 and 15.
C1:
−4.42 ×1010
C2:
72
150 ×103
BitRate
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MICRF505BML/YML
The modulator filter will not influence the frequency
deviation as long as the programmed cut-off
frequency is above the actual bit rate.
The frequency deviation must be programmed so
that the modulation index (2 x single sided frequency
deviation/Baudrate [bps]) always is greater than or
equal to 2 including the total frequency offset
between the receiver and the transmitter:
XCO_tune value and vice versa for FEE < 0.
FEE field holds a number in the range -128, … ,
127. However, it keeps counting above/below the
range, which is:
If FEE = -128 and still counting dwn-pulses:
1) =>-129 = +127
2) 126
3) 125
…
fDEV = Baudrate + fOFFSET
The calculated fDEV should be used to calculate the
needed receiver bandwidth, see chapter Switched
capacitor filter.
To avoid this situation, always make sure max count
is between limits. Suggestion: Count for 8 (or 16)
bits only.
Procedure description:
In the procedure below, UP+DWN pulses are
counted, and only the sign of the FEE is used. The
value of n is 8 or 16.
Assumption:
A transmitter is sending a 1010… pattern at the
correct frequency and bitrate.
The wanted receiver frequency is the mid-point
between the “0” and “1” frequencies.
Using the XCO-tune Bits
The RF chip has a built-in mechanism for tuning the
frequency of the crystal oscillator and is often used
in combination with the Frequency Error Estimator
(FEE). The XCO tuning is designed to eliminate or
reduce initial frequency tolerance of the crystal
and/or the frequency stability over temperature. If
the value in XCO_tune is increased (adding
capacitance), the frequency will decrease.
The XCO uses two external capacitors (see figure
5). The value of these will strongly affect the tuning
range. With a 16.0 MHz crystal (TN4-26011 from
Toyocom), and external capacitor values of 1.5 pF,
the tuning range will be approximately symmetrical
around the center frequency. A XCO_tune >16 will
decrease the frequency and vice versa (see figure
6).
A procedure for using the XCO_tune feature in
combination with the FEE is given below. The
MICRF505 measures the frequency offset between
the demodulated signal and the LO and tune the
XCO so the LO frequency is equal to received
carrier frequency.
A procedure like this can be called during production
(storing the calibrated XCO_tune value), at regular
intervals or implemented in the communication
protocol when the frequency has changed.
Input:
Nothing
Output
The best XCO_tune
lowest IFEEI)
(giving
the
Local variables:
XCO_Present: (5-bit) holds present value
in XCO_tune bits
XCO_Step:
(4-bit)
holds
increment/decrement of XCO_tune bits
SCO_Sign: (1 bit) holds POS or NEG
(increment/cerement) increasing LO is
done by reducing the XCO_tune value
XCO TUNE PROCEDURE
INT:
XCO_Present = 0
XCO_Step = 32
XCO_Sign = NEG
The FEE will count “UP”-pulses and “DOWN”-pulses
(pulses out of the demodulator when a logic “1” or
logic “0”, resp.., is received). The FEE can count
pulses for n bits, where n = 8, 16, 32 or 64.
Example: In FEE, count UP+DOWN pulses,
counting 8 bits:
A perfect case ==> FEE = 0
If FEE > 0: LO is too low, increase LO by decreasing
October 2006
value
Control_Word =
Default RX, clocks match transmitter
LOOP:
XCO_Step = XCO_Step/2
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MICRF505BML/YML
XCO_Sign == POS?
Yes --> XCO_Present- = XCO_Step //
increase LO
No --> XCO_Present+ = XCO_Step //
decrease LO
XCO_tune bits = CXO_Present
Program RFChip
Delay > n bits
Read FEE
FEE > 0?
Yes --> XCO_Sign = POS
No --> XCO_Sing = NEG // negative or
== 0
XCO_Step > 1?
Yes --> Branch to LOOP
No -->
XCO_Sing ==POS?
Yes --> XCO_Present- = 1
Branch to FIN
FIN: RETURN, return-value = XCO_Present
October 2006
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MICRF505BML/YML
V2P5_2
V2P5_2
V2P5_2
Typical Application
R1
6k2
C3
nc
C1
100nF
10nF
V2P5_3
C11
C12
C13
1nF
10nF
1nF
1nF
TP1
TP2
3
DIGVDD
NC
4
Y1
2
C8
1
26
DIGGND
25
27
GND
CP_OUT
28
29
NC
9
V2P5_2
C10
VARIN
30
DATACLK
R5
82k
V2P5_1
V2P5_0
R7
10R
GND
23
TSX 10A, 16MHz
22
21
20
19
18
1.5pF
CS
SCLK
IO
DATAIXO
DATACLK
17
NC
nc
RFVDD
8
CIBIAS
R4
LD
7
DATAlXO
24
16
3p3
IO
MLF32
RFGND
15
2p2
ANT
RSSI
6
QCHOUT
8p2
MICRF505
14
C4
8n7
SCLK
13
C6
5
RFGND
ICHOUT
ANT
50ohm line
CS
IFGND
C5
RFVDD
IFVDD
L1
50ohm line
XTALIN
12
4
C9
1.5pF
XTALOUT
PTATBIAS
11
3
RFGND
V2P5_0 10
V2P5_3
2
VCOGND
VCOVDD
32
31
NC
1
R3 18k
V2P5_1
C2
V2P5_2
R2
0R
LD
RSSI
R6
33k
C7
1n
MICRF505 – MLF32
Item
Part
Value
Description
Manufacturer
Part Numner
1
C1
10nF
10nF X7R ±10% 0603 50V
Kyocera
CM105X7R103K50A
2
C2
100nF
100nF X7R ±10% 0603 16V
Kyocera
CM105X7R104K16A
3
C3
NC
4
C4
3.3pF
3.3pF COG ±0.25pF 0603 50V
Kyocera
CM105CG3R3C50A
5
C5
8.2pF
8.2pF COG ±0.5pF 0603 50V
Kyocera
CM105CG8R2D50A
6
C6
2.2pF
2.2pF COG ±0.25pF 0603 50V
Kyocera
CM105CG2R2C50A
7
C7
1nF
Optional
Kyocera
CM105X7R102K50A
8
C8
1.5pF
1.5pF COG ±0.25pF 0603 50V
Kyocera
CM105CG1R5C50A
CM105CG1R5C50A
9
C9
1.5pF
1.5pF COG ±0.25pF 0603 50V
Kyocera
10
C10
1nF
1nF X7R ±10% 0603 50V
Kyocera
CM105X7R102K50A
11
C11
10nF
10nF X7R ±10% 0603 50V
Kyocera
CM105X7R103K50A
12
C12
1nF
1nF X7R ±10% 0603 50V
Kyocera
CM105X7R102K50A
13
C13
1nF
1nF X7R ±10% 0603 50V
Kyocera
CM105X7R102K50A
14
R1
6.2k
6.2k ±1% 0603 50V
Kyocera
CR10-6201F
15
R2
0Ω
0Ω ±1% 0603 50V
Kyocera
CJ10-000
16
R3
18k
18k ±1% 0603 50V
Kyocera
CR10-1802F
17
R5
82k
82k ±1% 0603 50V
Kyocera
CR10-8202F
18
R6
33k
Optional
Kyocera
CR10-3302F
19
R7
10Ω
10R ±1% 0603 50V
Kyocera
CR10-10R0F
20
L1
8.7nH
8.7nH ±5% 0603
Coilcraft
0603CS-8N7XJB
21
Y1
16MHz
16MHz, 9pF, 10/10ppm
Toyocom
TN4-26011
October 2006
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Micrel
MICRF505BML/YML
MICRF505BML/YML Land pattern
Figure below shows recommended land pattern. Red circles indicate Thermal/RFGND via’s. Recommended size
is 0.300-0.350mm with a pitch of 1mm. The recommended minimum number of via’s are 9 and they should be
directly connected to ground plane providing the best RF ground and thermal performance. For best yield plugged
or open via’s should be used.
d
D2'
X
SE
E2'
e
Y
SD
D2’
E2’
SD
SE
d
3.4 ±0.02
3.4 ±0.02
4.2 ±0.05
4.2 ±0.05
0.325 ±0.25
Red circle indicates Thermal Via. Size 0.300-0.350mm
October 2006
31
e
0.5
X
0.23 ±0.02
Y
0.5 ±0.02
Units
mm
M9999-103106
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Micrel
MICRF505BML/YML
Layout Considerations
The MICRF505 is a highly integrated RF IC with only a few “hot” pins, however it is suggested to study available
reference design on www.micrel.com before starting with schematics and layout.
•
To ensure the best RF design it is important to plan the layout and dedicate area for the different circuitry.
Good RF engineering is to start with the RF circuitry making sure that general RF guidelines are met
(following points). Separate noisy circuitry and RF by placing it on the opposite side maximizing the
distance between the circuitry. The RF circuitry should be placed as close to what is considered the
ground spot (EG battery) to avoid ground currents. Place the RF circuitry in a position that ensure as
short and straight trace to the antenna connection to avoid reflections.
•
Proper ground is needed. If the PCB is 2-layer, the bottom layer should be kept only for ground. Avoid
signal traces that split the ground plane. For a 4-layer PCB, it is recommended to keep the second layer
only for ground.
•
A ground via should be placed close to all the ground pins. The bottom ground (heat sink) pad should be
penetrated with >9 ground via’s. These via’s should be “open” or “plugged” to avoid air pockets caused by
the solder paste. If such air pockets appear, the air will expand during the reflow process and may/will
cause the device to twist/move.
•
The antenna pin (pin 5) has an impedance of ~50 ohm. The antenna trace should be kept to 50 ohm to
avoid signal reflection and loss of performance. Minor deviations can be compensated by matching the
LC filter. Any transmission line calculator can be used to find the needed trace width given a board build
up. Ex: A trace width of 75 mil (1.9 mm) gives 50 impedance on a FR4 board (dielectric cons=4.4) with
copper thickness of 35µm and height (layer 1-layer 2 spacing) of 1.00 mm.
•
RF circuitry is sensitive to voltage supply and therefore caution should be taken when choosing power
circuitry. To achieve the best performance, low noise LDO’s with high PSSR should be chosen. What is
present on the voltage supply will be directly modulated to the RF spectrum causing degradation and
regulatory issues. To make sure you have the right selection, please contact local sales for the latest
Micrel offerings in power management and guidance. To avoid “pickup” from other circuitry on the VDD
lines, it is recommended to route the VDD in a star configuration with decoupling at each circuitry and at
the common connection point (see above layout). If there is noisy circuitry in the design, it is strongly
recommended to use a separate power supply and/or place low value resistors (10ohms), inductors in
series with the power supply line into these circuitry.
•
It is recommended to connect the PLL loop filter to VDD (C1, C3 and R1). The VDD connection should be
placed as close to pin 31 (VCOVDD) as possible. The MICRF505 has a integrated VCO where the
resonator circuit (varactor ) has a reference to VDD. With a common reference point, the MICRF505
(PLL) will somewhat compensate for noise present on the VDD.
•
PLL loop filter components C1, C2, C3, R1 and R2 should have a compact layout and should be placed
as close to pin 27 and 29. Avoid signal traces/bus and noisy circuitry around/close/under this area.
•
Digital high speed logic or noisy circuitry should/must be at a safe distance from RF circuitry or RF VDD
as this might/will cause degradation of sensitivity and create spurious emissions. Example of such
circuitry is LCD display, charge pumps, RS232, clock / data bus etc.
October 2006
32
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
Package Information MICRF505BML
MICRF505BML
32-Pin MLF (B)
October 2006
33
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
Package Information MICRF505YML
D
D2
E
E2
e
b
L
CPL
H
h
H2
Units
5.0
3.10±0.10
5.0
3.10±0.10
0.5
0.25
0.4±0.05
0.20
0.85±0.05
0.00~0.05
0.2
mm
October 2006
34
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
Overview of programming bit
Address
Data
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0000000
LNA_by
PA2
PA1
PA0
Sync_en
Mode1
Mode0
Load_en
0000001
Modulation1
Modulation0
OL_opamp_en
(“0”)
VCO_by
(“0”)
VCO_BIAS_s
(“0”)
PA_LDc_en
(”0”)
RSSI_en
LD_en
PF_FC1
PF_FC0
PA_by
OUTS3
OUTS2
OUTS1
OUTS0
VCO_IB2
VCO_IB1
VCO_IB0
VCO_freq1
VCO_freq0
0000010
CP_HI
SC_by
0000011
IFBias_s
(“1”)
IFA_HG
(“1”)
0000100
Mod_F2
Mod_F1
Mod_F0
Mod_I4
Mod_I3
Mod_I2
Mod_I1
Mod_I0
Mod_shape
(“1”)
Mod_A3
Mod_A2
Mod_A1
Mod_A0
0000101
-
-
Mod_FHG
(“0”)
0000110
-
Mod_clkS2
Mod_clkS1
Mod_clkS0
BitSync_clkS2
BitSync_clkS1
BitSync_clkS0
BitRate_clkS2
0000111
BitRate_clkS1
BitRate_clkS0
RefClk_K5
RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
0001000
ScClk_X2
(“1”)
Prescal_s
(“0”)
ScClk5
ScClk4
ScClk3
ScClk2
ScClk1
ScClk0
0001001
SC_HI
(“1”)
PrescalMode_s
(“0”)
XCOAR_en
(”1”)
XCOtune4
XCOtune3
XCOtune2
XCOtune1
XCOtune0
0001010
-
-
A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
0001011
-
-
-
-
N0_11
N0_10
N0_9
N0_8
0001100
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
0001101
-
-
-
-
M0_11
M0_10
M0_9
M0_8
0001110
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
0001111
-
-
A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
0010000
-
-
-
-
N1_11
N1_10
N1_9
N1_8
0010001
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
0010010
-
-
-
-
M1_11
M1_10
M1_9
M1_8
0010011
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
0010100
Div2_HI
(“1”)
LO_IB1
(“0”)
LO_IB0
(“1”)
PA_IB4
(”1”)
PA_IB3
(”0”)
PA_IB2
(”1”)
PA_IB1
(”0”)
PA_IB0
(“1”)
0010101
-
-
-
-
FEEC_3
FEEC_2
FEEC_1
FEEC_0
0010110
FEE_7
FEE_6
FEE_5
FEE_4
FEE_3
FEE_2
FEE_1
FEE_0
Table 1: Detailed description of programming bit
ADR #
0000000
0000001
BIT #
7
6
5
4
3
2
1
0
7
6
5
4
3
October 2006
NAME
By_LNA
PA2
PA1
PA0
Sync_en
Mode1
Mode0
Load_en
Modulation1
Modulation0
OL_opamp_en
PA_LDc_en
RSSI_en
DESCRIPTION
LNA bypass on/off
Power amplifier level, 3.bit
Power amplifier level, 2.bit
Power amplifier level, 1.bit
Synchronizer Mode bit
Main Mode selection 2. Bit
Main Mode selection 1. Bit
Load generation (1=enable)
Modulation selection 2.bit
Modulation selection 1.bit
“0” mandatory. Opamp in OpenLoop circuit (0=disable)
“0” mandatory. PA controlled by Lock Detect
(0=disable)
RSSI function (1=enable)
35
COMMENTS
Ref. Table 6
Ref. Table 6
Ref. Table 6
Ref. Table 3
Ref. Table 2
Ref. Table 2
Ref. Table 4
Ref. Table 4
Ref. Table 6
M9999-103106
+1 408-944-0800
Micrel
0000010
0000011
0000100
0000101
0000110
0000111
0001000
MICRF505BML/YML
2
1
0
7
6
5
4
3
2
1
0
7
6
LD_en
PF_FC1
PF_FC0
CP_HI
SC_by
VCO_by
PA_by
OUTS3
OUTS2
OUTS1
OUTS0
IFBias_s
IFA_HG
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
VCO_Bias_s
VCO_IB2
VCO_IB1
VCO_IB0
VCO_freq1
VCO_freq0
Mod_F2
Mod_F1
Mod_F0
Mod_I4
Mod_I3
Mod_I2
Mod_I1
Mod_I0
----------------Mod_FHG
Mod_shape
Mod_A3
Mod_A2
Mod_A1
Mod_A0
--------Mod_clkS2
Mod_clkS1
Mod_clkS0
BitSync_clkS2
BitSync_clkS1
BitSync_clkS0
BitRate_clkS2
BitRate_clkS1
BitRate_clkS0
RefClk_K5
RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
SC_HI
ScClk_X2
ScClk5
October 2006
Lock detect function (1=enable)
Prefilter corner frequency 2.bit
Prefilter corner frequency 1.bit
High charge-pump current (0=125uA, 1=500uA)
Bypass of Switched Capacitor filter (1=enable)
“0” mandatory. Bypass of VCO (1=enable)
Bypass of PA (1=enable)
Test pins output 4.bit
Test pins output 3.bit
Test pins output 2.bit
Test pins output 1.bit
“1” mandatory.
“1” mandatory. High gain setting in preamplifier
“0” mandatory. Select separate bias for VCO on
VCOBias pin (1=enable)
VCO bias current setting, 3. bit (111 = highest current)
VCO bias current setting, 2. bit
VCO bias current setting, 1. bit
Frequency setting of VCO, 2. bit (11=highest frequency)
Frequency setting of VCO, 1.bit
Modulator filter setting, MSB (0=filter active)
Modulator filter setting
Modulator filter setting, LSB
Modulator current setting, MSB
Modulator current setting
Modulator current setting
Modulator current setting
Modulator current setting, LSB
Reserved/not in use
Reserved/not in use
“0” mandatory. Modulator Test bit.
“1” mandatory. Modulator shape enable
Modulator attenuator setting, MSB (1=attenuator active)
Modulator attenuator setting
Modulator attenuator setting
Modulator attenuator setting, LSB
Reserved/not in use
Modulator clock setting 3.bit, MSB
Modulator clock setting 2.bit
Modulator clock setting 1.bit, LSB
BitSync clock setting 3.bit, MSB
BitSync clock setting 2.bit
BitSync clock setting 1.bit, LSB
Bitrate clock setting 3.bit, MSB
Bitrate clock setting 2.bit
Bitrate clock setting 1.bit. LSB:
Reference clock divider 6.bit, MSB
Reference clock divider 5.bit
Reference clock divider 4.bit
Reference clock divider 3.bit
Reference clock divider 2.bit
Reference clock divider 1.bit, LSB
“1” mandatory. High current in Switched Cap filter
“1” mandatory. Switched Cap clock multiplied by two
SwitchCap clock divider 6.bit MSB
36
Ref. Table 5
Ref. Table 5
Ref. Table 8
Ref. Table 8
Ref. Table 8
Ref. Table 8
M9999-103106
+1 408-944-0800
Micrel
0001001
0001010
0001011
0001100
0001101
0001110
0001111
MICRF505BML/YML
4
3
2
1
0
ScClk4
ScClk3
ScClk2
ScClk1
ScClk0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
PrescalMode_s
Prescal_s
XCOAR_en
XCOtune4
XCOtune3
XCOtune2
XCOtune1
XCOtune0
----------------A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
--------------------------------N0_11
N0_10
N0_9
N0_8
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
--------------------------------M0_11
M0_10
M0_9
M0_8
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
---------
October 2006
SwitchCap clock divider 5.bit
SwitchCap clock divider 4.bit
SwitchCap clock divider 3.bit
SwitchCap clock divider 2.bit
SwitchCap clock divider 1.bit, LSB
“0” mandatory. Selects A, N and M divider output
control of prescaler mode
“0” mandatory. Selects pulse swallow prescaler.
“1” mandatory. Set XCO amplitude regulation on.
Crystal oscillator trimming, LSB
Crystal oscillator trimming
Crystal oscillator trimming
Crystal oscillator trimming
Crystal oscillator trimming, MSB
Reserved/not in use
Reserved/not in use
A0-counter 6.bit
A0-counter 5.bit
A0-counter 4.bit
A0-counter 3.bit
A0-counter 2.bit
A0-counter 1.bit
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
N0-counter 12.bit
N0-counter 11.bit
N0-counter 10.bit
N0-counter 9.bit
N0-counter 8.bit
N0-counter 7.bit
N0-counter 6.bit
N0-counter 5.bit
N0-counter 4.bit
N0-counter 3.bit
N0-counter 2.bit
N0-counter 1.bit
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
M0-counter 12.bit
M0-counter 11.bit
M0-counter 10.bit
M0-counter 9.bit
M0-counter 8.bit
M0-counter 7.bit
M0-counter 6.bit
M0-counter 5.bit
M0-counter 4.bit
M0-counter 3.bit
M0-counter 2.bit
M0-counter 1.bit
Reserved/not in use
37
M9999-103106
+1 408-944-0800
Micrel
0010000
0010001
0010010
0010011
0010100
0010101
MICRF505BML/YML
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
October 2006
--------A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
--------------------------------N1_11
N1_10
N1_9
N1_8
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
--------------------------------M1_11
M1_10
M1_9
M1_8
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
Div2_HI
LO_IB1
LO_IB0
PA_IB4
PA_IB3
PA_IB2
PA_IB1
PA_IB0
--------------------------------FEEC_3
FEEC_2
FEEC_1
FEEC_0
Reserved/not in use
A1-counter 6.bit
A1-counter 5.bit
A1-counter 4.bit
A1-counter 3.bit
A1-counter 2.bit
A1-counter 1.bit
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
N1-counter 12.bit
N1-counter 11.bit
N1-counter 10.bit
N1-counter 9.bit
N1-counter 8.bit
N1-counter 7.bit
N1-counter 6.bit
N1-counter 5.bit
N1-counter 4.bit
N1-counter 3.bit
N1-counter 2.bit
N1-counter 1.bit
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
M1-counter 12.bit
M1-counter 11.bit
M1-counter 10.bit
M1-counter 9.bit
M1-counter 8.bit
M1-counter 7.bit
M1-counter 6.bit
M1-counter 5.bit
M1-counter 4.bit
M1-counter 3.bit
M1-counter 2.bit
M1-counter 1.bit
“1” mandatory. Sets high bias current in Div2 circuit
“0” mandatory. Bias current setting of LObuffer, MSB
“1” mandatory. Bias current setting of LObuffer, LSB
“1” mandatory. Bias current setting of PA,MSB
“0” mandatory. Bias current setting of PA
“1” mandatory. Bias current setting of PAbuffer, MSB
“0” mandatory. Bias current setting of PAbuffer
“1” mandatory. Bias current setting of PAbuffer, LSB
Reserved/not in use
Reserved/not in use
Reserved/not in use
Reserved/not in use
FEE control bit
FEE control bit
FEE control bit
FEE control bit
38
Ref. Table 9
Ref. Table 9
Ref. Table 9
Ref. Table 11
Ref. Table 11
Ref. Table 10
Ref. Table 10
M9999-103106
+1 408-944-0800
Micrel
0010110
MICRF505BML/YML
7
6
5
4
3
2
1
0
October 2006
FEE_7
FEE_6
FEE_5
FEE_4
FEE_3
FEE_2
FEE_1
FEE_0
FEE value, bit 7, MSB
FEE value, bit 6
FEE value, bit 5
FEE value, bit 4
FEE value, bit 3
FEE value, bit 2
FEE value, bit 1
FEE value, bit 0, LSB
39
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
Table 2: Main Mode bit
Mode1
Mode0
State
Comments
0
0
0
Power down
Keeps Register configuration
1
Standby
Crystal Oscillator running
1
0
Receive
Full Receive
1
1
Transmit
Full Transmit ex. PA stage
Table 3: Synchronizer mode bit
Sync_en
State
Comments
0
Rx: Bit synchronization off
Transparent reception of data
0
Tx: DataClk pin off
Transparent transmission of data
1
Rx: Bit synchronization on
Bit-clock is generated by transceiver
1
Tx: DataClk pin on.
Bit-clock is generated by transceiver
Table 4: Modulation bit
State
Comments
0
Closed loop VCO-modulation
VCO is phase-locked
1
Open loop VCO-modulation
Not recommend
1
0
Modulation by A,M and N
Modulation inside PLL
1
1
Not defined
Reserved for future use
Modulation1
Modulation0
0
0
Table 5: Prefilter bit
PF_FC1
PF_FC0
0
0
3 dB filter corner at 100 KHz
0
1
3 dB filter corner at 150 KHz
1
0
3 dB filter corner at 230 KHz
1
1
3 dB filter corner at 340 KHz
October 2006
State
40
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
Table 6: Power amplifier bit
State
PA2
PA1
PA0
0
0
0
21dB attenuation/PA off
0
0
1
18dB attenuation
0
1
0
15dB attenuation
0
1
1
12dB attenuation
1
0
0
9dB attenuation
1
0
1
6dB attenuation
1
1
0
3dB attenuation
1
1
1
Max output
PALDc_en
0
PA is turned off by PA2=PA1=PA0=0
1
PA is turned on/off by Lock Detect, LD=1 -> PA on
PA2=PA1=PA0=0 now gives 21dB attenuation
PA_By
0
Power Amplifier enabled
1
Power Amplifier bypassed, approx 20dB reduced output power.
Table 7:Generation of Bitrate_clk, BitSync_clk and Mod_clk.
S2
0
0
0
0
1
1
1
1
(*) Can not be used as BitRate_clk.
Clock frequency
(F is crystal frequency, K
is RefClk integer)
BitRate_clk
BitSync_clk
Mod_clk
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
F/(64K)
F/(32K)
F/(16K)
F/(8K)
F/(4K)
F/(2K)
F/K (*)
F (*)
Table 8: Test signals
OutS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OutS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OutS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
October 2006
OutS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IchOut
Gnd
Ip mixer
Qp mixer
Ip IFamp
Qp IFamp
Ip SC-filter
Qp SC-filter
Ip mixer
Qp mixer
Ip mixer
Qp mixer
Ip mixer
Ip IFamp
Ip SC-filter
I limiter
N-div
QchOut
Gnd
In mixer
Qn mixer
In IFamp
Qn IFamp
In SC-filter
Qn SC-filter
In mixer
Qn mixer
In mixer
Qn mixer
Qp mixer
Qp IFamp
Qp SC-filter
Q limiter
M-div
41
Ichout2 / RSSI
Gnd
Ip IFamp
Qp IFamp
Ip SC-filter
Qp SC-filter
Gnd
Gnd
Ip SC-filter
Qp SC-filter
Gnd
Gnd
ModIn
TI1
DemodUp
Demod
Phi1n
QchOut2 / NC
Gnd
In IFamp
Qn IFamp
In SC-filter
Qn SC-filter
I limiter
Q limiter
In SC-filter
Qn SC-filter
I limiter
Q limiter
PrescalMode
TQ1
DemodDn
MAout
Phi2n
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
Table 9: PAbuffer bias current setting
State
PA_IB2
PA_IB1
PA_IB0
0
0
0
PAbuffer uses bias current from PTATBias source, external resistor (Pin 2)
0
0
1
PAbuffer uses bias current from separate bias source, external resistor (Pin 8)
0
1
0
PAbuffer uses bias current from internal bias source, lowest current
0
1
1
PAbuffer uses bias current from internal bias source
1
0
0
PAbuffer uses bias current from internal bias source, typical current
1
0
1
PAbuffer uses bias current from internal bias source
1
1
0
PAbuffer uses bias current from internal bias source
1
1
1
PAbuffer uses bias current from internal bias source, highest current
Table 10: Frequency Error Estimation control bit
FEEC_1
0
0
1
FEEC_0
0
1
0
1
1
FEE Mode
Off
Counting UP pulses
Counting DN pulses
Counting UP and DN pulses. UP increments the
counter, DN decrements it.
Table 11: Frequency Error Estimation control bit, cont.
FEEC_3
0
0
1
1
FEEC_2
0
1
0
1
No. of DEMOD_DT bit used during the
measurement.
8
16
32
64
MICREL, INC. 2180 FORTUNE DRIVE, SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel
for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended
for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a
significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a
Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
October 2006
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M9999-103106
+1 408-944-0800
