MRF89XA
Data Sheet
Ultra-Low Power, Integrated ISM Band
Sub-GHz Transceiver
2019 Microchip Technology Inc.
DS70000622E
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© 2019, Microchip Technology Incorporated, All Rights Reserved.
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DS70000622E-page 2
ISBN: 978-1-5224-4986-7
2019 Microchip Technology Inc.
MRF89XA
Ultra-Low Power, Integrated ISM Band
Sub-GHz Transceiver
Features
Baseband Features
•
•
•
•
•
•
•
•
•
•
• Packet handling feature with data whitening and
automatic CRC generation
• Incoming Sync Word (pattern) recognition
• Built-in bit synchronizer for incoming data, and
clock synchronization and recovery
• 64-byte transmit/receive FIFO with preload in
Standby mode
• Supports Manchester encoding/decoding techniques
Fully integrated ultra-low power, sub-GHz transceiver
Wide-band half-duplex transceiver
Supports proprietary sub-GHz wireless protocols
Simple 4-wire SPI-compatible interface
CMOS/TTL-compatible I/Os
On-chip oscillator circuit
Dedicated clock output
Supports power-saving modes
Operating voltage: 2.1-3.6V
Low-current consumption, typically:
- 3 mA in RX mode
- 25 mA at +10 dBm in TX mode
- 0.1 μA (Typical) and 2 μA (Maximum) in
Sleep mode
• Supports Industrial temperature range (-40ºC to
+85ºC)
• Complies with ETSI EN 300-220 and FCC part 15
• Small, 32-pin TQFN package
RF/Analog Features
• Supports ISM band sub-GHz frequency ranges:
863–870, 902–928 and 950–960 MHz
• Modulation technique: Supports FSK and OOK
• Supports high data rates: Up to 200 kbps, NRZ
coding
• Reception sensitivity: Down to -107 dBm at
25 kbps in FSK, -113 dBm at 2 kbps in OOK
• RF output power: +12.5 dBm programmable in
eight steps
• Wide Received Signal Strength Indicator (RSSI),
dynamic range: 70 dB from RX noise floor
• Signal-ended RF input/output
• On-chip frequency synthesizer
• Supports PLL loop filter with lock detect
• Integrated Power Amplifier (PA) and Low Noise
Amplifiers (LNA)
• Channel filters
• On-chip IF gain and mixers
• Integrated low-phase noise VCO
2010-2019 Microchip Technology Inc.
Typical Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Home/industrial/building automation
Remote wireless control
Wireless PC peripherals
Remote keyless entry
Wireless sensor networks
Vehicle sensor monitoring
Telemetry
Data logging systems
Wireless alarm
Remote automatic meter reading
Security systems for home/industrial environments
Automobile immobilizers
Sports and performance monitoring
Wireless toy controls
Medical applications
General Description
The MRF89XA is a single chip, multi-channel FSK/OOK
transceiver capable of operating in the 863-870 MHz
and 902-928 MHz license-free ISM frequency bands, as
well as the 950-960 MHz frequency band. The low-cost
MRF89XA is optimized for very low-power
consumption. It incorporates a baseband modem with
data rates up to 200 kbps. Data handling features
include a 64-byte FIFO, packet handling, automatic
CRC generation and data whitening. Its highly
integrated architecture allows for minimum external
component count while still maintaining design
flexibility.
Preliminary
DS70000622E-page 3
MRF89XA
All critical RF and baseband functions are integrated in
the MRF89XA, which minimizes the external
component count and reduces the design time. The RF
communication parameters are made programmable
and most of them may be dynamically set. A
microcontroller, RF SAW filter, 12.8 MHz crystal, and a
few passive components are required to create a
complete, reliable radio function. The MRF89XA uses
several low-power mechanisms to reduce overall
current consumption and extend battery life. Its small
size and low-power consumption makes the MRF89XA
ideal for a wide variety of short-range radio
applications. The MRF89XA complies with European
(ETSI EN 300-220) and United States (FCC Part
15.247 and 15.249) regulatory standards.
FIGURE 1:
Pin Diagram
Figure 1 illustrates the top-view pin arrangement of the
32-pin QFN package.
PIC18FXXXX 32-PIN QFN PIN DIAGRAM
TEST5
1
TEST1
2
VCORS
3
VCOTN
4
NC(2)
RFIO
TEST4
PARS
DVRS
AVRS
VDD
TEST3
32-Pin QFN
32
31
30
29
28
27
26
25
33 GND(1)
MRF89XA
24
TEST2
23
PLOCK
22
IRQ1
21
IRQ0
CLKOUT
PLLP
7
18
SCK
TEST6
8
17
SDI
10
11
12
13
14
15
16
SDO
9
CSDAT
19
CSCON
6
TEST8
PLLN
TEST0
DATA
OSC2
20
OSC1
5
TEST7
VCOTP
Note 1: Pin 33 (GND) is located on the underside of the IC package.
2: It is recommended to connect Pin 32 (NC) to GND.
DS70000622E-page 4
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
Table of Contents
Overview ............................................................................................................................................................................................... 7
Hardware Description ......................................................................................................................................................................... 11
Functional Description ........................................................................................................................................................................ 55
Application Details .............................................................................................................................................................................. 93
Electrical Characteristics................................................................................................................................................................... 103
Packaging Information ...................................................................................................................................................................... 129
Appendix A: FSK and OOK RX Filters vs. Bit rates .......................................................................................................................... 131
Appendix B: CRC Computation in C ................................................................................................................................................. 132
Appendix C: Revision History ........................................................................................................................................................... 133
The Microchip Web Site .................................................................................................................................................................... 135
Customer Change Notification Service ............................................................................................................................................. 135
Customer Support ............................................................................................................................................................................. 135
Product Identification System ........................................................................................................................................................... 139
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2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 5
MRF89XA
NOTES:
DS70000622E-page 6
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
1.0
OVERVIEW
The high-resolution PLL allows:
Microchip's MRF89XA is a fully integrated, half-duplex,
sub-GHz transceiver. This low-power, single-chip FSK
and OOK baseband transceiver supports:
• Usage of multiple channels in any of the bands
• Rapid settling time, which allows for faster
frequency hopping
• Superheterodyne architecture
• Multi-channel, multi-band synthesizer with Phase
Locked Loop (PLL) for easy RF design
• Power Amplifier (PA)
• Low Noise Amplifier (LNA)
• I/Q two stage down converter mixers
• I/Q demodulator, FSK/OOK
• Baseband filters and amplifiers
A communication link in most applications can be
created using a low-cost 12.8 MHz crystal, a SAW filter,
and a low-cost microcontroller. The MRF89XA
provides a clock signal for the microcontroller. The
transceiver can be interfaced with many popular
Microchip PIC® microcontrollers through a 4-wire
Serial Peripheral Interface (SPI), interrupts (IRQ0 and
IRQ1), PLL lock, and clock out. The interface between
the microcontroller and MRF89XA (a typical MRF89XA
RF node) is illustrated in Figure 1-2.
The simplified block diagram of the MRF89XA is
illustrated in Figure 1-1.
The MRF89XA is a good option for low-cost, highvolume, low data rate (200 kbps), and two-way shortrange wireless applications. This device is a single-chip
FSK and OOK transceiver capable of operating in the
863-870 MHz and 902-928 MHz license-free ISM
frequency bands, and the 950-960 MHz frequency
band.
The low-cost MRF89XA is optimized for very low-power
consumption (3 mA in Receive mode). It incorporates a
baseband modem with data rates up to 200 kbps in FSK
and 32 kbps in OOK. Data handling features include a
64-byte FIFO, packet handling, automatic CRC
generation, and data whitening. The device also
supports Manchester coding techniques. Its highly
integrated architecture allows for minimum external
component count while maintaining design flexibility. All
major
RF
communication
parameters
are
programmable and most of them may be dynamically
set.
The MRF89XA supports a stable sensitivity and
linearity characteristics for a wide supply range and is
internally regulated. The frequency synthesizer of the
MRF89XA is a fully integrated integer-N type PLL. The
oscillator circuit provided on the MRF89XA device
provides the reference clock for the PLL. The
frequency synthesizer requires only five external
components, which include the PLL loop filter and the
VCO tank circuit. Low-phase noise provides for
excellent adjacent channel rejection capability, Bit Error
Rate (BER), and longer communication range.
The MRF89XA supports the following digital data
processing features:
•
•
•
•
•
Received Signal Strength Indicator (RSSI)
Sync Word recognition
Packet handling
Interrupt and flags
Different operating modes (Continuous, Buffered,
and Packet)
• Data filtering/whitening/encoding
• Baseband power amplifier
• 64-byte TX/RX FIFO
The role of the digital processing unit is to interface the
data to/from the modulator/demodulator and the
microcontroller access points (SPI, IRQ and DATA pins).
It also controls all of the Configuration registers. The
receiver's Baseband Bandwidth (BBBW) can be
programmed to accommodate various deviations and
data rates requirements.
An optional Bit Synchronizer (BitSync) is provided, to
supply a synchronous clock and data stream to a
companion microcontroller in Continuous mode, or to
fill the FIFO with glitch-free data in Buffered mode. The
transceiver is integrated with different power-saving
modes and a software wake-up time through the host
microcontroller to keep track of the activities, which
reduce the overall current consumption and extends
the battery life. The small size and low-power
consumption of the MRF89XA makes it ideal for
various short-range radio applications.
The MRF89XA complies with European (ETSI EN 300220) and United States (FCC Part 15.247 and 15.249)
regulatory standards.
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 7
MRF89XA SIMPLIFIED BLOCK DIAGRAM
OOK
Demodulator
RSSI
X
SPI
X
DATA
X
IRQ1
X
IRQ0
X
CLKOUT
X
PLOCK
Reception Block
Digital
Demodulator
I
First
Stage
Mixers
LNA
Preliminary
RFIO
Second
Stage
Mixers
IF Gain
LO1 RX
X
Q
Filtering/
Amplification
FSK
Demodulator
LO2 RX
Sync Word
LO1 TX
LO2 TX
I
I
Second
Stage
Mixers
PA
First
Stage
Mixers
Q
Q
FIFO
Modulation
(DDS, DACs,
Interpolation Filters)
Control
Interface
Post-Demodulator
2010-2019 Microchip Technology Inc.
Phase Shift to Frequency Shift
Conversion (FSK mode)
Transmission Block
LO1 TX
For General Biasing
DVRS
Supply
Block
x
x
Supply
AVRS
VCORS
PARS
PLL Block
(Comparator, VCO,
Filter, Dividers)
Frequency
Synthesis Block
LO1 RX
LO2 TX
LO2 RX
x
x
Crystal
x
x
Loop Filter
MRF89XA
DS70000622E-page 8
FIGURE 1-1:
2010-2019 Microchip Technology Inc.
FIGURE 1-2:
MRF89XA TO MICROCONTROLLER INTERFACE (NODE) BLOCK DIAGRAM
Loop
Filter
Block
Tank
Circuit
Block
Antenna
PIC® MCU
MRF89XA
RF Block
Preliminary
Saw
Filter
Matching
Circuitry
Block
PARS
RFIO
RF
Circuits
Baseband
Amplifier/
Filter/
Limiter
Power
Management
Data
Processing
Unit
Control
Interface
Memory
CSDAT
I/O
CSCON
I/O
SDI
SDO
SDO
SDI
SCK
SCK
IRQ0
INT0
IRQ1
INT1
DATA
I/O
PLOCK
I/O
CLKOUT
OSC1
Note:
The interface between the MRF89XA and the MCU depends on the Data mode of operation. For more information, refer to Section 3.8, Data
Processing.
MRF89XA
DS70000622E-page 9
Crystal Frequency = 12.8 MHz
MRF89XA
NOTES:
DS70000622E-page 10
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.0
HARDWARE DESCRIPTION
The MRF89XA is an integrated, single-chip, low-power
ISM band sub-GHz transceiver. A detailed block
diagram of the MRF89XA is illustrated in Figure 2-1.
The frequency synthesizer is clocked by an external
12.8 MHz crystal, and frequency ranges from 863-870
MHz, 902-928 MHz, and 950-960 MHz are possible.
The MRF89XA receiver employs a superheterodyne
architecture. The first IF is one-ninth of the RF
frequency (approximately 100 MHz). The second
down-conversion, down converts the I and Q signals to
baseband in the case of the FSK receiver (zero-IF) and
to a low-IF (IF2) for the OOK receiver. After the second
down-conversion stage, the received signal is channel
select filtered and amplified to a level adequate for
demodulation. Both FSK and OOK demodulation are
available. Image rejection is achieved using a SAW
filter.
The baseband I and Q signals at the transmitter side are
digitally generated by a Direct Digital Synthesis (DDS),
whose Digital-to-Analog Converters (DAC) are followed
by two anti-aliasing, low-pass filters that transform the
digital signal into analog In-Phase (I) and Quadrature
(Q) components with frequency as the selected
Frequency Deviation (fdev). The transmitter supports
both FSK and OOK modes of operation. The transmitter
has a typical output power of +12.5 dBm. An internal
transmit/receive switch combines the transmitter and
receiver circuits into a single-ended RFIO pin (pin 31).
The RFIO pin is connected through the impedance
matching circuitry to an external antenna. The device
operates in the low-voltage range of 2.1-3.6V, and in
Sleep mode, it operates at a very low-current state,
typically 0.1 µA.
2010-2019 Microchip Technology Inc.
The frequency synthesizer is based on an integer-N
PLL having PLL bandwidth of 15 kHz. Two
programmable frequency dividers in the feedback loop
of the PLL and one programmable divider on the
reference oscillator allow the LO frequency to be
adjusted. The reference frequency is generated by a
crystal oscillator running at 12.8 MHz.
The MRF89XA is controlled by a digital block that
includes registers to store the configuration settings of
the radio. These registers are accessed by a host
microcontroller through a Serial Peripheral Interface
(SPI). The quality of the data is validated using the
RSSI and bit synchronizer blocks built into the
transceiver. Data is buffered in a 64-byte transmitter or
receiver FIFO. The transceiver is controlled through a
4-wire SPI, interrupts (IRQ0 and IRQ1), PLOCK, DATA,
and Chip Select pins for SPI, which are illustrated in
Figure 2-1. On-chip regulators provide stable supply
voltages to sensitive blocks and allow the MRF89XA to
be used with supply voltages from 2.1-3.6V. Most
blocks are supplied with a voltage below 1.4V.
The MRF89XA supports the following feature blocks:
•
•
•
•
Data filtering and whitening
Bit synchronization
64-byte transmit/receive FIFO buffer
General configuration registers
These features reduce the processing load, which
allow the use of simple, low-cost, 8-bit microcontrollers
for data processing.
Preliminary
DS70000622E-page 11
MRF89XA
FIGURE 2-1:
DETAILED BLOCK DIAGRAM OF THE MRF89XA
PARS
I
Q
PA
Waveform
Generator
LO2 TX
I
RFIO
LO1 TX
Q
I
Q
LO2 TX
RSSI
OOK
Demod
BitSync
LNA
Control
FSK
Demod
LO2 RX
CSCON
CSDAT
CLKOUT
DATA
LO1 RX
LO1 RX
OSC1
XO
TEST
I LO2 RX
Q
Frequency Synthesizer
LO
Generator
OSC2
IRQ0
IRQ1
SDI
SDO
SCK
PLOCK
I
LO1 TX
Q
I
LO2 TX
Q
Preliminary
AVRS
DVRS
VCOTP
VCOTN
VCORS
PLLN
PLLP
DS70000622E-page 12
2010-2019 Microchip Technology Inc.
MRF89XA
TABLE 2-1:
PIN DESCRIPTIONS
Pin
Number
Pin Name
Pin Type
1
TEST5
Digital I/O
Test Pin. Connected to Ground during normal operation.
Digital I/O
Test Pin. Connected to Ground during normal operation.
Description
2
TEST1
3
VCORS
4
VCOTN
Analog I/O
VCO tank.
5
VCOTP
Analog I/O
VCO tank.
6
PLLN
Analog I/O
PLL loop filter.
7
PLLP
Analog I/O
PLL loop filter.
8
TEST6
Digital I/O
Test Pin. Connected to Ground during normal operation.
9
TEST7
Digital I/O
Test Pin. Connected to Ground during normal operation.
10
OSC1
Analog Input
Crystal connection.
11
OSC2
Analog Input
Crystal connection.
12
TEST0
Digital Input
Test Pin. Connected to Ground during normal operation.
13
TEST8
Digital I/O
14
CSCON
Digital Input
SPI Configure Chip Select.
15
CSDAT
Digital Input
SPI Data Chip Select.
16
SDO
Analog Output Regulated voltage supply of the VCO (0.85V).
Test Pin. Allow pin to float; do not connect signal during normal
operation.
Digital Output Serial data output interface from MRF89XA.
17
SDI
Digital Input
Serial data input interface to MRF89XA.
18
SCK
Digital Input
Serial clock interface.
19
CLKOUT
20
DATA
21
IRQ0
Digital Output Interrupt request output.
22
IRQ1
Digital Output Interrupt request output.
23
PLOCK
24
TEST2
Digital I/O
25
TEST3
Digital I/O
26
VDD
Power
Digital Output Clock output. Output clock at reference frequency divided by a programmable factor. Refer to the Clock Output Control Register
(Register 2-28) for more information.
Digital I/O
NRZ data input and output (Continuous mode).
Digital Output PLL lock detection output. Refer to the FIFO Transmit PLL and RSSI
Interrupt Request Configuration Register (Register 2-15) for more
information.
Test Pin. Connected to Ground during normal operation.
Test Pin. Connected to Ground during normal operation.
Supply voltage.
27
AVRS
Analog Output Regulated supply of the analog circuitry (1.0V).
28
DVRS
Analog Output Regulated supply of the digital circuitry (1.0V).
29
PARS
Analog Output Regulated supply of the PA (1.8V).
30
TEST4
Digital I/O
31
RFIO
Analog I/O
32
NC
—
33
Vss
Ground
2010-2019 Microchip Technology Inc.
Test Pin. Connected to Ground during normal operation.
RF input/output (for more information, see Section 2.3, RFIO Pin).
No Connection. Connected to Ground during normal operation.
Exposed Pad. Connected to Ground during normal operation.
Preliminary
DS70000622E-page 13
MRF89XA
2.1
Power Supply and Ground Block
Pins
The large value decoupling capacitors should be
placed at the PCB power input. The smaller value
decoupling capacitors should be placed at every power
point of the device and at bias points for the RF port.
Poor bypassing can lead to conducted interference,
which can cause noise and spurious signals to couple
into the RF sections, thereby significantly reducing the
performance.
To
provide
stable
sensitivity
and
linearity
characteristics over a wide supply range, the
MRF89XA is internally voltage regulated. This internal
regulated power supply block structure is illustrated in
Figure 2-2.
The power supply bypassing is essential for better
handling of signal surges and noise in the power line.
To ensure correct operation of the regulator circuit, the
decoupling capacitor connection (shown in Figure 2-2)
is recommended. These decoupling components are
recommended for any design. The power supply block
generates four regulated supplies for the analog,
digital, VCO, and the PLL blocks to reduce the voltages
for their specific requirements. However, Power-on
Reset (POR), Configuration registers, and the SPI use
the VDD supply given to the MRF89XA.
FIGURE 2-2:
It is recommended that the VDD pin have two bypass
capacitors to ensure sufficient bypass and decoupling.
However, based on the selected carrier frequency, the
bypass capacitor values vary. The trace length (VDD pin
to bypass capacitors) should be made as short as
possible.
POWER SUPPLY BLOCK DIAGRAM
1 µF
Y5V
VBAT
VDD – Pin 26
2.1 – 3.6V
External Supply
Internal Regulator
1.4 V
VINTS
Biasing:
- SPI
- Config. Registers
- POR
Analog Regulator
1.0 V
Biasing Analog
Blocks
Digital Regulator
1.0 V
VCO Regulator
0.85 V
PA Regulator
1.80 V
Biasing Digital
Blocks
Biasing:
- VCO Circuit
- Ext. VCO Tank
Biasing:
- PA Driver
- Ext. PA Choke
1 µF
Y5V
TABLE 2-2:
0.22 µF
X7R
PARS
Pin 29
VCORS
Pin 3
DVRS
Pin 28
AVRS
Pin 27
0.1 µF
X7R
0.047 µF
X7R
POWER SUPPLY PIN DETAILS
Blocks
Biasing Through
Associated Pins
Regulated Voltage
(in Volts)
POR, SPI and Configuration Registers
VDD
VDD
2.1–3.6
Regulated Supply (VINTS)
VDD
VDD
1.4
Analog
VINTS
AVRS
1.0
Digital
VINTS
DVRS
1.0
VCO
VINTS
VCORS
0.85
VDD
PARS
1.8
PA
DS70000622E-page 14
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.2
Reset Pin
The device enters the Reset mode if any of the
following events takes place:
2.4
• Power-on Reset (POR)
• Manual Reset
The POR happens when the MRF89XA is switched on
using VDD. The POR cycle takes at least 10 ms to
execute any communication operations on the SPI bus.
An external hardware or manual Reset of the
MRF89XA can be performed by asserting the TEST8
pin (pin 13) to high for 100 µs and then releasing the
pin. After releasing the pin, it takes more than 5 ms for
the transceiver to be ready for any operations. The
reset pin is driven with an open-drain output; therefore,
is pulled high while the device is in POR. The device
does not accept commands during the Reset period.
For more information, refer to Section 3.1.2, Manual
Reset.
2.3
RFIO Pin
The receiver and the transmitter share the same RFIO
pin (pin 31). Figure 2-3 illustrates the configuration of
the common RF front-end.
• In Transmit mode, the PA and the PA regulator
are ON with voltage on the PARS pin (pin 29)
equal to the nominal voltage of the regulator
(about 1.8V). The external RF choke inductance
is used to bias the PA.
• In Receive mode, the PA and PA regulator are
OFF and PARS is tied to the ground. The external
RF choke inductor is used for biasing and matching the LNA (this is implemented as a common
gate amplifier).
FIGURE 2-3:
PARS
COMMON RF INPUT AND
OUTPUT PIN DIAGRAM
PA Regulator
(1.8V)
RX ON
To
Antenna
The PA and the LNA front-ends in the MRF89XA, which
share the same Input/Output pin, are internally
matched to approximately 50.
RFIO
PA
2.4.1
Filters and Amplifiers Block
INTERPOLATION FILTER
After the digital-to-analog conversion during transmission, both I and Q signals are smoothened by interpolation filters. These interpolation filters perform low
pass filtering of the digitally generated signal and prevent the alias signals from entering the modulators.
2.4.2
POWER AMPLIFIER
The Power Amplifier (PA) integrated in the MRF89XA
operates under a regulated voltage supply of 1.8V. The
external RF choke inductor is biased by an internal
regulator output made available on the PARS pin (pin
29). Therefore, the PA output power is consistent over
the power supply range. The consistency in operation
is important for applications which allows both
predictable RF performance and battery life.
An open collector output requires biasing using an
inductor as an RF choke. For the recommended PA
bias and matching circuit details see Section 4.5.2,
Suggested PA Biasing And Matching.
Note:
Image rejection is achieved using a SAW
filter on the RF input.
The matching of the SAW filter depends on the SAW
filter selected. Many modern SAW filters have 50
input and output, which simplifies matching for the
MRF89XA. This is demonstrated in the application
circuit. If the choice of SAW filter is different than 50,
the required impedance match on the input and output
of the SAW filter is needed.
2.4.3
LOW NOISE AMPLIFIER
FIRST MIXER)
(WITH
In Receive mode, the RFIO pin (pin 31) is connected to
a fixed-gain, common-gate, Low Noise Amplifier (LNA).
The performance of this amplifier is such that the Noise
Figure (NF) of the receiver is estimated to be
approximately 7 dB.
The LNA has approximately 50 impedance, which
functions well with the proposed antenna (PCB/
Monopole) during signal transmission. The LNA is followed by an internal RF band-pass filter.
LNA
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 15
MRF89XA
2.4.4
IF GAIN AND SECOND I/Q MIXER
Following the LNA and first down-conversion, there is
an IF amplifier whose gain can be programmed from
13.5-0 dB in 4.5 dB steps, through the register
DMODREG. For more information, refer to
Section 2.14.2, Data And Modulation Configuration
Register Details. The default setting corresponds to
0 dB gain, but lower values can be used to increase the
RSSI dynamic range.
2.4.5
CHANNEL FILTERS
The second mixer stages are followed by the channel
select filters. The channel select filters have a strong
influence on the noise bandwidth and selectivity of the
receiver, and therefore, its sensitivity. Each channel
select filter features a passive second-order RC filter,
with a programmable bandwidth, and the “fine” channel
selection is performed by an active, third-order,
Butterworth filter, which acts as a low-pass filter for the
zero-IF configuration (FSK), or a complex polyphase
filter for the low-IF (OOK) configuration. For more
information on configuring passive and active filters
see Section 3.4.4, Channel Filters.
FIGURE 2-4:
2.5
Frequency Synthesizer Block
The frequency synthesizer of the MRF89XA is a fully
integrated integer-N type PLL. The crystal oscillator
provides the reference frequency for the PLL. The PLL
circuit requires only a minimum of five external
components for the PLL loop filter and the VCO tank
circuit.
Figure 2-4 illustrates a block schematic of the
MRF89XA PLL. The crystal reference frequency and
the software controlled dividers R, P, and S blocks
determine the output frequency of the PLL.
The VCO tank inductors are connected to an external
differential input. Similarly, the loop filter is also located
externally.
FREQUENCY SYNTHESIZER BLOCK DIAGRAM
MRF89XA
75 * (Pi + 1) + Si
LO
PFD
(Ri + 1)
XO
Vtune
FCOMP
OSC1
PLLP
OSC2
PLLN
VCOTP
VCOTN
VCORS
2.5.1
REFERENCE OSCILLATOR PINS
(OSC1/OSC2)
The MRF89XA has an internal, integrated oscillator
circuit, and the OSC1 and OSC2 pins are used to
connect to an external crystal resonator. The crystal
oscillator provides the reference frequency for the PLL.
The crystal oscillator circuit, with the required loading
capacitors, provides a 12.8-MHz reference signal for
the PLL. The PLL then generates the local oscillator
frequency. It is possible to “pull” the crystal to the
accurate frequency by changing the load capacitor
value. The crystal oscillator load capacitance is
typically 15 pF, which allows the crystal oscillator circuit
to accept a wide range of crystals.
DS70000622E-page 16
Choosing a higher tolerance crystal results in a lower
TX to RX frequency offset and the ability to select a
smaller deviation in baseband bandwidth. Therefore,
the recommended crystal accuracy should be 40
ppm. The guidelines for selecting the appropriate
crystal with specifications are explained in Section 4.7,
Crystal Specification and Selection Guidelines.
Note:
Preliminary
Crystal frequency error directly translates
to carrier frequency (frf), bit rate, and
frequency deviation error.
2010-2019 Microchip Technology Inc.
MRF89XA
2.5.2
CLKOUT OUTPUT PIN (CLKOUT)
2.5.3.1
The transceiver can provide a clock signal through the
CLKOUT pin (pin 19) to the microcontroller for accurate
timing, thereby eliminating the need for a second
crystal. This results in reducing the component count.
The CLKOUT is a sub-multiple of the reference
frequency and is programmable.
The two main functions of the CLKOUT output are:
• To provide a clock output for a host
microcontroller, thus saving the cost of an
additional oscillator.
• To provide an oscillator reference output.
Measurement of the CLKOUT signal enables
simple software trimming of the initial crystal
tolerance.
Note:
To minimize the current consumption of
the MRF89XA, ensure that the CLKOUT
signal is disabled when unused.
CLKOUT can be made available in any operation
mode, except Sleep mode, and is automatically
enabled at power-up.
2.5.3
PHASE-LOCKED LOOP
ARCHITECTURE
The Integer-N Phase-Locked Loop (PLL) circuitry
determines the operating frequency of the device. The
PLL maintains accuracy using the crystal-controlled
reference oscillator and provides maximum flexibility in
performance to the designers.
The high resolution of the PLL allows the use of
multiple channels in any of the bands. The on-chip PLL
is capable of performing manual and automatic
calibration to compensate for the changes in
temperature or operating voltage.
FIGURE 2-5:
PLL Lock Pin (PLOCK)
The MRF89XA features a PLL lock (PLOCK) detect
indicator. This is useful for optimizing power consumption by adjusting the synthesizer wake-up time. The
lock status can also be read on the LSTSPLL bit from
the FTPRIREG register (Register 2-15), and must be
cleared by writing a ‘1’ to this same register. The lock
status is available on the PLOCK pin (pin 23) by setting
the LENPLL bit in the FTPRIREG register.
2.5.4
VOLTAGE CONTROLLED
OSCILLATOR
The integrated Voltage Controlled Oscillator (VCO)
requires two external tank circuit inductors. As the input
is differential, the two inductors must have the same
nominal value. The performance of these components
is essential for both the phase noise and the power
consumption of the PLL. It is recommended that a pair
of high Q inductors is selected. These should be
mounted orthogonally to other inductors in the circuit
(in particular the PA choke) to reduce spurious coupling
between the PA and the VCO. For best performance,
wire wound high-Q inductors with tight tolerance should
be used as described in Section 4.0, Application
Details. In addition, such measures may reduce radiated pulling effects and undesirable transient behavior,
thus minimizing spectral occupancy.
Note:
Ensuring a symmetrical layout of VCO
inductors further improves the PLL spectral purity.
The output signal of the VCO is used as the input to the
local oscillator (LO) generator stage, as illustrated in
Figure 2-5.The VCO frequency is subdivided and used
in a series of up or down conversions for transmission
or reception.
LO VCO OUTPUT GENERATOR
LO1 RX
Receiver
LOs
I
LO2 RX
8
90º
LO
VCO Output
Q
I
LO1 TX
90º
Q
Transmitter
LOs
I
LO2 TX
8
90º
2010-2019 Microchip Technology Inc.
Preliminary
Q
DS70000622E-page 17
MRF89XA
2.6
MRF89XA Operating Modes
(Includes Power-Saving Mode)
2.6.1
This section summarizes the settings for each
operating mode of the MRF89XA to save power, which
are based on the operations and available functionality.
The timing requirements for switching between modes
are described in Section 5.3, Switching Times and
Procedures.
TABLE 2-3:
MODES OF OPERATION
Table 2-3 lists the different operating modes of the
MRF89XA that can be used to save power.
2.6.2
DIGITAL PIN CONFIGURATION VS.
CHIP MODE
Table 2-4 lists the state of the digital I/Os in each of the
above described modes of operation, regardless of the
data operating mode (Continuous, Buffered, or
Packet).
OPERATING MODES
Mode
CMOD bits
(GCONREG
Sleep
000
SPI, POR.
Standby
001
SPI, POR, Top regulator, digital regulator, XO, CLKOUT (if activated through
CLKOREG).
Active Blocks
FS
010
Same as Standby + VCO regulator, all PLL and LO generation blocks.
Receive
011
Same as FS mode + LNA, first mixer, IF amplifier, second mixer set, channel filters,
baseband amplifiers and limiters, RSSI, OOK or FSK demodulator, BitSync and all
digital features if enabled.
Transmit
100
Same as FS mode + DDS, Interpolation filters, all up-conversion mixers, PA driver,
PA and external PARS pin (pin 29) output for the PA choke.
TABLE 2-4:
Chip.Mode
Pin
PIN CONFIGURATION VS. CHIP MODE
Sleep
Mode
Standby
Receive Transmit
FS Mode
Mode
Mode
Mode
Comment
CSCON
Input
Input
Input
Input
Input
CSCON has priority over CSDAT.
CSDAT
Input
Input
Input
Input
Input
—
Output
Output
Output
Output
Output
(4)
SDO
Output only if CSCON or CSDAT = 0.
SDI
Input
Input
Input
Input
Input
—
SCK
Input
Input
Input
Input
Input
—
IRQ0(3)
High-Z
Output(1)
Output(1)
Output
Output
—
High-Z
(1)
(1)
Output
Output
—
(3)
IRQ1
Output
Output
DATA
Input
Input
Input
Output
Input
—
CLKOUT
High-Z
Output
Output
Output
Output
—
PLOCK
High-Z
Output(2)
Note 1:
2:
3:
4:
Output(2) Output(2) Output(2) —
High-Z if Continuous mode is activated; otherwise, Output.
Output if LENPLL = 1; otherwise, High-Z.
Valid logic states must be applied to inputs at all times to avoid unwanted leakage currents. Suggestions
for designers to:
• Use external pull down resistor.
• Tri-state the microcontroller interrupt pin to output when setting the MRF89XA to sleep, then reverse
when waking it up. Since the microcontroller is in control, this should be easy to do and not require
an external pull down resistor.
The SDO pin defaults to a high impedance (High-Z) state when any of the CS pins is high (the MRF89XA
is not selected).
DS70000622E-page 18
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.7
Interrupt (IRQ0 and IRQ1) Pins
2.9
The Interrupt Requests (IRQ0 and IRQ1) pins 21 and
22 provide an interrupt signal to the host
microcontroller from the MRF89XA. Interrupt requests
are generated for the host microcontroller by pulling the
IRQ0 (pin 21) or IRQ1 (pin 22) pin low or high based on
the events and configuration settings of these
interrupts. Interrupts must be enabled and unmasked
before the IRQ pins are active. For detailed functional
description of interrupts, see Section 3.8, Data
Processing.
2.8
Transmitter
The transmitter chain is based on the same doubleconversion architecture and uses the same
intermediate frequencies as the receiver chain. The
main blocks include:
• A digital waveform generator that provides the
I and Q baseband signals. This block includes
digital-to-analog converters and anti-aliasing lowpass filters.
• A compound image-rejection mixer to up-convert the baseband signal to the first IF at oneninth of the carrier frequency (frf), and a second
image-rejection mixer to up-convert the IF signal
to the RF frequency transmitter driver and power
amplifier stages to drive the antenna port.
DATA Pin
After OOK or FSK demodulation, the baseband signal
is available to the user on the DATA pin (pin 20), when
Continuous mode is selected. Therefore, in Continuous
mode, the host microcontroller directly accesses the
NRZ data to or from the modulator or demodulator,
respectively, on the bidirectional DATA pin. The SPI
Data, FIFO, and packet handler are therefore inactive.
In Buffered and Packet modes, the data is retrieved
from the FIFO through the SPI.
During transmission, the DATA pin is configured as
DATA (Data Out) and with the internal Transmit mode
disabled; this manually modulates the data from the
external host microcontroller. If the Transmit mode is
enabled, this pin can be tied “high” or can be left
unconnected.
During reception, the DATA pin is configured as DATA
(Data In); this pin receives the data in conjunction with
DCLK. The DATA pin (unused in packed mode) should
be pulled up to VDD through a 100 kΩ resistor.
FIGURE 2-6:
TRANSMITTER ARCHITECTURE BLOCK DIAGRAM
Amplification
Second
up-conversion
First
up-conversion
I
Q
Interpolation
filters
DACs
DDS
Waveform
Generator
LO2 TX
Data
Clock
I
RFIO
LO1 TX
PA
Q
I
Q
RF
2010-2019 Microchip Technology Inc.
LO2 TX
IF
Preliminary
Baseband
DS70000622E-page 19
MRF89XA
2.9.1
TRANSMITTER ARCHITECTURE
Figure 2-6 illustrates the transmitter architecture block
diagram. The baseband I and Q signals are digitally
generated by a DDS whose Digital-to-Analog
Converters (DAC) followed by two anti-aliasing lowpass filters transform the digital signal into analog inphase (I) and quadrature (Q) components whose
frequency is the selected frequency deviation, and is
set using the FDVAL bits from FDEVREG.
In FSK mode, the input data switches the relative
phase of I and Q between -90° and +90° with continuous phase. The modulation is therefore performed at
this initial stage, because the information contained in
the phase difference is converted into a frequency shift
when the I and Q signals are up-converted in the first
mixer stage. This first up-conversion stage is duplicated to enhance image rejection. The FSK convention
is such that:
DATA = 1 frf + fdev
DATA = 0 frf – fdev
FIGURE 2-7:
In OOK mode, the phase difference between the I and
Q channels is kept constant (independent of the
transmitted data). Thus, the first stage of up-conversion
creates a fixed frequency signal at the low IF = fdev (this
explains why the transmitted OOK spectrum is offset by
fdev). OOK Modulation is accomplished by switching the
PA and PA regulator stages ON and OFF. By
convention:
DATA = 1 PAon
DATA = 0 PAoff
After the interpolation filters, a set of four mixers
combines the I and Q signals and converts them into a
pair of complex signals at the second intermediate
frequency, equal to one-eighth of the LO frequency, or
one-ninth of the RF frequency. These two new I and Q
signals are then combined and up-converted to the
final RF frequency by two quadrature mixers fed by the
LO signal. The signal is pre-amplified, and then the
transmitter output is driven by a final power amplifier
stage. The I and Q signal details are illustrated in
Figure 2-7.
I(t), Q(t) Signals Overview
1
Fdev
I(t)
Q(t)
DS70000622E-page 20
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.10
Receiver
2.10.1
The receiver is based on a superheterodyne
architecture and comprises the following major blocks:
• An LNA that provides a low-noise RF gain followed by an RF band-pass filter.
• A first mixer, which down-converts the RF signal
to an intermediate frequency equal to one-ninth of
the carrier frequency (frf 100 MHz for 915 MHz
signals).
• A variable gain first-IF preamplifier followed by
two second mixers, which down-convert the first
IF signal to I and Q signals at a low frequency
(zero-IF for FSK, low-IF for OOK).
• A two-stage IF filter followed by an amplifier chain
is available for both I and Q channels. Limiters at
the end of each chain drive the I and Q inputs to
the FSK demodulator function. An RSSI signal is
also derived from the I and Q IF amplifiers to drive
the OOK detector. The second filter stage in each
channel can be configured as either a third-order
Butterworth low-pass filter for FSK operation or an
image reject polyphase band-pass filter for OOK
operation.
• An FSK arctangent type demodulator driven from
the I and Q limiter outputs, and an OOK demodulator driven by the RSSI signal. Either detector
can drive a data and clock recovery function that
provides matched filter enhancement of the
demodulated data.
FIGURE 2-8:
RECEIVER ARCHITECTURE
Figure 2-8 illustrates the receiver architecture block
diagram. The first IF is one-ninth of the RF frequency
(approximately 100 MHz). The second downconversion down-converts the I and Q signals to
baseband in the case of the FSK receiver (zero-IF) and
to a low-IF (IF2) for the OOK receiver.
After the second down-conversion stage, the received
signal is channel-select filtered and amplified to a level
adequate for demodulation. Both FSK and OOK
demodulation are available. Finally, an optional bit
synchronizer (BitSync) is provided to supply a
synchronous clock and data stream to a companion
microcontroller in Continuous mode, or to fill the FIFO
buffers with glitch-free data in Buffered mode.
Note:
Image rejection is achieved using a SAW
filter on the RF input.
RECEIVER ARCHITECTURE BLOCK DIAGRAM
Second
down-conversion
First
down-conversion
RSSI
OOK
Demod
BitSync
FSK
Demod
LO2 RX
LNA
Control Logic
- Pattern Recognition
- FIFO Handler
- SPI Interface
- Packet Handler
LO1 RX
RF
IF1
2010-2019 Microchip Technology Inc.
Baseband, IF2 in OOK
Preliminary
DS70000622E-page 21
MRF89XA
FIGURE 2-9:
FSK RECEIVER SETTING
Second
down-conversion
0
IF2 = 0
in FSK mode
LO2
RX
First
down-conversion
Image
LO1 RX
Frequency
IF1
Approx. 100 MHz
FIGURE 2-10:
DS70000622E-page 22
Frequency
OOK RECEIVER SETTING
First
down-conversion
Second
down-conversion
0
IF2 < 0
in FSK mode
equal to fo
Channel
Image
LO1 RX
Frequency
IF1
LO2 RX
Approx.
100 MHz
Preliminary
Channel
Frequency
2010-2019 Microchip Technology Inc.
MRF89XA
2.11
Serial Peripheral Interface (SPI)
All the parameters can be programmed and set through
the SPI module. Any of these auxiliary functions can be
disabled when it is not required. After power-on, all
parameters are set to default values. The programmed
values are retained during Sleep mode. The interface
supports the read out of a status register, which provides detailed information about the status of the transceiver and the received data.
The MRF89XA communicates with the host
microcontroller through a 4-wire SPI port as a slave
device. An SPI-compatible serial interface allows the
user to select, command, and monitor the status of the
MRF89XA through the host microcontroller. All the
registers are addressed through the specific addresses
to control, configure, and read status bytes.
The MRF89XA supports SPI mode 0,0, which requires
the SCK to remain idle in a low state. The CS pins,
CSCON and CSDAT based on the mode (pin 14 and
15), must be held low to enable communication
between the host microcontroller and the MRF89XA.
The device’s timing specification details are listed in
Table 5-7. The SDO pin defaults to a high impedance
(hi-Z) state when any of the CS pins is high (the
MRF89XA is not selected). This pin has a tri-state
buffer and uses a bus hold logic.
The SPI in the MRF89XA consists of the following two
sub-blocks, as illustrated in Figure 2-11:
• SPI CONFIG: This sub-block is used in all data
operation modes to read and write the configuration
registers which control all the parameters of the chip
(operating mode, frequency, and bit rate).
• SPI DATA: This sub-block is used in Buffered and
Packet mode to write and read data bytes to and
from the FIFO. (FIFO Interrupts can be used to
manage the FIFO content).
As the device uses byte writes, any of the Chip Select
(CS) pins should be pulled low for 8 bits. Data bits on
the SDI pin (pin 17) are shifted into the device upon the
rising edge of the clock on the SCK pin (pin 18)
whenever the CS pins are low. The maximum clock
frequency for the SPI clock for CONFIG mode is 6
MHz. However, the maximum SPI Clock for DATA
mode (to read/write FIFO) is 1 MHz. Data is received by
the transceiver through the SDI pin and is clocked on
the rising edge of SCK. The MRF89XA sends the data
through the SDO pin and is clocked out on the falling
edge of SCK. The Most Significant bit (MSb) is sent first
in any data.
Both of these SPIs are configured in Slave mode while
the host microcontroller is configured as the master.
They have separate selection pins (CSCON and
CSDAT) but share the remaining pins:
• SCK (SPI Clock): Clock signal provided by the
host microcontroller
• SDI (SPI Input): Data Input signal provided by the
host microcontroller
• SDO (SPI Output): Data Output signal provided
by the MRF89XA
As listed in Table 2-5, only one interface can be
selected at a time, with CSCON having the priority:
TABLE 2-5:
The SPI sequence diagrams are illustrated in
Figure 2-12 through Figure 2-15.
CONFIG VS. DATA SPI
SELECTION
CSDAT
CSCON
SPI
0
0
1
1
0
1
0
1
CONFIG
DATA
CONFIG
None
FIGURE 2-11:
SPI OVERVIEW AND HOST MICROCONTROLLER CONNECTIONS
MRF89XA
CSCON
Configuration
Config.
Registers
SPI
CONFIG
(Slave)
SDI
SDO
SCK
I/O
SDO
SDI
SCK
I/O
FIFO
2010-2019 Microchip Technology Inc.
SPI
DATA
(Slave)
PIC® Microcontroller
(Master)
CSDAT
Preliminary
DS70000622E-page 23
MRF89XA
2.11.1
SPI CONFIG
Note:
Write Register - To write a value into a Configuration
register, the timing diagram illustrated in Figure 2-12
should be followed by the host microcontroller. The
new value of the register is effective from the rising
edge of CSCON.
FIGURE 2-12:
When writing more than one register successively, it is not compulsory to toggle
CSCON back high between two write
sequences. The bytes are alternatively
considered as address and value. In this
instance, all new values become effective
on the rising edge of CSCON.
WRITE REGISTER SEQUENCE
1
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
D(2)
D(1)
D(0)
D(2)
D(1)
CSCON (In)
SCK (In)
New value at
address A1
SDI (In)
rw
start
A(4)
A(3)
A(2)
A(1) A(0)
stop
D(7)
D(6)
x
x
HZ
(input)
x
x
x
D(4)
D(3)
Current value at
address A1*
Address = A1
SDO (Out)
D(5)
x
x
x
D(7)
D(6)
D(5)
D(4)
D(3)
D(0)
HZ
(input)
* when writing the new value at address A1, the current content of A1 can be read by the µC.
(In)/(Out) refers to MRF89XA side
Read Register - To read the value of a Configuration
register, the timing diagram illustrated in Figure 2-13
should be followed by the host microcontroller.
FIGURE 2-13:
Note:
When reading more than one register successively, it is not compulsory to toggle
CSCON back high between two read
sequences. The bytes are alternatively
considered as address and value.
READ REGISTER SEQUENCE
1
2
3
4
5
6
7
8
9
start
rw
A(4)
A(3)
A(2)
A(1)
A(0)
stop
xx
10
11
12
13
14
15
x
x
xx
16
CSCON (In)
SCK (In)
SDI(In)
xx
Current value at
address A1
Address = A1
SDO (Out)
HZ
(input)
x
DS70000622E-page 24
x
x
x
x
x
x
x
D(7)
Preliminary
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
HZ
(input)
2010-2019 Microchip Technology Inc.
MRF89XA
2.11.2
SPI DATA
Note:
Write Byte (before/during TX) - To write bytes into the
FIFO, the timing diagram illustrated in Figure 2-14
should be followed by the host microcontroller.
FIGURE 2-14:
It is compulsory to toggle CSDAT back
high between each byte written. The byte
is pushed into the FIFO on the rising edge
of CSDAT.
WRITE BYTES SEQUENCE (EXAMPLE DIAGRAM FOR 2 BYTES)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
CSDAT(In)
SCK (In)
1stbyte written
2ndbyte written
SDI (In)
D1(7) D1(6) D1(5) D1(4) D1(3)D1(2) D1(1) D1(0)
x
SDO (Out)HZ
(input)
x
x
x
x
x
x
x
x
D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0)
Read Byte (after/during RX) - To read bytes from the
FIFO, the timing diagram illustrated in Figure 2-15
should be followed by the host microcontroller.
FIGURE 2-15:
x
HZ
(input)
x
Note:
x
x
x
x
x
x
x HZ
(input)
It is recommended to toggle CSDAT back
high between each byte read.
READ BYTES SEQUENCE (EXAMPLE DIAGRAM FOR 2 BYTES)
1
2
3
4
5
6
7
8
x
x
x
x
x
x
x
x
1
2
3
4
5
6
7
8
x
x
x
x
x
x
x
x
CSDAT (In)
SCK (In)
SDI (In)
x
Second byte read
First byte read
D1(7)
SDO (Out)HZ
(input)
D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) D1(0)
2010-2019 Microchip Technology Inc.
D2(7)
HZ
(input)
Preliminary
D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0)
HZ
(input)
DS70000622E-page 25
MRF89XA
2.12
FIFO and Shift Register (SR)
2.13
In Buffered and Packet modes of operation, data to be
transmitted and data that has been received are stored
in a configurable First In First Out (FIFO) buffer. The
FIFO is accessed through the SPI data interface and
provides several interrupts for transfer management.
MRF89XA Configuration, Control
and Status Registers
The memory in the MRF89XA transceiver is
implemented as static RAM and is accessible through
the SPI port. The memory configuration of the
MRF89XA is illustrated in Figure 2-17 and Figure 2-18.
The FIFO is 1 byte (8 bits) wide; therefore, it only
performs byte (parallel) operations, whereas the
demodulator functions serially. A shift register (SR) is
therefore employed to interface the demodulator and
the FIFO. In Transmit mode, it takes bytes from the
FIFO and outputs them serially (MSB first) at the
programmed bit rate to the modulator. Similarly, in
Receive mode, the shift register gets bit-by-bit data
from the demodulator and writes them byte-by-byte to
the FIFO. This is illustrated in Figure 2-16.
FIGURE 2-16:
FIFO AND SHIFT
REGISTER
FIFO
Byte 1
Byte 0
8
Data TX/RX
SR (8 bits)
1
MSB
FIGURE 2-17:
LSB
MRF89XA MEMORY SPACE
0x00
0x00
Transmit/Receive
Control Registers
FIFO
0x1F
64 bytes
0x40
Data TX/RX
SHIFT REGISTER
(8 bits)
1
MSB
DS70000622E-page 26
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
FIGURE 2-18:
MRF89XA REGISTERS MEMORY MAP
Register Name
Register Name
0x00
GCONREG
0x10
FILCREG
0x01
DMODREG
0x11
PFCREG
0x02
FDEVREG
0x12
SYNCREG
0x03
BRSREG
0x13
RESVREG
0x04
FLTHREG
0x14
RSTSREG
0x05
FIFOCREG
0x15
OOKCREG
0x06
R1CREG
0x16
SYNCV31REG
0x07
P1CREG
0x17
SYNCV23REG
0x08
S1CREG
0x18
SYNCV15REG
0x09
R2CREG
0x19
SYNCV07REG
0x0A
P2CREG
0x1A
TXCONREG
0x0B
S2CREG
0x1B
CLKOREG
0x0C
PACREG
0x1C
PLOADREG
0x0D
FTXRXIREG
0x1D
NADDSREG
0x0E
FTPRIREG
0x1E
PKTCREG
0x0F
RSTHIREG
0x1F
FCRCREG
The
MRF89XA
registers
handle
command,
configuration, control, status, or data/FIFO fields as
listed in Table 2-6. The registers operate on
parameters common to transmit and receive modes,
Interrupts, Sync pattern, crystal oscillator, and packets.
The FIFO serves as a buffer for data transmission and
reception. There is a shifted register (SR) to handle bit
shifts for the FIFO during transmission and reception.
POR sets default values in all Configuration/Control/
Status registers.
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 27
MRF89XA
TABLE 2-6:
CONFIGURATION/CONTROL/STATUS REGISTER DESCRIPTION
General Configuration Registers: Size – 13 Bytes, Start Address – 0x00
Register
Address
Register
Name
Register Description
0x00
GCONREG
General Configuration Register
0x01
DMODREG
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
FDEVREG
BRSREG
FLTHREG
FIFOCREG
R1CREG
P1CREG
S1CREG
R2CREG
P2CREG
S2CREG
PACREG
Data and Modulation Configuration
Register
Frequency Deviation Control Register
Bit Rate Set Register
Floor Threshold Control Register
FIFO Configuration Register
R1 Counter Set Register
P1 Counter Set Register
S1 Counter Set Register
R2 Counter Set Register
P2 Counter Set Register
S2 Counter Set Register
Power Amplifier Control Register
Related Control Functions
Transceiver mode, frequency band
selection, VCO trimming, PLL frequency
dividers selection
Modulation type, Data mode, OOK
threshold type, IF gain
Frequency deviation in FSK Transmit mode
Operational bit rate
Floor threshold in OOK Receive mode
FIFO size and threshold
Value input for R1 counter
Value input for P1 counter
Value input for S1 counter
Value input for R2 counter
Value input for P2 counter
Value input for S2 counter
Ramp Control of PA regulator output
voltage in OOK
Interrupt Configuration Registers: Size – 3 Bytes, Start Address – 0x0D
Register
Address
Register
Name
Register Description
0x0D
FTXRXIREG
FIFO, Transmit and Receive Interrupt
Request Configuration Register
0x0E
FTPRIREG
FIFO Transmit PLL and RSSI Interrupt
Configuration Register
0x0F
RSTHIREG
RSSI Threshold Interrupt Request
Configuration Register
Related Control Functions
Interrupt request (IRQ0 and IRQ1) in
Receive mode, interrupt request (IRQ1) in
Transmit mode, interrupt request for FIFO
full, empty and overrun
FIFO fill method, FIFO fill, interrupt request
(IRQ0) for transmit start, interrupt request
for RSSI, PLL lock enable and status
RSSI threshold for interrupt
Receiver Configuration Registers: Size – 6 Bytes, Start Address – 0x10
Register
Address
Register
Name
Register Description
0x10
FILCREG
Filter Configuration Register
0x11
PFCREG
Polyphase Filter Configuration Register
0x12
SYNCREG
Sync Control Register
0x13
RESVREG
Reserved Register
DS70000622E-page 28
Preliminary
Related Control Functions
Passive filter bandwidth selection, sets the
receiver bandwidth
(Butterworth filter)
Selects the central frequency of the
polyphase filter
Enables polyphase filter (in OOK receive
mode, bit synchronizer control, Sync Word
recognition, Sync Word size, Sync Word
error
Reserved for future use
2010-2019 Microchip Technology Inc.
MRF89XA
TABLE 2-6:
CONFIGURATION/CONTROL/STATUS REGISTER DESCRIPTION (CONTINUED)
Receiver Configuration Registers: Size – 6 Bytes, Start Address – 0x14
Register
Address
0x14
0x15
Register
Name
RSTSREG
OOKCREG
Register Description
RSSI Status Read Register
OOK Configuration Register
Related Control Functions
RSSI output
RSSI threshold size in OOK demodulator,
RSSI threshold period in OOK demodulator,
cut-off frequency of the OOK threshold in
demodulator
Sync Word Configuration Registers: Size – 4 Bytes, Start Address – 0x16
Register
Address
0x16
0x17
0x18
0x19
Register
Name
Register Description
SYNCV31REG Sync Value 1st Byte Configuration
Register
SYNCV23REG Sync Value 2nd Byte Configuration
Register
SYNCV15REG Sync Value 3rd Byte Configuration
Register
SYNCV07REG Sync Value 4th Byte Configuration
Register
Related Control Functions
Configuring first byte of the 32-bit
Sync Word
Configuring second byte of the 32-bit
Sync Word
Configuring third byte of the 32-bit
Sync Word
Configuring fourth byte of the 32-bit
Sync Word
Transmitter Configuration Registers: Size – 1 Byte, Start Address – 0x1A
Register
Address
0x1A
Register
Name
Register Description
TXCONREG
Transmit Configuration Register
Related Control Functions
Transmit interpolation cut-off frequency,
power output
Oscillator Configuration Registers: Size – 1 Byte, Start Address – 0x1B
Register
Address
0x1B
Register
Name
CLKOREG
Register Description
Clock Output Control Register
Related Control Functions
Clock-out control, frequency
Packet Handling Configuration Registers: Size – 4 Bytes, Start Address – 0x1C
Register
Address
Register
Name
Register Description
0x1C
PLOADREG
Payload Configuration Register
0x1D
NADDSREG
Node Address Set Register
0x1E
PKTCREG
Packet Configuration Register
0x1F
FCRCREG
FIFO CRC Configuration Register
2010-2019 Microchip Technology Inc.
Preliminary
Related Control Functions
Enable Manchester encoding/decoding,
payload length
Node’s local address for filtering of received
packets
Packet format, size of the preamble,
whitening, CRC on/off, address filtering of
received packets, CRC status
FIFO auto-clear (if CRC failed), FIFO
access
DS70000622E-page 29
MRF89XA
2.14
General Configuration Registers
2.14.1
GENERAL CONFIGURATION REGISTER DETAILS
REGISTER 2-1:
R/W-0
GCONREG: GENERAL CONFIGURATION REGISTER
(ADDRESS:0X00) (POR:0X28)
R/W-0
R/W-1
CMOD
R/W-0
R/W-1
R/W-0
FBS
R/W-0
R/W-0
VCOT
bit 7
RPS
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-5
CMOD: Chip Mode bits
These bits select the mode of operation of the transceiver.
111 = Reserved; do not use
110 = Reserved; do not use
101 = Reserved; do not use
100 = Transmit mode
011 = Receive mode
010 = Frequency Synthesizer mode
001 = Standby mode (default)
000 = Sleep mode
bit 4-3
FBS: Frequency Band Select bits
These bits set the frequency band to be used in Sub-GHz range.
11 = Reserved
10 = 950-960 MHz or 863-870 MHz (application circuit dependent)
01 = 915-928 MHz (default)
00 = 902-915 MHz
bit 2-1
VCOT: TX bits
For each AFC cycle run, these bits toggle between logic ‘1’ and logic ‘0’.
11 = Vtune + 180 mV typ
10 = Vtune + 120 mV typ
01 = Vtune + 60 mV typ
00 = Vtune determined by tank inductors values (default)
bit 0
RPS: RPS Select bit
This bit selects between the two sets of frequency dividers of the PLL, Ri/Pi/Si. For more information,
see Section 3.2.7, Frequency Calculation.
1 = Enable R2/P2/S2 set
0 = Enable R1/P1/S1 set (default)
DS70000622E-page 30
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.14.2
DATA AND MODULATION CONFIGURATION REGISTER DETAILS
REGISTER 2-2:
R/W-1
DMODREG: DATA AND MODULATION CONFIGURATION REGISTER
(ADDRESS:0X01) (POR:0X88)
R/W-0
MODSEL
R/W-0
R/W-0
DMODE0
R/W-1
OOKTYP
R/W-0
R/W-0
DMODE1
R/W-0
IFGAIN
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-6
MODSEL: Modulation Type Selection bits
These bits set the type of modulation to be used in Sub-GHz range.
11 = Reserved
10 = FSK (default)
01 = OOK
00 = Reserved
bit 5
DMODE0: Data Mode 0 bit(1)
Setting this bit selects the data operational mode as LSB. Use this bit with DMODE1 to select the
operational mode.
0 = Default
bit 4-3
OOKTYP: OOK Demodulator Threshold Type bits
The combination of these bits selects the Demodulator Threshold Type for operation.
11 = Reserved
10 = Average Mode
01 = Peak Mode (default)
00 = Fixed threshold mode
bit 2
DMODE1: Data Mode 1 bit(1)
Setting this bit selects the data operational mode as MSB. Use this bit with DMODE0 to select the
operational mode.
0 = Default
bit 1-0
IFGAIN: IF Gain bits.
Selects gain on the IF chain.
11 = -13.5 dB
10 = -9 dB
01 = -4.5 dB
00 = 0 dB (maximal gain) (default)
Note 1: The combination of DMODE1:DMODE0 selects the Data Operation mode. See Table 2-7 for the available
Data Operation mode settings.
TABLE 2-7:
DATA OPERATION MODE SETTINGS
Data Operation Mode
DMODE1
DMODE0
Continuous (default mode)
0
0
Buffered
0
1
Packet
1
x (x = 0/1)
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 31
MRF89XA
2.14.3
FREQUENCY DEVIATION CONTROL REGISTER DETAILS
REGISTER 2-3:
R/W-0
FDEVREG: FREQUENCY DEVIATION CONTROL REGISTER
(ADDRESS:0X02) (POR:0X03)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
FDVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
FDVAL: Frequency Deviation Value bits
The bits indicate single side frequency deviation (in bit value) in FSK Transmit mode.
FDVAL = 00000011 fdev = 100 kHz (default)
f xtal
f dev = -------------------------------------------------- 32 FDVAL + 1
Where,
FDVAL is the value in the register and has the range from 0 ≤ FDVAL ≤ 255. Refer to Section 3.3.3,
fdev Setting in FSK Mode and Section 3.3.4, fdev Setting in OOK Mode for more information on
the fdev setting for FSK and OOK modes.
Note 1: fdev is used throughout the data sheet to understand the term frequency deviation and is calculated using
FDVAL from FDEVREG.
2.14.4
BIT RATE SET REGISTER DETAILS
REGISTER 2-4:
r
BRSREG: BIT RATE SET REGISTER (ADDRESS:0x03) (POR:0x07)
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-1
R/W-1
R/W-1
BRVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7
Reserved: Reserved bit; do not use
0 = Reserved (default)
bit 6-0
BRVAL: Bit Rate Value bits
These bits set the bit rate (in bit value) of:
f xtal
BitRate = ------------------------------------------- 64 BRVAL + 1
BRVAL = 0000111 Bit Rate = 25 kbps NRZ (default)
Where, BRVAL is the value in the register and has the range from 0 ≤ BRVAL ≤ 127.
Note 1:
The Bit Rates are good for crystal frequency of 12.8 MHz which is taken as a reference throughout the
data sheet.
DS70000622E-page 32
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.14.5
FLOOR THRESHOLD CONTROL REGISTER DETAILS
REGISTER 2-5:
R/W-0
FLTHREG: FLOOR THRESHOLD CONTROL REGISTER
(ADDRESS:0x04) (POR:0x0C)
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
FTOVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
FTOVAL: Floor Threshold OOK Value bits
The bits indicate Floor threshold in OOK receive mode.
FTOVAL = 00001100 6 dB (default)
FTOVAL assumes 0.5 dB RSSI Step
2.14.6
FIFO CONFIGURATION REGISTER DETAILS
REGISTER 2-6:
R/W-0
FIFOCREG: FIFO CONFIGURATION REGISTER (ADDRESS:0x05) (POR:0x0F)
R/W-0
R/W-0
R/W-0
R/W-1
FSIZE
R/W-1
R/W-1
R/W-1
FTINT
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-6
FSIZE: FIFO Size Selection bits
These bits set the size or number of FIFO locations.
11 = 64 bytes
10 = 48 bytes
01 = 32 bytes
00 = 16 bytes (default)
bit 5-0
FTINT: FIFO Threshold Interrupt bits
Setting these bits selects the FIFO threshold for interrupt source. Refer to Section 3.6.2, Interrupt
Sources and Flags for more information.
FTINT = 001111 (default)
The behavior of the FIFO_THRESHOLD interrupt source depends on the running mode (TX, RX, or
Standby mode).
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 33
MRF89XA
2.14.7
R1 COUNTER SET REGISTER DETAILS
REGISTER 2-7:
R/W-0
R1CREG: R1 COUNTER SET REGISTER (ADDRESS:0x06) (POR:0x77)
R/W-1
R/W-1
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R1CVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
R1CVAL: R1 Value bits
These bits indicate the value in R1 counter to generate carrier frequencies in FSK mode.
R1CVAL = 0x77 (default)
R1CVAL is activated if RPS = 0 in GCONREG. Also, default values R1, P1, and S1 generate 915 MHz
in FSK Mode.
2.14.8
P1 COUNTER SET REGISTER DETAILS
REGISTER 2-8:
R/W-0
P1CREG: P1 COUNTER SET REGISTER (ADDRESS:0x07) (POR:0x64)
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
P1CVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
P1CVAL: P1 Value bits
These bits indicate the value in P1 counter to generate carrier frequencies in FSK mode.
P1CVAL = 0x64 (default)
P1CVAL is activated if RPS = 0 in GCONREG. Also, default values R1, P1, and S1 generate 915 MHz
in FSK Mode.
DS70000622E-page 34
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.14.9
S1 COUNTER SET REGISTER DETAILS
REGISTER 2-9:
R/W-0
S1CREG: S1 COUNTER SET REGISTER (ADDRESS:0x08) (POR:0x32)
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
S1CVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
S1CVAL: S1 Value bits
These bits indicate the value in S1 counter to generate carrier frequencies in FSK mode.
S1CVAL = 0x32 (default)
S1CVAL is activated if RPS = 0 in GCONREG. Also, default values R1, P1, and S1 generate 915 MHz
in FSK Mode.
2.14.10
R2 COUNTER SET REGISTER DETAILS
REGISTER 2-10:
R/W-0
R2CREG: R2 COUNTER SET REGISTER (ADDRESS:0x09) (POR:0x74)
R/W-1
R/W-1
R/W-1
R/W-0
R/W-1
R/W-0
R/W-0
R2CVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
R2CVAL: R2 Value bits
These bits indicate the value in R2 counter to generate carrier frequencies in FSK mode.
R2CVAL = 0x74 (default)
R2CVAL is activated if RPS = 1 in GCONREG. Also, default values R2, P2, and S2 generate 920 MHz
in FSK Mode.
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 35
MRF89XA
2.14.11
P2 COUNTER SET REGISTER DETAILS
REGISTER 2-11:
R/W-0
P2CREG: P2 COUNTER SET REGISTER (ADDRESS:0x0A) (POR:0x62)
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
P2CVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
2.14.12
P2CVAL: P2 Value bits
These bits indicate the value in P2 counter to generate carrier frequencies in FSK mode.
P2CVAL = 0x62 (default)
P2CVAL is activated if RPS = 1 in GCONREG. Also, default values R2, P2, and S2 generate 920 MHz
in FSK Mode.
S2 COUNTER SET REGISTER DETAILS
REGISTER 2-12:
R/W-0
S2CREG: S2 COUNTER SET REGISTER (ADDRESS:0x0B) (POR:0x32)
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-1
S2CVAL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
S2CVAL: S2 Value bits
These bits indicate the value in S2 counter to generate carrier frequencies in FSK mode.
S2CVAL = 0x32 (default).
S2CVAL is activated if RPS = 1 in GCONREG. Also, default values R2, P2, and S2 generate 920 MHz
in FSK Mode.
DS70000622E-page 36
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
2.14.13
POWER AMPLIFIER CONTROL REGISTER DETAILS
REGISTER 2-13:
PACREG: POWER AMPLIFIER CONTROL REGISTER
(ADDRESS:0x0C) (POR:0x38)
r
r
r
—
—
—
R/W-1
R/W-1
PARC
r
r
r
—
—
—
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-5
Reserved: Reserved bits; not for use; needs to be a non-zero value
001 = Reserved (default)
bit 4-3
PARC: Power Amplifier Ramp Control bits
These bits control the RAMP rise and fall times of the TX PA regulator output voltage in OOK mode.
11 = 23 µs (default)
10 = 15 µs
01 = 8.5 µs
00 = 3 µs
bit 2-0
Reserved: Reserved bits; do not use
000 = Reserved (default)
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 37
MRF89XA
2.15
Interrupt Configuration Registers
2.15.1
FIFO TRANSMIT AND RECEIVE INTERRUPT REQUEST CONFIGURATION REGISTER
DETAILS
REGISTER 2-14:
R/W-0
FTXRXIREG: FIFO TRANSMIT AND RECEIVE INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0D) (POR:0x00)
R/W-0
IRQ0RXS
R/W-0
R/W-0
IRQ1RXS
R/W-0
R/W-0
R/W-0
R/W-0
IRQ1TX
FIFOFULL
FIFOEMPTY
FOVRRUN
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-6
IRQ0RXS: IRQ0 Receive Standby bits
These bits control the IRQ0 source in Receive and Standby modes:
If DMODE1:DMODE0 = 00 Continuous Mode (default)
11 = SYNC
10 = SYNC
01 = RSSI
00 = Sync (default)
If DMODE1:DMODE0 = 01 Buffered Mode
11 = SYNC
10 = FIFOEMPTY(1)
01 = WRITEBYTE
00 = - (default)
If DMODE1:DMODE0 = 1x Packet Mode
11 = SYNC or ARDSMATCH(3) (if address filtering is enabled)
10 = FIFOEMPTY(1)
01 = WRITEBYTE
00 = PLREADY(2) (default)
bit 5-4
IRQ1RXS: IRQ1 Receive Standby bits
These bits control the IRQ1 source in Receive and Standby modes:
If DMODE1:DMODE0 = 00 Continuous Mode (default)
xx = DCLK
If DMODE1:DMODE0 = 01 Buffered Mode
11 = FIFO_THRESHOLD(1)
10 = RSSI
01 = FIFOFULL(1)
00 = - (default)
If DMODE1:DMODE0 = 1x Packet Mode
11 = FIFO_THRESHOLD(1)
10 = RSSI
01 = FIFOFULL(1)
00 = CRCOK (default)
Note 1: This mode is also available in Standby mode.
2: PLREADY = Payload ready
3: ADRSMATCH = Address Match
DS70000622E-page 38
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
REGISTER 2-14:
bit 3
FTXRXIREG: FIFO TRANSMIT AND RECEIVE INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0D) (POR:0x00) (CONTINUED)
IRQ1TX: Transmit IRQ1 bit
This bit selects IRQ1 as source in Transmit mode.
If DMODE1:DMODE0 = 00 Continuous Mode (default):
x = DCLK
If DMODE1:DMODE0 = 01 Buffered Mode or 1x Packet Mode:
1 = TXDONE
0 = FIFOFULL (default)
bit 2
FIFOFULL: FIFO Full bit
This bit indicates FIFO Full through the IRQ source.
1 = FIFO full
0 = FIFO not full
bit 1
FIFOEMPTY: FIFO Empty bit
This bit indicates FIFO empty through the IRQ source.
1 = FIFO not Empty
0 = FIFO Empty
bit 0
FOVRRUN: FIFO Overrun Clear bit
This bit indicates if FIFO overrun occurred.
1 = FIFO Overrun occurred
0 = No FIFO Overrun occurred
Writing a ‘1’ for this bit clears the flag and the FIFO.
Note 1: This mode is also available in Standby mode.
2: PLREADY = Payload ready
3: ADRSMATCH = Address Match
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 39
MRF89XA
2.15.2
FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST CONFIGURATION REGISTER
DETAILS
REGISTER 2-15:
FTPRIREG: FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0E) (POR:0x01)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
FIFOFM
FIFOFSC
TXDONE
IRQ0TXST
ENRIRQS
RIRQS
LSTSPLL
LENPLL
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7
FIFOFM: FIFO Filling Method bits
This bit decides the method of filling the FIFO (supports Buffered mode only).
1 = Manually controlled by FIFO fill
0 = Automatically starts when a Sync Word is detected (default)
bit 6
FIFOFSC: FIFO Filling Status or Control bits
This bit indicates the status of FIFO filling and also controls the filling up of the FIFO
(supports Buffered mode only).
STATUS: Reading (FIFOFM = 0)
1 = FIFO getting filled ( Sync Word has been detected)
0 = FIFO filling completed/stopped
CONTROL: Writing (FIFOFM = 1), clears the bit and waits for a new Sync Word (FOVRCLR = 0)
1 = Start filling the FIFO
0 = Stop filling the FIFO
bit 5
TXDONE: Transmit Done bit
This bit selects TXDONE as the corresponding IRQ source.
1 = TXDONE (goes high when the last bit has left the shift register)
0 = TX still in process
bit 4
IRQ0TXST: Transmit Start with IRQ0 bit
This bit indicates transmit start condition with IRQ0 as source.
If DMODE1:DMODE0 = 01 Buffered Mode:
1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY
0 = Transmit starts if FIFO is full, IRQ0 mapped to FIFOEMPTY (default)
If DMODE1:DMODE0 = 1x Packet Mode:
1 = Transmit starts if FIFO is not empty, IRQ0 mapped to FIFOEMPTY
0 = Start transmission when the number of bytes in the FIFO is greater than or equal to the threshold
set by the FTINT bits (FIFOCREG 100 µs
Pin 13
(input)
DS70000622E-page 56
High-Z
1
Wait for
5 ms
Chip is ready from this point forward
High-Z
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
3.2
3.2.1
Frequency Synthesis Description
3.2.2
Use the recommended values provided in
the Bill Of Materials (BOM) in Section 4.8,
Bill of Materials for any PLL prototype
design.
BUFFERED CLOCK OUTPUT
The buffered clock output is a signal derived from fxtal.
It can be used as a reference clock (or a sub-multiple
of it) for the host microcontroller and is an output on the
CLKOUT pin (pin 19). The pin is activated using the
CLKOCNTRL bit (CLKOUTREG). The output
frequency (CLKOUT) division ratio is programmed
through the Clock Out Frequency bits (CLKOFREQ5CLK0FREQ1) in the Clock Output Control Register
(CLKOUTREG). The two uses of the CLKOUT
output are:
• To provide a clock output for a host microcontroller,
thus saving the cost of an additional oscillator.
CLKOUT can be made available in any operation
mode, except Sleep mode, and is automatically
enabled at power-up.
• To provide an oscillator reference output.
Measurement of the CLKOUT signal enables
simple software trimming of the initial crystal
tolerance.
Note:
3.2.3
CLKOUT is disabled when the MRF89XA
is in Sleep mode. If Sleep mode is used,
the host microcontroller must have provisions to run from its own clock source.
• The comparison frequency, FCOMP, of the Phase
Frequency Detector (PFD) input must remain
higher than six times the PLL bandwidth (PLLBW)
to guarantee loop stability and to reject harmonics
of the comparison frequency FCOMP. This is
expressed in the inequality:
FCOMP ≥ 6 * PLLBW
• However, the PLLBW must be sufficiently high to
allow adequate PLL lock times.
• Because the divider ratio R determines FCOMP, it
should be set close to 119, leading to
FCOMP ≈ 100 kHz, which will ensure suitable PLL
stability and speed.
The following criteria govern the R, P, and S values for
the PLL block:
•
•
•
•
64 ≤ R ≤ 169
P+1 > S
PLLBW = 15 kHz nominal
Start-up times and reference frequency drives as
specified
3.2.4.2
Note:
3.2.5
The LSTSPLL bit latches high each time
the PLL locks and must be reset by writing
a ‘1’ to LSTSPLL from FTPRIREG.
PLL REGISTERS
The registers associated with the PLL are:
• GCONREG (Register 2-1)
• CLKOUTREG (Register 2-28)
• GCONREG (Register 2-1)
• FTPRIREG (Register 2-15)
PHASE-LOCKED LOOP (PLL)
The frequency synthesizer of the MRF89XA is a fully
integrated integer-N type PLL. The PLL circuit requires
only five external components for the PLL loop filter
and the VCO tank circuit.
2010-2019 Microchip Technology Inc.
PLL Lock Detection Indicator
The MRF89XA features a PLL lock detect indicator.
This is useful for optimizing power consumption, by
adjusting the frequency synthesizer wake-up time
(TSFS). For more information on TSFS, refer to
Table 5-4. The lock status is available by reading the
Lock Status of PLL bit (LSTSPLL) in the FIFO
Transmit PLL and RSSI Interrupt Request
Configuration register (FTPRIREG), and must be
cleared by writing a ‘1’ to this same register. The
lock status can also be seen on the PLOCK pin (pin
23) of the device by setting the LENPLL bit
(FTPRIREG).
CLOCK REGISTERS
The registers associated with the Clock and its control
are:
3.2.4
PLL Requirements
With integer-N PLL architecture, the following
conditions must be met to ensure correct operation:
REFERENCE OSCILLATOR
The crystal oscillator (XTAL) forms the reference
oscillator of an Integer-N PLL. The crystal reference
frequency and the software controlled dividers R, P,
and S determine the output frequency of the PLL. The
guidelines for selecting the appropriate crystal with
specifications are explained in Section 4.7, Crystal
Specification and Selection Guidelines.
Note:
3.2.4.1
3.2.6
SW SETTINGS OF THE VCO
To guarantee the optimum operation of the VCO over
the MRF89XA’s frequency and temperature ranges,
the settings listed in Table 3-1 should be programmed
into the MRF89XA.
Preliminary
DS70000622E-page 57
MRF89XA
TABLE 3-1:
FREQUENCY BAND SETTING
Target Channel
(MHz)
FBS1
FBS0
863-870
1
0
902-915
0
0
915-928
0
1
950-960
1
0
Trimming the VCO
Hardware and Software
Tank
3.2.6.1
3.2.8
The formula provided in Equation 3-1 gives the
relationship between the local oscillator and R, P, and
S values when using FSK modulation.
EQUATION 3-1:
9
f rf fsk = --- f lo
8
by
To ensure that the frequency band of operation is
accurately addressed by the R, P, and S dividers of the
synthesizer, it is necessary to ensure that the VCO is
correctly centered. The MRF89XA built-in VCO
trimming feature makes it easy and is controlled by the
SPI interface. This tuning does not require any RF test
equipment, and can be achieved by measuring Vtune,
which is the voltage between the PLLN and PLLP pins
(6 and 7 pins).
The VCO is centered if the voltage is within the range
of 50 Vtune(mV) 150.
This measurement should be conducted when in
Transmit mode at the center frequency (fo) of the
desired band (for example, approximately 867 MHz in
the 863-870 MHz band), with the appropriate frequency
band
setting
using
the
(FBS
bits
(GCONREG).
If this inequality is not satisfied, adjust the VCOT
bits (GCONREG) from ‘00’ by monitoring Vtune.
This allows the VCO voltage to be trimmed in +60 mV
increments. If the desired voltage range is
inaccessible, the voltage may be adjusted further by
changing the tank circuit inductance value.
An increase in inductance results in an increased
Vtune. In addition, for mass production, the VCO
capacitance is piece-to-piece dependent. As such, the
optimization proposed above should be verified on
several prototypes, to ensure that the population is
centered with 100 mV.
9 f xtaL
frf fsk = --- ------------- 75 P + 1 + S
8 R+1
3.2.9
• GCONREG (Register 2-1)
• DMODREG (Register 2-2)
3.2.10
DS70000622E-page 58
OOK MODE
Due to the manner in which the baseband OOK
symbols are generated, the signal is always offset by
the FSK frequency deviation (FDVAL as
programmed in FDEVREG). Therefore, the
center of the transmitted OOK signal is represented by
Equation 3-2.
EQUATION 3-2:
f rf ook tx
9
f rf ook tx = --- f lo – f dev
8
f
9
xtaL
= --- ------------- 75 P + 1 + S – f dev
8 R+1
Consequently, in Receive mode, due to the low
intermediate frequency (Low-IF) architecture of the
MRF89XA, the frequency should be configured so as to
ensure the correct low-IF receiver baseband center
frequency, IF2, as shown in Equation 3-3.
EQUATION 3-3:
9
f rf ook rx = --- flo – IF2
8
9 f xtaL
f rf ook rx = --- ------------- 75 P + 1 + S – IF2
8 R+1
FREQUENCY CALCULATION
As illustrated in Figure 2-5, the PLL structure comprises three different dividers, R, P, and S, which set
the output frequency through the LO. A second set of
dividers is also available to allow rapid switching
between a pair of frequencies: R1/P1/S1 and R2/P2/
S2. These six dividers are programmed by six independent registers (see Register 2-7 through Register 212), which are selected by GCONREG.
FSK MODE REGISTERS
The registers associated with FSK mode are:
The register associated with VCO is GCONREG
(Register 2-1).
3.2.7
FSK MODE
As described in Section 3.4.4, Channel Filters, it is
recommended that IF2 be set to 100 kHz.
3.2.11
OOK MODE REGISTERS
The registers associated with OOK mode are:
•
•
•
•
GCONREG (Register 2-1)
DMODREG (Register 2-2)
FLTHREG (Register 2-5)
OOKCREG (Register 2-22)
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
3.3
Transmitter
3.3.4
The MRF89XA is set to Transmit mode when the
CMOD bits (GCONREG) are set to ‘100’
(see Register 2-1).
The transmitter chain in the MRF89XA is based on the
same double-conversion architecture and uses the
same intermediate frequencies as the receiver chain.
3.3.1
BIT RATE SETTING
In Continuous Transmit mode, setting the bit rate
through the BRVAL bits (BRSREG) is
useful to determine the frequency of DCLK. As
explained in Section 3.9.1, TX Processing, DCLK
triggers an interrupt on the host microcontroller each
time a new bit has to be transmitted, as shown in
Equation 3-4.
fdev has no physical meaning in OOK Transmit mode.
However, due to the DDS baseband signal generation,
the OOK signal is always offset by “-fdev” (see
Section 3.2.7, Frequency Calculation). It is
suggested that fdev retains its default value of 100 kHz
in OOK mode.
3.3.5
EQUATION 3-7:
BR
BW 3 f dev + ------2
f xtal
BR = ---------------------------------------------------------------------64 1 + val BRVAL
Where,
fdev is the programmed frequency deviation
as set in FDEVREG.
BR is the physical bit rate of transmission.
ALTERNATIVE SETTINGS
Bit rate, frequency deviation, and TX interpolation filter
settings are a function of the crystal frequency (fxtal) of
the reference oscillator. Settings other than those
programmed with a 12.8 MHz crystal can be obtained
by selecting the correct reference oscillator frequency.
3.3.3
INTERPOLATION FILTER
After the digital-to-analog conversion, the I and Q signals are smoothened by interpolation filters. Low-pass
filters in this block digitally generate the signal and prevent the alias signals from entering the modulators. Its
bandwidth
can
be
programmed
with
the
(TXIPOLFV bits (TXCONREG>7:4), and should
be calculated as shown in Equation 3-7.
EQUATION 3-4:
3.3.2
fdev SETTING IN OOK MODE
fdev SETTING IN FSK MODE
The frequency deviation, fdev, of the FSK transmitter is
programmed
through
the
FDVAL
bits
(FDEVREG), as shown in Equation 3-5.
Note:
Low interpolation filter bandwidth attenuates the baseband I/Q signals, thus reducing the power of the FSK signal.
Conversely,
excessive
bandwidth
degrades spectral purity.
For most of the applications, a BW of around 125 KHz
would be acceptable, but for wideband FSK
modulation, the recommended filter setting cannot be
reached. However, the impact on spectral purity is
negligible due to the existing wideband channel.
EQUATION 3-5:
f xtal
fdev = -----------------------------------------------------------------------
32 1 + val FDVAL
For correct operation, the modulation index should
be equal to Equation 3-6.
EQUATION 3-6:
2 f dev
= --------------- 2
BR
For communication between a pair of MRF89XAs, the
fdev should be at least 33 kHz to ensure a correct
operation on the receiver side.
2010-2019 Microchip Technology Inc.
Preliminary
DS70000622E-page 59
MRF89XA
3.3.6
3.3.7
POWER AMPLIFIER
3.3.6.1
The registers associated with the Transmit mode are:
Rise and Fall Time Control
In OOK mode, the PA ramp times can be accurately
controlled
through
the
PARC
bits
(PACONREG). These bits directly control the slew
rate of the PARS pin.
TABLE 3-2:
TRANSMIT MODE REGISTERS
POWER AMPLIFIER RISE/
FALL TIMES
PARC
tPARS
tPAOUT
(rise/fall)
00
01
10
11
3 µs
8.5 µs
15 µs
23 µs
2.5/2 µs
5/3 µs
10/6 µs
20/10 µs
•
•
•
•
•
•
•
•
•
•
•
•
•
GCONREG (Register 2-1)
DMODREG (Register 2-2)
FDEVREG (Register 2-3)
BRSREG (Register 2-4)
R1CREG (Register 2-7)
P1CREG (Register 2-8)
S1CREG (Register 2-9)
R2CREG (Register 2-10)
P2CREG (Register 2-11)
S2CREG (Register 2-12)
PACREG (Register 2-13)
FTXRXIREG (Register 2-14)
FTPRIREG (Register 2-15)
During the Transmit mode of the MRF89XA, the Shift
register takes bytes from the FIFO and outputs them
serially (MSb first) at the programmed bit rate to the
modulator. When the transmitter is enabled, it starts
sending out data from the Shift register with respect to
the set bit rate. After power-up and with the Transmit
registers enabled, the transmitter preloads the FIFO
with preambles before sending the actual data based
on the mode of operation. Figure 3-4 illustrates the PA
Control Timing.
FIGURE 3-4:
PA TIMING CONTROL
DATA
PARS
[V]
95%
95%
tPARS
PA Output
Power
60 dB
60 dB
tPA_OUT
DS70000622E-page 60
tPARS
tPA_OUT
Preliminary
2010-2019 Microchip Technology Inc.
MRF89XA
3.4
Receiver
3.4.1
The MRF89XA is set to Receive mode when the
CMOD bits (GCONREG) are set to ‘011’
(see Register 2-1).
MRF89XA SECOND IF FILTER
DETAILS
FIGURE 3-5:
The receiver is based on the superheterodyne
architecture. (In a superheterodyne architecture, you
need to use a saw filter to give better image rejection).
The front-end is composed of an LNA and a mixer
whose gains are constant. The mixer down-converts
the RF signal to an intermediate frequency, which is
equal to one-eighth of the LO frequency, which in turn
is equal to eight-ninths of the RF frequency. Behind this
first mixer is a variable gain IF amplifier that can be
programmed from a maximum gain of 13.5-0 dB in
steps of 4.5 dB by altering the IFGAIN bits
(DMODREG).
IF FILTERS IN FSK AND
OOK MODES
FCBW
Butterworth Low-Pass Filter for FSK
After the variable gain IF amplifier, the signal is downconverted into two I and Q baseband signals by two
quadrature mixers that are fed by reference signals at
one-eighth the LO frequency. These I and Q signals are
then filtered and amplified before demodulation.
The first filter is a second-order passive R-C filter
whose bandwidth can be programmed to 16 values
with the PASFILV bits (FILCREG). The
second filter can be configured as either a third-order
Butterworth active filter, which acts as a low-pass filter
for the zero-IF FSK configuration, or as a polyphase
band-pass filter for the low-IF OOK configuration. To
select the Butterworth low-pass filter operation, the
POLFILEN bit (SYNCREG) is set to ‘0’. The
bandwidth of the Butterworth filter can be programmed
to 16 values by configuring the BUTFILV bits
(FILCREG). The low-IF configuration must be
used for OOK modulation. This configuration is
enabled when the POLFILEN bit (SYNCREG) is
set to ‘1’. The center frequency (fo) of the polyphase
filter can be programmed to 16 values by setting the
POLCFV bits (PFCREG). The bandwidth of
the filter can be programmed by configuring the
BUTFILV bits (FILCREG). In OOK mode,
the value of the low-IF is equal to the deviation
frequency defined in FDEVREG.
In addition to the channel filtering, the function of the
polyphase filter is to reject the image. Figure 3-5
illustrates the two configurations of the second IF filter.
In the Butterworth configuration, FCBW is the 3 dB cutoff frequency. In the polyphase band-pass
configuration, FOPP is the center frequency given by
the POLCFV bits (PFCREG), and FCPP is
the upper 3 dB bandwidth of the filter whose offset,
referenced to FOPP, is given by BUTFILV bits
(FILCREG).
2010-2019 Microchip Technology Inc.
2 * FOPP – FCPP FOPP
FCPP
Polyphase Band-Pass Filter for OOK
After filtering, the I and Q signals are each amplified by
a chain of 11 amplifiers having 6 dB of gain each. The
outputs of these amplifiers and their intermediate 3 dB
nodes are used to evaluate the received signal strength
(RSSI). Limiters are located behind the 11 amplifiers of
the I and Q chains, and the signals at the output of
these limiters are used by the FSK demodulator. The
OOK demodulator uses the RSSI output. The global
bandwidth of the entire baseband chain is given by the
bandwidths of the passive filter, the Butterworth filter,
the amplifier chain, and the limiter. The maximum,
achievable global bandwidth when the bandwidths of
the first three blocks are programmed at their upper
limit is approximately 350 kHz.
3.4.2
LNA AND FIRST MIXER
In Receive mode, the RFIO pin is connected to a fixed
gain, common-gate, Low Noise Amplifier (LNA). The
performance of this amplifier is such that the Noise
Figure (NF) of the receiver is estimated to be
approximately 7 dB.
3.4.3
IF GAIN AND SECOND I/Q MIXER
Following the LNA and first down-conversion, there is
an IF amplifier whose gain can be programmed from 13.5-0 dB in 4.5 dB steps, through the IFGAIN
bits
(DMODREG). The
default
setting
corresponds to 0 dB gain, but lower values can be used
to increase the RSSI dynamic range. For more
information, refer Section 3.4.7, received signal
strength (RSSI).
Preliminary
DS70000622E-page 61
MRF89XA
3.4.4
CHANNEL FILTERS
EQUATION 3-8:
The second mixer stages are followed by the channel
select filters. The channel select filters have a strong
influence on the noise bandwidth and selectivity of the
receiver and hence its sensitivity. Each filter comprises
a passive and an active section.
3.4.4.1
Passive Filter
Each channel select filter features a passive secondorder RC filter, with a bandwidth programmable
through the PASFILV bits (FILCREG
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