MT093APR1

MT093 8 x 12 Analog Switch Array ISO-CMOS Data Sheet Features September 2011 • Internal control latches and address decoder • Short set-up and hold times • Wide operating voltage: 4.5 V to 14.5 V • 3.5Vpp analog signal capability • RON 65 max. @ VDD=14V, 25C • RON 10  @ VDD=14V, 25C • Full CMOS switch for low distortion • Minimum feedthrough and crosstalk • Low power consumption ISO-CMOS technology Ordering Information MT093AE1 MT093AP1 MT093APR1 PBX systems • Mobile radio • Test equipment /instrumentation • Analog/digital multiplexers • Audio/Video switching 0C to +70C Description The Zarlink MT093 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. STROBE DATA RESET VDD 1 AX0 VSS 1 8 x 12 Switch Array AX2 7 to 96 Decoder Latches AY0 AY1 AY2 96 96 ••••••••••••••••••• Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved. •••••••••••••••• AX1 AX3 Tubes Tubes Tubes *Pb Free Matte Tin Applications • 40 Pin PDIP* 44 Pin PLCC* 44 Pin PLCC* Xi I/O (i=0-11) MT093 VDD Y2 DATA Y1 NC Y0 NC X0 X1 X2 X3 X4 X5 NC NC AY1 AY0 AX2 AX1 Y4 NC NC X6 XY X8 X9 X10 X11 NC NC NC AX3 RESET AY2 Y3 VDD Y2 DATA Y1 Y0 NC AX0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 NC NC X0 X1 X2 X3 X4 X5 NC NC NC Y7 Y6 STROBE Y5 VSS Y4 AX1 AX2 AY0 AY1 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Y3 AY2 RESET AX3 AX0 NC NC X6 X7 X8 X9 X10 X11 NC Y7 NC Y6 STROBE Y5 VSS Data Sheet 40 PIN PLASTIC DIP 44 PIN PLCC Figure 2 - Pin Connections Change Summary Changes from the August 2005 issue to the September 2011 issue. Page Item 1 Ordering Information Change Removed leaded packages as per PCN notice. Pin Description Pin # Name PDIP PLCC 1 1 2 3 4,5 6,7 8-13 2 3 4,5 6-8 9-14 14 15 15-17 18 16 17 19 Description Y3 Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. AY2 Y2 Address Line (Input). RESET Master RESET (Input): this is used to turn off all switches. Active High. AX3,AX0 X3 and X0 Address Lines (Inputs). NC No Connection. X6-X11 X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. NC No Connection. Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. NC No Connection. Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 2 Zarlink Semiconductor Inc. MT093 Data Sheet Pin Description Pin # Name PDIP PLCC 18 20 19 21 20 21 22 23 22, 23 24, 25 26, 27 28 - 33 24,25 26,27 28-31 32-37 34 35 36 37 38 38,39 40 41 42 39 40 43 44 Description STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. Ground Reference. VSS Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. AX1,AX2 X1 and X2 Address Lines (Inputs). AY0,AY1 Y0 and Y1 Address Lines (Inputs). NC No Connection. X5-X0 X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. NC No Connection. Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. NC No Connection. Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. VDD Positive Power Supply. Functional Description The MT093 is an analog switch matrix with an array size of 8 x 12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address input lines (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input line. Data is asynchronously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input line will asynchronously return all memory locations to logical “0” turning off all crosspoint switches. Address Decode The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 3 Zarlink Semiconductor Inc. MT093 Data Sheet Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated. Parameter Symbol Min. Max. Units 1 Supply Voltage VDD VSS -0.3 -0.3 16.0 VDD+0.3 V V 2 Analog Input Voltage VINA -0.3 VDD+0.3 V 3 Digital Input Voltage VIN VSS-0.3 VDD+0.3 V 4 Current on any I/O Pin 15 mA 5 Storage Temperature +150 C 0.6 W I -65 TS 6 Package Power Dissipation PLASTIC DIP PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units TO 0 25 70 C 1 Operating Temperature 2 Supply Voltage VDD 4.5 14.5 V 3 Analog Input Voltage VINA VSS 3.5 V 4 Digital Input Voltage VIN VSS VDD V Test Conditions DC Electrical Characteristics†- Voltages are with respect to VSS=0V, VDD =14V unless otherwise stated. Characteristics 1 Quiescent Supply Current Sym. Min. Typ.‡ Max. Units Test Conditions 1 100 A All digital inputs at VIN=VSS or VDD 7 15 mA All digital inputs at VIN=2.4V IVXi - VYjI = VDD - VSS IDDQ 2 Off-state Leakage Current IOFF 1 A 3 Input Logic “0” level VIL 0.8 V 4 Input Logic “1” level VIH 5 Input Leakage (digital pins) 2.4 V ILEAK 10 A All digital inputs at VIN = VSS or VDD † DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 4 Zarlink Semiconductor Inc. MT093 Data Sheet DC Electrical Characteristics- Switch Resistance - VIDC/VODC is the external DC offset applied at the analog I/O pins. Characteristics Sym. 25C 60C 70C Units Test Conditions Typ. Max. Typ. Max. Typ. Max. 1 On-state VDD=14V Resistance RON 45 65 2 Difference in on-state resistance between two switches RON 5 10 10 75  VSS=0V, IVXi-VYjI = 0.25V VIDC=6.75V VODC=6.5V 10  VDD=14V, VSS=0, VIDC=6.75V VODC=6.5V IVXi-VYjI = 0.25V AC Electrical Characteristics† - Crosspoint Performance-VDC is the external DC offset applied at the analog I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated. Characteristics Sym. Typ.‡ Min. Max. Units Test Conditions 1 Switch I/O Capacitance CS 20 pF f=1 MHz 2 Feedthrough Capacitance CF 0.2 pF f=1 MHz 3 Frequency Response Channel “ON” 20LOG(VOUT/VXi)=-3dB F3dB 45 MHz Switch is “ON”; VINA = 2Vpp sinewave; RL = 1k 4 Total Harmonic Distortion THD 0.05 % Switch is “ON”; VINA = 2Vpp sinewave f= 1kHz; RL=1k 5 Feedthrough Channel “OFF” Feed.=20LOG (VOUT/VXi) FDT -95 dB All Switches “OFF”; VINA= 2Vpp sinewave f= 1kHz; RL= 1k. 6 Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk -45 dB VINA=2Vpp sinewave f= 10MHz; RL = 75. -90 dB VINA=2Vpp sinewave f= 10kHz; RL = 600. -85 dB VINA=2Vpp sinewave f= 10kHz; RL = 1k. -80 dB VINA=2Vpp sinewave f= 1kHz; RL = 10k. ns RL=1k; CL=50pF Xtalk=20LOG (VYj/VXi). 7 Propagation delay through switch 50 tPS † Timing is over recommended temperature range. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better. 5 Zarlink Semiconductor Inc. MT093 Data Sheet AC Electrical Characteristics† - Control and I/O Timings- VDC is the external DC offset applied at the analog I/O pins. Voltages are with respect to VDD=7V, VDC=0V, VSS=-7V, unless otherwise stated. Characteristics Sym. Min. Typ.‡ Max. Units Test Conditions CXtalk 50 mVpp Digital Input Capacitance CDI 10 pF 3 Switching Frequency FO 4 Setup Time DATA to STROBE tDS 20 ns RL= 1k, CL=50pF 5 Hold Time DATA to STROBE tDH 20 ns RL= 1k, CL=50pF 1 Control Input crosstalk to switch (for DATA, STROBE, Address) 2 10 VIN=3V+VDC squarewave; RIN=1k, RL=10k. f=1MHz MHz 6 Setup Time Address to STROBE tAS 20 ns RL= 1k, CL=50pF 7 Hold Time Address to STROBE tAH 20 ns RL= 1k, CL=50pF 8 STROBE Pulse Width tSPW 40 ns RL= 1k, CL=50pF 9 RESET Pulse Width tRPW 80 ns RL= 1k, CL=50pF 10 STROBE to Switch Status Delay tS 80 200 ns RL= 1k, CL=50pF 11 DATA to Switch Status Delay tD 100 200 ns RL= 1k, CL=50pF 70 200 ns RL = 12 RESET to Switch Status Delay tR † Timing is over recommended temperature range. Digital Input rise time (tr) and fall time (tf) = 10 ns. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 1k, CL=50pF tRPW 50% RESET 50% tSPW 50% STROBE 50% 50% tAS 50% ADDRESS 50% tAH 50% DATA 50% tDS tDH ON SWITCH* OFF tS tD Figure 3 - Control Memory Timing Diagram 6 Zarlink Semiconductor Inc. tR tR MT093 Data Sheet AX0 AX1 AX2 AX3 AY0 AY1 AY2 Connection 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 No Connection No Connection X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 No Connection No Connection 0  0  0  0  1  0  0  X0-Y1 1 0 1 1 1 0 0 X11-Y1 0  0  0  0  0  1  0  X0-Y2 1 0 1 1 0 1 0 X11-Y2 0  0  0  0  1  1  0  X0-Y3 1 0 1 1 1 1 0 X11-Y3 0  0  0  0  0  0  1  X0-Y4 1 0 1 1 0 0 1 X11-Y4 0  0  0  0  1  0  1  X0-Y5 1 0 1 1 1 0 1 X11-Y5 0  0  0  0  0  1  1  X0-Y6 1 0 1 1 0 1 1 X11-Y6 0  0  0  0  1  1  1  X0-Y7 1 0 1 1 1 1 1 X11-Y7 Table 1 - Address Decode Truth Table This address has no effect on device status. 7 Zarlink Semiconductor Inc.        For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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