MT8815AE1

MT8815 8 x 12 Analog Switch Array Data Sheet Features September 2011 • Internal control latches and address decoder • Short set-up and hold times • Wide operating voltage: 4.5V to 13.2V • 12Vpp analog signal capability • R ON 65 max. @ V DD=12V, 25×C • R ON  10 @ V DD=12V, 25C • Full CMOS switch for low distortion • Minimum feedthrough and crosstalk • Separate analog and digital reference supplies • Low power consumption ISO-CMOS technology Ordering Information MT8815AP1 44 Pin PLCC* Tubes MT8815APR1 44 Pin PLCC* Tape & Reel MT8815AE1 40 Pin PDIP* Tubes *Pb Free Matte Tin -40C to +85C Description The Zarlink MT8815 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Applications • Key systems • PBX systems • Mobile radio • Test equipment /instrumentation • Analog/digital multiplexers • Audio/Video switching STROBE DATA RESET VDD 1 VEE VSS 1 AX0 AX2 AX3 7 to 96 Decoder 8 x 12 Switch Array Latches AY0 AY1 AY2 96 96 ••••••••••••••••••• Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved. •••••••••••••••• AX1 Xi I/O (i=0-11) MT8815 Data Sheet Change Summary Changes from the December 2008 issue to the September 2011 issue. Page Item 1 Change Ordering Information Removed leaded packages as per PCN notice. Changes from August 2005 to December 2008 issue. Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Y3 AY2 RESET AX3 AX0 NC NC X6 X7 X8 X9 X10 X11 NC Y7 VSS Y6 STROBE Y5 VEE 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 MT8815AE removed - obsolete. Added pb free part numbers. NC Y2 DATA Y1 VDD Y0 NC X0 X1 X2 X3 X4 X5 NC NC AY1 AY0 AX2 AX1 Y4 NC NC X6 X7 X8 X9 X10 X11 NC NC Y7 AX3 RESET AY2 Y3 NC Y2 DATA Y1 VDD Ordering Information NC AX0 1 Change 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 Y0 NC X0 X1 X2 X3 X4 X5 NC NC NC VSS Y6 STROBE Y5 VEE Y4 AX1 AX2 AY0 AY1 NC Page 40 PIN PLASTIC DIP 44 PIN PLCC Figure 2 - Pin Connections Pin Description Pin # Name PDIP PLCC 1 1 Y3 2 2 AY2 3 3 RESET 4,5 4,5 6,7 6-8 NC 8-13 9-14 X6-X11 Description Y3 Analog (Input/Output): this is connected to the Y3 column of the switch array. Y2 Address Line (Input). Master RESET (Input): this is used to turn off all switches. Active High. AX3,AX0 X3 and X0 Address Lines (Inputs): these are used to select X3 and X0 rows of switches. No Connection. X6-X11 Analog (Inputs/Outputs): these are connected to the X6-X11 rows of the switch array. 2 Zarlink Semiconductor Inc. MT8815 Data Sheet Pin Description Pin # Name Description PDIP PLCC 14 15,16 NC No Connection 15 17 Y7 Y7 Analog (Input/Output): this is connected to the Y7 column of the switch array. 16 18 VSS Digital Ground Reference (Input). 17 19 Y6 Y6 Analog (Input/Output): this is connected to the Y6 column of the switch array. 18 20 19 21 Y5 Y5 Analog (Input/Output): this is connected to the Y5 column of the switch array. 20 22 VEE Negative Power Supply. 21 23 Y4 Y4 Analog (Input/Output): this is connected to the Y4 column of the switch array. 22, 23 24,25 AX1,AX2 X1 and X2 Address Lines (Inputs). 24, 25 26,27 AY0,AY1 Y0 and Y1 Address Lines (Inputs). 26, 27 28-31 NC 28 - 33 32-37 X5-X0 34 38 NC No Connection. 35 39 Y0 Y0 Analog (Input/Output): this is connected to the Y0 column of the switch array. 36 40 VDD 37 41 Y1 Y1 Analog (Input/Output): this is connected to the Y1 column of the switch array. 38 42 DATA DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. 39 43 Y2 Y2 Analog (Input/Output): this is connected to the Y2 column of the switch array. 40 44 NC No Connection. STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. No Connection. X5-X0 Analog (Inputs/Outputs): these are connected to the X5-X0 rows of the switch array. Positive Power Supply. 3 Zarlink Semiconductor Inc. MT8815 Data Sheet Functional Description The MT8815 is an analog switch matrix with an array size of 8×12. The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0-AX3). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off all crosspoint switches. Two voltage reference pins (VSS and VEE) are provided for the MT8815 to enable switching of negative analog signals. The range for digital signals is from VDD to VSS while the range for analog signals is from VDD to VEE. VSS and VEE pins can be tied together if a single voltage reference is needed. Address Decode The seven address inputs along with the STROBE are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 4 Zarlink Semiconductor Inc. MT8815 Data Sheet Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated. Parameter Symbol Min. Max. Units 1 Supply Voltage VDD VSS -0.3 -0.3 15.0 VDD+0.3 V V 2 Analog Input Voltage VINA -0.3 VDD+0.3 V 3 Digital Input Voltage VIN VSS-0.3 VDD+0.3 V 4 Current on any I/O Pin ±15 mA 5 Storage Temperature +150 C 0.6 W I -65 TS 6 Package Power Dissipation PLASTIC DIP PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics Sym. Min. Typ. Max. Units TO -40 25 85 C 1 Operating Temperature 2 Supply Voltage VDD VSS 4.5 VEE 13.2 VDD-4.5 V V 3 Analog Input Voltage VINA VEE VDD V 4 Digital Input Voltage VIN VSS VDD V Test Conditions DC Electrical Characteristics†- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated. Characteristics 1 Quiescent Supply Current Sym. Min. Typ.‡ Max. Units Test Conditions 1 100 A All digital inputs at VIN=VSS or VDD 0.4 1.5 mA All digital inputs at VIN=2.4V + VSS; VSS=7.0V 5 15 mA All digital inputs at VIN=3.4V 1 500 nA IVXi - VYjI = VDD - VEE See Appendix, Fig. A.1 0.8+VSS V VSS=7.5V; VEE=0V VSS=6.5V; VEE=0V IDD 2 Off-state Leakage Current (See G.9 in Appendix) IOFF 3 Input Logic “0” level VIL 4 Input Logic “1” level VIH 2.0+VSS V 5 Input Logic “1” level VIH 3.3 V 6 Input Leakage (digital pins) ILEAK 0.1 10 A All digital inputs at VIN = VSS or VDD † DC Electrical Characteristics are over recommended temperature range. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 5 Zarlink Semiconductor Inc. MT8815 Data Sheet DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins. Characteristics Sym 25C 70C 85C Units Test Conditions Typ. Max. Typ. Max. Typ. Max. 1 On-state VDD=12V Resistance VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) RON 45 55 120 65 75 185 75 85 215 80 90 225    VSS=VEE=0V,VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 2 Difference in on-state resistance between two switches (See G.4 in Appendix) RON 5 10 10 10  VDD=12V, VSS=VEE=0, VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless otherwise stated. Characteristics Sym. Typ.‡ Min. Max. Units Test Conditions 1 Switch I/O Capacitance CS 20 pF f=1 MHz 2 Feedthrough Capacitance CF 0.2 pF f=1 MHz 3 Frequency Response Channel “ON” 20LOG(VOUT/VXi)=-3dB F3dB 45 MHz Switch is “ON”; VINA = 2Vpp sinewave; RL = 1k See Appendix, Fig. A.3 4 Total Harmonic Distortion (See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; VINA = 2Vpp sinewave f= 1kHz; RL=1k 5 Feedthrough Channel “OFF” Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) FDT -95 dB All Switches “OFF”; VINA= 2Vpp sinewave f= 1kHz; RL= 1k. See Appendix, Fig. A.4 6 Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk -45 dB VINA=2Vpp sinewave f= 10MHz; RL = 75. -90 dB VINA=2Vpp sinewave f= 10kHz; RL = 600. -85 dB VINA=2Vpp sinewave f= 10kHz; RL = 1k. -80 dB VINA=2Vpp sinewave f= 1kHz; RL = 10k. Refer to Appendix, Fig. A.5 for test circuit. ns RL=1k; CL=50pF Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix). 7 Propagation delay through switch tPS 30 † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better. 6 Zarlink Semiconductor Inc. MT8815 Data Sheet AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless otherwise stated. Characteristics Sym. Min. Typ.‡ Max. Units Test Conditions VIN=3V squarewave; RIN=1k, RL=10k. See Appendix, Fig. A.6 CXtalk 30 mVpp Digital Input Capacitance CDI 10 pF 3 Switching Frequency FO 4 Setup Time DATA to STROBE tDS 10 ns RL= 1k, CL=50pF 5 Hold Time DATA to STROBE tDH 10 ns RL= 1k, CL=50pF 1 6 Setup Time Address to STROBE tAS 10 ns RL= 1k, CL=50pF 1 7 Hold Time Address to STROBE tAH 10 ns RL= 1k, CL=50pF 1 8 STROBE Pulse Width tSPW 20 ns RL= 1k, CL=50pF 1 9 RESET Pulse Width tRPW 40 ns RL= 1k, CL=50pF 1 10 STROBE to Switch Status Delay tS 40 100 ns RL= 1k, CL=50pF 1 11 DATA to Switch Status Delay tD 50 100 ns RL= 1k, CL=50pF 1 12 RESET to Switch Status Delay tR 35 100 ns RL= 1k, CL=50pF 1 1 Control Input crosstalk to switch (for DATA, STROBE, Address) 2 20 f=1MHz MHz † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. ‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 1 Refer to Appendix, Fig. A.7 for test circuit. tRPW 50% RESET 50% tSPW 50% STROBE 50% 50% tAS 50% ADDRESS 50% tAH 50% DATA 50% tDS tDH ON SWITCH* OFF tS tD Figure 3 - Control Memory Timing Diagram * See Appendix, Fig. A.7 for switching waveform 7 Zarlink Semiconductor Inc. tR tR  MT8815 Data Sheet AX0 AX1 AX2 AX3 AY0 AY1 AY2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Connection 0  0  0  0  1  0  0  X0-Y1  X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 No Connection No Connection X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 No Connection No Connection 1 0 1 1 1 0 0 X11-Y1 0  0  0  0  0  1  0  X0-Y2  1 0 1 1 0 1 0 X11-Y2 0  0  0  0  1  1  0  X0-Y3  1 0 1 1 1 1 0 X11-Y3 0  0  0  0  0  0  1  X0-Y4  1 0 1 1 0 0 1 X11-Y4 0  0  0  0  1  0  1  X0-Y5  1 0 1 1 1 0 1 X11-Y5 0  0  0  0  0  1  1  X0-Y6  1 0 1 1 0 1 1 X11-Y6 0  0  0  0  1  1  1  X0-Y7  1 0 1 1 1 1 1 X11-Y7 Table 1 - Address Decode Truth Table This address has no effect on device status. 8 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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