MT90866
Flexible 4 K x 2.4 K Channel Digital Switch with
H.110 Interface and 2.4 K x 2.4 K Local Switch
Data Sheet
Features
January 2006
•
2,432 x 2,432 non-blocking switching among local
streams
•
4,096 x 2,432 blocking switching between
backplane and local streams
•
2,048 x 2,048 non-blocking switching among
backplane streams
•
Rate conversion between backplane and local
streams
•
Connection memory block-programming for fast
device initialization
•
Rate conversion among local streams
•
Tristate-control outputs for external drivers
•
Backplane interface accepts data rates of
8.192 Mb/s or 16.384 Mb/s
•
•
Local interface accepts data rates of 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s
Pseudo-Random Binary Sequence (PRBS) pattern
generation and testing for backplane and local
streams
•
•
Sub-rate switching (2 or 4 bits) configuration for
local streams at a data rate of 2.048 Mb/s
Conforms to the mandatory requirements of the
IEEE-1149.1 (JTAG) standard
•
3.3 V operation with 5 V tolerant inputs and I/O’s
•
Meets all the key H.110 mandatory signal
requirements including timing
•
5 V tolerant PCI driver on CT-Bus I/O’s
•
Per-channel variable or constant throughput
delay
Applications
•
Per-stream input delay, programmable for local
streams on a per bit basis
•
Carrier-grade VoIP Gateways
•
IP-PBX and PABX
•
Per-stream output advancement, programmable
for backplane and local streams
•
Integrated Access Devices
•
Per-channel direction control for backplane
streams
•
Access Servers
•
CTI Applications/CompactPCI® Platforms
•
Per-channel message mode for backplane and
local streams
•
H.110, H.100, ST-BUS and proprietary Backplane
Applications
•
Per-channel high impedance output control for
backplane and local streams
Description
•
Compatible to Stratum 4 Enhanced clock
switching standard
The MT90866 Digital Switch provides switching
capacities of 4,096 x 2,432 channels between
backplane and local streams, 2,432 x 2,432 channels
among local streams and 2,048 x 2,048 channels
among backplane streams. The local connected serial
inputs and outputs have 32, 64 and 128 64 kb/s
channels per frame with data rates of 2.048, 4.096 and
8.192 Mb/s respectively. The backplane connected
serial inputs and outputs have 128 and 256 64 kb/s
channels per frame with data rates of 8.192 and
16.384 Mb/s respectively.
-
•
Ordering Information
MT90866AG
344 Ball PBGA
Trays
MT90866AG2 344 Ball PBGA* Trays
*Pb Free Tin/Silver/Copper
-40°C to +85°C
Integrated PLL conforms to Telcordia GR-1244CORE Stratum 4 Enhanced switching standard
-Holdover Mode with holdover frequency
stability of 0.07 ppm
- Jitter attenuation from 1.52 Hz.
- Time interval error (TIE) correction
- Master and Slave mode operation
Non-multiplexed microprocessor interface
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MT90866
Data Sheet
The MT90866 also offers a sub-rate switching configuration which allows 2-bit wide 16 kb/s or 4-bit wide 32 kb/s
data channels to be switched within the device.
The device has features that are programmable on a per-stream or a per-channel basis including message mode,
input delay offset, output advancement offset, direction control, and high impedance output control.
The MT90866 supports all three of the H.110 specification required clocking modes: Primary Master, Secondary
Master and Slave.
VDD5V VDD VSS
STio0
PCI_OE
Backplane
Backplane Data Memory
Interface
(4,096 channels)
Output
P/S
Converter
STo27
Mux
Local Connection Memory
(2,432 locations)
P/S
STo0
Local
Interface
S/P
&
ODE
HiZ
Control
Converter
LCSTo
STio31
(2,432 channels)
Output
S/P
Converter
STi27
Mux
Backplane Connection Memory
(4,096 locations)
Test Port
TMS
TDi
TDo
TCK
TRST
DTA
D15-D0
A13-A0
C32/64o
C1M5o
FAIL_PRI
FAIL_SEC
B_Active
C8_B_io
FRAME_B_io
A_Active
C8_A_io
FRAME_A_io
CS
R/W
Internal Registers &
Microprocessor Interface
DPLL
RESET
Local Interface
Timing Unit
Figure 1 - Functional Block Diagram
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Zarlink Semiconductor Inc.
IC0-IC8
APLL
FAIL_A
FAIL_B
CTREF1
CTREF2
NREFo
PRI_LOS
SEC_LOS
LREF7-0
C20i
TM1
TM2
SG1
AT1
DT1
STi0
Local
Interface
Local Data Memory
DS
BCSTo
HiZ
Control
ST_FPo0
ST_CKo0
ST_FPo1
ST_CKo1
MT90866
Data Sheet
Table of Contents
1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.0 Frame Alignment Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0 Switching Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Backplane Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Local Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.0 Local Input Delay Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.0 Output Advancement Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Local Output Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.0 Delay Through the MT90866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.0 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.1 DTA Data Transfer Acknowledgment Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11.0 Address Mapping of Memories and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.0 Backplane Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.0 Local Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15.0 External Tristate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15.1 BCSTo Control Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15.2 LCSTo Control Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16.0 DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16.1 MT90866 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16.1.1 Primary Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16.1.2 Secondary Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
16.1.3 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
17.0 DPLL Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.1 Reference Select and Frequency Mode MUX Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.2 PRI and SEC MUX Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.3 Frame Select MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.4 CT Clock and Frame Monitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.5 Reference Monitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.6 State Machine Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.0 Phase Locked Loop (PLL) Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18.1 Skew Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
18.2 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
18.3 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18.4 Phase Offset Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18.5 Phase Slope Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.6 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.7 Digitally Controlled Oscillator (DCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.8 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.9 Frequency Select MUX Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
18.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
18.10.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
18.10.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
18.10.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
Table of Contents
19.1 Intrinsic Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19.2 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19.4 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
19.5 Holdover Frequency Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
19.6 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
19.7 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
19.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
19.9 Phase Lock Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
20.0 Initialization of the MT90866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
21.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
21.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
21.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
21.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
21.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
22.0 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
23.0 DC/AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
24.0 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2 - 27 mm x 27 mm PBGA (JEDEC MO-151) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3 - CT-Bus Timing for 8 Mb/s Backplane Data Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4 - ST-BUS Timing for 16 Mb/s Backplane Data Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5 - Block Programming Data in the Connection Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6 - Backplane Control (BCSTo) Timing when the STio data rate is 8 Mb/s. . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7 - Backplane Control (BCSTo) Timing when the STio data rate is 16 Mb/s. . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8 - Local Control (LCSTo) Timing when STo0-18 are operated at 8 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9 - Local Control (LCSTo) Timing when STo0-18 are operated at 4 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10 - Local Control (LCSTo) Timing when all STo0-27 are operated at 2 Mb/s . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11 - Example of Local Control (LCSTo) Timing when the Local Streams have Different Data Rates . . . . . 31
Figure 12 - Typical Timing Control Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13 - DPLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14 - State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15 - Block Diagram of the PLL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16 - Skew Control Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17 - DPLL Jitter Transfer Function Diagram - wide range of frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18 - Detailed DPLL Jitter Transfer Function Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19 - Local Input Bit Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 20 - Example of Backplane Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 21 - Local Output Advancement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 22 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 23 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master Mode and
Secondary Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 24 - Backplane Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 25 - Reference Input Timing Diagram when the input frequency = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 26 - Reference Input Timing Diagram when the input frequency = 2.048 MHz . . . . . . . . . . . . . . . . . . . . . 71
Figure 27 - Reference Input Timing Diagram when the input frequency = 1.544 Hz . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 28 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 72
Figure 29 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . 72
Figure 30 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register . . . . . . . . . . . . . . . . 72
Figure 31 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register . . . . . . . . . . . . . . . 72
Figure 32 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register . . . . . . . . . . . . . . . 73
Figure 33 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz . . . . . . . . . . . . . . . . . . . . . . 73
Figure 34 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz . . . . . . . . . . . . . . . . . . . . . . 74
Figure 35 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 36 - C1M5o Output Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 37 - Backplane Serial Stream Timing when the Data Rate is 8 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 38 - Backplane Serial Stream Timing when the Data Rate is 16 Mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39 - Local Serial Stream Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 40 - Local Serial Stream Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 41 - Local Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 42 - Backplane Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 43 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 44 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 45 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 46 - Reset Pin Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5
Zarlink Semiconductor Inc.
MT90866
Data Sheet
List of Tables
Table 1 - Mode Selection for Backplane Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2 - Mode Selection for Local STi0 - 3 and STo0 - 3 Streams, Group 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3 - Mode Selection for Local STi4 - 7 and STo4 - 7 Streams, Group 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4 - Mode Selection for Local STi8 - 11 and STo8 - 11 Streams, Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6 - Mode Selection for Local STi16 - 27 and STo16 - 27 Streams, Group 4. . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5 - Mode Selection for Local STi12 - 15 and ST012 - 15 Streams, Group 3 . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7 - Address Map For Internal Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10 - Device Mode Selection (DMS) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 11 - Block Programming Mode (BPM) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 12 - Local Input Bit Delay Registers (LIDR0 to LIDR9) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 13 - Local Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 14 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 15 - Local Output Advancement Registers (LOAR0 to LOAR3) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16 - Local Bit Error Rate Input Selection (LBIS) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17 - Local Bit Error Rate Register (LBERR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 18 - Backplane Bit Error Rate Input Selection (BBIS) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 19 - Backplane Bit Error Rate Register (BBERR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 20 - DPLL Operation Mode (DOM1) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 21 - DPLL Operation Mode (DOM2) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 22 - MT90866 Mode Selection - By Programming DOM1 and DOM2 Registers . . . . . . . . . . . . . . . . . . . . . 60
Table 23 - DPLL Output Adjustment (DPOA) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 24 - DPLL House Keeping (DHKR) Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 25 - Backplane Connection Memory Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 26 - BSAB and BCAB Bits Usage when Source Streams are from the Local Port. . . . . . . . . . . . . . . . . . . . 64
Table 27 - BSAB and BCAB Bits Usage when Source Streams are from the Backplane Port. . . . . . . . . . . . . . . . 64
Table 28 - Local Connection Memory High Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 29 - Local Connection Memory Low Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 30 - LSAB and LCAB Bits Usage when Source Streams are from the Backplane Port . . . . . . . . . . . . . . . . 66
Table 31 - LSAB and LCAB Bits Usage when Source Stream are from the Local Port . . . . . . . . . . . . . . . . . . . . . 66
6
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Changes Summary
The following table captures the changes from the September 2005 issue.
Page
Item
Change
9
Ball Signal Assignment
Added missing Ball signals.
11
Pin name: RESET
Worst case 600 µs instead of 100 µs is specified for the
delay that must be applied before performing the first
microprocessor access after the release of RESET pin.
44
Section 20.0
The 600 µs delay requirement before performing the first
microprocessor access after the release of RESET pin is
added in this section for completeness.
80
Figure 40
Corrected 8 Mb/s stream channel to ch127
The following table captures the changes from the October 2003 issue.
Page
Item
Change
37, 58
Section 18.2 and Table 21
Added description clarifying that the MTIE reset must be
set when the device is in the slave mode.
60
Table 22
Added MRST (bit 10) in MT90866 Mode Selection table
39, 41
Section 18.7 and Section 19.1
Deleted the intrinsic jitter descriptions in Section 18.7 and
Section 19.1 and replaced them with “AC Electrical
Characteristics†- Output Clock Jitter Generation
(Unfiltered)” on page 76.
77, 78,
80
“AC Electrical Characteristics† Backplane Serial Streams with Data
Rate of 8 Mb/s” , “AC Electrical
Characteristics† - Backplane Serial
Streams with Data Rate of 16 Mb/s” and
“AC Electrical Characteristics† - Local
Serial Stream Input Timing” .
Input data sampling timings were updated for clarity
purposes.
7
Zarlink Semiconductor Inc.
MT90866
1
1
2
3
4
5
6
7
8
9
10
11
Data Sheet
12
13
14
15
16
17
18
19
20
A
STio VDD5V
14
STio
17
STio
19
STio
22
STio
25
STio
26
STio
31
VDD5V
STi2
STi3
STi8
STi9
STi12
STi13
STi16
STi21
STi22
STi24
STi26
A
B
STio
13
GND
STio
18
STio
21
STio
24
STio
27
STio
30
PCI_
OE
STi1
STi5
STi6
STi10
GND
STi14
STi17
STi20
STi23
STi25
STi27
B
C
STio
12
GND
STio
16
STio
20
STio
23
STio
28
STio
29
GND
STi0
STi4
STi7
STi11
GND
STi15
STi18
STi19
GND
GND
GND
C
STio
11
GND
VDD
GND
VDD
VDD
GND
VDD
GND
VDD
GND
GND
STo0
STo1
D
VDD
LCSTo
STo2
STo3
E
GND
STo4
STo5
STo6
F
VDD
STo8
STo9
STo7
G
GND
STo10
STo11
STo13
H
VDD
STo12
STo14
STo15
J
GND
STo16
STo17
STo18
K
VDD
STo20
STo21
STo19
L
VDD
STo22
STo23
STo24
M
GND
STo27
STo26
STo25
N
VDD
GND
B_Act
ive
A_Act
ive
P
C8_A_io
Frame_
A _io
R
VDD5V
STio
15
STio
10
D
STio
9
E
STio
6
STio
7
STio
8
VDD
F
STio
5
STio
2
STio
3
GND
G
STio
4
STio
0
STio
1
VDD
H
VDD5V
GND
GND
GND
J
DTA
BCSTo
D15
K
D12
D13
L
D9
M
VDD
GND
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D14
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D10
D11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D6
D7
D8
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N
D5
D3
D4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P
D2
D1
D0
VDD
GND
GND
GND
GND
GND
GND
GND
GND
R
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T
A13
A12
A11
VDD
U
A10
A9
A8
GND
VDD
GND
VDD
GND
VDD
V
CS
A7
A5
A2
RESET
TCK
IC2
IC4
W
DS
A6
A3
A0
TMS
TDi
IC5
Y
R/W
A4
A1
TDo
TRST
IC0
2
3
4
5
6
1
VDD
GND
VDD
IC6
IC3
TM1
GND
ST_
FPo1
IC7
SG1
AT1
IC1
ST_
CKo1
IC8
TM2
7
8
9
10
GND
GND
ODE
VDD
Frame_ C8_B_io Fail_A
B _io
T
GND
Fail_B CTREF1 CTREF2
U
VDD
GND
APLL
VDD
APLL
GND
LREF5 LREF2 NREFo
GND
C64
BYPS
FAIL_
LREF6 LREF3 LREF0 C32/64o
PRI
DT1
GND
C20i
FAIL_
C1M5o Sec_Los Pri_Los
SEC LREF7 LREF4 LREF1
11
12
13
14
15
VDD
16
17
GND
18
ST_
CKo0
ST_
FPo0
V
GND
GND
W
19
Top View
1
- A1 corner is identified by metallized markings.
Figure 2 - 27 mm x 27 mm PBGA (JEDEC MO-151) Pinout
8
Zarlink Semiconductor Inc.
20
Y
MT90866
Data Sheet
Ball Signal Assignment
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
STIO14
C5
STIO20
F1
STIO5
H17
GND
L6
GND
N14
GND
A2
VDD5V
C6
STIO23
F2
STIO2
H18
STO10
L7
GND
N15
GND
A3
STIO17
C7
STIO28
F3
STIO3
H19
STO11
L8
GND
N17
GND
A4
STIO19
C8
STIO29
F4
GND
H20
STO13
L9
GND
N18
STO27
A5
STIO22
C9
GND
F8
GND
J1
DTA
L10
GND
N19
STO26
A6
STIO25
C10
STI0
F9
GND
J2
BCSTO
L11
GND
N20
STO25
A7
STIO26
C11
STI4
F10
GND
J3
D15
L12
GND
P1
D2
A8
STIO31
C12
STI7
F11
GND
J4
VDD
L13
GND
P2
D1
A9
VDD5V
C13
STI11
F12
GND
J6
GND
L14
GND
P3
D0
A10
STI2
C14
GND
F13
GND
J7
GND
L15
GND
P4
VDD
A11
STI3
C15
STI15
F17
GND
J8
GND
L17
VDD
P7
GND
A12
STI8
C16
STI18
F18
STO4
J9
GND
L18
STO20
P8
GND
A13
STI9
C17
STI19
F19
STO5
J10
GND
L19
STO21
P9
GND
A14
STI12
C18
GND
F20
STO6
J11
GND
L20
STO19
P10
GND
A15
STI13
C19
GND
G1
STIO4
J12
GND
M1
D6
P11
GND
A16
STI16
C20
GND
G2
STIO0
J13
GND
M2
D7
P12
GND
A17
STI21
D1
STIO9
G3
STIO1
J14
GND
M3
D8
P13
GND
GND
A18
STI22
D2
STIO10
G4
VDD
J15
GND
M4
VDD
P14
A19
STI24
D3
STIO11
G7
GND
J17
VDD
M6
GND
P17
VDD
A20
STI26
D4
GND
G8
GND
J18
STO12
M7
GND
P18
GND
B1
STIO13
D5
VDD
G9
GND
J19
STO14
M8
GND
P19
B_ACTIVE
B2
VDD5V
D6
GND
G10
GND
J20
STO15
M9
GND
P20
A_ACTIVE
B3
GND
D7
VDD
G11
GND
K1
D12
M10
GND
R1
GND
B4
STIO18
D8
GND
G12
GND
K2
D13
M11
GND
R2
GND
B5
STIO21
D9
VDD
G13
GND
K3
D14
M12
GND
R3
GND
B6
STIO24
D10
GND
G14
GND
K4
VDD
M13
GND
R4
GND
B7
STIO27
D11
VDD
G17
VDD
K6
GND
M14
GND
R8
GND
B8
STIO30
D12
VDD
G18
STO8
K7
GND
M15
GND
R9
GND
B9
PCI_OE
D13
GND
G19
STO9
K8
GND
M17
VDD
R10
GND
B10
STI1
D14
VDD
G20
STO7
K9
GND
M18
STO22
R11
GND
B11
STI5
D15
GND
H1
VDD5V
K10
GND
M19
STO23
R12
GND
B12
STI6
D16
VDD
H2
GND
K11
GND
M20
STO24
R13
GND
B13
STI10
D17
GND
H3
GND
K12
GND
N1
D5
R17
GND
B14
GND
D18
GND
H4
GND
K13
GND
N2
D3
R18
ODE
B15
STI14
D19
STO0
H6
GND
K14
GND
N3
D4
R19
C8_A_IO
B16
STI17
D20
STO1
H7
GND
K15
GND
N4
GND
R20
FRAME_A_IO
B17
STI20
E1
STIO6
H8
GND
K17
GND
N6
GND
T1
A13
B18
STI23
E2
STIO7
H9
GND
K18
STO16
N7
GND
T2
A12
B19
STI25
E3
STIO8
H10
GND
K19
STO17
N8
GND
T3
A11
B20
STI27
E4
VDD
H11
GND
K20
STO18
N9
GND
T4
VDD
C1
STIO12
E17
VDD
H12
GND
L1
D9
N10
GND
T17
VDD
C2
STIO15
E18
LCSTO
H13
GND
L2
D10
N11
GND
T18
FRAME_B_IO
C3
GND
E19
STO2
H14
GND
L3
D11
N12
GND
T19
C8_B_IO
C4
STIO16
E20
STO3
H15
GND
L4
GND
N13
GND
T20
FAIL_A
9
Zarlink Semiconductor Inc.
MT90866
Ball
Signal
Ball
Signal
U1
A10
W6
TDi
U2
A9
W7
IC5
ST_FPo1
U3
A8
W8
U4
GND
W9
IC7
U5
VDD
W10
SG1
U6
GND
W11
AT1
U7
VDD
W12
GND
U8
GND
W13
C64BYPS
U9
VDD
W14
FAIL_PRI
U10
VDD
W15
LREF6
U11
GND
W16
LREF3
U12
VDD
W17
LREF0
U13
GND
W18
C32/64o
U14
VDD
W19
GND
U15
GND
W20
GND
U16
VDD
Y1
R/W
U17
GND
Y2
A4
U18
FAIL_B
Y3
A1
U19
CTREF1
Y4
TDo
U20
CTREF2
Y5
TRST
V1
CS
Y6
IC0
V2
A7
Y7
IC1
V3
A5
Y8
ST_CKo1
V4
A2
Y9
IC8
V5
RESET
Y10
TM2
V6
TCK
Y11
DT1
V7
IC2
Y12
GND
V8
IC4
Y13
C20I
V9
IC6
Y14
FAIL_SEC
V10
IC3
Y15
LREF7
V11
TM1
Y16
LREF4
V12
GND
Y17
LREF1
V13
APLLVDD
Y18
C1M5O
V14
APLLGND
Y19
SEC_LOS
V15
LREF5
Y20
PRI_LOS
V16
LREF2
V17
NREFo
V18
GND
V19
ST_CKo0
V20
ST_FPo0
W1
DS
W2
A6
W3
A3
W4
A0
W5
TMS
10
Zarlink Semiconductor Inc.
Data Sheet
MT90866
Data Sheet
Pin Description
PBGA
Ball Number
Name
Description
D5, D7, D9, D11,
D12, D14, D16,
E4, E17, G4, G17,
J4, J17, K4, L17,
M4, M17, P4,
P17, T4, T17,U5,
U7, U9, U10, U12,
U14, U16
VDD
A2,A9,B2,H1
VDD5V
B3, B14,C3, C9,
C14, C18, C19,
C20, D4, D6, D8,
D10, D13, D15,
D17, D18, F4,
F8-F13, F17,
G7-G14, H2, H3,
H4, H6-H15, H17,
J6-J15,
K6-K15, K17, L4,
L6-L15, M6-M15,
N4, N6-15, N17,
P7-P14, P18, R1,
R2, R3, R4,
R8-R13, R17, U4,
U6, U8, U11, U13,
U15, U17, V12,
V18, W12, W19,
W20, Y12
VSS
V13
APLLVDD
+3.3 Volt Analog PLL Power Supply. No special filtering is required for this
pin.
V14
APLLVss
Analog PLL Ground
V5
RESET
Device Reset (5 V Tolerant Input). This input (active low) puts the device in
its reset state; this state clears the device’s internal counters and registers.
To ensure proper reset action, the reset pin must be low for longer than
400 ns. To ensure proper operation, a delay of 600 µs must be applied
before the first microprocessor access is performed after the RESET pin is
set high. The device reset also tristates STo0-27 and STio0-31, and sets the
LCSTo and BCSTo pins. When in a RESET condition, the C8_A_io,
FRAME_A_io, C8_B_io, and FRAME_B_io signals are tri-stated.
G2, G3, F2, F3,
G1, F1, E1, E2,
E3, D1, D2, D3,
C1, B1, A1, C2
STio0-3,
STio4-7,
STio8-11,
STio12-15
+3.3 Volt Power Supply.
+5.0 V/+3.3 V Power Supply. If 5 V power supply is tied to these pins,
STio0-31 pins will meet 5 V PCI requirements. If 3.3 V power supply is tied
to these pins, STio0-31 pins will meet 3.3 V PCI requirements.
Ground.
Serial Input/Output Streams 0 - 15 (5 V Tolerant PCI I/Os). In H.110
mode, these pins accept serial TDM data streams at 8.192 Mb/s with 128
channels per stream. In the 16 Mb/s mode, these pins accept serial TDM
data streams at 16.384 Mb/s with 256 channels per stream respectively.
11
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Pin Description (continued)
PBGA
Ball Number
Name
Description
C4, A3, B4, A4,
C5, B5, A5, C6,
B6, A6, A7, B7,
C7, C8, B8, A8
STio16 - 19,
STio20 - 23,
STio24 - 27,
STio28 - 31
Serial Input/Output Streams 16 - 31 (5 V Tolerant PCI I/Os). In H.110
mode, these pins accept serial TDM data streams at 8.192 Mb/s with 128
channels per stream. In the 16 Mb/s mode, these pins are tristated internally
and should be connected to ground.
C10, B10, A10,
A11
STi0-3
Serial Input Streams 0 - 3 (5 V Tolerant Inputs). In 2 Mb/s, 4 Mb/s or
8Mb/s mode, these inputs accept data rates of 2.048, 4.096 or 8.192 Mb/s
with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit
sub-rate modes, these inputs accept a data rate of 2.048 Mb/s.
C11, B11, B12,
C12
STi4 - 7
Serial Input Streams 4 - 7 (5 V Tolerant Inputs). In 2 Mb/s, 4 Mb/s or
8 Mb/s mode, these inputs accept data rates of 2.048, 4.096 or 8.192 Mb/s
with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit
sub-rate modes, these inputs accept a data rate of 2.048 Mb/s.
A12, A13, B13,
C13
STi8 - 11
Serial Input Streams 8 - 11 (5 V Tolerant Inputs). In 2 Mb/s, 4 Mb/s or
8 Mb/s mode, these inputs accepts data rates of 2.048, 4.096 or 8.192 Mb/s
with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit
sub-rate modes, these inputs accept a data rate of 2.048 Mb/s.
A14, A15, B15,
C15
STi12 - 15
Serial Input Streams 12 - 15 (5 V Tolerant Inputs). In 2 Mb/s, 4 Mb/s or
8 Mb/s mode, these inputs accept data rates of 2.048, 4.096 or 8.192 Mb/s
with 32, 64 or 128 channels per stream respectively. In the 2-bit and 4-bit
sub-rate modes, these inputs accept a data rate of 2.048 Mb/s.
A16, B16, C16,
C17, B17, A17,
A18, B18, A19,
B19, A20, B20
STi16 - 27
Serial Input Streams 16 - 27 (5 V Tolerant Inputs). In 2 Mb/s mode, these
inputs accept data rates of 2.048 Mb/s with 32 channels per stream
respectively. In 4 Mb/s or 8 Mb/s mode, the STi16 - 18 inputs accept data
rates of 4.096 or 8.192 Mb/s with 64 or 128 channels per stream
respectively. In 4 Mb/s or 8 Mb/s mode the STi19 - 27 inputs should be
driven low. No sub-rate switching mode is offered for STi16-27.
D19, D20, E19,
E20
STo0 - 3
Serial Output Streams 0 - 3 (5 V Tolerant Tri-State Outputs). In 2 Mb/s,
4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048, 4.096 or
8.192 Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit
and 4-bit sub-rate modes, these outputs have a data rate of 2.048 Mb/s.
F18, F19, F20,
G20
STo4 - 7
Serial Output Streams 4 - 7 (5 V Tolerant Tri-State Outputs). In 2 Mb/s,
4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048, 4.096 or
8.192 Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit
and 4-bit sub-rate modes, these outputs have a data rate of 2.048 Mb/s.
G18, G19, H18,
H19
STo8 - 11
Serial Output Streams 8 - 11 (5 V Tolerant Tri-State Outputs). In 2 Mb/s,
4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048, 4.096 or
8.192 Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit
and 4-bit sub-rate modes, these outputs have a data rate of 2.048 Mb/s.
J18, H20, J19,
J20
STo12 - 15
Serial Output Streams 12 - 15 (5 V Tolerant Tri-State Outputs). In 2 Mb/s,
4 Mb/s or 8 Mb/s mode, these outputs have data rates of 2.048, 4.096 or
8.192 Mb/s with 32, 64 or 128 channels per stream respectively. In the 2-bit
and 4-bit sub-rate modes, these outputs have a data rate of 2.048 Mb/s.
12
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Pin Description (continued)
PBGA
Ball Number
Name
Description
K18, K19, K20,
L20, L18, L19,
M18, M19, M20,
N20, N19, N18
STo16 - 27
Serial Output Streams 16 to 27 (5 V Tolerant Tri-state Outputs). In
2 Mb/s mode, these outputs have data rate of 2.048 Mb/s with 32 channels
per stream. In 4 Mb/s or 8 Mb/s mode, the STo16 - 18 outputs have data
rates of 4.096 Mb/s or 8.192 Mb/s with 64 or 128 channels per stream
respectively; STo19 - 27 are driven low. No sub-rate switching mode is
offered for STo16-27.
R18
ODE
Output Drive Enable (5 V Tolerant Input). When this pin is low, STo0 to
STo27, STio0 to STio31, C1M5o, C32/64o, ST_CKo0, ST_CKo1, ST_FPo0
and ST_FPo1 outputs are all in high-impedance state. When ODE is high all
of the aforementioned pins are active.
J2
BCSTo
Backplane Control Signal (Output). This pin is used for backplane
external tristate controllers. When this signal is high, the corresponding
output channels are in a high impedance state. BCSTo’s bit rate is
32.768 MHz.
E18
LCSTo
Local Control Signal (Output). This pin is used for local external tristate
control. When this signal is high, the corresponding ouput channels are in a
high impedance state. The bit rate is 32.768 MHz.
Y13
C20i
Master Clock (5 V Tolerant Input). This pin accepts a 20.000 MHz clock.
R19
C8_A_io
Clock A (5 V Tolerant I/O). This is a 8.192 MHz clock with 50% duty cycle.
R20
FRAME_A_io Frame Reference A (5 V Tolerant I/O). This is a 122 ns wide, negative
pulse, with 125 us period.
P20
A_Active
A Clock Active Indicator (5 V Tolerant Output): This pin indicates whether
the C8_A_io and the FRAME_A_io pins are inputs or outputs. When Bit 13
of the DOM1 register is low, this pin drives low and the C8_A_io and
FRAME_A_io output drivers are disabled. When Bit 13 of the DOM1 register
is high, this pin drives high and the C8_A_io and FRAME_A_io output
drivers are enabled.
T19
C8_B_io
Clock B (5 V Tolerant I/O). This is a 8.192 MHz clock with 50% duty cycle.
T18
FRAME_B_io Frame Reference B (5 V Tolerant I/O). This is a 122 ns wide, negative
pulse, with 125 us period.
P19
B_Active
B Clock Active Indicator (5 V Tolerant Output): This pin indicates whether
the C8_B_io and the FRAME_B_io pins are inputs or outputs. When Bit 14
of the DOM1 register is low, this pin drives low and the C8_B_io and
FRAME_B_io output drivers are disabled. When Bit 14 of the DOM1 register
is high, this pins drives high and the C8_B_io and FRAME_B_io output
drivers are enabled.
T20
FAIL_A
A Failure (Output). When the C8_A_io or the FRAME_A_io signal fails, this
signal goes to high.
U18
FAIL_B
B Failure (Output). When the C8_B_io or the FRAME_B_io signal fails, this
signal goes to high.
13
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Pin Description (continued)
PBGA
Ball Number
Name
U19
CTREF1
CT-Bus Reference 1 (5 V Tolerant Input). This pin accepts 8 KHz,
1.544 MHz or 2.048 MHz network timing reference.
U20
CTREF2
CT-Bus Reference 2 (5 V Tolerant Input). This pin accepts 8 KHz,
1.544 MHz or 2.048 MHz network timing reference.
W17, Y17, V16,
W16, Y16, V15,
W15, Y15
LREF0- 7
Local Reference (5 V Tolerant Inputs). These pins accept 8 KHz,
1.544 MHz or 2.048 MHz local timing reference.
V17
NREFo
Network Reference Output (Output). Any local reference can be switched
to this output. The output data rate can be either the same as the selected
reference input data rate or divided to be 8 KHz.
Y20
PRI_LOS
Primary Reference Lost (5 V Tolerant Input). When this signal is high, it
indicates that PRIMARY REFERENCE is not valid. Combined with
SEC_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
Y19
SEC_LOS
Secondary Reference Lost (5 V Tolerant Input). When this signal is high,
it indicates that SECONDARY REFERENCE is not valid. Combined with the
PRI_LOS input, this input pin is used in the External Reference Switching
Mode of the DPLL.
W14
FAIL_PRI
Primary Reference Failure (5 V Tolerant Output). This pin reflects the
logic status of the PLS bit of the DPLL House Keeping Register (DHKR).
When the primary reference fails, this signal goes to 1.
Y14
FAIL_SEC
Secondary Reference Failure (5 V Tolerant Output). This pin reflects the
logic status of the SLS bit of the DPLL House Keeping Register (DHKR).
When the secondary reference fails, this signal goes to 1.
W18
C32/64o
C32/64o Clock (5 V Tolerant Output). A 32.768 MHz output clock when the
DPLL Clock Monitor register bit (CKM) is low. A 65.536 MHz clock when the
DPLL Clock Monitor register bit (CKM) is high.
Y18
C1M5o
C1.5o Clock (5 V Tolerant Output). A 1.544 MHz output clock.
V20
ST_FPo0
ST-Bus Frame Pulse Output (5 V Tolerant Output). The width of this
output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is
8 KHz.
V19
ST_CKo0
ST-Bus Clock Output (5 V Tolerant Output). The frequency of this output
ST-Bus clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
W8
ST_FPo1
ST-Bus Frame Pulse Output (5 V Tolerant Output). The width of this
output ST-Bus frame pulse can be 244 ns, 122 ns or 61 ns. The frequency is
8 KHz.
Y8
ST_CKo1
ST-Bus Clock Output (5 V Tolerant Output). The frequency of this output
ST-Bus clock can be 4.096 MHz, 8.192 MHz or 16.384 MHz.
V1
CS
Description
Chip Select (5 V Tolerant Input). This active low input is used by the
microprocessor to access the microport.
14
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Pin Description (continued)
PBGA
Ball Number
Name
Description
W1
DS
Data Strobe (5 V Tolerant Input). This active low input works in conjunction
with CS to initiate the read and write cycles.
Y1
R/W
Read/Write (5 V Tolerant Input). This input controls the direction of the data
bus lines (D0 - D15) during the microprocessor access.
W4, Y3, V4, W3,
Y2, V3, W2, V2,
U3, U2, U1, T3,
T2, T1
A0 - A13
Address 0 - 13 (5 V Tolerant Inputs). These are the address lines to the
internal memories and registers.
P3, P2, P1, N2,
N3, N1, M1, M2,
M3, L1, L2, L3,
K1, K2, K3, J3
D0 - D15
Data Bus 0 - 15 (5 V Tolerant I/Os). These pins form the 16-bit data bus of
the microport.
J1
DTA
Data Transfer Acknowledge (5 V Tolerant Output). This active low output
indicates that a data bus transfer is completed. A pull-up resistor is required
to hold a high level.
B9
PCI_OE
W13
C64BYPS
V11
TM1
APLL Test Pin 1 (3.3 V Input). Use for APLL testing only. In normal
operation, this input should be connected to ground.
Y10
TM2
APLL Test Pin 2 (3.3 V Input). Use for APLL testing only. In normal
operation, this input should be connected to ground.
W10
SG1
APLL Test Control (3.3 V Input). Use for APLL testing only. In normal
operation, this input should be connected to ground.
W11
AT1
Analog Test Access (5 V Tolerant I/O). Use for APLL testing only. No
connection for normal operation.
Y11
DT1
Digital Test Access Output (5 V Tolerant Output). Use for APLL testing
only. No connection for normal operation.
W5
TMS
Test Mode Select (3.3 V Input with Internal pull-up). JTAG signal that
controls the state transitions of the TAP controller. This pin is pulled high by
an internal pull-up when not driven.
W6
TDi
Test Serial Data In (3.3 V Input with Internal pull-up). JTAG serial test
instructions and data are shifted in on this pin. This pin is pulled high by an
internal pull-up when not driven.
Y4
TDo
Test Serial Data Out (3.3 V Tolerant Tri-state Output). JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high
impedance state when JTAG is not enabled.
PCI Output Enable (3.3 V Tolerant Input). This active low input is the
control signal used to tristate the STio0 - 31 pins during hot-swapping.
During normal operation this signal should be low.
PLL Bypass Clock Input (5 V Tolerant Input). Used for device testing. In
functional mode, this input MUST be low.
15
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Pin Description (continued)
PBGA
Ball Number
Name
V6
TCK
Test Clock (5 V Tolerant Input). Provides the clock to the JTAG test logic.
This pin should be low when JTAG is not enabled.
Y5
TRST
Test Reset (3.3 V Input with Internal pull-up). Asynchronously initializes
the JTAG TAP Controller by putting it in the Test-Logic-Reset state. This pin
should be pulled low to ensure that the MT90866 is in normal functional
mode.
Y6
IC0
Leave unconnected for normal operation.
Y7
IC1
Leave unconnected for normal operation.
V7
IC2
In normal operation this pin MUST be connected to ground.
V10
IC3
Leave unconnected for normal operation.
V8
IC4
Leave unconnected for normal operation.
W7
IC5
Leave unconnected for normal operation.
V9
IC6
Leave unconnected for normal operation.
W9
IC7
Leave unconnected for normal operation.
Y9
IC8
Leave unconnected for normal operation.
Description
16
Zarlink Semiconductor Inc.
MT90866
1.0
Data Sheet
Device Overview
The MT90866 can switch up to 4,096 × 2,432 channels while providing a rate conversion capability. It is designed to
switch 64 kb/s PCM or N X 64 kb/s data between the backplane and local switching applications. The device
maintains frame integrity in data applications and minimum throughput delay for voice application on a per channel
basis.
The backplane interface can operate at 8.192 Mb/s in CT-Bus mode or 16.384 Mb/s in ST-BUS mode and is
arranged in 125 µs wide frames that contain 128 or 256 channels respectively. A built-in rate conversion circuit
allows users to interface between backplane and local interfaces which operates at 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s. When the device is in the local sub-rate switching mode, 2-bit 16 kb/s or 4-bit 32 kb/s data channels
can be switched within the device. The local sub-rate switching mode is available in 2 Mb/s mode only.
By using Zarlink’s message mode capability, the microprocessor can access input and output time slots on a per
channel basis. This feature is useful for transferring control and status information for external circuits or other TDM
devices.
2.0
Functional Description
A Functional Block Diagram of the MT90866 is shown in Figure 1, "Functional Block Diagram" on page 2. It is
designed to interface CT-Bus and ST-BUS serial streams from a backplane source and ST-BUS serial streams from
a local source.
3.0
Frame Alignment Timing
In the ST-BUS or the CT-Bus mode, the C8_A_io or C8_B_io pin accepts an 8.192 MHz clock for the frame pulse
alignment. The FRAME_A_io or FRAME_B_io is the frame pulse signal which goes low at the frame boundary for
122 ns. The frame boundary is defined by the rising edge of the C8_A_io or C8_B_io clock during the low cycle of
the frame pulse. Figure 3, "CT-Bus Timing for 8 Mb/s Backplane Data Streams" on page 17 is the CT-Bus timing for
the backplane 8.192 Mb/s data streams and Figure 4, "ST-BUS Timing for 16 Mb/s Backplane Data Streams" on
page 18 is the ST-BUS timing for the 16.384 Mb/s backplane data stream.
FRAME_A_io,
FRAME_B_io
(CT Frame)
C8_A_io,
C8_B_io
(8.192 MHz)
Channel 0
STio 0 - 31
(8 Mb/s mode)
1
0
7
6
5
4
3
Channel 127
2
1
0
6
5
4
3
2
Figure 3 - CT-Bus Timing for 8 Mb/s Backplane Data Streams
17
Zarlink Semiconductor Inc.
1
0
7
MT90866
Data Sheet
FRAME_A_io,
FRAME_B_io
(CT Frame)
C8_A_io,
C8_B_io
8.192 MHz
Ch 255
STio 0 - 15
(16 Mb/s mode)
Channel 0
Channel 1
Channel 254
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Channel 255
Ch 0
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5
Figure 4 - ST-BUS Timing for 16 Mb/s Backplane Data Streams
4.0
Switching Configuration
The device has two operation modes at different data rates for the backplane interface and five operation modes for
the local interface. These modes can be programmed via the Device Mode Selection (DMS) register. Mode
selections between the backplane and local interfaces are independent.
4.1
Backplane Interface
The backplane interface can be programmed to accept data streams of 8 Mb/s or 16 Mb/s. When H.110 mode is
enabled, STio0 to STio31 have a data rate of 8.192 Mb/s. When ST-BUS mode is enabled, STio0 to STio15 have a
data rate of 16.384 Mb/s. Table 1 on page 18 describes the data rates and mode selections for the backplane
interface.
4.2
Local Interface
Five operation modes, 2 Mb/s, 4 Mb/s, 8 Mb/s, 2-bit sub-rate and 4-bit sub-rate switching, can be selected for the
local ST-BUS interface. The local interface is divided into five groups. Group 0 contains STi/STo0-3, Group 1
contains STi/STo4-7, Group 2 contains STi/STo8-11, Group 3 contains STi/STo12-15 and Group 4 contains
STi/STo16-27. Each group can be selected individually through the Device Mode Selection (DMS) register. Streams
belonging to the same group have the same operation mode. For Groups 0 to 3, any one of the five operation
modes can be selected. Input data streams STi0-15 and output data streams, STo0 -15 can be selected according
to the group to which they belong. STi16-27 and output data streams STo16-27 belong to Group 4 and can operate
in 2 Mb/s mode. In Group 4, only input data streams Sti16-18 and output data streams Sto16-18 can operate in
4 Mb/s and 8 Mb/s mode. When operating Group 4 at 4 Mb/s or 8 Mb/s the unused output streams, STo19-27 are
driven low. No sub-rate modes are available for Group 4 data streams. See Table 2 on page 19 to Table 6 on
page 20 for a description of the data rates and mode selection for the local ST-BUS interface.
BMS bit of the DMS Register
Modes
Backplane Interface
0
8.192 Mb/s
STio0 - 31
1
16.384 Mb/s
STio0 - 15
Table 1 - Mode Selection for Backplane Streams
18
Zarlink Semiconductor Inc.
MT90866
DMS Register Bits
Modes
LG02
LG01
LG00
0
0
0
8.192 Mb/s
0
0
1
4.096 Mb/s
0
1
0
2.048 Mb/s
0
1
1
4-bit subrate
1
0
0
2-bit subrate
Data Sheet
Usable Streams
STi0 - 3, STo0 - 3
Table 2 - Mode Selection for Local STi0 - 3 and STo0 - 3 Streams, Group 0
DMS Register Bits
Modes
LG12
LG11
LG10
0
0
0
8.192 Mb/s
0
0
1
4.096 Mb/s
0
1
0
2.048 Mb/s
0
1
1
4-bit subrate
1
0
0
2-bit subrate
Usable Streams
STi4 - 7, STo4 -7
Table 3 - Mode Selection for Local STi4 - 7 and STo4 - 7 Streams, Group 1
DMS Register Bits
Modes
LG22
LG21
LG20
0
0
0
8.192 Mb/s
0
0
1
4.096 Mb/s
0
1
0
2.048 Mb/s
0
1
1
4-bit subrate
1
0
0
2-bit subrate
Usable Streams
STi8 - 11, STo8 - 11
Table 4 - Mode Selection for Local STi8 - 11 and STo8 - 11 Streams, Group 2
19
Zarlink Semiconductor Inc.
MT90866
DMS Register Bits
Data Sheet
Modes
LG32
LG31
LG30
0
0
0
8.192 Mb/s
0
0
1
4.096 Mb/s
0
1
0
2.048 Mb/s
0
1
1
4-bit subrate
1
0
0
2-bit subrate
Usable Streams
STi12-15, STo12-15
Table 5 - Mode Selection for Local STi12 - 15 and ST012 - 15 Streams, Group 3
DMS Register Bits
Modes
Usable Streams
0
8.192 Mb/s
STi16 - 18, STo16 - 18
0
1
4.096 Mb/s
1
0
2.048 Mb/s
LG41
LG40
0
STi16 - 27, STo16 - 27
Table 6 - Mode Selection for Local STi16 - 27 and STo16 - 27 Streams, Group 4
5.0
Local Input Delay Selection
The local input delay selection allows individual local input streams to be aligned and shifted against the input frame
pulse (FRAME_A_io or FRAME_B_io). This feature compensates for the variable path delays in the local interface.
Such delays can occur in large centralized and distributed switching system.
Each local input stream can have its own bit delay offset value by programming the local input bit delay selection
registers (LIDR0 to LIDR9). See Table 12, "Local Input Bit Delay Registers (LIDR0 to LIDR9) Bits" on page 50, for
the contents of these registers. Possible bit adjustment can range up to +7 3/4 bit periods forward with resolution of
1/4 bit period. See Table 13 on page 51 and Figure 19 on page 51 for local input delay programming.
6.0
Output Advancement Selection
The MT90866 allows users to advance individual backplane or local output streams with respect to the frame
boundary. This feature is useful in compensating variable output delays caused by various output loading
conditions. Each output stream can have its own advancement value programmed by the output advancement
registers. The backplane output advancement registers (BOAR0 to BOAR3) are used to program the backplane
output advancement. The local output advancement registers (LOAR0 to LOAR3) are used to program the local
output advancement. Possible adjustment for local and backplane output data streams is 22.5 ns with a resolution
of 7.5 ns. The advancement is independent of the output data rate. Table 14 on page 52 and Figure 20, "Example
of Backplane Output Advancement Timing" on page 52, and Table 15 on page 53 and Figure 21, "Local Output
Advancement Timing" on page 53 describe the details of the output advancement programming for the backplane
and local interfaces respectively.
20
Zarlink Semiconductor Inc.
MT90866
7.0
Data Sheet
Local Output Timing Considerations
The output data of the MT90866’s local side is slightly advanced with respect to the frame and bit boundary as
defined by the local output clocks and frame pulses (ST_FPo0, ST_CKo0, ST_FPo1, ST_CKo1). The advancement
is in the range of 5 ns to 17 ns. Despite this advancement, the MT90866 will operate within the parameters
specified in the datasheet because input data are usually sampled at the 3/4 or 1/2 point of the bit cell. However, the
user should be cautious when introducing additional delay to the clock signals only (e.g., by passing them through
glue logic, FPGA, or CPLD), which will introduce a few nanoseconds of delay relative to the data. If the clock signal
is delayed, data will be advanced from the receiver device’s point of view. This may cause errors in sampling the
data. Using an example where a 3/4 sampling point is used, there is about 30 ns from the sampling point to the end
of the bit cell. With a worst-case of 17 ns advancement, the timing margin will be approximately 13 ns. Any
additional delays applied to the local output clocks (ST_CKo0 and ST_CKo1) must not exceed 13 ns minus the
hold time of the receiving device. Delays applied to both clocks and data equally will not impact the device
operation.
8.0
Memory Block Programming
The MT90866 block programming mode (BPM) register provides users with the capability of initializing the local
and backplane connection memories in two frames. The local connection memory is partitioned into high and low
parts. Bit 13 - bit 15 of every backplane connection memory location will be programmed with the pattern stored in
bit 6 - bit 8 of the BPM register. Bit 13 - bit 15 of every local connection memory low location will be programmed
with the pattern stored in bits 3 to 5 of the BPM register. The other bit positions of the backplane connection
memory, the local low connection memory and all bits of the local high connection memory are loaded with zeros.
See Figure 5, "Block Programming Data in the Connection Memories" on page 22 for the connection memory
contents when the device is in block programming mode.
The block programming mode is enabled by setting the memory block program (MBP) bit of the Control register to
high. After the block programming enable (BPE) bit of the BPM register is set to high, the block programming data
will be loaded into bits 13 to 15 of every backplane connection memory location and bits 13 to 15 of every local
connection memory low location. The other connection memory bits are loaded with zeros. When the memory block
programming is completed, the device resets the BPE bit to low. See Table 11 on page 49 for the bit assignment of
the BPM register.
9.0
Delay Through the MT90866
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time slot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications it is recommended to select variable throughput delay to
ensure minimum delay between input and output data. In wideband data applications it is recommended to select
constant throughput delay to maintain the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the BTM2 - BTM0 bits of
the backplane connection memory or LTM0 - LTM2 bits of the local connection memory as described in Table 25 on
page 63 and Table 29 on page 65, respectively.
9.1
Variable Delay Mode
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams. The minimum delays achievable in the MT90866 device are 3-channel
delay, 5-channel delay, and 10-channel delay for the 2 MB/s, 4 MB/s, and 8 MB/s respectively. The maximum delay
is one frame plus three channels, one frame plus five channels, and one frame plus ten channels for the 2 Mb/s,
4 Mb/s and 8 Mb/s modes respectively.
For the backplane interface, the variable delay mode can be programmed through the backplane connection
memory bits, BTM2 - BTM0. When BTM2 - BTM0 are programmed to “000”, it is a per-channel variable delay from
21
Zarlink Semiconductor Inc.
MT90866
Data Sheet
local input to the backplane output. When BTM2 - BTM0 are set to “010”, it is a per-channel variable delay from
backplane input to backplane output.
For the local interface, the variable delay mode can be programmed through the local connection memory low
bits, LTM2 - LTM0. When LTM2 - LTM0 is programmed to “000”, it is a per-channel variable delay from local
input to local output. When LTM2 - LTM0 is set to “010”, it is a per-channel variable delay from backplane input
to local output.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BBPD2 BBPD1 BBPD0
Backplane Connection Memory (BCM)
15
14
13
12
LBPD2 LBPD1 LBPD0
0
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Local Connection Memory Low (LCML)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Local Connection Memory High (LCMH)
Figure 5 - Block Programming Data in the Connection Memories
9.2
Constant Delay Mode
In this mode, a multiple data memory buffer is used to maintain frame integrity in all switching configurations by
using three pages of Data Memory where a channel written in any of the buffers during frame N is always read out
during frame N+2.
For the backplane interface, when BTM2 - BTM0 is programmed to “001”, it is a per-channel constant delay mode
from local input to backplane output. When BTM2 - BTM0 is programmed to “011”, it is a per-channel constant
delay from backplane input to backplane output.
For the local interface, when LTM2 - LTM0 is programmed to “001”, it is a per-channel constant delay mode from
local input to local output. When LTM2 - LTM0 is set to “011”, it is a per-channel constant delay mode from
backplane input to local output.
10.0
Microprocessor Interface
The MT90866 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is
compatible with Motorola non-multiplexed bus structure. The required microprocessor signals are the 16-bit data
bus (D15-D0), 14-bit address bus (A13-A0) and 4 control lines (CS, DS, R/W and DTA). See Figure 44, "Motorola
Non-Multiplexed Bus Timing" on page 83 for the Motorola non-multiplexed bus timing.
The MT90866 microprocessor port provides access to the internal registers, the connection and data memories. All
locations provide read/write access except for the Local and Backplane Bit Error Rate registers (LBERR and
BBERR) and Data Memory which can only be read by the users.
10.1
DTA Data Transfer Acknowledgment Pin
The DTA pin of the microprocessor is driven LOW by internal logic to indicate that a data bus transfer is completed.
When the bus cycle ends, this pin switches to the high impedance state. An external pull-up of between 1 KΩ and
10 KΩ is required at this output.
22
Zarlink Semiconductor Inc.
MT90866
11.0
Data Sheet
Address Mapping of Memories and Registers
The address bus on the microprocessor interface selects the internal registers and memories of the MT90866. If
the address bit A13 is low, then the registers are addressed by A12 to A0 as shown in Table 7 on page 23.
A13 - A0
Location
0000H
Control Register, CR
0001H
Device Mode Selection Register, DMS
0002H
Block Programming Mode Register, BPM
0003H
Reserved
0004H
Local Input Bit Delay Register 0, LIDR0
0005H
Local Input Bit Delay Register 0, LIDR1
0006H
Local Input Bit Delay Register 2, LIDR2
0007H
Local Input Bit Delay Register 3, LIDR3
0008H
Local Input Bit Delay Register 4, LIDR4
0009H
Local Input Bit Delay Register 5, LIDR5
000AH
Local Input Bit Delay Register 6, LIDR6
000BH
Local Input Bit Delay Register 7, LIDR7
000CH
Local Input Bit Delay Register 8, LIDR8
000DH
Local Input Bit Delay Register 9, LIDR9
000EH
to 001BH
Reserved
001CH
Backplane Output Advancement Register 0, BOAR0
001DH
Backplane Output Advancement Register 1, BOAR1
001EH
Backplane Output Advancement Register 2, BOAR2
001FH
Backplane Output Advancement Register 3, BOAR3
0020H
Local Output Advancement Register 0, LOAR0
0021H
Local Output Advancement Register 1, LOAR1
0022H
Local Output Advancement Register 2, LOAR2
0023H
Local Output Advancement Register 3, LOAR3
0024H
to 0026H
Reserved
0027H
Local BER Input Selection Register, LBIS
0028H
Local BER Register, LBERR
0029H
Backplane BER Input Selection Register, BBIS
002AH
Backplane BER Register, BBERR
002BH
DPLL Operation Mode Register 1, DOM1
Table 7 - Address Map For Internal Registers (A13 = 0)
23
Zarlink Semiconductor Inc.
MT90866
A13 - A0
Data Sheet
Location
002CH
DPLL Operation Mode Register 2, DOM2
002DH
DPLL Output Adjustment Register, DPOA
002EH
DPLL House Keeping Register, DHKR
Table 7 - Address Map For Internal Registers (A13 = 0) (continued)
If A13 is high, the remaining address input lines are used to select the data and connection memory positions
corresponding to the serial input or output data streams as shown in Table 8 on page 25.
The Control register (CR), the Device Mode Selection register (DMS) and the Block Programming Mode register
(BPM) control all the major functions of the device. The DMS and BPM should be programmed immediately after
system power up to establish the desired switching configuration as explained in the Frame Alignment Timing and
Switching Configurations sections. The Control register is used to select Data or Connection Memory for microport
operations, ST-BUS output frame and clock modes, and to set Memory Block Programing and Bit Error Rate
Testing.
The Control register (CR) consists of the memory block programming bit (MBP) and the memory select bits
(MS2-0). The memory block programming bit allows users to program the entire connection memory in two frames
(see Memory Block Programming section). The memory select bits control the selection of the connection
memories or the data memories. See Table 9 on page 46 for content of the Control register.
The DMS register consists of the backplane and the local mode selection bits (BMS, LG41 - LG40, LG32 - LG30,
LG22 - LG20, LG12 - LG10 and LG02 - LG00) that are used to enable various switching modes for the backplane
and the local interfaces respectively. See Table 10 on page 47 for the content of the DMS register.
The BPM register consists of the block programming data bits (LBPD2-0 and BBPD2-0) and the block programming
enable bit (BPE). The block programming enable bit allows users to program the entire backplane and local
connection memories in two frames (see Memory Block Programming section). If the ODE pin is low, the backplane
CT-Bus is in input mode and the local output drivers are in high impedance state. If the ODE pin is high, all the
backplane CT-Bus and local ST-BUS output drivers are controlled on a per channel basis by backplane and local
connection memories, respectively. By programming BTM2 through BTM0 bits to “110” in the backplane connection
memory, the user can control the per-channel input on the backplane interface. For the local interface, users can
program LTM2 -0 bits to “110” in the local connection memory to control the per-channel high impedance output on
the local ST-BUS. See Table 11 on page 49 for the content of the BPM register.
24
Zarlink Semiconductor Inc.
MT90866
A13
(Note 1)
1
1
1
1
1
1
1
1
1
.
.
.
.
.
.
1
1
1
1
1
Data Sheet
Stream Address (ST0-31)
Channel Address (Ch0-255)
A12
A11
A10
A9
A8
Stream #
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
0
.
.
.
.
.
.
1
1
1
1
1
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
1
1
1
1
1
0
0
0
0
1
1
1
1
0
.
.
.
.
.
.
0
1
1
1
1
0
0
1
1
0
0
1
1
0
.
.
.
.
.
.
1
0
0
1
1
0
1
0
1
0
1
0
1
0
.
.
.
.
.
.
1
0
1
0
1
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
.
.
.
.
.
Stream 27
Stream 28
Stream 29
Stream 30
Stream 31
0
0
.
.
0
0
0
0
.
.
0
0
.
.
0
0
.
.
1
1
0
0
.
.
0
0
0
0
.
.
0
0
.
.
1
1
.
.
1
1
0
0
.
.
0
0
1
1
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
.
.
1
1
0
1
.
.
0
1
0
1
.
.
0
1
.
.
0
1
.
.
0
1
Channel #
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3 & 6)
.
.
Ch 126
Ch 127 (Note 4 & 7)
.
.
Ch 254
Ch 255 (Note 5)
Notes:
1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2 Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4 Mb/s.
4. Channels 0 to 127 are used when serial stream is at 8 Mb/s.
5. Channels 0 to 255 are used when serial stream is at 16 Mb/s.
6. Channels 0 to 63 are used when local serial stream is in 4-bit wide sub-rate switching mode.
7. Channels 0 to 127 are used when local serial stream is in 2-bit wide sub-rate switching mode.
Table 8 - Address Map for Memory Locations (A13 = 1)
12.0
Backplane Connection Memory
The backplane connection memory controls the switching configuration of the backplane interface. Locations in the
backplane connection memory are associated with particular STio streams.
The BTM2 - 0 bits of each backplane connection memory allows the per-channel selection for the message or the
connection mode, the constant or the variable delay mode, the high impedance control of the STio driver or the bit
error test enable. See Table 25 on page 63 for the content per-channel control function.
In the switching mode, the contents of the backplane connection memory stream address bits (BSAB4-0) and
channel address bits (BCAB7-0) define the source information (stream and channel) of the time slot that will be
switched to the backplane STio streams. During the message mode, only the lower 8 bits (8 least significant bits) of
the backplane connection memory will be transferred to the STio pins.
13.0
Local Connection Memory
The local connection memory controls the local interface switching configuration. Local connection memory is split
into a high and a low part. Locations in the local connection memory are associated with particular STo output
streams.
The LTM2 - 0 bits of each local connection memory low allows the per-channel selection for the message or the
connection mode, the constant or the variable delay mode, the high impedance control of the STo driver or the bit
error test enable. See Table 29 on page 65 for the content per-channel control function.
In the switching mode, the contents of the local connection memory low stream address bits (LSAB4-0) and the
channel address bits (LCAB7-0) of the local connection memory defines the source information (stream and
25
Zarlink Semiconductor Inc.
MT90866
Data Sheet
channel) of the time slot that will be switched to the local STo streams. During the message mode, only the lower 8
bits (8 least significant bits) of the local connection memory low bits are transferred to the STo pins.
In the sub-rate switching mode, although the output channels are divided up into 2 or 4-bit channels, the input
streams still have 8-bit channel boundaries. Therefore, it is necessary to indicate which bits in the input 8-bit
channel will be switched out to the 2 or 4-bit channel. When 2-bit or 4-bit sub-rate switching is enabled, the
LSRS1-0 bits in the local connection memory high define which bit positions contains the sub-rate data.
14.0
Bit Error Rate Test
The MT90866 offers users a Bit Error Rate (BER) test feature for the backplane and the local interfaces. The
circuitry of the BER test consists of a transmitter and a receiver on both interfaces that can transmit and receive the
BER patterns independently. The transmitter can output a pseudo random patterns of the form 215 - 1 to any
channel and any stream within a frame time. For the test, users can program the output channel and stream
through the backplane or local connection memory and the input channel and stream using Local or Backplane
BER Input Selection (BIS) registers. See Table 16 on page 54 and Table 18 on page 54 for the LBIS and the BBIS
registers contents, respectively.
The receiver receives the BER pattern and does an internal BER pattern comparison. For backplane interface, the
comparison result is stored in the Backplane BER register (BBERR). For local interface, the result is stored in the
Local BER register (LBERR).
15.0
External Tristate Control
The MT90866 has the flexibility to provide users with the choice of external per-channel tristate control. Two control
signals are provided. For the backplane interface, it is the BCSTo output. For the local interface, it is the LCSTo
output. Each control signal has a data rate of 32.768 Mb/s with 4,096 control bits per frame. Each bit position
corresponds to a specific output stream and channel location. When the control bit is high, the corresponding
output channel is in the high impedance state, whereas when the control bit is low, the corresponding output
channel has active output data.
15.1
BCSTo Control Stream
When the STio0-31 streams are in the 8 Mb/s mode, the STio0_Ch0 control bit of the BCSTo stream is advanced by
thirty-six C32/64o 32.768 Mb/s clock cycles from the backplane frame boundary. See Figure 6, "Backplane Control
(BCSTo) Timing when the STio data rate is 8 Mb/s" on page 26 for the BCSTo control bit pattern.
When the STio0-15 streams are in the 16 Mb/s mode, the STio0_Ch0 control bit of the BCSTo is advanced by
thirty-six C32/64o 32.768 Mb/s clock cycles from the backplane frame boundary. See Figure 7, "Backplane Control
(BCSTo) Timing when the STio data rate is 16 Mb/s" on page 27 for the BCSTo control bit pattern.
Frame
Boundary
Frame
Boundary
C8_A_io,
C8_B_io
c32o
STio22,Ch0
STio23,Ch0
STio24,Ch0
STio25,Ch0
STio26,Ch0
STio27,Ch0
STio28,Ch0
STio29,CH0
STio30,Ch0
STio31,Ch0
STio0,Ch1
STio1,Ch1
STio2,Ch1
STio3,Ch1
STio4,Ch1
STio5,Ch1
STio6,Ch1
STio7,Ch1
STio26,Ch125
STio27,Ch125
STio28,Ch125
STio29,Ch125
STio30,Ch126
STio31,Ch127
STio0,Ch0
STio1,Ch0
STio2,Ch0
STio3,Ch0
BCSTo0
(8 Mb/s Mode)
STio0,Ch1
STio1,Ch1
STio2,Ch1
STio3,Ch1
STio4,Ch1
STio5,Ch1
STio6,Ch1
STio7,Ch1
Thirty-six c32o cycles
Figure 6 - Backplane Control (BCSTo) Timing when the STio data rate is 8 Mb/s
26
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Frame
Boundary
C8_A_io,
CA_B_io
Frame
Boundary
c32o
STio6,Ch1
STio7,Ch1
STio8,Ch1
STio9,Ch1
STio10,Ch1
STio11,Ch1
STio12,Ch1
STio13,CH1
STio14,Ch1
STio15,Ch1
STio0,Ch2
STio1,Ch2
STio2,Ch2
STio3,Ch2
STio4,Ch2
STio5,Ch2
STio6,Ch2
STio7,Ch2
STio10,Ch250
STio11,Ch251
STio12,Ch252
STio13,Ch253
STio14,Ch254
STio15,Ch255
STio0,Ch0
STio1,Ch0
STio2,Ch0
STio3,Ch0
BCSTo0
(16 Mb/s Mode)
STio0,Ch2
STio1,Ch2
STio2,Ch2
STio3,Ch2
STio4,Ch2
STio5,Ch2
STio6,Ch2
STio7,Ch2
Thirty-six c32o cycles
Figure 7 - Backplane Control (BCSTo) Timing when the STio data rate is 16 Mb/s
15.2
LCSTo Control Stream
The LCSTo control bits are partitioned into 128 time slots, Slots 0 to 127. Each slot has 32 bits. Dummy bits
represent logic levels which should be ignored by the users. The first control bit in Slot 0 is advanced by thirty-two
C32/64o 32.768 Mb/s clock cycles from the frame boundary. See Figure 8, "Local Control (LCSTo) Timing when
STo0-18 are operated at 8 Mb/s" on page 28 for the partition of the time slots and the frame alignment details.
When the STo0-18 streams are operated at 8 Mb/s, Slots 0 to 127 are used to represent the control bits for
Channels 0 to 127 of the 8 Mb/s streams. STo19-17 are driven low in this configuration. See Figure 8, "Local
Control (LCSTo) Timing when STo0-18 are operated at 8 Mb/s" on page 28 for the LCSTo control bit pattern.
When the STo0-18 streams are operated at 4 Mb/s, Slots 2N (where N = 0 to 63) have the control bit pattern but
Slots 2N+1 have dummy bits which should be ignored by the user. STo19-17 are driven low in this configuration.
See Figure 9, "Local Control (LCSTo) Timing when STo0-18 are operated at 4 Mb/s" on page 29 for the LCSTo
control bit pattern.
When the STo0-27 streams are operated at 2 Mb/s, Slots 4N (where N = 0 to 31) have the control bit pattern, but
Slots 4N+1, 4N+2 and 4N+3 have dummy bits. See Figure 10, "Local Control (LCSTo) Timing when all STo0-27 are
operated at 2 Mb/s" on page 30 for the LCSTo control bit pattern.
When the STo streams are programmed with various data rates as described in Table 6 on page 20, the available
control bit positions in every time slot is associated with the corresponding output stream channels which operate at
various data rates. Figure 11, "Example of Local Control (LCSTo) Timing when the Local Streams have Different
Data Rates" on page 31 gives an example when STo0-3, 4-7, 8-11, 12-15, 16-27 are programmed to operate at
8 Mb/s, 4 Mb/s, 8 Mb/s, 4 Mb/s and 2 Mb/s respectively.
27
Zarlink Semiconductor Inc.
8Mb/s
8Mb/s
LCSTo0
Slot 127
Slot 2
Slot 1
Frame
Boundary
Slot 2
Slot 3
Slot 1
Slot 4
Slot 3
Figure 8 - Local Control (LCSTo) Timing when STo0-18 are operated at 8 Mb/s
Slot 0
Slot 0
Thirty-two
c32o cycles
Slot 0
Frame
Boundary
Ch0 STo0
Ch0 STo1
Ch0 STo2
Ch0 STo3
Ch0 STo4
Ch0 STo5
Ch0 STo6
Ch0 STo7
Ch0 STo8
Ch0 STo9
Ch0 STo10
Ch0 STo11
Ch0 STo12
Ch0 STo13
Ch0 STo14
Ch0 STo15
Ch0 STo16
Ch0 STo17
Ch0 STo18
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Ch1 STo0
Ch1 STo1
Ch1 STo2
Ch1 STo3
Ch1 STo4
Ch1 STo5
Ch1 STo6
Ch1 STo7
Ch1 STo8
Ch1 STo9
Ch1 STo10
Ch1 STo11
Ch1 STo12
Ch1 STo13
Ch1 STo14
Ch1 STo15
Ch1 STo16
Ch1 STo17
Ch1 STo18
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Frame
Boundary
Ch2 STo0
Ch2 STo1
Ch2 STo2
Ch2 STo3
Ch2 STo4
Ch2 STo5
Ch2 STo6
Ch2 STo7
Ch2 STo8
Ch2 STo9
Ch2 STo10
Ch2 STo11
Ch2 STo12
Ch2 STo13
Ch2 STo14
Ch2 STo15
Ch2 STo16
Ch2 STo17
Ch2 STo18
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Ch3 STo0
Ch3 STo1
Ch3 STo2
Ch3 STo3
Ch3 STo4
Ch3 STo5
Ch3 STo6
Ch3 STo7
Ch3 STo8
Ch3 STo9
Ch3 STo10
Ch3 STo11
Ch3 STo12
Ch3 STo13
Ch3 STo14
Ch3 STo15
Ch3 STo16
Ch3 STo17
Ch3 STo18
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Zarlink Semiconductor Inc.
28
MT90866
Data Sheet
4Mb/s
4Mb/s
LCSTo0
Slot 127
Slot 2
Slot 1
Frame
Boundary
Slot 2
Slot 3
Slot 1
Slot 4
Slot 3
Figure 9 - Local Control (LCSTo) Timing when STo0-18 are operated at 4 Mb/s
Slot 0
Slot 0
Thirty-two
c32o cycles
Slot 0
Frame
Boundary
Ch0 STo0
Ch0 STo1
Ch0 STo2
Ch0 STo3
Ch0 STo4
Ch0 STo5
Ch0 STo6
Ch0 STo7
Ch0 STo8
Ch0 STo9
Ch0 STo10
Ch0 STo11
Ch0 STo12
Ch0 STo13
Ch0 STo14
Ch0 STo15
Ch0 STo16
Ch0 STo17
Ch0 STo18
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
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Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Frame
Boundary
Ch1 STo0
Ch1 STo1
Ch1 STo2
Ch1 STo3
Ch1 STo4
Ch1 STo5
Ch1 STo6
Ch1 STo7
Ch1 STo8
Ch1 STo9
Ch1 STo10
Ch1 STo11
Ch1 STo12
Ch1 STo13
Ch1 STo14
Ch1 STo15
Ch1 STo16
Ch1 STo17
Ch1 STo18
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Zarlink Semiconductor Inc.
29
MT90866
Data Sheet
2Mb/s
2Mb/s
LCSTo0
Slot 127
Slot 2
Slot 1
Frame
Boundary
Slot 2
Slot 3
Slot 1
Slot 4
Slot 3
Figure 10 - Local Control (LCSTo) Timing when all STo0-27 are operated at 2 Mb/s
Slot 0
Slot 0
Thirty-two
c32o cycles
Slot 0
Frame
Boundary
Ch0 STo0
Ch0 STo1
Ch0 STo2
Ch0 STo3
Ch0 STo4
Ch0 STo5
Ch0 STo6
Ch0 STo7
Ch0 STo8
Ch0 STo9
Ch0 STo10
Ch0 STo11
Ch0 STo12
Ch0 STo13
Ch0 STo14
Ch0 STo15
Ch0 STo16
Ch0 STo17
Ch0 STo18
Ch0 STo19
Ch0 ST020
Ch0 STo21
Ch0 STo22
Ch0 STo23
Ch0 STo24
Ch0 STo25
Ch0 STo26
Ch0 STo27
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Frame
Boundary
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Zarlink Semiconductor Inc.
30
MT90866
Data Sheet
(8Mb/s)
(4Mb/s)
(4Mb/s)
Slot 2
(2Mb/s)
(2Mb/s)
Frame
Boundary
Slot 2
(8Mb/s)
(8Mb/s)
(4Mb/s)
Slot 3
(4Mb/s)
(8Mb/s)
(8Mb/s)
(4Mb/s)
(2Mb/s)
Slot 3
(4Mb/s)
Slot 1
Slot 4
(2Mb/s)
Slot 0
Figure 11 - Example of Local Control (LCSTo) Timing when the Local Streams have Different Data Rates
(4Mb/s)
(8Mb/s)
Slot 1
This drawing is used to illustrate the LCSTo control bit format with a specific data rate combination from different local data streams.
(8Mb/s)
(4Mb/s)
Slot 0
Slot 0
For this drawing, we assume that LSTo0-3, 4-7, 8-11, 12-15, 16-27 have data rates of 8Mb/s, 4Mb/s, 8Mb/s, 4Mb/s and 2Mb/s respectively.
(8Mb/s)
LCSTo0
Slot 127
Thirty-two
c32o cycles
Frame
Boundary
Ch0 STo0
Ch0 STo1
Ch0 STo2
Ch0 STo3
Ch0 STo4
Ch0 STo5
Ch0 STo6
Ch0 STo7
Ch0 STo8
Ch0 STo9
Ch0 STo10
Ch0 STo11
Ch0 STo12
Ch0 STo13
Ch0 STo14
Ch0 STo15
Ch0 STo16
Ch0 STo17
Ch0 STo18
Ch0 STo19
Ch0 ST020
Ch0 STo21
Ch0 STo22
Ch0 STo23
Ch0 STo24
Ch0 STo25
Ch0 STo26
Ch0 STo27
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Ch1 STo0
Ch1 STo1
Ch1 STo2
Ch1 STo3
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Ch1 STo8
Ch1 STo9
Ch1 STo10
Ch1 STo11
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Frame
Boundary
Ch2 STo0
Ch2 STo1
Ch2 STo2
Ch2 STo3
Ch1 STo4
Ch1 STo5
Ch1 STo6
Ch1 STo7
Ch2 STo8
Ch2 STo9
Ch2 STo10
Ch2 STo11
Ch1 STo12
Ch1 STo13
Ch1 STo14
Ch1 STo15
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Ch3 STo0
Ch3 STo1
Ch3 STo2
Ch3 STo3
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Ch3 STo8
Ch3 STo9
Ch3 STo10
Ch3 STo11
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Dummy Bit
Zarlink Semiconductor Inc.
31
MT90866
Data Sheet
MT90866
16.0
Data Sheet
DPLL
The Digital Phase Locked Loop (DPLL) accepts selectable 1.544 MHz, 2.048 MHz, or 8 kHz input reference
signals. It accepts reference inputs from independent sources and provides bit-error-free reference switching. The
DPLL meets phase slope and MTIE requirements defined by the Telcordia GR-1244-CORE standard.
The DPLL also provides the timing for the rest of the MT90866 Digital Switch, generating several network clocks
with the appropriate quality. Clocks are synchronized to one of two input reference clocks and meet the
requirements of the H.110 clock specification.
The master clock (CLK80M) for the DPLL is provided by the Analog Phase Locked Loop (APLL) from the MT90866
master clock input pin C20i. Since the APLL output is “locked” to the input, the accuracy of CLK80M clock is equal
to the accuracy of C20i.
16.1
MT90866 Modes of Operation
The DPLL, and consequently the MT90866, can, as required by the H.110 standard, operate in three different
modes: Primary Master, Secondary Master and Slave. See Figure 12, "Typical Timing Control Configuration" on
page 32.
To configure the DPLL, there are two Operation Mode registers: DOM1 and DOM2. See Table 20 on page 55 and
Table 21, "DPLL Operation Mode (DOM2) Register Bits" on page 58 for the contents of these registers.
In all modes the MT90866 monitors both the “A Clocks” (C8_A_io and FRAME_A_io) and the “B Clocks” (C8_B_io
and FRAME_B_io). The Fail_A and the Fail_B signals indicate the quality of the “A Clocks” and “B Clocks”
respectively.
CT_C8_A/CT_FRAME_A
CT_C8_B/CT_FRAME_B
CT_NETREF1
LREF0-7
LREF0-7
PRIMARY
MASTER
SLAVE
Network Ref
(8kHz / T1 / E1)
Network Ref
(8kHz / T1 / E1)
NREFo
B_Clocks
A_Clocks
NREFo
LREF0-7
SECONDARY
MASTER
Network Ref
(8kHz / T1 / E1)
B_Clocks
A_Clocks
CTREF2
CTREF1
B_Clocks
A_Clocks
CTREF2
CTREF1
B_Clocks
A_Clocks
CT_NETREF2
LREF0-7
SLAVE
Network Ref
(8kHz / T1 / E1)
Figure 12 - Typical Timing Control Configuration
16.1.1
Primary Master Mode
In the Primary Master Mode, the MT90866 drives the “A Clocks” (C8_A_io and FRAME_A_io), by locking to the
primary reference (PRI_REF). The PRI_REF can be provided by one of the locally derived network reference
sources (LREF0-7), or the CTREF1 input or the CTREF2 input. In this mode the MT90866 has the ability to monitor
the primary reference. If the primary reference becomes unreliable, the device continues driving “A Clocks” in
stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference
(SEC_REF) for its network timing. The secondary reference can be provided by one of the local network references
(LREF0-7), the CTREF1 or the CTREF2.
32
Zarlink Semiconductor Inc.
MT90866
Data Sheet
If the primary reference comes back or recovers, the MT90866 makes a Stratum 4 Enhanced compatible switch
back to the original primary reference and the system returns to normal operation state.
If necessary, the MT90866 can be prevented from switching back to the original primary reference by programming
the RPS bit in DOM1 register to give preference to the secondary reference.
While in the Primary Master mode, the MT90866 attenuates jitter and wander above 1.52 Hz from the selected
input reference clock and generates all output clocks according to the DPLL jitter transfer function diagram on
Figure 17, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on page 42 and Figure 18,
"Detailed DPLL Jitter Transfer Function Diagram" on page 43.
For the Primary Master mode selection, see Table 22, "MT90866 Mode Selection - By Programming DOM1 and
DOM2 Registers" on page 60.
16.1.2
Secondary Master Mode
In the Secondary Master Mode, the MT90866 drives the “B Clocks” (C8_B_io and FRAME_B_io), by locking to the
“A Clocks”. As required by the H.110 standard, the “B Clocks” are edge-synchronous with the “A Clocks”, as long as
jitter on the “A Clocks” meets Telcordia GR-1244-CORE specifications.
If the “A Clocks” become unreliable, system software is notified and the MT90866 continues driving the “B Clocks”
in stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the secondary reference
(SEC_REF) for its network timing. The secondary reference can be the local network reference (LREF0-7), the
CTREF1 or the CTREF2. If the “A Clocks” can not recover, the designated secondary master can be promoted to
primary master by system software. This promotion will cause the “B Clocks” to assume the role of the “A Clocks”.
For the Secondary Master mode selection, see Table 22, "MT90866 Mode Selection - By Programming DOM1 and
DOM2 Registers" on page 60.
16.1.3
Slave Mode
In the Slave Mode, the MT90866 is phase locked to the “A Clocks”. If the “A Clocks” become unreliable, the device
goes to stable Holdover Mode until it makes a Stratum 4 Enhanced compatible switch to the “B Clocks”. The
MT90866 will perform all required functionality as long as the “A Clocks” and the “B Clocks” conform to the
Telcordia GR-1244-CORE jitter specifications.
In addition, the device can be used to generate a CT reference (CT_REF1 or CT_REF2) from its network
references, LREF0-7.
While the device is in Slave Mode and the “A Clocks” or the “B Clocks” do not recover, then the designated slave
can be promoted to secondary master by system software. In that case, the network reference can be used as the
secondary reference.
Table 22 on page 60 shows how to program the DOM1 and DOM2 registers to enable the Slave mode of the
MT90866.
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Zarlink Semiconductor Inc.
MT90866
17.0
Data Sheet
DPLL Functional Description
HOLDOVER_RESET
(HRST bit in DOM2)
PHASE_OFFSET
(POS0-6 bits in DPOA)
MTIE_RESET
(MRST bit in DOM2)
SKEW_CONTROL
(SK0-2 bits in DPOA)
REF_SEL
(RPS bit in DOM1)
PRI
MUX
PRI_LOS Pin
C64
LOS_PRI
HOLDOVER
State
Machine
(Fig 16)
AUTODETECT
(Selected by FDM0-1 bits in DOM2)
SEC
MUX
SEC_LOS Pin
CT_C8
(C8_A_o)
MTIE_START
MTIE_DONE
PLL
(Fig 17)
C1M5o
LOS_SEC
CT_FRAME
(FRAME_A_o)
REF_SELECT
FREQ_MOD_PRI
(FP1-0 bits in DOM1)
FREQ_MOD_SEC
or
(C8_B_o)
or
(FRAME_B_o)
Frequency
FREQ_MOD
Mode
MUX
(FS1-0 bits in DOM1)
PRI_REF
(Selected by SP3-0 bits
in DOM1)
SEC_REF
Reference
Select
MUX
REF
(Selected by SS3-0 bits
in DOM1)
FRAME
FAIL_PRI
Reference
Monitor
C8_A_i
FRAME_A_i
FRAME_B_i
CLK80M
C20i
Frame
Select
MUX
Reference FAIL_SEC
Monitor
C8_B_i
CT Clock
and Frame
Monitor
FAIL_A
CT Clock
and Frame
Monitor
FAIL_B
APLL
Figure 13 - DPLL Functional Block Diagram
17.1
Reference Select and Frequency Mode MUX Circuits
The DPLL accepts two simultaneous reference input signals and operates on their rising edges. Either the primary
reference (PRI_REF) signal or the secondary reference (SEC_REF) signal can be selected to be the reference
signal (REF) to the PLL circuit. The appropriate frequency mode input (either FREQ_MOD_PRI or
FREQ_MOD_SEC) is selected to be the input of the PLL Circuit. The selection is done by the State Machine Circuit
based on the current state.
The FREQ_MOD_PRI and the FREQ_MOD_SEC are 2-bit wide inputs which reflect the value in the FP1-0 and
FS1-0 bits of the DOM1 register. The primary and the secondary references operate independently from each other
and can have different frequencies. Switching the reference from one frequency to another does not require the
device reset to be applied. Table 20 on page 55 shows input frequency selection for the primary and secondary
reference respectively.
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Zarlink Semiconductor Inc.
MT90866
17.2
Data Sheet
PRI and SEC MUX Circuits
The DPLL has four different modes to handle reference failure. These modes are selected by the FDM0 and FDM1
bits of the DOM2 Register. If FDM1-0 is ’10’ then the Primary reference is always used regardless of failures. If
FDM1-0 is ’11’ then the Secondary reference is always used regardless of failures. Otherwise the DPLL operates in
one of two failure detection modes: Autodetect or Manual detection mode. When the FDM0 and FDM1 bits are set
to low in the DOM2 register ‘00’, the DPLL is in the Autodetect Mode. In this mode, the outputs from the Reference
Monitor Circuits LOS_PRI and LOS_SEC are used by the State Machine Circuit. When the FDM0 bit is set to high
and FDM1 bit is set to low ‘01’, the DPLL is in the Manual Detection Mode and the LOS_PRI and LOS_SEC signals
are selected from the PRI_LOS and SEC_LOS input pins to be used by the State Machine Circuit. See Table 21 on
page 58 for selection of the Failure Detection Modes.
17.3
Frame Select MUX
When the “A Clocks” or the “B Clocks” are selected as the input reference, an 8.192 MHz clock (either C8_A_io or
C8_B_io) is provided to be the input reference to the PLL circuit (REF). Because the output frame pulse
(CT_FRAME) must be aligned with the selected input frame pulse, the appropriate frame pulse (either
FRAME_A_io or FRAME_B_io) is selected in the Frame Select MUX circuit to be the input of the PLL circuit
(FRAME).
17.4
CT Clock and Frame Monitor Circuits
The CT Clock and Frame Monitor circuits check the period of the C8_A_io and the C8_B_io clocks and the
FRAME_A_io and FRAME_B_io frame pulses. According to the H.110 specification, the C8 period is 122 ns with a
tolerance of +/- 35 ns measured between rising edges. If C8 falls outside the range of [87 ns,157 ns], the clock is
rejected and the fail signal (FAIL_A or FAIL_B) becomes high. The Frame pulse period is measured with respect to
the C8 clock. The frame pulse period must have exactly 1024 C8 cycles. Otherwise, the fail signal (FAIL_A or
FAIL_B) becomes high. When the CT BUS clock and frame pulse signals return to normal, the FAIL_A or FAIL_B
signal returns to logic low.
17.5
Reference Monitor Circuits
There are two Reference Monitor Circuits: one for the primary reference (PRI_REF) and one for the secondary
reference (SEC_REF). These two circuits monitor the selected input reference signals and detect failures by setting
up the appropriate fail outputs (FAIL_PRI and FAIL_SEC). These fail signals are used in the Autodetect mode as
the LOS_PRI and LOS_SEC signals to indicate when the reference has failed. The method of generating a failure
depends on the selected reference.
When the selected reference frequency is 8.192 MHz (“A Clocks” or “B Clocks”), the fail signals are passed through
from the CT Clock and Frame Monitor circuit outputs FAIL_A and FAIL_B, and used directly as FAIL_PRI and
FAIL_SEC, accordingly.
For all other reference frequencies (8 kHz, 1.544 MHz and 2.048 MHz), the following checks are performed:
•
For all references, the “minimum 90 ns” check is done. This is required by the H.110 specifications - both low
level and high level of the reference must last for minimum 90 ns each.
•
The “period in the specified range” check is done for all references. The length of the period of the selected
input reference is checked if it is in the specified range. For the E1 (2.048 MHz clock) or the T1 (1.544 MHz
clock) reference, the period of the clock can vary within the range of 1 +/- 1/4 of the defined clock period
which is 488 ns for the E1 clock and 648 ns for T1 clock. For the 8 KHz reference, the variation is from 1 +/1/32 period.
•
If the selected reference is E1 or T1, “64 periods in the specified range” check is done. The selected
reference is observed for a long period (64 reference clock cycles) and checked if it is within the specified
range - from 62 to 66 clock periods.
35
Zarlink Semiconductor Inc.
MT90866
Data Sheet
These reference signal verifications include a complete loss or a large frequency shift of the selected reference
signal. When the reference signal returns to normal, the LOS_PRI and LOS_SEC signals will return to logic low.
17.6
State Machine Circuit
The State Machine handles the reference selection. Depending on REF_SEL and LOS signals (selection between
FAIL_PRI and PRI_LOS and between FAIL_SEC and SEC_LOS), the state machine selects PRI_REF or
SEC_REF as the current input reference and dictates the PLL Circuit mode: Normal or Holdover Mode. In the
Normal Mode, the DPLL output clocks are locked to the selected input reference (PRI_REF or SEC_REF). In the
Holdover Mode, the DPLL clocks retain the phase and frequency values they had 32 to 64 ms prior to moving from
the Normal to the Holdover Mode. When going from the Holdover to the Normal Mode, the State Machine activates
the MTIE circuit and goes through the states MTIE PRI or MTIE SEC to prevent a phase shift of the output clocks
during the DPLL reference switch (from PRI_REF to SEC_REF and vice versa). The state diagram is given in
Figure 14, "State Machine Diagram" on page 36.
RESET Pin = 0
and xx0
Normal
PRI
Normal
0
SEC
0X0 or 011
100 or X01
MTIE
MTIE
4
1XX or X01
RESET Pin = 0
and xx1
0X0 or X1X
PRI
3
SEC
0x0 or
X11
1X0 or X01
100 or
X01
0x0 or
011
Holdover
PRI
7
100 or x01
0x0 or 011
2
Holdover
SEC
6
XXX = {LOS_PRI, LOS_SEC, REF_SEL}
Figure 14 - State Machine Diagram
18.0
Phase Locked Loop (PLL) Circuit
As shown in Figure 15, "Block Diagram of the PLL Module" on page 37, the PLL module consists of a Skew Control,
Maximum Time Interval Error (MTIE), Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop Filter,
Digitally Controlled Oscillator (DCO), Divider and Frequency Select MUX modules.
36
Zarlink Semiconductor Inc.
MT90866
HOLDOVER_RESET
MTIE_RESET
HOLDOVER
SKEW_CONTROL
PHASE_OFFSET
Skew
Control
(Fig 18)
REF_VIR
Phase
Detector
MTIE
MTIE_DONE
MTIE_START
REF
Data Sheet
C64
Phase
Offset
Adder
Phase
Slope
Limiter
Loop
Filter
CT_C8
Divider
DCO
C2M
C1M5o
CT_FRAME
FRAME
FREQ_MOD
Frequency
Select
MUX
FEEDBACK
Figure 15 - Block Diagram of the PLL Module
18.1
Skew Control
The circuit delays a selected reference input with a tapped delay line with seven taps - see Figure 16, "Skew
Control Circuit Diagram" on page 37. The maximum delay of the per unit delay element is factored at intervals of
3.5 ns. The tap is selected by the SKEW_CONTROL bus which is programmed by the SKC2-SKC0 bits of the
DPLL Output Adjustment (DPOA) register. The skew of this input will result in a static phase offset which varies
from 0 to 7 steps of the maximum delay per unit delay element, between the input and the outputs of the DPLL.
MUX
reference
input
delayed
reference
SKEW_CONTROL
Figure 16 - Skew Control Circuit Diagram
18.2
Maximum Time Interval Error (MTIE)
The MTIE circuit prevents any significant change in the output clock phase during a reference switch. Because the
input references can have any relationship between their phases and the output follows the selected input
reference, any switch from one reference to another could cause a large phase jump in the output clock if such a
circuit did not exist. This large phase jump could cause significant data loss. The MTIE circuit keeps the phase
difference between the output clock of the DPLL and the input reference the same as if the reference switch had not
taken place.
The MTIE circuit has two modes:
•
Measuring mode - the circuit measures the phase difference between the new reference from the Skew
Control circuit and the feedback signal (FEEDBACK) from the Frequency Select MUX circuit. This mode is
active during the movement of the DPLL from the Holdover to the Normal Mode, and is set by the
MTIE_START signal of the State machine module. The measured value is stored into a counter and used in
the Delay mode. When the measurement process is done, the State Machine module is notified by
generating the MTIE_DONE signal, allowing it to go to the Normal Mode.
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Zarlink Semiconductor Inc.
MT90866
•
Data Sheet
Delay mode - after the rising edge of the new reference clock from the Skew Control circuit, the MTIE circuit
uses the measured value to generate the virtual reference pulse (REF_VIR) to the Phase Detector circuit.
While the DPLL is in the Normal Mode, the MTIE Circuit is in Delay mode. It keeps the phase difference
between the output signals of the DPLL and selected input reference as the previous output signal would
have been if the reference switch had not taken place.
During a reference switch, the State Machine module first changes the mode of the DPLL from the Normal to the
Holdover Mode. In the Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates very
accurate outputs using storage techniques.
Because the input reference coming from the Skew Control circuit is asynchronous to the sampling clock used in
the MTIE circuit, a phase error may exist between the selected input reference signal and the output signal of the
DPLL. In the worst case, the Maximum Time Interval Error (MTIE) is one period of the internally used clock cycle
(65.536 MHz if the selected reference frequency is 8 kHz, 2.048 MHz and 8.192 MHz, and 49.408 MHz when the
selected reference frequency is 1.544 MHz). This phase error is a function of the difference in phase between the
two input reference signals during reference rearrangements. Each time a reference switch is made, the delay
between the input signal and the output signal can change. The value of this delay is the accumulation of the error
measured during each reference switch. After many switches from one reference to another, the delay between the
selected input reference and the DPLL output clocks can become unacceptably large. The user should provide
MTIE reset (set MRST bit in the DOM2 register to high) causing output clocks to align to the nearest edge of the
selected input reference. It is recommended that the MTIE is reset after multiple reference switchings and the
device falls back to its initial reference. The MTIE MUST be kept in the reset mode when the ZL50031 is operating
in the slave mode.
18.3
Phase Detector
The Phase Detector circuit compares the virtual reference signal from the MTIE Circuit (REF_VIR) with the
feedback signal from the Frequency Select MUX circuit (FEEDBACK) with respect to their rising edges, and
provides an error signal corresponding to the phase difference between the two. This error signal is passed to the
Phase Offset Adder Circuit. The Frequency Select MUX allows the proper feedback signal to be selected (e.g.,
8 kHz, 1.544 MHz, 2.048 MHz or 8.192 MHz).
18.4
Phase Offset Adder
The Phase Offset Adder Circuit adds the PHASE_OFFSET word (bits POS6-POS0 of the DPLL Output Adjustment
register - see Table 23 on page 61) to the error signal from the Phase Detector circuit to create the final phase error.
This value is passed to the Phase Slope Limiter circuit. The PHASE_OFFSET word can be positive or negative.
Since the PLL will stabilize to a situation where the average of the sum of the phase offset word and the phase
detector output is zero, a nonzero value in the input of the Phase Offset Adder circuit will result in a static phase
offset between the input and output signals of the DPLL.
If the selected input reference of the DPLL is either 8 KHz or 2.048 MHz, the step size in this static phase offset is
15.2 ns. With a 7-bit 2’s complement value, the static phase offset can be set between -0.96 µs and +0.97 µs. If the
selected input reference of the DPLL is 1.544 MHz, the maximum phase offset is between -1.27 µs and 1.29 µs
with a resolution of 20.2 ns.
Together with the Skew Control bits (SKC2-SKC0), users can program a static phase offset between -960 ns and
+990 ns if the selected input reference of the DPLL is either 8 kHz or 2.048 MHz. If the selected reference is
1.544 MHz, the programmable phase offset is between -1.27 µs and 1.30 µs. For the programmable ranges
mentioned above, the resolution is 1.9 ns per step. See Table 23 on page 61 for the content of the DPOA register.
When the selected input reference frequency of the DPLL is 8.192 MHz (“A Clocks” or “B Clocks” are selected as
the reference), the Phase Offset Adder is bypassed. The output of the Phase Detector circuit is connected directly
to the input of the Phase Slope Limiter circuit. When an 8.192 MHz clock (C8_A_io or C8_B_io) is used as the
reference in the Secondary Master or the Slave mode, the H.110 standard requires the output clock to always
follow the input reference on an edge-to-edge basis, so the static phase offset is not required.
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Zarlink Semiconductor Inc.
MT90866
18.5
Data Sheet
Phase Slope Limiter
The limiter receives the error signal from the Phase Offset Adder circuit and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 7.6 ns per 125 us. Because of this slope, the
MT90866 is within the maximum phase slope of 81 ns per 1.326 ms specified by the Telcordia GR-1244-CORE
standard.
The frequency stability of the Holdover Mode is ±0.07 ppm, which translates to a worst case 49 frame (125 µs) slips
in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of ±0.37 ppm (255 frame slips
per 24 hours).
18.6
Loop Filter
The Loop Filter circuit gives frequency offset to the DCO circuit, based on the phase difference between the input
and the feedback reference. It is similar to a first order low pass filter, with two positions for cut-off frequency (-3 dB
attenuation) depending on the selected reference frequency, and it mainly determines the jitter transfer function of
the DPLL.
In Primary Master mode when the selected input reference frequency is either 2.048 MHz, 1.544 MHz or 8 kHz, the
cut-off frequency is approximately at 1.52 Hz and all the reference variations, including jitter, are attenuated
according to the DPLL jitter transfer function (see Figure 17, "DPLL Jitter Transfer Function Diagram - wide range of
frequencies" on page 42 and Figure 18, "Detailed DPLL Jitter Transfer Function Diagram" on page 43). The Loop
Filter circuit ensures that the jitter transfer requirements in ETS 300-011 and Telecordia GR-499-CORE are met
when the selected reference frequency is either 2.048 MHz, 1.544 MHz or 8 kHz.
When the selected input reference frequency is 8.192 MHz (i.e., in Secondary Master or Slave modes), the
reference variations are bypassed to the output clocks. The cut-off frequency is at about 100 kHz, well beyond
500 Hz, the corner frequency of the Telcordia GR-1244-CORE input jitter tolerance curve.
The storage techniques, which enable generating very accurate output frequencies during the Holdover Mode of
DPLL, are built into the Loop Filter circuit. When no jitter is presented on the selected input reference, the holdover
frequency stability is 0.007 ppm.
18.7
Digitally Controlled Oscillator (DCO)
The DCO circuit adds frequency offset from the Loop Filter, which represents the phase error between the input and
the feedback reference, to the ideal center frequency value and generates appropriately corrected output high
speed clock. The Synchronization method of the DCO is dependent on the state of the DPLL State Machine
module.
In the Normal Mode, the DCO circuit provides an output signal which is frequency and phase locked to the selected
input reference signal.
In the Holdover Mode, the DCO circuit is running at a frequency that is equal to the frequency which was generated
by the DCO circuit when the DPLL was in the Normal Mode.
In the Freerun Mode, the DCO circuit is free running at its center frequency with an output accuracy equal to the
accuracy of the device master clock (C20i).
18.8
Divider
The Divider Circuit divides the DCO output frequency down to the required outputs. The following outputs are
generated:
•
C64 (65.536 MHz clock) - used as the internal clock for the MT90866 device.
•
CT_C8 (8.192 MHz clock), C2M (2.048 MHz clock), C1M5o (1.544 MHz clock) and CT_FRAME (8 kHz
negative frame pulse) - feedback reference signals to the Frequency Select MUX Circuit.
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
The CT_FRAME and the CT_C8 are required clocks. C1M5o is provided as an output clock of the MT90866.
The duty cycle of all output signals is independent of the duty cycle of the device master clock, C20i. The CT_C8,
C2M and C1M5o clocks have nominal 50% duty cycle,
The output frame pulse (CT_FRAME) is generated in such a way that it is always aligned with the CT_C8 clock to
form the required H.110 CT Bus clock and frame pulse shape (when the CT_FRAME is low the rising edge of the
CT_C8 defines the frame boundary). Depending on the selected input reference frequency, the CT_FRAME is
generated in the following way:
•
When the input reference frequency is 8 kHz, the output frame pulse is aligned with the rising edge of the
reference.
•
When the reference frequency is either 2.048 MHz or 1.544 MHz, the CT_FRAME randomly defines the
output frame boundary, always keeping the described relation to the CT_C8 clock.
•
When the reference frequency is 8.192 MHz, the output frame pulse (CT_FRAME) has to be aligned with the
input frame pulse (FRAME_A_io or FRAME_B_io). Since an 8.192 MHz clock (either C8_A_io or C8_B_io)
is used as the reference clock, the selected frame pulse from the Frame Select MUX is provided as the input
to the Divider circuit and the CT_FRAME is synchronized to it.
18.9
Frequency Select MUX Circuit
According to the selected input reference of the DPLL, this MUX will select the appropriate output frequency to be
the feedback signal to the PLL and MTIE Circuits.
18.10
Modes of Operation
The DPLL can operate in two main modes: the Normal and the Holdover Mode. Each of these modes has two
states: the primary or the secondary state. The state depends on which reference is currently selected as the
preferred reference the PRI_REF or the SEC_REF. When the DPLL is in the Holdover Mode and the HRST bit of
the DOM2 register is pulsed logic high (or held high continuously), the DPLL operates in Freerun Mode.
18.10.1
Normal Mode
Normal Mode is typically used when a clock source synchronized to the network is required.
In the Normal Mode, the DPLL provides timing (C64, CT_C8, C2M and C1M5o) and frame synchronization
(CT_FRAME) signals which are synchronized to one of two input references (PRI_REF or SEC_REF). The input
reference signal may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz or 8.192 MHz.
From a device reset condition or after reference switch, the DPLL can take up to 50 seconds to phase lock the
output signals to the selected input reference signal.
18.10.2
Holdover Mode
Holdover Mode is typically used for short durations while network synchronization is temporarily disrupted.
If the FDM1-0 bits are programmed to ‘01’ in the DOM2 register and the PRI_LOS and SEC_LOS pins are high, the
DPLL is in the Holdover Mode. The DPLL can also be in the Holdover Mode if the FDM1-0 bits are programmed to
‘00’ and the SLS and PLS bit are observed as ‘11’ in the DPLL House Keeping Register (DHKR).
In the Holdover Mode, the DPLL provides timing and synchronization signals which are based on storage
techniques and are not locked to an external reference signal. The storage value is determined while the device is
in Normal Mode and locked to an external reference signal. When the DPLL is in the Normal Mode and locks to the
input reference signal, a numerical value corresponding to the DPLL output reference frequency is stored
alternately in two memory locations every 32 ms. When the device is switched into the Holdover Mode, the value in
memory from between 32 ms and 64 ms is used to set the output frequency of the device.
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
The frequency stability of the Holdover Mode is ±0.07 ppm, which translates to a worst case 49 frame (125 µs) slips
in 24 hours.
Two factors affect the frequency stability of the Holdover Mode. The first factor is the drift on the frequency of the
master clock (C20i) while in the Holdover Mode. Drift on the master clock directly affects the Holdover Mode
stability. Note that the absolute master clock stability does not affect the Holdover Frequency stability, only the
change in C20i stability while in Holdover. For example, a ±32 ppm master clock may have a temperature
coefficient of ±0.1 ppm/ °C. So a 10 degree change in temperature, while the DPLL is in the Holdover Mode may
result in an additional offset (over the ±0.07 ppm) in frequency stability of ±1 ppm, which is much greater than the
±0.07 ppm of the DPLL. The second factor affecting Holdover frequency stability is large jitter on the reference input
prior to the mode switch.
18.10.3
Freerun Mode
When the DPLL is in the Holdover Mode and the HRST bit of the DOM2 register is pulsed logic high (or held high
continuously), the device is in Freerun Mode.
In Freerun Mode, the DPLL provides timing and synchronization signals which are based on the frequency of the
master clock (C20i) only, and are not synchronized to the reference input signals. The frequency of the output
signals is an ideal frequency with the freerun accuracy of -0.03 ppm plus the accuracy of the master clock (i.e.,
CT_C8 has frequency of 8.192 MHz +/- C20i_accuracy - 0.03 ppm).
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up
before network synchronization is achieved.
19.0
Measures of Performance
The following are some the DPLL performance indicators and their corresponding definitions.
19.1
Intrinsic Output Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, such as freerun or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the
applicable standards.
19.2
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards. The input jitter
tolerance of the DPLL depends on the selected reference frequency and can not exceed: ± 15 U.I. for E1 or T1
references, and ± 1 U.I. for 8 kHz references.
19.3
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
In slave and secondary master mode the H.110 standard requires the “B Clocks” to be edge-synchronous with the
“A Clocks”, as long as jitter on the “A Clocks” meets Telcordia GR-1244-CORE specifications. Therefore in these
two modes no jitter attenuation is performed
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
In primary master mode the jitter attenuation of the DPLL is determined by the internal 1.52 Hz low pass Loop Filter
and the Phase Slope Limiter. Figure 17, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on
page 42 shows the DPLL jitter transfer function diagram in a wide range of frequencies, while Figure 18, "Detailed
DPLL Jitter Transfer Function Diagram" on page 43 is the portion of the diagram from Figure 17 around 0 dB of the
jitter transfer amplitude. At this point it is possible to see that when operating in primary master mode the DPLL is a
second order, type 2 PLL. The jitter transfer function can be described as a low pass filter to 1.52 Hz,
-20 dB/decade, with peaking less then 0.5 dB.
All outputs are derived from the same signal, therefore these diagrams apply to all outputs. Since 1U.I. at
1.544 MHz (648 nsPP) is not equal to 1 U.I. at 2.048 MHz (488 nsPP). a transfer value using different input and
output frequencies must be calculated in common units (e.g., seconds) as shown in the following example:
What is the T1 and E1 output jitter when the T1 input jitter is 20 U.I. (T1 U.I. Units) and the T1 to T1 jitter attenuation
is 18 dB, for a given jittering frequency?
OutputT1 = InputT1 ×10
A
–----- 20
18
–------- 20
OutputT1 = 20 ×10
= 2.5UI ( T1 )
( 1UIT1 )
OutputE1 = OutputT1 × ---------------------( 1UIE1 )
( 644ns )
OutputE1 = OutputT1 × ------------------- = 3.3UI ( T1 )
( 488ns )
Using the method mentioned above, the jitter attenuation can be calculated for all combinations of inputs and
outputs.
Because intrinsic jitter is always present, the jitter attenuation will appear to be lower for small input jitter signals
than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input
jitter signals (e.g., 75% of the specified maximum jitter tolerance).
Figure 17 - DPLL Jitter Transfer Function Diagram - wide range of frequencies
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
Figure 18 - Detailed DPLL Jitter Transfer Function Diagram
19.4
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when the DPLL is not locked to
an external reference, but is operating in the Freerun Mode. Because the output of the DCO Circuit has only
discrete values, the output frequency of the DPLL has the limited accuracy of 0.03 ppm based upon the design
implementation. In addition, the master clock (C20i) accuracy also directly affects the freerun accuracy. The freerun
accuracy is then, 0.03 ppm plus the master clock accuracy.
19.5
Holdover Frequency Stability
Holdover frequency stability is defined as the maximum fractional frequency offset of an output clock signal when it
is operating using a stored frequency value. For the DPLL, the stored value is determined while the device is in
Normal Mode and locked to an external reference signal. As a result, when the DPLL is in the Normal Mode, the
stability of the master clock (C20i) does not affect the holdover frequency stability because the DPLL will
compensate for master clock changes while in Normal Mode. However, when the DPLL is in the Holdover Mode,
the stability of the master clock does affect the Holdover frequency stability. The holdover frequency stability is
0.07 ppm assuming that the C20i frequency is held constant.
19.6
Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is defined by the Loop Filter Circuit and is equal to +/- 298 ppm.
Note that the locking range is related to the master clock (C20i). If the master clock is shifted by -100 ppm, the
whole locking range also shifts -100 ppm downwards to be: -398 ppm to 198 ppm.
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Zarlink Semiconductor Inc.
MT90866
19.7
Data Sheet
Phase Slope
The phase slope or the phase alignment speed is the rate at which a given signal changes phase with respect to an
ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally
equal to the value of the final output signal or final input signal. Many telecom standards like Telcordia
GR-1244-CORE state that the phase slope may not exceed a certain value, usually 81 ns/1.327 ms (61 ppm). This
can be achieved by limiting the phase detector output to 61 ppm or less.
In the DPLL when operating in primary master mode the Phase Slope Limiter Circuit achieves the maximum phase
slope to be: 56 ppm or 7.0 ns/125 us. When operating in secondary master or slave mode the output edges follow
the input edges in accordance with the H.110 standard.
19.8
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
For the DPLL, the maximum time interval error is less than 21 ns per reference switch.
19.9
Phase Lock Time
The Phase Lock Time is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the
input and the output signals are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
i) initial input to output phase difference
ii) initial input to output frequency difference
iii) PLL loop filter
iv) PLL limiter
Although a short phase lock time is desirable, it is not always possible to achieve due to other PLL requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time, but better (smaller) phase slope performance (limiter) results in longer lock times. The DPLL loop filter and
limiter were optimized to meet the Telcordia GR-499-CORE jitter transfer and Telcordia GR-1244-CORE phase
alignment speed requirements. Consequently, phase lock time, which is not a standards requirement, is less than
50 seconds.
20.0
Initialization of the MT90866
During power up, the TRST pin should be pulled low to ensure that the MT90866 is in the functional mode. An
external pull-down resistor is required on this pin so that the MT90866 will not enter the JTAG test mode during
power up.
After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after
power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching
matrix. This procedure prevents two serial outputs from driving the same stream simultaneously. To ensure proper
operation, a delay of 600 µs must be applied before the first microprocessor access is performed after the RESET
pin is set high
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the switch. The memory block programming feature can also be used to quickly initialize the backplane and
local connection memories.
When this process is completed, the microprocessor controlling the MT90866 can bring the ODE pin high to
relinquish the high impedance state control.
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Zarlink Semiconductor Inc.
MT90866
21.0
Data Sheet
JTAG Support
The MT90866 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the
boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
21.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the MT90866 test functions. It consists of three input pins and one output pin
as follows:
•
•
•
•
•
Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any
on-chip clock and thus remains independent in the functional mode. The TCK permits shifting of test data
into or out of the Boundary-Scan register cells concurrently with the operation of the device and without
interfering with the on-chip logic.
Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Input (TDI) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDO) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDO. The data out of the
TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDO driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not
driven from an external source.
21.2
Instruction Register
The MT90866 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a
four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDI and TDO during data register scanning.
21.3
Test Data Register
As specified in IEEE 1149.1, the MT90866 JTAG Interface contains three test data registers:
•
•
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the MT90866 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDI to its TDO.
The Device Identification Register - The JTAG device ID for the MT90866 is 0086614BH.
Version:
0000
Part No. :
0000 1000 0110 0110
Manufacturer ID:
0001 0100 101
LSB:
1
21.4
BSDL
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149 test interface.
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Zarlink Semiconductor Inc.
MT90866
22.0
Data Sheet
Register Descriptions
Read/Write Address: 0000H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
STS3
STS2
STS1
STS0
PRST
CBEBB
SBERB
CBERL
SBERL
0
MBP
MS2
MS1
MS0
Bit
Name
Description
15-14
Unused
Reserved.
13-12
STS3-2
ST-BUS Frame Pulse and Clock Output Selection 1: These two bits are used to select
different ST-BUS output frame pulse (ST_FPo1) and clock (ST_CKo1).
STS3 STS2 ST_FPo1 Pulse Width
0
0
244 ns
0
1
122 ns
1
0
61 ns
11-10
STS1-0
ST_CKo1 Freq
4.096 MHz
8.192 MHz
16.384 MHz
ST-BUS Frame Pulse and Clock Output Selection 0: These two bits are used to select
different ST-BUS output frame pulse (ST_FPo0) and clock (ST_CKo0).
STS1 STS0 ST_FPo0 Pulse Width
ST_CKo0 Freq
0
0
244 ns
4.096 MHz
0
1
122 ns
8.192 MHz
1
0
61 ns
16.384 MHz
9
PRST
8
CBERB
Backplane Bit Error Rate Clear: A low to high transition of this bit will reset the
backplane internal bit error counter and the backplane BER register (BBERR).
7
SBERB
Backplane Start Bit Error Rate Test: A low to high transition in this bit starts the
backplane bit error rate test. The bit error test result is kept in the backplane BER register
(BBERR).
6
CBERL
Local Bit Error Rate Clear: A low to high transition of this bit will reset the local internal
bit error counter and the BER register (LBERR).
5
SBERL
Local Start Bit Error Rate Test: A low to high transition in this bit starts the local bit error
rate test. The bit error test result is kept in the local BER register (LBERR).
4
Unused
Reserved. In functional mode, this bit MUST be low.
3
MBP
PRBS Reset: When high, the PRBS transmitter output will be initialized.
Memory Block Programming: When this bit is high, the connection memory block
programming feature is ready for the programming of bit 13 to bit 15 of the backplane
connection memory and local connection memory low. When it is low this feature is
disabled.
Table 9 - Control Register (CR) Bits
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Zarlink Semiconductor Inc.
MT90866
Bit
Name
2-0
MS2-0
Data Sheet
Description
Memory Select Bits: These three bits are used to select different connection and data
memories.
MS2
MS11
MS0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
Memory Selection
Local Connection Memory Low
Read/Write
Local Connection Memory High
Read/Write
Backplane Connection Memory
Read/Write
Local Data Memory Read
Backplane Data Memory Read
Table 9 - Control Register (CR) Bits (continued)
Read/Write Address: 0001H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
BMS
LG41
LG40
LG32
LG31
LG30
LG22
LG21
LG20
LG12
LG11
LG10
LG02
LG01
LG00
Bit
Name
15
Unused
14
BMS
Description
Reserved.
Backplane Mode Select: This bit refers to the different mode for the backplane interface.
BMS
0
1
13-12
LG41-LG40
Local Group 4 Mode Select: These two bits refer to different switching mode for group
4(STi16-27 and STo16-27) of the local interface. When operating at 4Mb/s or 8Mb/s, the
STo19-27 are driven low.
LG41
0
0
1
11-9
LG32-LG30
Switching Mode Usable Streams
8 Mb/s
STio0 - 31
16 Mb/s
STio0 - 15
LG40 Switching Mode
Usable Streams
0
8 Mb/s
STi16-18, STo16-18
1
4 Mb/s
STi16-18, STo16-18
0
2 Mb/s
STi16-27, STo16-27
Local Group 3 Mode Select: These three bits refer to different switching mode for
group 3 (STi12-15 and STo12-15) of the local interface.
LG32
0
0
0
0
1
LG31
0
0
1
1
0
LG30
0
1
0
1
0
Switching Mode
8 Mb/s
4 Mb/s
2 Mb/s
4-bit wide subrate
2-bit wide subrate
Usable Streams
STi12-15, STo12-15
STi12-15, STo12-15
STi12-15, STo12-15
STi12-15, STo12-15
STi12-15, STo12-15
Table 10 - Device Mode Selection (DMS) Register Bits
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Zarlink Semiconductor Inc.
MT90866
Bit
Name
8-6
LG22-LG20
Description
Local Group 2 Mode Select: These three bits refer to different switching mode for
group 2 (STi8-11 and STo8-11) of the local interface.
LG22
0
0
0
0
1
5-3
LG12-LG10
LG02-LG00
LG21
0
0
1
1
0
LG20
0
1
0
1
0
Switching Mode
8 Mb/s
4 Mb/s
2 Mb/s
4-bit wide subrate
2-bit wide subrate
Usable Streams
STi8-11, STo8-11
STi8-11, STo8-11
STi8-11, STo8-11
STi8-11, STo8-11
STi8-11, STo8-11
Local Group 1 Mode Select: These three bits refer to different switching modes for
group 1 (STi4-7 and STo4-7) of the local interface.
LG12
0
0
0
0
1
2-0
Data Sheet
LG11
0
0
1
1
0
LG10
0
1
0
1
0
Switching Mode
8 Mb/s
4 Mb/s
2 Mb/s
4-bit wide subrate
2-bit wide subrate
Usable Streams
STi4-7, STo4-7
STi4-7, STo4-7
STi4-7, STo4-7
STi4-7, STo4-7
STi4-7, STo4-7
Local Group 0 Mode Select: These three bits refer to different switching modes for
group 0 (STi0-3 and STo0-3) of the local interface.
LG02
0
0
0
0
1
LG01
0
0
1
1
0
LG00
0
1
0
1
0
Switching Mode
8 Mb/s
4 Mb/s
2 Mb/s
4-bit wide subrate
2-bit wide subrate
Usable Streams
STi0-3, STo0-3
STi0-3, STo0-3
STi0-3, STo0-3
STi0-3, STo0-3
STi0-3, STo0-3
Table 10 - Device Mode Selection (DMS) Register Bits (continued)
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
Read/Write Address: 0002H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
BBPD2
BBPD1
BBPD0
LBPD2
LBPD1
LBPD0
BPE
0
0
Bit
Name
Description
15-9
Unused
8-6
BBPD2-0
Backplane Block Programming Data Bits: These bits carry the value to be loaded into
the backplane connection memory block whenever the Memory Block Programming feature
is activated. After the MBP bit in the control register is set to high and the BPE is set to high,
the contents of the bits BBPD2 - 0 are loaded into bits 15 - 13 of the backplane connection
memory. Bits 12 - 0 of the backplane connection memory are programmed to be zero.
5-3
LBPD2-0
Local Block Programming Data Bits: These bits carry the value to be loaded into the
local connection memory low whenever the Memory Block Programming feature is
activated. After the MBP bit in the control register is set to high and the BPE is set to high,
the contents of the bits LBPD2 - 0 are loaded into bits 15 - 13 of the local connection
memory low. Bits 12 - 0 of the local connection memory low and bits 15 - 0 of the local
connection memory high are programmed to be zero.
2
BPE
Block Programming Enable: A low to high transition of this bit enables the Memory Block
Programming function. The BPE, BBPD2-0 and LBPD2-0 in the BPM register have to be
defined in the same write operation. Once the BPE bit is set to high, MT90866 requires two
frames to complete the block programming. After the block programming has finished, the
BPE bit returns to low to indicate that the operation is complete. When BPE is high, BPE or
MBP can be set to low to abort the programming operation. When BPE is high, the other
bits in the BPM register must not be changed for two frames to ensure proper operation.
Reserved. In functional mode, these bits MUST be low.
Whenever the microprocessor writes BPE to be high to start the block programming
function, the user must maintain the same logical value on the other bits in the BPM register
to avoid any change in the setting of the device.
1-0
Unused
Reserved. In functional mode, these bits MUST be low.
Table 11 - Block Programming Mode (BPM) Register Bits
49
Zarlink Semiconductor Inc.
MT90866
Read/Write Addresses:
0004H for LIDR0 register,
0006H for LIDR2 register,
0008H for LIDR4 register,
000AH for LIDR6 register,
000CH for LIDR8 register,
Data Sheet
0005H for LIDR1 register,
0007H for LIDR3 register,
0009H for LIDR5 register,
000BH for LIDR7 register,
000DH for LIDR9 register,
Reset Value: 0000H
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LIDR0 0
15
LID24
LID23
LID22
LID21
LID20
LID14
LID13
LID12
LID11
LID10
LID04
LID03
LID02
LID01
LID00
LIDR1 0
LID54
LID53
LID52
LID51
LID50
LID44
LID43
LID42
LID41
LID40
LID34
LID33
LID32
LID31
LID30
LIDR2 0
LID84
LID83
LID82
LID81
LID80
LID74
LID73
LID72
LID71
LID70
LID64
LID63
LID62
LID61
LID60
LIDR3 0
LID114
LID113
LID112
LID111
LID110
LID104
LID103
LID102
LID101
LID100
LID94
LID93
LID92
LID91
LID90
LIDR4 0
LID144
LID143
LID142
LID141
LID140
LID134
LID133
LID132
LID131
LID130
LID124
LID123
LID122
LID121
LID120
LIDR5 0
LID174
LID173
LID172
LID171
LID170
LID164
LID163
LID162
LID161
LID160
LID154
LID153
LID152
LID151
LID150
LIDR6 0
LID204
LID203
LID202
LID201
LID200
LID194
LID193
LID192
LID191
LID190
LID184
LID183
LID182
LID181
LID180
LIDR7 0
LID234
LID233
LID232
LID231
LID230
LID224
LID223
LID222
LID221
LID220
LID214
LID213
LID212
LID211
LID210
LIDR8 0
LID264
LID263
LID262
LID261
LID260
LID254
LID253
LID252
LID251
LID250
LID244
LID243
LID242
LID241
LID240
LIDR9 0
0
0
0
0
0
0
0
0
0
0
LID274
LID273
LID272
LID271
LID270
Name
Description
LIDn4, LIDn3,
LIDn2, LIDn1,
LIDn0
(See Note 1)
Local Input Delay Bits 4 - 0: These five bits define how long the serial interface receiver
takes to recognize and to store bit 0 from the STi input pins: i.e., to start a new frame.
The input delay can be selected to +7.75 data rate clock periods from the frame
boundary.
Note 1: n denotes an STi stream number from 0 to 27.
Table 12 - Local Input Bit Delay Registers (LIDR0 to LIDR9) Bits
50
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Corresponding Delay Bits
Local Input Bit Delay
LIDn4
LIDn3
LIDn2
LIDn1
LIDn0
No clock period shift (Default)
0
0
0
0
0
+ 1/4 data rate clock period
0
0
0
0
1
+ 1/2 data rate clock period
0
0
0
1
0
+ 3/4 data rate clock period
0
0
0
1
1
+ 1 data rate clock period
0
0
1
0
0
+ 1 1/4 data rate clock period
0
0
1
0
1
+ 1 1/2 data rate clock period
0
0
1
1
0
+ 1 3/4 data rate clock period
0
0
1
1
1
+ 2 data rate clock period
0
1
0
0
0
1
1
..........
...........
+ 7 3/4 data rate clock period
1
1
1
Table 13 - Local Input Bit Delay Programming
ST_FPo0/1
input data
input data
input data
input data
Bit Delay 0
LID=00000
bit7
Bit Delay 1/4
LID=00001
bit7
Bit Delay 1/2
LID=00010
bit7
Bit Delay 3/4
LID=00011
bit7
input data
Bit Delay 1
LID=00100
bit7
input data
bit7
Figure 19 - Local Input Bit Delay Timing
51
Zarlink Semiconductor Inc.
Bit Delay 1 1/2
LID=00101
MT90866
Read/Write Addresses:
001CH for BOAR0 register,
001EH for BOAR2 register,
0000H for all BOAR registers.
Reset value:
Data Sheet
001DH for BOAR1 register,
001FH for BOAR3 register,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BOAR0
BOA
71
BOA
70
BOA
61
BOA
60
BOA
51
BOA
50
BOA
41
BOA
40
BOA
31
BOA
30
BOA
21
BOA
20
BOA
11
BOA
10
BOA
01
BOA
00
BOAR1
BOA
151
BOA
150
BOA
141
BOA
140
BOA
131
BOA
130
BOA
121
BOA
120
BOA
111
BOA
110
BOA
101
BOA
100
BOA
91
BOA
90
BOA
81
BOA
80
BOAR2
BOA
231
BOA
230
BOA
221
BOA
220
BOA
211
BOA
210
BOA
201
BOA
200
BOA
191
BOA
190
BOA
181
BOA
180
BOA
171
BOA
170
BOA
161
BOA
160
BOAR3
BOA
311
BOA
310
BOA
301
BOA
300
BOA
291
BOA
290
BOA
281
BOA
280
BOA
271
BOA
270
BOA
271
BOA
260
BOA
251
BOA
250
BOA
241
BOA
240
Name)
BOAn1, BOAn0
(See Note 1)
Description
Backplane Output Advancement Bits 1 - 0: These two bits represent the amount of
offset that a particular stream output can be advanced. When the offset is zero, the
serial output stream has normal alignment with the frame pulse.
BOAn1
BOAn0
Output
Advancement
C8_A_io
or C8_B_io
period
8.192 Mb/s
(bit)
16.384 Mb/s
(bit)
0
0
0 ns
0
0
0
0
1
7.5 ns
- 1/16
- 1/16
- 1/8
1
0
15 ns
- 1/8
- 1/8
- 1/4
1
1
22.5 ns
- 3/16
- 3/16
- 3/8
Note 1: n denotes a STio stream number from 0 to 31.
Table 14 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit
FRAME_A_io
or FRAME_B_io
C64
(internal clock)
8 Mb/s Stream
8 Mb/s Stream
8 Mb/s Stream
8 Mb/s Stream
advancement is 0ns
BOA=00
Bit 7
advancement is 7.5 ns
BOA=01
Bit 7
advancement is 15 ns
BOA=10
Bit 7
Bit 7
denotes the starting point of the bit cell
advancement is 22.5 ns
BOA=11
Figure 20 - Example of Backplane Output Advancement Timing
52
Zarlink Semiconductor Inc.
MT90866
Read/Write Addresses:
0020H for LOAR0 register,
0022H for LOAR2 register,
0000H for all LOAR registers.
Reset value:
15
14
13
Data Sheet
12
11
10
9
8
7
6
0021H for LOAR1 register,
0023H for LOAR3 register,
5
4
3
2
1
0
LOAR0 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA
71
70
61
60
51
50
41
40
31
30
21
20
11
10
01
00
LOAR1 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA
151 150 141 140 131 130 121 120 111 110 101 100 91
90
81
80
LOAR2 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA
231 230 221 220 211 210 201 200 191 190 181 180 171 170 161 160
LOAR3
0
0
0
0
0
0
0
0
LOA LOA LOA LOA LOA LOA LOA LOA
271 270 271 260 251 250 241 240
Name
Description
LOAn1,
LOAn0
(See Note 1)
Local Output Advancement Bits 1-0: These two bits represent the amount of offset
that a particular stream output can be advanced. When the offset is zero, the serial
output stream has normal alignment with the frame pulse.
LOAn1
LOAn0
Output
Advancement
C8_A_io
or C8_B_io
period
0
0
0 ns
0
0
0
0
0
1
- 7.5 ns
- 1/16
- 1/64
- 1/32
- 1/16
1
0
- 15 ns
- 1/8
- 1/32
- 1/16
- 1/8
1
1
- 22.5 ns
- 3/16
- 3/64
- 3/32
- 3/16
2.048 Mb/s
(bit)
4.096M b/s
(bit)
8.192 Mb/s
(bit)
Note 1: n denotes a STi stream number from 0 to 27.
Table 15 - Local Output Advancement Registers (LOAR0 to LOAR3) Bits
ST_FPo0/1
C64
(internal clock)
8 Mb/s Stream
8 Mb/s Stream
8 Mb/s Stream
8 Mb/s Stream
advancement is 0 ns
LOA=00
Bit 7
advancement is 7.5 ns
LOA=01
Bit 7
advancement is 15 ns
LOA=10
Bit 7
Bit 7
denotes the starting point of the bit cell
Figure 21 - Local Output Advancement Timing
53
Zarlink Semiconductor Inc.
advancement is 22.5 ns
LOA=11
MT90866
Data Sheet
Read/Write Address: 0027H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
LBS
A4
LBS
A3
LBS
A2
LBS
A1
LBS
A0
LBC
A7
LBC
A6
LBC
A5
LBC
A4
LBC
A3
LBC
A2
LBC
A1
LBC
A0
Bit
Name
Description
15 - 13
Unused
12 - 8
LBSA4 - LBSA0
Local BER Input Stream Address Bits: These bits refer to the local input data
stream which receives the BER data.
7-0
LBCA7 - LBCA0
Local BER Input Channel Address Bits: These bits refer to the local input
channel which receives the BER data.
Reserved.
Table 16 - Local Bit Error Rate Input Selection (LBIS) Register Bits
Read Address: 0028H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBER
15
LBER
14
LBER
13
LBER
12
LBER
11
LBER
10
LBER
9
LBER
8
LBER
7
LBER
6
LBER
5
LBER
4
LBER
3
LBER
2
LBER
1
LBER
0
Bit
Name
Description
15 - 0
LBER15 - LBER0
Local Bit Error Rate Count Bits: These bits refer to the local bit error counts.
This counter stops incrementing when it reaches the value 0xFFFF.
Table 17 - Local Bit Error Rate Register (LBERR) Bits
Read/Write Address: 0029H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
BBSA
4
BBSA
3
BBSA
2
BBSA
1
BBSA
0
BBCA
7
BBCA
6
BBCA
5
BBCA
4
BBCA
3
BBCA
2
BBCA
1
BBCA
0
Bit
Name
Description
15 - 13
Unused
12 - 8
BBSA4 - BBSA0
Backplane BER Input Stream Address Bits: These bits refer to the backplane
input data stream which receives the BER data.
7-0
BBCA7 - BBCA0
Backplane BER Input Channel Address Bits: These bits refer to the
backplane input channel which receives the BER data.
Reserved.
Table 18 - Backplane Bit Error Rate Input Selection (BBIS) Register Bits
54
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Read Address: 002AH
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBER
15
BBER
14
BBER
13
BBER
12
BBER
11
BBER
10
BBER
9
BBER
8
BBER
7
BBER
6
BBER
5
BBER
4
BBER
3
BBER
2
BBER
1
BBER
0
Bit
Name
Description
15 - 0
BBER15 -BBER0
Backplane Bit Error Rate Count Bits: These bits refer to the backplane bit
error count. This counter stops incrementing when it reaches the value 0xFFFF.
Table 19 - Backplane Bit Error Rate Register (BBERR) Bits
Read/Write Address: 002BH for DOM1 Register
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNEN
BEN
AEN
RPS
FS1
FS0
FP1
FP0
SS3
SS2
SS1
SS0
SP3
SP2
SP1
SP0
Bit
Name
15
CNEN
14
BEN
Description
NREFo Output Enable Bit: When CNEN is low, NREFo output is disabled, i.e. tri-stated.
When CNEN is high, NREFo output is enabled.
B Clocks Output Enable Bit: When BEN is low, the “B Clocks” (C8_B_io and FRAME_B_io)
are disabled, i.e. tri-stated - C8_B_io and FRAME_B_io behave as inputs.
When BEN is high, the “B Clocks” are enabled - C8_B_io and FRAME_B_io behave as
outputs.
13
AEN
A Clocks Output Enable Bit: When AEN is low, the “A Clocks” (C8_A_io and FRAME_A_io)
are disabled, i.e. tri-stated - C8_A_io and FRAME_A_io behave as inputs.
When AEN is high, the “A Clocks” are enabled - C8_A_io and FRAME_A_io behave as
outputs.
12
RPS
Reference Selection Bit: When RPS is low, the preferred reference is the primary reference
(PRI_REF). When RPS is high, the preferred reference is the secondary reference
(SEC_REF).
11 - 10 FS1 - FS0 SEC_REF Frequency Selection Bits: These bits are used to select different clock
frequencies for the secondary reference.
FS1
FS0
Secondary Reference
0
0
8 kHz
0
1
1.544 MHz
1
0
2.048 MHz
1
1
8.192 MHz (“A Clocks” or “B Clocks”)
Table 20 - DPLL Operation Mode (DOM1) Register Bits
55
Zarlink Semiconductor Inc.
MT90866
Bit
9-8
Name
Description
FP1 - FP0 PRI_REF Frequency Selection Bits: These bits are used to select different clock
frequencies for the primary reference.
FS1
7-4
Data Sheet
FS0
Primary Reference
0
0
8 kHz
0
1
1.544 MHz
1
0
2.048 MHz
1
1
8.192 MHz (“A Clocks” or “B
Clocks”)
SS3 - SS0 Secondary Clock Reference Input Selection Bits: These bits are used to select secondary
reference input.
SS3 - SS0
Secondary Clock Reference Input
0000
CTREF1
0001
CTREF2
0010
“A Clocks”
0011
“B Clocks”
0100
Reserved
0101
Reserved
0110
Reserved
0111
Reserved
1000
LREF0
1001
LREF1
1010
LREF2
1011
LREF3
1100
LREF4
1101
LREF5
1110
LREF6
1111
LREF7
Table 20 - DPLL Operation Mode (DOM1) Register Bits (continued)
56
Zarlink Semiconductor Inc.
MT90866
Bit
3-0
Name
Data Sheet
Description
SP3 - SP0 Primary Clock Reference Input Selection Bits: These bits are used to select primary
reference input.
SP3 - SS0
Primary Clock Reference Input
0000
CTREF1
0001
CTREF2
0010
“A Clocks”
0011
“B Clocks”
0100
Reserved
0101
Reserved
0110
Reserved
0111
Reserved
1000
LREF0
1001
LREF1
1010
LREF2
1011
LREF3
1100
LREF4
1101
LREF5
1110
LREF6
1111
LREF7
Table 20 - DPLL Operation Mode (DOM1) Register Bits (continued)
57
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Read/Write Address: 002CH for DOM2 Register
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
HRST
MRST
FDM1
FDM0
BFEN
AFEN
CNIN
DIV1
DIV0
CNS2
CNS1
CNS0
Bit
Name
Description
15 - 12
Unused
11
HRST
DPLL Hold Memory Reset Bit: When HRST is low, the DPLL hold memory
circuit is in functional mode. When HRST is high, the hold memory circuit will be
reset. While the DPLL is in Holdover Mode, pulsing HRST high (or holding it high
continuously) will force the DPLL to the Freerun Mode.
10
MRST
MTIE Reset Bit: When MRST is low, the DPLL MTIE circuit is in functional mode.
When MRST is high, the MTIE circuit will be reset - the DPLL outputs will align
with the nearest edge of the selected reference. When the MT90866 is operating
in the slave mode, this bit MUST be set high to reset the MTIE circuit.
9-8
FDM1 FDM0
Failure Detect Mode Bits: These two bits control how to choose the Failure
Detection.
Reserved.
FDM1
FDM0
Failure Detection Mode
0
0
Autodetect - Automatic Failure Detection by internal reference monitor circuit
0
1
External - Failure Detection controlled by external inputs
(PRI_LOS and SEC_LOS)
1
0
Forced Primary - The DPLL is forced to use primary reference
1
1
Forced Secondary - The DPLL is forced to use secondary
reference
7
BFEN
B Clocks Fail Output Enable Bit: When BFEN is low, FAIL_B output is disabled,
i.e., tri-stated. When BFEN is high, FAIL_B output is enabled.
6
AFEN
A Clocks Fail Output Enable Bit: When AFEN is low, FAIL_A output is disabled,
i.e., tri-stated. When AFEN is high, FAIL_A output is enabled.
5
CNIN
CTREF1 andCTREF2 Inputs Inverted: When CNIN is high, the CTREF1 and
CTREF2 inputs will be inverted, prior to entering the DPLL module. When CNIN is
low, the CTREF1 and CTREF2 inputs will not be inverted.
Table 21 - DPLL Operation Mode (DOM2) Register Bits
58
Zarlink Semiconductor Inc.
MT90866
Bit
Name
4 -3
DIV1 - DIV0
2-0
CNS2 - CNS0
Data Sheet
Description
Divider Bits: These two bits define the relationship between the input reference
and the NREFo output.
DIV1
DIV0
NREFo Output
0
0
Input reference
0
1
Input reference/193 (8 KHz signal when input
reference clock = 1.544 MHz)
1
0
Input reference/256 (8 KHz signal when input
reference clock = 2.048 MHz)
1
1
Reserved
NREFo Source Selection Bits: These three bits select one of the LREF7 LREF0 to be the NREFo source.
CNS2
CNS1
CNS0
NREFo Source
0
0
0
LREF0
0
0
1
LREF1
0
1
0
LREF2
0
1
1
LREF3
1
0
0
LREF4
1
0
1
LREF5
1
1
0
LREF6
1
1
1
LREF7
Table 21 - DPLL Operation Mode (DOM2) Register Bits (continued)
59
Zarlink Semiconductor Inc.
MT90866
DOM1
register Bits
Bit
Secondary Master Mode
Slave Mode
BEN (bit 14)
0 - Monitor “B Clocks”
1 - Drive “B Clocks”
0 - Monitor “B Clocks”
AEN (bit 13)
1 - Drive “A Clocks”
0 - Monitor “A Clocks”
0 - Monitor “A Clocks”
RPS (bit 12)
0 - Preferred reference is
PRI_REF
0 - Preferred reference is
PRI_REF
0 - Preferred reference is
PRI_REF
FS1-0
(bits 11-10)
Frequency of the
secondary
reference
00 - 8 kHz
01 - 1.544 MHz
10 - 2.048 MHz
00 - 8 kHz
01 - 1.544 MHz
10 - 2.048 MHz
11 - 8.192 MHz Clock
(“B Clocks”)
FP1-0
(bits 9-8)
Frequency of the
primary
reference
00 - 8 kHz
01 - 1.544 MHz
10 - 2.048 MHz
11 - 8.192 MHz Clock
(“A Clocks”)
11 - 8.192 MHz Clock
(“A Clocks”)
SS3-0
(bits 7-4)
0000 - CTREF1
0001 - CTREF2
1000 - LREF0
1001 - LREF1
1010 - LREF2
1011 - LREF3
1100 - LREF4
1101 - LREF5
1110 - LREF6
1111 - LREF7
0000 - CTREF1
0001 - CTREF2
1000 - LREF0
1001 - LREF1
1010 - LREF2
1011 - LREF3
1100 - LREF4
1101 - LREF5
1110 - LREF6
1111 - LREF7
XXXX - C8_B_io
When bits FS1-0 are set to 11,
C8_B_io is always used as the
secondary reference,
regardless of the values of bits
SS3-0. Output frame pulses
are aligned to FRAME_B_io if
secondary reference is the
active reference
0000 - CTREF1
0001 - CTREF2
1000 - LREF0
1001 - LREF1
1010 - LREF2
1011 - LREF3
1100 - LREF4
1101 - LREF5
1110 - LREF6
1111 - LREF7
XXXX - C8_A_io
When bits FP1-0 are set to 11,
C8_A_io is always used as the
primary reference, regardless
of the values of bits SP3-0.
Output frame pulses are
aligned to FRAME_A_io if
primary reference is the active
reference
XXXX - C8_A_io
When bits FP1-0 are set to 11,
C8_A_io is always used as the
primary reference, regardless
of the values of bits SP3-0.
Output frame pulses are
aligned to FRAME_A_io if
primary reference is the active
reference
0 - MTIE functional
1 - MTIE reset
0 - MTIE functional
1 - MTIE reset
1 - MTIE MUST be kept in the
reset state in Slave mode
00 - Autodetect Mode
00 - Autodetect Mode
01 - External Mode
00 - Autodetect Mode
01 - External Mode
(Note 1)
(Note 1)
Secondary
reference
selection:
SP3-0
(bits 3-0)
Primary
reference
selection:
MRST (bit 10)
DOM 2
Register Bits
Primary Master
Mode
Data Sheet
FDM1, FDM0
(bits 9-8)
Failure detect
mode selection
* Note 1: It is assumed that the switching among references is done by an external software control, if the External Mode is
selected.
Table 22 - MT90866 Mode Selection - By Programming DOM1 and DOM2 Registers
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
Read/Write Address: 002DH for DPOA Register
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POS
6
POS
5
POS
4
POS
3
POS
2
POS
1
POS
0
0
0
0
0
0
0
SKC2
SKC1
SKC0
Bit
Name
Description
15 - 9
POS6 - POS0
8-3
2-0
Unused
SKC2 - SKC0
Phase Offset Bits: These seven bits refer to the 2’s complement phase word to
control the DPLL output phase offset. The offset varies in steps of 15 ns if the
reference is 8 kHz or 2.048 MHz. The offset varies in steps of 20 ns if the reference
is 1.544 MHz.
Reserved.
Skew Control Bits: These three bits control the delay of the DPLL outputs from 0
to 7 steps in interval of maximum unit delay of 3.5 ns.
Table 23 - DPLL Output Adjustment (DPOA) Register Bits
Read/Write Address: 002EH for DHKR Register
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SLS
PLS
CKM
Limit
State 2
State 1
State 0
Bit
Name
Description
15 - 7
6
Unused
SLS
5
PLS
4
CKM
3
Limit
Reserved.
Secondary Loss Detection Bit (Read-only bit): This bit is the same as the output
from the DPLL Reference Monitor FAIL_SEC.
Primary Loss Detection Bit (Read-only bit): This bit is the same as the output from
the DPLL Reference Monitor FAIL_PRI.
DPLL Clock Monitor Bit: When high, the primary output C32/64o is 65.536 MHz clock.
When low, the primary output C32/64o is 32.768 MHz clock. This is the only writable bit
in this register.
Limit (Read-only bit): Indicates that DPLL Phase Slope limiter limits input phase.
Table 24 - DPLL House Keeping (DHKR) Register Bits
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Zarlink Semiconductor Inc.
MT90866
2-0
State
Data Sheet
State: These 3 bits indicate the state of the DPLL State Machine. Please refer to Figure
14, "State Machine Diagram" on page 36.
State 2-0
State Name
000
NORMAL_PRI
001
Reserved
010
HOLDOVER_PRI
011
MTIE_PRI
100
NORMAL_SEC
101
Reserved
110
HOLDOVER_SEC
111
MTIE_SEC
Table 24 - DPLL House Keeping (DHKR) Register Bits (continued)
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BTM
2
BTM
1
BTM
0
BSAB
4
BSAB
3
BSAB
2
BSAB
1
BSAB
0
BCA
B7
BCA
B6
BCA
B5
BCA
B4
BCA
B3
BCA
B2
BCA
B1
BCA
B0
Bit
Name
Description
15 -13
BTM2 - 0
Throughput Delay and Message Control Bits: These three bits control the backplane
CT-Bus input or output.
BTM2-0
000
001
010
011
100
101
BTM1
BTM0
Input Source
BTM2
110
111
Throughput delay and Message Mode control
Per-channel variable delay from local interface; the content of the connection
memory is the local data memory address of the switched input channel
and stream. The backplane CT-Bus output is from local ST-BUS input.
Per-channel constant delay from local interface; the content of the connection
memory is the local data memory address of the switched input channel
and stream. The backplane CT-Bus output is from local ST-BUS input.
Per-channel variable delay from backplane interface; the content of the
connection memory is the backplane data memory address of the switched
input channel and stream. The backplane CT-Bus output is from backplane
CT-Bus input.
Per-channel constant delay from backplane interface; the content of the
connection memory is the backplane data memory address of the switched
input channel and stream. The backplane CT-Bus output is from backplane
CT-Bus input.
Per-channel message mode; only the lower byte (bits 7 to 0) of the
connection memory location will be the presented to the backplane CT-Bus
output channel.
Per-channel BER pattern; the pseudo random BER test pattern will be
presented to the backplane CT-Bus output channel.
Per-channel input. The backplane CT-Bus is input.
Reserved.
0
0
0
x
0
0
1
x
0
1
0
x
0
1
1
x
1
0
0
1
0
1
1
1
0
1
1
1
Local
Backplane
Var.
delay
Const.
delay
Msg
Mode
BER
I/O HiZ
x
x
x
x
x
x
x
Reserved
12 - 8
BSAB4 - BSAB0
Source Stream Address Bits: These five bits refer to the number of the data streams
for the source (local or backplane) connection.
7-0
(See
Note 1)
BCAB7 - BCAB0
Source Channel Address Bits: These eight bits refer to the number of the channel that
is the source (local or backplane) connection.
Note 1: Only Bits 7-0 will be used for per-channel message mode for the backplane STio streams.
Table 25 - Backplane Connection Memory Bits
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
Data Rate
Source Stream
BSAB Bit Usage
BCAB Bit Usage
2 Mb/s
STi0-27
BSAB4-0
BCAB4-0 (32-ch/frame)
4 Mb/s
STi0-18
BSAB4-0
BCAB5-0 (64-ch/frame)
8 Mb/s
STi0-18
BSAB4-0
BCAB6-0 (128-ch/frame)
2-bit subrate
STi0-15
BSAB3-0
BCAB6-0 (128 ch/frame)
4-bit subrate
STi0-15
BSAB3-0
BCAB5 -0 (64 ch/frame)
Table 26 - BSAB and BCAB Bits Usage when Source Streams are from the Local Port
Data Rate
Source Stream
BSAB Bit Usage
BCAB Bit Usage
8 Mb/s
STio0-31
BSAB4-0
BCAB6-0 (128-ch/frame)
16 Mb/s
STio0-15
BSAB3-0
BCAB7-0 (256 ch/frame)
Table 27 - BSAB and BCAB Bits Usage when Source Streams are from the Backplane Port
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSRS1
LSRS0
Bit
Name
Description
15 - 2
Unused
1-0
LSRS1 - LSRS0
Reserved.
Sub-rate Switching Bits:
For the 4-bit wide sub-rate switching:
LSRS1 - 0
STo Output
01
Bit 7 - 4 of the 8 bit data
00
Bit 3 - 0 of the 8 bit data
For 2-bit wide sub-rate switching:
LSRS1 - 0
STo Output
11
Bit 7 - 6 of the 8 bit data
10
Bit 5 - 4 of the 8 bit data
01
Bit 3 - 2 of the 8 bit data
00
Bit 1 - 0 of the 8 bit data
Table 28 - Local Connection Memory High Bits
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LTM
2
LTM
1
LTM
0
LSAB
4
LSAB
3
LSAB
2
LSAB
1
LSAB
0
LCAB
7
LCAB
6
LCAB
5
LCAB
4
LCAB
3
LCAB
2
LCAB
1
LCAB
0
Bit
15 -13
Name
LTM2 - 0
Description
Throughput Delay and Message Channel Control Bits: These three bits control the
local ST-BUS output.
LTM2-0
Throughput delay and Message Mode control
000
Per-channel variable delay from local interface; the content of the connection
memory is the local data memory address of the switched input channel and stream.
The local ST-BUS output is from the local ST-BUS input.
001
Per-channel constant delay from local interface; the content of the connection
memory is the local data memory address of the switched input channel and stream.
The local ST-BUS output is from the local ST-BUS input.
010
Per-channel variable delay from backplane interface; the content of the connection
memory is the backplane data memory address of the switched input channel and
stream. The local ST-BUS output is from the backplane CT-Bus input.
011
Per-channel constant delay from the backplane interface; the content of the
connection memory is the backplane data memory address of the switched input
channel and stream. The local ST-BUS output is from backplane CT-Bus input.
100
Per-channel message mode; only the lower byte (bits 7 to 0) of the connection
memory location will be presented to the local ST-BUS output channel.
101
Per-channel BER pattern; the pseudo random BER test pattern will be presented to
the local ST-BUS output channel.
110
Per-channel high-impedance. The local ST-BUS output is high-impedance.
111
Reserved
12 - 8
LSAB4 LSAB0
LTM0
Input Source
LTM1
LTM2
.
0
0
0
x
0
0
1
x
0
1
0
x
0
1
1
x
1
0
0
1
0
1
1
1
0
1
1
1
Local
Backplane
Var.
delay
Const.
delay
Msg
Mode
BER
Output HiZ
x
x
x
x
x
x
x
Reserved
Source Stream Address Bits: These five bits refer to the number of the data streams for
the source (local or backplane) connection.
Table 29 - Local Connection Memory Low Bits
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
Bit
Name
Description
7-0
(See
Note 1)
LCAB7 LCAB0
Source Channel Address Bits: These eight bits refer to the number of the channel that
is the source (local or backplane) connection.
Note 1: Only Bits 7-0 will be used for per-channel message mode for the local STo streams.
Table 29 - Local Connection Memory Low Bits (continued)
Data Rate
Source Stream
LSAB Bit Usage
LCAB Bit Usage
8 Mb/s
STio0-31
LSAB4-0
LCAB6-0 (128-ch/frame)
16 Mb/s
STio0-15
LSAB3-0
LCAB7-0 (256 ch/frame)
Table 30 - LSAB and LCAB Bits Usage when Source Streams are from the Backplane Port
Data Rate
Source Stream
LSAB Bit Usage
LCAB Bit Usage
2 Mb/s
STi0-27
LSAB4-0
LCAB4-0 (32-ch/frame)
4 Mb/s
STi0-18
LSAB4-0
LCAB5-0 (64-ch/frame)
8 Mb/s
STi0-18
LSAB4-0
LCAB6-0 (128-ch/frame)
2-bit subrate
STi0-15
LSAB3-0
LCAB6-0 (128 ch/frame)
4-bit subrate
STi0-15
LSAB3-0
LCAB5 -0 (64 ch/frame)
Note: When operating at 4 Mb/s or 8 Mb/s, STo19-27 are driven low.
Table 31 - LSAB and LCAB Bits Usage when Source Stream are from the Local Port
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Zarlink Semiconductor Inc.
MT90866
23.0
Data Sheet
DC/AC Electrical Characteristics
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD
-0.5
5.0
V
VDD5V
-0.5
7.0
V
1
Supply Voltage
2
BSTio Bias Voltage
3
Input Voltage
VI
-0.5
VDD + 0.5
V
4
Output Voltage
Vo
-0.5
VDD + 0.5
V
5
Package power dissipation
PD
2
W
6
Storage temperature
TS
+125
°C
- 55
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
1
Operating Temperature
TOP
-40
25
+85
°C
2
Positive Supply
VDD
3.0
3.3
3.6
V
3
BSTio Bias Voltage (3 V PCI Spec)
VDD5V
3.0
3.3
3.6
V
3
BSTio Bias Voltage (5 V PCI Spec)
VDD5V
4.5
5.0
5.5
V
4
Input Voltage
VI
0
VDD
V
5
Input Voltage on 5 V Tolerant Inputs
VI_5V
0
VDD5V
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
480
mA
1
Supply Current
IDD
2
Input High Voltage
VIH
3
Input Low Voltage
VIL
0.3VDD
V
4
Input Leakage (input pins)
IL
15
µA
0.7VDD
Test Conditions
Output unloaded
V
0 < V < VDD_IO
See Note 1
5
Weak Pullup Current
IPU
33
50
µA
Input at 0V
6
Weak Pulldown Current
IPD
33
50
µA
Input at VDD
7
Input Pin Capacitance
5
10
pF
CI
V
IOH = 10 mA
0.4
V
IOL = 10 mA
IOZ
5
µA
0 < V < VDD_IO
CO
15
pF
8
Output High Voltage
VOH
9
Output Low Voltage
VOL
10
High Impedance Leakage
11
Output Pin Capacitance
0.8VDD
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (Vin).
67
Zarlink Semiconductor Inc.
MT90866
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
Characteristics
1
Sym.
Level
Units
VCT
0.5VDD
V
V
V
CMOS Threshold
2
Rise/Fall Threshold Voltage High
VHM
0.7VDD
3
Rise/Fall Threshold Voltage Low
VLM
0.3VDD
Conditions
AC Electrical Characteristics† - Input Frame Pulse and Input Clock Timing
Characteristic
Sym.
Min.
Typ.‡
122
1
FRAME_A_io, FRAME_B_io Input Frame Pulse Width
tCFPIW
90
2
FRAME_A_io, FRAME_B_io Input Frame Pulse Setup
Time
tCFPIS
3
FRAME_A_io, FRAME_B_io Input Frame Pulse Hold
Time
4
Max. Units Notes
180
ns
45
90
ns
tCFPIH
45
90
ns
C8_A_io, C8_B_io Input Clock Period
tC8MIP
122-φ
122+φ
ns
5
C8_A_io, C8_B_io Input Clock High Time
tC8MIH
58-φ
64+φ
ns
6
C8_A_io, C8_B_io Input Clock Low Time
tC8MIL
58-φ
64+φ
ns
7
Phase Correction
φ
0
10
ns
8
C8_A_io, C8_B_io Input Rise/Fall Time
trC8i, tfC8i
0
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
CBFPIW
FRAME_A_io,
FRAME_B_io
(INPUT)
tCFPIS
tBFPH
tC8MIP
tC8MIL
C8_A_io,
C8_B_io
(INPUT)
tC8MIH
trC8i
Backplane Frame Boundary
Figure 22 - Backplane Frame Pulse Input and Clock Input Timing Diagram
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Zarlink Semiconductor Inc.
tfC8i
MT90866
Data Sheet
AC Electrical Characteristics† - Output Frame Pulse and Output Clock Timing
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
∆∗
6.50
7.50
ns
tFBOS
1.25-∆
2.5+∆
ns
FRAME_A_io, FRAME_B_io Output Pulse
Width
tCFPOW
122-∆
122+∆
ns
4
Delay from FRAME_A_io, FRAME_B_io
output falling edge to C8_a_io,C8_B_io
output rising edge
tCFODF
61-∆/2
61+∆/2
ns
5
Delay from C8_A_io,C8_B_io output rising
edge to FRAME_A_io,FRAME_B_io output
rising edge
tCFODR
61-∆/2
61+∆/2
ns
6
C8_A_io, C8_B_io Output Clock Period
tC8MP
122-∆
122+∆
ns
7
C8_A_io, C8_B_io Output High Time
tC8MH
61-∆/2
61+∆/2
ns
8
C8_A_io, C8_B_io Output Low Time
tC8ML
61-∆/2
61+∆/2
ns
9
C8_A_io, C8_B_io Output Rise Time
trC8o
13
ns
10
C8_A_io, C8_B_io Output Fall Time
tfC8o
14
11
C32/64o (32.768 MHz) Output Delay Time
tC32MOD
∆
ns
12
C32/64o (32.768 MHz) Period
tC32MP
30.5-∆
30.5+∆
ns
13
C32/64o (32.768 MHz) High Time
tC32MH
15.25-∆/2
15.25+∆/2
ns
14
C32/64o (32.768 MHz) Low Time
tC32ML
15.25-∆/2
15.25+∆/2
ns
15
C32/64o (65.536 MHz) Period
tC64MP
15.25-∆/2 15.25 15.25+∆/2
ns
16
C32/64o (65.536 MHz) High Time
tC64MH
∆
0.5+∆
ns
17
C32/64o (65.536 MHz) Low Time
tC64ML
∆
5.5+∆
ns
18
C32/64o Clock Rise Time
(32.768 MHz or 65.536 MHz)
tr32o
5
ns
19
C32/64o Clock Fall Time
(32.768 MHz or 65.536 MHz)
tf32o
6
ns
1
Internal Timing Variation
2
Backplane Frame Boundary Offset
3
122
Notes
CL=30pF
122
30.5
CL=30pF
CL=30pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* The AC electrical characteristics are listed as a function of the internal timing variation (∆) to highlight the value of each parameter independent
of the variation. It is important to choose the maximum or minimum ∆ value correctly for worst case timing calculation. When adding parameters
for timing calculation, it is sufficient to include this ∆ only once in the calculation.
69
Zarlink Semiconductor Inc.
MT90866
Data Sheet
Backplane Frame Boundary
tFBOS
tCFPOW
FRAME_A_io,
FRAME_B_io
(OUTPUT)
tCFODR
tC8MH
C8_A_io,
C8_B_io
(OUTPUT)
tC32ML tC32MH
tCFODF
tC8MP
tC8ML
trC8o
tC32MP
tfC8o
tC32MOD
C32/64o
(32.768 MHz)
tC64ML
tC64MH
trC32o
tC64MP
tfC32o
tC64MOD
C32/64o
(65.536 MHz)
Figure 23 - Backplane Frame Pulse Output and Clock Output Timing Diagram (in Primary Master
Mode and Secondary Master Mode)
AC Electrical Characteristics† - C20i Master Input Clock Timing
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
tC20MP
49.995
50
50.005
ns
-100
100
ppm
1
C20i Input Clock Period
2
C20i Input Clock Tolerance
3
C20i Input Clock High Time
tC20MH
20
30
ns
4
C20i Input Clock Low Time
tC20ML
20
30
ns
5
C20i Input Rise/Fall Time
trC20M,
tfC20M
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tC20MP
tC20ML
tC20MH
C20i
trC20M
tfC20M
Figure 24 - Backplane Frame Pulse Input and Clock Input Timing Diagram
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Zarlink Semiconductor Inc.
Notes
MT90866
Data Sheet
AC Electrical Characteristics† - Reference Input Timing
Characteristic
1
Min.
Typ.‡
tR8KP
121
125
129
µs
128.91
µs
Sym.
CTREF1, CTREF2, LREF0-7 Period
Max.
Units
2
CTREF1, CTREF2, LREF0-7 High Time
tR8kh
0.09
3
CTREF1, CTREF2, LREF0-7 Low Time
tR8kL
0.09
128.91
µs
4
CTREF1, CTREF2, LREF0-7 Rise/Fall Time
trR8K, tfR8K
0
20
ns
5
CTREF1, CTREF2, LREF0-7 Period
tR2MP
366
488
610
ns
6
CTREF1, CTREF2, LREF0-7 High Time
tR2Mh
90
244
520
ns
7
CTREF1, CTREF2, LREF0-7 Low Time
tR2ML
90
244
520
ns
8
CTREF1, CTREF2, LREF0-7 Rise/Fall Time
trR2M,
tfR2M
0
20
ns
9
CTREF1, CTREF2, LREF0-7 Period
tR1M5P
486
648
810
ns
10 CTREF1, CTREF2, LREF0-7 High Time
tR1M5h
90
324
720
ns
11 CTREF1, CTREF2, LREF0-7 Low Time
tR1M5L
90
324
720
ns
12 CTREF1, CTREF2, LREF0-7 Rise/Fall Time
trR1M5,
tfR1M5
0
20
ns
Notes
8 kHz
Mode
2.048 MHz
Mode
1.544 MHz
Mode
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tR8KP
CTREF1,
CTREF2,
LREF0-7
(8 kHz)
tR8KH
trR8K
tR8KL
tfR8K
Figure 25 - Reference Input Timing Diagram when the input frequency = 8 kHz
tR2MP
tR2ML
tR2MH
CTREF1,
CTREF2,
LREF0-7
(2.048 MHz)
trR2M
tfR2M
Figure 26 - Reference Input Timing Diagram when the input frequency = 2.048 MHz
tR1M5P
tR1M5L
CTREF1,
CTREF2,
LREF0-7
(1.544 MHz)
tR1M5H
trR1M5
tfR1M5
Figure 27 - Reference Input Timing Diagram when the input frequency = 1.544 Hz
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
AC Electrical Characteristics† - Reference Output Timing
Characteristic
Sym.
1
NREFo Output Delay Time
2
Typ.‡
Min.
Max.
Units
20
ns
tROD
NREFo Clock Period
tRP
Same as LREF0-7 Period
3
NREFo Clock High Time
tRH
Same as LREF0-7 High Time
4
NREFo Clock Low Time
tRL
Same as LREF0-7 Low Time
5
NREFo Clock Rise/Fall Time
6
trREF,
tfREF
0
NREFo Clock Period
tR8KOP
124.9
7
NREFo Clock High Time
tR8KO2H
8
NREFo Clock Low Time
9
Notes
(DIV1,DIV0) =
(0,0)
12
14
ns
125
125.1
µs
124.4
124.5
124.6
µs
tR8KO2L
488-∆
488
488+∆
ns
NREFo Clock High Time
tR8KO15H
124.3
124.4
124.5
µs
10 NREFo Clock Low Time
tR8KO15L
648-∆
648
648+∆
ns
in the DOM2
Register
(DIV1,DIV0) =
(0,1) or
(DIV1,DIV0) =
(1,0)
in the DOM2
Register
‡ Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
LREF0-7
(8 KHz)
tROD
NREFo
(8 KHz)
tRP
tRH
tRL
trREF
tfREF
Figure 28 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
LREF0-7
(2.048 MHz)
tROD
tRP
tRH
tRL
NREFo
(2.048 MHz)
trREF
tfREF
Figure 29 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
LREF0-7
(1.544 MHz)
tROD
tRP
tRH
tRL
NREFo
(1.544 MHz)
trREF
tfREF
Figure 30 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
LREF0-7
(2.048 MHz)
NREFo
(8 KHz)
tROD
tR8KO2L
trREF
tR8KOP
tR8KO2H
tfREF
Figure 31 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register
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Zarlink Semiconductor Inc.
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LREF0-7
(1.544 MHz)
tROD
tR8KOP
tR8KO15L
NREFo
(8 KHz)
trREF
Data Sheet
tR8KO15H
tfREF
Figure 32 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 1) in DOM2 Register
AC Electrical Characteristics† - Local Frame Pulse and Clock Timing, ST_CKo = 4.096 MHz
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
17.5+∆
ns
244+∆
ns
1
Local Frame Boundary Offset1
tLFBOS
∆
2
ST_FPo0/1 Width
tFPW4
244-∆
3
ST_FPo0/1 Output Delay from Falling edge
of ST_FPo0/1 to falling edge of ST_CKo0/1
tFODF4
122-∆/2
122+∆/2
ns
4
ST_FPo 0/1Output Delay from Falling edge
tFODR4
122-∆/2
122+∆/2
ns
244+∆
ns
244
Notes
CL=30pF
of ST_CKo0/1 to rising edge of ST_FPo0/1
5
ST_CKo0/1 Clock Period
tCP4
244-∆
6
ST_CKo0/1 Clock Pulse Width High
tCH4
122-∆/2
122+∆/2
ns
7
ST_CKo0/1 Clock Pulse Width Low
tCL4
122-∆/2
122+∆/2
ns
8
ST_CKo0/1 Clock Rise/Fall Time
14
ns
244
trC4o, tC4o
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1: No jitter presented on input reference clock.
Backplane Frame Boundary
Local Output Frame Boundary
tLFBOS
tFPW4
ST_FPo0/1
tFODF4
tFODR4
tCP4
tCH4
tCL4
ST_CKo0/1
(4.096 MHz)
tfC4o
trC4o
Figure 33 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 4.096 MHz
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Data Sheet
AC Electrical Characteristics† - Local Frame Pulse and Clock Timing, ST_CKo0 = 8.192 MHz
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
17.5+∆
ns
122+∆
ns
1
Local Frame Boundary Offset1
tLFBOS
∆
2
ST_FPo0/1 Width
tFPW8
122-∆
3
ST_FPo0/1 Output Delay from Falling edge
of ST_FPo0/1 to falling edge of ST_CKo0/1
tFODF8
61-∆/2
61+∆/2
ns
4
ST_FPo0/1 Output Delay from Falling edge
of ST_CKo0-1 to rising edge of ST_FPo0/1
tFODR8
61-∆/2
61+∆/2
ns
5
ST_CKo0/1 Clock Period
tCP8
122-∆
122+∆
ns
6
ST_CKo0/1 Clock Pulse Width High
tCh8
61-∆/2
61+∆/2
ns
7
ST_CKo0/1 Clock Pulse Width Low
tCL8
61-∆/2
61+∆/2
ns
8
ST_CKo0/1 Clock Rise/Fall Time
trC8o,
tfC8o
14
ns
122
122
Notes
CL=30 pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1: No jitter presented on input reference clock.
Backplane Frame Boundary
Local Output Frame Boundary
tLFBOS
tFPW8
ST_FPo0/1
tCL8
tFODF8
tFODR8
tCH8
tCP8
ST_CKo0/1
(8.192 MHz)
trC8o
tfC8o
Figure 34 - Local Clock Timing Diagram when ST_CKo0/1 frequency = 8.192 MHz
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Data Sheet
AC Electrical Characteristics† - Local Frame Pulse and Clock Timing, ST_CKo = 16.384 MHz
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
17+∆
ns
61+∆
ns
1
Local Frame Boundary Offset1
tLFBOS
∆
2
ST_FPo0/1 Width
tFPw16
61-∆
3
ST_FPo0/1 Output Delay from Falling edge
of ST_FPo0/1 to falling edge of ST_CKo0/1
tFODF16
30.5-∆/2
30.5+∆/2
ns
4
ST_FPo Output Delay from Falling edge of
tFODR16
30.5-∆/2
30.5+∆/2
ns
61+∆
ns
61
Notes
ST_CKo0/1 to rising edge of ST_FPo0/1
5
ST_CKo0/1 Clock Period
tCP16
61-∆
61
6
ST_CKo0/1 Clock Pulse Width High
tCh16
30.5-∆/2
30.5+∆/2
ns
7
ST_CKo0/1 Clock Pulse Width Low
tCL16
30.5-∆/2
30.5+∆/2
ns
8
ST_CKo0/1 Clock Rise/Fall Time
14
ns
trC16o, tfC16o
CL=30pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1: No jitter presented on input reference clock.
Backplane Frame Boundary
Local Output Frame Boundary
tLFBOS
tFPW16
ST_FPo0/1
tFODR16
tFODF16
tCL16
tCH16
tCP16
ST_CKo0/1
(16.384 MHz)
trC16o
tfC16o
Figure 35 - Local Clock Timing Diagram when ST_CKo frequency = 16.384 MHz
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Zarlink Semiconductor Inc.
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Data Sheet
AC Electrical Characteristics†- C1M5o Output Clock Timing
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
Notes
CL=30 pF
1
C1M5o Period
tC1M5oP
648-∆
648
648+∆
ns
2
C1M5o High Time
tC1M5oH
324-∆/2
324
324+∆/2
ns
3
C1M5o Low Time
tC1M5oL
324-∆/2
324
324+∆/2
ns
4
C1M5o Rise Time
trC1M5o
10
ns
11
5
tfC1M5o
C1M5o Fall Time
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
ns
C1M5o
(1.544 MHz)
trC1M5o
tfC1M5o
tC1M5oH
tC1M5oL
tC1M5oP
Figure 36 - C1M5o Output Clock Timing Diagram
AC Electrical Characteristics†- Output Clock Jitter Generation (Unfiltered)
Characteristic
Typ.‡
Max.
Units
Notes
Device locks to1.544 MHZ
reference input, and no jitter
present on the reference
1
Jitter at C1M5o (1.544 MHz)
7.4
8.0
ns-pp
2
Jitter at ST_CKo0-1 (4.096 MHz)
7.1
8.8
ns-pp
3
Jitter at ST_CKo0-1 (8.192 MHz)
7.0
8.3
ns-pp
4
Jitter at ST_CKo0-1 (16.384 MHz)
7.6
9.9
ns-pp
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
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MT90866
Data Sheet
AC Electrical Characteristics† - Backplane Serial Streams with Data Rate of 8 Mb/s
Characteristic
1
2
3
4
5
STio0-31 Input Data Sample Point
STio0-31 Input Setup Time
STio0-31 Input Hold Time
STio0-31 Output Delay
Active to Active
Per Channel boundary HiZ
Sym.
Min.‡
Typ.‡
Max.
Units
Test Conditions
tSAMP8
tCIS8
tCIH8
tDOD8
91.5
5+∆
5+∆
1-∆
91.5
91.5
ns
ns
ns
ns
CL = 30 pF, Note 1
5+∆
tDOZ8
tZDO8
10
10
ns
ns
RL=1K, CL=30 pF,
Note 2
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: To meet the H.110 output timing requirement, the output delay time can be reduced further by programming the backplane output
advancement registers (BOA0 - 3).
* Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
FRAME_A_io,
FRAME_B_io
(INPUT)
C8_A_io,
C8_B_io
(8.192 MHz)
(INPUT)
tSAMP8
tCIH8
tCIS8
STio (8 Mb/s)
Backplane input
Bit 6
Ch127
Bit 7
Ch127
Bit 0
Ch 0
tZDO8
STio (8 Mb/s)
Backplane output
Bit 6
Ch127
Bit 1
Ch 0
Bit 2
Ch 0
Bit 3
Ch 0
Bit 4
Ch 0
VTT
tDOD8
Bit 7
Ch127
Bit 0
Ch 0
Bit 1
Ch 0
Bit 2
Ch 0
Bit 3
Ch 0
Bit 4
Ch 0
tDOZ8
Figure 37 - Backplane Serial Stream Timing when the Data Rate is 8 Mb/s
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Zarlink Semiconductor Inc.
VTT
MT90866
Data Sheet
AC Electrical Characteristics† - Backplane Serial Streams with Data Rate of 16 Mb/s
Characteristic
1
Min.
Typ.‡
Max.
Units
tSAMP16
46
46
46
ns
ns
ns
Sym.
STio0-15 Input Data Sample Point
2
STio0-15 Input Setup Time
tCIS16
5+∆
3
STio0-15 Input Hold Time
tCIH16
5+∆
4
STio0-15 Output Delay
Active to Active
tDOD16
1-∆
5+∆
Test Conditions
ns
CL = 30 pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
FRAME_A_io,
FRAME_B_io
(Input)
C8_A_io,
C8_B_io
(8.192 MHz)
(Input)
STio (16 Mb/s)
Backplane input
tSAMP16
tCIS16
Bit 3
Ch255
Bit 1
Bit 2
Ch255 Ch255
Bit 0
Ch255
tCIH16
Bit 7
Ch 0
Bit 6
Ch 0
Bit 5
Ch 0
Bit 4
Ch 0
Bit 3
Ch 0
Bit 2
Ch 0
Bit 1
Ch 0
Bit 0
Ch 0
Bit 7
Ch 1
Bit 6
Ch 1
VTT
tDOD16
STio (16 Mb/s)
Backplane output
Bit 3
Ch255
Bit 1
Bit 2
Ch255 Ch255
Bit 0
Ch255
Bit 7
Ch 0
Bit 6
Ch 0
Bit 5
Ch 0
Bit 4
Ch 0
Bit 3
Ch 0
Bit 2
Ch 0
Bit 1
Ch 0
Bit 0
Ch 0
Bit 7
Ch 1
Bit 6
Ch 1
Figure 38 - Backplane Serial Stream Timing when the Data Rate is 16 Mb/s
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Zarlink Semiconductor Inc.
VTT
MT90866
Data Sheet
AC Electrical Characteristics† - Local Serial Stream Output Timing
Characteristic
1
STo Delay - Active to Active
@2.048 Mb/s
@4.096 Mb/s
@8.192 Mb/s
Sym.
Min.
tSOD2
tSOD4
tSOD8
-10-∆∗
-10-∆∗
-10-∆∗
Typ.‡
Max.
Units
Test Conditions
1.5-∆∗
1.5-∆∗
1.5-∆∗
ns
ns
ns
CL = 30 pF
CL = 30 pF
CL = 30 pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* See Section 7.0, “Local Output Timing Considerations” on page 21
ST_FPo0/1,
ST_CKo0/1
tSOD8
STo (8 Mb/s)
Local output
Bit 1
Ch127
Bit 0
Ch127
Bit 7
Ch 0
Bit 6
Ch 0
Bit 5
Ch 0
Bit 4
Ch 0
Bit 3
Ch 0
Bit 2
Ch 0
VTT
tSOD4
STo (4 Mb/s)
Local output
Bit 6, Ch 0
Bit 7, Ch 0
Bit 5, Ch 0
VTT
tSOD2
STo (2 Mb/s)
Local output
Bit 0, Ch 31
Bit 7, Ch 0
Bit 6, Ch 0
Bit 3, Ch 0
Bit 2, Ch 0
Bit 1, Ch 0
Bit 0, Ch 0
VTT
tSOD2
STo0-15
(2 Mb/s)
4-bit wide output
Bit 0, Ch 31
STo0-15 (2 Mb/s)
2-bit wide output
Bit 0, Ch 31
VTT
tSOD2
Figure 39 - Local Serial Stream Output Timing
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MT90866
Data Sheet
AC Electrical Characteristics† - Local Serial Stream Input Timing
Sym.
Min.
Typ.‡
Max.
Units
tSAMP2L
tSAMP4L
tSAMP8L
366
183
91.5
366
183
91.5
366
183
91.5
ns
ns
ns
STi Setup Time
@2.048 Mb/s
@4.096 Mb/s
@8.192 Mb/s
tSIS2
tSIS4
tSIS8
5+∆
5+∆
5+∆
ns
ns
ns
STi Hold Time
@2.048 Mb/s
@4.096 Mb/s
@8.192 Mb/s
tSIH2
tSIH4
tSHI8
5+∆
5+∆
5+∆
ns
ns
ns
Characteristic
1
2
3
STi Input Data Sample Point
@2.048 Mb/s
@4.096 Mb/s
@8.192 Mb/s
FRAME_A_io
FRAME_B_io
(Input)
C8_A_io
C8_B_io
(Input)
tSAMP8
tSIS8
STi (8 Mb/s)
Local input
Bit 1
Ch 127
Bit 0
Ch 127
tSAMP4
STi (4 Mb/s)
Local input
tSIH8
Bit 6
Ch 0
Bit 7
Ch 0
tSIS4
Bit 0
Ch63
Bit 5
Ch 0
Bit 4
Ch 0
Bit 3
Ch 0
VTT
tSIH4
Bit 7
Ch 0
tSAMP2
STi (2 Mb/s)
Local input
Test Conditions
Bit 6
Ch 0
tSIS2
tSIH2
Bit 7
Ch 0
Bit 0
Ch31
Figure 40 - Local Serial Stream Input Timing
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Zarlink Semiconductor Inc.
VTT
VTT
MT90866
Data Sheet
AC Electrical Characteristics† - Local and Backplane Tristate Timing
Characteristic
1
Sym.
STo/STio Delay - Active to High-Z
- High-Z to Active
2.048 Mb/s (local)
4.096 Mb/s (local)
8.192 Mb/s (local)
8.192 Mb/s (backplane)
16.384 Mb/s (backplane)
2
2
Output Driver Enable (ODE) Delay
- High-Z to Active
2.048 Mb/s (local)
4.096 Mb/s (local)
8.192 Mb/s (local)
8.192 Mb/s (backplane)
16.384 Mb/s (backplane)
Output Driver Disable (ODE) Delay
- Active to High-Z
2.048 Mb/s (local)
4.096 Mb/s (local)
8.192 Mb/s (local)
8.192 Mb/s (backplane)
16.384 Mb/s (backplane)
Typ.‡
Min.
tDZ, tZD
-12-∆
-12-∆
-12-∆
-1-∆
-1-∆
Max.
Units
Test Conditions
3.5-∆
3.5-∆
3.5-∆
7+∆
7+∆
ns
ns
ns
ns
ns
RL=1K, CL=30pF,
See Note 1.
37
37
37
20
20
ns
ns
ns
ns
ns
20
20
20
20
20
ns
ns
ns
ns
ns
tZD_ODE
tDZ_ODE
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
ST_FPo0/1
VTT
ST_CKo0/1
tDZ
STo
Valid Data
Tri-state
VTT
Valid Data
VTT
tZD
STo
Tri-state
Figure 41 - Local Serial Output and External Control
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FRAME_A_io
FRAME_B_io
(Input)
C8_A_io
C8_B_io
(Input)
STio
(Output)
Data Sheet
VTT
tDZ
Valid Data
Tri-state
VTT
Valid Data
VTT
tZD
Tri-state
STio
(Output)
Figure 42 - Backplane Serial Output and External Control
VTT
ODE
tDZ_ODE
tZD_ODE
STo or STio
(Output)
HiZ
Valid Data
HiZ
VTT
Figure 43 - Output Driver Enable (ODE)
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Zarlink Semiconductor Inc.
MT90866
Data Sheet
AC Electrical Characteristics† - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.‡
Max.
Test Conditions1
Units
1
CS setup from DS falling
tCSS
0
ns
2
R/W setup from DS falling
tRWS
15
ns
3
Address setup from DS falling
tADS
5
ns
4
CS hold after DS rising
tCSH
0
ns
5
R/W hold after DS rising
tRWH
0
ns
6
Address hold after DS rising
tADH
5
ns
7
Data setup from DTA Low on Read
tDDR
20
ns
CL=30pF
8
Data hold on read
tDHR
20
ns
CL=30pF, RL=1K
See Note 2
9
Valid Write Data Setup
tWDS
20
ns
10 Data hold on write
11
8
tDHW
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
12 Acknowledgment Hold Time
tAKD
ns
97/82
110/95
158/114 171/127
30
tAKH
ns
ns
CL=30pF
CL=30pF
ns
CL=30pF, RL=1K,
See Note 2
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*Note 1: A delay of 100 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high.
*Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
VTT
DS
tCSH
tCSS
VTT
CS
tRWH
tRWS
VTT
R/W
tADH
tADS
VTT
VALID ADDRESS
A0-A13
tDHR
D0-D15
READ
VTT
VALID READ DATA
tWDS
tDHW
D0-D15
WRITE
VTT
VALID WRITE DATA
tDDR
VTT
DTA
tAKD
Figure 44 - Motorola Non-Multiplexed Bus Timing
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Zarlink Semiconductor Inc.
tAKH
MT90866
Data Sheet
AC Electrical Characteristics† - JTAG Test Port and Reset Pin Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
1
TCK Clock Period
tTCKP
200
ns
2
TCK Clock Pulse Width High
tTCKH
80
ns
3
TCK Clock Pulse Width Low
tTCKL
80
ns
4
TMS Set-up Time
tTMSS
10
ns
5
TMS Hold Time
tTMSH
10
ns
6
TDi Input Set-up Time
tTDIS
20
ns
7
TDi Input Hold Time
tTDIH
20
ns
8
TDo Output Delay
tTDOD
9
TRST pulse width
tTRSTW
10 Reset pulse width
tRSTW
30
ns
CL=30pF
20
ns
CL=30pF
400
ns
CL=30pF
† Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL
tTCKH
tTCKP
TCK
tTMSH
tTMSS
TMS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
Figure 45 - JTAG Test Port Timing Diagram
tRSTW
Reset
Figure 46 - Reset Pin Timing Diagram
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Zarlink Semiconductor Inc.
Notes
MT90866
24.0
Data Sheet
Trademarks
CompactPCI® is a registered trademark of PICMG-PCI Industrial Computer Manufacturers Group, Inc.
85
Zarlink Semiconductor Inc.
Package Code
c Zarlink Semiconductor 2002 All rights reserved.
ISSUE
ACN
DATE
APPRD.
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However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
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