MT9160BS1

MT9160B/61B 5 Volt Multi-Featured Codec (MFC) Data Sheet Features May 2005 • Improved idle channel noise over MT9160 • MT9161 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices • Programmable µ-Law/A-Law Codec and Filters • Programmable ITU-T G.711/sign-magnitude coding • Programmable transmit, receive and side-tone gains • Fully differential interface to handset transducers - including 300 ohm receiver driver Description • Flexible digital interface including ST-BUS/SSI • Serial microport or default controllerless mode • Single 5 volt supply • Low power operation The MT9160B/61B 5 V Multi-featured Codec incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip antialias filters, reference voltage and bias source. The device supports both ITU-T and sign-magnitude A-Law and µ-Law requirements. • ITU-T G.714 compliant Ordering Information MT9160BE 24 Pin PDIP MT9160BS 20 Pin SOIC MT9160BN 20 Pin SSOP MT9160BSR 20 Pin SOIC MT9160BN1 20 Pin SSOP* MT9160BSR1 20 Pin SOIC* MT9160BS1 20 Pin SOIC* *Pb Free Matte Tin Tubes Tubes Tubes Tape & Reel Tubes Tape & Reel Tubes -40°C to +85°C Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible with various industry standard microcontrollers. The device also supports controllerless operation utilizing the default register conditions. Applications • Digital telephone sets • Cellular radio sets • Local area communications stations The MT9160B/61B is fabricated in Zarlink's ISO2CMOS technology ensuring low power consumption and high reliability. VSSD VDD VSSA FILTER/CODEC GAIN MENCODER 7dB DECODER -7dB VBias VRef M+ Transducer Interface HSPKR + HSPKR - Din Timing Dout STB/F0i CLOCKin Flexible Digital Interface ST-BUS C&D Channels STBd/FOod (MT9161B only) Serial Microport PWRST IC CS DATA1 DATA2 A/µ/IRQ SCLK Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT9160B/61B MT9160BE MT9160BS/BN VBias VRef PWRST IC A/m/IRQ VSSD CS SCLK DATA1 DATA2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Data Sheet M+ MVSSA HSPKR + HSPKR VDD CLOCKin STB/F0i Din Dout 20 PIN SOIC/SSOP VBias VRef NC PWRST IC A/m/IRQ VSSD CS NC SCLK DATA1 DATA2 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 MT9161BE/BS/BN M+ MVSSA NC HSPKR + HSPKR VDD CLOCKin NC STB/F0i Din Dout VBias VRef NC PWRST IC A/m/IRQ VSSD CS NC SCLK DATA1 DATA2 24 PIN PDIP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 M+ MVSSA NC HSPKR + HSPKR VDD CLOCKin STBd/FOod STB/F0i Din Dout 24 PIN PDIP/SOIC/SSOP Figure 2 - Pin Connections Pin Description Pin # Pin # 20 Pin 24 Pin Name Description 1 1 VBias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µF capacitor to VSSA,Connect 1 µF capacitor to Vref. 2 2 VRef Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used internally. Connect 0.1 µF capacitor to VSSA,Connect 1 µF capacitor to VBias. 3 4 PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low). Resets internal state of device. 4 5 IC 5 6 6 7 VSSD 7 8 CS Chip Select (Input). This input signal is used to select the device for microport data transfers. Active low. CMOS level compatible. 8 10 SCLK Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level compatible. 9 11 DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/National mode of operation, this pin becomes the data transmit pin only and data receive is performed on the DATA 2 pin. Input CMOS level compatible. 10 12 DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for data receive. In Intel mode, serial data transmit and receive are performed on the DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible. 11 13 Dout Internal Connection. Tie externally to VSSD for normal operation. A/m/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs the companding law used by the filter/Codec; µ-Law when tied to VSSD and A-Law when tied to VDD. Logically OR’ed with A/µ register bit. IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt output signalling valid access to the D-Channel registers in ST-BUS mode. Digital Ground. Nominally 0 volts. Data Output. A high impedance three-state digital output for 8 bit wide channel data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with the rising edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. 2 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet Pin Description (continued) Pin # Pin # 20 Pin 24 Pin Name Description 12 14 Din Data Input. A digital input for 8 bit wide channel data received from the Layer 1 transceiver. Data is sampled on the falling edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatible. 13 15 STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. Standard frame pulse definitions apply in STBUS mode (refer to figure 11). CMOS level compatible input. 16 (MT9161B only) STBd/FOo Delayed Frame Pulse Output. In SSI mode, an 8 bit wide strobe is output after the first strobe goes low. In ST-BUS mode, a frame pulse is output 4 channel time slots d after /F0i. 14 17 CLOCKin Clock (Input). The clock provided to this input pin is used for the internal device functions. For SSI mode connect the bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin. CMOS level compatible. 15 18 16 19 HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced). 17 20 HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker (balanced). 18 22 VSSA 19 23 M- Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone. 20 24 M+ Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the handset microphone. 3,9, 16,21 NC No Connect. (24 Pin Packages only). Pin 16 is NC for MT9160B. VDD Positive Power Supply (Input). Nominally 5 volts. Analog Ground (Input). Nominally 0 volts. Overview The 5 V Multi-featured Codec (MFC) features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard handset transmitter and receiver (Transducer Interface). The receiver amplifier is capable of driving a 300 ohm load. Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller port compatible with Intel MCS-51®, Motorola SPI® and National Semiconductor Microwire® specifications. These parameters include: gain control, power down, mute, B-Channel select (ST-BUS mode), C&D channel control/access, law control, digital interface programming and loopback. Optionally the device may be used in a controllerless mode utilizing the power-on default settings. 3 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet Functional Description Filter/Codec The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion or true-sign/Inverted Magnitude coding, respectively. Optionally, sign-magnitude coding may also be selected for proprietary applications. The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and side-tone gains for the MT9160B/61B. In the event of PWRST, the MT9160B/61B defaults such that the side-tone path is off, all programmable gains are set to 0 dB and ITU-T µ-Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI and driver sections are powered up. (See Microport section) The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the Transducer Interface section to provide full chip realization of these capabilities for the handset functions. A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog ground at all times. Although VRef may only be used internally, a 0.1µF capacitor must be connected from VRef to ground. The analog ground reference point for these two capacitors must be physically the same point. Connect a 1 µF capacitor between VBias and VRef to ensure a quiet reference voltage. To facilitate this the VRef and VBias pins are situated on adjacent pins. The transmit filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz. The receive filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0 dB). Gain control allows the output signal to be attenuated up to 7 dB. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate. Side-tone is derived from the input of the Tx filter and is not subject to the gain control of the Tx filter section. Sidetone is summed into the receive handset transducer driver path after the Rx filter gain control section so that Rx gain adjustment will not affect side-tone levels. The side-tone path may be enabled/disabled with the gain control bits located in Gain Control Register 2 (address 01h). Transmit and receive filter gains are controlled by the TxFG0-TxFG2 and RxFG0-RxFG2 control bits, respectively. These are located in Gain Control Register 1 (address 00h). Transmit filter gain is adjustable from 0 dB to +7 dB and receive filter gain from 0dB to -7 dB, both in 1 dB increments. Side-tone filter gain is controlled by the STG0-STG2 control bits located in Gain Control Register 2 (address 01h). Side-tone gain is adjustable from -9.96 dB to +9.96 dB in 3.32 dB increments. Companding law selection for the Filter/Codec is provided by the A/µ companding control bit while the coding scheme is controlled by the Smag/ITU-T control bit. The A/µ control bit is logically OR’ed with the A/µ pin providing access in both controller and controllerless modes. Both A/µ and Smag/ITU-T reside in Control Register 2 (address 04h). Table 1 illustrates these choices. 4 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet ITU-T (G.711) Code Sign/ Magnitude µ-Law A-Law + Full Scale 1111 1111 1000 0000 1010 1010 + Zero 1000 0000 1111 1111 1101 0101 -Zero (quiet code) 0000 0000 0111 1111 0101 0101 0111 1111 0000 0000 0010 1010 - Full Scale Table 1 - PCM Coding Transducer Interfaces Standard handset transducer interfaces are provided by the MT9160B/61B. These are: • The handset microphone inputs (transmitter), pins M+/M-. The transmit path gain path may be adjusted to either 6.0 dB or 15.3 dB. Control of this gain is provided by the TxINC control bit (Gain Control register 1, address 00h). • The handset speaker outputs (receiver), pins HSPKR+/HSPKR-. This internally compensated fully differential output driver is capable of driving the load shown in Figure 3. The nominal receive path gain may be adjusted to either 0 dB, -6 dB or -12 dB. Control of this gain is provided by the RxINC control bit (Gain Control register 1, address 00h). This gain adjustment is in addition to the programmable gain provided by the receive filter. Filter/Codec and Transducer Interface Serial Port Default Bypass Din 2.05 dB Receive Filter Gain 0 to -7 dB (1 dB steps) -8.05 dB or -2.05 dB Receiver Driver -6 dB Side-tone -9.96 to +9. 96 dB (3.32 dB steps) HSPKR + 75 W HSPKR - Handset Receiver (150 W) 75 W Default Side-tone off PCM Decoder -11 dB PCM Dout Encoder -2.05 dB Transmit Filter Transmit Filter Gain Gain 00 to to +7 +7dBdB (1 dB steps) (1 dB steps) Transmit Gain -0.37 dB or 8.93 dB Transmit Gain 8.42 dB INTERNAL TO DEVICE Figure 3 - Audio Gain Partitioning 5 Zarlink Semiconductor Inc. M+ M- Transmitter Microphone EXTERNAL TO DEVICE MT9160B/61B Data Sheet The serial microport, compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0,CPHA=0) and National Semiconductor Microwire specifications provides access to all MT9160B/61B internal read and write registers. This microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). For D-channel contention control, in ST-BUS mode, this interface provides an open-drain interrupt output (IRQ). COMMAND/ADDRESS 5 1 DATA INPUT/OUTPUT 1 4 COMMAND/ADDRESS: DATA 1 RECEIVE D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DATA 1 TRANSMIT D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SCLK 2 4 CS 3 3 1 Delays due to internal processor timing which are transparent. 2 The MT9160:-latches received data on the rising edge of SCLK. -outputs transmit data on the falling edge of SCLK. 3 The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data until terminated via CS returning high. 4 A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. D7 5 The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 3 bits - Addressing Data X X X X A2 A1 4 bits - Unused D0 A0 R/W Figure 4 - Serial Port Relative Timing for Intel Mode 0 The microport dynamically senses the state of the serial clock (SCLK) each time chip select becomes active. The device then automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must be used. DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. Although the dual port Motorola controller configuration usually supports full-duplex communication, only half-duplex communication is possible in the MT9160B/61B. The micro must discard non-valid data which it clocks in during a valid write transfer to the MT9160B/61B. During a valid read transfer from the MT9160B/61B data simultaneously clocked out by the micro is ignored by the MT9160B/61B. All data transfers through the microport are two-byte transfers requiring the transmission of a Command/Address byte followed by the data byte written or read from the addressed register. CS must remain asserted for the duration of this two-byte transfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT9160B/61B that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT9160B/61B and the microcontroller. At the end of the two-byte transfer CS is brought high again to terminate the session. The rising edge of CS will tri-state the output driver of DATA1 which will remain tri-stated as long as CS is high. 6 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet Intel processors utilize least significant bit first transmission while Motorola/National processors employ most significant bit first transmission. The MT9160B/61B microport automatically accommodates these two schemes for normal data bytes. However, to ensure decoding of the R/W and address information, the Command/Address byte is defined differently for Intel operation than it is for Motorola/National operation. Refer to the relative timing diagrams of Figures 5 and 6. Receive data is sampled on the rising edge of SCLK while transmit data is made available concurrent with the falling edge of SCLK. COMMAND/ADDRESS 5 DATA INPUT/OUTPUT 1 4 COMMAND/ADDRESS: 1 DATA 2 RECEIVE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DATA 1 TRANSMIT D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCLK 2 CS 4 3 3 1 Delays due to internal processor timing which are transparent. 2 The MT9160:-latches received data on the rising edge of SCLK. -outputs transmit data on the falling edge of SCLK. 3 The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data until terminated via CS returning high. 4 A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. D7 5 The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 3 bits - Addressing Data A2 4 bits - Unused X X R/W X A1 D0 A0 X Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire 125 ms F0i DSTi, DSTo F0od CHANNEL 0 D-channel CHANNEL 1 C-channel LSB first for DChannel CHANNEL 2 B1-channel CHANNEL 3 B2-channel CHANNELS 4-31 Not Used MSB first for C, B1- & B2Channels Figure 6 - ST-BUS Channel Assignment Flexible Digital Interface A serial link is required to transport data between the MT9160B/61B and an external digital transmission device. The MT9160B/61B utilizes the ST-BUS architecture defined by Zarlink Semiconductor but also supports a strobed data interface found on many standard Codec devices. This interface is commonly referred to as Simple Serial 7 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet Interface (SSI). The combination of ST-BUS and SSI provides a Flexible Digital Interface (FDI) capable of supporting all Zarlink basic rate transmission devices as well as many other 2B+D transceivers. The required mode of operation is selected via the CSL2-0 control bits (Control Register 2, address 04h). Pin definitions alter dependent upon the operational mode selected, as described in the following subsections as well as in the Pin Description tables. Quiet Code The FDI can be made to send quiet code to the decoder and receive filter path by setting the RxMute bit high. Likewise, the FDI will send quiet code in the transmit path when the TxMute bit is high. Both of these control bits reside in Control Register 1 at address 03h. When either of these bits are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet code definition. ST-BUS Mode The ST-BUS consists of output (DSTo) and input (DSTi) serial data streams, in FDI these are named Dout and Din respectively, a synchronous clock input signal CLOCKin (C4i), and a framing pulse input (F0i). These signals are direct connections to the corresponding pins of Zarlink basic rate devices. The CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS operation. The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s bandwidth. A frame pulse (a 244 nSec low going pulse) is used to separate the continuous serial data streams into the 32 channel TDM frames. Each frame has a 125 µSecond period translating into an 8 kHz frame rate. A valid frame begins when F0i is logic low coincident with a falling edge of C4i. Refer to figure 11 for detailed ST-BUS timing. C4i has a frequency (4096 kHz) which is twice the data rate. This clock is used to sample the data at the 3/4 bit-cell position on DSTi and to make data available on DSTo at the start of the bit-cell. C4i is also used to clock the MT9160B/61B internal functions (i.e., Filter/Codec, Digital gain and tone generation) and to provide the channel timing requirements. The MT9160B/61B uses only the first four channels of the 32 channel frame. These channels are always defined, beginning with Channel 0 after the frame pulse, as shown in Figure 6 (ST-BUS channel assignments). The MT9161B provides a delayed frame pulse (F0od), 4 channels after the input frame pulse. The first two (D & C) Channels are enabled for use by the DEN and CEN bits respectively, (Control Register 2, address 04h). ISDN basic rate service (2B+D) defines a 16 kb/s signalling (D) Channel. The MT9160B/61B supports transparent access to this signalling channel. ST-BUS basic rate transmission devices, which may not employ a microport, provide access to their internal control/status registers through the ST-BUS Control (C) Channel. The MT9160B/61B supports microport access to this C-Channel. DEN - D-Channel In ST-BUS mode access to the D-Channel (transmit and receive) data is provided through an 8-bit read/write register (address 06h). D-Channel data is accumulated in, or transmitted from this register at the rate of 2 bits/frame for 16 kb/s operation (1 bit/frame for 8 kb/s operation). Since the ST-BUS is asynchronous, with respect to the microport, valid access to this register is controlled through the use of an interrupt (IRQ) output. D-Channel access is enabled via the (DEn) bit. DEN: When 1, ST-BUS D-channel data (1 or 2 bits/frame depending on the state of the D8 bit) is shifted into/out of the Dchannel (READ/WRITE) register. When 0, the receive D-channel data (READ) is still shifted into the proper register while the DSTo D-channel timeslot and IRQ outputs are tri-stated (default). 8 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet D8: When 1, D-Channel data is shifted at the rate of 1 bit/frame (8 kb/s). When 0, D-Channel data is shifted at the rate of 2 bits/frame (16 kb/s default). 16 kb/s D-Channel operation is the default mode which allows the microprocessor access to a full byte of DChannel information every fourth ST-BUS frame. By arbitrarily assigning ST-BUS frame n as the reference frame, during which the microprocessor D-Channel read and write operations are performed, then: (a) A microport read of address 04 hex will result in a byte of data being extracted which is composed of four di-bits (designated by roman numerals I,II,III,IV). These di-bits are composed of the two D-Channel bits received during each of frames n, n-1, n-2 and n-3. Referring to Fig. 7a: di-bit I is mapped from frame n-3, di-bit II is mapped from frame n-2, di-bit III is mapped from frame n-1 and di-bit IV is mapped from frame n. The D-Channel read register is not preset to any particular value on power-up (PWRST) or software reset (RST). (b) A microport write to Address 04 hex will result in a byte of data being loaded which is composed of four dibits (designated by roman numerals I, II, III, IV). These di-bits are destined for the two D-Channel bits transmitted during each of frames n+1, n+2, n+3, n+4. Referring to Fig. 7a: di-bit I is mapped to frame n+1, dibit II is mapped to frame n+2, di bit III is mapped to frame n+3 and di bit IV is mapped to frame n+4. If no new data is written to address 04 hex, the current D-channel register contents will be continuously retransmitted. The D-Channel write register is preset to all ones on power-up (PWRST) or software reset (RST). An interrupt output is provided (IRQ) to synchronize microprocessor access to the D-Channel register during valid ST-BUS periods only. IRQ will occur every fourth (eighth in 8 kb/s mode) ST-BUS frame at the beginning of the third (second in 8 kb/s mode) ST-BUS bit cell period. The interrupt will be removed following a microprocessor Read or Write of Address 04 hex or upon encountering the following frames F0i input, whichever occurs first. To ensure DChannel data integrity, microport read/write access to Address 04 hex must occur before the following frame pulse. See Figure 7b for timing. 8 kb/s operation expands the interrupt to every eight frames and processes data one-bit-per-frame. D-Channel register data is mapped according to Figure 7c. Cen - C-Channel Channel 1 conveys the control/status information for the Layer 1 transceiver. C-Channel data is transferred MSB first on the ST-BUS by the MT9160B/61B. The full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheet for the selected transceiver for its C-Channel bit definitions and order of bit transfer. When CEN is high, data written to the C-Channel register (address 05h) is transmitted, most significant bit first, on DSTo. On power-up reset (PWRST) or software reset (Rst, address 03h) all C-Channel bits default to logic high. Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state. When low, data transmission is halted and this timeslot is tri-stated on DSTo. B1-Channel and B2-Channel Channels 2 and 3 are the B1 and B2 channels, respectively. B-channel PCM associated with the Filter/Codec and transducer audio paths is selected on an independent basis for the transmit and receive paths. TxBSel and RxBSel (Control Register 1, address 03h) are used for this purpose. If no valid transmit path has been selected then the timeslot output on DSTo is tri-stated (see PDFDI and PDDR control bits, Control Register 1 address 03h). 9 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet IRQ Microport Read/Write Access FP n-3 n-2 n-1 n n+1 n+2 n+3 n+4* DSTo/ DSTi Di-bit Group Receive D0 D-Channel I II D1 D2 D3 No preset value D4 III IV D5 D6 D7 Di-bit Group Transmit D0 D-Channel I D1 D2 II D3 D4 III D5 D6 IV D7 Power-up reset to 1111 1111 * note that frame n+4 is equivalent to frame n of the next cycle. Figure 7a - D-Channel 16 kb/s Operation FP C4i C2 DSTo/ DSTi D0 tir =500 nsec max Rpullup= 10 k D1 tif =500 nsec max IRQ 8 kb/s operation 16 kb/s operation Reset coincident with Read/Write of Address 04 Hex or next FP, whichever occurs first Microport Read/Write Access Figure 7b - IRQ Timing Diagram IRQ Microport Read/Write Access FP n-7 n-6 n-5 n-4 n-3 n-2 n-1 n n+1 n+2 n+3 n+4 n+6 n+5 n+7 n+8 D-Channel Di-bit Group Receive D-Channel I D0 II D1 III D2 IV D3 No preset value V D4 VI D5 VII D6 VIII D7 Di-bit Group Transmit D-Channel I D0 II D1 III D2 IV D3 V D4 VI D5 Power-up reset to 1111 1111 Figure 7c - D-Channel 8 kb/s Operation 10 Zarlink Semiconductor Inc. VII D6 VIII D7 MT9160B/61B Data Sheet SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), a framing strobe input (STB) and the MT9161B provides a delayed framing strobe output (STBd). The frame strobe must be synchronous with, and eight cycles of, the bit clock. A 4.096 MHz master clock is also required for SSI operation if the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 12 & 13. In SSI mode the MT9160B/61B supports only B-Channel operation. The internal C and D Channel registers used in ST-BUS mode are not functional for SSI operation. The control bits TxBSel and RxBSel, as described in the STBUS section, are ignored since the B-Channel timeslot is defined by the input STB strobe. Hence, in SSI mode transmit and receive B-Channel data are always in the channel defined by the STB input. The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This is an active high signal with an 8 kHz repetition rate.The MT9161B provides a delayed strobe pulse (STBd) which occurs 4 frames after the initial strobe goes low and is held high for the duration of 8 pcm bits. SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is 512 kHz or greater then it is used directly by the internal MT9160B/61B functions allowing synchronous operation. If the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal MT9160B/61B functions. Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT9160B/61B will realign its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control bits CSL2, CSL1 and CSL0 in Control Register 2 (address 04h) are used to program the bit rates. For synchronous operation data is sampled, from Din, on the falling edge of BCL during the time slot defined by the STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input. Dout is tri-stated at all times when STB is not true. If STB is valid and PDDR is set, then quiet code will be transmitted on Dout during the valid strobe period. There is no frame delay through the FDI circuit for synchronous operation. For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the FDI circuit for asynchronous operation. Refer to the specifications of Figures 13 & 14 for both synchronous and asynchronous SSI timing. PWRST/Software Reset (Rst) While the MT9160B/61B is held in PWRST no device control or functionality is possible. While in software reset (Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing the Rst bit low or by performing a hardware PWRST. While the Rst bit is high, the other bits in Control Register 1 are held low and cannot be reprogrammed. Therefore to modify Control Register 1 the Rst bit must first be written low, followed by a 2nd write operation which writes the desired data. This avoids a race condition between clearing the reset bit and the writing of the other bits in Control Register 1. After a Power-up reset (PWRST) or software reset (Rst) all control bits assume their "Power Reset Value" default states; µ-Law coding, 0 dB Rx and 6dB Tx gains and the device powered up in SSI mode 2048 kb/s operation with Dout tri-stated while there is no strobe active on STB. If a valid strobe is supplied to STB, then Dout will be active, during the defined channel. To attain complete power-down from a normal operating condition, write PDFDI = 1 and PDDR = 1 (Control Register 1, address 03h) or set the PWRST pin low. 11 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet Register Summary Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description 00 RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0 Gain Control Register 1 01 - - - - - STG2 STG1 STG0 Gain Control Register 2 02 - - - - - - - DrGain Path Control 03 PDFDI PDDR RST - TxMute RxMute TxBsel RxBsel Control Register 1 04 CEN DEN D8 A/m Smag/ ITU-T CSL2 CSL1 CSL0 Control Register 2 05 C7 C6 C5 C4 C3 C2 C1 C0 C-Channel Register 06 D7 D6 D5 D4 D3 D2 D1 D0 D-Channel Register 07y - - - - PCM/ ANALOG loopen - - Loop Back Table 2 - V Multi-Featured Codec Register Map Gain Control Register 1 ADDRESS = 00h WRITE/READ VERIFY Power Reset Value 1000 0000 RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0 7 Receive Gain 6 5 4 3 RxFG2 RxFG1 RxFG0 (default) 0 0 0 0 -1 0 0 1 -2 0 1 -3 0 -4 2 1 Transmit Gain 0 TxFG2 TxFG1 TxFG0 (default) 0 0 0 0 1 0 0 1 0 2 0 1 0 1 1 3 0 1 1 1 0 0 4 1 0 0 -5 1 0 1 5 1 0 1 -6 1 1 0 6 1 1 0 -7 1 1 1 7 1 1 1 Setting (dB) RxFGn = Receive Filter Gain bit n Setting (dB) TxFGn = Transmit Filter Gain bit n RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB. TxINC: When high, the transmit nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB. Note: Bits marked "-" are reserved bits and should be written with logic "0" 12 Zarlink Semiconductor Inc. MT9160B/61B Gain Control Register 2 Data Sheet ADDRESS = 01h WRITE/READ VERIFY - - - - - STG2 STG1 STG0 7 6 5 4 3 2 1 0 Side-tone Gain Setting (dB) STG2 STG1 STG0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 (default) OFF -9.96 -6.64 -3.32 0 3.32 6.64 9.96 Power Reset Value XXXX X000 STGn = Side-tone Gain bit n Path Control ADDRESS = 02h WRITE/READ VERIFY 7 DrGain - - - - - - DrGain 6 5 4 3 2 1 0 When high, the receive path is summed with the side tone path and is attenuated by 6 dB. When low, the receive path contains no side tone (default). 13 Zarlink Semiconductor Inc. Power Reset Value XX00 0000 MT9160B/61B Control Register 1 ADDRESS = 03h WRITE/READ VERIFY PDFDI PDDR 7 PDFDI PDDR Rst TxMute RxMute TxBsel RxBsel Data Sheet 6 Rst _ 5 4 TxMute RxMute TxBsel RxBsel 3 2 1 Power Reset Value 0000 0000 0 When high, the FDI PLA and the Filter/Codec are powered down. When low, the FDI is active (default). When high, the ear driver and Filter/Codec are powered down. In addition, in ST-BUS mode, the selected output channel is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The output will be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver and Filter/Codec are active if PDFDI is low (default). When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the Rst bit remains high and device remains powered up. A software reset can be removed only by writing this bit low or by means of a hardware reset (PWRST). This bit is useful for quickly programming the Registers to the default Power Reset Values. When this bit is low, the reset condition is removed allowing the registers to be modified. When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a mute state (only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When low the full transmit path functions normally (default). When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a mute state. When low the full receive path functions normally (default). When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in ST-BUS mode. Not used in SSI mode. When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in ST-BUS mode. Not used in SSI mode. 14 Zarlink Semiconductor Inc. MT9160B/61B Control Register 2 CEn ADDRESS = 04h WRITE/READ VERIFY DEn D8 A/µ 6 5 4 7 CEn Data Sheet Smag/ ITU-T 3 CSL2 CSL1 2 1 CSL0 Power Reset Value 0000 0010 0 When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation and is ignored for SSI operation. When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0 on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation. When high, D-channel operates at 8 kb/s. When low, D-channel operates at 16 kb/s (default). When high, A-Law encoding/decoding is selected for the MT9160B/61B. When low, µ-Law encoding/decoding is selected. When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code assignment is selected for the Codec input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate digit inversion (A-Law). DEn D8 A/m Smag/ITU-T CSL2 CSL1 CSL0 Bit Clock rate (kHz) CLOCKin (kHz) Mode 1 1 1 1 0 0 N/A 4096 ST-BUS 128 4096 SSI 1 0 0 0 1 256 4096 SSI 0 512 512 0 0 SSI 1 1536 1536 SSI 0 1 0 0 1 1 2048 2048 SSI (default) 4096 4096 SSI 15 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet C-Channel Register ADDRESS = 05h WRITE/READ C7 C6 C5 C4 C3 C2 C1 C0 7 6 5 4 3 2 1 0 Power Reset Value 1111 1111- write XXXX XXXX - read Micro-port access to the ST-BUS C-Channel information read and write D-Channel Register D7-D0 ADDRESS = 06h WRITE/READ D7 D6 7 6 D5 D4 5 4 D3 D2 D1 D0 3 2 1 0 Power Reset Value 1111 1111- write XXXX XXXX - read Data written to this register will be transmitted every frame, in channel 0, if the DEn control bit is set (address 04h). Received D-Channel data is valid, regardless of the state of DEn. These bits are valid for ST-BUS mode only and are accessible only when IRQ indicates valid access. ADDRESS = 07h WRITE/READ VERIFY Loopback Register PCM/ loopen ANALOG - - - - 7 6 5 4 3 2 - - 1 0 Power Reset Value XXXX 0000 PCM/ANALOG This control bit functions only when loopen is set high. It is ignored when loopen is low. For loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. Data on Din is looped back to Dout without conversion to the analog domain. However, the receive D/A path (from Din to HSPKR ±) still functions. When low, the device is configured for analog-to-analog operation. An analog input signal at M± is looped back to the SPKR± outputs through the A/D and D/A circuits as well as through the normal transmit A/D path (from M± to Dout). loopen When high, loopback operation is enabled and the loopback type is governed by the state of the PCM/ANALOG bit. When low, loopbacks are disabled, the device operates normally and the PCM/ANALOG bit is ignored. Dout Dout M +/- Digital Loopback Analog Loopback PCM/ANALOG = 0 HSPKR +/- Din HSPKR +/- PCM/ANALOG = 1 loopen = 1 Figure 8 - Loopback Signal Flows Note: Bits marked "-" are reserved bits and should be written with logic "0" 16 Zarlink Semiconductor Inc. loopen = 1 MT9160B/61B Data Sheet Applications Figure 9 shows an application in a digital phone set. Various configurations of pair gain drops are depicted in Figures 12a and 12b using the MT9125 and MT9126, respectively. 330 W +5 V + + 330 W M+ 10 mF 0.1 mF 100 K 511 W + Electret Microphone T Av = 1 + 2R T VBias 0.1 mF + M+ T 10 mF R VBias +5 V + 1K R 0.1 mF + Electret Microphone VBias R 100 K Single-ended Amplifier - 511 W M- + Differential Amplifier VBias ( 0.1 mF Typical External Gain AV= 5-10 ) M+ M- 1 mF 0.1 mF 0.1 mF 1 2 100 K +5 V 3 4 5 A/m/IRQ INTEL MCS-51 or MOTOROLA SPI MicroController CS SCLK DATA1 DATA2 DATA2 Motorola Mode only MT9160B 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 75 W +5 V DSTi +5 V DC to DC Converter 150 W 75 W Lin ZT MT8972 DNIC DSTo F0i Twisted Pair Lout C4b 10.24 MHz Figure 9 - Digital Telephone Set 17 Zarlink Semiconductor Inc. M- MT9160B/61B VBias 0.1 mF ( Typical External Gain AV= 5-10 ) 1 mF 0.1 mF 0.1 mF 1 100 K 5 6 A/m/IRQ 7 8 9 CS INTEL MCS-51 or MOTOROLA SPI MicroController SCLK MT9161B 1 10 11 12 DATA1 DATA2 From Subscriber Line Interface 24 23 2 3 4 +5 V Data Sheet 22 21 20 19 18 17 16 15 Output to Subscriber Line Interface +5 V F0od 14 13 DATA2 Motorola Mode only DSTi +5 V DC to DC Converter DSTo Lin From Digital ZT MT8972 DNIC F0i Phone Twisted Pair 0.1 mF Lout VBias C4b From Subscriber Line Interface 1 mF 0.1 mF 1 24 23 2 3 4 +5 V 5 6 A/m/IRQ 7 8 9 CS SCLK DATA1 MT9161B 2 10 11 12 DATA2 22 21 20 19 18 17 16 15 Output to Subscriber Line Interface +5 V 14 13 DATA2 Motorola Mode only +5 V DC to DC Converter DSTi Lin From Digital ZT Phone DSTo MT8972 DNIC F0i Twisted Pair Lout C4b C4 Clock Input Figure 10 - Delayed Frame Pulse of First MT9161B Signalling Second MT9161B 18 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet Absolute Maximum Ratings† Parameter † Symbol Min. Max. Units VDD - VSS - 0.3 7 V VI/VO VSS - 0.3 VDD + 0.3 V ± 20 mA + 150 °C 750 mW 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin (transducers excluded) II/IO 4 Storage Temperature TS 5 Power Dissipation (package) PD - 65 Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated Characteristics Sym. Min. Typ. Max. Units 5 5.25 V Test Conditions 1 Supply Voltage VDD 4.75 2 CMOS Input Voltage (high) VIHC 4.5 VDD V 3 CMOS Input Voltage (low) VILC VSS 0.5 V 4 Operating Temperature TA - 40 + 85 ×C Typ. Max. Units IDDC1 4 20 µA Outputs unloaded, Input signals static, not loaded IDDFT 7.0 10 mA See Note 1. Power Characteristics Characteristics 1 Static Supply Current (clock disabled, all functions off, PDFDI/PDDR=1, PWRST=0) 2 Dynamic Supply Current: Total all functions enabled Sym. Min. Note 1: Power delivered to the load is in addition to the bias current requirements. 19 Zarlink Semiconductor Inc. Test Conditions MT9160B/61B Data Sheet DC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Sym. Min. 3.5 Typ.‡ Max. Units Test Conditions 1 Input HIGH Voltage CMOS inputs VIHC 2 Input LOW Voltage CMOS inputs VILC 3 VBias Voltage Output VBias VDD/2 V Max. Load = 10 kΩ 4 VRef Output Voltage VRef VDD/2-1.9 V No load 5 Input Leakage Current IIZ 0.1 6 Positive Going Threshold Voltage (PWRST only) Negative Going Threshold Voltage (PWRST only) VT+ 7 Output HIGH Current IOH 3 7 mA VOH = 0.9*VDD See Note 1 8 Output LOW Current IOL 5 10 mA VOL = 0.1*VDD See Note 1 9 Output Leakage Current IOZ 0.01 mA VOUT = VDD and VSS 10 Output Capacitance Co 15 pF 11 Input Capacitance Ci 10 pF V 1.5 10 3.7 V mA VIN=VDD to VSS V VT- 1.3 10 V † DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note 1 - Magnitude measurement, ignore signs. Clockin Tolerance Characteristics (ST-BUS Mode) Characteristics 1 C4i Frequency Min. Typ.‡ Max. Units 4095.6 4096 4096.4 kHz Test Conditions (i.e., 100 ppm) † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 20 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet AC Characteristics† for A/D (Transmit) Path - 0 dBm0 = ALo3.17 - 3.17 dB = 1.773Vrms for µ-Law and 0 dBm0 = ALo3.14 - 3.14 dB =1.843Vrms for A-Law, at the Codec (VRef=0.6 volts and VBias=2.5 volts.) Characteristics 1 Analog input equivalent to overload decision 2 Absolute half-channel gain M ± to Dout Sym. Min. ALi3.17 ALi3.14 GAX1 GAX2 Tolerance at all other transmit filter settings (1 to 7 dB) Typ.‡ Max. 7.33 7.6 Units Vp-p Vp-p Test Conditions µ-Law A-Law Both at Codec Transmit filter gain=0 dB setting. TxINC = 0* TxINC = 1* @1020 Hz 5.2 14.5 6.0 15.3 6.8 16.1 dB dB -0.2 ±0.1 +0.2 dB 0.3 0.6 1.6 dB dB dB 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 dB dB dB 0 to -30 dBm0 -40 dBm0 -45 dBm0 3 Gain tracking vs. input level ITU-T G.714 Method 2 GTX -0.3 -0.6 -1.6 4 Signal to total Distortion vs. input level. ITU-T G.714 Method 2 DQX 35 29 24 5 Transmit Idle Channel Noise NCX NPX 6 Gain relative to gain at 1020 Hz 4600 Hz GRX 7 Absolute Delay DAX 360 ms at frequency of minimum delay 8 Group Delay relative to DAX DDX 750 380 130 750 ms ms ms ms 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz 9 Power Supply Rejection f=1020 Hz f=0.3 to 3 kHz f=3 to 4 kHz f=4 to 50 kHz 8.5 -71 -45 -0.25 -0.9 -23 -40 PSSR PSSR1 PSSR2 PSSR3 37 40 35 40 12 -69 dBrnC0 dBm0p -25 -30 0.0 0.25 0.25 -12.5 -25 dB dB dB dB dB dB dB dB dB dB dB µ-Law A-Law ±100 mV peak signal on VDD µ-law PSSR1-3 not production tested † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: TxINC, refer to Control Register 1, address 00h. 21 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet AC Characteristics† for D/A (Receive) Path - 0 dBm0 = ALo3.17 - 3.17 dB = 1.773Vrms for µ-Law and 0 dBm0 = ALo3.14 - 3.14 dB =1.843Vrms for A-Law, at the Codec. (VRef=0.6 volts and VBias=2.5 volts.) Characteristics Sym. 1 Analog output at the Codec full scale ALo3.17 ALo3.14 2 Absolute half-channel gain. Din to HSPKR± GAR1 GAR2 GAR3 GAR4 Tolerance at all other receive filter settings (-1 to -7dB) relative to output at 0 dB setting Min. Typ.‡ Max. 7.225 7.481 Units Vp-p Vp-p Test Conditions µ-Law A-Law -0.8 -6.8 -6.8 -12.8 0 -6 -6 -12 0.8 -5.2 -5.2 -11.2 dB dB dB dB -0.2 ±0.1 +0.2 dB 0.3 0.6 1.6 dB dB dB 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 dB dB dB 0 to -30 dBm0 -40 dBm0 -45 dBm0 DrGain=0, RxINC =1* DrGain=0, RxINC =0* DrGain=1, RxINC =1* DrGain=1, RxINC =0* @ 1020 Hz 3 Gain tracking vs. input level ITU-T G.714 Method 2 GTR -0.3 -0.6 -1.6 4 Signal to total distortion vs. input level. ITU-T G.714 Method 2 GQR 35 29 24 5 Receive Idle Channel Noise NCR NPR 6 Gain relative to gain at 1020 Hz 200 Hz 300 - 3000 Hz 3000 - 3400 Hz 4000 Hz >4600 Hz GRR 7 Absolute Delay DAR 240 ms at frequency of min. delay 8 Group Delay relative to DAR DDR 750 380 130 750 ms ms ms ms 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz 9 Crosstalk CTRT CTTR dB dB G.714.16 ITU-T D/A to A/D A/D to D/A 7 -84 -0.25 -0.90 10 -80 dBrnC0 dBm0p 0.25 0.25 0.25 -12.5 -25 dB dB dB dB dB -74 -80 µ-Law A-Law † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h. 22 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet AC Electrical Characteristics† for Side-tone Path Characteristics 1 Absolute path gain gain adjust = 0 dB 2 Tolerance of other side-tone settings (-9.96 to 9.96 dB) relative to output at 0 dB setting Sym. Typ.‡ Min. GAS1 GAS2 Max. Units -17.43 -16.63 -15.83 -11.43 -10.63 -9.83 -0.5 +/-0.2 dB dB +0.5 Test Conditions RxINC = 0* RxINC = 1* M± inputs to HSPKR± outputs 1000 Hz at STG2=1 dB † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h. Electrical Characteristics† for Analog Outputs Characteristics Sym. Min. Typ.‡ 260 300 ohms 300 pF each pin: % 300 ohms load across HSPKR± (tol-15%), VO≤693mVRMS, RxINC=1*, Rx gain=0 dB 1 EarpIece load impedance EZL 2 Allowable earpiece capacitive load ECL 3 Earpiece harmonic distortion ED Max. Units 0.5 Test Conditions across HSPKR± HSPKR+, HSPKR- † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: RxINC, refer to Control Register 1, address 00h. Electrical Characteristics† for Analog Inputs Characteristics 1 Sym. Min. Typ.‡ Max. Units Test Conditions Maximum input voltage without overloading Codec across M+/M- 2.90 1.03 VIOLH Vp-p Vp-p TxINC = 0, A/µ = 0* TxINC = 1, A/µ = 1* Tx filter gain=0 dB setting 50 kW M+/M2 Input Impedance ZI † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: TxINC, refer to Control Register 1, address 00h. 23 Zarlink Semiconductor Inc. to VSSA MT9160B/61B Data Sheet AC Electrical Characteristics† - ST-BUS Timing (See Figure 11) Characteristics Sym. Typ.‡ Min. Max. Units 1 C4i Clock Period tC4P 244 ns 2 C4i Clock High period tC4H 122 ns 3 C4i Clock Low period tC4L 122 ns 4 C4i Clock Transition Time tT 20 ns 5 F0i Frame Pulse Setup Time tF0iS 40 ns 6 F0i Frame Pulse Hold Time tF0iH 40 ns 7 Delayed Frame Pulse delay after C4i rising tF0odS 20 50 ns 8 Delayed Frame Pulse hold time from C4i rising tF0odH 20 50 ns 9 DSTo Delay tDSToD 100 125 ns 10 DSTi Setup Time tDSTiS 20 Test Conditions CL = 50 pF, 1 kΩ load.* ns 50 ns 11 DSTi Hold Time tDSTiH † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: All conditions → data-data, data-HiZ, HiZ-data. tC4P C4i tT 1 bit cell tT tC4H tC4L 70% 30% tDSToD DSTo 70% 30% tDSTiS DSTi 70% 30% tT F0i F0od tDSTiH tF0iS tF0iH tT 70% 30% tF0odS tF0odH NOTE: Levels refer to %VDD 70% 30% 64 Clock Periods Figure 11 - ST-BUS Timing Diagram 24 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet AC Electrical Characteristics† - SSI BUS Synchronous Timing (See Figure 12) Characteristics Typ.‡ Max. Units Test Conditions 1953 ns BCL=4096 kHz to 512 kHz ns BCL=4096 kHz 122 ns BCL=4096 kHz ns Note 1 tENW 20 8 x tBCL ns Note 1 tENWD 8 x tBCL ns Note 1 Sym. Min. 1 BCL Clock Period tBCL 244 2 BCL Pulse Width High tBCLH 122 3 BCL Pulse Width Low tBCLL 4 BCL Rise/Fall Time tR/tF 5 Strobe Pulse Width 6 Delayed Strobe Pulse Width 7 Strobe setup time before BCL falling tSSS 70 tBCL-80 ns 8 Strobe hold time after BCL falling tSSH 80 tBCL-80 ns 9 Delayed Strobe Pulse delay after BCL rising tDSTBR 20 40 ns Note 1 10 Delayed Strobe Pulse hold time after BCL rising tDSTBF 20 40 ns Note 1 11 Dout High Impedance to Active Low from Strobe rising tDOZL 50 ns CL=150 pF, RL=1 K 12 Dout High Impedance to Active High from Strobe rising tDOZH 50 ns CL=150 pF, RL=1 K 13 Dout Active Low to High Impedance from Strobe falling tDOLZ 50 ns CL=150 pF, RL=1 K 14 Dout Active High to High Impedance from Strobe falling tDOHZ 50 ns CL=150 pF, RL=1 K 15 Dout Delay (high and low) from BCL rising tDD 50 ns CL=150 pF, RL=1 K 16 Din Setup time before BCL falling tDIS 20 ns 17 Din Hold Time from BCL falling tDIH 50 ns † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. NOTE 1: Not production tested, guaranteed by design. 25 Zarlink Semiconductor Inc. MT9160B/61B Data Sheet tBCL tBCLH tR tF CLOCKin 70% (BCL) 30% tBCLL tDIS Din tDIH 70% 30% tDD tDOZL Dout 70% 30% tDOZH STB tDOLZ tDOHZ tSSH tENW tSSS 70% 30% tDSTBR tDSTBF 70% STBd 30% tENWD NOTE: Levels refer to % VDD (CMOS I/O) Figure 12 - SSI Synchronous Timing Diagram AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (See Figure 13) Characteristics 1 Bit Cell Period 2 Frame Jitter Sym. Typ.‡ Min. Max. 7812 3906 TDATA Units ns ns Test Conditions BCL=128 kHz BCL=256 kHz Tj 600 ns 3 Bit 1 Dout Delay from STB going high tdda1 Tj+600 ns CL=150 pF, RL=1 K 4 Bit 2 Dout Delay from STB going high tdda2 600+ TDATA-Tj 600+ TDATA 600 + TDATA+Tj ns CL=150 pF, RL=1 K 5 Bit n Dout Delay from STB going high tddan 600 + (n-1) x TDATA-Tj 600 + (n-1) x TDATA 600 + (n-1) x TDATA+Tj ns CL=150 pF, RL=1 K n=3 to 8 TDATA1 TDATA-Tj TDATA+Tj ns 7 Din Bit n Data Setup time from STB rising tSU TDATA\2 +500ns-Tj +(n-1) x TDATA ns 8 Din Data Hold time from STB rising tho TDATA\2 +500ns+Tj +(n-1) x TDATA ns 6 Bit 1 Data Boundary † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. NOTE 1: Not production tested, guaranteed by design. 26 Zarlink Semiconductor Inc. n=1-8 MT9160B/61B Data Sheet Tj STB 70% 30% tdda2 tdha1 tdda1 Dout 70% Bit 1 30% Bit 2 Bit 3 TDATA TDATA1 tho tsu Din 70% D2 D1 30% TDATA/2 TDATA D3 TDATA NOTE: Levels refer to % VDD (CMOS I/O) Figure 13 - SSI Asynchronous Timing Diagram AC Electrical Characteristics† - Microport Timing (See Figure 14) Characteristics Sym. Min. Typ.‡ Max. Units 1 Input data setup tIDS 100 ns 2 Input data hold tIDH 30 ns 3 Output data delay tODD 4 Serial clock period tCYC 500 1000 ns 5 SCLK pulse width high tCH 250 500 ns 6 SCLK pulse width low tCL 250 500 ns 7 CS setup-Intel tCSSI 200 ns 8 CS setup-Motorola tCSSM 200 ns 9 CS hold tCSH 100 ns 10 CS to output high impedance tOHZ 100 100 ns ns Test Conditions CL = 150 pF, RL = 1 K * CL = 150 pF, RL = 1 K † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note: All conditions → data-data, data-HiZ, HiZ-data. 27 Zarlink Semiconductor Inc. MT9160B/61B 2.0V Data Sheet DATA INPUT 0.8V tIDS HiZ 0.8V tIDH 10% Intel Mode = 0 tODD tCYC tCH 90% 2.0V DATA OUTPUT 2.0V SCLK 0.8V tCSSI tOHZ tCL 2.0V CS 0.8V tCSSM tCSH tCH 2.0V SCLK Motorola Mode = 00 0.8V tCL tCYC tODD tIDH DATA OUTPUT 2.0V 0.8V 90% HiZ 10% tIDS 2.0V DATA INPUT 0.8V NOTE: % refers to % VDD Figure 14 - Microport Timing 28 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE