PAC1710/20
Single and Dual High-Side Current-Sense Monitor with
Power Calculation
Features
Description
• Single and Dual High-Side Current Sensor
- Current measurement is integrated over 2.5 ms
to 2.6 seconds with up to 11-bit resolution
- 1% current measurement accuracy in
positive range
- Measures VSOURCE voltages
• Calculates Power
• VSOURCE Voltage Range 0V to 40V
• Bidirectional Current Sensing
• Auto-Zero Input Offset Voltage
• Digital Averaging
- Adjustable sampling time and resolution
• 5 µA Typical Standby Current
• Programmable Sense Voltage Range
- ±10 mV, ±20 mV, ±40 mV, and ±80 mV
• Power Supply Range 3.0V to 5.5V
• Wide Temperature Operating Range: -40°C to
+85°C
• ALERT Output for Voltage and Current out of
Limit Transients Between Sampling Interval
• SMBus 2.0 Communications Interface
- Block Read and Block Write
- Address selectable by resistor decode
• Sample Time Configurable from 2.5 ms to 320 ms
- With averaging effective sampling times up to
2.6 seconds
• 10-Lead 3 x 3 mm VDFN package
The PAC1710/20 are single and dual high-side
bidirectional current sensing monitors with precision
voltage measurement capabilities. Each sensor
measures the voltage developed across an external
sense resistor to represent the high-side current of a
battery or voltage regulator. The PAC1710/20 also
measures the SENSE+ pin voltage and calculates
average power over the integration period. The
PAC1710/20 can be programmed to assert the ALERT
pin when high and low limits are exceeded for Current
Sense and Bus Voltage.
The PAC1710/20 device is good for measuring
dynamic power. The long integration time allows for
extending system polling cycles without losing any
power consumption information. In addition the alert
ensures that transient events are captured between the
polling cycles.
Available in a RoHS compliant 3 x 3 mm 10-pin VDFN
package.
Package Types
PAC1710/20
3x3 VDFN*
SENSE1+ 1
SENSE1- 2
SENSE2+†
3
SENSE2-† 4
GND 5
10 VDD
EP
11
9 SMCLK
8 SMDATA
7 ALERT
6 ADDR_SEL
Applications
•
•
•
•
•
Notebook and Desktop Computers
Industrial
Power Management Systems
Embedded Applications
Servers
2015-2016 Microchip Technology Inc.
*Includes Exposed Thermal Pad (EP), see Table 3-1
†PAC1720 only.
DS20005386B-page 1
PAC1710/20
Device Block Diagram
VDD
SENSE2-
SENSE2+
SENSE1-
SENSE1+
PAC1720 only
Power
Management
ADDR_SEL
Current Limits
Current
Measurement
Current
Measurement
Current Registers
Configuration
Configuration
Analog
MUX
SMBus
Interface
SMCLK
SMDATA
Power Register
ALERT
Voltage
Voltage
Measurement
Measurement
Voltage
Registers
Voltage Limits
GND
DS20005386B-page 2
2015-2016 Microchip Technology Inc.
PAC1710/20
1.0
ELECTRICAL CHARACTERISTICS
1.1
Electrical Specifications
Absolute Maximum Ratings(†)
VDD pin............................................................................................................................................................-0.3 to 6.0V
Voltage on SENSE- and SENSE+ pins .............................................................................................................-42 to 42V
Voltage on any other pin to GND ..................................................................................................-GND-0.3 to VDD+0.3V
Voltage between Sense pins (|(SENSE+ – SENSE-)|)................................................................................................40V
Input current to any pin except VDD ......................................................................................................................+10 mA
Output short-circuit current.............................................................................................................................. Continuous
Package Power Dissipation (Note) ............................................................................................ 0.5W up to TA = 85°C/W
Junction to Ambient (J-A) .....................................................................................................................................78°C/W
Operating Ambient Temperature Range ......................................................................................................... -40 to 85°C
Storage Temperature Range......................................................................................................................... -55 to 150°C
ESD Rating – SMCLK, SMDATA, and ALERT pins – HBM.....................................................................................8000V
SD Rating – all other pins – HBM............................................................................................................................2000V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
Note:
The Package Power Dissipation specification assumes a recommended thermal via design consisting of a
2 x 3 matrix of 0.3 mm (12 mil) vias at 0.9 mm pitch connected to the ground plane with a 1.6 mm x 2.3 mm
thermal landing.
2015-2016 Microchip Technology Inc.
DS20005386B-page 3
PAC1710/20
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 3V to 5.5V, VSOURCE = 0V to 40V; typical values are at TA = +25°C, VDD = 3.3V, VSOURCE = 24V,
VSENSE = (SENSE+ – SENSE-) = 0V; Current Sense Full Scale Range = 80 mV unless otherwise noted
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
Power Supply
VSOURCE
0
—
40
V
VDD Range
Voltage on SENSE+
VDD
3.0
—
5.5
V
VDD Pin Supply
Current (PAC1720)
IDD
—
0.525
1.3
mA
Both measurement channels
enabled. Continuous conversions
(see Table 4-1)
—
13
50
µA
Both measurement channels
enabled. One conversion per
second (see Table 4-1).
VSRC_SAMP_TIME = 2.5 ms
CS_SAMP_TIME = 2.5 ms
No SMBus communications
—
360
900
µA
Continuous Conversions
(see Table 4-1)
—
10
35
µA
One conversion per second
(see Table 4-1).
VSRC_SAMP_TIME = 2.5 ms
CS_SAMP_TIME = 2.5 ms
No SMBus communications
VDD Pin Supply
Current (PAC1710)
IDD
VDD Rise Rate
VDD_RISE
0.03
VDD Standby Current
IDD_STBY
—
5.5
15
V/ms 0 to 3V in 100 ms
µA
Standby state
Common-mode voltage on SENSE
pins, referenced to ground
Analog Input Characteristics
SENSE+/SENSEPins Common-Mode
Voltage Range
VCM
0
—
40
V
VSENSE Differential
Input Voltage Range
VDIFF
-80
—
+80
mV
Current-Sense Power
Supply Rejection
Ratio
PSRR_CS
—
10
—
µV/V
Full-Scale Range (±)
(see Section 4.4
“Current
Measurement”)
FSR
-10
—
10
mV
1 LSB = 4.885 µV
11-bit data resolution
-20
—
20
mV
1 LSB = 9.77 µV
11-bit data resolution
-40
—
40
mV
1 LSB = 19.54 µV
11-bit data resolution
-80
—
80
mV
1 LSB = 39.08 µV
11-bit data resolution
VSENSE _CMRR
80
100
—
dB
Common-Mode Rejection,
0V < VSOURCE < 40V
SENSE+/SENSEPins Common-Mode
Voltage Range
VCM
0
—
40
V
Common-mode voltage on SENSE
pins, referenced to ground
VBUS Gain Accuracy
VBUS_GAIN_ERR
—
—
±0.4
%
Measured at ADC output, Gain = 1
Common-Mode
Rejection
DS20005386B-page 4
Voltage between SENSE+ and
SENSE- pins
3.0V < VDD < 5.5V
2015-2016 Microchip Technology Inc.
PAC1710/20
TABLE 1-1:
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 3V to 5.5V, VSOURCE = 0V to 40V; typical values are at TA = +25°C, VDD = 3.3V, VSOURCE = 24V,
VSENSE = (SENSE+ – SENSE-) = 0V; Current Sense Full Scale Range = 80 mV unless otherwise noted
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
SENSE+, SENSE- Pin ISENSE +, ISENSELeakage Current
—
—
1.0
µA
VBUS = 24V, VSENSE = 0V
Sleep state
SENSE+, SENSE- Pin ISENSE +, ISENSELeakage Current
—
—
1.0
µA
VDD = 0V
SENSE+ Pin Bias
Current
ISENSE +
—
100
150
µA
-80 mV < VSENSE < 80 mV
Active state
SENSE- Pin Bias
Current
ISENSE-
—
0.1
1
µA
-80 mV < VSENSE < 80 mV
Active state
—
±15
—
µV
FSR = ±10 mV
—
±15
—
µV
FSR = ±20 mV
—
±20
—
µV
FSR = ±40 mV
—
±40
—
µV
FSR = ±80 mV
—
±0.5
±1
%
FSR
FSR = 0 to +10 mV
—
±0.3
±0.6
%
FSR
FSR = 0 to +20 mV
—
±0.2
±0.4
%
FSR
FSR = 0 to +40 mV
—
±0.2
±0.4
%
FSR
FSR = 0 to +80 mV
-1
-1.3
-1.6
%
FSR
FSR = -10 mV to 0
-1
-1.3
-1.6
%
FSR
FSR = -20 mV to 0
-1
-1.3
-1.6
%
FSR
FSR = -40 mV to 0
-1.6
-2
-2.4
%
FSR
FSR = -80 mV to 0
PSRR
—
10
—
mV/V 3.0V < VDD < 5.5V
VSOURCE_ ERR
—
0.15
0.3
%
FSV
Current-Sense Offset Error Voltage
Offset Error Voltage
(referred to input)
VOS
Current-Sense Total Measurement Error
Total Error
(positive range)
(see Section 4.4
“Current
Measurement”)
Total Error
(negative range)
(see Section 4.4
“Current
Measurement”)
VSENSE _TOT_ERR
VSENSE _TOT_ERR
VSOURCE Voltage Measurement
Power Supply
Rejection Ratio
VSOURCE Error (±)
2015-2016 Microchip Technology Inc.
DS20005386B-page 5
PAC1710/20
TABLE 1-1:
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 3V to 5.5V, VSOURCE = 0V to 40V; typical values are at TA = +25°C, VDD = 3.3V, VSOURCE = 24V,
VSENSE = (SENSE+ – SENSE-) = 0V; Current Sense Full Scale Range = 80 mV unless otherwise noted
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Conditions
Total Power Ratio
Measurement Error
(±)
(positive range)
PRATIO _ERR
—
—
1
%
FSR
FSR = 0 to +10 mV, 0 to +20 mV,
0 to +40 mV, or 0 to +80 mV
Total Power Ratio
Measurement Error
(±)
(negative range)
PRATIO _ERR
—
—
2
%
FSR
FSR = -10 mV to 0, -20 mV to 0,
-40 mV to 0, or -80 mV to 0
tCONV_P
—
—
220
ms
VPULLUP
3.0
—
5.5
V
tCOMM
—
—
25
ms
Input High Voltage
VIH
2.0
—
—
V
Input Low Voltage
VIL
—
—
0.8
V
Output Low Voltage
VOL
—
—
0.4
V
OD pin pulled to VPULLUP
3 mA current sink
Leakage Current (±)
ILEAK
—
—
5
µA
Powered or unpowered
TA < +85°C
Power Ratio
First Power Ratio
Ready
Time after power-up before PRATIO
updated
Digital I/O Pins (SMCLK, SMDATA, ALERT)
Pull-up Voltage Range
Time to First
Communications
DS20005386B-page 6
Pull-up voltage for SMBus and
ALERT pins
SMCLK, SMDATA
OD pins pulled up to VPULLUP
2015-2016 Microchip Technology Inc.
PAC1710/20
TABLE 1-2:
SMBUS MODULE SPECIFICATIONS
Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40°C to +85°C,
VDD = 3V to 5.5V, VBUS = 0V to 32V; Typical values are at TA = +25°C, VDD = 3.3V, VBUS = 24V,
VSENSE = (SENSE+ – SENSE-) = 0V
Characteristic
Sym.
Min.
Typ.
Max.
Units
CIN
—
4
10
pF
Conditions
SMBus Interface
Input Capacitance
SMBus Timing
fSMB
10
—
400
kHz
Spike Suppression
tSP
—
—
100
ns
Bus Free Time Stop to
Start
tBUF
1.3
—
—
µs
tSU:STA
0.6
—
—
µs
Start Hold Time
tHD:STA
0.6
—
—
µs
Stop Setup Time
tSU:STO
0.6
—
—
µs
Clock Frequency
Start Setup Time
Data Hold Time
tHD:DAT
0
—
—
µs
When transmitting to the master
Data Hold Time
tHD:DAT
0.3
—
—
µs
When receiving from the master
Data Setup Time
tSU:DAT
0.6
—
—
µs
Clock Low Period
tLOW
1.3
—
—
µs
Clock High Period
tHIGH
0.6
—
—
µs
Clock/Data Fall Time
tFALL
—
—
300
ns
tRISE
—
—
300
ns
Min = 20 + 0.1 CLOAD ns
CLOAD
—
—
400
pF
Total per bus line
Clock/Data Rise Time
Capacitive Load
TLOW
THIGH
THD:STA
TRISE
SMCLK
T
THD:STA HD:DAT
Min = 20 + 0.1 CLOAD ns
TSU:STO
TFALL
TSU:DA
TSU:STA
T
SMDATA
TBUF
P
FIGURE 1-1:
S
S - Start Condition
S
P - Stop Condition
P
SMBus Timing.
2015-2016 Microchip Technology Inc.
DS20005386B-page 7
PAC1710/20
NOTES:
DS20005386B-page 8
2015-2016 Microchip Technology Inc.
PAC1710/20
2.0
TYPICAL OPERATING CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, maximum values are at TA = -40°C to +85°C, VDD = 3V to 5.5V, VSOURCE = 0V to
40V; typical values are at TA = +25°C, VDD = 3.3V, VSOURCE = 24V, VSENSE = (SENSE+ – SENSE-) = 0V.
120.000
440.0
Idd (μA)
400.0
380.0
360.0
T = +85˚C
T = +25˚C
T = -40˚C
340.0
ISENSE+ Current (μA)
100.000
420.0
80.000
60.000
40.000
20.000
0.000
-20.000
320.0
3.0
3.3
3.6
4.5
5.0
0
5.5
VDD (V)
20
30
40
50
VBUS (V)
FIGURE 2-1:
IDD vs. VDD, Continuous
Conversions (PAC1710).
FIGURE 2-4:
ISENSE+ Pin Current vs.
VBUS (TA = -40°C to +85°C).
20.0
16.0
14.0
12.0
T = +85˚C
10.0
T = +25˚C
ISENSE+ Current (μA)
18.0
IDD (μA)
10
T = -40˚C
102.0
101.5
101.0
100.5
100.0
99.5
99.0
98.5
98.0
97.5
T = +85˚C
T = +25˚C
T = -40˚C
8.0
3.0
3.3
3.6
VDD (V)
4.5
5.0
5.5
VSENSE (% of full scale)
13.000
12.000
11.000
10.000
9.000
8.000
7.000
6.000
5.000
4.000
3.000
FIGURE 2-5:
(80 mV Range).
ISENSE+ Pin Bias Current
0.20
0.15
T = +85˚C
T = +25˚C
T = -40˚C
3.0
FIGURE 2-3:
(PAC1710)
3.3
3.6
VDD (V)
4.5
5.0
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
5.5
IDD vs. VDD, Standby Mode
2015-2016 Microchip Technology Inc.
ISENSE- Current (μA)
IDD (μA)
FIGURE 2-2:
IDD vs. VDD, One
Conversion per Second, Lowest Resolution
(PAC1710).
VSENSE (% of full scale)
FIGURE 2-6:
ISENSE- Pin Bias Current
(80 mV Range, TA = -40°C to +85°C).
DS20005386B-page 9
PAC1710/20
0.010
580.0
0.005
IDD (μA)
560.0
540.0
520.0
500.0
T = +85˚C
T = +25˚C
T = -40˚C
480.0
460.0
3.0
3.3
3.6
4.5
5.0
ISENSE+ Current [μA]
600.0
0.000
-0.005
-0.010
-0.015
-0.020
5.5
VSENSE (% of full scale)
VDD (V)
FIGURE 2-7:
IDD vs. VDD, Continuous
Conversions (PAC1720).
0.010
20.000
0.005
IDD (μA)
16.000
14.000
T = +85˚C
T = +25˚C
T = -40˚C
12.000
10.000
3.0
3.3
3.6
VDD (V)
4.5
5.0
ISENSE+ Current (μA)
22.000
18.000
0.000
-0.005
-0.010
-0.015
-0.020
5.5
VSENSE (% of full scale)
FIGURE 2-8:
IDD vs. VDD, One
Conversion per Second, Lowest Resolution
(PAC1720).
IDD (μA)
FIGURE 2-10:
ISENSE+ Pin Leakage
Current, TA = -40°C to +85°C.
13.000
12.000
11.000
10.000
9.000
8.000
7.000
6.000
5.000
4.000
3.000
FIGURE 2-11:
ISENSE- Pin Leakage
Current, TA = -40°C to +85°C.
T = +85˚C
T = +25˚C
T = -40˚C
3.0
3.3
3.6
4.5
5.0
5.5
VDD (V)
FIGURE 2-9:
(PAC1720).
DS20005386B-page 10
IDD vs. VDD, Standby Mode
2015-2016 Microchip Technology Inc.
PAC1710/20
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN DESCRIPTIONS
PAC1710/20
3x3 VDFN
Symbol
Type
(See Table 3-2)
1
SENSE1+
AIO40
VBUS1/VSENSE1+ input
2
SENSE1-
AIO40
VSENSE1- input
3
SENSE2+
AIO40
VBUS2/VSENSE2+ input
4
SENSE2-
AIO40
VSENSE2- input
5
GND
Power
Ground
6
ADDR_SEL
AIO
Selects SMBus/I2C™ address
SMBus Alert Pin
7
ALERT
DO
8
SMDATA
DIOD
9
SMCLK
DI
10
VDD
Power
11
EP
—
TABLE 3-2:
Pin Type
PIN TYPES DESCRIPTION
Description
Power
This pin is used to power the device
AIO40
Analog Input/Output – this pin is used as
an I/O for analog signals.
Maximum voltage is 40V.
AIO5
DI
DIOD
3.1
Analog Input/Output – this pin is used as
an I/O for analog signals.
Maximum voltage is 5V.
SMDATA: SMBus - requires pull-up resistor
SMCLK: SMBus - requires pull-up resistor
Positive power supply voltage
Not internally connected, but recommend grounding.
3.5
SMBus ALERT (ALERT)
This pin is the SMBus ALERT pin that is asserted under
fault conditions.
3.6
SMBus Data (SMDATA)
This is the bidirectional SMBus data pin. This pin is
open drain, and requires a pull-up resistor.
3.7
SMBus Clock (SMCLK)
Digital Input – this pin is used for digital
inputs
This is the SMBus clock pin. This pin is open drain, and
requires a pull-up resistor.
Digital Input/Output Open Drain – this pin
is used for digital I/O and is open drain
3.8
Sense1+/Sense1-
These two pins form the differential input for measuring
voltage across a sense resistor in the application. The
positive input (Sense1+) also acts as the input pin for
bus voltage.
3.2
Description
Positive Power Supply Voltage
(VDD)
Power supply input pin for the device.
3.9
Exposed Thermal Pad (EP)
This pad should be connected to ground for noise
immunity.
Sense2+/Sense2- (PAC1720 only)
These two pins form the differential input for measuring
voltage across a sense resistor in the application. The
positive input (Sense2 +) also acts as the input pin for
bus voltage.
3.3
Ground (GND)
System ground.
3.4
Address Selection (ADDR_SEL)
Address selection for the SMBus Slave address, based
on the pull-down resistor.
2015-2016 Microchip Technology Inc.
DS20005386B-page 11
PAC1710/20
NOTES:
DS20005386B-page 12
2015-2016 Microchip Technology Inc.
PAC1710/20
4.0
The PAC1710/20 measures the differential voltage
across an external sense resistor, digitizes it with a
variable resolution (6-bit to 11-bit plus sign)
Sigma-Delta ADC, and transmits via the SMBus or the
I2C™ protocol. The current range allows for large
variations in measured current with high accuracy and
low voltage drop across the resistor.
GENERAL DESCRIPTION
The PAC1710/20 is a bidirectional high-side
current-sensing device with precision voltage
measurement capabilities. It measures the voltage
developed across an external sense resistor to
represent the high-side current of a battery or voltage
regulator. The PAC1710/20 also measures the
SENSE1+ and SENSE2+ pin voltages (VSOURCE) and
calculates average power over the integration period.
The PAC1710/20 has programmable high and low
limits for current sense and bus voltage with a
maskable ALERT signal to the host when an
out-of-limit measurement occurs.
A system diagram is shown in Figure 4-1.
Sense
Resistors
SENSE2+*
SENSE1-
100k – 1M
SENSE1+
0V – 40V
SMCLK
3.0V to
5.0V
Host
MCU
SMDATA
VDD
5.2V Zener
3.0V to 5.5V
SENSE2-*
VSOURCE
ALERT
GND
ADDR_SEL
PAC1710/20
Note 1: The device MUST be biased PRIOR to applying VSOURCE. Failure to do so will result in damage.
2: The unpowered bias on VDD must be greater than VDD, if VDD will be removed prior to VSOURCE.
*PAC1720 only.
FIGURE 4-1:
PAC1710/20 System Diagram.
2015-2016 Microchip Technology Inc.
DS20005386B-page 13
PAC1710/20
4.1
Power States
The PAC1710/20 has three states of operation:
• Active – The PAC1710/20 initiates conversion
cycles for the programmed conversion rate.
• Standby – This is the lowest power state. There
are no conversion cycles. The majority of circuitry
is powered-down to reduce supply current to a
minimum. The SMBus is active and the part will
return requested data. To enter the Standby state,
disable all measurements (see Register 6-1).
• One-Shot – While the device is in the Standby
state, the host can initiate a conversion cycle on
demand (see Register 6-3). After the conversion
cycle is complete, the device will return to the
Standby state.
4.2
Conversion Cycle
The conversion cycle is the period of time in which the
measurements are taken and the data is updated. In the
Active state, individual measurement can be disabled.
In the Standby state, all measurements are updated.
During the conversion cycle, both channels on the
PAC1720 begin taking measurements at the same time.
In both devices, the VSENSE sample is taken first for its
programmed sample time. Then, the VSOURCE sample
is taken for its programmed sample time. Digital
averaging may be applied to average the last 2-8
samples. Sample time and digital averaging have
separate controls for VSENSE and VSOURCE as well as
for each channel, in the case of PAC1720. (see
Register 6-7 and Register 6-8).
At the end of the conversion cycle, the enabled
measurements are updated. The Power Ratio, High
Limit Status (which includes a CONV_DONE status bit),
and Low Limit Status registers are always updated. The
ALERT pin will be asserted, by default, if any out-of-limit
conditions exist (see Section 4.7 “ALERT Output”).
4.3
4.4
Current Measurement
The PAC1710/20 includes one or two high-side current
sensing circuits. These circuits measure the voltage
(VSENSE) induced across a fixed external current sense
resistor (RSENSE) and stores the voltage as a signed
11-bit (by default) number in the Sense Voltage registers.
The PAC1710/20 current sensing operates in one of
four bipolar Full-Scale Ranges (FSR): ±10 mV,
±20 mV, ±40 mV, or ±80 mV (see Section 4.4
“Current Measurement”). The default FSR is ±80 mV.
Full-Scale Current (FSC) can be calculated from
Equation 4-1.
EQUATION 4-1:
FSR
FSC = ---------------------R SENSE
Where:
FSC
=
Full-scale current
FSR
=
±10 mV, ±20 mV, ±40 mV, or ±80 mV
(see Table 4-6)
RSENSE
=
External sense resistor value
The actual current through RSENSE can then be
calculated using Equation 4-2.
EQUATION 4-2:
If the actual sampling time for both measurements
(VSOURCE and VSENSE) is greater than 1/conversion
rate for either channel, the PAC1710/20 will override
the programmed conversion rate and operate in
continuous mode.
DS20005386B-page 14
BUS CURRENT
V SENSE
I BUS = FSC ----------------------------------Denominator
Where:
IBUS
=
Actual bus current
FSC
=
Full-scale current value (from
Equation 4-1)
VSENSE
=
The value read from the Sense
Voltage Registers (in decimal),
ignoring the four lowest bits
which are always zero (see
Register 6-10 and
Register 6-11 for PAC1720)
Denominator
=
Determined by the sample time,
as shown in Table 4-5.
Conversion Rate
For power management in the Active state, a conversion
rate can be programmed. Conversion rate specifies how
often measurement data should be updated. Once per
second is the lowest setting (see Register 6-2).
FULL-SCALE CURRENT
As an example, suppose the system is drawing 1.65A
through a 10 mΩ resistor, the FSR is set for ±20 mV,
and sample time is 80 ms. Using Equation 4-1, the FSC
is 2A. The measured VSENSE is 1.65A 10 mΩ =
16.5 mV. This value of VSENSE is represented in the
Sense
Voltage
Registers
as
69_8h
(0110_1001_1000b or 1688d) ignoring the 4 lower
bits of the low byte as these are always 0. This value,
when applied to Equation 4-2, results in an IBUS current
of 1.649A.
2015-2016 Microchip Technology Inc.
PAC1710/20
For a negative voltage, the Sense Voltage Registers
are read as 96_0h (again ignoring the lower 4 bits of the
low byte as these are always 0). To calculate current,
the binary value is first converted from two’s
complement by inverting the bits and adding one:
96_80h = 1001_0110_1000b. Inverting equals
0110_1001_0111b (69_7h) and adding one gives
0110_1001_1000b (69_8h).
This results in the same calculated value as in the
positive voltage case.
4.5
Voltage Measurement
The pin voltage is measured on the supply side of the
appropriate SENSE+ pin and stored as an unsigned
11-bit number in the VSOURCE Voltage Registers as
VSOURCE (see Register 6-12).
Full-Scale Voltage (FSV) is given by the maximum
value of the VSENSE Voltage Registers:
EQUATION 4-3:
FULL-SCALE VOLTAGE
40
FSV = 40 – ----------------------------------Denominator
Where:
FSV
=
Full scale voltage
Denominator
=
determined by the sample time,
as shown in Table 4-2
Actual voltage at SENSE+ can be calculated using
Equation 4-4.
EQUATION 4-4:
BUS VOLTAGE
V SOURCE
V SOURCE_PIN = FSV ----------------------------------Denominator
As an example using 10-bit resolution, suppose that
the actual pin voltage is 24V. The VSOURCE Voltage
Registers will report a value of 99_80h
(1001_1001_10XX_XXXXb) in 10-bit resolution
(default). When reading the data, the lower 5 bits are
always ignored. Because the default operation is to
measure the VSOURCE voltage with 10-bit resolution,
the sixth bit is likewise ignored. Therefore, decoding
the upper 10 bits results in a decimal value of 614. This
value, when applied in Equation 4-3, results in
VSOURCE_PIN equal to 23.98V.
As an example using 11-bit resolution, suppose that the
actual pin voltage is 10.65V. The VSOURCE Voltage
Registers will report a value of 44_10h
(0100_0100_001X_XXXXb). Because the lower 5 bits
are ignored, the decimal result is 545d. This value,
when applied in Equation 4-4, results in VSOURCE_PIN
equal to 10.64V.
The VSOURCE voltage may also be determined by
scaling each bit set by the indicated bit weighting as
described in Section 4.11 “VSOURCE Data
representation”.
4.6
Power Calculation
The PAC1710/20 may be used to determine the
average power provided at the source side of SENSE+
(SENSE1+ and SENSE2+) using the value PRATIO,
contained in the Power Ratio Registers (see
Register 6-14). The value represents the percentage of
maximum calculable power.
PRATIO is mathematically generated by multiplying the
absolute values of VSENSE and VSOURCE (see
Section 4.4
“Current
Measurement”
and
Section 4.5 “Voltage Measurement”) and is stored
as a 16-bit number. PRATIO is updated whenever either
VSENSE or VSOURCE is updated.
Full-scale power can be calculated from Equation 4-5.
Where:
VSOURCE_PIN
=
The actual voltage on the
SENSE1+/SENSE2+ pin
EQUATION 4-5:
FSV
=
The full-scale voltage (from
Equation 4-3)
Where:
VSOURCE
=
The value read from the
VSOURCE Voltage Registers (in
decimal), ignoring the lowest
five bits which are always zero
(see Section 4.11 “VSOURCE
Data representation”).
Denominator
=
FULL-SCALE POWER
FSP = FSC FSV
FSP
=
The full-scale power
FSC
=
The full-scale current (from Equation 4-1)
FSV
=
The full-scale voltage (from Equation 4-3)
Determined by the sample time,
as shown in Table 4-2
2015-2016 Microchip Technology Inc.
DS20005386B-page 15
PAC1710/20
EQUATION 4-6:
BUS POWER
P RATIO
P BUS = FSP ---------------------65 535
Where:
PBUS
=
The actual power provided by the
source measured at SENSE+
FSP
=
the full-scale power (from
Equation 4-5)
PRATIO
=
the value read from the Power Ratio
Registers (in decimal). See
Register 6-14 and Register 6-15
As an example, suppose that the actual pin voltage is
10.65V, the current through a 10 mΩ resistor is 1.65A,
the FSR is set for ±20 mV, and the sample times are
the defaults. The FSC value is 2A per Equation 4-1.
The FSV value is 39.96V per Equation 4-4. Using
Equation 4-5, the FSP value is 79.92W. Applying P = V
I, the expected power is 17.57W which is 21.98% of
the FSP value.
Reading the Power Ratio Registers will report PRATIO
as 38_47h (0011_1000_0100_0111b or 14,407d).
Using Equation 4-6, this value results in a calculated
bus power of 17.57W which is ~21.98% of the FSP
value.
4.7
ALERT Output
The ALERT pin is an open-drain output and requires a
pull-up resistor to VPULLUP.
4.8
The Conversion Rate controls how often VSENSE,
VSOURCE, PRATIO and the status bits are updated in the
Active state (see Table 4-1). The conversion rate
should only be updated when the PAC1710/20 is in the
Standby state. To do this, disable the measurements in
the Configuration Register 00h, wait for the conversion
cycle to complete by monitoring the XMEAS_DIS bits in
00h until they stay set to ‘1’, change the conversion
rate, and then enable the desired measurements.
TABLE 4-1:
Conversion Rate
The ALERT pin can be asserted for 5 μs when all
measurements are finished (if enabled by setting
CONV_DONE_EN, see Register 6-1).
DS20005386B-page 16
1
0
0
0
1 per sec
0
1
2 per sec
1
0
4 per sec
1
1
Continuous (default)
4.9
Sampling Time and Resolution
The PAC1710/20 sampling interval and resolution for
measuring VSOURCE and VSENSE are register
controlled. The VSOURCE settings based on register
values are shown in Table 4-2 and Table 4-3. The
VSENSE measurements have an additional parameter:
Full-Scale Resolution of the differential input. The
VSENSE settings based on register values are shown in
Table 4-4, Table 4-5 and Table 4-6.
TABLE 4-2:
Equation 4-3
Denominator
Equation 4-4
Denominator
VOLTAGE SOURCE
SAMPLING TIME SETTINGS
VSOURCE
Sample Time
The ALERT pin can be masked for all out-of-limit
measurements by setting the MASK_ALL bit (see
Register 6-1) or for an individual out-of-limit
measurement (see Register 6-5). Once the ALERT pin
has been masked, it will be de-asserted if no unmasked
out-of-limit conditions exist. Any interrupt conditions
that occur while the ALERT pin is masked will update
the status registers normally.
CONVERSION RATE FOR
MEASUREMENT
CONV_RATE
The ALERT pin is used as an interrupt signal or as an
SMBus Alert signal that allows an SMBus slave to
communicate an error condition to the master. One or
more SMBus Alert outputs can be hardwired together.
The ALERT pin will be asserted (by default) if the measured VSOURCE voltage or VSENSE voltage are out of
limit (≥ high limit or < low limit). The ALERT pin will
remain asserted as long as an out-of-limit condition
remains. Once the out-of-limit condition has been
removed, the ALERT pin will remain asserted until the
appropriate status bits are cleared.
Conversion Rate
VSRC_SAMP_TIME
Actual power drawn from the source can be calculated
using Equation 4-6.
0
0
2.5 ms (data = 8 bits)
256
255
0
1
5 ms (data = 9 bits)
512
511
1
0
10 ms (data = 10 bits)
(Default)
1024
1023
1
1
20 ms (data = 11 bits)
2048
2047
TABLE 4-3:
VOLTAGE SOURCE
AVERAGING SETTINGS
VSRC_AVG
Samples to Average
0
0
Disabled (default)
0
1
2
1
0
4
1
1
8
2015-2016 Microchip Technology Inc.
PAC1710/20
TABLE 4-4:
4.10
CURRENT-SENSING
AVERAGING SETTINGS
CS_SAMP_AVG
Samples to Average
0
0
Disabled (default)
0
1
2
1
0
4
1
1
8
Current Sensor
Sample Time
Equation 4-2
Denominator
CURRENT-SENSING
SAMPLING TIME SETTINGS
CS_SAMP_TIME
TABLE 4-5:
0
0
0
2.5 ms (Data = sign + 6 bits)
63
0
0
1
5 ms (Data = sign + 7 bits)
127
0
1
0
10 ms (Data = sign + 8 bits)
255
0
1
1
20 ms (Data = sign + 9 bits)
511
1
0
0
40 ms (Data = sign + 10 bits)
1023
1
0
1
80 ms (Data = sign + 11 bits)
(default)
2047
1
1
0
160 ms (Data = sign + 11 bits)
2047
320 ms (Data = sign + 11 bits)
2047
1
1
Note 1:
2:
1
160 ms sampling time has built-in 2X
analog oversampling using ADC at 12-bit
resolution.
320 mx sampling time has built-in 4X
analog oversampling using ADC at 13-bit
resolution.
Sense Voltage measurement
Resolution
The Sense Voltage Registers store the measured
VSENSE
value
(see
Section 4.4
“Current
Measurement”). Note that the bit weighting values are
for representation of the voltage relative to full scale.
There is no internal scaling of data and all normal
binary bit weightings still apply.
The Sense Voltage Registers data format is standard
two’s complement format with the positive full-scale
value (7F_Fh) and negative full-scale value (80_0h)
equal to the programmed FSR.
The Sign bit indicates the direction of current flow. If the
Sign bit is ‘0’, the current is flowing through RSENSE
from the SENSE+ pin to the SENSE- pin. If the Sign bit
is ‘1’, the current is flowing through RSENSE from the
SENSE- pin to the SENSE+ pin.
Data resolution is dependent upon sampling time as
shown in Table 4-8. The data format (assuming 11-bit
resolution) is shown in Table 4-7. This data will scale
directly with the sampling time.
TABLE 4-7:
VSENSE
Binary
Hex
(as read by
registers)
- Full-Scale
1000_0000_0000
80_0h
-2 LSB
1111_1111_1110
FF_Eh
-1 LSB
1111_1111_1111
FF_Fh
0
0000_0000_0000
00_0h
+1 LSB
0000_0000_0001
00_1h
+2 LSB
0000_0000_0010
00_2h
+Full-Scale
-1 LSB
0111_1111_1111
7F_Fh
TABLE 4-8:
TABLE 4-6:
CURRENT-SENSING RANGE
SETTINGS
CS_RNG
Full Scale Range
0
0
-10 mV to 10 mV
0
1
-20 mV to 20 mV
1
0
-40 mV to 40 mV
1
1
-80 mV to 80 mV (default)
2015-2016 Microchip Technology Inc.
VSENSE DATA FORMAT
Sampling
Time
VSENSE DATA RESOLUTION
Resolution (±)
±10 mV
±20 mV
±40 mV
±80 mV
2.5 ms
156.3 µV
5 ms
78.13 µV
312.5 µV
625.0 µV
1.250 mV
156.3 µV
312.5 µV
10 ms
625.0 µV
39.06 µV
78.13 µV
156.3 µV
312.5 µV
20 ms
19.53 µV
39.06 µV
78.13 µV
156.3 µV
40 ms
9.76 µV
19.53 µV
39.06 µV
78.13 µV
≥ 80 ms
4.88 µV
9.76 µV
19.53 µV
39.06 µV
DS20005386B-page 17
PAC1710/20
4.11
VSOURCE Data representation
The VSOURCE Voltage Registers store the measured
VSOURCE
value
(see
Section 4.5
“Voltage
Measurement”). The measured voltage is determined
by summing the bit weights of each bit set. For
example, if VSOURCE was 7.4V, the VSOURCE Voltage
Registers would read 0010_1111 for the high byte and
0100_0000b for the low byte corresponding to
5V + 1.25V + 0.625V + 0.3125V + 0.1563V + 0.0390V
= 7.3828V.
The bit weightings are assigned for human
interpretation. They should be disregarded when
translating the information via a computing system, as
shown in Section 4.5 “Voltage Measurement”.
The VSOURCE Voltage Registers cannot support
negative values, so all values less than 0V will be
recorded as 0V.
4.12
Power Ratio Data Representation
The Power Ratio Registers store a power factor value,
PRATIO, that is used to determine the final average
power delivered to the system (see Section 4.6
“Power Calculation”). PRATIO is the result of the
multiplication of the VSENSE reading and the VSOURCE
reading values shifted to a 16-bit number. It represents
the ratio of delivered power with respect to maximum
power.
DS20005386B-page 18
4.13
Limit Registers
These registers are used in concordance with the
ALERT pin to indicate when high or low limits have
been exceeded.
4.13.1
VSENSE LIMITS
The VSENSE Limit Registers store a high and low limit
for VSENSE. VSENSE is compared against both limits
after each conversion cycle.
The data format for the limit is a raw binary form that is
relative to the maximum VSENSE that has been
programmed.
If the measured sense voltage meets or exceeds the
high limit or drops below the low limit, the ALERT pin is
asserted (by default, see Section 4.7 “ALERT
Output”) and the VSENSE_HIGH or VSENSE_LOW
status bits are set in the High Limit Status or Low Limit
Status registers (see Register 6-16 and Register 6-18).
4.13.2
VSOURCE LIMITS
The VSOURCE Voltage Limit registers store the high and
low limits for VSOURCE. VSOURCE is compared against
both limits after each conversion cycle.
If VSOURCE meets or exceeds the corresponding high
limit or drops below the low limit, the ALERT pin is
asserted (by default, see Section 4.7 “ALERT
Output”) and the VSRC_HIGH or VSRC_LOW status
bits are set in the High Limit Status or Low Limit Status
registers (see Register 6-20 and Register 6-22).
2015-2016 Microchip Technology Inc.
PAC1710/20
5.0
5.0.1
SMBUS COMMUNICATION
SMBus START BIT
The SMBus Start bit is defined as a transition of the
SMBus Data line from a logic ‘1’ state to a logic ‘0’ state
while the SMBus Clock line is in a logic ‘1’ state.
5.0.2
SMBus ADDRESS AND RD/WR BIT
The SMBus Address Byte consists of the 7-bit client
address followed by a 1-bit RD/WR indicator. If this
RD/WR bit is a logic ‘0’, the SMBus host is writing data
to the client device. If this RD/WR bit is a logic ‘1’, the
SMBus host is reading data from the client device.
The PAC1710/20 SMBus address is determined by a
single resistor connected between ground and the
ADDR_SEL pin as shown in Table 5-1.
TABLE 5-1:
RES
(5%)
ADDR_SEL RESISTOR
SETTING
SMBus Address
RES
(5%)
SMBus Address
0
1001_100(r/w)
1600
0101_000(r/w)
100
1001_101(r/w)
2000
0101_001(r/w)
180
1001_110(r/w)
2700
0101_010(r/w)
300
1001_111(r/w)
3600
0101_011(r/w)
430
1001_000(r/w)
5600
0101_100(r/w)
560
1001_001(r/w)
9100
0101_101(r/w)
750
1001_010(r/w)
20000
0101_110(r/w)
1270
1001_011(r/w)
Open
0011_000(r/w)
All SMBus Data bytes are sent most significant bit first
and composed of 8 bits of information.
5.0.3
SMBus ACK AND NACK BITS
The SMBus client will acknowledge all data bytes that it
receives (as well as the client address if it matches and
the ARA address if the ALERT pin is asserted). This is
done by the client device pulling the SMBus Data line
low after the eigth bit of each byte that is transmitted.
5.0.5
SMBus TIMEOUT
The PAC1710/20 includes an SMBus timeout feature.
Following a 30 ms period of inactivity on the SMBus,
the device will time out and reset the SMBus interface.
The time-out functionality defaults to disabled and can
be enabled by writing to the TIMEOUT bit (see
Register 6-1).
5.1
SMBus and I2C Compliance
The major differences between SMBus and I2C
devices are highlighted below. For more information,
refer to the SMBus 2.0 and I2C specifications.
• PAC1710/20 supports I2C fast mode at 400 kHz.
This covers the SMBus maximum time of 100 kHz.
• Minimum frequency for SMBus communications
is 10 kHz.
• The SMBus client protocol will reset if the clock is
held at a logic ‘0’ for longer than 30 ms. This timeout functionality is disabled by default in the
PAC1710/20 and can be enabled by writing to the
TIMEOUT bit. I2C does not have a timeout.
• The SMBus client protocol will reset if both the
clock and data lines are held at a logic ‘1’ for
longer than 200 μs (idle condition). This function
is disabled by default in the PAC1710/20 and can
be enabled by setting the TIMEOUT bit. I2C does
not have an idle condition.
• I2C devices do not support the Alert Response
Address functionality (which is optional for SMBus).
• I2C devices support Block Read and Block Write
differently. I2C protocol allows for unlimited
number of bytes to be sent in either direction. The
SMBus protocol requires that an additional data
byte indicating number of bytes to read/write is
transmitted. The PAC1710/20 supports I2C
formatting only.
The host will not acknowledge (NACK) the data
received from the client by holding the SMBus data line
high after the eigth data bit has been sent.
5.0.4
SMBus STOP BIT
The SMBus Stop bit is defined as a transition of the
SMBus Data line from a logic ‘0’ state to a logic ‘1’ state
while the SMBus clock line is in a logic ‘1’ state. When
the PAC1710/20 detects an SMBus Stop bit, and it has
been communicating with the SMBus protocol, it will
reset its client interface and prepare to receive further
communications.
2015-2016 Microchip Technology Inc.
DS20005386B-page 19
PAC1710/20
5.2
SMBUS PROTOCOLS
The PAC1710/20 communicates with a host controller
through the SMBus. The SMBus is a two-wire serial
communication protocol between a computer host and
its peripheral devices. A detailed timing diagram is
shown in Figure 1-1. Stretching of the SMCLK signal is
supported; however, the PAC1710/20 will not stretch
the clock signal.
All of the below protocols use the convention in
Table 5-2.
TABLE 5-2:
PROTOCOL FORMAT
Data Sent to Device
Data Sent to the Host
# of bits sent
# of bits sent
5.2.1
WRITE BYTE
The Write Byte is used to write one byte of data to the
registers, as shown in Table 5-3.
TABLE 5-3:
WRITE BYTE PROTOCOL
START
Slave Address
WR
ACK
Register Address
ACK
Register Data
ACK
STOP
10
YYYY_YYY
0
0
XXh
0
XXh
0
01
5.2.2
READ BYTE
The Read Byte protocol is used to read one byte of data
from the registers as shown in Table 5-4.
TABLE 5-4:
READ BYTE PROTOCOL
START
Slave
Address
WR
ACK
Register
Address
ACK
START
Slave
Address
RD
ACK
Register
Data
NACK
STOP
10
YYYY_YYY
0
0
XXh
0
10
YYYY_YYY
1
0
XXh
1
01
5.2.3
SEND BYTE
The Send Byte protocol is used to set the internal
address register pointer to the correct address location.
No data is transferred during the Send Byte protocol as
shown in Table 5-5.
TABLE 5-5:
SEND BYTE PROTOCOL
START
Slave Address
WR
ACK
Register Address
ACK
STOP
10
YYYY_YYY
0
0
XXh
0
01
5.2.4
RECEIVE BYTE
The Receive Byte protocol is used to read data from a
register when the internal register address pointer is
known to be at the right location (e.g. set via Send
Byte). This is used for consecutive reads of the same
register as shown in Table 5-6.
TABLE 5-6:
RECEIVE BYTE PROTOCOL
START
Slave Address
RD
ACK
Register Address
NACK
STOP
10
YYYY_YYY
1
0
XXh
1
01
DS20005386B-page 20
2015-2016 Microchip Technology Inc.
PAC1710/20
5.2.5
ALERT RESPONSE ADDRESS
The ALERT output can be used as a processor
interrupt or as an SMBus Alert when configured to
operate as an interrupt.
When it detects that the ALERT pin is asserted, the
host will send the Alert Response Address (ARA) to the
general address of 0001_100xb. All devices with
active interrupts will respond with their client address,
as shown in Table 5-7.
TABLE 5-7:
ALERT RESPONSE ADDRESS PROTOCOL
START
Alert Response Address
RD
ACK
Device Address
NACK
STOP
10
0001_100
1
0
YYYY_YYY
1
01
The PAC1710/20 will respond to the ARA in the
following way if the ALERT pin is asserted:
• Send Slave Address and verify that full slave
address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due
to a bus contention event).
• Set the MASK bit to clear the ALERT pin.
I2C Protocols
5.3
The PAC1710/20 supports I2C Block Read and Block
Write.
The protocols listed below use the convention in
Table 5-1.
5.3.1
BLOCK WRITE
The Block Write is used to write multiple data bytes to
a group of contiguous registers, as shown in Table 5-8.
TABLE 5-8:
BLOCK WRITE PROTOCOL
START
Slave
Address
WR
ACK
Register
Address
ACK
Register Data
ACK
1 0
YYYY_YYY
0
0
XXh
0
XXh
0
Register
Data
ACK
Register
Data
ACK
Register
Address
Register
Data
ACK
STOP
XXh
0
XXh
0
XXh
0
01
2015-2016 Microchip Technology Inc.
DS20005386B-page 21
PAC1710/20
5.3.2
BLOCK READ
The Block Read is used to read multiple data bytes
from a group of contiguous registers, as shown in
Table 5-9.
TABLE 5-9:
BLOCK READ PROTOCOL
START
Slave
Address
WR
ACK
Register
Address
ACK
START
Slave
Address
RD
ACK
Register
Data
10
YYYY_YYY
0
0
XXh
0
1 0
YYYY_YYY
1
0
XXh
ACK
Register
Data
ACK
Register
Data
ACK
Register
Data
ACK
...
Register
Data
NACK
STOP
0
XXh
0
XXh
0
XXh
0
...
XXh
1
01
DS20005386B-page 22
2015-2016 Microchip Technology Inc.
2015-2016 Microchip Technology Inc.
6.0
REGISTERS IN HEXADECIMAL ORDER
The registers shown in Table 6-1 are accessible through the SMBus. In the
individual register tables that follow, an entry of ‘—’ indicates that the bit is not
used and will always read ‘0’.
TABLE 6-1:
Register
Address
00h
REGISTER SET IN HEXADECIMAL ORDER
Register
Name
Configuration
01h
Conversion Rate
02h
One-Shot
03h
Channel Mask Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default
Value
—
CDEN
MSKAL
C2IDS
C2VDS
TOUT
C1IDS
C1VDS
00h
—
—
—
—
—
—
CONV1
CONV0
03h
OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
00h
—
—
—
—
C2VS
C2VSR
C1VS
C1VSR
00h
High-Limit Status
CVDN
—
—
—
C2VSH
C2VRH
C1VSH
C1VRH
00h
05h
Low-Limit Status
—
—
—
—
C2VSL
C2VRL
C1VSL
C1VRL
00h
0Ah
VSOURCE Sampling
Configuration
C2RS1
C2RS0
C2RA1
C2RA0
C1RS1
C1RS0
C1RA1
C1RA0
88h
0Bh
CH1 VSENSE Sampling
Configuration
—
C1SS2
C1SS1
C1SS0
C1SA1
C1SA0
C1SR1
C1SR0
53h
0Ch
CH2 VSENSE Sampling
Configuration
—
C2SS2
C2SS1
C2SS0
C2SA1
C2SA0
C2SR1
C2SR0
53h
0Dh
CH1 Sense Voltage
High Byte
C1SR11
C1SR10
C1SR9
C1SR8
C1SR7
C1SR6
C1SR5
C1SR4
00h
0Eh
CH1 Sense Voltage
Low Byte
C1SR3
C1SR2
C1SR1
C1SR0
—
—
—
—
00h
0Fh
CH2 Sense Voltage
High Byte
C2SR11
C2SR10
C2SR9
C2SR8
C2SR7
C2SR6
C2SR5
C2SR4
00h
10h
CH2 Sense Voltage
Low Byte
C2SR3
C2SR2
C2SR1
C2SR0
—
—
—
—
00h
11
CH1 VSOURCE Voltage
High Byte
C1VR10
C1VR9
C1VR8
C1VR7
C1VR6
C1VR5
C1VR4
C1VR3
00h
12
CH1 VSOURCE Voltage
Low Byte
C1VR2
C1VR1
C1VR0
—
—
—
—
—
00h
13h
CH2 VSOURCE Voltage
High Byte
C2VR10
C1VR9
C2VR8
C2VR7
C2VR6
C2VR5
C2VR4
C2VR3
00h
14h
CH2 VSOURCE Voltage
Low Byte
C2VR2
C2VR1
C2VR0
—
—
—
—
—
00h
PAC1710/20
DS20005386B-page 23
04h
Register
Address
REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)
Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Default
Value
2015-2016 Microchip Technology Inc.
15h
CH1 Power Ratio
High Byte
C1P15
C1P14
C1P13
C1P12
C1P11
C1P10
C1P8
C1P7
00h
16h
CH1 Power Ratio
Low Byte
C1P7
C1P6
C1P5
C1P4
C1P3
C1P2
C1P1
C1P0
00h
17h
CH2 Power Ratio
High Byte
C2P15
C2P14
C2P13
C2P12
C2P11
C2P10
C2P8
C2P7
00h
18h
CH2 Power Ratio
Low Byte
C2P7
C2P6
C2P5
C2P4
C2P3
C2P2
C2P1
C2P0
00h
19h
CH1 Sense Voltage
High Limit
C1SH7
C1SH6
C1SH5
C1SH4
C1SH3
C1SH2
C1SH1
C1SH0
7Fh
1Ah
CH2 Sense Voltage
High Limit
C2SH7
C2SH6
C2SH5
C2SH4
C2SH3
C2SH2
C2SH1
C2SH0
7Fh
1Bh
CH1 Sense Voltage
Low Limit
C1SL7
C1SL6
C1SL5
C1SL4
C1SL3
C1SL2
C1SL1
C1SL0
80h
1Ch
CH2 Sense Voltage
Low Limit
C2SL7
C2SL6
C2SL5
C2SL4
C2SL3
C2SL2
C2SL1
C2SL0
80h
1Dh
CH1 VSOURCE Voltage
High Limit
C1VH7
C1VH6
C1VH5
C1VH4
C1VH3
C1VH2
C1VH1
C1VH0
FFh
1Eh
CH2 VSOURCE Voltage
High Limit
C2VH7
C2VH6
C2VH5
C2VH4
C2VH3
C2VH2
C2VH1
C2VH0
FFh
1Fh
CH1 VSOURCEVoltage
Low Limit
C1VL7
C1VL6
C1VL5
C1VL4
C1VL3
C1VL2
C1VL1
C1VL0
00h
20h
CH2 VSOURCE Voltage
Low Limit
C2VL7
C2VL6
C2VL5
C2VL4
C2VL3
C2VL2
C2VL1
C2VL0
00h
FDh
Product ID
PID7
PID6
PID5
PID4
PID3
PID2
PID1
PID0
57h/58h
FEh
Manufacturer ID
MID7
MID6
MID5
MID4
MID3
MID2
MID1
MID0
5Dh
FFh
Revision
REV7
REV6
REV5
REV4
REV3
REV2
REV1
REV0
81h
PAC1710/20
DS20005386B-page 24
TABLE 6-1:
PAC1710/20
6.1
Read Multiple Data Bytes
When any measurement high-byte register is read
(VSOURCE or VSENSE), the corresponding low byte is
copied into an internal “shadow” register. The user is
free to read the low byte at any time and be guaranteed
that it will correspond to the previously read high byte.
Regardless if the low byte is read or not, reading from
the same high byte register again will automatically
refresh this stored low byte data.
6.2
Detailed Register Description
REGISTER 6-1:
R/W-0
—
bit 7
CONFIGURATION REGISTER (ADDRESS 00H)
R/W-0
CDEN
Legend:
R = Read bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0
MSKAL
W = Writable bit
‘1’ = bit is set
R/W-0
C2IDS
R/W-0
C2VDS
R/W-0
TOUT
R/W-0
C1IDS
R/W-0
C1VDS
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
Unimplemented: Read as ‘0’
CDEN: Enables the ALERT pin to be asserted when the conversion cycle is finished.
1 = ALERT pin will be asserted for 5 μs when the conversion cycle is finished.
0 = ALERT pin is not masked. If any of the appropriate status bits are set, the ALERT pin will be asserted.
MSKAL: Masks the ALERT pin from asserting due to out-of-limit conditions.
1 = ALERT pin is masked. It will not be asserted for any interrupt condition. The Status Registers will
be updated normally.
0 = ALERT pin is not masked. It will be asserted for any interrupt condition not masked by
Register 6-4. The Status Registers will be updated normally.
C2IDS: Disables the VSENSE measurement for channel 2 (PAC1720)
1 = The device is not measuring the sense voltage. It will update CH2 Sense Voltage Registers when
a One-Shot command is given.
0 = The device is measuring sense voltage for CH2
Unimplemented: Read as ‘0’ (PAC1710)
C2VDS: Disables the VSOURCE measurement for channel 2 (PAC1720)
1 = The device is not measuring the Source voltage. It will update CH2 Source Voltage Registers
when a One-Shot command is given.
0 = The device is measuring Source voltage for CH2
Unimplemented: Read as ‘0’ (PAC1710)
TOUT: Enables the time-out and idle reset functionality of the communications protocol (see
Section 5.0.5 “SMBus Timeout”).
1 = Time out enabled
0 = Time out disabled
C1IDS: Disables the VSENSE measurement for channel 1
1 = The device is not measuring the sense voltage. It will update CH1 Sense Voltage Registers when
a One-Shot command is given.
0 = The device is measuring sense voltage for CH1
C1VDS: Disables the VSOURCE measurement for channel 1
1 = The device is not measuring the Source voltage. It will update CH1 Source Voltage Registers
when a One-Shot command is given.
0 = The device is measuring source voltage for CH1
2015-2016 Microchip Technology Inc.
DS20005386B-page 25
PAC1710/20
REGISTER 6-2:
CONVERSION RATE REGISTER (ADDRESS 01H)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Read bit
-n = Value at POR
bit 7-2
bit 1-0
W = Writable bit
‘1’ = bit is set
R/W-1
R/W-1
CONV
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
Unimplemented: Read as ‘0’
CONV: Determines the conversion rate as shown in Table 4-1.
00b = 1 Sample/Second
01b = 2 Samples/Second
01b = 4 Samples/Second
11b = Continuous
REGISTER 6-3:
R/W-0
ONE-SHOT REGISTER (ADDRESS 02H)
R/W-0
R/W-0
R/W-0
R/W-0
OS
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
OS: When the device is in the Standby state, writing to the One-Shot Register will initiate a
conversion cycle and update all measurements.
REGISTER 6-4:
U-0
—
CHANNEL MASK REGISTER (ADDRESS 03H)
U-0
—
U-0
—
bit 7
Legend:
R = Read bit
-n = Value at POR
bit 7-4
bit 3
bit 2
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
W = Writable bit
‘1’ = bit is set
U-0
—
R/W-0
C2VS
R/W-0
C2VSR
R/W-0
C1VS
R/W-0
C1VSR
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
Unimplemented: Read as ‘0’
C2VS: Masks the ALERT pin from asserting when the channel 2 VSENSE value meets or exceeds the
high limit or drops below the low limit (PAC1720).
1 = The channel 2 VSENSE voltage measurement cannot cause the ALERT pin to be asserted (if enabled).
0 = The channel 2 VSENSE voltage measurement can cause the ALERT pin to be asserted (if enabled).
Unimplemented: Read as ‘0’ (PAC1710)
C2VSR: Masks the ALERT pin from asserting when the channel 2 VSOURCE value meets or exceeds
the high limit or drops below the low limit (PAC1720).
1 = The channel 2 VSOURCE voltage measurement cannot cause the ALERT pin to be asserted
(if enabled).
0 = The channel 2 VSOURCE voltage measurement can cause the ALERT pin to be asserted (if enabled).
Unimplemented: Read as ‘0’ (PAC1710)
DS20005386B-page 26
2015-2016 Microchip Technology Inc.
PAC1710/20
REGISTER 6-4:
bit 1
bit 0
C1VS: Masks the ALERT pin from asserting when the channel 1 VSENSE value meets or exceeds the
high limit or drops below the low limit.
1 = The channel 1 VSENSE voltage measurement cannot cause the ALERT pin to be asserted
(if enabled).
0 = The channel 1 VSENSE voltage measurement can cause the ALERT pin to be asserted
(if enabled).
C1VSR: Masks the ALERT pin from asserting when the channel 1 VSOURCE value meets or exceeds
the high limit or drops below the low limit.
1 = The channel 1 VSOURCE voltage measurement cannot cause the ALERT pin to be asserted
(if enabled).
0 = The channel 1 VSOURCE voltage measurement can cause the ALERT pin to be asserted
(if enabled).
REGISTER 6-5:
RC-0
CVDN
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
HIGH-LIMIT STATUS REGISTER (ADDRESS 04H)
U-0
—
Legend:
R = Read bit
-n = Value at POR
bit 7
CHANNEL MASK REGISTER (ADDRESS 03H) (CONTINUED)
U-0
—
W = Writable bit
‘1’ = bit is set
U-0
—
RC-0
C2VSH
RC-0
C2VRH
RC-0
C1VSH
RC-0
C1VRH
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
CVDN: Indicates that the conversion cycle (see Section 4.2 “Conversion Cycle”) is complete. This
bit is cleared when read.
1 = Conversion complete
0 = Conversion not complete
Unimplemented: Read as ‘0’
C2VSH: This bit is set when the channel 2 VSENSE value meets or exceeds its programmed high limit
(PAC1720).
1 = The channel 2 VSOURCE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal operation
Unimplemented: Read as ‘0’ (PAC1710)
C2VRH: This bit is set when the channel 2 VSOURCE value meets or exceeds its programmed high limit
(PAC1720).
1 = The channel 2 VSOURCE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
Unimplemented: Read as ‘0’ (PAC1710)
C1VSH: This bit is set when the channel 1 VSENSE value meets or exceeds its programmed high limit.
1 = The channel 1 VSENSE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
C1VRH: This bit is set when the channel 1 VSOURCE value meets or exceeds its programmed high limit.
1 = The channel 1 VSOURCE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
2015-2016 Microchip Technology Inc.
DS20005386B-page 27
PAC1710/20
REGISTER 6-6:
U-0
—
LOW-LIMIT STATUS REGISTER (ADDRESS 05H)
U-0
—
U-0
—
U-0
—
RC-0
C2VSL
RC-0
C2VRL
RC-0
C1VSL
bit 7
Legend:
R = Read bit
-n = Value at POR
bit 7-4
bit 3
bit 2
bit 1
bit 0
W = Writable bit
‘1’ = bit is set
VSOURCE SAMPLING CONFIGURATION REGISTER (ADDRESS 0AH)
R/W-0
R/W-0
C2RS
bit 7
Legend:
R = Read bit
-n = Value at POR
bit 5-4
bit 3-2
bit 1-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
Unimplemented: Read as ‘0’
C2VSL: This bit is set when the channel 2 VSENSE falls below its programmed low limit (PAC1720)
1 = The channel 2 VSENSE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal operation
Unimplemented: Read as ‘0’ (PAC1710)
C2VRL: This bit is set when the channel 2 VSOURCE value falls below its programmed low limit.
1 = The channel 2 VSOURCE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
Unimplemented: Read as ‘0’ (PAC1710)
C1VSL: This bit is set when the channel 1 VSENSE value falls below its programmed low limit.
1 = The channel 1 VSENSE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
C1VRL: This bit is set when the channel 1 VSOURCE value falls below its programmed low limit.
1 = The channel 1 VSOURCE voltage measurement caused the ALERT pin to be asserted (if enabled).
0 = Normal Operation
REGISTER 6-7:
bit 7-6
RC-0
C1VRL
bit 0
R/W-0
R/W-0
C2RA
W = Writable bit
‘1’ = bit is set
R/W-0
R/W-0
C1RS
R/W-0
R/W-0
C1RA
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C2RS: Determines the channel 2 VSOURCE measurement sample time, as shown in Table 4-2
(PAC1720). This will affect the resolution of the data presented in the VSOURCE Voltage Registers.
Unimplemented: Read as ‘0’ (PAC1710)
C2RA: Controls the digital averaging that is applied to the channel 2 VSOURCE measurement, as
shown in Table 4-3 (PAC1720). This determines the number of consecutive samples that are
averaged.
Unimplemented: Read as ‘0’ (PAC1710)
C1RS: Determines the channel 1 VSOURCE measurement sample time, as shown in Table 4-2.
This will affect the resolution of the data presented in the VSOURCE Voltage Registers.
C1RA: Controls the digital averaging that is applied to the channel 1 VSOURCE measurement, as
shown in Table 4-3. This determines the number of consecutive samples that are averaged.
DS20005386B-page 28
2015-2016 Microchip Technology Inc.
PAC1710/20
REGISTER 6-8:
R/W-0
—
bit 7
CHANNEL 1 VSENSE SAMPLING CONFIGURATION REGISTER (ADDRESS 0BH)
R/W-1
Legend:
R = Read bit
-n = Value at POR
bit 7
bit 6-4
bit 3-2
bit 1-0
bit 3-2
bit 1-0
W = Writable bit
‘1’ = bit is set
R/W-0
R/W-0
C1SA
R/W-1
R/W-1
C1SR
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
CHANNEL 2 VSENSE SAMPLING CONFIGURATION REGISTER (ADDRESS 0CH)
R/W-1
Legend:
R = Read bit
-n = Value at POR
bit 7
bit 6-4
R/W-1
Unimplemented: Read as ‘0’
C1CSS: Determines the Channel 1 VSENSE voltage measurement sample time, as shown in
Table 4-5. This will affect the resolution of the data in the CH1 Sense Voltage Registers.
C1SA: Controls the digital averaging that is applied to the channel 1 VSENSE measurement, as
shown in Table 4-4. This determines the number of consecutive samples that are averaged.
C1SR: Determines the Current Sense full scale range for channel 1 VSENSE measurement as
shown in Table 4-6.
REGISTER 6-9:
R/W-0
—
bit 7
R/W-0
C1CSS
R/W-0
C2CSS
W = Writable bit
‘1’ = bit is set
R/W-1
R/W-0
R/W-0
C2SA
R/W-1
R/W-1
C2SR
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
Unimplemented: Read as ‘0’
C2CSS: Determines the Channel 2 VSENSE voltage measurement sample time, as shown in
Table 4-5 (PAC1720). This will affect the resolution of the data in the CH2 Sense Voltage Registers.
Unimplemented: Read as ‘0’(PAC1710).
C2SA: Controls the digital averaging that is applied to the Channel 2 VSENSE measurement, as
shown in Table 4-4 (PAC1720). This determines the number of consecutive samples that are averaged.
Unimplemented: Read as ‘0’ (PAC1710)
C2SR: Determines the Channel 2 Current Sense full scale range channel 2 VSENSE
measurement as shown in Table 4-6 (PAC1720).
Unimplemented: Read as ‘0’ (PAC1710)
2015-2016 Microchip Technology Inc.
DS20005386B-page 29
PAC1710/20
REGISTER 6-10:
R-0
CHANNEL 1 VSENSE RESULT REGISTER (ADDRESSES 0DH AND 0EH)
R-0
R-0
R-0
R-0
C1SR
R-0
R-0
R-0
bit 15
bit 8
R-0
R-0
R-0
C1SR
R-0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 15-4
bit 3-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C1SR: These registers contain the most recent digitized value Channel 1 VSENSE samples.
Unimplemented: Read as ‘0’
REGISTER 6-11:
R-0
CHANNEL 2 VSENSE RESULT REGISTER (ADDRESSES 0FH AND 10H)
R-0
R-0
R-0
R-0
C2SR
R-0
R-0
R-0
bit 15
bit 8
R-0
R-0
R-0
C2SR
R-0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 15-4
bit 3-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as 0
‘0’ = Bit is cleared
x = Bit in unknown
C2SR: These registers contain the most recent digitized value channel 2 VSENSE samples
(PAC1720).
Unimplemented: Read as ‘0’ (PAC1710)
Unimplemented: Read as ‘0’
DS20005386B-page 30
2015-2016 Microchip Technology Inc.
PAC1710/20
REGISTER 6-12:
R-0
CHANNEL 1 VSOURCE RESULT REGISTER (ADDRESSES 11H AND 12H)
R-0
R-0
R-0
R-0
C1VR
R-0
R-0
R-0
bit 15
R-0
bit 8
R-0
C1VR
R-0
U
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 15-5
bit 4-0
U-0
—
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C1VR: These registers contain the most recent digitized value Channel 1 VSOURCE samples.
400h = 20V
200h = 10V
100h = 5V
080h = 2.5V
040h = 1.25V
020h = 625 mV
010h = 312.5 mV
008h = 156.25 mV
004h = 78.125 mV
002h = 39.063 mV
001h = 19.531 mV
Unimplemented: Read as ‘0’
2015-2016 Microchip Technology Inc.
DS20005386B-page 31
PAC1710/20
REGISTER 6-13:
R-0
CHANNEL 2 VSOURCE RESULT REGISTER (ADDRESSES 13H AND 14H)
R-0
R-0
R-0
R-0
C2VR
R-0
R-0
R-0
bit 15
R-0
bit 8
R-0
C2VR
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 15-5
bit 4-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C2VR: These registers contain the most recent digitized value Channel 2 VSOURCE samples
(PAC1720).
400h = 20V
200h = 10V
100h = 5V
080h = 2.5V
040h = 1.25V
020h = 625 mV
010h = 312.5 mV
008h = 156.25 mV
004h = 78.125 mV
002h = 39.063 mV
001h = 19.531 mV
Unimplemented: Read as ‘0’ (PAC1710)
Unimplemented: Read as ‘0’
REGISTER 6-14:
R-0
CHANNEL 1 POWER RATIO REGISTER (ADDRESSES 15H AND 16H)
R-0
R-0
R-0
R-0
C1P
R-0
R-0
R-0
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
C1P
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 15-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C1P: These registers contain the most recent channel 1 Power ratio calculations. This is a
16-bit binary number representing a ratio based on Power FSR.
DS20005386B-page 32
2015-2016 Microchip Technology Inc.
PAC1710/20
REGISTER 6-15:
R-0
CHANNEL 2 POWER RATIO REGISTER (ADDRESS 17H AND 18H)
R-0
R-0
R-0
R-0
C2P
R-0
R-0
R-0
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
C2P
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 15-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C2P: These registers contain the most recent channel 2 power ratio calculations (PAC1720).
This is a 16-bit binary number representing a ratio based on Power FSR
Unimplemented: Read as ‘0’ (PAC1710)
REGISTER 6-16:
R/W-0
W = Writable bit
‘1’ = bit is set
CHANNEL 1 VSENSE HIGH LIMIT REGISTER (ADDRESS 19H)
R/W-1
R/W-1
R/W-1
R/W-1
C1SH
R/W-1
R/W-1
R/W-1
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C1SH: Two’s complement high-limit channel 1 VSENSE
0100_000 = 1024
0010_0000 = 512
0001_0000 = 256
0000_1000 = 128
0000_0100 = 64
0000_0010 = 32
0000_0001 = 16
1111_1111 = -1
1000_000 = -1024
2015-2016 Microchip Technology Inc.
DS20005386B-page 33
PAC1710/20
REGISTER 6-17:
R/W-0
CHANNEL 2 VSENSE HIGH-LIMIT REGISTER (ADDRESS 1AH)
R/W-1
R/W-1
R/W-1
R/W-1
C2SH
R/W-1
R/W-1
R/W-1
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C2SH: Two’s complement high-limit channel 2 VSENSE (PAC1720)
0100_000 = 1024
0010_0000 = 512
0001_0000 = 256
0000_1000 = 128
0000_0100 = 64
0000_0010 = 32
0000_0001 = 16
1111_1111 = -1
1000_000 = -1024
Unimplemented: Read as ‘0’ (PAC1710)
REGISTER 6-18:
R/W-1
W = Writable bit
‘1’ = bit is set
CHANNEL 1 VSENSE LOW-LIMIT REGISTER (ADDRESS 1BH)
R/W-0
R/W-0
R/W-0
R/W-0
C1SL
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C1SL: Two’s complement low-limit channel 1 VSENSE
0100_000 = 1024
0010_0000 = 512
0001_0000 = 256
0000_1000 = 128
0000_0100 = 64
0000_0010 = 32
0000_0001 = 16
1111_1111 = -1
1000_000 = -1024
DS20005386B-page 34
2015-2016 Microchip Technology Inc.
PAC1710/20
REGISTER 6-19:
R/W-1
CHANNEL 2 VSENSE LOW-LIMIT REGISTER (ADDRESS 1CH)
R/W-0
R/W-0
R/W-0
R/W-0
C2SL
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C2SL: Two’s complement low-limit channel 2 VSENSE (PAC1720)
0100_000 = 1024
0010_0000 = 512
0001_0000 = 256
0000_1000 = 128
0000_0100 = 64
0000_0010 = 32
0000_0001 = 16
1111_1111 = -1
1000_000 = -1024
Unimplemented: Read as ‘0’ (PAC1710)
REGISTER 6-20:
R/W-1
W = Writable bit
‘1’ = bit is set
CHANNEL 1 VSOURCE HIGH-LIMIT REGISTER (ADDRESS 1DH)
R/W-1
R/W-1
R/W-1
R/W-1
C1VH
R/W-1
R/W-1
R/W-1
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as 0
‘0’ = Bit is cleared
x = Bit in unknown
C1VH: Two’s complement high-limit channel 1 VSOURCE
80h = 20V
40h = 10V
20h = 5V
10h = 2.5V
08h = 1.25V
04h = 625 mV
02h = 312.5 mV
01h = 156.25 mV
2015-2016 Microchip Technology Inc.
DS20005386B-page 35
PAC1710/20
REGISTER 6-21:
R/W-1
CHANNEL 2 VSOURCE HIGH-LIMIT REGISTER (ADDRESS 1EH)
R/W-1
R/W-1
R/W-1
R/W-1
C2VH
R/W-1
R/W-1
R/W-1
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C2VH: Two’s complement high-limit channel 2 VSOURCE (PAC1720)
0h = 20V
40h = 10V
20h = 5V
10h = 2.5V
08h = 1.25V
04h = 625 mV
02h = 312.5 mV
01h = 156.25 mV
Unimplemented: Read as ‘0’ (PAC1710)
REGISTER 6-22:
R/W-0
W = Writable bit
‘1’ = bit is set
CHANNEL 1 VSOURCE LOW-LIMIT REGISTER (ADDRESS 1FH)
R/W-0
R/W-0
R/W-0
R/W-0
C1VL
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C1VL: Two’s complement low-limit channel 1 VSOURCE
0h = 20V
40h = 10V
20h = 5V
10h = 2.5V
08h = 1.25V
04h = 625 mV
02h = 312.5 mV
01h = 156.25 mV
DS20005386B-page 36
2015-2016 Microchip Technology Inc.
PAC1710/20
REGISTER 6-23:
R/W-0
CHANNEL 2 VSOURCE LOW-LIMIT REGISTER (ADDRESS 20H)
R/W-0
R/W-0
R/W-0
R/W-0
C2VL
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
C2VL: Two’s complement low-limit channel 2 VSOURCE
0h = 20V
40h = 10V
20h = 5V
10h = 2.5V
08h = 1.25V
04h = 625 mV
02h = 312.5 mV
01h = 156.25 mV
REGISTER 6-24:
R-0
PRODUCT REGISTER (ADDRESS FDH)
R-1
R-0
R-1
R-0
R-1
R-1
R-1
PID
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
PID: Product ID for PAC1710/20
57h = PAC1720
58H = PAC1710
REGISTER 6-25:
R-0
MCHP ID REGISTER (ADDRESS FEH)
R-1
R-0
R-1
R-1
R1
R-0
R-1
MID
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
MID: Manufacturer ID
2015-2016 Microchip Technology Inc.
DS20005386B-page 37
PAC1710/20
REGISTER 6-26:
R/W-1
REVISION REGISTER (ADDRESS FFH)
R/W-0
R/W-0
R/W-0
R/W-0
REV
R/W-0
R/W-0
R/W-1
bit 7
bit 0
Legend:
R = Read bit
-n = Value at POR
bit 7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit in unknown
REV: Silicon Revision
DS20005386B-page 38
2015-2016 Microchip Technology Inc.
PAC1710/20
7.0
PACKAGE DESCRIPTION
7.1
Package Marking Information
10-Lead VDFN (3x3x0.9 mm)
25WW
NNNA
e4
Example
Part Number
Code
PAC1710-1-AIA-TR
25WW
PAC1720-1-AIA-TR
26WW
e4
PIN 1
PIN 1
Legend: Y
WW
NNN
Note:
2504
256A
Year code (last digit of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Package
Country of origin
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015-2016 Microchip Technology Inc.
DS20005386B-page 39
PAC1710/20
10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.10 C
1
2X
2
TOP VIEW
0.10 C
0.10 C
A1
C
A
SEATING
PLANE
10X
(A3)
SIDE VIEW
0.05 C
D2
P
NOTE 1
1
2
P
L
E2
K
N
10X b
e
BOTTOM VIEW
0.10
0.05
C A B
C
Microchip
Sheet
1 of
MicrochipTechnology
TechnologyDrawing
DrawingC04-206B
C04-206%
Sheet
12
of 2
DS20005386B-page 40
2015-2016 Microchip Technology Inc.
PAC1710/20
10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Terminals
e
Pitch
A
Overall Height
Standoff
A1
(A3)
Terminal Thickness
D
Overall Length
D2
Exposed Pad Length
E
Overall Width
E2
Exposed Pad Width
Exposed Pad Chamfer
P
b
Terminal Width
L
Terminal Length
Terminal-to-Exposed-Pad
K
MIN
0.80
0.00
2.20
1.50
0.18
0.35
0.25
MILLIMETERS
NOM
10
0.50 BSC
0.85
0.02
0.20 REF
3.00 BSC
2.30
3.00 BSC
1.60
0.25
0.25
0.40
0.30
MAX
0.90
0.05
2.40
1.70
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-206% Sheet 2 of 2
2015-2016 Microchip Technology Inc.
DS20005386B-page 41
PAC1710/20
10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C
2X CH
ØV
1
10
2
VX
X1
X2
E
G1
VY
SILK SCREEN
(G2)
Y2
Y1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Y2
Optional Center Pad Width
Optional Center Pad Length
X2
Contact Pad Spacing
C
Center Pad Chamfer
CH
Contact Pad Width (X10)
X1
Contact Pad Length (X10)
Y1
Contact Pad to Contact Pad (X8)
G1
Contact Pad to Center Pad (X10)
G2
Thermal Via Diameter
V
Thermal Via Pitch
VX
Thermal Via Pitch
VY
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.70
2.40
3.00
0.28
0.30
0.80
0.20
0.25 REF
0.30
1.00
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerances, for reference only.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2206%
DS20005386B-page 42
2015-2016 Microchip Technology Inc.
PAC1710/20
APPENDIX A:
REVISION HISTORY
Revision B (February 2016)
The following was modified:
1.
Updated the package drawings in Section 7.0,
Package Description
Revision A (May 2015)
• Replaces previous SMSC version 1.1 (12-08-11)
• Updated the Absolute Maximum Ratings in
Section 1.1, Electrical Specifications
• Added information for the dual high-side current
sensor (PAC1720)
Revision 1.1 (December 2011)
• Initial release
2015-2016 Microchip Technology Inc.
DS20005386B-page 43
PAC1710/20
NOTES:
DS20005386B-page 44
2015-2016 Microchip Technology Inc.
PAC1710/20
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
-XXX
Device
SMBus
Address
Package
-XX
Tape and
Reel
Device:
PAC1710/20: High-side power/current monitor with analog
output
SMBus Address:
-1
= selectable address
Package:
AIA
= 10-lead 3 mm x 3 mm VDFN
Shipping Pack:
TR
=4,000 piece Tape and Reel
2015-2016 Microchip Technology Inc.
Examples:
a) PAC1710-1-AIA-TR: Single-channel high-side
current monitor
3x3 VDFN 8-lead package,
shipped in a 4,000 piece
Tape and Reel
DS20005386B-page 45
PAC1710/20
NOTES:
DS20005386B-page 46
2015-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2015-2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0276-3
DS20005386B-page 47
Worldwide Sales and Service
AMERICAS
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Technical Support:
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Web Address:
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07/14/15
DS20005386B-page 48
2015-2016 Microchip Technology Inc.
