PIC10F200/202/204/206
6-Pin, 8-Bit Flash Microcontrollers
Devices Included In This Data Sheet:
• PIC10F200
• PIC10F204
• PIC10F202
• PIC10F206
Low-Power Features/CMOS Technology:
• Operating Current:
- < 175 A @ 2V, 4 MHz, typical
• Standby Current:
- 100 nA @ 2V, typical
• Low-Power, High-Speed Flash Technology:
- 100,000 Flash endurance
- > 40 year retention
• Fully Static Design
• Wide Operating Voltage Range: 2.0V to 5.5V
• Wide Temperature Range:
- Industrial: -40C to +85C
- Extended: -40C to +125C
High-Performance RISC CPU:
• Only 33 Single-Word Instructions to Learn
• All Single-Cycle Instructions except for Program
Branches, which are Two-Cycle
• 12-Bit Wide Instructions
• 2-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
for Data and Instructions
• 8-Bit Wide Data Path
• Eight Special Function Hardware Registers
• Operating Speed:
- 4 MHz internal clock
- 1 s instruction cycle
Peripheral Features (PIC10F200/202):
• Four I/O Pins:
- Three I/O pins with individual direction control
- One input-only pin
- High current sink/source for direct LED drive
- Wake-on-change
- Weak pull-ups
• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
Special Microcontroller Features:
• 4 MHz Precision Internal Oscillator:
- Factory calibrated to ±1%
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Debugging (ICD) Support
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with Dedicated On-Chip
RC Oscillator for Reliable Operation
• Programmable Code Protection
• Multiplexed MCLR Input Pin
• Internal Weak Pull-ups on I/O Pins
• Power-Saving Sleep mode
• Wake-up from Sleep on Pin Change
TABLE 1:
Peripheral Features (PIC10F204/206):
• Four I/O Pins:
- Three I/O pins with individual direction control
- One input-only pin
- High current sink/source for direct LED drive
- Wake-on-change
- Weak pull-ups
• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
• One Comparator:
- Internal absolute voltage reference
- Both comparator inputs visible externally
- Comparator output visible externally
PIC10F20X MEMORY AND FEATURES
Program Memory
Data Memory
Device
I/O
Timers
8-bit
Comparator
Flash (words)
SRAM (bytes)
PIC10F200
256
16
4
1
0
PIC10F202
512
24
4
1
0
PIC10F204
256
16
4
1
1
PIC10F206
512
24
4
1
1
2004-2014 Microchip Technology Inc.
DS40001239F-page 1
PIC10F200/202/204/206
Pin Diagrams
FIGURE 3:
VSS
2
GP1/ICSPCLK
3
GP0/ICSPDAT/CIN+
1
VSS
2
GP1/ICSPCLK/CIN-
3
PIC10F200/202
1
6
GP3/MCLR/VPP
5
VDD
4
GP2/T0CKI/FOSC4
PIC10F204/206
GP0/ICSPDAT
6
GP3/MCLR/VPP
5
VDD
4
GP2/T0CKI/COUT/FOSC4
8-PIN PDIP
2
GP2/T0CKI/FOSC4
3
GP1/ICSPCLK
4
N/C
1
VDD
2
GP2/T0CKI/COUT/FOSC4
3
GP1/ICSPCLK/CIN-
4
8
PIC10F200/202
1
PIC10F204/206
N/C
VDD
GP3/MCLR/VPP
7
VSS
6
N/C
5
GP0/ICSPDAT
8
GP3/MCLR/VPP
7
VSS
6
N/C
5
GP0/ICSPDAT/CIN+
8-PIN DFN
DS40001239F-page 2
N/C
1
VDD
2
GP2/T0CKI/FOSC4
3
GP1/ICSPCLK
4
N/C
1
VDD
2
GP2/T0CKI/COUT/FOSC4
3
GP1/ICSPCLK/CIN-
4
PIC10F200/202
FIGURE 2:
6-PIN SOT-23
8
PIC10F204/206
FIGURE 1:
8
GP3/MCLR/VPP
7
VSS
GP3/MCLR/VPP
7
VSS
6
N/C
5
GP0/ICSPDAT
6
N/C
5
GP0/ICSPDAT/CIN+
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
Table of Contents
1.0 General Description...................................................................................................................................................................... 4
2.0 PIC10F200/202/204/206 Device Varieties .................................................................................................................................. 5
3.0 Architectural Overview ................................................................................................................................................................. 6
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Port ....................................................................................................................................................................................... 20
6.0 Timer0 Module and TMR0 Register (PIC10F200/202)............................................................................................................... 23
7.0 Timer0 Module and TMR0 Register (PIC10F204/206)............................................................................................................... 27
8.0 Comparator Module.................................................................................................................................................................... 31
9.0 Special Features of the CPU...................................................................................................................................................... 35
10.0 Instruction Set Summary ............................................................................................................................................................ 45
11.0 Development Support................................................................................................................................................................. 53
12.0 Electrical Characteristics ............................................................................................................................................................ 57
13.0 DC and AC Characteristics Graphs and Tables......................................................................................................................... 67
14.0 Packaging Information................................................................................................................................................................ 75
The Microchip Web Site ....................................................................................................................................................................... 85
Customer Change Notification Service ................................................................................................................................................ 85
Customer Support ................................................................................................................................................................................ 85
Product Identification System .............................................................................................................................................................. 86
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2004-2014 Microchip Technology Inc.
DS40001239F-page 3
PIC10F200/202/204/206
1.0
GENERAL DESCRIPTION
1.1
Applications
The PIC10F200/202/204/206 devices fit in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The Flash technology makes customizing application
programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and
convenient. The small footprint packages, for through
hole or surface mounting, make these microcontrollers
well suited for applications with space limitations. Low
cost, low power, high performance, ease-of-use and I/O
flexibility make the PIC10F200/202/204/206 devices
very versatile even in areas where no microcontroller
use has been considered before (e.g., timer functions,
logic and PLDs in larger systems and coprocessor
applications).
The PIC10F200/202/204/206 devices from Microchip
Technology are low-cost, high-performance, 8-bit,
fully-static, Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single-word/
single-cycle instructions. All instructions are single
cycle (1 s) except for program branches, which take
two cycles. The PIC10F200/202/204/206 devices
deliver performance in an order of magnitude higher
than their competitors in the same price category. The
12-bit wide instructions are highly symmetrical,
resulting in a typical 2:1 code compression over other
8-bit microcontrollers in its class. The easy-to-use and
easy to remember instruction set reduces development
time significantly.
The PIC10F200/202/204/206 products are equipped
with special features that reduce system cost and
power requirements. The Power-on Reset (POR) and
Device Reset Timer (DRT) eliminate the need for
external Reset circuitry. INTRC Internal Oscillator
mode is provided, thereby preserving the limited
number of I/O available. Power-Saving Sleep mode,
Watchdog Timer and code protection features improve
system cost, power and reliability.
The PIC10F200/202/204/206 devices are available in
cost-effective Flash, which is suitable for production in
any volume. The customer can take full advantage of
Microchip’s price leadership in Flash programmable
microcontrollers, while benefiting from the Flash
programmable flexibility.
The PIC10F200/202/204/206 products are supported
by a full-featured macro assembler, a software
simulator, an in-circuit debugger, a ‘C’ compiler, a
low-cost development programmer and a full featured
programmer. All the tools are supported on IBM® PC
and compatible machines.
TABLE 1-1:
PIC10F200/202/204/206 DEVICES
PIC10F200
Clock
Maximum Frequency of Operation (MHz)
Memory
Flash Program Memory
Data Memory (bytes)
Peripherals
Timer Module(s)
Wake-up from Sleep on Pin Change
Comparators
Features
PIC10F202
PIC10F204
PIC10F206
4
4
4
4
256
512
256
512
16
24
16
24
TMR0
TMR0
TMR0
TMR0
Yes
Yes
Yes
Yes
0
0
1
1
I/O Pins
3
3
3
3
Input-Only Pins
1
1
1
1
Internal Pull-ups
Yes
Yes
Yes
Yes
In-Circuit Serial Programming™
Yes
Yes
Yes
Yes
33
33
33
Number of Instructions
Packages
6-pin SOT-23
6-pin SOT-23
6-pin SOT-23
8-pin PDIP, DFN 8-pin PDIP, DFN 8-pin PDIP, DFN
33
6-pin SOT-23
8-pin PDIP, DFN
The PIC10F200/202/204/206 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current
capability and precision internal oscillator.
The PIC10F200/202/204/206 devices use serial programming with data pin GP0 and clock pin GP1.
DS40001239F-page 4
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
2.0
PIC10F200/202/204/206 DEVICE
VARIETIES
A variety of packaging options are available.
Depending
on
application
and
production
requirements, the proper device option can be selected
using the information in this section. When placing
orders, please use the PIC10F200/202/204/206
Product Identification System at the back of this data
sheet to specify the correct part number.
2.1
2.2
Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your local Microchip Technology sales office for
more details.
2004-2014 Microchip Technology Inc.
DS40001239F-page 5
PIC10F200/202/204/206
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC10F200/202/204/206
devices can be attributed to a number of architectural
features commonly found in RISC microprocessors. To
begin with, the PIC10F200/202/204/206 devices use a
Harvard architecture in which program and data are
accessed on separate buses. This improves
bandwidth over traditional von Neumann architectures
where program and data are fetched on the same bus.
Separating program and data memory further allows
instructions to be sized differently than the 8-bit wide
data word. Instruction opcodes are 12 bits wide,
making it possible to have all single-word instructions.
A 12-bit wide program memory access bus fetches a
12-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (33) execute in a single
cycle (1 s @ 4 MHz) except for program branches.
The table below lists program memory (Flash) and data
memory (RAM) for the PIC10F200/202/204/206
devices.
TABLE 3-1:
PIC10F2XX MEMORY
The PIC10F200/202/204/206 devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean functions between data in the working register
and any register file.
The ALU is 8 bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two’s
complement in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1 and
Figure 3-2, with the corresponding device pins
described in Table 3-2.
Memory
Device
Program
Data
PIC10F200
256 x 12
16 x 8
PIC10F202
512 x 12
24 x 8
PIC10F204
256 x 12
16 x 8
PIC10F206
512 x 12
24 x 8
The PIC10F200/202/204/206 devices can directly or
indirectly address its register files and data memory. All
Special Function Registers (SFR), including the PC,
are mapped in the data memory. The PIC10F200/202/
204/206 devices have a highly orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation, on any register, using any
addressing mode. This symmetrical nature and lack of
“special optimal situations” make programming with the
PIC10F200/202/204/206 devices simple, yet efficient.
In addition, the learning curve is reduced significantly.
DS40001239F-page 6
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 3-1:
PIC10F200/202 BLOCK DIAGRAM
9-10
512 x12 or
256 x12
24 or 16
bytes
File
Registers
Stack 1
Stack 2
12
RAM Addr
GPIO
GP0/ICSPDAT
GP1/ICSPCLK
GP2/T0CKI/FOSC4
GP3/MCLR/VPP
RAM
Program
Memory
Program
Bus
8
Data Bus
Program Counter
Flash
9
Addr MUX
Instruction Reg
Direct Addr
5
5-7
Indirect
Addr
FSR Reg
STATUS Reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
Timing
Generation
Power-on
Reset
Watchdog
Timer
Internal RC
Clock
ALU
8
W Reg
Timer0
MCLR
VDD, VSS
2004-2014 Microchip Technology Inc.
DS40001239F-page 7
PIC10F200/202/204/206
FIGURE 3-2:
PIC10F204/206 BLOCK DIAGRAM
9-10
512 x12 or
256 x12
GPIO
GP0/ICSPDAT/CIN+
GP1/ICSPCLK/CINGP2/T0CKI/COUT/FOSC4
GP3/MCLR/VPP
RAM
Program
Memory
Program
Bus
8
Data Bus
Program Counter
Flash
24 or 16
bytes
Stack 1
Stack 2
File
Registers
12
RAM Addr
9
Addr MUX
Instruction Reg
Direct Addr
5
5-7
Indirect
Addr
FSR Reg
STATUS Reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
Timing
Generation
Power-on
Reset
Watchdog
Timer
Internal RC
Clock
ALU
8
W Reg
CIN+
Timer0
CIN-
MCLR
VDD, VSS
DS40001239F-page 8
Comparator
COUT
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
TABLE 3-2:
PIC10F200/202/204/206 PINOUT DESCRIPTION
Name
GP0/ICSPDAT/CIN+
GP1/ICSPCLK/CIN-
GP2/T0CKI/COUT/
FOSC4
GP3/MCLR/VPP
Function
Input
Type
Output
Type
GP0
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPDAT
ST
CMOS In-Circuit Serial Programming™ data pin.
—
Description
CIN+
AN
GP1
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal
weak pull-up and wake-up from Sleep on pin change.
ICSPCLK
ST
CMOS In-Circuit Serial Programming clock pin.
—
Comparator input (PIC10F204/206 only).
CIN-
AN
GP2
TTL
Comparator input (PIC10F204/206 only).
T0CKI
ST
COUT
—
CMOS Comparator output (PIC10F204/206 only).
FOSC4
—
CMOS Oscillator/4 output.
GP3
TTL
—
Input pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
MCLR
ST
—
Master Clear (Reset). When configured as MCLR, this pin is
an active-low Reset to the device. Voltage on GP3/MCLR/VPP
must not exceed VDD during normal device operation or the
device will enter Programming mode. Weak pull-up always on
if configured as MCLR.
CMOS Bidirectional I/O pin.
—
Clock input to TMR0.
VPP
HV
—
Programming voltage input.
VDD
VDD
P
—
Positive supply for logic and I/O pins.
VSS
VSS
P
—
Ground reference for logic and I/O pins.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog input
2004-2014 Microchip Technology Inc.
DS40001239F-page 9
PIC10F200/202/204/206
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
The clock is internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. Internally, the PC is incremented every Q1
and the instruction is fetched from program memory
and latched into the instruction register in Q4. It is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow is shown
in Figure 3-3 and Example 3-1.
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC + 1
Fetch INST (PC)
Execute INST (PC – 1)
EXAMPLE 3-1:
PC + 2
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
SUB_1
4. BSF
GPIO, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS40001239F-page 10
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
4.0
MEMORY ORGANIZATION
The PIC10F200/202/204/206 memories are organized
into program memory and data memory. Data memory
banks are accessed using the File Select Register
(FSR).
4.1
FIGURE 4-1:
PC
9
CALL, RETLW
Stack Level 1
Stack Level 2
Program Memory Organization for
the PIC10F200/204
The PIC10F200/204 devices have a 9-bit Program
Counter (PC) capable of addressing a 512 x 12
program memory space.
Reset Vector(1)
0000h
On-chip Program
Memory
User Memory
Space
Only the first 256 x 12 (0000h-00FFh) for the
PIC10F200/204 are physically implemented (see
Figure 4-1). Accessing a location above these
boundaries will cause a wraparound within the first
256 x 12 space (PIC10F200/204). The effective
Reset vector is at 0000h (see Figure 4-1). Location
00FFh (PIC10F200/204) contains the internal clock
oscillator calibration value. This value should never
be overwritten.
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F200/204
256 Word
00FFh
0100h
01FFh
Note 1:
2004-2014 Microchip Technology Inc.
Address 0000h becomes the
effective Reset vector. Location
00FFh contains the MOVLW XX
internal oscillator calibration value.
DS40001239F-page 11
PIC10F200/202/204/206
4.2
Program Memory Organization for
the PIC10F202/206
The PIC10F202/206 devices have a 10-bit Program
Counter (PC) capable of addressing a 1024 x 12
program memory space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC10F202/206 are physically implemented (see
Figure 4-2). Accessing a location above these
boundaries will cause a wraparound within the first
512 x 12 space (PIC10F202/206). The effective
Reset vector is at 0000h (see Figure 4-2). Location
01FFh (PIC10F202/206) contains the internal clock
oscillator calibration value. This value should never
be overwritten.
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F202/206
PC
10
CALL, RETLW
Reset Vector
0000h
The Special Function Registers include the TMR0
register, the Program Counter (PCL), the STATUS
register, the I/O register (GPIO) and the File Select
Register (FSR). In addition, Special Function Registers
are used to control the I/O port configuration and
prescaler options.
The General Purpose registers are used for data and
control information under command of the instructions.
For the PIC10F200/204, the register file is composed of
seven Special Function registers and 16 General
Purpose registers (see Figure 4-3 and Figure 4-4).
For the PIC10F202/206, the register file is composed of
eight Special Function registers and 24 General
Purpose registers (see Figure 4-4).
GENERAL PURPOSE REGISTER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.9 “Indirect Data Addressing:
INDF and FSR Registers”.
User Memory
Space
On-chip Program
Memory
Data Memory Organization
Data memory is composed of registers or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFR)
and General Purpose Registers (GPR).
4.3.1
Stack Level 1
Stack Level 2
(1)
4.3
512 Words
01FFh
0200h
02FFh
Note 1:
Address 0000h becomes the
effective Reset vector. Location
01FFh contains the MOVLW XX
internal oscillator calibration value.
DS40001239F-page 12
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 4-3:
PIC10F200/204 REGISTER
FILE MAP
FIGURE 4-4:
PIC10F202/206 REGISTER
FILE MAP
File Address
File Address
00h
INDF(1)
TMR0
01h
TMR0
02h
PCL
02h
PCL
03h
STATUS
03h
STATUS
04h
FSR
04h
FSR
05h
OSCCAL
05h
OSCCAL
06h
GPIO
06h
GPIO
07h
CMCON0(2)
07h
CMCON0(2)
00h
01h
INDF
(1)
08h
08h
Unimplemented(3)
General
Purpose
Registers
0Fh
10h
General
Purpose
Registers
1Fh
1Fh
Note 1:
Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
Note 1:
Not a physical register. See Section 4.9
“Indirect Data Addressing: INDF and
FSR Registers”.
2:
PIC10F204 only. Unimplemented on the
PIC10F200 and reads as 00h.
2:
PIC10F206 only. Unimplemented on the
PIC10F202 and reads as 00h.
3:
Unimplemented, read as 00h.
2004-2014 Microchip Technology Inc.
DS40001239F-page 13
PIC10F200/202/204/206
4.3.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC10F200/202/204/206)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset(2)
Register
on Page
00h
INDF
Uses Contents of FSR to Address Data Memory (not a physical register)
xxxx xxxx
19
01h
TMR0
8-bit Real-Time Clock/Counter
xxxx xxxx
23, 27
02h(1)
PCL
Low-order 8 bits of PC
1111 1111
03h
STATUS
GPWUF
04h
FSR
Indirect Data Memory Address Pointer
05h
OSCCAL
06h
GPIO
07h
(4)
CMCON0
N/A
TRISGPIO
N/A
OPTION
Legend:
Note 1:
2:
3:
4:
5:
CWUF
(5)
—
TO
PD
Z
DC
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
—
—
GP3
GP2
GP1
CMPOUT COUTEN
POL
CMPT0CS CMPON CNREF CPREF
—
—
—
—
GPWU
GPPU
T0CS
T0SE
C
PS2
PS1
15
111x xxxx
19
FOSC4 1111 1110
17
GP0
---- xxxx
20
CWU
1111 1111
28
---- 1111
31
1111 1111
16
I/O Control Register
PSA
00-1 1xxx
18
(3)
PS0
– = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition.
The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for an
explanation of how to access these bits.
Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change
Reset.
See Table 9-1 for other Reset specific values.
PIC10F204/206 only.
PIC10F204/206 only. On all other devices, this bit is reserved and should not be used.
DS40001239F-page 14
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
4.4
STATUS Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 4-1:
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register. These instructions do not affect the Z, DC or C
bits from the STATUS register. For other instructions
which do affect Status bits, see Section 10.0
“Instruction Set Summary”.
STATUS REGISTER
R/W-0
R/W-0
U-1
R-1
R-1
R/W-x
R/W-x
R/W-x
GPWUF
CWUF(1)
—
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GPWUF: GPIO Reset bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6
CWUF: Comparator Wake-up on Change Flag bit(1)
1 = Reset due to wake-up from Sleep on comparator change
0 = After power-up or other Reset conditions.
bit 5
Reserved: Do not use. Use of this bit may affect upward compatibility with future products.
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF:
SUBWF:
RRF or RLF:
1 = A carry occurred
1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
Note 1:
This bit is used on the PIC10F204/206. For code compatibility do not use this bit on the PIC10F200/202.
2004-2014 Microchip Technology Inc.
DS40001239F-page 15
PIC10F200/202/204/206
4.5
OPTION Register
The OPTION register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A Reset sets the OPTION bits.
REGISTER 4-2:
Note:
If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of GPPU and GPWU).
Note:
If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
OPTION REGISTER
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6
GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0 = Transition on internal instruction cycle clock, FOSC/4
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on the T0CKI pin
0 = Increment on low-to-high transition on the T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0
PS: Prescaler Rate Select bits
x = Bit is unknown
Bit Value Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
.
DS40001239F-page 16
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
4.6
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal precision 4 MHz oscillator. It
contains seven bits for calibration.
Note:
Erasing the device will also erase the
pre-programmed internal calibration value
for the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
After you move in the calibration constant, do not
change the value. See Section 9.2.2 “Internal 4 MHz
Oscillator”.
REGISTER 4-3:
OSCCAL REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
FOSC4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
CAL: Oscillator Calibration bits
0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 = Minimum frequency
bit 0
FOSC4: INTOSC/4 Output Enable bit(1)
1 = INTOSC/4 output onto GP2
0 = GP2/T0CKI/COUT applied to GP2
Note 1:
x = Bit is unknown
Overrides GP2/T0CKI/COUT control registers when enabled.
2004-2014 Microchip Technology Inc.
DS40001239F-page 17
PIC10F200/202/204/206
4.7
4.7.1
Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8-0 of the PC are provided
by the GOTO instruction word. The Program Counter
Low (PCL) is mapped to PC.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC
does not come from the instruction word, but is always
cleared (Figure 4-5).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PC, ADDWF PC and
BSF PC,5.
Note:
Because PC is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
FIGURE 4-5:
LOADING OF PC
BRANCH INSTRUCTIONS
GOTO Instruction
8 7
PC
0
PCL
EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in program memory (i.e.,
the oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 0000h and
begin executing user code.
4.8
Stack
The PIC10F200/204 devices have a 2-deep, 8-bit wide
hardware PUSH/POP stack.
The PIC10F202/206 devices have a 2-deep, 9-bit wide
hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack 1
into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than two
sequential CALLs are executed, only the most recent two
return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2.
Note 1: The W register will be loaded with the
literal value specified in the instruction.
This is particularly useful for the
implementation of the data look-up tables
within the program memory.
2: There are no Status bits to indicate stack
overflows or stack underflow conditions.
3: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
Instruction Word
CALL or Modify PCL Instruction
8 7
PC
0
PCL
Instruction Word
Reset to ‘0’
DS40001239F-page 18
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
4.9
EXAMPLE 4-1:
Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
4.10
NEXT
MOVLW
MOVWF
CLRF
0x10
FSR
INDF
INCF
BTFSC
GOTO
CONTINUE
Indirect Addressing
•
•
•
•
Register file 09 contains the value 10h
Register file 0A contains the value 0Ah
Load the value 09 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 0A)
• A read of the INDR register now will return the
value of 0Ah.
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
FSR,F
FSR,4
NEXT
:
:
;initialize pointer
;to RAM
;clear INDF
;register
;inc pointer
;all done?
;NO, clear next
;YES, continue
The FSR is a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
The FSR bits are used to select data memory
addresses 00h to 1Fh.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although Status bits may be affected).
Note:
PIC10F200/202/204/206 – Do not use
banking. FSR are unimplemented
and read as ‘1’s.
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
FIGURE 4-6:
DIRECT/INDIRECT ADDRESSING (PIC10F200/202/204/206)
Direct Addressing
4
(opcode)
Indirect Addressing
4
0
Location Select
(FSR)
0
Location Select
00h
Data
Memory(1)
0Fh
10h
1Fh
Bank 0
Note 1:
For register map detail, see Section 4.3 “Data Memory Organization”.
2004-2014 Microchip Technology Inc.
DS40001239F-page 19
PIC10F200/202/204/206
5.0
I/O PORT
5.3
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP). Bits 7 through 4 are
unimplemented and read as ‘0’s. Please note that GP3
is an input-only pin. Pins GP0, GP1 and GP3 can be
configured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not pin selectable. If GP3/MCLR is
configured as MCLR, weak pull-up is always on and
wake-up on change for this pin is not enabled.
5.2
FIGURE 5-1:
TABLE 5-1:
PIC10F200/202/204/206
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
W
Reg
Q
Data
Latch
VDD VDD
Q
CK
P
N
D
TRIS ‘f’
I/O
pin
Q
TRIS
Latch
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
Priority
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is inputonly, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
WR
Port
TRIS Registers
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the
corresponding output driver in a High-Impedance
mode. A ‘0’ puts the contents of the output data latch
on the selected pins, enabling the output buffer. The
exceptions are GP3, which is input-only and the GP2/
T0CKI/COUT/FOSC4 pin, which may be controlled by
various registers. See Table 5-1.
Note:
I/O Interfacing
CK
VSS
VSS
Q
Reset
(1)
RD Port
Note 1:
See Table 3-2 for buffer type.
ORDER OF PRECEDENCE
FOR PIN FUNCTIONS
GP0
GP1
GP2
GP3
1
CIN+
CIN-
FOSC4
I/MCLR
2
TRIS GPIO
TRIS GPIO
COUT
—
3
—
—
T0CKI
—
4
—
—
TRIS GPIO
—
DS40001239F-page 20
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
TABLE 5-2:
Address
SUMMARY OF PORT REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
N/A
TRISGPIO
—
—
—
—
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
03h
STATUS
06h
GPIO
Legend:
Note 1:
2:
5.4
5.4.1
Bit 3
Bit 2
Bit 1
Bit 0
I/O Control Register
PSA
PS2
PS1
PS0
Value on
Power-On
Reset
Value on
All Other Resets
---- 1111
---- 1111
1111 1111
1111 1111
GPWUF
CWUF
—
TO
PD
Z
DC
C
00-1 1xxx
qq-q quuu(1), (2)
—
—
—
—
GP3
GP2
GP1
GP0
---- xxxx
---- uuuu
Shaded cells are not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x = unknown, u = unchanged,
q = depends on condition.
If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
If Reset was due to wake-up on comparator change, then bit 6 = 1. All other Resets will cause bit 6 = 0.
I/O Programming Considerations
EXAMPLE 5-1:
BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and rewrite the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 2 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit 2 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bidirectional
I/O pin (say bit 0), and it is defined as an input at this
time, the input signal present on the pin itself would be
read into the CPU and rewritten to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
2004-2014 Microchip Technology Inc.
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
;GPIO Inputs
;GPIO Outputs
;
;
GPIO latch
;
---------BCF
GPIO, 1 ;---- pp01
BCF
GPIO, 0 ;---- pp10
MOVLW 007h;
TRIS
GPIO
;---- pp10
;
GPIO pins
------------- pp11
---- pp11
---- pp11
Note 1:
The user may have expected the pin values to
be ---- pp00. The 2nd BCF caused GP1 to
be latched as the pin value (High).
5.4.2
SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-2).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
DS40001239F-page 21
PIC10F200/202/204/206
FIGURE 5-2:
SUCCESSIVE I/O OPERATION (PIC10F200/202/204/206)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
Fetched
MOVWF GPIO
PC + 1
MOVF GPIO, W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
GP
Port pin
written here
Instruction
Executed
DS40001239F-page 22
MOVWF GPIO
(Write to GPIO)
Port pin
sampled here
MOVF GPIO,W
(Read GPIO)
This example shows a write to GPIO followed by a
read from GPIO.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle
TPD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
NOP
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
6.0
TIMER0 MODULE AND TMR0
REGISTER (PIC10F200/202)
Counter mode is selected by setting the T0CS bit
(OPTION). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1 “Using Timer0 with an
External Clock (PIC10F200/202)”.
The Timer0 module has the following features:
•
•
•
•
8-bit timer/counter register, TMR0
Readable and writable
8-bit software programmable prescaler
Internal or external clock select:
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (OPTION). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, 1:256
are selectable. Section 6.2 “Prescaler” details the
operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
TIMER0 BLOCK DIAGRAM
Data Bus
GP2/T0CKI
Pin
FOSC/4
0
PSOUT
1
1
Programmable
Prescaler(2)
T0SE(1)
0
8
Sync with
Internal
Clocks
TMR0 Reg
PSOUT
(2 TCY delay) Sync
3
T0CS(1)
Note 1:
2:
The prescaler is shared with the Watchdog Timer (Figure 6-5).
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1
Instruction
Fetch
Timer0
PSA(1)
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
FIGURE 6-2:
PC
(Program
Counter)
PS2, PS1, PS0(1)
PC
MOVWF TMR0
T0
T0 + 1
Instruction
Executed
2004-2014 Microchip Technology Inc.
PC + 1
PC + 2
PC + 3
PC + 4
PC + 5
PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0 + 2
Write TMR0
executed
NT0 + 1
NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0 + 2
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
DS40001239F-page 23
PIC10F200/202/204/206
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC – 1
T0
Timer0
PC
PC + 2
PC + 4
Read TMR0
reads NT0
PC + 6
NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
01h
TMR0
Timer0 – 8-bit Real-Time Clock/Counter
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
—
—
—
—
PSA
Bit 2
Bit 1
Bit 0
PS2
PS1
PS0
I/O Control Register
N/A
TRISGPIO(1)
Legend:
Note 1:
Shaded cells not used by Timer0. – = unimplemented, x = unknown,
The TRIS of the T0CKI pin is overridden when T0CS = 1.
6.1
PC + 5
NT0
Write TMR0
executed
TABLE 6-1:
PC + 3
T0 + 1
Instruction
Executed
Address
PC + 1
Using Timer0 with an External
Clock (PIC10F200/202)
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
Value on
Power-On
Reset
Value on
All Other
Resets
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
---- 1111
---- 1111
u = unchanged.
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI to be
high for at least 2 TOSC (and a small RC delay of 2
Tt0H) and low for at least 2 TOSC (and a small RC delay
of 2 Tt0H). Refer to the electrical specification of the
desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4 TOSC (and a small RC delay of 4
Tt0H) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they do
not violate the minimum pulse width requirement of
Tt0H. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
DS40001239F-page 24
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output(2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
Note 1:
6.2
T0
T0 + 2
Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2:
External clock if no prescaler selected; prescaler output otherwise.
3:
The arrows indicate the points in time where sampling occurs.
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 9.6
“Watchdog Timer (WDT)”). For simplicity, this counter
is being referred to as “prescaler” throughout this data
sheet.
Note:
T0 + 1
The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
The PSA and PS bits (OPTION) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a Reset, the prescaler contains all ‘0’s.
2004-2014 Microchip Technology Inc.
6.2.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 6-1)
must be executed when changing the prescaler
assignment from Timer0 to the WDT.
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0 WDT)
CLRWDT
;Clear WDT
CLRF
TMR0
;Clear TMR0 & Prescaler
MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)
OPTION
;are required only if
;desired
CLRWDT
;PS are 000 or 001
MOVLW ‘00xx1xxx’b ;Set Postscaler to
OPTION
;desired WDT rate
DS40001239F-page 25
PIC10F200/202/204/206
EXAMPLE 6-2:
To change the prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
MOVLW
‘xxxx0xxx’
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY (= FOSC/4)
Data Bus
0
GP2/T0CKI(2)
Pin
1
8
M
U
X
1
M
U
X
0
T0SE(1)
T0CS(1)
0
Watchdog
Timer
1
M
U
X
Sync
2
Cycles
TMR0 Reg
PSA(1)
8-bit Prescaler
8
8-to-1 MUX
PS(1)
PSA(1)
WDT Enable bit
1
0
MUX
PSA(1)
WDT
Time-out
Note 1:
2:
T0CS, T0SE, PSA, PS are bits in the OPTION register.
T0CKI is shared with pin GP2 on the PIC10F200/202/204/206.
DS40001239F-page 26
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
7.0
TIMER0 MODULE AND TMR0
REGISTER (PIC10F204/206)
The second Counter mode uses the output of the
comparator to increment Timer0. It can be entered in
two different ways. The first way is selected by setting
the T0CS bit (OPTION) and clearing the CMPT0CS
bit (CMCON); (COUTEN [CMCON]) does not
affect this mode of operation. This enables an internal
connection between the comparator and the Timer0.
The Timer0 module has the following features:
•
•
•
•
8-bit timer/counter register, TMR0
Readable and writable
8-bit software programmable prescaler
Internal or external clock select:
- Edge select for external clock
- External clock from either the T0CKI pin or
from the output of the comparator
The second way is selected by setting the T0CS bit
bit
(OPTION),
setting
the
CMPT0CS
(CMCON0) and clearing the COUTEN bit
(CMCON0). This allows the output of the
comparator onto the T0CKI pin, while keeping the
T0CKI input active. Therefore, any comparator change
on the COUT pin is fed back into the T0CKI input. The
T0SE bit (OPTION) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input as discussed in
Section 7.1 “Using Timer0 with an External Clock
(PIC10F204/206)”
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (OPTION). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 7.2 “Prescaler” details
the operation of the prescaler.
There are two types of Counter mode. The first Counter
mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CS bit (OPTION), setting
the CMPT0CS bit (CMCON0) and setting the
COUTEN bit (CMCON0). In this mode, Timer0 will
increment either on every rising or falling edge of pin
T0CKI. The T0SE bit (OPTION) determines the
source edge. Clearing the T0SE bit selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 7.1 “Using Timer0 with
an External Clock (PIC10F204/206)”.
A summary of registers associated with the Timer0
module is found in Table 7-1.
TIMER0 BLOCK DIAGRAM (PIC10F204/206)
FIGURE 7-1:
T0CKI
Pin
Data Bus
FOSC/4
Internal
Comparator
Output
0
PSOUT
1
1
1
0
T0SE
Programmable
Prescaler(2)
(1)
0
8
Sync with
Internal
Clocks
TMR0 Reg
PSOUT
(2 TCY delay) Sync
3
CMPT0CS(3)
T0CS(1)
Note 1:
2:
3:
PS2, PS1, PS0(1)
PSA(1)
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
The prescaler is shared with the Watchdog Timer (Figure 7-5).
Bit CMPT0CS is located in the CMCON0 register, CMCON0.
2004-2014 Microchip Technology Inc.
DS40001239F-page 27
PIC10F200/202/204/206
FIGURE 7-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC – 1
Instruction
Fetch
PC
PC + 1
MOVWF TMR0
T0
Timer0
T0 + 1
T0 + 2
Instruction
Executed
PC + 3
PC + 4
PC+5
NT0 + 1
NT0
Write TMR0
executed
FIGURE 7-3:
PC + 2
PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0 + 2
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC – 1
T0
Timer0
PC
PC + 1
T0 + 1
Address
PC + 3
PC + 4
PC + 5
NT0
Instruction
Executed
Write TMR0
executed
TABLE 7-1:
PC + 2
Read TMR0
reads NT0
PC + 6
NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
01h
TMR0
Timer0 – 8-bit Real-Time Clock/Counter
xxxx xxxx
uuuu uuuu
07h
CMCON0
CMPOUT
COUTEN
POL
1111 1111
uuuu uuuu
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
1111 1111
1111 1111
N/A
TRISGPIO(1)
—
—
—
—
---- 1111
---- 1111
Legend:
Note 1:
7.1
CMPT0CS CMPON CNREF CPREF CWU
Shaded cells not used by Timer0.
– = unimplemented,
The TRIS of the T0CKI pin is overridden when T0CS = 1.
Using Timer0 with an External
Clock (PIC10F204/206)
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of an external clock with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-4). Therefore, it is necessary for T0CKI or the
comparator output to be high for at least 2 TOSC (and a
DS40001239F-page 28
PSA
PS2
PS1
PS0
I/O Control Register
x = unknown,
u = unchanged.
small RC delay of 2 Tt0H) and low for at least 2 TOSC
(and a small RC delay of 2 Tt0H). Refer to the electrical
specification of the desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI or the
comparator output to have a period of at least 4 TOSC
(and a small RC delay of 4 Tt0H) divided by the
prescaler value. The only requirement on T0CKI or the
comparator output high and low time is that they do not
violate the minimum pulse width requirement of Tt0H.
Refer to parameters 40, 41 and 42 in the electrical
specification of the desired device.
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
7.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 7-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 7-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2
Q3 Q4
Q1 Q2 Q3
External Clock Input or
Prescaler Output(2)
Q4
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
Note 1:
7.2
T0
T0 + 2
Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2:
External clock if no prescaler selected; prescaler output otherwise.
3:
The arrows indicate the points in time where sampling occurs.
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Figure 9-6). For
simplicity, this counter is being referred to as
“prescaler” throughout this data sheet.
Note:
T0 + 1
The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
The PSA and PS bits (OPTION) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a Reset, the prescaler contains all ‘0’s.
2004-2014 Microchip Technology Inc.
7.2.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 7-1)
must be executed when changing the prescaler
assignment from Timer0 to the WDT.
EXAMPLE 7-1:
CHANGING PRESCALER
(TIMER0 WDT)
CLRWDT
;Clear WDT
CLRF
TMR0
;Clear TMR0 & Prescaler
MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7)
OPTION
;are required only if
;desired
CLRWDT
;PS are 000 or 001
MOVLW ‘00xx1xxx’b ;Set Postscaler to
OPTION
;desired WDT rate
To change the prescaler from the WDT to the Timer0
module, use the sequence shown in Example 7.2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
DS40001239F-page 29
PIC10F200/202/204/206
EXAMPLE 7-2:
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
MOVLW
‘xxxx0xxx’
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
FIGURE 7-5:
GP2/T0CKI
Pin
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
(2)
TCY (= FOSC/4)
Data Bus
0
1
Comparator
Output
1
8
M
U
X
1
M
U
X
0
0
T0SE(1)
T0CS(1)
Sync
2
Cycles
TMR0 Reg
PSA(1)
CMPT0CS(3)
0
Watchdog
Timer
M
U
X
1
8-bit Prescaler
8
8-to-1 MUX
PS(1)
PSA(1)
WDT Enable bit
1
0
MUX
PSA(1)
WDT
Time-out
Note 1:
T0CS, T0SE, PSA, PS are bits in the OPTION register.
2:
T0CKI is shared with pin GP2.
3:
Bit CMPT0CS is located in the CMCON0 register.
DS40001239F-page 30
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
8.0
COMPARATOR MODULE
The comparator module contains one Analog
comparator. The inputs to the comparator are
multiplexed with GP0 and GP1 pins. The output of the
comparator can be placed on GP2.
The CMCON0 register, shown in Register 8-1, controls
the comparator operation. A block diagram of the
comparator is shown in Figure 8-1.
REGISTER 8-1:
CMCON0 REGISTER
R-1
CMPOUT
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
COUTEN
POL
CMPT0CS
CMPON
CNREF
CPREF
CWU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CMPOUT: Comparator Output bit
1 = VIN+ > VIN0 = VIN+ < VIN-
bit 6
COUTEN: Comparator Output Enable bit(1, 2)
1 = Output of comparator is NOT placed on the COUT pin
0 = Output of comparator is placed in the COUT pin
bit 5
POL: Comparator Output Polarity bit(2)
1 = Output of comparator not inverted
0 = Output of comparator inverted
bit 4
CMPT0CS: Comparator TMR0 Clock Source bit(2)
1 = TMR0 clock source selected by T0CS control bit
0 = Comparator output used as TMR0 clock source
bit 3
CMPON: Comparator Enable bit
1 = Comparator is on
0 = Comparator is off
bit 2
CNREF: Comparator Negative Reference Select bit(2)
1 = CIN- pin(3)
0 = Internal voltage reference
bit 1
CPREF: Comparator Positive Reference Select bit(2)
1 = CIN+ pin(3)
0 = CIN- pin(3)
bit 0
CWU: Comparator Wake-up on Change Enable bit(2)
1 = Wake-up on comparator change is disabled
0 = Wake-up on comparator change is enabled.
Note 1:
2:
3:
x = Bit is unknown
Overrides T0CS bit for TRIS control of GP2.
When the comparator is turned on, these control bits assert themselves. When the comparator is off, these
bits have no effect on the device operation and the other control registers have precedence.
PIC10F204/206 only.
2004-2014 Microchip Technology Inc.
DS40001239F-page 31
PIC10F200/202/204/206
8.1
Comparator Configuration
The on-board comparator inputs, (GP0/CIN+, GP1/
CIN-), as well as the comparator output (GP2/COUT),
are steerable. The CMCON0, OPTION and TRIS
registers are used to steer these pins (see Figure 8-1).
If the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
change delay shown in Table 12-1.
FIGURE 8-1:
Note:
The comparator can have an inverted
output (see Figure 8-1).
BLOCK DIAGRAM OF THE COMPARATOR
T0CKI/GP2/COUT
CPREF
C+
COUTEN
+
C-
COUT (Register)
-
Band Gap Buffer
(0.6V)
CNREF
POL
CMPON
T0CKI
T0CKI Pin
T0CKSEL
CWU
Q
D
S
CWUF
TABLE 8-1:
Read
CMCON
TMR0 CLOCK SOURCE
FUNCTION MUXING
T0CS
CMPT0CS
COUTEN
Source
0
x
x
Internal Instruction
Cycle
1
0
0
CMPOUT
1
0
1
CMPOUT
1
1
0
CMPOUT
1
1
1
T0CKI
DS40001239F-page 32
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
8.2
Comparator Operation
8.5
A single comparator is shown in Figure 8-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 8-2 represent
the uncertainty due to input offsets and response time.
See Table 12-1 for Common Mode Voltage.
FIGURE 8-2:
SINGLE COMPARATOR
Vin+
+
Vin-
–
Result
Note:
8.6
Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is
specified.
Comparator Wake-up Flag
The comparator wake-up flag is set whenever all of the
following conditions are met:
• CWU = 0 (CMCON0)
• CMCON0 has been read to latch the last known
state of the CMPOUT bit (MOVF CMCON0, W)
• Device is in Sleep
• The output of the comparator has changed state
8.7
VIN+
Result
Comparator Reference
An internal reference signal may be used depending on
the Comparator Operating mode. The analog signal
that is present at VIN- is compared to the signal at VIN+
and the digital output of the comparator is adjusted
accordingly (Figure 8-2). Please see Table 12-1 for
internal reference specifications.
8.4
The comparator output is read through CMCON0
register. This bit is read-only. The comparator output
may also be used internally, see Figure 8-1.
The wake-up flag may be cleared in software or by
another device Reset.
VIN-
8.3
Comparator Output
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is to have a valid level. If the
comparator inputs are changed, a delay must be used
to allow the comparator to settle to its new state. Please
see Table 12-1 for comparator response time
specifications.
2004-2014 Microchip Technology Inc.
Comparator Operation During
Sleep
When the comparator is active and the device is placed
in Sleep mode, the comparator remains active. While
the comparator is powered-up, higher Sleep currents
than shown in the power-down current specification will
occur. To minimize power consumption while in Sleep
mode, turn off the comparator before entering Sleep.
8.8
Effects of a Reset
A Power-on Reset (POR) forces the CMCON0 register
to its Reset state. This forces the comparator module to
be in the comparator Reset mode. This ensures that all
potential inputs are analog inputs. Device current is
minimized when analog inputs are present at Reset
time. The comparator will be powered-down during the
Reset interval.
8.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
DS40001239F-page 33
PIC10F200/202/204/206
FIGURE 8-3:
ANALOG INPUT MODE
VDD
VT = 0.6V
RS < 10 k
RIC
AIN
CPIN
5 pF
VA
ILEAKAGE
±500 nA
VT = 0.6V
VSS
Legend: CPIN
VT
ILEAKAGE
RIC
RS
VA
TABLE 8-2:
Address
= Input Capacitance
= Threshold Voltage
= Leakage Current at the Pin
= Interconnect Resistance
= Source Impedance
= Analog Voltage
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CWUF
—
TO
PD
Z
DC
C
03h
STATUS
GPWUF
07h
CMCON0
CMPOUT COUTEN
N/A
TRISGPIO
Legend:
—
—
POL
—
CMPT0CS CMPON CNREF CPREF CWU
—
I/O Control Register
Value on
POR
Value on
All Other
Resets
00-1 1xxx qq0q quuu
1111 1111 uuuu uuuu
---- 1111 ---- 1111
x = Unknown, u = Unchanged, – = Unimplemented, read as ‘0’, q = Depends on condition.
DS40001239F-page 34
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
processors are special circuits that deal with the needs
of real-time applications. The PIC10F200/202/204/206
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide powersaving operating modes and offer code protection.
These features are:
• Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Watchdog Timer (WDT)
- Wake-up from Sleep on pin change
- Wake-up from Sleep on comparator change
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
• Clock Out
REGISTER 9-1:
The PIC10F200/202/204/206 devices have a
Watchdog Timer, which can be shut off only through
Configuration bit WDTE. It runs off of its own RC
oscillator for added reliability. When using INTRC,
there is an 18 ms delay only on VDD power-up. With
this timer on-chip, most applications need no external
Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through a change on input pins, wake-up from
comparator change, or through a Watchdog Timer
time-out.
9.1
Configuration Bits
The PIC10F200/202/204/206 Configuration Words
consist of 12 bits. Configuration bits can be
programmed to select various device configurations.
One bit is the Watchdog Timer enable bit, one bit is the
MCLR enable bit and one bit is for code protection (see
Register 9-1).
CONFIGURATION WORD FOR PIC10F200/202/204/206(1,2)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
—
—
—
—
—
—
MCLRE
CP
WDTE
—
—
bit 11
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 11-5 Unimplemented: Read as ‘0’
bit 4
MCLRE: GP3/MCLR Pin Function Select bit
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3
CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
Reserved: Read as ‘0’
Note 1:
2:
Refer to the “PIC10F200/202/204/206 Memory Programming Specifications” (DS41228) to determine how
to access the Configuration Word. The Configuration Word is not user addressable during device
operation.
INTRC is the only oscillator mode offered on the PIC10F200/202/204/206.
2004-2014 Microchip Technology Inc.
DS40001239F-page 35
PIC10F200/202/204/206
9.2
Oscillator Configurations
9.2.1
9.3
OSCILLATOR TYPES
The PIC10F200/202/204/206 devices are offered with
Internal Oscillator mode only.
• INTOSC: Internal 4 MHz Oscillator
9.2.2
INTERNAL 4 MHz OSCILLATOR
The internal oscillator provides a 4 MHz (nominal) system
clock (see Section 12.0 “Electrical Characteristics” for
information on variation over voltage and temperature).
In addition, a calibration instruction is programmed into
the last address of memory, which contains the
calibration value for the internal oscillator. This location
is always uncode protected, regardless of the codeprotect settings. This value is programmed as a MOVLW
xx instruction where xx is the calibration value and is
placed at the Reset vector. This will load the W register
with the calibration value upon Reset and the PC will
then roll over to the users program at address 0x000.
The user then has the option of writing the value to the
OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
Note:
Reset
The device differentiates between various kinds of
Reset:
•
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT time-out Reset during normal operation
WDT time-out Reset during Sleep
Wake-up from Sleep on pin change
Wake-up from Sleep on comparator change
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD, GPWUF and CWUF bits. They are set or
cleared differently in different Reset situations. These
bits are used in software to determine the nature of
Reset. See Table 9-1 for a full description of Reset
states of all registers.
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
TABLE 9-1:
RESET CONDITIONS FOR REGISTERS – PIC10F200/202/204/206
Register
Address
Power-on Reset
MCLR Reset, WDT Time-out,
Wake-up On Pin Change, Wake on
Comparator Change
qqqq qqqu(1)
qqqq qqqu(1)
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
1111 1111
STATUS
03h
00-1 1xxx
q00q quuu(2)
STATUS(3)
03h
00-1 1xxx
qq0q quuu(2)
FSR
04h
111x xxxx
111u uuuu
OSCCAL
05h
1111 1110
uuuu uuuu
GPIO
06h
---- xxxx
---- uuuu
07h
1111 1111
uuuu uuuu
—
1111 1111
1111 1111
—
---- 1111
---- 1111
W
—
INDF
CMCON
(3)
OPTION
TRISGPIO
Legend:
Note 1:
2:
3:
u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Bits of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory.
See Table 9-2 for Reset value for specific conditions.
PIC10F204/206 only.
DS40001239F-page 36
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
TABLE 9-2:
RESET CONDITION FOR SPECIAL REGISTERS
—
STATUS Address: 03h
PCL Address: 02h
Power-on Reset
00-1 1xxx
1111 1111
MCLR Reset during normal operation
000u uuuu
1111 1111
MCLR Reset during Sleep
0001 0uuu
1111 1111
WDT Reset during Sleep
0000 0uuu
1111 1111
WDT Reset normal operation
0000 uuuu
1111 1111
Wake-up from Sleep on pin change
1001 0uuu
1111 1111
Wake-up from Sleep on comparator change
0101 0uuu
1111 1111
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.
9.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 9-1.
FIGURE 9-1:
MCLR SELECT
GPWU
GP3/MCLR/VPP
Internal MCLR
MCLRE
9.4
Power-on Reset (POR)
The PIC10F200/202/204/206 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the internal POR,
program the GP3/MCLR/VPP pin as MCLR and tie
through a resistor to VDD, or program the pin as GP3.
An internal weak pull-up resistor is implemented using
a transistor (refer to Table 12-2 for the pull-up resistor
ranges). This will eliminate external RC components
usually needed to create a Power-on Reset. A
maximum rise time for VDD is specified. See
Section 12.0 “Electrical Characteristics” for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters
(voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
devices must be held in Reset until the operating
parameters are met.
The Power-on Reset circuit and the Device Reset
Timer (see Section 9.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 9-3. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
In Figure 9-4, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be GP3). The VDD is stable before
the Start-up Timer times out and there is no problem in
getting a proper Reset. However, Figure 9-5 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this situation, when the Start-up Timer times
out, VDD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 9-4).
Note:
When the devices start normal operation
(exit the Reset condition), device
operating parameters (voltage, frequency,
temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Notes
AN522 “Power-up Considerations”, (DS00522) and
AN607 “Power-up Trouble Shooting”, (DS00000607).
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 9-2.
2004-2014 Microchip Technology Inc.
DS40001239F-page 37
PIC10F200/202/204/206
FIGURE 9-2:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
GP3/MCLR/VPP
MCLR Reset
MCLRE
WDT Reset
WDT Time-out
S
Q
R
Q
Start-up Timer
CHIP Reset
(10 s or 18 ms)
Pin Change
Sleep
Wake-up on pin change Reset
FIGURE 9-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 9-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
DS40001239F-page 38
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 9-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 VDD min.
2004-2014 Microchip Technology Inc.
DS40001239F-page 39
PIC10F200/202/204/206
9.5
Device Reset Timer (DRT)
On the PIC10F200/202/204/206 devices, the DRT runs
any time the device is powered-up.
The DRT operates on an internal oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
The on-chip DRT keeps the devices in a Reset
condition for approximately 18 ms after MCLR has
reached a logic high (VIH MCLR) level. Programming
GP3/MCLR/VPP as MCLR and using an external RC
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/
or space restricted applications, as well as allowing the
use of the GP3/MCLR/VPP pin as a general purpose
input.
The Device Reset Time delays will vary from chip-tochip due to VDD, temperature and process variation.
See AC parameters for details.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 9.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 9-3:
9.6
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, VDD and part-to-part
process variations (see DC specs).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
9.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
DRT PERIOD
POR Reset
Subsequent
Resets
18 ms (typical)
10 s (typical)
Oscillator
INTOSC
9.6.1
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
internal 4 MHz oscillator. This means that the WDT will
run even if the main processor clock has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation or Sleep, a WDT Reset or
wake-up Reset, generates a device Reset.
The TO bit (STATUS) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by
programming the configuration WDTE as a ‘0’ (see
Section 9.1 “Configuration Bits”). Refer to the
PIC10F200/202/204/206 Programming Specifications
to determine how to access the Configuration Word.
DS40001239F-page 40
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 9-6:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
1
Watchdog
Time
M
U
X
Postscaler
8-to-1 MUX
PS
PSA
WDT Enable
Configuration
Bit
To Timer0 (Figure 6-4)
0
1
MUX
PSA
WDT Time-out
TABLE 9-4:
Address
N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
Value on
Power-On
Reset
Value on
All Other
Resets
1111 1111
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u = unchanged.
2004-2014 Microchip Technology Inc.
DS40001239F-page 41
PIC10F200/202/204/206
9.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF, CWUF)
The TO, PD, GPWUF and CWUF bits in the STATUS
register can be tested to determine if a Reset condition
has been caused by a power-up condition, a MCLR,
Watchdog Timer (WDT) Reset, wake-up on comparator
change or wake-up on pin change.
TABLE 9-5:
TO, PD, GPWUF, CWUF STATUS AFTER RESET
CWUF
GPWUF
TO
PD
Reset Caused By
0
0
0
0
WDT wake-up from Sleep
0
0
0
u
WDT time-out (not from Sleep)
0
0
1
0
MCLR wake-up from Sleep
0
0
1
1
Power-up
0
0
u
u
MCLR not during Sleep
0
1
1
0
Wake-up from Sleep on pin change
1
0
1
0
Wake-up from Sleep on comparator change
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: The TO, PD, GPWUF and CWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the
MCLR input does not change the TO, PD, GPWUF or CWUF Status bits.
9.8
Reset on Brown-out
FIGURE 9-8:
A Brown-out Reset is a condition where device power
(VDD) dips below its minimum value, but not to zero,
and then recovers. The device should be reset in the
event of a brown-out.
To reset PIC10F200/202/204/206 devices when a
Brown-out Reset occurs, external brown-out protection
circuits may be built, as shown in Figure 9-7 and
Figure 9-8.
FIGURE 9-7:
VDD
VDD
R1
Q1 MCLR(2)
R2
Note 1:
VDD
33k
10k
Q1
MCLR(2)
PIC10F20X
40k(1)
2:
PIC10F20X
40k(1)
BROWN-OUT
PROTECTION CIRCUIT 1
VDD
Note 1:
BROWN-OUT
PROTECTION CIRCUIT 2
2:
This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
R1
= 0.7V
VDD •
R1 + R2
Pin must be confirmed as MCLR.
This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
Pin must be confirmed as MCLR.
DS40001239F-page 42
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 9-9:
BROWN-OUT
PROTECTION CIRCUIT 3
VDD
MCP809
VSS
Bypass
Capacitor
9.9.2
The device can wake-up from Sleep through one of
the following events:
1.
VDD
2.
VDD
RST
MCLR
3.
PIC10F20X
4.
Note:
9.9
This brown-out protection circuit employs
Microchip
Technology’s
MCP809
microcontroller supervisor. There are
seven different trip point selections to
accommodate 5V to 3V systems.
Power-down Mode (Sleep)
A device may be powered-down (Sleep) and later
powered-up (wake-up from Sleep).
9.9.1
SLEEP
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS) is set, the PD
bit (STATUS) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
Note:
A Reset generated by a WDT time-out
does not drive the MCLR pin low.
For lowest current consumption while powered-down,
the T0CKI input should be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level if MCLR is
enabled.
2004-2014 Microchip Technology Inc.
WAKE-UP FROM SLEEP
An external Reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
A Watchdog Timer time-out Reset (if WDT was
enabled).
A change on input pin GP0, GP1 or GP3 when
wake-up on change is enabled.
A comparator output change has occurred when
wake-up on comparator change is enabled.
These events cause a device Reset. The TO, PD
GPWUF and CWUF bits can be used to determine the
cause of device Reset. The TO bit is cleared if a WDT
time-out occurred (and caused wake-up). The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked. The GPWUF bit indicates a change in state
while in Sleep at pins GP0, GP1 or GP3 (since the last
file or bit operation on GP port). The CWUF bit
indicates a change in the state while in Sleep of the
comparator output.
Caution: Right before entering Sleep, read the
input pins. When in Sleep, wake-up
occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before
re-entering Sleep, a wake-up will occur
immediately even if no pins change
while in Sleep mode.
Note:
The WDT is cleared when the device
wakes from Sleep, regardless of the
wake-up source.
DS40001239F-page 43
PIC10F200/202/204/206
9.10
Program Verification/Code
Protection
FIGURE 9-10:
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (Reset
vector) can be read, regardless of the code protection
bit setting.
9.11
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during Program/Verify.
External
Connector
Signals
TYPICAL IN-CIRCUIT
SERIAL
PROGRAMMING™
CONNECTION
To Normal
Connections
PIC10F20X
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1
Data I/O
GP0
Use only the lower four bits of the ID locations and
always program the upper eight bits as ‘0’s.
9.12
In-Circuit Serial Programming™
VDD
To Normal
Connections
The PIC10F200/202/204/206 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground and the
programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware, to be programmed.
The devices are placed into a Program/Verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 becomes the programming clock
and GP0 becomes the programming data. Both GP1
and GP0 are Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. Depending on the command, 16 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
details of serial programming, please refer to the
PIC10F200/202/204/206 Programming Specifications.
A typical In-Circuit Serial Programming connection is
shown in Figure 9-10.
DS40001239F-page 44
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
10.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instruction type and one or
more operands which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 10-1, while the various opcode
fields are summarized in Table 10-1.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 s.
Figure 10-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
where ‘h’ signifies a hexadecimal digit.
FIGURE 10-1:
Byte-oriented file register operations
11
TABLE 10-1:
f
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility with
all Microchip software tools.
d
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label
TOS
PC
WDT
TO
8 7
5 4
b (BIT #)
0
f (FILE #)
b = 3-bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations – GOTO instruction
11
9
8
OPCODE
0
k (literal)
k = 9-bit immediate value
Watchdog Timer counter
Time-out bit
Power-down bit
[
]
Options
(
)
Contents
italics
OPCODE
Top-of-Stack
Destination, either the W register or the specified
register file location
11
Program Counter
PD
< >
0
f (FILE #)
Label name
dest
4
Bit-oriented file register operations
Description
Register file address (0x00 to 0x7F)
5
d
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
OPCODE FIELD
DESCRIPTIONS
Field
6
OPCODE
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
GENERAL FORMAT FOR
INSTRUCTIONS
Assigned to
Register bit field
In the set of
User defined term (font is courier)
2004-2014 Microchip Technology Inc.
DS40001239F-page 45
PIC10F200/202/204/206
TABLE 10-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
12-Bit Opcode
Description
Cycles
MSb
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
LSb
Status
Notes
Affected
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff C, DC, Z 1, 2, 4
ffff
Z
2, 4
ffff
Z
4
0000
Z
ffff
Z
ffff
Z
2, 4
ffff
None
2, 4
ffff
Z
2, 4
ffff
None
2, 4
ffff
Z
2, 4
ffff
Z
2, 4
ffff
None
1, 4
0000
None
ffff
C
2, 4
ffff
C
2, 4
ffff C, DC, Z 1, 2, 4
ffff
None
2, 4
ffff
Z
2, 4
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
AND literal with W
Call Subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Load OPTION register
Return, place Literal in W
Go into Standby mode
Load TRIS register
Exclusive OR literal to W
1
1
1(2)
1(2)
0100
0101
0110
0111
2, 4
2, 4
LITERAL AND CONTROL OPERATIONS
Note 1:
2:
3:
4:
k
k
k
—
k
—
f
k
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
1
3
The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.7 “Program Counter”.
When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS40001239F-page 46
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
ADDWF
Add W and f
BCF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BCF
Operands:
0 f 31
d 01
Operands:
0 f 31
0b7
Operation:
(W) + (f) (dest)
Operation:
0 (f)
Status Affected: C, DC, Z
Status Affected:
None
Description:
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 31
0b7
Status Affected: Z
Operation:
1 (f)
Description:
Status Affected:
None
ANDLW
Syntax:
f,d
Bit Clear f
Add the contents of the W register
and register ‘f’. If ‘d’ is ‘0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
AND literal with W
[ label ] ANDLW
k
Operands:
0 k 255
Operation:
(W).AND. (k) (W)
The contents of the W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 31
d [0,1]
Operation:
f,d
Description:
The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
2004-2014 Microchip Technology Inc.
f,b
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0 f 31
0b7
Operation:
skip if (f) = 0
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next
instruction fetched during the
current instruction execution is
discarded, and a NOP is executed
instead, making this a 2-cycle
instruction.
(W) .AND. (f) (dest)
Status Affected: Z
f,b
DS40001239F-page 47
PIC10F200/202/204/206
BTFSS
Bit Test f, Skip if Set
CLRW
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRW
0 f 31
0b VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Max. output current sunk by any I/O pin .............................................................................................................. 25 mA
Max. output current sourced by any I/O pin ......................................................................................................... 25 mA
Max. output current sourced by I/O port .............................................................................................................. 75 mA
Max. output current sunk by I/O port ................................................................................................................... 75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2004-2014 Microchip Technology Inc.
DS40001239F-page 57
PIC10F200/202/204/206
PIC10F200/202/204/206 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
FIGURE 12-1:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
DS40001239F-page 58
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
12.1
DC Characteristics: PIC10F200/202/204/206 (Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C TA +85°C (industrial)
DC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Min. Typ.(1) Max. Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
V
See Figure 12-1
D002
VDR
RAM Data Retention Voltage(2)
1.5*
—
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage
to ensure Power-on Reset
—
Vss
—
V
D004
SVDD
VDD Rise Rate
to ensure Power-on Reset
0.05*
—
—
V/ms
IDD
Supply Current(3)
—
—
175
0.63
275
1.1
A
mA
VDD = 2.0V
VDD = 5.0V
—
—
0.1
0.35
1.2
2.4
A
A
VDD = 2.0V
VDD = 5.0V
—
—
1.0
7
3
16
A
A
VDD = 2.0V
VDD = 5.0V
—
—
12
44
23
80
A
A
VDD = 2.0V
VDD = 5.0V
—
85
175
115
195
A
A
VDD = 2.0V
VDD = 5.0V
D010
IPD
Power-down Current(4)
D020
IWDT
WDT Current(5)
D022
ICMP
Comparator Current(5)
D023
IVREF
Internal Reference Current(5,6)
D024
*
Note 1:
2:
3:
4:
5:
6:
These parameters are characterized but not tested.
Data in the Typical (“Typ.”) column is based on characterization results at 25C. This data is for design
guidance only and is not tested.
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, bus rate, internal code execution pattern and temperature also have an impact on the current
consumption.
a) The test conditions for all IDD measurements in active operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state
and tied to VDD or VSS.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled.
Measured with the comparator enabled.
2004-2014 Microchip Technology Inc.
DS40001239F-page 59
PIC10F200/202/204/206
12.2
DC Characteristics: PIC10F200/202/204/206 (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C TA +125°C (extended)
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min. Typ.(1) Max.
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
V
See Figure 12-1
D002
VDR
RAM Data Retention
Voltage(2)
1.5*
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage
to ensure Power-on Reset
—
Vss
—
V
D004
SVDD
VDD Rise Rate
to ensure Power-on Reset
0.05*
—
—
V/ms
IDD
Supply Current(3)
—
—
175
0.63
275
1.1
A
mA
VDD = 2.0V
VDD = 5.0V
—
—
0.1
0.35
9
15
A
A
VDD = 2.0V
VDD = 5.0V
—
—
1.0
7
18
22
A
A
VDD = 2.0V
VDD = 5.0V
—
—
12
42
27
85
A
A
VDD = 2.0V
VDD = 5.0V
—
85
175
120
200
A
A
VDD = 2.0V
VDD = 5.0V
D010
IPD
Power-down Current(4)
D020
IWDT
WDT Current(5)
D022
ICMP
Comparator Current(5)
D023
VREF
Internal Reference Current(5,6)
D024
*
Note 1:
2:
3:
4:
5:
6:
These parameters are characterized but not tested.
Data in the Typical (“Typ.”) column is based on characterization results at 25C. This data is for design
guidance only and is not tested.
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, bus rate, internal code execution pattern and temperature also have an impact on the current
consumption.
a) The test conditions for all IDD measurements in active operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep
mode.
Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state
and tied to VDD or VSS.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled.
Measured with the Comparator enabled.
DS40001239F-page 60
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
12.3
DC Characteristics: PIC10F200/202/204/206 (Industrial, Extended)
DC CHARACTERISTICS
Param.
Sym.
No.
VIL
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating temperature -40°C TA +85°C (industrial)
-40°C TA +125°C (extended)
Operating voltage VDD range as described in DC specification
Min.
Typ.†
Max.
Units
Vss
—
0.8
V
Vss
—
0.15
VDD
V
Vss
—
0.2 VDD
V
Vss
—
0.2 VDD
V
Conditions
Input Low Voltage
I/O ports:
D030
with TTL buffer
D030A
D031
with Schmitt Trigger
buffer
D032
MCLR, T0CKI
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger
buffer
MCLR, T0CKI
D042
D070
For all 4.5V VDD 5.5V
IPUR
GPIO weak pull-up
current(3)
IIL
Input Leakage Current(1, 2)
—
2.0
—
VDD
V
4.5V VDD 5.5V
0.25 VDD + 0.8
—
VDD
V
Otherwise
0.8VDD
—
VDD
V
For entire VDD range
0.8VDD
—
VDD
V
50
250
400
A
VDD = 5V, VPIN = VSS
D060
I/O ports
—
±0.1
±1
A
Vss VPIN VDD, Pin at
high-impedance
D061
GP3/MCLR(3)
—
±0.7
±5
A
Vss VPIN VDD
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
—
—
0.6
V
IOL = 7.0 mA, VDD = 4.5V,
-40C to +125C
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
VDD – 0.7
—
—
V
IOH = -2.5 mA, VDD = 4.5V,
-40C to +125C
—
50*
pF
Output Low Voltage
D080
I/O ports
D080A
Output High Voltage
D090
I/O ports(2)
D090A
Capacitive Loading Specs on Output Pins
D101
All I/O pins
—
† Data in “Typ.” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
* These parameters are for design guidance only and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
2: Negative current is defined as coming out of the pin.
3: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage
current of the MCLR circuit is higher than the standard I/O logic.
2004-2014 Microchip Technology Inc.
DS40001239F-page 61
PIC10F200/202/204/206
TABLE 12-1:
COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No.
D300
Sym.
Characteristics
VOS
Input Offset Voltage
Min.
Typ.†
Max.
Units
—
5.0
10
mV
D301
VCM
Input Common Mode Voltage
0
—
VDD–1.5*
V
D302
CMRR
Common Mode Rejection Ratio
55*
—
—
dB
D303*
TRT
Response Time
Falling
—
150
600
ns
Rising
—
200
1000
ns
—
—
10*
s
0.55
0.6
0.65
V
D304*
TMC2COV Comparator Mode Change to
Output Valid
D305
VIVRF
Internal Reference Voltage
Comments
(VDD - 1.5)/2
(Note 1)
2.0V VDD 5.5V
-40°C TA ±125°C
(extended)
* These parameters are characterized but not tested.
† Data in ‘Typ.’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
TABLE 12-2:
VDD (Volts)
PULL-UP RESISTOR RANGES
Temperature (C)
Min.
Typ.
Max.
Units
-40
73K
105K
186K
25
73K
113K
187K
85
82K
123K
190K
125
86K
132k
190K
-40
15K
21K
33K
25
15K
22K
34K
85
19K
26k
35K
125
23K
29K
35K
-40
63K
81K
96K
25
77K
93K
116K
GP0/GP1
2.0
5.5
GP3
2.0
5.5
DS40001239F-page 62
85
82K
96k
116K
125
86K
100K
119K
-40
16K
20k
22K
25
16K
21K
23K
85
24K
25k
28K
125
26K
27K
29K
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
12.4
Timing Parameter Symbology and Load Conditions – PIC10F200/202/204/206
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency
T Time
Lowercase subscripts (pp) and their meanings:
pp
2
to
mc
MCLR
ck
CLKOUT
osc
Oscillator
cy
Cycle time
t0
T0CKI
drt
Device Reset Timer
wdt
Watchdog Timer
io
I/O port
wdt
Watchdog Timer
Uppercase letters and their meanings:
S
F
Fall
P
Period
H
High
R
Rise
I
Invalid (high-impedance)
V
Valid
L
Low
Z
High-impedance
FIGURE 12-2:
LOAD CONDITIONS – PIC10F200/202/204/206
pin
CL
Legend:
CL = 50 pF for all pins
VSS
2004-2014 Microchip Technology Inc.
DS40001239F-page 63
PIC10F200/202/204/206
TABLE 12-3:
CALIBRATED INTERNAL RC FREQUENCIES – PIC10F200/202/204/206
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
-40C TA +85C (industrial),
-40C TA +125C (extended)
Operating Voltage VDD range is described in
Section 12.1 “DC Characteristics: PIC10F200/202/204/206
(Industrial)”
Param.
Sym.
No.
Freq.
Min. Typ.† Max. Units
Tolerance
F10
Characteristic
FOSC Internal Calibrated
INTOSC Frequency(1,2)
Conditions
1%
3.96
4.00
4.04
MHz VDD=3.5V @ 25C
2%
3.92
4.00
4.08
MHz 2.5V VDD 5.5V
0C TA +85C (industrial)
5%
3.80
4.00
4.20
MHz 2.0V VDD 5.5V
-40C TA +85C (industrial)
-40C TA +125C (extended)
* These parameters are characterized but not tested.
† Data in the Typical (“Typ.”) column is at 5V, 25C unless otherwise stated. These parameters are for
design guidance only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: Under stable VDD conditions.
FIGURE 12-3:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING –
PIC10F200/202/204/206
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout(2)
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pin(1)
Note 1:
2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
Runs on POR only.
DS40001239F-page 64
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
TABLE 12-4:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC10F200/202/204/206
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
-40C TA +125C (extended)
Operating Voltage VDD range is described in Section 12.1 “DC
Characteristics: PIC10F200/202/204/206 (Industrial)”
AC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2*
5*
—
—
—
—
s
s
VDD = 5V, -40°C to +85°C
VDD = 5.0V
31
TWDT
Watchdog Timer Time-out
Period (no prescaler)
10
10
16
16
29
31
ms
ms
VDD = 5.0V (industrial)
VDD = 5.0V (extended)
32
TDRT
Device Reset Timer Period
(standard)
10
10
16
16
29
31
ms
ms
VDD = 5.0V (industrial)
VDD = 5.0V (extended)
34
TIOZ
I/O High-impedance from MCLR
low
—
—
2*
s
*
Note 1:
These parameters are characterized but not tested.
Data in the Typical (“Typ.”) column is at 5V, 25C unless otherwise stated. These parameters are for
design guidance only and are not tested.
FIGURE 12-4:
TIMER0 CLOCK TIMINGS – PIC10F200/202/204/206
T0CKI
40
41
42
TABLE 12-5:
TIMER0 CLOCK REQUIREMENTS – PIC10F200/202/204/206
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
-40C TA +125C (extended)
Operating Voltage VDD range is described in
Section 12.1 “DC Characteristics: PIC10F200/202/204/206 (Industrial)”.
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Min.
Typ.(1) Max. Units
40
Tt0H T0CKI High Pulse No Prescaler
Width
With Prescaler
0.5 TCY + 20*
10*
—
—
ns
41
Tt0L
T0CKI Low Pulse
Width
0.5 TCY + 20*
—
—
ns
42
Tt0P
T0CKI Period
*
Note 1:
No Prescaler
With Prescaler
—
—
Conditions
ns
10*
—
—
ns
T CY + 40
20 or -------------------------N
—
—
ns
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
These parameters are characterized but not tested.
Data in the Typical (“Typ.”) column is at 5V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
2004-2014 Microchip Technology Inc.
DS40001239F-page 65
PIC10F200/202/204/206
TABLE 12-6:
THERMAL CONSIDERATIONS
Standard Operating Conditions (unless otherwise specified)
Param.
No.
Sym.
Characteristic
Typ.
Units
Conditions
Thermal Resistance Junction to
Ambient
60
C/W 6-pin SOT-23 package
80
C/W 8-pin PDIP package
90
C/W 8-pin DFN package
Thermal Resistance Junction to
Case
31.4
TJMAX
Maximum Junction Temperature
150
TH04
PD
Power Dissipation
—
W
PD = PINTERNAL + PI/O
TH05
PINTERNAL Internal Power Dissipation
—
W
PINTERNAL = IDD x VDD(1)
TH06
PI/O
I/O Power Dissipation
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07
PDER
Derated Power
—
W
PDER = PDMAX (TJ - TA)/JA(2)
TH01
TH02
TH03
JA
JC
C/W 6-pin SOT-23 package
24
C/W 8-pin PDIP package
24
C/W 8-pin DFN package
C
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature; TJ = Junction Temperature.
DS40001239F-page 66
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
13.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
FIGURE 13-1:
IDD vs. VDD OVER FOSC
XT Mode
1,400
1,200
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Maximum
1,000
IDD (A)
4 MHz
800
Typical
600
4 MHz
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2004-2014 Microchip Technology Inc.
DS40001239F-page 67
PIC10F200/202/204/206
FIGURE 13-2:
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical
(Sleep Mode all Peripherals Disabled)
0.45
0.40
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0.35
IPD (A)
0.30
0.25
0.20
0.15
0.10
0.05
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-3:
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum
(Sleep Mode all Peripherals Disabled)
18.0
16.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
14.0
Max. 125°C
IPD (A)
12.0
10.0
8.0
6.0
4.0
Max. 85°C
2.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001239F-page 68
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 13-4:
80
COMPARATOR IPD vs. VDD (COMPARATOR ENABLED)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Maximum
IPD (A)
60
Typical
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
VDD (V)
TYPICAL WDT IPD vs. VDD
FIGURE 13-5:
9
8
7
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (A)
6
5
4
3
2
1
0
2.0
2.5
3.0
3.5
VDD (V)
2004-2014 Microchip Technology Inc.
DS40001239F-page 69
PIC10F200/202/204/206
FIGURE 13-6:
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
Maximum
25.0
20.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
IPD (A)
Max. 125°C
15.0
10.0
Max. 85°C
5.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-7:
WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)
50
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
45
40
Max. 85°C
35
Time (ms)
30
Typical. 25°C
25
20
Min. -40°C
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001239F-page 70
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 13-8:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40×C TO 125×C)
0.8
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0.7
Max. 125°C
0.6
VOL (V)
0.5
Max. 85°C
0.4
Typical 25°C
0.3
0.2
Min. -40°C
0.1
0.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 13-9:
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.45
Typical: Statistical Mean @25°C
Typical:
Statistical
Mean @25×C
Maximum:
Mean
(Worst-Case
Temp) + 3
Maximum: Meas(-40×C
+ 3 to 125×C)
(-40°C to 125°C)
0.40
Max. 125°C
0.35
Max. 85°C
VOL (V)
0.30
0.25
Typ. 25°C
0.20
0.15
Min. -40°C
0.10
0.05
0.00
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
2004-2014 Microchip Technology Inc.
DS40001239F-page 71
PIC10F200/202/204/206
FIGURE 13-10:
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.5
3.0
Max. -40°C
Typ. 25°C
2.5
Min. 125°C
VOH (V)
2.0
1.5
1.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
FIGURE 13-11:
(VDD = 5.0V)
VOH vs. IOH OVER TEMPERATURE
(
,
)
5.5
5.0
Max. -40°C
Typ. 25°C
VOH (V)
4.5
Min. 125°C
4.0
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
DS40001239F-page 72
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
FIGURE 13-12:
TTL INPUT THRESHOLD VIN vs. VDD
(TTL Input, -40×C TO 125×C)
1.7
1.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. -40°C
VIN (V)
1.3
Typ. 25°C
1.1
Min. 125°C
0.9
0.7
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-13:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
(ST Input, -40×C TO 125×C)
4.0
VIH Max. 125°C
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
VIH Min. -40°C
VIN (V)
3.0
2.5
2.0
VIL Max. -40°C
1.5
VIL Min. 125°C
1.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2004-2014 Microchip Technology Inc.
DS40001239F-page 73
PIC10F200/202/204/206
FIGURE 13-14:
INTOSC (INTERNAL OSCILLATOR) POWER-UP TIMES vs. VDD
Maximum
(Sleep Mode all Peripherals Disabled)
45
Power-up Time (ms)
40
35
Max. 125°C
30
25
Max. 85°C
20
Typical 25°C
15
Max. -40°C
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001239F-page 74
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
14.0
PACKAGING INFORMATION
14.1
Package Marking Information
6-Lead SOT-23
Example
XXNN
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
0217
Example
PIC10F200
I/P e3 017
1433
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
2004-2014 Microchip Technology Inc.
DS40001239F-page 75
PIC10F200/202/204/206
Package Marking Information (Continued)
8-Lead DFN (2x3x0.9 mm)
Example
BE0
433
17
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS40001239F-page 76
2004-2014 Microchip Technology Inc.
PIC10F200/202/204/206
TABLE 14-1:
8-LEAD 2x3 DFN (MC)
PACKAGE TOP MARKING
Part Number
PIC10F200-I/MC
Marking
TABLE 14-2:
6-LEAD SOT-23 (OT)
PACKAGE TOP MARKING
Part Number
Marking
BA0
PIC10F200-I/OT
00NN
PIC10F200-E/MC
BB0
PIC10F200-E/OT
00NN
PIC10F202-I/MC
BC0
PIC10F202-I/OT
02NN
PIC10F202-E/MC
BD0
PIC10F202-E/OT
02NN
PIC10F204-I/MC
BE0
PIC10F204-I/OT
04NN
PIC10F204-E/MC
BF0
PIC10F204-E/OT
04NN
PIC10F206-I/MC
BG0
PIC10F206-I/OT
06NN
PIC10F206-E/MC
BH0
PIC10F206-E/OT
Note:
2004-2014 Microchip Technology Inc.
NN
represents
traceability code.
06NN
the
alphanumeric
DS40001239F-page 77
PIC10F200/202/204/206
14.2
Package Details
The following sections give the technical details of the packages.
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