PIC12C67X
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter
and EEPROM Data Memory
Devices Included in this Data Sheet:
PDIP, SOIC, Windowed CERDIP
PIC12C671
PIC12C672
PIC12CE673
PIC12CE674
Note:
VDD
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP3/MCLR/VPP
Throughout this data sheet PIC12C67X
refers to the PIC12C671, PIC12C672,
PIC12CE673 and PIC12CE674.
PIC12CE67X refers to PIC12CE673 and
PIC12CE674.
Device
•
•
•
•
•
•
Program
Data
RAM
Data
EEPROM
PIC12C671
1024 x 14
128 x 8
—
PIC12C672
2048 x 14
128 x 8
—
PIC12CE673
1024 x 14
128 x 8
16 x 8
PIC12CE674
2048 x 14
128 x 8
16 x 8
14-bit wide instructions
8-bit wide data path
Interrupt capability
Special function hardware registers
8-level deep hardware stack
Direct, indirect and relative addressing modes for
data and instructions
Peripheral Features:
• Four-channel, 8-bit A/D converter
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• 1,000,000 erase/write cycle EEPROM data
memory
• EEPROM data retention > 40 years
1997-2013 Microchip Technology Inc.
3
4
VDD
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP3/MCLR/VPP
1
2
3
4
PIC12CE673
PIC12CE674
Memory
2
8
7
VSS
GP0/AN0
6
5
GP1/AN1/VREF
GP2/T0CKI/AN2/
INT
8
7
VSS
6
5
GP1/AN1/VREF
GP2/T0CKI/AN2/
INT
PDIP, Windowed CERDIP
High-Performance RISC CPU:
• Only 35 single word instructions to learn
• All instructions are single cycle (400 ns) except for
program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
1
PIC12C671
PIC12C672
•
•
•
•
Pin Diagrams:
GP0/AN0
Special Microcontroller Features:
•
•
•
•
•
•
•
•
•
•
•
•
In-Circuit Serial Programming (ICSP™)
Internal 4 MHz oscillator with programmable calibration
Selectable clockout
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Programmable code protection
Power saving SLEEP mode
Interrupt-on-pin change (GP0, GP1, GP3)
Internal pull-ups on I/O pins (GP0, GP1, GP3)
Internal pull-up on MCLR pin
Selectable oscillator options:
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
- XT:
Standard crystal/resonator
- HS:
High speed crystal/resonator
- LP:
Power saving, low frequency crystal
CMOS Technology:
• Low-power, high-speed CMOS EPROM/EEPROM
technology
• Fully static design
• Wide operating voltage range 2.5V to 5.5V
• Commercial, Industrial and Extended
temperature ranges
• Low power consumption
< 2 mA @ 5V, 4 MHz
15 A typical @ 3V, 32 kHz
< 1 A typical standby current
DS30561C-page 1
PIC12C67X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC12C67X Device Varieties ........................................................................................................................................................ 5
3.0 Architectural Overview .................................................................................................................................................................. 7
4.0 Memory Organization.................................................................................................................................................................. 11
5.0 I/O Port........................................................................................................................................................................................ 25
6.0 EEPROM Peripheral Operation .................................................................................................................................................. 33
7.0 Timer0 Module ............................................................................................................................................................................ 39
8.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................... 45
9.0 Special Features of the CPU....................................................................................................................................................... 53
10.0 Instruction Set Summary............................................................................................................................................................. 69
11.0 Development Support ................................................................................................................................................................. 83
12.0 Electrical Specifications .............................................................................................................................................................. 89
13.0 DC and AC Characteristics ....................................................................................................................................................... 109
14.0 Packaging Information .............................................................................................................................................................. 115
Appendix A:Compatibility ................................................................................................................................................................... 119
Appendix B:Code for Accessing EEPROM Data Memory ................................................................................................................. 119
Index .................................................................................................................................................................................................. 121
On-Line Support................................................................................................................................................................................. 125
Reader Response .............................................................................................................................................................................. 126
PIC12C67X Product Identification System ........................................................................................................................................ 127
To Our Valued Customers
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
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Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
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DS30561C-page 2
1997-2013 Microchip Technology Inc.
PIC12C67X
1.0
GENERAL DESCRIPTION
The PIC12C67X devices are low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converter and
EEPROM data memory (EEPROM on PIC12CE67X
versions only).
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC12C67X microcontrollers have
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches, which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
PIC12C67X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC12C67X devices have 128 bytes of RAM, 16
bytes of EEPROM data memory (PIC12CE67X only), 5
I/O pins and 1 input pin. In addition a timer/counter is
available. Also a 4-channel, high-speed, 8-bit A/D is
provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, (i.e.,
thermostat control, pressure sensing, etc.)
The PIC12C67X devices have special features to
reduce external components, thus reducing cost,
enhancing system reliability and reducing power consumption. The Power-On Reset (POR), Power-up
Timer (PWRT), and Oscillator Start-up Timer (OST)
eliminate the need for external reset circuitry. There are
five oscillator configurations to choose from, including
INTRC precision internal oscillator mode and the
power-saving LP (Low Power) oscillator mode. Powersaving SLEEP mode, Watchdog Timer and code
protection features improve system cost, power and
reliability. The SLEEP (power-down) feature provides a
power-saving mode. The user can wake-up the chip
from SLEEP through several external and internal
interrupts and resets.
1997-2013 Microchip Technology Inc.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock-up.
A UV erasable windowed package version is ideal for
code development, while the cost-effective One-TimeProgrammable (OTP) version is suitable for production
in any volume. The customer can take full advantage of
Microchip’s price leadership in OTP microcontrollers,
while benefiting from the OTP’s flexibility.
1.1
Applications
The PIC12C67X series fits perfectly in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The EPROM technology makes customizing application programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and convenient, while the EEPROM data memory (PIC12CE67X
only) technology allows for the changing of calibration
factors and security codes. The small footprint packages, for through hole or surface mounting, make this
microcontroller series perfect for applications with
space limitations. Low-cost, low-power, high performance, ease of use and I/O flexibility make the
PIC12C67X series very versatile even in areas where
no microcontroller use has been considered before
(i.e., timer functions, replacement of "glue" logic and
PLD’s in larger systems, coprocessor applications).
1.2
Family and Upward Compatibility
The PIC12C67X products are compatible with other
members of the 14-bit PIC16CXXX families.
1.3
Development Support
The PIC12C67X devices are supported by a fullfeatured macro assembler, a software simulator, an incircuit emulator, a low-cost development programmer
and a full-featured programmer. A “C” compiler and
fuzzy logic support tools are also available.
DS30561C-page 3
PIC12C67X
TABLE 1-1:
PIC12C67X & PIC12CE67X FAMILY OF DEVICES
PIC12C671
Clock
Memory
Peripherals
Features
PIC12LC671
PIC12C672
PIC12LC672 PIC12CE673 PIC12LCE673 PIC12CE674 PIC12LCE674
Maximum
Frequency
of Operation
(MHz)
10
10
10
10
10
10
10
10
EPROM
Program
Memory
1024 x 14
1024 x 14
2048 x 14
2048 x 14
1024 x 14
1024 x 14
2048 x 14
2048 x 14
RAM Data
Memory
(bytes)
128
128
128
128
128
128
128
128
EEPROM
—
Data Memory
(bytes)
—
—
—
16
16
16
16
Timer
Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
A/D Converter (8-bit)
Channels
4
4
4
4
4
4
4
4
Wake-up
from SLEEP
on pin
change
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt
Sources
4
4
4
4
4
4
4
4
I/O Pins
5
5
5
5
5
5
5
5
Input Pins
1
1
1
1
1
1
1
1
Internal
Pull-ups
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit
Yes
Serial
Programming
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Number of
Instructions
35
35
35
35
35
35
35
Voltage
3.0V - 5.5V
Range (Volts)
2.5V - 5.5V
3.0V - 5.5V
2.5V - 5.5V
3.0V - 5.5V
2.5V - 5.5V
3.0V - 5.5V
2.5V - 5.5V
Packages
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW
8-pin DIP,
JW
8-pin DIP,
JW
8-pin DIP,
JW
35
8-pin DIP,
JW, SOIC
All PIC12C67X devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12C67X devices use serial programming with data pin GP0 and clock pin GP1.
DS30561C-page 4
1997-2013 Microchip Technology Inc.
PIC12C67X
2.0
PIC12C67X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC12C67X Product Identification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For example, the PIC12C67X device “type” is indicated
in the device number:
1.
C, as in PIC12C671. These devices have
EPROM type memory and operate over the
standard voltage range.
LC, as in PIC12LC671. These devices have
EPROM type memory and operate over an
extended voltage range.
CE, as in PIC12CE674. These devices have
EPROM type memory, EEPROM data memory
and operate over the standard voltage range.
LCE, as in PIC12LCE674. These devices have
EPROM type memory, EEPROM data memory
and operate over an extended voltage range.
2.
3.
4.
2.1
2.3
Quick-Turn-Programming (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices, but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turn Programming
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
UV Erasable Devices
The UV erasable version, offered in windowed package, is optimal for prototype development and pilot programs.
The UV erasable version can be erased and reprogrammed to any of the configuration modes.
Microchip's PICSTART Plus and PRO MATE programmers both support the PIC12C67X. Third party
programmers also are available; refer to the Microchip
Third Party Guide for a list of sources.
Note:
2.2
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1997-2013 Microchip Technology Inc.
DS30561C-page 5
PIC12C67X
NOTES:
DS30561C-page 6
1997-2013 Microchip Technology Inc.
PIC12C67X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12C67X family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC12C67X uses a Harvard architecture, in which
program and data are accessed from separate memories using separate buses. This improves bandwidth
over traditional von Neumann architecture in which program and data are fetched from the same memory
using the same bus. Separating program and data
buses also allow instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are 14bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single instruction
cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all
instructions (35) execute in a single cycle (200 ns @ 20
MHz) except for program branches.
The table below lists program memory (EPROM), data
memory (RAM), and non-volatile memory (EEPROM)
for each PIC12C67X device.
Device
PIC12C671
PIC12C672
PIC12CE673
PIC12CE674
Program
Memory
RAM Data
Memory
EEPROM
Data
Memory
1K x 14
2K x 14
1K x 14
2K x 14
128 x 8
128 x 8
128 x 8
128 x 8
—
—
16x8
16x8
1997-2013 Microchip Technology Inc.
The PIC12C67X can directly or indirectly address its
register files or data memory. All special function registers, including the program counter, are mapped in the
data memory. The PIC12C67X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC12C67X simple yet efficient. In addition, the learning curve is reduced significantly.
PIC12C67X devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
DS30561C-page 7
PIC12C67X
FIGURE 3-1:
PIC12C67X BLOCK DIAGRAM
Program Memory
Data Memory (RAM)
Non-Volatile Memory (EEPROM)
PIC12C671
1K x 14
128 x 8
—
PIC12C672
2K x 14
128 x 8
—
PIC12CE673
1K x 14
128 x 8
16 x 8
PIC12CE674
2K x 14
128 x 8
16 x 8
13
Program
Bus
GP0/AN0
GP1/AN1/VREF
GP2/T0CKI/AN2/INT
GP3/MCLR/VPP
GP4/OSC2/AN3/CLKOUT
GP5/OSC1/CLKIN
RAM
128 bytes
File
Registers
8 Level Stack
(13 bit)
14
RAM Addr (1)
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
3
Power-up
Timer
OSC1/CLKIN
OSC2/CLKOUT
Internal
4 MHz Clock
Timing
Generation
16x8
EEPROM
Data
Memory
PIC12CE673
PIC12CE674
STATUS reg
8
Instruction
Decode &
Control
GPIO
SDA
EPROM
Program
Memory
8
Data Bus
Program Counter
SCL
Device
Oscillator
Start-up Timer
Watchdog
Timer
Power-on
Reset
MUX
ALU
8
W reg
Timer0
MCLR
VDD, VSS
A/D
Note 1: Higher order bits are from the STATUS Register.
DS30561C-page 8
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 3-1:
PIC12C67X PINOUT DESCRIPTION
DIP Pin #
I/O/P
Type
GP0/AN0
7
I/O
TTL/ST Bi-directional I/O port/serial programming data/analog input 0.
Can be software programmed for internal weak pull-up and
interrupt-on-pin change. This buffer is a Schmitt Trigger input
when used in serial programming mode.
GP1/AN1/VREF
6
I/O
TTL/ST Bi-directional I/O port/serial programming clock/analog input 1/
voltage reference. Can be software programmed for internal
weak pull-up and interrupt-on-pin change. This buffer is a
Schmitt Trigger input when used in serial programming mode.
GP2/T0CKI/AN2/INT
5
I/O
GP3/MCLR/VPP
4
I
GP4/OSC2/AN3/CLKOUT
3
I/O
GP5/OSC1/CLKIN
2
I/O
VDD
1
P
—
Positive supply for logic and I/O pins.
VSS
8
P
—
Ground reference for logic and I/O pins.
Name
Buffer
Type
ST
Description
Bi-directional I/O port/analog input 2. Can be configured as
T0CKI or external interrupt.
TTL/ST Input port/master clear (reset) input/programming voltage
input. When configured as MCLR, this pin is an active low
reset to the device. Voltage on MCLR/VPP must not exceed
VDD during normal device operation. Can be software programmed for internal weak pull-up and interrupt-on-pin
change. Weak pull-up always on if configured as MCLR . This
buffer is Schmitt Trigger when in MCLR mode.
TTL
Bi-directional I/O port/oscillator crystal output/analog input 3.
Connections to crystal or resonator in crystal oscillator mode
(HS, XT and LP modes only, GPIO in other modes). In EXTRC
and INTRC modes, the pin output can be configured to CLKOUT, which has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
TTL/ST Bi-directional IO port/oscillator crystal input/external clock
source input (GPIO in INTRC mode only, OSC1 in all other
oscillator modes). Schmitt trigger input for EXTRC oscillator
mode.
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input.
1997-2013 Microchip Technology Inc.
DS30561C-page 9
PIC12C67X
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, and the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute
are pipelined such that fetch takes one instruction
cycle, while decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change
(i.e., GOTO), then two cycles are required to complete
the instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the “Instruction Register" (IR) in cycle
Q1. This instruction is then decoded and executed
during the Q2, Q3, and Q4 cycles. Data memory is
read during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(EXTRC and
INTRC modes)
EXAMPLE 3-1:
1. MOVLW 55h
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF GPIO
3. CALL
SUB_1
4. BSF
GPIO, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1
Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetched
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30561C-page 10
1997-2013 Microchip Technology Inc.
PIC12C67X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
The PIC12C67X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space.
For the PIC12C671 and the PIC12CE673, the first 1K x
14 (0000h-03FFh) is implemented.
For the PIC12C672 and the PIC12CE674, the first 2K
x 14 (0000h-07FFh) is implemented. Accessing a location above the physically implemented address will
cause a wraparound. The reset vector is at 0000h and
the interrupt vector is at 0004h.
FIGURE 4-1:
PIC12C67X PROGRAM
MEMORY MAP AND STACK
Data Memory Organization
The data memory is partitioned into two banks, which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
RP0 (STATUS) = 1 Bank 1
RP0 (STATUS) = 0 Bank 0
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain Special
Function Registers. Some "high use" Special Function
Registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
Also note that F0h through FFh on the PIC12C67X is
mapped into Bank 0 registers 70h-7Fh as common
RAM.
PC
CALL, RETURN
RETFIE, RETLW
4.2
13
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indirectly through the File Select Register FSR
(Section 4.5).
Stack Level 1
Stack Level 8
Reset Vector
0000h
Peripheral Interrupt Vector
0004h
0005h
On-Chip Program
Memory
(PIC12C672 and
PIC12CE674 only)
03FFh
0400h
07FFh
0800h
1FFFh
1997-2013 Microchip Technology Inc.
DS30561C-page 11
PIC12C67X
FIGURE 4-2:
PIC12C67X REGISTER FILE
MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
GPIO
INDF(1)
OPTION
PCL
STATUS
FSR
TRIS
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
OSCCAL
ADRES
ADCON0
ADCON1
General
Purpose
Register
General
Purpose
Register
70h
7Fh
Mapped
in Bank 0
Bank 0
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
A0h
BFh
C0h
EFh
F0h
FFh
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
DS30561C-page 12
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 4-1:
Address
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets(3)
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
03h(1)
STATUS
04h(1)
FSR
05h
GPIO
IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
SCL(5)
SDA(5)
GP5
GP4
GP3
GP2
GP1
GP0
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
11xx xxxx
11uu uuuu
06h
—
Unimplemented
—
—
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
—
Unimplemented
09h
0Ah(1,2)
PCLATH
—
—
—
0Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
0Ch
PIR1
—
ADIF
—
—
—
—
—
—
—
---0 0000
---0 0000
GPIF
0000 000x
0000 000u
—
-0-- ----
-0-- ----
Write Buffer for the upper 5 bits of the Program Counter
0Dh
—
Unimplemented
—
—
0Eh
—
Unimplemented
—
—
0Fh
—
Unimplemented
—
—
10h
—
Unimplemented
—
—
11h
—
Unimplemented
—
—
12h
—
Unimplemented
—
—
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
—
Unimplemented
—
—
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
1Eh
ADRES
1Fh
ADCON0
Unimplemented
A/D Result Register
ADCS1
ADCS0
reserved
CHS1
CHS0
GO/DONE
reserved
ADON
—
—
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
1997-2013 Microchip Technology Inc.
DS30561C-page 13
PIC12C67X
TABLE 4-1:
Address
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets(3)
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
0000 0000
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
83h
STATUS
84h(1)
FSR
85h
TRIS
IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
GPIO Data Direction Register
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
--11 1111
--11 1111
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
—
Unimplemented
89h
8Ah(1,2)
PCLATH
—
8Bh(1)
INTCON
8Ch
PIE1
8Dh
—
8Eh
PCON
8Fh
OSCCAL
—
—
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
—
ADIE
—
—
—
—
—
—
—
---0 0000
---0 0000
GPIF
0000 000x
0000 000u
—
-0-- ----
-0-- ----
Write Buffer for the upper 5 bits of the PC
Unimplemented
—
—
—
—
—
—
—
—
POR
—
---- --0-
---- --u-
CAL3
CAL2
CAL1
CAL0
CALFST
CALSLW
—
—
0111 00--
uuuu uu--
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
---- -000
---- -000
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
DS30561C-page 14
1997-2013 Microchip Technology Inc.
PIC12C67X
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS Register, because these instructions do not
affect the Z, C or DC bits from the STATUS Register.
For other instructions, not affecting any status bits, see
the "Instruction Set Summary."
The STATUS Register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.
Note 1: Bits IRP and RP1 (STATUS) are not
used by the PIC12C67X and should be
maintained clear. Use of these bits as
general purpose R/W bits is NOT recommended, since this may affect upward
compatibility with future products.
2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS Register
as 000u u1uu (where u = unchanged).
REGISTER 4-1:
Reserved Reserved
IRP
RP1
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
Z
DC
C
bit7
bit 7:
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved; always maintain this bit clear.
bit 6-5: RP: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved; always maintain this bit clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:
For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1997-2013 Microchip Technology Inc.
DS30561C-page 15
PIC12C67X
4.2.2.2
OPTION REGISTER
Note:
The OPTION Register is a readable and writable register, which contains various control bits to configure the
TMR0/WDT prescaler, the External INT Interrupt,
TMR0 and the weak pull-ups on GPIO.
REGISTER 4-2:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer by setting bit PSA
(OPTION).
OPTION REGISTER (ADDRESS 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
GPPU: Weak Pull-up Enable
1 = Weak pull-ups disabled
0 = Weak pull-ups enabled (GP0, GP1, GP3)
bit 6:
INTEDG: Interrupt Edge
1 = Interrupt on rising edge of GP2/T0CKI/AN2/INT pin
0 = Interrupt on falling edge of GP2/T0CKI/AN2/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI/AN2/INT pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI/AN2/INT pin
0 = Increment on low-to-high transition on GP2/T0CKI/AN2/INT pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
DS30561C-page 16
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1997-2013 Microchip Technology Inc.
PIC12C67X
4.2.2.3
INTCON REGISTER
Note:
The INTCON Register is a readable and writable register, which contains various enable and flag bits for the
TMR0 Register overflow, GPIO port change and external GP2/INT pin interrupts.
REGISTER 4-3:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: INT External Interrupt Enable bit
1 = Enables the external interrupt on GP2/INT/T0CKI/AN2 pin
0 = Disables the external interrupt on GP2/INT/T0CKI/AN2 pin
bit 3:
GPIE: GPIO Interrupt on Change Enable bit
1 = Enables the GPIO Interrupt on Change
0 = Disables the GPIO Interrupt on Change
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: INT External Interrupt Flag bit
1 = The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software)
0 = The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur
bit 0:
GPIF: GPIO Interrupt on Change Flag bit
1 = GP0, GP1 or GP3 pins changed state (must be cleared in software)
0 = Neither GP0, GP1 nor GP3 pins have changed state
1997-2013 Microchip Technology Inc.
DS30561C-page 17
PIC12C67X
4.2.2.4
PIE1 REGISTER
Note:
This register contains the individual enable bits for the
Peripheral interrupts.
REGISTER 4-4:
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
PIE1 REGISTER (ADDRESS 8Ch)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
ADIE
—
—
—
—
—
—
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
DS30561C-page 18
1997-2013 Microchip Technology Inc.
PIC12C67X
4.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
Peripheral interrupts.
REGISTER 4-5:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR1 REGISTER (ADDRESS 0Ch)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
ADIF
—
—
—
—
—
—
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
1997-2013 Microchip Technology Inc.
DS30561C-page 19
PIC12C67X
4.2.2.6
PCON REGISTER
The Power Control (PCON) Register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), an external MCLR Reset and a WDT Reset.
REGISTER 4-6:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
POR
—
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
Unimplemented: Read as '0'
DS30561C-page 20
1997-2013 Microchip Technology Inc.
PIC12C67X
4.2.2.7
OSCCAL REGISTER
The Oscillator Calibration (OSCCAL) Register is used
to calibrate the internal 4 MHz oscillator. It contains four
bits for fine calibration and two other bits to either
increase or decrease frequency.
REGISTER 4-7:
OSCCAL REGISTER (ADDRESS 8Fh)
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
U-0
U-0
CAL3
CAL2
CAL1
CAL0
CALFST
CALSLW
—
—
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-4: CAL: Fine Calibration
bit 3:
CALFST: Calibration Fast
1 = Increase frequency
0 = No change
bit 2:
CALSLW: Calibration Slow
1 = Decrease frequency
0 = No change
bit 1-0: Unimplemented: Read as ’0’
Note:
If CALFST = 1 and CALSLW = 1, CALFST has precedence.
1997-2013 Microchip Technology Inc.
DS30561C-page 21
PIC12C67X
4.3
PCL and PCLATH
4.3.2
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL Register, which is a readable
and writable register. The high byte (PC) is not
directly readable or writable and comes from PCLATH.
On any reset, the PC is cleared. Figure 4-3 shows the
two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH PCH). The lower example in the figure shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH PCH).
FIGURE 4-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
5
8
PCLATH
Instruction with
PCL as
Destination
The PIC12C67X family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event
of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an interrupt address.
ALU result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH
11
Opcode
PCLATH
4.3.1
COMPUTED GOTO
STACK
4.4
Program Memory Paging
The PIC12C67X ignores both paging bits
PCLATH, which are used to access program
memory when more than one page is available. The
use of PCLATH as general purpose read/write
bits for the PIC12C67X is not recommended since this
may affect upward compatibility with future products.
A Computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing
a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
DS30561C-page 22
1997-2013 Microchip Technology Inc.
PIC12C67X
4.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-1:
The INDF Register is not a physical register. Addressing the INDF Register will cause indirect addressing.
movlw
movwf
clrf
incf
btfss
goto
NEXT
Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF Register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF Register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR Register and the IRP bit
(STATUS), as shown in Figure 4-4. However, IRP is
not used in the PIC12C67X.
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(1)
from opcode
RP1 RP0
6
bank select
location select
Indirect Addressing
0
IRP
(1)
7
bank select
00
01
10
FSR register
0
location select
11
00h
180h
not used
Data
Memory
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For register file map detail see Figure 4-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
1997-2013 Microchip Technology Inc.
DS30561C-page 23
PIC12C67X
NOTES:
DS30561C-page 24
1997-2013 Microchip Technology Inc.
PIC12C67X
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However, read
instructions (i.e., MOVF GPIO,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance), since the I/O control registers are all
set.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP). Bits 6 and 7 (SDA and SCL,
respectively) are used by the EEPROM peripheral on
the PIC12CE673/674. Refer to Section 6.0 and
Appendix B for use of SDA and SCL. Please note that
GP3 is an input only pin. The configuration word can
set several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during port
read. Pins GP0, GP1 and GP3 can be configured with
weak pull-ups and also with interrupt-on-change. The
interrupt on change and weak pull-up functions are not
pin selectable. If pin 4, (GP3), is configured as MCLR,
a weak pull-up is always on. Interrupt-on-change for
this pin is not set and GP3 will read as '0'. Interrupt-onchange is enabled by setting bit GPIE, INTCON.
Note that external oscillator use overrides the GPIO
functions on GP4 and GP5.
5.2
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1 through Figure 5-5. All port pins, except
GP3, which is input only, may be used for both input
and output operations. For input operations, these
ports are non-latching. Any input must be present until
read by an input instruction (i.e., MOVF GPIO,W). The
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
Port pins GP6 (SDA) and GP7 (SCL) are used for the
serial EEPROM interface on the PIC12CE673/674.
These port pins are not available externally on the
package. Users should avoid writing to pins GP6
(SDA) and GP7 (SCL) when not communicating with
the serial EEPROM memory. Please see Section 6.0,
EEPROM Peripheral Operation, for information on
serial EEPROM communication.
Note:
On a Power-on Reset, GP0, GP1, GP2
and GP4 are configured as analog inputs
and read as '0'.
TRIS Register
This register controls the data direction for GPIO. A '1'
from a TRIS Register bit puts the corresponding output
driver in a hi-impedance mode. A '0' puts the contents
of the output data latch on the selected pins, enabling
the output buffer. The exceptions are GP3, which is
input only and its TRIS bit will always read as '1', while
GP6 and GP7 TRIS bits will read as ’0’.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Upon reset, the TRIS Register is all '1's, making all
pins inputs.
TRIS for pins GP4 and GP5 is forced to a ’1’ where
appropriate. Writes to TRIS will have an effect
in EXTRC and INTRC oscillator modes only. When
GP4 is configured as CLKOUT, changes to TRIS
will have no effect.
1997-2013 Microchip Technology Inc.
DS30561C-page 25
PIC12C67X
FIGURE 5-1:
BLOCK DIAGRAM OF GP0/AN0 AND GP1/AN1/VREF PIN
GPPU
Data Bus
WR PORT
D
Q
CK
Q
VDD
VDD
P
P
VDD
I/O Pin
Data Latch
N
WR TRIS
D
Q
CK
Q
VSS
VSS
TRIS Latch
Analog
Input
Mode
TTL
Input
Buffer
RD TRIS
Q
D
EN
RD PORT
GP0/INT(1) and GP1/INT(1)
To A/D Converter
Note 1: Wake-up on pin change interrupts for GP0 and GP1.
DS30561C-page 26
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 5-2:
BLOCK DIAGRAM OF GP2/T0CKI/AN2/INT PIN
Data Bus
WR PORT
D
Q
CK
Q
VDD
VDD
P
I/O Pin
Data Latch
N
WR TRIS
D
Q
CK
Q
VSS
VSS
TRIS Latch
Analog
Input
Mode
Schmitt Trigger
Input Buffer
RD TRIS
Q
D
EN
RD PORT
TMR0 Clock Input
GP2/INT
To A/D Converter
1997-2013 Microchip Technology Inc.
DS30561C-page 27
PIC12C67X
FIGURE 5-3:
BLOCK DIAGRAM OF GP3/MCLR/VPP PIN
VDD
GPPU
P
MCLREN
Input Pin
VSS
MCLR
Schmitt Trigger
Input Buffer
Program Mode
HV Detect
TTL Input
Buffer
Data Bus
Q
D
EN
RD PORT
RD TRIS
VSS
GP3/INT(1)
Note 1: Wake-up on pin change interrupt for GP3.
DS30561C-page 28
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 5-4:
BLOCK DIAGRAM OF GP4/OSC2/AN3/CLKOUT PIN
INTRC or EXTRC w/ CLKOUT
CLKOUT (FOSC/4)
1
0
From OSC1
Data Bus
D
WR PORT
CK
Q
VDD
Q
Oscillator
Circuit
VDD
P
I/O Pin
Data Latch
N
VSS
WR TRIS
D
Q
CK
Q
INTRC/
EXTRC
VSS
INTRC or EXTRC
w/o CLKOUT
TRIS Latch
Analog
Input
Mode
TTL
Input Buffer
RD TRIS
Q
D
EN
RD PORT
To A/D Converter
1997-2013 Microchip Technology Inc.
DS30561C-page 29
PIC12C67X
FIGURE 5-5:
BLOCK DIAGRAM OF GP5/OSC1/CLKIN PIN
To OSC2
Oscillator
Circuit
Data Bus
WR PORT
D
Q
EN
Q
VDD
VDD
P
Data Latch
I/O Pin
N
WR TRIS
D
Q
EN
Q
INTRC
VSS
VSS
TRIS Latch
INTRC
TTL
Input Buffer
RD TRIS
Q
D
EN
RD PORT
DS30561C-page 30
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 5-1:
Address
85h
SUMMARY OF PORT REGISTERS
Name
TRIS
Bit 7
Bit 6
—
—
INTEDG
81h
OPTION
GPPU
03h
STATUS
IRP
(1)
05h
GPIO
SCL(2)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO Data Direction Register
Value on
Power-on
Reset
Value on
all other
Resets
--11 1111
--11 1111
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
(1)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
SDA(2)
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
RP1
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,
q = see tables in Section 9.4 for possible values.
Note 1: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
2: The SCL and SDA bits are unimplemented on the PIC12C671 and PIC12C672.
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of GPIO will cause all eight bits of GPIO to be read into
the CPU. Then the BSF operation takes place on bit5
and GPIO is written to the output latches. If another bit
of GPIO is used as a bi-directional I/O pin (i.e., bit0) and
it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU and
rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the
input mode, no problem occurs. However, if bit0 is
switched to an output, the content of the data latch may
now be unknown.
Reading the port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port
pins is read, the desired operation is done to this value,
and this value is then written to the port latch.
1997-2013 Microchip Technology Inc.
Example 5-1 shows the effect of two sequential readmodify-write instructions on an I/O port.
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
; GPIO Inputs
; GPIO Outputs
;
;
GPIO latch GPIO pins
;
---------- ---------BCF
GPIO, 5
;--01 -ppp
--11 pppp
BCF
GPIO, 4
;--10 -ppp
--11 pppp
MOVLW 007h
;
TRIS GPIO
;--10 -ppp
--10 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
DS30561C-page 31
PIC12C67X
NOTES:
DS30561C-page 32
1997-2013 Microchip Technology Inc.
PIC12C67X
6.0
EEPROM PERIPHERAL
OPERATION
The PIC12CE673 and PIC12CE674 each have 16
bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles
and a data retention of greater than 40 years. The
EEPROM data memory supports a bi-directional 2-wire
bus and data transmission protocol. These two-wires
are serial data (SDA) and serial clock (SCL), that are
mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h). Unlike the GP0-GP5 that are connected to the I/O pins, SDA and SCL are only
connected to the internal EEPROM peripheral. For
most applications, all that is required is calls to the
following functions:
; Byte_Write: Byte write routine
;
Inputs: EEPROM Address
EEADDR
;
EEPROM Data
EEDATA
;
Outputs:
Return 01 in W if OK, else
return 00 in W
;
; Read_Current: Read EEPROM at address
currently held by EE device.
;
Inputs: NONE
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK, else
return 00 in W
;
; Read_Random: Read EEPROM byte at supplied
address
;
Inputs: EEPROM Address
EEADDR
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK,
else return 00 in W
The code for these functions is available on our web
site (www.microchip.com). The code will be accessed
by either including the source code FL67XINC.ASM or
by linking FLASH67X.ASM. FLASH67X.INC provides
external definition to the calling program.
6.0.1
SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the device.
6.1
Bus Characteristics
The following bus protocol is to be used with the
EEPROM data memory. In this section, the term “processor” is used to denote the portion of the PIC12C67X that
interfaces to the EEPROM via software.
• Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 6-3).
6.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
6.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
6.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
6.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the available data
EEPROM space.
For normal data transfer, SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
6.0.2
SERIAL CLOCK
This SCL signal is used to synchronize the data transfer from and to the EEPROM.
1997-2013 Microchip Technology Inc.
DS30561C-page 33
PIC12C67X
6.1.5
ACKNOWLEDGE
The EEPROM, when addressed, will generate an
acknowledge after the reception of each byte. The processor must generate an extra clock pulse which is
associated with this acknowledge bit.
Note:
Acknowledge bits are not generated if an
internal programming cycle is in progress.
FIGURE 6-1:
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-4).
BLOCK DIAGRAM OF GPIO6 (SDA LINE)
VDD
Reset
To EEPROM SDA
Pad
D
Data Bus
Write
GPIO
EN
CK
P
Q
Output Latch
Q
D
Schmitt Trigger
EN
CK
Input Latch
ltchpin
Read
GPIO
FIGURE 6-2:
BLOCK DIAGRAM OF GPIO7 (SCL LINE)
VDD
D
Data Bus
Write
GPIO
CK
P
EN
Q
Output Latch
Q
N
D
Schmitt Trigger
EN
CK
Read
GPIO
DS30561C-page 34
To EEPROM SCL
Pad
ltchpin
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 6-3:
SCL
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(C)
(D)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
(C)
(A)
SDA
FIGURE 6-4:
STOP
CONDITION
DATA
ALLOWED
TO CHANGE
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
SDA
3
4
5
6
7
8
9
1
Device Addressing
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed. The EEPROM address
consists of a 4-bit device code (1010) followed by three
don't care bits.
The last bit of the control byte determines the operation
to be performed. When set to a one, a read operation
is selected, and when set to a zero, a write operation is
selected (Figure 6-5). The bus is monitored for its corresponding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
1997-2013 Microchip Technology Inc.
3
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
2
FIGURE 6-5:
CONTROL BYTE FORMAT
Read/Write Bit
Device Select
Bits
S
1
0
1
Don’t Care
Bits
0
X
X
X
R/W ACK
EEPROM Address
Start Condition
Acknowledge Condition
DS30561C-page 35
PIC12C67X
6.3
Write Operations
6.4
6.3.1
BYTE WRITE
Since the EEPROM will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write command has been issued from the processor, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the processor sending a start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the processor can then
proceed with the next read or write command. (See
Figure 6-6 for flow diagram.)
Following the start signal from the processor, the
device code (4 bits), the don't care bits (3 bits), and the
R/W bit (which is a logic low) are placed onto the bus
by the processor. This indicates to the addressed
EEPROM that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the processor is the word address and will be written
into the address pointer. Only the lower four address
bits are used by the device, and the upper four bits are
don’t cares. If the address byte is acknowledged, the
processor will then transmit the data word to be written
into the addressed memory location. The memory
acknowledges again and the processor generates a
stop condition. This initiates the internal write cycle,
and during this time will not generate acknowledge signals. After a byte write command, the internal address
counter will not be incremented and will point to the
same address location that was just written. If a stop bit
sequence is transmitted to the device at any point in the
write command sequence before the entire sequence
is complete, then the command will abort and no data
will be written. If more than 8 data bits are transmitted
before the stop bit sequence is sent, then the device will
clear the previously loaded byte and begin loading the
data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full
eight data bits have been transmitted, then the write
command will abort and no data will be written. The
EEPROM memory employs a VCC threshold detector
circuit, which disables the internal erase/write logic if
the VCC is below minimum VDD. Byte write operations
must be preceded and immediately followed by a bus
not busy bus cycle where both SDA and SCL are held
high. (See Figure 6-7 for Byte Write operation.)
Acknowledge Polling
FIGURE 6-6:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did EEPROM
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
FIGURE 6-7:
BYTE WRITE
S
T
A
R
T
SDA LINE
ACTIVITY
S
CONTROL
BYTE
1
0
1
0
X
X
WORD
ADDRESS
X
X
0
A
C
K
X
X
S
T
O
P
DATA
P
X
A
C
K
A
C
K
X = Don’t Care Bit
DS30561C-page 36
1997-2013 Microchip Technology Inc.
PIC12C67X
6.5
Read Operations
address is sent, the processor generates a start condition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again, but with the R/W bit set to a one. The
EEPROM will then issue an acknowledge and transmits the 8-bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-9). After this command, the internal address
counter will point to the address location following the
one that was just read.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations; current address read, random
read and sequential read.
6.5.1
CURRENT ADDRESS READ
The EEPROM contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the EEPROM address with the R/W bit set to
one, the EEPROM issues an acknowledge and transmits the 8-bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-8).
6.5.2
6.5.3
Sequential reads are initiated in the same way as a random read, except that after the device transmits the first
data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-10).
RANDOM READ
To provide sequential reads, the EEPROM contains an
internal address pointer, which is incremented by one
at the completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
EEPROM as part of a write operation. After the word
FIGURE 6-8:
SEQUENTIAL READ
CURRENT ADDRESS READ
S
T
A
R
T
SDA LINE
ACTIVITY
S
T
O
P
CONTROL
BYTE
S 1 0 1 0 X XX 1
P
A
C
K
N
O
DATA
A
C
K
X = Don’t Care Bit
FIGURE 6-9:
RANDOM READ
S
T
A
R
T
CONTROL
BYTE
X X X X
S 1 0 1 0 X X X 0
SDA LINE
ACTIVITY
S
T
A
R
T
WORD
ADDRESS (n)
P
S 1 0 1 0 X X X 1
A
C
K
A
C
K
S
T
O
P
CONTROL
BYTE
A
C
K
DATA (n)
N
O
A
C
K
X = Don’t Care Bit
FIGURE 6-10: SEQUENTIAL READ
CONTROL
BYTE
SDA LINE
ACTIVITY
DATA n
DATA n + 1
DATA n + 2
S
T
O
P
DATA n + X
P
A
C
K
1997-2013 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
N
O
A
C
K
DS30561C-page 37
PIC12C67X
NOTES:
DS30561C-page 38
1997-2013 Microchip Technology Inc.
PIC12C67X
7.0
TIMER0 MODULE
(OPTION). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are discussed in detail in Section 7.2.
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit
PSA (OPTION). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer mode is selected by clearing bit T0CS
(OPTION). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the bit T0SE
FIGURE 7-1:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON). The interrupt can be masked by
clearing bit T0IE (INTCON). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP. See
Figure 7-4 for Timer0 interrupt timing.
TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
8
1
Sync with
Internal
clocks
1
Programmable
Prescaler
GP2/TOCKI/
AN2/INT
0
TMR0
(2 TCY delay)
TOSE
3
Set interrupt
flag bit T0IF
on overflow
PSA
PS
TOCS
Note 1: TOCS, TOSE, PSA, PS (OPTION).
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
FIGURE 7-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
T0
T0+1
Instruction
Executed
1997-2013 Microchip Technology Inc.
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0
Read TMR0
reads NT0
NT0+1
NT0+2
T0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
DS30561C-page 39
PIC12C67X
FIGURE 7-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
Instruction
Fetch
T0
TMR0
T0+1
Instruction
Execute
Write TMR0
executed
FIGURE 7-4:
NT0+1
NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
T0IF bit
(INTCON)
FFh
00h
01h
02h
1
1
Interrupt Latency(2)
GIE bit
(INTCON)
INSTRUCTION
FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
Note 1:
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Interrupt flag bit T0IF is sampled here (every Q1).
2:
Interrupt latency = 3TCY where TCY = instruction cycle time.
3:
CLKOUT is available only in the INTRC and EXTRC oscillator modes.
DS30561C-page 40
1997-2013 Microchip Technology Inc.
PIC12C67X
7.2
Using Timer0 with an External Clock
caler, so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the
desired device.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
used as the clock source. The synchronization of
T0CKI with the internal phase clocks is accomplished
by sampling the prescaler output on the Q2 and Q4
cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least
2TOSC (and a small RC delay of 20 ns) and low for at
least 2TOSC (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
7.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the delay
from the external clock edge to the timer incrementing.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
FIGURE 7-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Small pulse
misses sampling
External Clock Input or
Prescaler output(2)
(1)
External Clock/Prescaler
Output after sampling
(3)
Increment Timer0 (Q4)
Timer0
Note 1:
T0
T0 + 1
T0 + 2
Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4TOSC max.
2:
External clock if no prescaler selected; prescaler output otherwise.
3:
The arrows indicate the points in time where sampling occurs.
1997-2013 Microchip Technology Inc.
DS30561C-page 41
PIC12C67X
7.3
The PSA and PS bits (OPTION) determine
the prescaler assignment and prescale ratio.
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
FIGURE 7-6:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (i.e., CLRF 1, MOVWF 1,
BSF 1,x...., etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= FOSC/4)
0
GP2/T0CKI/
AN2/INT
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS are (OPTION).
DS30561C-page 42
1997-2013 Microchip Technology Inc.
PIC12C67X
7.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2.
The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program
execution).
Note:
To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
EXAMPLE 7-1:
BCF
CLRF
BSF
CLRWDT
MOVLW
MOVWF
BCF
EXAMPLE 7-2:
BSF
MOVLW
MOVWF
BCF
;Clear WDT and
;prescaler
STATUS, RP0 ;Bank 1
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
OPTION_REG ;clock source
STATUS, RP0 ;Bank 0
CHANGING PRESCALER
(TIMER0WDT)
STATUS, RP0
TMR0
STATUS, RP0
b'xxxx1xxx'
OPTION_REG
STATUS, RP0
TABLE 7-1:
CLRWDT
CHANGING PRESCALER
(WDTTIMER0)
;Bank 0
;Clear TMR0 & Prescaler
;Bank 1
;Clears WDT
;Select new prescale
;value & WDT
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Address Name
01h
TMR0
0Bh/8Bh
INTCON
81h
OPTION
85h
TRIS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
PEIE
GPPU INTEDG
—
—
T0IE
INTE
GPIE
T0IF
INTF
GPIF
Value on
POR
Value on
all other
Resets
xxxx xxxx
uuuu uuuu
0000 000x
0000 000u
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
TRIS5
TRIS4
TRIS3
TRIS2
TRIS1
TRIS0
--11 1111
--11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1997-2013 Microchip Technology Inc.
DS30561C-page 43
PIC12C67X
NOTES:
DS30561C-page 44
1997-2013 Microchip Technology Inc.
PIC12C67X
8.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-To-Digital (A/D) converter module has four
analog inputs.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s positive supply voltage (VDD)
or the voltage level on the GP1/AN1/VREF pin. The A/D
converter has a unique feature of being able to operate
while the device is in SLEEP mode.
The ADCON0 Register, shown in Figure 8-1, controls
the operation of the A/D module. The ADCON1 Register, shown in Figure 8-2, configures the functions of the
port pins. The port pins can be configured as analog
inputs (GP1 can also be a voltage reference) or as digital I/O.
Note 1: If the port pins are configured as analog
inputs (reset condition), reading the port
(MOVF GPIO,W) results in reading '0's.
2: Changing ADCON1 Register can cause
the GPIF and INTF flags to be set in the
INTCON Register.
These interrupts
should be disabled prior to modifying
ADCON1.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
REGISTER 8-1:
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0
R/W-0
ADCS1 ADCS0 reserved
bit7
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
GO/DONE reserved
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an RC oscillation)
bit 5:
Reserved
bit 4-3: CHS: Analog Channel Select bits
00 = channel 0, (GP0/AN0)
01 = channel 1, (GP1/AN1)
10 = channel 2, (GP2/AN2)
11 = channel 3, (GP4/AN3)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion
is complete)
bit 1:
Reserved
bit 0:
ADON: A/D on bit
1 = A/D converter module is operating
0 = A/D converter module is shut off and consumes no operating current
1997-2013 Microchip Technology Inc.
DS30561C-page 45
PIC12C67X
REGISTER 8-2:
U-0
—
bit7
ADCON1 REGISTER (ADDRESS 9Fh)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1-0: PCFG: A/D Port Configuration Control bits
PCFG
GP4
GP2
GP1
GP0
VREF
000(1)
001
010
011
100
101
110
111
A
A
A
A
VDD
A
D
D
D
D
D
D
A
A
A
D
D
D
D
VREF
A
VREF
A
VREF
D
D
A
A
A
A
A
A
D
GP1
VDD
GP1
VDD
GP1
VDD
VDD
A = Analog input
D = Digital I/O
Note 1: Value on reset.
2: Any instruction that reads a pin configured as an analog input will read a '0'.
DS30561C-page 46
1997-2013 Microchip Technology Inc.
PIC12C67X
The ADRES Register contains the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0) is cleared, and A/D interrupt flag bit
ADIF (PIE1) is set. The block diagrams of the A/D
module are shown in Figure 8-1.
2.
3.
4.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine sample time, see Section 8.1. After
this acquisition time has elapsed, the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
1.
5.
OR
6.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1 and TRIS)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 8-1:
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
7.
• Waiting for the A/D interrupt
Read A/D Result Register (ADRES), clear bit
ADIF if required.
For the next conversion, go to step 1, step 2 or
step 3 as required. The A/D conversion time per
bit is defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
A/D BLOCK DIAGRAM
CHS
11
GP4/AN3
VIN
10
(Input voltage)
GP2/AN2
01
A/D
Converter
GP1/AN1/VREF
00
GP0/AN0
VDD
VREF
(Reference
voltage)
PCFG
1997-2013 Microchip Technology Inc.
DS30561C-page 47
PIC12C67X
8.1
A/D Sampling Requirements
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 8-2. The maximum recommended impedance for analog sources is 10 k. After the analog
input channel is selected (changed), this acquisition
must be done before the conversion can be started.
To calculate the minimum acquisition time, Equation 8-1
may be used. This equation assumes that 1/2 LSb error
is used (512 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
EQUATION 8-1:
A/D MINIMUM CHARGING
TIME
2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3: The maximum recommended impedance
for analog sources is 10 k. This is
required to meet the pin leakage specification.
4: After a conversion has completed, a
2.0 TAD delay must complete before
acquisition can begin again. During this
time, the holding capacitor is not connected to the selected A/D input channel.
EXAMPLE 8-1:
CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
TACQ = Internal Amplifier Settling Time +
Holding Capacitor Charging Time +
VHOLD = (VREF - (VREF/512)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
Temperature Coefficient
or
TACQ = 5 s + Tc + [(Temp - 25C)(0.05 s/C)]
Tc = -(51.2 pF)(1 k + RSS + RS) ln(1/511)
Example 8-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
TC =
-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 k + 7 k + 10 k) ln(0.0020)
-51.2 pF (18 k) ln(0.0020)
Rs = 10 k
-0.921 s (-6.2146)
1/2 LSb error
5.724 s
VDD = 5V Rss = 7 k
TACQ = 5 s + 5.724 s + [(50C - 25C)(0.05 s/C)]
Temp (system max.) = 50C
10.724 s + 1.25 s
VHOLD = 0 @ t = 0
11.974 s
FIGURE 8-2:
ANALOG INPUT MODEL
VDD
Rs
VA
Sampling
Switch
VT = 0.6V
RAx
CPIN
5 pF
VT = 0.6V
RIC 1k
SS
Rss
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
DS30561C-page 48
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( k )
1997-2013 Microchip Technology Inc.
PIC12C67X
8.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selected. The four possible options for TAD are:
•
•
•
•
2TOSC
8TOSC
32TOSC
Internal ADC RC oscillator
Configuring Analog Port Pins
The ADCON1 and TRIS Registers control the operation of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS bits and the TRIS bits.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s. If the minimum TAD time of 1.6 s can not be
obtained, TAD should be 8 s for preferred operation.
Table 8-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 8-1:
8.3
Note 1: When reading the port register, all pins
configured as analog input channel will
read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN
pins) may cause the input buffer to consume current that is out of the devices
specification.
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency
AD Clock Source (TAD)
Operation
ADCS
4 MHz
1.25 MHz
333.33 kHz
1.6 s
6 s
6.4 s
24 s(3)
2TOSC
00
8TOSC
01
500
2.0 s
32TOSC
10
8.0 s
25.6 s(3)
96 s(3)
Internal ADC RC Oscillator(5)
11
2 - 6 s(1,4)
2 - 6 s(1,4)
2 - 6 s(1)
Note 1:
2:
3:
4:
5:
ns(2)
The RC source has a typical TAD time of 4 s.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification.
For extended voltage devices (LC), please refer to Electrical Specifications section.
1997-2013 Microchip Technology Inc.
DS30561C-page 49
PIC12C67X
8.4
A/D Conversions
Example 8-2 shows how to perform an A/D conversion.
The GPIO pins are configured as analog inputs. The
analog reference (VREF) is the device VDD. The A/D
interrupt is enabled and the A/D conversion clock is
FRC. The conversion is performed on the GP0 channel.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
EXAMPLE 8-2:
BSF
CLRF
BSF
BCF
MOVLW
MOVWF
BCF
BSF
BSF
;
;
;
;
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed
conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started on
the selected channel.
DOING AN A/D CONVERSION
STATUS,
ADCON1
PIE1,
STATUS,
0xC1
ADCON0
PIR1,
INTCON,
INTCON,
RP0
ADIE
RP0
ADIF
PEIE
GIE
;
;
;
;
;
;
;
;
;
Select Page 1
Configure A/D inputs
Enable A/D interrupts
Select Page 0
RC Clock, A/D is on, Channel 0 is selected
Clear A/D interrupt flag bit
Enable peripheral interrupts
Enable all interrupts
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
:
ADCON0, GO
DS30561C-page 50
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
; is cleared upon completion of the A/D Conversion.
1997-2013 Microchip Technology Inc.
PIC12C67X
A/D Accuracy/Error
The overall accuracy of the A/D is less than 1 LSb for
VDD = 5V 10% and the analog VREF = VDD. This overall accuracy includes offset error, full scale error, and
integral error. The A/D converter is monotonic over the
full VDD range. The resolution and accuracy may be
less when either the analog reference (VDD) is less than
5.0V or when the analog reference (VREF) is less than
VDD.
The maximum pin leakage current is specified in the
Device Data Sheet electrical specification, parameter
#D060.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be
8 s for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock transitions. This reduces, to a large extent,
the effects of digital switching noise. This is not possible
with the RC derived clock. The loss of accuracy due to
digital switching noise can be significant if many I/O
pins are active.
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conversion is out of specification.
Note:
For the PIC12C67X, care must be taken
when using the GP4 pin in A/D conversions due to its proximity to the OSC1 pin.
An external RC filter is sometimes added for antialiasing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 k recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
8.9
Transfer Function
The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input
voltage (VAIN) is 1 LSb (or Analog VREF / 256)
(Figure 8-3).
FIGURE 8-3:
A/D TRANSFER FUNCTION
FFh
FEh
04h
03h
02h
01h
00h
256 LSb
(full scale)
8.6
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS = 11). To perform an A/D
conversion in SLEEP, the GO/DONE bit
must be set, followed by the SLEEP
instruction.
Connection Considerations
255 LSb
Note:
8.8
4 LSb
Turning off the A/D places the A/D module in its lowest
current consumption state.
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the ADRES
register is not modified for a Reset. The ADRES register will contain unknown data after a Power-on Reset.
3 LSb
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Effects of a Reset
2 LSb
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES Register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
8.7
0.5 LSb
1 LSb
A/D Operation During Sleep
Digital code output
8.5
Analog input voltage
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
1997-2013 Microchip Technology Inc.
DS30561C-page 51
PIC12C67X
FIGURE 8-4:
FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
A/D Clock
= RC?
Start of A/D
Conversion Delayed
1 Instruction Cycle
SLEEP Yes
Instruction?
Finish Conversion
GO = 0
ADIF = 1
No
No
Yes
Device in
SLEEP?
Abort Conversion
GO = 0
ADIF = 0
Wake-up Yes
From Sleep?
Finish Conversion
GO = 0
ADIF = 1
Wait 2 TAD
No
No
SLEEP
Power-down A/D
Finish Conversion
GO = 0
ADIF = 1
Stay in Sleep
Power-down A/D
Wait 2 TAD
Wait 2 TAD
TABLE 8-2:
SUMMARY OF A/D REGISTERS
Address Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000u
—
ADIF
—
—
—
—
—
—
-0-- ----
-0-- ----
—
ADIE
—
—
—
—
—
—
-0-- ----
-0-- ----
xxxx xxxx
uuuu uuuu
Bit 7
0Bh/8Bh
INTCON(1)
0Ch
PIR1
8Ch
PIE1
1Eh
ADRES
A/D Result Register
1Fh
ADCON0
ADCS1 ADCS0 reserved CHS1
9Fh
ADCON1
05h
85h
GPIO
TRIS
CHS0
GO/DONE
reserved
ADON
0000 0000
0000 0000
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
---- -000
SCL(2)
SDA(2)
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
TRIS0
--11 1111
--11 1111
—
—
TRIS5
TRIS4 TRIS3
TRIS2
TRIS1
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers can be addressed from either bank.
2: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
DS30561C-page 52
1997-2013 Microchip Technology Inc.
PIC12C67X
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC12C67X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection. These are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
CP1
CP0
CP1
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The INTRC/EXTRC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
9.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The PIC12C67X has a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
REGISTER 9-1:
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h3FFFh), which can be accessed only during
programming.
CONFIGURATION WORD
CP0
CP1
CP0 MCLRE
CP1
bit13
CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0
bit0
Register:
Address
CONFIG
2007h
bit 13-8, CP: Code Protection bit pairs(1)
6-5: 11 = Code protection off
10 = Locations 400h through 7FEh code protected (do not use for PIC12C671 and PIC12CE673)
01 = Locations 200h through 7FEh code protected
00 = All memory is code protected
bit 7:
MCLRE: Master Clear Reset Enable bit
1 = Master Clear Enabled
0 = Master Clear Disabled
bit 4:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0:
FOSC: Oscillator Selection bits
111 = EXTRC, Clockout on OSC2
110 = EXTRC, OSC2 is I/O
101 = INTRC, Clockout on OSC2
100 = INTRC, OSC2 is I/O
011 = Invalid Selection
010 = HS Oscillator
001 = XT Oscillator
000 = LP Oscillator
Note 1: All of the CP pairs have to be given the same value to enable the code protection scheme listed.
1997-2013 Microchip Technology Inc.
DS30561C-page 53
PIC12C67X
9.2
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
TABLE 9-1:
The PIC12C67X can be operated in seven different
oscillator modes. The user can program three
configuration bits (FOSC) to select one of these
seven modes:
•
•
•
•
•
LP:
HS:
XT:
INTRC*:
EXTRC*:
Low Power Crystal
High Speed Crystal/Resonator
Crystal/Resonator
Internal 4 MHz Oscillator
External Resistor/Capacitor
*Can be configured to support CLKOUT
9.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, HS or LP modes, a crystal or ceramic resonator
is connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 9-1). The
PIC12C67X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, HS or LP modes, the
device can have an external clock source drive the
GP5/OSC1/CLKIN pin (Figure 9-2).
FIGURE 9-1:
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(XT, HS OR LP OSC
CONFIGURATION)
C1(1)
OSC1
PIC12C67X
SLEEP
XTAL
RS(2)
RF(3)
OSC2
To internal
logic
C2(1)
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode selected
(approx. value = 10 M).
FIGURE 9-2:
Osc
Type
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12C67X
Resonator
Freq
Cap. Range
C1
Cap. Range
C2
XT
455 kHz
22-100 pF
22-100 pF
2.0 MHz
15-68 pF
15-68 pF
4.0 MHz
15-68 pF
15-68 pF
HS
4.0 MHz
15-68 pF
15-68 pF
8.0 MHz
10-68 pF
10-68 pF
10.0 MHz
10-22 pF
10-22 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
TABLE 9-2:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC12C67X
Osc
Type
Resonator
Freq
Cap. Range
C1
Cap. Range
C2
LP
32 kHz(1)
100 kHz
200 kHz
100 kHz
200 kHz
455 kHz
1 MHz
2 MHz
4 MHz
4 MHz
8 MHz
10 MHz
15 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-47 pF
15-30 pF
15-30 pF
15-30 pF
15 pF
30-47 pF
15-82 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15-30 pF
15-47 pF
15-30 pF
15-30 pF
15-30 pF
XT
HS
Note 1: For VDD > 4.5V, C1 = C2 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in HS mode, as well as XT mode, to
avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer
for appropriate values of external components.
EXTERNAL CLOCK INPUT
OPERATION (XT, HS OR LP
OSC CONFIGURATION)
OSC1
Clock from
ext. system
PIC12C67X
Open
DS30561C-page 54
OSC2
1997-2013 Microchip Technology Inc.
PIC12C67X
9.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a pre-packaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Pre-packaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used; one with parallel
resonance or one with series resonance.
Figure 9-3 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 k resistor
provides the negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 9-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC12C67X
74AS04
CLKIN
10k
XTAL
9.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Figure 9-5 shows how the R/C combination is
connected to the PIC12C67X. For REXT values below
2.2 k, the oscillator operation may become unstable
or stop completely. For very high REXT values
(i.e., 1 M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 3 k and 100 k.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
The variation is larger for larger R (since leakage
current variation will affect RC frequency more for
large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
FIGURE 9-5:
10k
EXTERNAL RC OSCILLATOR
MODE
VDD
20 pF
20 pF
REXT
Figure 9-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator
circuit. The 330 resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 9-4:
Internal
clock
OSC1
N
CEXT
PIC12C67X
VSS
FOSC/4
OSC2/CLKOUT
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330
To Other
Devices
330
74AS04
74AS04
74AS04
PIC12C67X
CLKIN
0.1 F
XTAL
1997-2013 Microchip Technology Inc.
DS30561C-page 55
PIC12C67X
9.2.5
INTERNAL 4 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C. See
Section 13.0 for information on variation over voltage
and temperature.
In addition, a calibration instruction is programmed into
the last address of the program memory which contains
the calibration value for the internal RC oscillator. This
value is programmed as a RETLW XX instruction where
XX is the calibration value. In order to retrieve the calibration value, issue a CALL YY instruction where YY is
the last location in program memory (03FFh for the
PIC12C671 and the PIC12CE673, 07FFh for the
PIC12C672 and the PIC12CE674). Control will be
returned to the user’s program with the calibration
value loaded into the W register. The program should
then perform a MOVWF OSCCAL instruction to load the
value into the internal RC oscillator trim register.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. Bits , CAL are
used for fine calibration, while bit 3, CALFST, and bit 2,
CALSLW, are used for more coarse adjustment. Adjusting CAL from 0000 to 1111 yields a higher clock
speed. Set CALFST = 1 for greater increase in frequency or set CALSLW = 1 for greater decrease in frequency. Note that bits 1 and 0 of OSCCAL are
unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices.
Note:
9.2.6
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
9.3
Reset
The PIC12C67X differentiates between various kinds
of reset:
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), MCLR Reset, WDT
Reset, and MCLR Reset during SLEEP. They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different reset situations,
as indicated in Table 9-5. These bits are used in
software to determine the nature of the reset. See
Table 9-6 for a full description of reset states of all
registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 9-6.
The PIC12C67X has a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
When MCLR is asserted, the state of the OSC1/CLKIN
and CLKOUT/OSC2 pins are as follows:
TABLE 9-3:
Oscillator Mode
DS30561C-page 56
OSC1/CLKIN Pin OSC2/CLKout Pin
EXTRC, CLKOUT
on OSC2
OSC1 pin is
tristated and
driven by external
circuit
OSC2 pin is driven
low
EXTRC, OSC2 is
I/O
OSC1 pin is
tristated and
driven by external
circuit
OSC2 pin is
tristate input
INTRC, CLKOUT
on OSC2
OSC1 pin is
tristate input
OSC2 pin is driven
low
INTRC, OSC2 is
I/O
OSC1 pin is
tristate input
OSC2 pin is
tristate input
CLKOUT
The PIC12C67X can be configured to provide a clock
out signal (CLKOUT) on pin 3 when the configuration
word address (2007h) is programmed with FOSC2,
FOSC1, and FOSC0, equal to 101 for INTRC or 111 for
EXTRC. The oscillator frequency, divided by 4, can be
used for test purposes or to synchronize other logic.
CLKIN/CLKOUT PIN STATES
WHEN MCLR ASSERTED
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 9-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Weak
Pull-up
GP3/MCLR/VPP Pin
MCLRE
INTERNAL MCLR
WDT SLEEP
Module
WDT Time-out
VDD rise
detect Power-on Reset
VDD
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 9-4 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1997-2013 Microchip Technology Inc.
DS30561C-page 57
PIC12C67X
9.4
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
9.4.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
9.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See
Table 11-4.
TABLE 9-4:
9.4.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
TIME-OUT SEQUENCE
On power-up, the Time-out Sequence is as follows:
first, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary, based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 9-7, Figure 9-8, and Figure 9-9 depict time-out
sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-9). This is useful for testing purposes or to
synchronize more than one PIC12C67X device operating in parallel.
9.4.5
POWER CONTROL (PCON)/STATUS
REGISTER
The Power Control/Status Register, PCON (address
8Eh), has one bit. See Register 4-6 for register.
Bit1 is POR (Power-on Reset). It is cleared on a Poweron Reset and is unaffected otherwise. The user sets
this bit following a Power-on Reset. On subsequent
resets, if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
XT, HS, LP
INTRC, EXTRC
TABLE 9-5:
Power-up
PWRTE = 0
72 ms + 1024TOSC
72 ms
PWRTE = 1
1024TOSC
—
Wake-up from SLEEP
1024TOSC
—
STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
TO
PD
0
0
0
1
1
1
1
1
0
x
0
0
u
1
1
x
0
u
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown.
DS30561C-page 58
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 9-6:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0-
MCLR Reset during normal operation
000h
000u uuuu
---- --u-
MCLR Reset during SLEEP
000h
0001 0uuu
---- --u-
WDT Reset during normal operation
000h
0000 uuuu
---- --u-
PC + 1
uuu0 0uuu
---- --u-
PC + 1(1)
uuu1 0uuu
---- --u-
Condition
WDT Wake-up from SLEEP
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 9-7:
Register
INITIALIZATION CON\DITIONS FOR ALL REGISTERS
Power-on Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or Interrupt
W
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
0000 0000
0000 0000
0000 0000
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
PC + 1(2)
STATUS
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
xxxx xxxx
uuuu uuuu
uuuu uuuu
GPIO
PIC12CE67X
11xx xxxx
11uu uuuu
11uu uuuu
GPIO
PIC12C67X
--xx xxxx
--uu uuuu
--uu uuuu
PCLATH
---0 0000
---0 0000
---u uuuu
INTCON
0000 000x
0000 000u
uuuu uqqq(1)
PIR1
-0-- ----
-0-- ----
-q-- ----(4)
ADCON0
0000 0000
0000 0000
uuuu uquu(5)
OPTION
1111 1111
1111 1111
uuuu uuuu
TRIS
--11 1111
--11 1111
--uu uuuu
PIE1
-0-- ----
-0-- ----
-u-- ----
PCON
---- --0-
---- --u-
---- --u-
OSCCAL
0111 00--
uuuu uu--
uuuu uu--
ADCON1
---- -000
---- -000
---- -uuu
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 9-5 for reset value for specific condition.
If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause bit 6 = u.
If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause bit 3 = u.
1997-2013 Microchip Technology Inc.
DS30561C-page 59
PIC12C67X
FIGURE 9-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 9-8:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30561C-page 60
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 9-10: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 9-11: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
D
VDD
33k
VDD
10k
R
R1
4.3k
MCLR
C
MCLR
PIC12C67X
PIC12C67X
Note 1: External Power-on Reset circuit is required only
if VDD power-up slope is too slow. The diode D
helps discharge the capacitor quickly when VDD
powers down.
2: R < 40 k is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100 to 1 k will limit any current flowing
into MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
Note 1: This circuit will activate reset when VDD goes
below (Vz + 0.7V), where Vz = Zener voltage.
2: Resistors should be adjusted for the characteristics of the transistor.
FIGURE 9-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
4.3k
PIC12C67X
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
R1
= 0.7V
VDD •
R1 + R2
2: Resistors should be adjusted for the characteristics of the transistor.
1997-2013 Microchip Technology Inc.
DS30561C-page 61
PIC12C67X
9.5
Interrupts
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
There are four sources of interrupt:
Interrupt Sources
TMR0 Overflow Interrupt
External Interrupt GP2/INT pin
GPIO Port Change Interrupts (pins GP0, GP1, GP3)
A/D Interrupt
The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set, regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON),
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt flag bits are set,
regardless of the status of their corresponding mask bit
or the GIE bit. The GIE bit is cleared on reset.
The GP2/INT, GPIO port change interrupt and the
TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag ADIF, is contained in the
Special Function Register PIR1. The corresponding
interrupt enable bit is contained in Special Function
Register PIE1, and the peripheral interrupt enable bit is
contained in Special Function Register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid repeated interrupts.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles. The exact latency depends on when
the interrupt event occurs (Figure 9-14). The latency is
the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
FIGURE 9-13: INTERRUPT LOGIC
T0IF
T0IE
Wake-up
(If in SLEEP mode)
INTF
INTE
GPIF
GPIE
ADIF
ADIE
Interrupt to CPU
PEIE
GIE
DS30561C-page 62
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 9-14: INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT
3
4
INT pin
INTF flag
(INTCON)
1
1
Interrupt Latency 2
5
GIE bit
(INTCON)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC+1
Inst (PC+1)
Inst (PC)
0004h
PC+1
—
Dummy Cycle
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTRC and EXTRC oscillator modes.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
1997-2013 Microchip Technology Inc.
DS30561C-page 63
PIC12C67X
9.5.1
9.6
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit T0IF (INTCON). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON) (Section 7.0). The flag bit T0IF
(INTCON) will be set, regardless of the state of the
enable bits. If used, this flag must be cleared in software.
9.5.2
INT INTERRUPT
External interrupt on GP2/INT pin is edge triggered;
either rising if bit INTEDG (OPTION) is set, or falling, if the INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, flag bit INTF
(INTCON) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON). Flag bit INTF
must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up.
See Section 9.8 for details on SLEEP mode.
9.5.3
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 shows the storing and restoring of the
STATUS and W registers. The register, W_TEMP, must
be defined in both banks and must be defined at the
same offset from the bank base address (i.e., if
W_TEMP is defined at 0x20 in bank 0, it must also be
defined at 0xA0 in bank 1).
Example 9-2 shows the saving and restoring of STATUS and W using RAM locations 0x70 - 0x7F.
W_TEMP is defined at 0x70 and STATUS_TEMP is
defined at 0x71.
The example:
a)
b)
c)
d)
e)
f)
GPIO INTCON CHANGE
Context Saving During Interrupts
Stores the W register.
Stores the STATUS register in bank 0.
Executes the ISR code.
Restores the STATUS register (and bank select
bit).
Restores the W register.
Returns from interrupt.
An input change on GP3, GP1 or GP0 sets flag bit GPIF
(INTCON). The interrupt can be enabled/disabled by
setting/clearing enable bit GPIE (INTCON)
(Section 5.1) . This flag bit GPIF (INTCON) will be
set, regardless of the state of the enable bits. If used, this
flag must be cleared in software.
EXAMPLE 9-1:
SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM
(0x20 - 0x6F)
MOVWF
SWAPF
BCF
MOVWF
:
:(ISR)
:
SWAPF
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
;Copy W to TEMP
;Swap status to
;Change to bank
;Save status to
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
RETFIE
STATUS
W_TEMP,F
W_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;Return from interrupt
EXAMPLE 9-2:
MOVWF
MOVF
MOVWF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
SWAPF
RETFIE
DS30561C-page 64
register, could be bank one or zero
be saved into W
zero, regardless of current bank
bank zero STATUS_TEMP register
SAVING STATUS AND W REGISTERS USING SHARED RAM (0x70 - 0x7F)
W_TEMP
STATUS,W
STATUS_TEMP
;Copy W to TEMP register (bank independent)
;Move STATUS register into W
;Save contents of STATUS register
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;Retrieve copy of STATUS register
;Restore pre-isr STATUS register contents
;
;Restore pre-isr W register contents
;Return from interrupt
1997-2013 Microchip Technology Inc.
PIC12C67X
9.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 9.1).
9.7.1
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
Note:
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
When the prescaler is assigned to the
WDT, always execute a CLRWDT instruction
before changing the prescale value, otherwise a WDT reset may occur.
See Example 7-1 and Example 7-2 for changing prescaler between WDT and Timer0.
FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-5)
0
1
WDT Timer
Postscaler
M
U
X
8
8 - to - 1 MUX
PS
PSA
WDT
Enable Bit
To TMR0 (Figure 7-5)
0
1
MUX
WDT
Time-out
Note: PSA and PS are bits in the OPTION register.
TABLE 9-8:
PSA
SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits(1)
81h
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCLRE
CP1
CP0
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
1997-2013 Microchip Technology Inc.
DS30561C-page 65
PIC12C67X
9.8
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS) is cleared, the
TO (STATUS) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input, if enabled, should also be at VDD or VSS
for lowest current consumption. The contribution from
on-chip pull-ups on GPIO should be considered.
The MCLR pin, if enabled, must be at a logic high level
(VIHMC).
9.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
GP2/INT interrupt, interrupt GPIO port change
or some Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupt can wake the device
from SLEEP:
1.
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
9.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the the execution of
a SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from sleep . The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
A/D conversion (when A/D clock source is RC).
DS30561C-page 66
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 9-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
GPIO pin
GPIF flag
(INTCON)
Interrupt Latency
(Note 3)
GIE bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst(PC) = SLEEP
Instruction
executed
Inst(PC - 1)
PC+1
PC+2
PC+2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will
continue in-line.
4: CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.
9.9
Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
9.10
Microchip does not recommend code protecting windowed devices.
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID
location are used.
9.11
In-Circuit Serial Programming
PIC12C67X microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming voltage. This allows customers to manufacture boards with
unprogrammed devices, and then program the microcontroller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 (clock) becomes the programming
clock and GP0 (data) becomes the programming data.
Both GP0 and GP1 are Schmitt Trigger inputs in this
mode.
1997-2013 Microchip Technology Inc.
After reset, and if the device is placed into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the
device. Depending on the command, 14-bits of program data are then supplied to or from the device,
depending if the command was a load or a read. For
complete details of serial programming, please refer to
the PIC12C67X Programming Specifications.
FIGURE 9-17: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC12C67X
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1
Data I/O
GP0
VDD
To Normal
Connections
DS30561C-page 67
PIC12C67X
NOTES:
DS30561C-page 68
1997-2013 Microchip Technology Inc.
PIC12C67X
10.0
INSTRUCTION SET SUMMARY
Each PIC12C67X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC12C67X instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 101 shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 s.
Table 10-2 lists the instructions recognized by the
MPASM assembler.
Figure 10-1 shows the three general formats that the
instructions can have.
Note:
To maintain upward compatibility with
future PIC12C67X products, do not use the
OPTION and TRIS instructions.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 10-1:
OPCODE FIELD
DESCRIPTIONS
All examples use the following format to represent a
hexadecimal number:
0xhh
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label Label name
TOS
PC
Top of Stack
where h signifies a hexadecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
Program Counter
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
dest Destination either the W register or the specified
register file location
[ ]
Options
( )
Contents
0
b = 3-bit bit address
f = 7-bit file register address
PCLATH Program Counter High Latch
GIE
0
Literal and control operations
General
13
8 7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
10
0
Assigned to
OPCODE
k (literal)
Register bit field
k = 11-bit immediate value
In the set of
italics User defined term (font is courier)
1997-2013 Microchip Technology Inc.
DS30561C-page 69
PIC12C67X
10.1
Special Function Registers as
Source/Destination
The PIC12C67X’s orthogonal instruction set allows
read and write of all file registers, including special
function registers. There are some special situations
the user should be aware of:
10.1.1
STATUS AS DESTINATION
If an instruction writes to STATUS, the Z, C and DC bits
may be set or cleared as a result of the instruction and
overwrite the original data bits written. For example,
executing CLRF STATUS will clear register STATUS,
and then set the Z bit leaving 0000 0100b in the register.
10.1.3
Read, write or read-modify-write on PCL may have the
following results:
Read PC:
PCL dest
Write PCL:
PCLATH PCH;
8-bit destination value PCL
Read-Modify-Write:
PCL ALU operand
PCLATH PCH;
8-bit result PCL
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
10.1.4
10.1.2
PCL AS SOURCE OR DESTINATION
BIT MANIPULATION
TRIS AS DESTINATION
Bit 3 of the TRIS register always reads as a '1' since
GP3 is an input only pin. This fact can affect some readmodify-write operations on the TRIS register.
DS30561C-page 70
All bit manipulation instructions are done by first reading the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 10-2:
Mnemonic,
Operands
INSTRUCTION SET SUMMARY
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( i.e., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1997-2013 Microchip Technology Inc.
DS30561C-page 71
PIC12C67X
10.2
Instruction Descriptions
ADDLW
Add Literal and W
ANDLW
And Literal with W
Syntax:
[ label ] ANDLW
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operands:
0 k 255
Operation:
(W) + k (W)
Operation:
(W) .AND. (k) (W)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
11
k
111x
kkkk
kkkk
Encoding:
11
k
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and
the result is placed in the W register.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W register.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ADDLW
0x15
Example
Before Instruction
W
=
=
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d
Operation:
(W) + (f) (dest)
Status Affected:
C, DC, Z
Encoding:
00
W
W
f,d
dfff
ffff
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0, the result
is stored in the W register. If 'd' is
1, the result is stored back in register 'f'.
Words:
Cycles:
Example
0xA3
=
0x03
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d
Operation:
(W) .AND. (f) (dest)
Status Affected:
Z
Encoding:
00
f,d
0101
dfff
ffff
Description:
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
1
Words:
1
1
Cycles:
1
ADDWF
FSR, 0
W =
FSR =
0x17
0xC2
After Instruction
W =
FSR =
Example
ANDWF
FSR, 1
Before Instruction
Before Instruction
DS30561C-page 72
=
After Instruction
0x25
0111
0x5F
Before Instruction
0x10
After Instruction
W
ANDLW
0xD9
0xC2
W =
FSR =
0x17
0xC2
After Instruction
W =
FSR =
0x17
0x02
1997-2013 Microchip Technology Inc.
PIC12C67X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] BCF
Syntax:
[ label ] BTFSC f,b
Operands:
0 f 127
0b7
Operands:
0 f 127
0b7
Operation:
0 (f)
Operation:
skip if (f) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example
BCF
Encoding:
FLAG_REG = 0x47
bfff
ffff
If bit 'b' in register 'f' is '0', then the
next instruction is skipped.
If bit 'b' is '0', then the next instruction fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a 2 cycle instruction.
Words:
1
Cycles:
1(2)
Before Instruction
FLAG_REG = 0xC7
10bb
Description:
FLAG_REG, 7
After Instruction
01
Example
HERE
FALSE
TRUE
FLAG,1
PROCESS_CO
DE
BTFSC
GOTO
•
•
•
Before Instruction
PC =
address HERE
After Instruction
if FLAG = 0,
PC =
address TRUE
if FLAG=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f)
Status Affected:
None
Encoding:
Description:
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Example
f,b
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
1997-2013 Microchip Technology Inc.
DS30561C-page 73
PIC12C67X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
Operands:
0 f 127
0b VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byGPIO pins combined ...................................................................................................100 mA
Maximum current sourced by GPIO pins combined..............................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997-2013 Microchip Technology Inc.
DS30561C-page 89
PIC12C67X
FIGURE 12-1: PIC12C67X VOLTAGE-FREQUENCY GRAPH, -40C TA 0C, +70C TA +125C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
20
10
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 12-2: PIC12C67X VOLTAGE-FREQUENCY GRAPH, 0C TA +70C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS30561C-page 90
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 12-3: PIC12LC67X VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1997-2013 Microchip Technology Inc.
DS30561C-page 91
PIC12C67X
12.1
DC Characteristics:
PIC12C671/672 (Commercial, Industrial, Extended)
PIC12CE673/674 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
–40°C TA +125°C (extended)
DC CHARACTERISTICS
Parm
No.
Characteristic
Sym
D001
Supply Voltage
VDD
D002
RAM Data Retention
Voltage(2)
VDR
D003
VDD Start Voltage to ensure VPOR
Power-on Reset
D004
VDD Rise Rate to ensure
Power-on Reset
SVDD
D010
Supply Current(3)
IDD
D010C
D010A
Min
Typ(1) Max Units
3.0
5.5
Conditions
V
1.5*
V
Device in SLEEP mode
VSS
V
See section on Power-on Reset for details
0.05*
V/ms See section on Power-on Reset for details
—
1.2
2.5
mA
—
1.2
2.5
mA
—
2.2
8
mA
—
19
29
A
—
19
37
A
—
32
60
A
FOSC = 4MHz, VDD = 3.0V
XT and EXTRC mode (Note 4)
FOSC = 4MHz, VDD = 3.0V
INTRC mode (Note 6)
FOSC = 10MHz, VDD = 5.5V
HS mode
FOSC = 32kHz, VDD = 3.0V, WDT disabled
LP mode, Commercial Temperature
FOSC = 32kHz, VDD = 3.0V, WDT disabled
LP mode, Industrial Temperature
FOSC = 32kHz, VDD = 3.0V, WDT disabled
LP mode, Extended Temperature
D020
Power-down Current(5)
D021
D021B
IPD
—
—
—
—
—
—
0.25
0.25
2
0.5
0.8
3
6
7
14
8
9
16
A
A
A
A
A
A
VDD = 3.0V, Commercial, WDT disabled
VDD = 3.0V, Industrial, WDT disabled
VDD = 3.0V, Extended, WDT disabled
VDD = 5.5V, Commercial, WDT disabled
VDD = 5.5V, Industrial, WDT disabled
VDD = 5.5V, Extended, WDT disabled
D022
Watchdog Timer Current
IWDT
—
—
—
2.2
2.2
4
5
6
11
A
A
A
VDD = 3.0V, Commercial
VDD = 3.0V, Industrial
VDD = 3.0V, Extended
D028
Supply Current(3)
During read/write to
EEPROM peripheral
IEE
—
0.1
0.2
mA
FOSC = 4MHz, VDD = 5.5V, SCL = 400kHz
For PIC12CE673/674 only
* These parameters are characterized but not tested.
Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is for design guidance only and is not
tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator
type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula:
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.
DS30561C-page 92
1997-2013 Microchip Technology Inc.
PIC12C67X
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
–40°C TA +125°C (extended)
DC CHARACTERISTICS
Parm
No.
Characteristic
LP Oscillator Operating
Frequency
INTRC/EXTRC Oscillator
Operating Frequency
XT Oscillator Operating
Frequency
HS Oscillator Operating
Frequency
Sym
FOSC
Min
Typ(1) Max Units
Conditions
0
200
kHz
—
4(6)
MHz All temperatures
0
4
MHz All temperatures
0
10
MHz All temperatures
All temperatures
* These parameters are characterized but not tested.
Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is for design guidance only and is not
tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator
type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula:
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.
1997-2013 Microchip Technology Inc.
DS30561C-page 93
PIC12C67X
12.2
DC Characteristics:
PIC12LC671/672 (Commercial, Industrial)
PIC12LCE673/674 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature 0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min
Typ† Max Units
2.5
5.5
Conditions
V
D001
Supply Voltage
VDD
D002
RAM Data Retention
Voltage(2)
VDR
1.5*
V
Device in SLEEP mode
D003
VDD Start Voltage to
ensure Power-on Reset
VPOR
VSS
V
See section on Power-on Reset for details
D004
VDD Rise Rate to ensure
Power-on Reset
SVDD
D010
Supply Current(3)
IDD
0.05*
V/ms See section on Power-on Reset for details
—
0.4
2.1
mA
D010C
—
0.4
2.1
mA
D010A
—
15
33
A
—
—
0.2
0.2
5
6
A
A
VDD = 2.5V, Commercial
VDD = 2.5V, Industrial
Watchdog Timer Current IWDT
—
2.0
2.0
4
6
A
A
VDD = 2.5V, Commercial
VDD = 2.5V, Industrial
LP Oscillator Operating FOSC
Frequency
INTRC/EXTRC Oscillator
Operating Frequency
XT Oscillator Operating
Frequency
HS Oscillator Operating
Frequency
0
200
kHz
All temperatures
—
4(6)
MHz
All temperatures
0
4
MHz
All temperatures
0
10
MHz
All temperatures
D020
D021
D021B
Power-down Current(5)
FOSC = 4MHz, VDD = 2.5V
XT and EXTRC mode (Note 4)
FOSC = 4MHz, VDD = 2.5V
INTRC mode (Note 6)
FOSC = 32kHz, VDD = 2.5V, WDT disabled
LP mode, Industrial Temperature
IPD
* These parameters are characterized but not tested.
Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is for design guidance only and is not
tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator
type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD,
MCLR = VDD; WDT disabled.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula:
Ir = VDD/2REXT (mA) with REXT in kOhm.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.
DS30561C-page 94
1997-2013 Microchip Technology Inc.
PIC12C67X
12.3
DC CHARACTERISTICS:
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D031
D032
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
(in EXTRC mode)
OSC1 (in EXTRC mode)
OSC1 (in XT, HS, and LP)
Input High Voltage
I/O ports
with TTL buffer
D033
D033
D040
D040A
D041
with Schmitt Trigger buffer
D042 MCLR, GP2/T0CKI/AN2/INT
D042A OSC1 (XT, HS, and LP)
D043 OSC1 (in EXTRC mode)
Input Leakage Current (Notes 2, 3)
D060 I/O ports
PIC12C671/672 (Commercial, Industrial, Extended)
PIC12CE673/674 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
–40°C TA +125°C (extended)
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Sym
Min
Typ† Max Units
Conditions
VIL
—
—
—
—
0.8V
0.15VDD
0.2VDD
0.2VDD
V
V
V
V
VSS
VSS
—
—
0.2VDD
0.3VDD
V
2.0V
0.25VDD + 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5V VDD 5.5V
otherwise
For entire VDD range
—
—
+1
A
+30
+5
A
A
A
VSS VPIN VDD, Pin at
hi-impedance
VSS VPIN VDD
VSS VPIN VDD
VSS VPIN VDD
VIH
IIL
D061 GP3/MCLR (Note 5)
D061A GP3 (Note 6)
D062 GP2/T0CKI
—
—
D063
OSC1
—
—
D070
GPIO weak pull-up current (Note 4)
MCLR pull-up current
Output Low Voltage
I/O ports
IPUR
50
250
—
—
—
400
30
A
A
VOL
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
D080
D080A
D083
OSC2/CLKOUT
D083A
†
Note 1:
2:
3:
4:
5:
6:
For 4.5V VDD5.5V
otherwise
VSS
VSS
VSS
VSS
+5
+5
A
Note 1
Note 1
Note 1
VSS VPIN VDD, XT, HS, and
LP osc configuration
VDD = 5V, VPIN = VSS
VDD = 5V, VPIN = VSS
IOL = 8.5 mA, VDD = 4.5V,
–40C to +85C
IOL = 7.0 mA, VDD = 4.5V,
–40C to +125C
IOL = 1.6 mA, VDD = 4.5V,
–40C to +85C
IOL = 1.2 mA, VDD = 4.5V,
–40C to +125C
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Does not include GP3. For GP3 see parameters D061 and D061A.
This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
1997-2013 Microchip Technology Inc.
DS30561C-page 95
PIC12C67X
DC CHARACTERISTICS
Param
No.
Characteristic
Output High Voltage
I/O ports (Note 3)
D090
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
–40°C TA +125°C (extended)
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Sym
Min
Typ† Max Units
Conditions
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
COSC2
—
—
15
pF
CIO
—
—
50
pF
VOH
D090A
D092
OSC2/CLKOUT
D092A
Capacitive Loading Specs on
Output Pins
OSC2 pin
D100
D101
All I/O pins
†
Note 1:
2:
3:
4:
5:
6:
IOH = -3.0 mA, VDD = 4.5V,
–40C to +85C
IOH = -2.5 mA, VDD = 4.5V,
–40C to +125C
IOH = 1.3 mA, VDD = 4.5V,
–40C to +85C
IOH = 1.0 mA, VDD = 4.5V,
–40C to +125C
In XT and LP modes when
external clock is used to drive
OSC1.
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Does not include GP3. For GP3 see parameters D061 and D061A.
This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit
is higher than the standard I/O logic.
DS30561C-page 96
1997-2013 Microchip Technology Inc.
PIC12C67X
12.4
DC CHARACTERISTICS:
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D031
D032
D033
D033
D040
D040A
D041
D042
D042A
D043
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
(in EXTRC mode)
OSC1 (in EXTRC mode)
OSC1 (in XT, HS, and LP)
Input High Voltage
I/O ports
with TTL buffer
PIC12LC671/672 (Commercial, Industrial)
PIC12LCE673/674 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Sym
Min
Typ† Max
Units
Conditions
VIL
VSS
VSS
VSS
VSS
—
—
—
—
0.8V
0.15VDD
0.2VDD
0.2VDD
V
V
V
V
For 4.5V VDD5.5V
otherwise
VSS
VSS
—
—
0.2VDD
0.3VDD
V
V
Note 1
Note 1
2.0V
0.25VDD + 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5V VDD 5.5V
otherwise
For entire VDD range
—
—
+1
A
+30
+5
A
A
A
Vss VPIN VDD, Pin at
hi-impedance
Vss VPIN VDD
Vss VPIN VDD
Vss VPIN VDD
VIH
D060
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
OSC1 (XT, HS, and LP)
OSC1 (in EXTRC mode)
Input Leakage Current (Notes 2, 3)
I/O ports
D061
D061A
D062
GP3/MCLR (Note 5)
GP3 (Note 6)
GP2/T0CKI
—
—
D063
OSC1
—
—
+5
+5
D070
GPIO weak pull-up current (Note 4)
MCLR pull-up current
Output Low Voltage
I/O ports
IPUR
—
50
—
250
—
400
30
A
A
VOL
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
—
—
0.6
V
D080
D080A
D083
OSC2/CLKOUT
D083A
†
Note 1:
2:
3:
4:
5:
6:
IIL
A
Note 1
Vss VPIN VDD, XT, HS and
LP osc configuration
VDD = 5V, VPIN = VSS
VDD = 5V, VPIN = VSS
IOL = 8.5 mA, VDD = 4.5V,
–40C to +85C
IOL = 7.0 mA, VDD = 4.5V,
–40C to +125C
IOL = TBD, VDD = 4.5V,
–40C to +85C
IOL = TBD, VDD = 4.5V,
–40C to +125C
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Does not include GP3. For GP3 see parameters D061 and D061A.
This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is
higher than the standard I/O logic.
1997-2013 Microchip Technology Inc.
DS30561C-page 97
PIC12C67X
DC CHARACTERISTICS
Param
No.
Characteristic
Output High Voltage
I/O ports (Note 3)
D090
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Sym
Min
Typ† Max
Units
Conditions
VOH
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
COSC2
—
—
15
pF
CIO
—
—
50
pF
D090A
D092
OSC2/CLKOUT
D092A
Capacitive Loading Specs on
Output Pins
OSC2 pin
D100
D101
All I/O pins
†
Note 1:
2:
3:
4:
5:
6:
IOH = -3.0 mA, VDD = 4.5V,
–40C to +85C
IOH = -2.5 mA, VDD = 4.5V,
–40C to +125C
IOH = TBD, VDD = 4.5V,
–40C to +85C
IOH = TBD, VDD = 4.5V,
–40C to +125C
In XT and LP modes when
external clock is used to drive
OSC1.
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X
be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
Does not include GP3. For GP3 see parameters D061 and D061A.
This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up
enabled.
This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is
higher than the standard I/O logic.
DS30561C-page 98
1997-2013 Microchip Technology Inc.
PIC12C67X
12.5
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 12-4: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464
CL = 50 pF
15 pF
1997-2013 Microchip Technology Inc.
for all pins except OSC2
for OSC2 output
DS30561C-page 99
PIC12C67X
12.6
Timing Diagrams and Specifications
FIGURE 12-5: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 12-1:
Parameter
No.
CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and EXTRC osc mode
DC
—
4
MHz HS osc mode (PIC12CE67X-04)
DC
—
10
MHz HS osc mode (PIC12CE67X-10)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz EXTRC osc mode
(Note 1)
.455
—
4
MHz XT osc mode
4
—
4
MHz HS osc mode (PIC12CE67X-04)
4
—
10
MHz HS osc mode (PIC12CE67X-10)
5
—
200
kHz LP osc mode
1
TOSC External CLKIN Period
250
—
—
ns
XT and EXTRC osc mode
(Note 1)
250
—
—
ns
HS osc mode (PIC12CE67X-04)
100
—
—
ns
HS osc mode (PIC12CE67X-10)
5
—
—
s
LP osc mode
Oscillator Period
250
—
—
ns
EXTRC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (PIC12CE67X-04)
100
—
250
ns
HS osc mode (PIC12CE67X-10)
5
—
—
s
LP osc mode
2
TCY Instruction Cycle Time (Note 1) 400
—
DC
ns
TCY = 4/FOSC
3
TosL, External Clock in (OSC1) High
50
—
—
ns
XT oscillator
TosH or Low Time
2.5
—
—
s
LP oscillator
10
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise
—
—
25
ns
XT oscillator
TosF or Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based
on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than
expected current consumption. All devices are tested to operate at "min." values with an external clock applied to
the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC12C67X.
FOSC
DS30561C-page 100
External CLKIN Frequency
(Note 1)
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 12-2:
CALIBRATED INTERNAL RC FREQUENCIES -PIC12C671, PIC12C672, PIC12CE673,
PIC12CE674, PIC12LC671,
PIC12LC672, PIC12LCE673,
PIC12LCE674
AC Characteristics
Parameter
No.
*
Note 1:
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C (commercial),
–40C TA +85C (industrial),
–40C TA +125C (extended)
Operating Voltage VDD range is described in Section 10.1
Min*
Typ(1)
Internal Calibrated RC Frequency
3.65
4.00
4.28
MHz VDD = 5.0V
Internal Calibrated RC Frequency
3.55
4.00
4.31
MHz VDD = 2.5V
Sym
Characteristic
Max* Units
Conditions
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1997-2013 Microchip Technology Inc.
DS30561C-page 101
PIC12C67X
FIGURE 12-6: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 12-4 for load conditions.
TABLE 12-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL OSC1 to CLKOUT
—
75
200
ns
Note 1
11*
TosH2ckH OSC1 to CLKOUT
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH Port in valid before CLKOUT
TOSC + 200
—
—
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT
0
—
—
ns
Note 1
17*
TosH2ioV
OSC1 (Q1 cycle) to Port out valid
—
50
150
ns
18*
TosH2ioI
OSC1 (Q2 cycle) to Port
input invalid (I/O in hold
time)
18A*
PIC12C67X
100
—
—
ns
PIC12LC67X
200
—
—
ns
0
—
—
ns
PIC12C67X
—
10
40
ns
PIC12LC67X
—
—
80
ns
PIC12C67X
—
10
40
ns
PIC12LC67X
—
—
80
ns
19*
TioV2osH Port input valid to OSC1(I/O in setup
time)
20*
TioR
Port output rise time
20A*
21*
TioF
21A*
Port output fall time
22††*
Tinp
GP2/INT pin high or low time
TCY
—
—
ns
23††*
Trbp
GP0/GP1/GP3 change INT high or low
time
TCY
—
—
ns
*
†
††
Note 1:
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are asynchronous events not related to any internal clock edge.
Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.
DS30561C-page 102
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
36
34
31
34
I/O Pins
TABLE 12-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
Parameter
No.
Sym
*
†
Characteristic
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
s
VDD = 5V, –40°C to +125°C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, –40°C to +125°C
32
Tost
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power up Timer Period
28
72
132
ms
VDD = 5V, –40°C to +125°C
34
TIOZ
I/O Hi-impedance from MCLR
Low or Watchdog Timer Reset
—
—
2.1
s
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
1997-2013 Microchip Technology Inc.
DS30561C-page 103
PIC12C67X
FIGURE 12-8: TIMER0 CLOCK TIMINGS
GP2/T0CKI
41
40
42
TMR0
Note: Refer to Figure 12-4 for load conditions.
TABLE 12-5:
Param
No.
Sym
40*
Tt0H
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic
T0CKI High Pulse Width
Min
No Prescaler
0.5TCY + 20
—
—
ns
10
—
—
ns
With Prescaler
41*
Tt0L
T0CKI Low Pulse Width
No Prescaler
0.5TCY + 20
—
—
ns
10
—
—
ns
TCY + 40
—
—
ns
—
—
ns
—
7Tos
c
—
With Prescaler
42*
Tt0P
T0CKI Period
No Prescaler
With Prescaler
48
TCKE2tmr1 Delay from external clock edge to timer
increment
Typ† Max Units
Greater of:
20 or TCY + 40
N
2TOSC
Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale
value (2, 4,...,
256)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
TABLE 12-6:
GPIO PULL-UP RESISTOR RANGES
VDD (Volts)
Temperature (C)
Min
Typ
Max
Units
2.5
–40
38K
42K
63K
25
42K
48K
63K
85
42K
49K
63K
125
50K
55K
63K
–40
15K
17K
20K
25
18K
20K
23K
85
19K
22K
25K
125
22K
24K
28K
GP0/GP1
5.5
GP3
–40
285K
346K
417K
25
343K
414K
532K
85
368K
457K
532K
125
431K
504K
593K
–40
247K
292K
360K
25
288K
341K
437K
85
306K
371K
448K
125
351K
These parameters are characterized but not tested.
407K
500K
2.5
5.5
*
DS30561C-page 104
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 12-7:
Param
No.
Sym
A01
NR
A02
A/D CONVERTER CHARACTERISTICS:
PIC12C671/672-04/PIC12CE673/674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC12C671/672-10/PIC12CE673/674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC12LC671/672-04/PIC12LCE673/674-04 (COMMERCIAL, INDUSTRIAL)
Characteristic
Resolution
EABS Total absolute error
Min
Typ†
Max
Units
Conditions
—
—
8-bits
bit
VREF = VDD = 5.12V,
VSS VAIN VREF
—
—
< 1
LSb
VREF = VDD = 5.12V,
VSS VAIN VREF
A03
EIL
Integral linearity error
—
—
< 1
LSb
VREF = VDD = 5.12V,
VSS VAIN VREF
A04
EDL
Differential linearity error
—
—
< 1
LSb
VREF = VDD = 5.12V,
VSS VAIN VREF
A05
EFS
Full scale error
—
—
< 1
LSb
VREF = VDD = 5.12V,
VSS VAIN VREF
A06
EOFF Offset error
—
—
< 1
LSb
VREF = VDD = 5.12V,
VSS VAIN VREF
—
guaranteed
(Note 3)
—
—
2.5V
—
VDD + 0.3
V
VSS - 0.3
—
VREF + 0.3
V
—
—
10.0
k
PIC12C67X
—
180
—
A
PIC12LC67X
—
90
—
A
10
—
1000
A
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 8.1.
—
—
10
A
During A/D Conversion
cycle
A10
—
Monotonicity
A20
VREF Reference voltage
A25
VAIN
Analog input voltage
A30
ZAIN
Recommended impedance of
analog voltage source
A40
IAD
A/D conversion
current (VDD)
A50
IREF
VREF input current (Note 2)
VSS VAIN VREF
Average current consumption when A/D is on.
(Note 1)
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
1997-2013 Microchip Technology Inc.
DS30561C-page 105
PIC12C67X
FIGURE 12-9: A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
Q4
130
132
A/D CLK
7
A/D DATA
6
5
4
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 12-8:
A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
130
TAD
A/D clock period
Min
1.6
—
—
s
TOSC based, VREF 3.0V
—
—
s
TOSC based, VREF full range
PIC12C67X
2.0
4.0
6.0
s
A/D RC Mode
PIC12LC67X
3.0
6.0
9.0
s
A/D RC Mode
11
—
11
TAD
Note 2
20
—
s
5*
—
—
s
The minimum time is the
amplifier setting time. This
may be used if the "new"
input voltage has not
changed by more than 1 LSb
(i.e., 20.0 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of
TCY is added before the A/D
clock starts. This allows the
SLEEP instruction to be executed.
1.5 §
—
—
TAD
132
TACQ
Acquisition time
TSWC
Conditions
2.0
Conversion time (not including S/H
time) (Note 1)
135
Units
PIC12LC67X
TCNV
TGO
Max
PIC12C67X
131
134
Typ†
Q4 to A/D clock start
Switching from convert sample time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and
are not tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 8.1 for min. conditions.
DS30561C-page 106
1997-2013 Microchip Technology Inc.
PIC12C67X
TABLE 12-9:
EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE673/674 ONLY.
AC Characteristics
Parameter
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0C TA +70C, Vcc = 3.0V to 5.5V (commercial)
–40C TA +85C, Vcc = 3.0V to 5.5V (industrial)
–40C TA +125C, Vcc = 4.5V to 5.5V (extended)
Operating Voltage VDD range is described in Section 12.1
Symbol
Min
Max
Units
Conditions
Clock frequency
FCLK
—
—
—
100
100
400
kHz
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
Clock high time
THIGH
4000
4000
600
—
—
—
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
Clock low time
TLOW
4700
4700
1300
—
—
—
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
SDA and SCL rise time
(Note 1)
TR
—
—
—
1000
1000
300
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
SDA and SCL fall time
TF
—
300
ns
(Note 1)
START condition hold time
THD:STA
4000
4000
600
—
—
—
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
START condition setup time
TSU:STA
4700
4700
600
—
—
—
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
Data input hold time
THD:DAT
0
—
ns
(Note 2)
Data input setup time
TSU:DAT
250
250
100
—
—
—
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
STOP condition setup time
TSU:STO
4000
4000
600
—
—
—
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
TAA
—
—
—
3500
3500
900
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
Bus free time: Time the bus must
be free before a new transmission can start
TBUF
4700
4700
1300
—
—
—
ns
4.5V Vcc 5.5V (E Temp range)
3.0V Vcc 4.5V
4.5V Vcc 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
20+0.1
CB
250
ns
(Note 1), CB 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
—
50
ns
(Notes 1, 3)
Write cycle time
TWC
—
4
ms
1M
—
cycles
Output valid from clock
(Note 2)
Endurance
25C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL and avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s website.
1997-2013 Microchip Technology Inc.
DS30561C-page 107
PIC12C67X
NOTES:
DS30561C-page 108
1997-2013 Microchip Technology Inc.
PIC12C67X
13.0
DC AND AC CHARACTERISTICS - PIC12C671/PIC12C672/PIC12LC671/
PIC12LC672/PIC12CE673/PIC12CE674/PIC12LCE673/PIC12LCE674
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables
the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only
and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3) and (mean – 3)
respectively, where is standard deviation.
FIGURE 13-1: CALIBRATED INTERNAL RC
FREQUENCY RANGE VS.
TEMPERATURE (VDD = 5.0V)
(INTERNAL RC IS
CALIBRATED TO 25°C, 5.0V)
4.50
4.50
4.40
4.40
4.30
4.30
4.20
Max.
4.20
Max.
4.10
Frequency (MHz)
Frequency (MHz)
FIGURE 13-2: CALIBRATED INTERNAL RC
FREQUENCY RANGE VS.
TEMPERATURE (VDD = 2.5V)
(INTERNAL RC IS
CALIBRATED TO 25°C, 5.0V)
4.00
3.90
4.10
4.00
3.90
3.80
3.80
Min.
3.70
3.70
3.60
3.60
3.50
3.50
-40
0
25
85
Temperature (Deg.C)
1997-2013 Microchip Technology Inc.
125
Min.
-40
0
25
85
125
Temperature (Deg.C)
DS30561C-page 109
PIC12C67X
TABLE 13-1:
DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C
Oscillator
Frequency
External RC
4 MHz
Internal RC
4 MHz
XT
4 MHz
LP
32 kHz
*Does not include current through external R&C.
VDD = 2.5V
VDD = 5.5V
400 µA*
400 µA
400 µA
15 µA
900 µA*
900 µA
900 µA
60 µA
FIGURE 13-4: IOH vs. VOH, VDD = 2.5 V
FIGURE 13-3: WDT TIMER TIME-OUT
PERIOD vs. VDD
-0
55
-1
50
-2
45
-3
WDT period (mS)
35
Max +125C
IOH (mA)
-4
40
Min +125C
-5
Min +85C
-6
Typ +25C
30
Max +85C
-7
25
-8
20
Typ +25C
-9
Max -40C
-10
15
.5 .75 1.0 1.25 1.5 1.75 2.0 2.25 2.5
MIn –40C
10
0
2.5
3.5
4.5
5.5
VOH (Volts)
6.5
VDD (Volts)
DS30561C-page 110
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 13-5: IOH vs. VOH, VDD = 3.5 V
FIGURE 13-7: IOL vs. VOL, VDD = 2.5 V
35
0
30
-5
IOH (mA)
Max -40C
Min +125C
25
-10
IOL (mA)
Min +85C
Typ +25C
-15
20
Typ +25C
15
Max -40C
-20
Min +85C
10
Min +125C
-25
1.5
2.0
2.5
3.0
3.5
5
VOH (Volts)
0
0
FIGURE 13-6: IOH vs. VOH, VDD = 5.5 V
0.25
0.5
0.75
1.0
VOL (Volts)
0
FIGURE 13-8: IOL vs. VOL, VDD = 3.5 V
-5
45
-10
IOH (mA)
-15
n
Mi
M
25
+1
+
in
40
C
85
25
p+
Ty
-20
Max -40C
C
35
C
30
-25
M
ax
-30
IOL (mA)
–4
0
C
Typ +25C
-35
25
20
-40
3.5
4.0
4.5
5.0
5.5
15
Min +85C
VOH (Volts)
Min +125C
10
0
0
0.25
0.5
0.75
1.0
VOL (Volts)
1997-2013 Microchip Technology Inc.
DS30561C-page 111
PIC12C67X
FIGURE 13-9: IOL vs. VOL, VDD = 5.5 V
FIGURE 13-10: VTH (INPUT THRESHOLD
VOLTAGE) OF GPIO PINS
vs. VDD
55
1.8
Max -40C
50
Max (-40 to 125)
VTH (Volts)
1.6
45
40
1.4
Typ (25
1.2
35
IOL (mA)
Typ +25C
Min (-40 to 125)
1.0
30
0.8
25
Min +85C
20
15
Min +125C
0.6
0
2.5
3.5
4.5
VDD (Volts)
5.5
10
0
0
0.25
0.5
0.75
1.0
VOL (Volts)
DS30561C-page 112
1997-2013 Microchip Technology Inc.
PIC12C67X
FIGURE 13-11: VIL, VIH OF NMCLR AND T0CKI vs. VDD
3.5
VIH Max (-40 to 125)
VIH Typ (25
VIH Min (-40 to 125)
VIL, VIH (Volts)
3.0
2.5
2.0
VIL Max (-40 to 125)
1.5
VIL Typ (25
VIL Min (-40 to 125)
1.0
0.5
2.5
3.5
4.5
5.5
VDD (Volts)
1997-2013 Microchip Technology Inc.
DS30561C-page 113
PIC12C67X
NOTES:
DS30561C-page 114
1997-2013 Microchip Technology Inc.
PIC12C67X
14.0
PACKAGING INFORMATION
14.1
Package Marking Information
8-Lead PDIP (300 mil)
MMMMMMMM
XXXXXCDE
AABB
12CE674
04/PSAZ
9925
8-Lead SOIC (208 mil)
MMMMMMM
XXXXXXX
AABBCDE
Example
JW
MM
CE674
MMMMMM
Legend: MM...M
XX...X
AA
BB
C
D
E
*
Example
12C671
04I/SM
9924SAZ
8-Lead Windowed Ceramic Side Brazed (300 mil)
Note:
Example
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1997-2013 Microchip Technology Inc.
DS30561C-page 115
PIC12C67X
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
A
L
c
A1
B1
p
eB
B
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
MAX
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
8
Pitch
.100
Top to Seating Plane
A
.140
.155
.170
Molded Package Thickness
A2
.115
.130
.145
Base to Seating Plane
.015
A1
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.360
.373
.385
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
eB
.310
.370
.430
Mold Draft Angle Top
5
10
15
Mold Draft Angle Bottom
5
10
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
DS30561C-page 116
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
1997-2013 Microchip Technology Inc.
PIC12C67X
8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
2
1
n
B
c
A2
A
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
c
B
MIN
.070
.069
.002
.300
.201
.202
.020
0
.008
.014
0
0
INCHES*
NOM
8
.050
.075
.074
.005
.313
.208
.205
.025
4
.009
.017
12
12
A1
MAX
.080
.078
.010
.325
.212
.210
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.78
1.97
1.75
1.88
0.05
0.13
7.62
7.95
5.11
5.28
5.13
5.21
0.51
0.64
0
4
0.20
0.23
0.36
0.43
0
12
0
12
MIN
MAX
2.03
1.98
0.25
8.26
5.38
5.33
0.76
8
0.25
0.51
15
15
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
Drawing No. C04-056
1997-2013 Microchip Technology Inc.
DS30561C-page 117
PIC12C67X
8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
W
T
D
2
1
n
U
A
A2
L
A1
c
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Top of Body to Seating Plane
Standoff
Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
Lid Length
Lid Width
*Controlling Parameter
JEDC Equivalent: MS-015
Drawing No. C04-083
DS30561C-page 118
A
A2
A1
E1
D
L
c
B1
B
eB
W
T
U
MIN
.145
.103
.025
.280
.510
.130
.008
.050
.016
.296
.161
.440
.260
INCHES*
NOM
8
.100
.165
.123
.035
.290
.520
.140
.010
.055
.018
.310
.166
.450
.270
MAX
.185
.143
.045
.300
.530
.150
.012
.060
.020
.324
.171
.460
.280
MILLIMETERS
NOM
8
2.54
3.68
4.19
2.62
3.12
0.64
0.89
7.11
7.37
12.95
13.21
3.30
3.56
0.20
0.25
1.27
1.40
0.41
0.46
7.52
7.87
4.09
4.22
11.18
11.43
6.60
6.86
MIN
MAX
4.70
3.63
1.14
7.62
13.46
3.81
0.30
1.52
0.51
8.23
4.34
11.68
7.11
1997-2013 Microchip Technology Inc.
PIC12C67X
APPENDIX A: COMPATIBILITY
To convert code written for PIC16C5X to PIC12C67X,
the user should take the following steps:
1.
2.
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to 0000h.
1997-2013 Microchip Technology Inc.
APPENDIX B: CODE FOR
ACCESSING EEPROM
DATA MEMORY
Please refer to our web site at www.microchip.com for
code availability.
APPENDIX C: REVISION HISTORY
Revision C (January 2013)
Added a note to each package outline drawing.
DS30561C-page 119
PIC12C67X
NOTES:
DS30561C-page 120
1997-2013 Microchip Technology Inc.
PIC12C67X
INDEX
A
A/D
Accuracy/Error ............................................................ 51
ADCON0 Register....................................................... 45
ADIF bit ....................................................................... 47
Analog Input Model Block Diagram............................. 48
Analog-to-Digital Converter......................................... 45
Configuring Analog Port Pins...................................... 49
Configuring the Interrupt ............................................. 47
Configuring the Module............................................... 47
Connection Considerations......................................... 51
Conversion Clock........................................................ 49
Conversions ................................................................ 50
Converter Characteristics ......................................... 105
Delays ......................................................................... 48
Effects of a Reset........................................................ 51
Equations .................................................................... 48
Flowchart of A/D Operation......................................... 52
GO/DONE bit .............................................................. 47
Internal Sampling Switch (Rss) Impedence ................ 48
Operation During Sleep .............................................. 51
Sampling Requirements.............................................. 48
Sampling Time ............................................................ 48
Source Impedence...................................................... 48
Time Delays ................................................................ 48
Transfer Function........................................................ 51
Absolute Maximum Ratings ................................................ 89
ADDLW Instruction ............................................................. 72
ADDWF Instruction ............................................................. 72
ADIE bit ............................................................................... 18
ADIF bit ............................................................................... 19
ADRES Register ..................................................... 13, 45, 47
ALU ....................................................................................... 7
ANDLW Instruction ............................................................. 72
ANDWF Instruction ............................................................. 72
Application Notes
AN546 ......................................................................... 45
AN556 ......................................................................... 22
Architecture
Harvard ......................................................................... 7
Overview ....................................................................... 7
von Neumann................................................................ 7
Assembler
MPASM Assembler..................................................... 83
B
BCF Instruction ................................................................... 73
Bit Manipulation .................................................................. 70
Block Diagrams
Analog Input Model ..................................................... 48
On-Chip Reset Circuit ................................................. 57
Timer0......................................................................... 39
Timer0/WDT Prescaler ............................................... 42
Watchdog Timer.......................................................... 65
BSF Instruction ................................................................... 73
BTFSC Instruction............................................................... 73
BTFSS Instruction ............................................................... 74
1997-2013 Microchip Technology Inc.
C
C bit .................................................................................... 15
CAL0 bit .............................................................................. 21
CAL1 bit .............................................................................. 21
CAL2 bit .............................................................................. 21
CAL3 bit .............................................................................. 21
CALFST bit ......................................................................... 21
CALL Instruction ................................................................. 74
CALSLW bit ........................................................................ 21
Carry bit ................................................................................ 7
Clocking Scheme................................................................ 10
CLRF Instruction................................................................. 74
CLRW Instruction................................................................ 74
CLRWDT Instruction........................................................... 75
Code Examples
Changing Prescaler (Timer0 to WDT) ........................ 43
Changing Prescaler (WDT to Timer0) ........................ 43
Indirect Addressing..................................................... 23
Code Protection ............................................................ 53, 67
COMF Instruction................................................................ 75
Computed GOTO................................................................ 22
Configuration Bits ............................................................... 53
D
DC and AC Characteristics............................................... 109
DC bit.................................................................................. 15
DC Characteristics
PIC12C671/672, PIC12CE673/674 ............................ 92
PIC12LC671/672, PIC12LCE673/674 ........................ 94
DECF Instruction ................................................................ 75
DECFSZ Instruction............................................................ 75
Development Support ..................................................... 3, 83
Digit Carry bit ........................................................................ 7
Direct Addressing ............................................................... 23
E
EEPROM Peripheral Operation .......................................... 33
Electrical Characteristics - PIC12C67X .............................. 89
Errata .................................................................................... 2
External Brown-out Protection Circuit................................. 61
External Power-on Reset Circuit......................................... 61
F
Family of Devices ................................................................. 4
Features ............................................................................... 1
FSR Register .......................................................... 13, 14, 23
G
General Description .............................................................. 3
GIE bit................................................................................. 62
GOTO Instruction................................................................ 76
GPIF bit .............................................................................. 64
GPIO............................................................................. 25, 59
GPIO Register .................................................................... 13
GPPU bit............................................................................. 16
DS30561C-page 121
PIC12C67X
I
K
I/O Interfacing...................................................................... 25
I/O Ports .............................................................................. 25
I/O Programming Considerations........................................ 31
ID Locations ........................................................................ 53
INCF Instruction .................................................................. 76
INCFSZ Instruction.............................................................. 76
In-Circuit Serial Programming ....................................... 53, 67
INDF Register ............................................................... 14, 23
Indirect Addressing ............................................................. 23
Initialization Conditions for All Registers ............................. 59
Instruction Cycle.................................................................. 10
Instruction Flow/Pipelining .................................................. 10
Instruction Format ............................................................... 69
Instruction Set
ADDLW ....................................................................... 72
ADDWF ....................................................................... 72
ANDLW ....................................................................... 72
ANDWF ....................................................................... 72
BCF ............................................................................. 73
BSF ............................................................................. 73
BTFSC ........................................................................ 73
BTFSS ........................................................................ 74
CALL ........................................................................... 74
CLRF........................................................................... 74
CLRW ......................................................................... 74
CLRWDT..................................................................... 75
COMF ......................................................................... 75
DECF .......................................................................... 75
DECFSZ...................................................................... 75
GOTO ......................................................................... 76
INCF............................................................................ 76
INCFSZ ....................................................................... 76
IORLW ........................................................................ 76
IORWF ........................................................................ 77
MOVF.......................................................................... 77
MOVLW ...................................................................... 77
MOVWF ...................................................................... 77
NOP ............................................................................ 78
OPTION ...................................................................... 78
RETFIE ....................................................................... 78
RETLW ....................................................................... 78
RETURN ..................................................................... 79
RLF ............................................................................. 79
RRF............................................................................. 79
SLEEP ........................................................................ 79
SUBLW ....................................................................... 80
SUBWF ....................................................................... 80
SWAPF ....................................................................... 81
TRIS ............................................................................ 81
XORLW ....................................................................... 81
XORWF....................................................................... 81
Section ........................................................................ 69
INTCON Register ................................................................ 17
INTEDG bit.......................................................................... 16
Internal Sampling Switch (Rss) Impedence ........................ 48
Interrupts ............................................................................. 53
A/D .............................................................................. 62
GP2/INT ...................................................................... 62
GPIO Port ................................................................... 62
Section ........................................................................ 62
TMR0 .......................................................................... 64
TMR0 Overflow ........................................................... 62
IORLW Instruction............................................................... 76
IORWF Instruction............................................................... 77
IRP bit ................................................................................. 15
KeeLoq Evaluation and Programming Tools ................... 86
DS30561C-page 122
L
Loading of PC ..................................................................... 22
M
MCLR............................................................................ 56, 59
Memory
Data Memory .............................................................. 11
Program Memory ........................................................ 11
Register File Map - PIC12CE67X ............................... 12
MOVF Instruction................................................................ 77
MOVLW Instruction............................................................. 77
MOVWF Instruction ............................................................ 77
MPLAB Integrated Development Environment Software.... 83
N
NOP Instruction .................................................................. 78
O
Opcode ............................................................................... 69
OPTION Instruction ............................................................ 78
OPTION Register................................................................ 16
Orthogonal ............................................................................ 7
OSC selection..................................................................... 53
OSCCAL Register............................................................... 21
Oscillator
EXTRC ....................................................................... 58
HS............................................................................... 58
INTRC......................................................................... 58
LP ............................................................................... 58
XT ............................................................................... 58
Oscillator Configurations..................................................... 54
Oscillator Types
EXTRC ....................................................................... 54
HS............................................................................... 54
INTRC......................................................................... 54
LP ............................................................................... 54
XT ............................................................................... 54
P
Package Marking Information ........................................... 115
Packaging Information ...................................................... 115
Paging, Program Memory................................................... 22
PCL..................................................................................... 70
PCL Register .......................................................... 13, 14, 22
PCLATH.............................................................................. 59
PCLATH Register ................................................... 13, 14, 22
PCON Register ............................................................. 20, 58
PD bit ............................................................................ 15, 56
PICDEM-1 Low-Cost PIC MCU Demo Board ..................... 85
PICDEM-2 Low-Cost PIC16CXX Demo Board ................... 85
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 85
PICSTART Plus Entry Level Development System ......... 85
PIE1 Register...................................................................... 18
Pinout Description - PIC12CE67X ........................................ 9
PIR1 Register ..................................................................... 19
POP .................................................................................... 22
POR .................................................................................... 58
Oscillator Start-up Timer (OST) ............................ 53, 58
Power Control Register (PCON)................................. 58
Power-on Reset (POR)................................... 53, 58, 59
Power-up Timer (PWRT) ...................................... 53, 58
Power-Up-Timer (PWRT) ........................................... 58
Time-out Sequence .................................................... 58
Time-out Sequence on Power-up ............................... 60
TO............................................................................... 56
Power.................................................................................. 56
1997-2013 Microchip Technology Inc.
PIC12C67X
Power-down Mode (SLEEP) ............................................... 66
Prescaler, Switching Between Timer0 and WDT ................ 43
PRO MATE II Universal Programmer .............................. 85
Program Branches ................................................................ 7
Program Memory
Paging......................................................................... 22
Program Verification ........................................................... 67
PS0 bit ................................................................................ 16
PS1 bit ................................................................................ 16
PS2 bit ................................................................................ 16
PSA bit ................................................................................ 16
PUSH .................................................................................. 22
R
RC Oscillator ....................................................................... 55
Read Modify Write .............................................................. 31
Read-Modify-Write .............................................................. 31
Register File ........................................................................ 11
Registers
Map
PIC12C67X ......................................................... 12
Reset Conditions......................................................... 59
Reset............................................................................. 53, 56
Reset Conditions for Special Registers .............................. 59
RETFIE Instruction.............................................................. 78
RETLW Instruction .............................................................. 78
RETURN Instruction ........................................................... 79
RLF Instruction.................................................................... 79
RP0 bit .......................................................................... 11, 15
RP1 bit ................................................................................ 15
RRF Instruction ................................................................... 79
S
SEEVAL Evaluation and Programming System ............... 86
Services
One-Time-Programmable (OTP) .................................. 5
Quick-Turnaround-Production (QTP)............................ 5
Serialized Quick-Turnaround Production (SQTP)......... 5
SFR ..................................................................................... 70
SFR As Source/Destination ................................................ 70
SLEEP .......................................................................... 53, 56
SLEEP Instruction ............................................................... 79
Software Simulator (MPLAB-SIM) ...................................... 84
Special Features of the CPU .............................................. 53
Special Function Register
PIC12C67X ................................................................. 13
Special Function Registers ................................................. 70
Special Function Registers, Section ................................... 12
Stack ................................................................................... 22
Overflows .................................................................... 22
Underflow.................................................................... 22
STATUS Register ............................................................... 15
SUBLW Instruction.............................................................. 80
SUBWF Instruction ............................................................. 80
SWAPF Instruction.............................................................. 81
T
T0CS bit.............................................................................. 16
TAD ..................................................................................... 49
Timer0
RTCC.......................................................................... 59
Timers
Timer0
Block Diagram .................................................... 39
External Clock .................................................... 41
External Clock Timing......................................... 41
Increment Delay ................................................. 41
Interrupt .............................................................. 39
Interrupt Timing .................................................. 40
Prescaler ............................................................ 42
Prescaler Block Diagram .................................... 42
Section ............................................................... 39
Switching Prescaler Assignment ........................ 43
Synchronization .................................................. 41
T0CKI ................................................................. 41
T0IF .................................................................... 64
Timing................................................................. 39
TMR0 Interrupt ................................................... 64
Timing Diagrams
A/D Conversion ........................................................ 106
CLKOUT and I/O ...................................................... 102
External Clock Timing............................................... 100
Time-out Sequence .................................................... 60
Timer0 ........................................................................ 39
Timer0 Interrupt Timing .............................................. 40
Timer0 with External Clock......................................... 41
Wake-up from Sleep via Interrupt............................... 67
TO bit .................................................................................. 15
TOSE bit ............................................................................. 16
TRIS Instruction .................................................................. 81
TRIS Register ......................................................... 14, 25, 31
Two’s Complement ............................................................... 7
U
UV Erasable Devices............................................................ 5
W
W Register
ALU............................................................................... 7
Wake-up from SLEEP......................................................... 66
Watchdog Timer (WDT).................................... 53, 56, 59, 65
WDT ................................................................................... 59
Block Diagram ............................................................ 65
Period ......................................................................... 65
Programming Considerations ..................................... 65
Timeout....................................................................... 59
WWW, On-Line Support ....................................................... 2
X
XORLW Instruction ............................................................. 81
XORWF Instruction............................................................. 81
Z
Z bit..................................................................................... 15
Zero bit ................................................................................. 7
1997-2013 Microchip Technology Inc.
DS30561C-page 123
PIC12C67X
NOTES:
DS30561C-page 124
1997-2013 Microchip Technology Inc.
PIC16XXXXXX FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
1997-2013 Microchip Technology Inc.
DS30561C-page 125
PIC16XXXXXX FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: PIC16xxxxxx family
Literature Number: DS30561C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS30561C-page 126
1997-2013 Microchip Technology Inc.
PIC12C67X
PIC12C67X PRODUCT IDENTIFICATION SYSTEM
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
Package:
P
JW
SM
= 300 mil PDIP
= 300 mil Windowed Ceramic Side Brazed
= 208 mil SOIC
Temperature
Range:
I
E
= 0C to +70C
= -40C to +85C
= -40C to +125C
Frequency
Range:
04
10
= 4 MHz/200 kHz
= 10 MHz
Device
PIC12CE673
PIC12CE674
PIC12LCE673
PIC12LCE674
PIC12C671
PIC12C672
PIC12C671T (Tape & reel for SOIC only)
PIC12C672T (Tape & reel for SOIC only)
PIC12LC671
PIC12LC672
PIC12LC671T (Tape & reel for SOIC only)
PIC12LC672T (Tape & reel for SOIC only)
a)
PIC12CE673-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
b)
PIC12CE673-04I/P
Industrial Temp., PDIP
package, 4 MHz, normal
VDD limits
c)
PIC12CE673-10I/P
Industrial Temp.,
PDIP package, 10 MHz,
normal VDD limits
d)
PIC12C671-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
e)
PIC12C671-04I/SM
Industrial Temp., SOIC
package, 4 MHz, normal
VDD limits
f)
PIC12C671-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement
of each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
Your local Microchip sales office
The Microchip Worldwide Site (www.microchip.com)
1997-2013 Microchip Technology Inc.
DS30561C-page 127
PIC12C67X
DS30561C-page 128
1997-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1997-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769287
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
1997-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS30561C-page 129
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
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Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
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Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
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Tel: 49-89-627-144-0
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Tel: 678-957-9614
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Tel: 774-760-0087
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Tel: 630-285-0071
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Tel: 949-462-9523
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Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
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Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS30561C-page 130
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
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