PIC12C5XX
8-Pin, 8-Bit CMOS Microcontrollers
Devices included in this Data Sheet:
Peripheral Features:
• PIC12C508 • PIC12C508A
• PIC12C509 • PIC12C509A
• PIC12CR509A
• PIC12CE518
• PIC12CE519
PIC12C508
512 x 12
25
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Power-On Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• 1,000,000 erase/write cycle EEPROM data
memory
• EEPROM data retention > 40 years
• Power saving SLEEP mode
• Wake-up from SLEEP on pin change
• Internal weak pull-ups on I/O pins
• Internal pull-up on MCLR pin
• Selectable oscillator options:
- INTRC: Internal 4 MHz RC oscillator
- EXTRC: External low-cost RC oscillator
- XT:
Standard crystal/resonator
- LP:
Power saving, low frequency crystal
PIC12C508A
512 x 12
25
CMOS Technology:
PIC12C509
1024 x 12
41
PIC12C509A
1024 x 12
41
PIC12CE518
512 x 12
25
16
PIC12CE519
1024 x 12
41
16
Note: Throughout this data sheet PIC12C5XX
refers to the PIC12C508, PIC12C509,
PIC12C508A, PIC12C509A,
PIC12CR509A, PIC12CE518 and
PIC12CE519. PIC12CE5XX refers to
PIC12CE518 and PIC12CE519.
High-Performance RISC CPU:
• Only 33 single word instructions to learn
• All instructions are single cycle (1 µs) except for
program branches which are two-cycle
• Operating speed: DC - 4 MHz clock input
DC - 1 µs instruction cycle
Memory
Device
PIC12CR509A
EPROM
Program
ROM
Program
1024 x 12
•
•
•
•
•
RAM
Data
EEPROM
Data
41
12-bit wide instructions
8-bit wide data path
Seven special function hardware registers
Two-level deep hardware stack
Direct, indirect and relative addressing modes for
data and instructions
• Internal 4 MHz RC oscillator with programmable
calibration
• In-circuit serial programming
1999 Microchip Technology Inc.
• Low power, high speed CMOS EPROM/ROM
technology
• Fully static design
• Wide operating voltage range
• Wide temperature range:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Low power consumption
- < 2 mA @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 KHz
- < 1 µA typical standby current
DS40139E-page 1
PIC12C5XX
Pin Diagram - PIC12C508/509
PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed
1
2
GP4/OSC2
GP3/MCLR/VPP
3
PIC12C508
PIC12C509
VDD
GP5/OSC1/CLKIN
4
8
VSS
7
GP0
6
GP1
5
GP2/T0CKI
Pin Diagram - PIC12C508A/509A,
PIC12CE518/519
PDIP, 150 & 208 mil SOIC, Windowed CERDIP
1
2
GP4/OSC2
GP3/MCLR/VPP
3
4
PIC12C508A
PIC12C509A
PIC12CE518
PIC12CE519
VDD
GP5/OSC1/CLKIN
8
VSS
7
GP0
6
GP1
5
GP2/T0CKI
8
VSS
7
GP0
6
GP1
5
GP2/T0CKI
Pin Diagram - PIC12CR509A
PDIP, 150 & 208 mil SOIC
1
2
GP4/OSC2
GP3/MCLR/VPP
3
4
PIC12CR509A
VDD
GP5/OSC1/CLKIN
Device Differences
Device
Voltage
Range
Oscillator
Oscillator
Calibration2
(Bits)
Process
Technology
(Microns)
PIC12C508A
3.0-5.5
See Note 1
6
0.7
PIC12LC508A
2.5-5.5
See Note 1
6
0.7
PIC12C508
2.5-5.5
See Note 1
4
0.9
PIC12C509A
3.0-5.5
See Note 1
6
0.7
PIC12LC509A
2.5-5.5
See Note 1
6
0.7
PIC12C509
2.5-5.5
See Note 1
4
0.9
PIC12CR509A
2.5-5.5
See Note 1
6
0.7
PIC12CE518
3.0-5.5
-
6
0.7
PIC12LCE518
2.5-5.5
-
6
0.7
PIC12CE519
3.0-5.5
-
6
0.7
PIC12LCE519
2.5-5.5
-
6
0.7
Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, please verify
oscillator characteristics in your application.
Note 2: See Section 7.2.5 for OSCCAL implementation differences.
DS40139E-page 2
1999 Microchip Technology Inc.
PIC12C5XX
TABLE OF CONTENTS
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
General Description............................................................................................................................................... 4
PIC12C5XX Device Varieties ................................................................................................................................ 7
Architectural Overview........................................................................................................................................... 9
Memory Organization .......................................................................................................................................... 13
I/O Port ................................................................................................................................................................ 21
Timer0 Module and TMR0 Register .................................................................................................................... 25
EEPROM Peripheral Operation........................................................................................................................... 29
Special Features of the CPU ............................................................................................................................... 35
Instruction Set Summary ..................................................................................................................................... 47
Development Support.......................................................................................................................................... 59
Electrical Characteristics - PIC12C508/PIC12C509............................................................................................ 65
DC and AC Characteristics - PIC12C508/PIC12C509 ........................................................................................ 75
Electrical Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/
PIC12CE518/PIC12CE519/
PIC12LCE518/PIC12LCE519/PIC12LCR509A ................................................................................................... 79
14.0 DC and AC Characteristics
PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/
PIC12LCE518/PIC12LCE519/ PIC12LCR509A .................................................................................................. 93
15.0 Packaging Information......................................................................................................................................... 99
Index ........................................................................................................................................................................... 105
PIC12C5XX Product Identification System ................................................................................................................ 109
Sales and Support: ..................................................................................................................................................... 109
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner
of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet
(include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time
to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any
information that is missing or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
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We appreciate your assistance in making this a better document.
1999 Microchip Technology Inc.
DS40139E-page 3
PIC12C5XX
1.0
GENERAL DESCRIPTION
The PIC12C5XX from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static,
EEPROM/EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are
single cycle (1 µs) except for program branches
which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide
instructions are highly symmetrical resulting in 2:1
code compression over other 8-bit microcontrollers in
its class. The easy to use and easy to remember
instruction set reduces development time significantly.
The PIC12C5XX products are equipped with special
features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset
Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose
from, including INTRC internal oscillator mode and the
power-saving LP (Low Power) oscillator mode. Power
saving SLEEP mode, Watchdog Timer and code
protection features also improve system cost, power
and reliability.
1.1
Applications
The PIC12C5XX series fits perfectly in applications
ranging from personal care appliances and security
systems to low-power remote transmitters/receivers.
The EPROM technology makes customizing application programs (transmitter codes, appliance settings,
receiver frequencies, etc.) extremely fast and convenient, while the EEPROM data memory technology
allows for the changing of calibration factors and security codes. The small footprint packages, for through
hole or surface mounting, make this microcontroller
series perfect for applications with space limitations.
Low-cost, low-power, high performance, ease of use
and I/O flexibility make the PIC12C5XX series very versatile even in areas where no microcontroller use has
been considered before (e.g., timer functions, replacement of “glue” logic and PLD’s in larger systems, coprocessor applications).
The PIC12C5XX are available in the cost-effective
One-Time-Programmable (OTP) versions which are
suitable for production in any volume. The customer
can take full advantage of Microchip’s price leadership
in OTP microcontrollers while benefiting from the OTP’s
flexibility.
The PIC12C5XX products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, fuzzy logic support tools,
a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM
PC and compatible machines.
DS40139E-page 4
1999 Microchip Technology Inc.
PIC12C5XX
TABLE 1-1:
PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES
PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674
Clock
Memory
Peripherals
Features
Maximum
Frequency
of Operation
(MHz)
4
4
4
4
4
10
10
10
10
EPROM
Program
Memory
512 x 12
1024 x 12
1024 x 12
(ROM)
512 x 12
1024 x 12
1024 x 14
2048 x 14
1024 x 14
2048 x 14
RAM Data
Memory
(bytes)
25
41
41
25
41
128
128
128
128
EEPROM
Data Memory
(bytes)
—
—
—
16
16
—
—
16
16
Timer
Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
A/D Converter (8-bit)
Channels
—
—
—
—
—
4
4
4
4
Wake-up
from SLEEP
on pin
change
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt
Sources
—
—
—
4
4
4
4
I/O Pins
5
5
5
5
5
5
5
5
5
Input Pins
1
1
1
1
1
1
1
1
1
Internal
Pull-ups
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit
Serial
Programming
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Number of
Instructions
33
33
33
33
33
35
35
35
35
Packages
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW
8-pin DIP,
JW
All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.
1999 Microchip Technology Inc.
DS40139E-page 5
PIC12C5XX
NOTES:
DS40139E-page 6
1999 Microchip Technology Inc.
PIC12C5XX
2.0
PIC12C5XX DEVICE VARIETIES
A variety of packaging options are available.
Depending
on
application
and
production
requirements, the proper device option can be
selected using the information in this section. When
placing orders, please use the PIC12C5XX Product
Identification System at the back of this data sheet to
specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in ceramic side
brazed package, is optimal for prototype development
and pilot programs.
The UV erasable version can be erased and
reprogrammed to any of the configuration modes.
Note:
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
Microchip’s PICSTART PLUS and PRO MATE programmers all support programming of the PIC12C5XX.
Third party programmers also are available; refer to the
Microchip Third Party Guide for a list of sources.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates or small volume applications.
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please contact your local Microchip Technology sales office for
more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
2.5
Read Only Memory (ROM) Device
Microchip offers masked ROM to give the customer a
low cost option for high volume, mature products.
The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1999 Microchip Technology Inc.
DS40139E-page 7
PIC12C5XX
NOTES:
DS40139E-page 8
1999 Microchip Technology Inc.
PIC12C5XX
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12C5XX family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC12C5XX uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (1µs @ 4MHz) except for
program branches.
The table below lists program memory (EPROM), data
memory (RAM), ROM memory, and non-volatile
(EEPROM) for each device.
EPROM
Program
ROM
Program
RAM
Data
PIC12C508
512 x 12
25
PIC12C509
1024 x 12
41
PIC12C508A
512 x 12
25
PIC12C509A
1024 x 12
41
PIC12CR509A
1024 x 12
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
Memory
Device
The PIC12C5XX device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
EEPROM
Data
41
PIC12CE518
512 x 12
25 x 8
16 x 8
PIC12CE519
1024 x 12
41 x 8
16 x 8
The PIC12C5XX can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC12C5XX has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC12C5XX simple yet efficient.
In addition, the learning curve is reduced significantly.
1999 Microchip Technology Inc.
DS40139E-page 9
PIC12C5XX
PIC12C5XX BLOCK DIAGRAM
12
GP0
GP1
GP2/T0CKI
GP3/MCLR/VPP
GP4/OSC2
GP5/OSC1/CLKIN
RAM
25 x 8 or
41 x 8
File
Registers
STACK1
STACK2
12
RAM Addr
9
Addr MUX
Instruction reg
Direct Addr
5
5-7
Indirect
Addr
FSR reg
STATUS reg
8
3
OSC1/CLKIN
OSC2
Timing
Generation
Internal RC
OSC
Power-on
Reset
Watchdog
Timer
16 X 8
EEPROM
Data
Memory
PIC12CE5XX
Only
MUX
Device Reset
Timer
Instruction
Decode &
Control
GPIO
SDA
Program
Bus
8
Data Bus
Program Counter
ROM/EPROM
512 x 12 or
1024 x 12
Program
Memory
SCL
FIGURE 3-1:
ALU
8
W reg
Timer0
MCLR
VDD, VSS
DS40139E-page 10
1999 Microchip Technology Inc.
PIC12C5XX
TABLE 3-1:
PIC12C5XX PINOUT DESCRIPTION
DIP
Pin #
SOIC
Pin #
I/O/P
Type
GP0
7
7
I/O
TTL/ST Bi-directional I/O port/ serial programming data. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
GP1
6
6
I/O
TTL/ST Bi-directional I/O port/ serial programming clock. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
Name
Buffer
Type
ST
Description
GP2/T0CKI
5
5
I/O
GP3/MCLR/VPP
4
4
I
Bi-directional I/O port. Can be configured as T0CKI.
GP4/OSC2
3
3
I/O
GP5/OSC1/CLKIN
2
2
I/O
VDD
1
1
P
—
Positive supply for logic and I/O pins
VSS
8
8
P
—
Ground reference for logic and I/O pins
TTL/ST Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation
or the device will enter programming mode. Can be
software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. Weak pull-up
always on if configured as MCLR. ST when in MCLR
mode.
TTL
Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, GPIO in other modes).
TTL/ST Bidirectional IO port/oscillator crystal input/external
clock source input (GPIO in Internal RC mode only,
OSC1 in all other oscillator modes). TTL input when
GPIO, ST input in external RC oscillator mode.
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input
1999 Microchip Technology Inc.
DS40139E-page 11
PIC12C5XX
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
EXAMPLE 3-1:
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
SUB_1
4. BSF
GPIO, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40139E-page 12
1999 Microchip Technology Inc.
PIC12C5XX
MEMORY ORGANIZATION
PIC12C5XX memory is organized into program memory and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one STATUS register bit. For the PIC12C509, PIC12C509A,
PICCR509A and PIC12CE519 with a data memory
register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
4.1
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK
PC
12
CALL, RETLW
Stack Level 1
Stack Level 2
Reset Vector (note 1)
0000h
Program Memory Organization
The PIC12C5XX devices have a 12-bit Program
Counter (PC) capable of addressing a 2K x 12
program memory space.
Only the first 512 x 12 (0000h-01FFh) for the
PIC12C508, PIC12C508A and PIC12CE518 and 1K x
12 (0000h-03FFh) for the PIC12C509, PIC12C509A,
PIC12CR509A, and PIC12CE519 are physically
implemented. Refer to Figure 4-1. Accessing a
location above these boundaries will cause a wraparound within the first 512 x 12 space (PIC12C508,
PIC12C508A and PIC12CE518) or 1K x 12 space
(PIC12C509, PIC12C509A, PIC12CR509A and
PIC12CE519). The effective reset vector is at 000h,
(see Figure 4-1). Location 01FFh (PIC12C508,
PIC12C508A and PIC12CE518) or location 03FFh
(PIC12C509, PIC12C509A, PIC12CR509A and
PIC12CE519) contains the internal clock oscillator
calibration value. This value should never be
overwritten.
1999 Microchip Technology Inc.
On-chip Program
Memory
User Memory
Space
4.0
512 Word
01FFh
0200h
On-chip Program
Memory
1024 Word
03FFh
0400h
7FFh
Note 1: Address 0000h becomes the
effective reset vector. Location
01FFh (PIC12C508, PIC12C508A,
PIC12CE518) or location 03FFh
(PIC12C509, PIC12C509A,
PIC12CR509A, PIC12CE519) contains the MOVLW XX INTERNAL RC
oscillator calibration value.
DS40139E-page 13
PIC12C5XX
4.2
Data Memory Organization
FIGURE 4-2:
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.
PIC12C508, PIC12C508A AND
PIC12CE518 REGISTER FILE
MAP
File Address
00h
INDF (1)
The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.
01h
TMR0
The general purpose registers are used for data and
control information under command of the instructions.
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
07h
For the PIC12C508, PIC12C508A and PIC12CE518,
the register file is composed of 7 special function
registers and 25 general purpose registers (Figure 42).
General
Purpose
Registers
For the PIC12C509, PIC12C509A, PIC12CR509A,
and PIC12CE519 the register file is composed of 7
special function registers, 25 general purpose
registers, and 16 general purpose registers that may
be addressed using a banking scheme (Figure 4-3).
4.2.1
1Fh
Note
GENERAL PURPOSE REGISTER FILE
1:
Not a physical register. See Section 4.8
The general purpose register file is accessed either
directly or indirectly through the file select register FSR
(Section 4.8).
FIGURE 4-3:
PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519 REGISTER FILE MAP
FSR
00
01
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
20h
Addresses map
back to
addresses
in Bank 0.
07h
General
Purpose
Registers
2Fh
0Fh
30h
10h
General
Purpose
Registers
3Fh
1Fh
Bank 0
Note 1:
DS40139E-page 14
General
Purpose
Registers
Bank 1
Not a physical register. See Section 4.8
1999 Microchip Technology Inc.
PIC12C5XX
4.2.2
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control
the operation of the device (Table 4-1).
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Name
Bit 7
Bit 6
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets(2)
--11 1111
--11 1111
OPTION
Contains control bits to configure Timer0, Timer0/WDT
prescaler, wake-up on change, and weak pull-ups
1111 1111
1111 1111
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
uuuu uuuu
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Low order 8 bits of PC
1111 1111
1111 1111
03h
STATUS
0001 1xxx
q00q quuu(3)
04h
FSR
(PIC12C508/
PIC12C508A/
PIC12C518)
Indirect data memory address pointer
111x xxxx
111u uuuu
04h
FSR
(PIC12C509/
PIC12C509A/
PIC12CR509A/
PIC12CE519) Indirect data memory address pointer
110x xxxx
11uu uuuu
05h
OSCCAL
(PIC12C508/
PIC12C509)
CAL3
CAL2
CAL1
CAL0
—
—
—
—
0111 ----
uuuu ----
05h
OSCCAL
(PIC12C508A/
PIC12C509A/
PIC12CE518/
PIC12CE519/
PIC12CR509A)
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
1000 00--
uuuu uu--
06h
GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
06h
GPIO
(PIC12CE518/
PIC12CE519)
SCL
SDA
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
N/A
N/A
TRIS
GPWUF
—
PA0
TO
PD
Z
DC
C
Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as ’0’ (if applicable)
x = unknown, u = unchanged, q = see the tables in Section 8.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6
for an explanation of how to access these bits.
2: Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.
3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.
1999 Microchip Technology Inc.
DS40139E-page 15
PIC12C5XX
4.3
STATUS Register
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bit for
program memories larger than 512 words.
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Instruction Set Summary.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
FIGURE 4-4:
R/W-0
GPWUF
bit7
STATUS REGISTER (ADDRESS:03h)
R/W-0
—
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
6
5
4
3
2
1
R/W-x
C
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
GPWUF: GPIO reset bit
1 = Reset due to wake-up from SLEEP on pin change
0 = After power up or other reset
bit 6:
Unimplemented
bit 5:
PA0: Program page preselect bits
1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519
0 = Page 0 (000h - 1FFh) - PIC12C5XX
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF
SUBWF
1 = A carry occurred
1 = A borrow did not occur
0 = A carry did not occur
0 = A borrow occurred
DS40139E-page 16
RRF or RLF
Load bit with LSB or MSB, respectively
1999 Microchip Technology Inc.
PIC12C5XX
4.4
OPTION Register
Note:
If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin; i.e., note that TRIS overrides
OPTION control of GPPU and GPWU.
Note:
If the T0CS bit is set to ‘1’, GP2 is forced to
be an input even if TRIS GP2 = ‘0’.
The OPTION register is a 8-bit wide, write-only
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION bits.
FIGURE 4-5:
OPTION REGISTER
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
6
5
4
3
2
1
bit7
bit 7:
GPWU: Enable wake-up on pin change (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 6:
GPPU: Enable weak pull-ups (GP0, GP1, GP3)
1 = Disabled
0 = Enabled
bit 5:
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Transition on internal instruction cycle clock, Fosc/4
bit 4:
T0SE: Timer0 source edge select bit
1 = Increment on high to low transition on the T0CKI pin
0 = Increment on low to high transition on the T0CKI pin
bit 3:
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0:
PS2:PS0: Prescaler rate select bits
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1999 Microchip Technology Inc.
bit0
W = Writable bit
U = Unimplemented bit
- n = Value at POR reset
Reference Table 4-1 for
other resets.
DS40139E-page 17
PIC12C5XX
4.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains four to
six bits for calibration. Increasing the cal value
increases the frequency. See Section 7.2.5 for more
information on the internal oscillator.
FIGURE 4-6:
OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508 AND PIC12C509
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
U-0
U-0
CAL3
CAL2
CAL1
CAL0
—
—
—
—
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-4: CAL: Calibration
bit 3-0: Unimplemented: Read as ’0’
FIGURE 4-7:
OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508A/C509A/CR509A/12CE518/
12CE519
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: CAL: Calibration
bit 1-0: Unimplemented: Read as ’0’
DS40139E-page 18
1999 Microchip Technology Inc.
PIC12C5XX
4.6
Program Counter
4.6.1
EFFECTS OF RESET
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the oscillator calibration instruction. After
executing MOVLW XX, the PC will roll over to location
00h, and begin executing user code.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC. Bit 5 of the STATUS register
provides page information to bit 9 of the PC (Figure 48).
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is preselected.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC
does not come from the instruction word, but is always
cleared (Figure 4-8).
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5.
Note:
Because PC is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any program memory page (512 words long).
FIGURE 4-8:
LOADING OF PC
BRANCH INSTRUCTIONS PIC12C5XX
GOTO Instruction
11 10
9
8
7
0
PC
Instruction Word
0
CALL or Modify PCL Instruction
8
7
PIC12C5XX devices have a 12-bit wide L.I.F.O.
hardware push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
Note 2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
STATUS
9
Stack
Note 1: There are no STATUS bits to indicate
stack overflows or stack underflow conditions.
PA0
11 10
4.7
Upon any reset, the contents of the stack remain
unchanged, however the program counter (PCL) will
also be reset to 0.
PCL
7
Therefore, upon a RESET, a GOTO instruction will
automatically cause the program to jump to page 0
until the value of the page bits is altered.
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
7
0
STATUS
1999 Microchip Technology Inc.
DS40139E-page 19
PIC12C5XX
4.8
Indirect Data Addressing; INDF and
FSR Registers
EXAMPLE 4-2:
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 4-1:
INDIRECT ADDRESSING
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
•
•
•
•
Register file 07 contains the value 10h
Register file 08 contains the value 0Ah
Load the value 07 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 08)
• A read of the INDR register now will return the
value of 0Ah.
:
;YES, continue
The FSR is a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
The FSR bits are used to select data memory
addresses 00h to 1Fh.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-9:
NEXT
movlw
movwf
clrf
incf
btfsc
goto
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
PIC12C508/PIC12C508A/PIC12CE518:
Does not
use banking. FSR are unimplemented and read
as '1's.
PIC12C509/PIC12C509A/PIC12CR509A/
PIC12CE519: Uses FSR. Selects between bank 0
and bank 1. FSR is unimplemented, read as '1’ .
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
6 5
4
bank select
location select
Indirect Addressing
(opcode)
0
6
5
4
bank
00
(FSR)
0
location select
01
00h
Addresses
map back to
addresses
in Bank 0.
Data
Memory(1)
0Fh
10h
1Fh
Bank 0
3Fh
Bank 1(2)
Note 1: For register map detail see Section 4.2.
Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519.
DS40139E-page 20
1999 Microchip Technology Inc.
PIC12C5XX
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers are all
set. See Section 7.0 for SCL and SDA description for
PIC12CE5XX.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O’s to
alternate functions. When acting as alternate functions
the pins will read as ‘0’ during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with wake-up on change. The wake-up on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, weak pullup is always on and wake-up on change for this pin is
not enabled.
5.2
TRIS Register
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see Figure 45.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
1999 Microchip Technology Inc.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output operations.
For input operations these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO,W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
WR
Port
W
Reg
Q
Data
Latch
CK
VDD
Q
P
N
D
Q
TRIS
Latch
TRIS ‘f’
CK
Reset
I/O
pin(1,3)
VSS
Q
(2)
RD Port
Note 1: I/O pins have protection diodes to VDD
and VSS.
Note 2: See Table 3-1 for buffer type.
Note 3: See Section 7.0 for SCL and SDA
description for PIC12CE5XX
DS40139E-page 21
PIC12C5XX
TABLE 5-1:
Address
N/A
N/A
SUMMARY OF PORT REGISTERS
Name
TRIS
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other Resets
—
—
--11 1111
--11 1111
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
GPWUF
—
PAO
TO
PD
Z
DC
C
0001 1xxx
q00q quuu(1)
03H
STATUS
06h
GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
06h
GPIO
(PIC12CE518/
PIC12CE519)
SCL
SDA
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,
q = see tables in Section 8.7 for possible values.
Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit5 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bidirectional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wiredand”). The resulting high output currents may damage
the chip.
DS40139E-page 22
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
; GPIO Inputs
; GPIO Outputs
;
;
GPIO latch GPIO pins
;
---------- ---------BCF
GPIO, 5
;--01 -ppp
--11 pppp
BCF
GPIO, 4
;--10 -ppp
--11 pppp
MOVLW 007h
;
TRIS GPIO
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
5.4.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
1999 Microchip Technology Inc.
PIC12C5XX
FIGURE 5-2:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
MOVWF GPIO
PC + 1
MOVF GPIO,W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
This example shows a write to GPIO followed
by a read from GPIO.
NOP
NOP
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
GP5:GP0
TPD = propagation delay
Port pin
written here
Instruction
executed
MOVWF GPIO
(Write to
GPIO)
1999 Microchip Technology Inc.
Port pin
sampled here
MOVF GPIO,W
(Read
GPIO)
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
NOP
DS40139E-page 23
PIC12C5XX
NOTES:
DS40139E-page 24
1999 Microchip Technology Inc.
PIC12C5XX
6.0
TIMER0 MODULE AND
TMR0 REGISTER
Counter mode is selected by setting the T0CS bit
(OPTION). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
FIGURE 6-1:
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 6-1.
TIMER0 BLOCK DIAGRAM
Data bus
GP2/T0CKI
Pin
FOSC/4
0
PSout
1
1
Programmable
Prescaler(2)
0
T0SE
8
Sync with
Internal
Clocks
TMR0 reg
PSout
(2 TCY delay) Sync
3
T0CS(1)
PS2, PS1, PS0(1)
PSA(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
1999 Microchip Technology Inc.
DS40139E-page 25
PIC12C5XX
FIGURE 6-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
T0
Timer0
PC
PC+1
T0+1
T0+2
PC+4
PC+5
MOVF TMR0,W
NT0
Write TMR0
executed
Read TMR0
reads NT0
NT0+1
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+2
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
PC+3
PC+4
PC+5
MOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+1
NT0
Instruction
Execute
TABLE 6-1:
PC+2
MOVF TMR0,W MOVF TMR0,W
T0+1
T0
Timer0
Address
PC+3
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Executed
FIGURE 6-3:
PC+2
MOVWF TMR0
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
01h
TMR0
Timer0 - 8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
N/A
TRIS
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--11 1111 --11 1111
Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged,
DS40139E-page 26
1999 Microchip Technology Inc.
PIC12C5XX
6.1
Using Timer0 with an External Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
6.1.3
OPTION REGISTER EFFECT ON GP2 TRIS
If the option register is set to read TIMER0 from the pin,
the port is forced to an input regardless of the TRIS register setting.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1999 Microchip Technology Inc.
DS40139E-page 27
PIC12C5XX
6.2
Prescaler
EXAMPLE 6-1:
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 8.6). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
1.CLRWDT
2.CLRF
TMR0
3.MOVLW '00xx1111’b
4.OPTION
;Clear WDT
;Clear TMR0 & Prescaler
;These 3 lines (5, 6, 7)
; are required only if
; desired
5.CLRWDT
;PS are 000 or 001
6.MOVLW '00xx1xxx’b ;Set Postscaler to
7.OPTION
; desired WDT rate
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
The PSA and PS2:PS0 bits (OPTION)
determine prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will
clear the prescaler along with the WDT. The prescaler
is neither readable nor writable. On a RESET, the
prescaler contains all '0's.
6.2.1
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
MOVLW
'xxxx0xxx'
SWITCHING PRESCALER ASSIGNMENT
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
FIGURE 6-5:
CHANGING PRESCALER
(TIMER0→WDT)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
0
GP2/T0CKI
Pin
1
8
M
U
X
1
M
U
X
0
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Sync
2
Cycles
TMR0 reg
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS40139E-page 28
1999 Microchip Technology Inc.
PIC12C5XX
7.0
EEPROM PERIPHERAL
OPERATION
This section applies
PIC12CE519 only.
to
PIC12CE518
and
The PIC12CE518 and PIC12CE519 each have 16
bytes of EEPROM data memory. The EEPROM memory has an endurance of 1,000,000 erase/write cycles
and a data retention of greater than 40 years. The
EEPROM data memory supports a bi-directional 2-wire
bus and data transmission protocol. These two-wires
are serial data (SDA) and serial clock (SCL), that are
mapped to bit6 and bit7, respectively, of the GPIO register (SFR 06h). Unlike the GP0-GP5 that are connected to the I/O pins, SDA and SCL are only
connected to the internal EEPROM peripheral. For
most applications, all that is required is calls to the following functions:
; Byte_Write: Byte write routine
;
Inputs: EEPROM Address
EEADDR
;
EEPROM Data
EEDATA
;
Outputs:
Return 01 in W if OK, else
return 00 in W
;
; Read_Current: Read EEPROM at address
currently held by EE device.
;
Inputs: NONE
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK, else
return 00 in W
;
; Read_Random: Read EEPROM byte at supplied
address
;
Inputs: EEPROM Address
EEADDR
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK,
else return 00 in W
The code for these functions is available on our website
www.microchip.com. The code will be accessed by
either including the source code FL51XINC.ASM or by
linking FLASH5IX.ASM.
Namely, to avoid code overhead in modifying the TRIS
register, both SDA and SCL are always outputs. To
read data from the EEPROM peripheral requires outputting a ‘1’ on SDA placing it in high-Z state, where
only the internal 100K pull-up is active on the SDA line.
SDA:
Built-in 100K (typical) pull-up to VDD
Open-drain (pull-down only)
Always an output
Outputs a ‘1’ on reset
SCL:
Full CMOS output
Always an output
Outputs a ‘1’ on reset
The following example requires:
• Code Space: 77 words
• RAM Space: 5 bytes (4 are overlayable)
• Stack Levels:1 (The call to the function itself. The
functions do not call any lower level functions.)
• Timing:
- WRITE_BYTE takes 328 cycles
- READ_CURRENT takes 212 cycles
- READ_RANDOM takes 416 cycles.
• IO Pins: 0 (No external IO pins are used)
This code must reside in the lower half of a page. The
code achieves it’s small size without additional calls
through the use of a sequencing table. The table is a
list of procedures that must be called in order. The
table uses an ADDWF PCL,F instruction, effectively a
computed goto, to sequence to the next procedure.
However the ADDWF PCL,F instruction yields an 8 bit
address, forcing the code to reside in the first 256
addresses of a page.
It is very important to check the return codes when
using these calls, and retry the operation if unsuccessful. Unsuccessful return codes occur when the EE data
memory is busy with the previous write, which can take
up to 4 mS.
7.0.1
SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the device.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
The EEPROM interface is a 2-wire bus protocol consisting of data (SDA) and a clock (SCL). Although
these lines are mapped into the GPIO register, they are
not accessible as external pins; only to the internal
EEPROM peripheral. SDA and SCL operation is also
slightly different than GPO-GP5 as listed below.
1999 Microchip Technology Inc.
DS40139E-page 29
PIC12C5XX
Figure 7-1: Block diagram of GPIO6 (SDA line)
VDD
reset
To 24L00 SDA
Pad
D
databus
write
GPIO
ck
EN
Q
Output Latch
Q
D
Schmitt Trigger
EN
ck
Input Latch
ltchpin
Read
GPIO
Figure 7-2: Block diagram of GPIO7 (SCL line)
VDD
To 24LC00 SCL
Pad
D
databus
write
GPIO
ck
Q
EN
Q
D
Schmitt Trigger
EN
ck
Read
GPIO
DS40139E-page 30
ltchpin
1999 Microchip Technology Inc.
PIC12C5XX
7.0.2
SERIAL CLOCK
This SCL input is used to synchronize the data transfer
from and to the device.
7.1
BUS CHARACTERISTICS
The following bus protocol is to be used with the
EEPROM data memory.
• Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 7-3).
7.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
7.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
7.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
1999 Microchip Technology Inc.
7.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
7.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
Acknowledge bits are not generated if an
internal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 7-4).
DS40139E-page 31
PIC12C5XX
FIGURE 7-3:
SCL
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(C)
(D)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
(C)
(A)
SDA
FIGURE 7-4:
STOP
CONDITION
DATA
ALLOWED
TO CHANGE
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
SCL
2
SDA
3
4
5
6
7
8
9
1
Device Addressing
After generating a START condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of operation is to be performed. The slave address consists of
a 4-bit device code (1010) followed by three don’t care
bits.
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 7-5). The bus is monitored for its corresponding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
DS40139E-page 32
3
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
7.2
2
FIGURE 7-5:
CONTROL BYTE FORMAT
Read/Write Bit
Don’t Care
Bits
Device Select
Bits
S
1
0
1
0
X
X
X R/W ACK
Slave Address
Start Bit
Acknowledge Bit
1999 Microchip Technology Inc.
PIC12C5XX
7.3
WRITE OPERATIONS
7.4
7.3.1
BYTE WRITE
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master sending a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-6 for
flow diagram.
Following the start signal from the master, the device
code (4 bits), the don’t care bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer. Only the lower four address
bits are used by the device, and the upper four bits are
don’t cares. The address byte is acknowledgeable and
the master device will then transmit the data word to be
written into the addressed memory location. The memory acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this time will not generate acknowledge signals (Figure 7-7). After a byte write command, the internal address counter will not be incremented and will
point to the same address location that was just written.
If a stop bit is transmitted to the device at any point in
the write command sequence before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a stop bit is sent before a
full eight data bits have been transmitted, then the write
command will abort and no data will be written. The
EEPROM memory employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below minimum VDD.
ACKNOWLEDGE POLLING
FIGURE 7-6:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Byte write operations must be preceded and immediately followed by a bus not busy bus cycle where both
SDA and SCL are held high.
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
FIGURE 7-7:
BYTE WRITE
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S
CONTROL
BYTE
1
0
1
0
BUS ACTIVITY
X
X
WORD
ADDRESS
X
X
0
A
C
K
X
X
S
T
O
P
DATA
P
X
A
C
K
A
C
K
X = Don’t Care Bit
1999 Microchip Technology Inc.
DS40139E-page 33
PIC12C5XX
7.5
READ OPERATIONS
device as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. It will then issue an
acknowledge and transmits the eight bit data word. The
master will not acknowledge the transfer but does generate a stop condition and the device discontinues
transmission (Figure 7-9). After this command, the
internal address counter will point to the address location following the one that was just read.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
7.5.1
CURRENT ADDRESS READ
It contains an address counter that maintains the
address of the last word accessed, internally incremented by one. Therefore, if the previous read access
was to address n, the next current address read operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the device issues an acknowledge and transmits the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
device discontinues transmission (Figure 7-8).
7.5.2
7.5.3
Sequential reads are initiated in the same way as a random read except that after the device transmits the first
data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 7-10).
RANDOM READ
To provide sequential reads, it contains an internal
address pointer which is incremented by one at the
completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
FIGURE 7-8:
SEQUENTIAL READ
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S 1 0 1 0 X XX 1
S
T
O
P
CONTROL
BYTE
P
A
C
K
BUS ACTIVITY
N
O
A
C
K
DATA
X = Don’t Care Bit
FIGURE 7-9:
RANDOM READ
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
X X X X
S 1 0 1 0 X X X 0
SDA LINE
S
T
O
P
CONTROL
BYTE
P
S 1 0 1 0 X X X 1
A
C
K
A
C
K
BUS ACTIVITY
S
T
A
R
T
WORD
ADDRESS (n)
A
C
K
DATA (n)
N
O
A
C
K
X = Don’t Care Bit
FIGURE 7-10: SEQUENTIAL READ
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
S
T
O
P
DATA n + X
P
SDA LINE
BUS ACTIVITY
DS40139E-page 34
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
1999 Microchip Technology Inc.
PIC12C5XX
8.0
SPECIAL FEATURES OF THE
CPU
The PIC12C5XX has a Watchdog Timer which can be
shut off only through configuration bit WDTE. It runs
off of its own RC oscillator for added reliability. If using
XT or LP selectable oscillator options, there is always
an 18 ms (nominal) delay provided by the Device
Reset Timer (DRT), intended to keep the chip in reset
until the crystal oscillator is stable. If using INTRC or
EXTRC there is an 18 ms delay only on VDD power-up.
With this timer on-chip, most applications need no
external reset circuitry.
What sets a microcontroller apart from other
processors are special circuits to deal with the needs
of real-time applications. The PIC12C5XX family of
microcontrollers has a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up
from SLEEP through a change on input pins or
through a Watchdog Timer time-out. Several oscillator
options are also made available to allow the part to fit
the application, including an internal 4 MHz oscillator.
The EXTRC oscillator option saves system cost while
the LP crystal option saves power. A set of
configuration bits are used to select various options.
• Oscillator selection
• Reset
- Power-On Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from SLEEP on pin change
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit Serial Programming
FIGURE 8-1:
8.1
Configuration Bits
The PIC12C5XX configuration word consists of 12
bits. Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the MCLR enable bit.
CONFIGURATION WORD FOR PIC12C5XX
—
—
—
—
—
—
—
MCLRE
CP
bit11
10
9
8
7
6
5
4
3
WDTE FOSC1 FOSC0
2
1
bit0
Register:
Address(1):
CONFIG
FFFh
bit 11-5: Unimplemented
bit 4:
MCLRE: MCLR enable bit.
1 = MCLR pin enabled
0 = MCLR tied to VDD, (Internally)
bit 3:
CP: Code protection bit.
1 = Code protection off
0 = Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator selection bits
11 = EXTRC - external RC oscillator
10 = INTRC - internal RC oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the
configuration word. This register is not user addressable during device operation.
1999 Microchip Technology Inc.
DS40139E-page 35
PIC12C5XX
8.2
Oscillator Configurations
8.2.1
OSCILLATOR TYPES
TABLE 8-1:
The PIC12C5XX can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1:FOSC0) to select one of
these four modes:
•
•
•
•
LP:
XT:
INTRC:
EXTRC:
8.2.2
Low Power Crystal
Crystal/Resonator
Internal 4 MHz Oscillator
External Resistor/Capacitor
Osc
Type
CRYSTAL OPERATION (OR
CERAMIC RESONATOR) (XT
OR LP OSC
CONFIGURATION)
C1(1)
OSC1
Cap. Range
C1
Cap. Range
C2
XT
4.0 MHz
30 pF
30 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
FIGURE 8-2:
Resonator
Freq
TABLE 8-2:
In XT or LP modes, a crystal or ceramic resonator is
connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 8-2). The
PIC12C5XX oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT or LP modes, the device
can have an external clock source drive the GP5/
OSC1/CLKIN pin (Figure 8-3).
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12C5XX
Osc
Type
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR PIC12C5XX
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
32 kHz(1)
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required to avoid overdriving crystals with low
drive level specification. Since each crystal has its
own characteristics, the user should consult the crystal manufacturer for appropriate values of external
components.
LP
XT
PIC12C5XX
SLEEP
XTAL
(2)
RF(3)
OSC2
To internal
logic
RS
C2(1)
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF approximate value = 10 MΩ.
FIGURE 8-3:
EXTERNAL CLOCK INPUT
OPERATION (XT OR LP OSC
CONFIGURATION)
OSC1
PIC12C5XX
Clock from
ext. system
Open
DS40139E-page 36
OSC2
1999 Microchip Technology Inc.
PIC12C5XX
8.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 8-4 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 8-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
74AS04
PIC12C5XX
CLKIN
10k
XTAL
10k
20 pF
20 pF
Figure 8-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 8-5:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330
To Other
Devices
PIC12C5XX
330
74AS04
74AS04
74AS04
8.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Figure 8-6 shows how the R/C combination is
connected to the PIC12C5XX. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
FIGURE 8-6:
EXTERNAL RC OSCILLATOR
MODE
VDD
Rext
OSC1
Cext
Internal
clock
N
PIC12C5XX
VSS
CLKIN
0.1 µF
XTAL
1999 Microchip Technology Inc.
DS40139E-page 37
PIC12C5XX
8.2.5
INTERNAL 4 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C, see “Electrical Specifications” section for information on variation
over voltage and temperature.
In addition, a calibration instruction is programmed into
the top of memory which contains the calibration value
for the internal RC oscillator. This location is never code
protected regardless of the code protect settings. This
value is programmed as a MOVLW XX instruction where
XX is the calibration value, and is placed at the reset
vector. This will load the W register with the calibration
value upon reset and the PC will then roll over to the
users program at address 0x000. The user then has the
option of writing the value to the OSCCAL Register
(05h) or ignoring it.
Some registers are not reset in any way; they are
unknown on POR and unchanged in any other reset.
Most other registers are reset to “reset state” on poweron reset (POR), MCLR, WDT or wake-up on pin
change reset during normal operation. They are not
affected by a WDT reset during SLEEP or MCLR reset
during SLEEP, since these resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD, and GPWUF bits. They are set or cleared
differently in different reset situations. These bits are
used in software to determine the nature of reset. See
Table 8-3 for a full description of reset states of all
registers.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. .
Note:
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be read prior to
erasing the part. so it can be reprogrammed correctly later.
For the PIC12C508A, PIC12C509A, PIC12CE518,
PIC12CE519, and PIC12CR509A, bits , CAL5CAL0 are used for calibration. Adjusting CAL5-0 from
000000 to 111111 yields a higher clock speed. Note
that bits 1 and 0 of OSCCAL are unimplemented and
should be written as 0 when modifying OSCCAL for
compatibility with future devices.
For the PIC12C508 and PIC12C509, the upper 4 bits of
the register are used. Writing a larger value in this location yields a higher clock speed.
8.3
RESET
The device differentiates between various kinds of
reset:
a) Power on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT time-out reset during normal operation
e) WDT time-out reset during SLEEP
f) Wake-up from SLEEP on pin change
DS40139E-page 38
1999 Microchip Technology Inc.
PIC12C5XX
TABLE 8-3:
RESET CONDITIONS FOR REGISTERS
Address
Power-on Reset
MCLR Reset
WDT time-out
Wake-up on Pin Change
W (PIC12C508/509)
—
qqqq xxxx (1)
qqqq uuuu (1)
W (PIC12C508A/509A/
PIC12CE518/519/
PIC12CE509A)
—
qqqq qqxx (1)
qqqq qquu (1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PC
02h
1111 1111
STATUS
03h
0001 1xxx
1111 1111
q00q quuu (2,3)
FSR (PIC12C508/
PIC12C508A/
PIC12CE518)
04h
111x xxxx
111u uuuu
FSR (PIC12C509/
PIC12C509A/
PIC12CE519/
PIC12CR509A)
04h
110x xxxx
11uu uuuu
OSCCAL
(PIC12C508/509)
05h
0111 ----
uuuu ----
OSCCAL
(PIC12C508A/509A/
PIC12CE518/512/
PIC12CR509A)
05h
1000 00--
uuuu uu--
GPIO
(PIC12C508/PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
06h
--xx xxxx
--uu uuuu
GPIO
(PIC12CE518/
PIC12CE519)
06h
Register
OPTION
TRIS
Legend:
Note 1:
Note 2:
Note 3:
11xx xxxx
11uu uuuu
—
1111 1111
1111 1111
—
--11 1111
--11 1111
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Bits of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory.
See Table 8-7 for reset value for specific conditions
If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.
TABLE 8-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power on reset
0001 1xxx
1111 1111
MCLR reset during normal operation
000u uuuu
1111 1111
MCLR reset during SLEEP
0001 0uuu
1111 1111
WDT reset during SLEEP
0000 0uuu
1111 1111
WDT reset normal operation
0000 uuuu
1111 1111
Wake-up from SLEEP on pin change
1001 0uuu
1111 1111
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.
1999 Microchip Technology Inc.
DS40139E-page 39
PIC12C5XX
8.3.1
MCLR ENABLE
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD, and the pin is assigned to be a GPIO. See
Figure 8-7. When pin GP3/MCLR/VPP is configured as
MCLR, the internal pull-up is always on.
FIGURE 8-7:
MCLR SELECT
MCLRE
WEAK
PULL-UP
GP3/MCLR/V PP
8.4
INTERNAL MCLR
Power-On Reset (POR)
The PIC12C5XX family incorporates on-chip PowerOn Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program
the GP3/MCLR/VPP pin as MCLR and tie through a
resistor to VDD or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor.
Refer to Table 11-1 for the pull-up resistor ranges. This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
VDD is specified. See Electrical Specifications for
details.
The Power-On Reset circuit and the Device Reset
Timer (Section 8.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the onchip reset signal.
A power-up example where MCLR is held low is
shown in Figure 8-9. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
In Figure 8-10, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together or the
pin is programmed to be GP3.). The VDD is stable
before the start-up timer times out and there is no
problem in getting a proper reset. However, Figure 811 depicts a problem situation where VDD rises too
slowly. The time between when the DRT senses that
MCLR is high and when MCLR (and VDD) actually
reach their full value, is too long. In this situation, when
the start-up timer times out, VDD has not reached the
VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations,
we recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-10).
Note:
When the device starts normal operation
(exits the reset condition), device operating
parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the
device must be held in reset until the operating conditions are met.
For additional information refer to Application Notes
“Power-Up Considerations” - AN522 and “Power-up
Trouble Shooting” - AN607.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 8-8.
DS40139E-page 40
1999 Microchip Technology Inc.
PIC12C5XX
FIGURE 8-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
Pin Change
Wake-up on
pin change
SLEEP
GP3/MCLR/VPP
WDT Time-out
MCLRE
RESET
8-bit Asynch
On-Chip
DRT OSC
S
Q
R
Q
Ripple Counter
(Start-Up Timer)
CHIP RESET
FIGURE 8-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
1999 Microchip Technology Inc.
DS40139E-page 41
PIC12C5XX
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
8.5
Device Reset Timer (DRT)
In the PIC12C5XX, DRT runs from RESET and varies
based on oscillator selection (see Table 8-5.)
The DRT operates on an internal RC oscillator. The
processor is kept in RESET as long as the DRT is
active. The DRT delay allows VDD to rise above VDD
min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high (VIHMCLR)
level. Thus, programming GP3/MCLR/VPP as MCLR
and using an external RC network connected to the
MCLR input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the GP3/
MCLR/VPP pin as a general purpose input.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog
Timer time-out. This is particularly important for
applications using the WDT to wake from SLEEP
mode automatically.
DS40139E-page 42
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO bit (STATUS) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a ’0’
(Section 8.1). Refer to the PIC12C5XX Programming
Specifications to determine how to access the
configuration word.
TABLE 8-5:
Oscillator
Configuration
DRT (DEVICE RESET TIMER
PERIOD)
POR Reset
Subsequent
Resets
IntRC &
ExtRC
18 ms (typical)
300 µs (typical)
XT & LP
18 ms (typical)
18 ms (typical)
1999 Microchip Technology Inc.
PIC12C5XX
8.6.1
WDT PERIOD
8.6.2
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and part-topart process variations (see DC specs).
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 8-5)
0
1
Watchdog
Timer
M
Postscaler
Postscaler
U
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
Configuration Bit
To Timer0 (Figure 8-4)
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 8-6:
Address
N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Value on
All Other
Resets
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as ’0’, u = unchanged
1999 Microchip Technology Inc.
DS40139E-page 43
PIC12C5XX
8.7
Time-Out Sequence, Power Down,
and Wake-up from SLEEP Status Bits
(TO/PD/GPWUF)
FIGURE 8-14: BROWN-OUT PROTECTION
CIRCUIT 2
VDD
The TO, PD, and GPWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) reset.
R1
TABLE 8-7:
R2
TO
PD
0
0
0
VDD
Q1
MCLR
TO/PD/GPWUF STATUS
AFTER RESET
GPWUF
40k* PIC12C5XX
RESET caused by
WDT wake-up from
SLEEP
0
0
u WDT time-out (not from
SLEEP)
0
1
0 MCLR wake-up from
SLEEP
0
1
1 Power-up
0
u
u MCLR not during SLEEP
1
1
0 Wake-up from SLEEP on
pin change
Legend: u = unchanged
Note 1: The TO, PD, and GPWUF bits maintain
their status (u) until a reset occurs. A lowpulse on the MCLR input does not change
the TO, PD, and GPWUF status bits.
8.8
VDD
Reset on Brown-Out
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
VDD •
To reset PIC12C5XX devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 8-13 , Figure 8-14 and
Figure 8-15
FIGURE 8-13: BROWN-OUT PROTECTION
CIRCUIT 1
VDD
= 0.7V
*Refer to Figure 8-7 and Table 11-1 for internal
weak pull-up on MCLR.
FIGURE 8-15: BROWN-OUT PROTECTION
CIRCUIT 3
VDD
MCP809
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
R1
R1 + R2
Vss
bypass
capacitor
VDD
VDD
RST
MCLR
PIC12C5XX
This brown-out protection circuit employs
Microchip Technology’s MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX family of
supervisors provide push-pull and open collector
outputs with both high and low active reset pins.
There are 7 different trip point selections to
accomodate 5V and 3V systems.
VDD
VDD
33k
10k
Q1
MCLR
40k* PIC12C5XX
This circuit will activate reset when VDD goes below
Vz + 0.7V (where Vz = Zener voltage).
*Refer to Figure 8-7 and Table 11-1 for internal
weak pull-up on MCLR.
DS40139E-page 44
1999 Microchip Technology Inc.
PIC12C5XX
8.9
Power-Down Mode (SLEEP)
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
8.9.1
SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS) is set, the PD
bit (STATUS) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level (VIHMC) if
MCLR is enabled.
8.9.2
WAKE-UP FROM SLEEP
8.10
Program Verification/Code Protection
If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
The first 64 locations can be read by the PIC12C5XX
regardless of the code protection bit setting.
The last memory location cannot be read if code protection is enabled on the PIC12C508/509.
The last memory location can be read regardless of the
code protection bit setting on the PIC12C508A/509A/
CR509A/CE518/CE519.
8.11
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other codeidentification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as ’0’s.
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
An external reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
A Watchdog Timer time-out reset (if WDT was
enabled).
A change on input pin GP0, GP1, or GP3/
MCLR/VPP when wake-up on change is
enabled.
These events cause a device reset. The TO, PD, and
GPWUF bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
SLEEP at pins GP0, GP1, or GP3 (since the last time
there was a file or bit operation on GP port).
Caution: Right before entering SLEEP, read the
input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and the pins are not read before
reentering SLEEP, a wake up will occur
immediately even if no pins change while
in SLEEP mode.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
1999 Microchip Technology Inc.
DS40139E-page 45
PIC12C5XX
8.12
In-Circuit Serial Programming
The PIC12C5XX microcontrollers with EPROM program memory can be serially programmed while in the
end application circuit. This is simply done with two
lines for clock and data, and three other lines for power,
ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed
devices, and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be programmed.
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 becomes the programming clock
and GP0 becomes the programming data. Both GP1
and GP0 are Schmitt Trigger inputs in this mode.
After reset, a 6-bit command is then supplied to the
device. Depending on the command, 14-bits of program data are then supplied to or from the device,
depending if the command was a load or a read. For
complete details of serial programming, please refer to
the PIC12C5XX Programming Specifications.
FIGURE 8-16: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC12C5XX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1
Data I/O
GP0
VDD
To Normal
Connections
A typical in-circuit serial programming connection is
shown in Figure 8-16.
DS40139E-page 46
1999 Microchip Technology Inc.
PIC12C5XX
9.0
INSTRUCTION SET SUMMARY
Each PIC12C5XX instruction is a 12-bit word divided
into an OPCODE, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The PIC12C5XX
instruction set summary in Table 9-2 groups the
instructions into byte-oriented, bit-oriented, and literal
and control operations. Table 9-1 shows the opcode
field descriptions.
For byte-oriented instructions, ’f’ represents a file
register designator and ’d’ represents a destination
designator. The file register designator is used to
specify which one of the 32 file registers is to be used
by the instruction.
The destination designator specifies where the result
of the operation is to be placed. If ’d’ is ’0’, the result is
placed in the W register. If ’d’ is ’1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
8 or 9-bit constant or literal value.
TABLE 9-1:
OPCODE FIELD
DESCRIPTIONS
Field
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
d
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ’f’)
Default is d = 1
label
Label name
TOS
Top of Stack
PC
Program Counter
WDT
Watchdog Timer Counter
TO
Time-Out bit
PD
Power-Down bit
[ ]
Options
Contents
→
Assigned to
Register bit field
italics
0xhhh
where ’h’ signifies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
11
6
OPCODE
5
d
4
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11
OPCODE
8 7
5 4
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTO instruction
11
9
8
OPCODE
0
k (literal)
k = 9-bit immediate value
Destination, either the W register or the specified
register file location
( )
∈
Figure 9-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
Description
f
dest
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
In the set of
User defined term (font is courier)
1999 Microchip Technology Inc.
DS40139E-page 47
PIC12C5XX
TABLE 9-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f,d
f,d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
12-Bit Opcode
Description
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
LSb
Status
Affected Notes
Cycles
MSb
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C,DC,Z
None
Z
1,2,4
2,4
4
1
1
1 (2)
1 (2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2,4
2,4
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
2,4
2,4
2,4
2,4
2,4
2,4
1,4
2,4
2,4
1,2,4
2,4
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
k
k
k
k
–
k
–
f
k
AND literal with W
Call subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
Exclusive OR Literal to W
1
3
Note 1: The 9th bit of the program counter will be forced to a ’0’ by any instruction that writes to the PC except for GOTO.
(Section 4.6)
2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven
low by an external device, the data will be written back with a ’0’.
3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of
GPIO. A ’1’ forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS40139E-page 48
1999 Microchip Technology Inc.
PIC12C5XX
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
Operation:
ANDWF
[ label ] ANDWF
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected: C, DC, Z
Encoding:
0001
Description:
AND W with f
Syntax:
f,d
f,d
Status Affected: Z
11df
ffff
Encoding:
0001
01df
ffff
Add the contents of the W register and
register ’f’. If ’d’ is 0 the result is stored
in the W register. If ’d’ is ’1’ the result is
stored back in register ’f’.
Description:
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example:
ADDWF
Example:
ANDWF
FSR, 0
Before Instruction
W
=
FSR =
FSR,
0x17
0xC2
W =
FSR =
0x17
0xC2
After Instruction
After Instruction
W
=
FSR =
W
=
FSR =
0xD9
0xC2
ANDLW
And literal with W
Syntax:
[ label ] ANDLW
BCF
Operands:
0 ≤ k ≤ 255
Operation:
(W).AND. (k) → (W)
0x17
0x02
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 31
0≤b≤7
Status Affected: Z
Operation:
0 → (f)
Encoding:
Status Affected: None
1110
Description:
kkkk
1
Cycles:
1
Example:
ANDLW
0x5F
Before Instruction
W
=
0xA3
After Instruction
W
k
kkkk
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Words:
=
1
Before Instruction
Encoding:
0100
bbbf
f,b
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Example:
BCF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
0x03
1999 Microchip Technology Inc.
DS40139E-page 49
PIC12C5XX
BSF
Bit Set f
Syntax:
[ label ] BSF
BTFSS
Operands:
Operation:
Bit Test f, Skip if Set
Syntax:
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0≤b≤7
Operands:
0 ≤ f ≤ 31
0≤b
