PIC12F519
Data Sheet
8-Pin, 8-Bit Flash Microcontrollers
*8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
© 2008 Microchip Technology Inc.
DS41319B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41319B-page ii
© 2008 Microchip Technology Inc.
PIC12F519
8-Pin, 8-Bit Flash Microcontroller
High-Performance RISC CPU:
Low-Power Features/CMOS Technology:
• Only 33 Single-Word Instructions
• All Single-Cycle Instructions except for Program
Branches which are Two-Cycle
• Two-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
for Data and Instructions
• Operating Speed:
- DC – 8 MHz Oscillator
- DC – 500 ns instruction cycle
• On-chip Flash Program Memory
- 1024 x 12
• General Purpose Registers (SRAM)
- 41 x 8
• Flash Data Memory
- 64 x 8
• Standby Current:
- 100 nA @ 2.0V, typical
• Operating Current:
- 11 μA @ 32 kHz, 2.0V, typical
- 175 μA @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 μA @ 2.0V, typical
- 7 μA @ 5.0V, typical
• High Endurance Program and Flash Data Memory
Cells
- 100,000 write Program Memory endurance
- 1,000,000 write Flash Data Memory endurance
- Program and Flash Data retention: >40 years
• Fully Static Design
• Wide Operating Voltage Range: 2.0V to 5.5V
- Wide temperature range
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Special Microcontroller Features:
• 8 MHz Precision Internal Oscillator
- Factory calibrated to ±1%
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Debugging (ICD) Support
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with Dedicated On-Chip
RC Oscillator for Reliable Operation
• Programmable Code Protection
• Multiplexed MCLR Input Pin
• Internal Weak Pull-ups on I/O Pins
• Power-Saving Sleep mode
• Wake-up from Sleep on Pin Change
• Selectable Oscillator Options:
- INTRC: 4 MHz or 8 MHz precision Internal
RC oscillator
- EXTRC: External low-cost RC oscillator
- XT:
Standard crystal/resonator
- LP:
Power-saving, low-frequency crystal
© 2008 Microchip Technology Inc.
Peripheral Features:
• 6 I/O Pins
- 5 I/O pins with individual direction control
- 1 input-only pin
- High current sink/source for direct LED drive
• 8-bit Real-Time Clock/Counter (TMR0) with 8-bit
Programmable Prescaler.
DS41319B-page 1
PIC12F519
FIGURE 1:
PIC12F519 8-PIN PDIP, SOIC, MSOP, 2X3 DFN DIAGRAM
VDD
1
GP5/OSC1/CLKIN
2
GP4/OSC2
3
GP3/MCLR/VPP
4
PIC12F519
PDIP, SOIC, MSOP
8
7
VSS
6
GP1/ICSPCLK
5
GP2/T0CKI
GP0/ICSPDAT
VDD
1
GP5/OSC1/CLKIN
2
GP4/OSC2
3
GP3/MCLR/VPP
4
Program Memory
PIC12F519
DFN
8
VSS
7
GP0/ICSPDAT
6
GP1/ICSPCLK
5
GP2/T0CKI
Data Memory
Device
PIC12F519
DS41319B-page 2
Flash (words)
SRAM (bytes)
Flash (bytes)
1024
41
64
I/O
Timers 8-bit
6
1
© 2008 Microchip Technology Inc.
PIC12F519
Table of Contents
1.0
General Description .................................................................................................................................................................. 5
2.0
PIC12F519 Device Varieties .................................................................................................................................................... 7
3.0
Architectural Overview .............................................................................................................................................................. 9
4.0
Memory Organization ............................................................................................................................................................. 13
5.0
Flash Data Memory ................................................................................................................................................................ 21
6.0
I/O Port ................................................................................................................................................................................... 23
7.0
Timer0 Module and TMR0 Register ........................................................................................................................................ 31
8.0
Special Features Of The CPU ................................................................................................................................................ 37
9.0
Instruction Set Summary ........................................................................................................................................................ 49
10.0 Development Support ............................................................................................................................................................. 57
11.0 Electrical Characteristics ........................................................................................................................................................ 61
12.0 DC and AC Characteristics Graphs and Charts ..................................................................................................................... 73
13.0 Packaging Information ............................................................................................................................................................ 83
Index ................................................................................................................................................................................................... 89
The Microchip Web Site ...................................................................................................................................................................... 91
Customer Change Notification Service ............................................................................................................................................... 91
Customer Support ............................................................................................................................................................................... 91
Reader Response ............................................................................................................................................................................... 92
Product Identification System ............................................................................................................................................................. 93
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2008 Microchip Technology Inc.
DS41319B-page 3
PIC12F519
NOTES:
DS41319B-page 4
© 2008 Microchip Technology Inc.
PIC12F519
1.0
GENERAL DESCRIPTION
The PIC12F519 device from Microchip Technology is
low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontrollers. They employ a RISC
architecture with only 33 single-word/single-cycle
instructions. All instructions are single cycle except for
program branches, which take two cycles. The
PIC12F519 device delivers performance an order of
magnitude higher than their competitors in the same
price category. The 12-bit wide instructions are highly
symmetrical, resulting in a typical 2:1 code
compression over other 8-bit microcontrollers in its
class. The easy-to-use and easy to remember
instruction set reduces development time significantly.
The PIC12F519 product is equipped with special
features that reduce system cost and power
requirements. The Power-on Reset (POR) and Device
Reset Timer (DRT) eliminate the need for external
Reset circuitry. There are four oscillator configurations
to choose from including INTRC Internal Oscillator
mode and the power-saving LP (Low-power) Oscillator
mode. Power-Saving Sleep mode, Watchdog Timer
and code protection features improve system cost,
power and reliability.
1.1
Applications
The PIC12F519 device fits in applications ranging from
personal care appliances and security systems to lowpower remote transmitters/receivers. The Flash
technology makes customizing application programs
(transmitter codes, appliance settings, receiver
frequencies, etc.) extremely fast and convenient. The
small footprint packages, for through hole or surface
mounting, make these microcontrollers perfect for
applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC12F519 device very versatile even in
areas where no microcontroller use has been
considered before (e.g., timer functions, logic and
PLDs in larger systems and coprocessor applications).
The PIC12F519 device is available in the cost-effective
Flash programmable version, which is suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in Flash
programmable microcontrollers, while benefiting from
the Flash programmable flexibility.
The PIC12F519 product is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full featured programmer. All the tools are supported on
PC and compatible machines.
TABLE 1-1:
FEATURES AND MEMORY OF PIC12F519
PIC12F519
Clock
Maximum Frequency of Operation (MHz)
Memory
Flash Program Memory
SRAM Data Memory (bytes)
Flash Data Memory (bytes)
Peripherals
Timer Module(s)
Wake-up from Sleep on Pin Change
Features
8
1024
41
64
TMR0
Yes
I/O Pins
5
Input Pins
1
Internal Pull-ups
Yes
In-Circuit Serial Programming™
Yes
Number of Instructions
Packages
33
8-pin PDIP, SOIC, MSOP, 2X3 DFN
The PIC12F519 device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and
precision internal oscillator.
The PIC12F519 device uses serial programming with data pin GP0 and clock pin GP1.
© 2008 Microchip Technology Inc.
DS41319B-page 5
PIC12F519
NOTES:
DS41319B-page 6
© 2008 Microchip Technology Inc.
PIC12F519
2.0
PIC12F519 DEVICE VARIETIES
When placing orders, please use the PIC12F519
Product Identification System at the back of this data
sheet to specify the correct part number. A variety of
packaging options are available. Depending on
application and production requirements, the proper
device option can be selected using the information in
this section.
2.1
Quick Turn Programming (QTP)
Devices
2.2
Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where a
few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
Microchip offers a QTP programming service for factory
production orders. This service is made available for
users who choose not to program medium-to-high
quantity units and whose code patterns have stabilized.
The devices are identical to the Flash devices but with
all Flash locations and fuse options already
programmed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available. Please contact your local
Microchip Technology sales office for more details.
© 2008 Microchip Technology Inc.
DS41319B-page 7
PIC12F519
NOTES:
DS41319B-page 8
© 2008 Microchip Technology Inc.
PIC12F519
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12F519 device can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC12F519 device uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional
von Neumann architectures where program and data
are fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12 bits wide, making it possible to have
all single-word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions (33) execute in a single cycle (500 ns @ 8 MHz,
1 μs @ 4 MHz) except for program branches.
The ALU is 8 bits wide and capable of addition,
subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s
complement in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-2.
Table 3-1 below lists memory supported by the
PIC12F519 device.
TABLE 3-1:
PIC12F519 MEMORY
Program
Memory
Data Memory
Device
PIC12F519
Flash
(words)
SRAM
(bytes)
Flash
Data
(bytes)
1024
41
64
The PIC12F519 device can directly or indirectly
address its register files and data memory. All Special
Function Registers (SFR), including the PC, are
mapped in the data memory. The PIC12F519 device
has a highly orthogonal (symmetrical) instruction set
that makes it possible to carry out any operation, on
any register, using any addressing mode. This symmetrical nature and lack of “special optimal situations”
make programming with the PIC12F519 device simple,
yet efficient. In addition, the learning curve is reduced
significantly.
The PIC12F519 device contains an 8-bit ALU and
working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
© 2008 Microchip Technology Inc.
DS41319B-page 9
PIC12F519
FIGURE 3-1:
PIC12F519 ARCHITECTURAL BLOCK DIAGRAM
Flash Program
Memory
1K x 12
11
Flash Data
Memory
64x8
8
Data Bus
Program Counter
GP0/ICSPDAT
GP1/ICSPCLK
GP2/T0CKI
GP3/MCLR/VPP
GP4/OSC2
GP55/OSC1/CLKIN
RAM
41 x 8
File
Registers
Stack 1
Stack 2
Program 12
Bus
RAM Addr
GPI/O
9
Addr MUX
Instruction Reg
Direct Addr
5
5-7
Indirect
Addr
FSR Reg
STATUS Reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2
Timing
Generation
Internal RC
OSC
Power-on
Reset
Watchdog
Timer
ALU
8
W Reg
Timer0
MCLR
VDD, VSS
DS41319B-page 10
© 2008 Microchip Technology Inc.
PIC12F519
TABLE 3-2:
Name
PIC12F519 PINOUT DESCRIPTION
Function
GP0/ICSPDAT
GP1/ICSPCLK
GP4/OSC2
GP5/OSC1/
CLKIN
VDD
VSS
Legend:
Description
TTL
CMOS
Bidirectional I/O port with weak pull-up
ICSPDAT
I/O
ST
CMOS
ICSP™ mode Schmitt Trigger
GP1
I/O
TTL
CMOS
I
ST
—
GP2
GP3/MCLR/VPP
Input Type Output Type
I/O
ICSPCLK
GP2/T0CKI
Type
GP0
Bidirectional I/O port with weak pull-up
ICSP™ mode Schmitt Trigger
I/O
TTL
CMOS
T0CKI
I
ST
—
Timer0 clock input
Bidirectional I/O port
GP3
I
TTL
—
Standard TTL input with weak pull-up
MCLR
I
ST
—
MCLR input (Weak pull-up always enabled in
this mode)
VPP
I
High Voltage
—
Test mode high voltage pin
GP4
I/O
TTL
CMOS
Bidirectional I/O port
OSC2
O
—
XTAL
XTAL oscillator output pin
GP5
I/O
TTL
CMOS
I
XTAL
—
CLKIN
I
ST
—
EXTRC Schmitt Trigger input
VDD
P
—
—
Positive supply for logic and I/O pins
VSS
P
—
—
Ground reference for logic and I/O pins
OSC1
Bidirectional I/O port
XTAL oscillator input pin
I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog Voltage
© 2008 Microchip Technology Inc.
DS41319B-page 11
PIC12F519
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2 and Example 3-1.
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 1
Fetch INST (PC)
Execute INST (PC - 1)
EXAMPLE 3-1:
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
4. BSF
SUB_1
GPIO, 1
PC + 2
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
INSTRUCTION PIPELINE FLOW
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS41319B-page 12
© 2008 Microchip Technology Inc.
PIC12F519
The PIC12F519 memory is organized into program
memory and data memory (SRAM). The self-writable
portion of the program memory called Flash data memory, is located at addresses 400h-43Fh. As the device
has more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed
using STATUS register bit, PA0. For the PIC12F519,
with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks
are accessed using the File Select Register (FSR).
4.1
Program Memory Organization for
the PIC12F519
The PIC12F519 device has an 11-bit Program Counter
(PC) capable of addressing a 2K x 12 program memory
space.
Only the first 1K x 12 (0000h-03FFh) are physically
implemented (see Figure 4-1). Accessing a location
above these boundaries will cause a wrap-around
within the 1K x 12 space. The effective Reset vector
is a 0000h (see Figure 4-1). Location 03FFh contains
the internal clock oscillator calibration value. This
value should never be overwritten.
FIGURE 4-1:
MEMORY MAP
PC
10
CALL, RETLW
Stack Level 1
Stack Level 2
Reset Vector(1)
0000h
On-chip Program
Memory
User Memory
Space
MEMORY ORGANIZATION
512 Word
01FFh
0200h
On-chip Program
Memory
1024 Word
Flash Data Memory
Space
4.0
03FFh
0400h
Flash Data Memory
043Fh
0440h
7FFh
Note 1:
2:
© 2008 Microchip Technology Inc.
Address 0000h becomes the effective
Reset vector. Location 03FFh contains
the MOVLW XX internal oscillator
calibration value.
Flash data memory is non-executable.
DS41319B-page 13
PIC12F519
4.2
Data Memory (SRAM and FSRs)
Data memory is composed of registers or bytes of
SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into
two functional groups: Special Function Registers
(SFR) and General Purpose Registers (GPR).
The Special Function Registers include the TMR0
register, the Program Counter Low (PCL), the STATUS
register, the I/O register (port) and the File Select
Register (FSR). In addition, the EECON, EEDATA and
EEADR registers provide for interface with the Flash
data memory.
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
The PIC12F519 register file is composed of 10 Special
Function Registers and 41 General Purpose Registers.
4.2.1
GENERAL PURPOSE REGISTER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.8 “Indirect Data Addressing:
INDF and FSR Registers”.
FIGURE 4-2:
REGISTER FILE MAP
FSR
0
1
File Address
00h
INDF(1)
INDF(1)
01h
TMR0
EECON
02h
PCL
PCL
03h
STATUS
STATUS
04h
FSR
FSR
05h
OSCCAL
EEDATA
06h
GPIO
EEADR
General
Purpose
Registers
Address map
back to
addresses
in Bank 0
20h
07h
08h
09h
0Ah
2Fh
0Fh
10h
30h
General
Purpose
Registers
General
Purpose
Registers
1Fh
3Fh
Bank 0
Bank 1
Note 1: Not a physical register.
DS41319B-page 14
© 2008 Microchip Technology Inc.
PIC12F519
TABLE 4-1:
Addr
Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
—
—
TRISGPIO5
TRISGPIO4
TRISGPIO3
TRISGPIO2
TRISGPIO1
TRISGPIO0
--11 1111
N/A
TRISGPIO
N/A
OPTION
Contains Control Bits to Configure Timer0 and Timer0/WDT Prescaler
1111 1111
00h
INDF
Uses Contents of FSR to Address Data Memory (not a physical register)
xxxx xxxx
01h
TMR0
Timer0 Module Register
xxxx xxxx
02h(1)
PCL
Low Order 8 bits of PC
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
—
1111 1111
PA0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
21h
EECON
25h
EEDATA
26h
EEADR
Legend:
Note 1:
GPWUF
0-01 1xxx
110x xxxx
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
1111 111-
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
—
—
EEDATA7 EEDATA6
—
—
—
FREE
WRERR
WREN
WR
RD
---0 x000
EEDATA5
EEDATA4
EEDATA3
EEDATA2
EEDATA1
EEDATA0
xxxx xxxx
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
--xx xxxx
x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused
The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to
access these bits.
© 2008 Microchip Technology Inc.
DS41319B-page 15
PIC12F519
4.3
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
STATUS register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
Therefore, it is recommended that only BCF, BSF and
MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits
from the STATUS register. For other instructions which
do affect Status bits, see Section 9.0 “Instruction Set
Summary”.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 4-1:
STATUS: STATUS REGISTER
R/W-0
U-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
GPWUF
—
PA0
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GPWUF: Wake-up From Sleep on Pin Change bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6
Unimplemented: Read as ‘0’
bit 5
PA0: Program Page Preselect bit
1 = Page 1 (000h-1FFh)
0 = Page 0 (200h-3FFh)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF:
SUBWF:
RRF or RLF:
1 = A carry occurred
1 = A borrow did not occur
Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
DS41319B-page 16
© 2008 Microchip Technology Inc.
PIC12F519
4.4
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION register. A Reset sets the OPTION bits.
OPTION Register
The OPTION register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
REGISTER 4-2:
Note:
If the T0SC bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
OPTION: OPTION REGISTER
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GPWU: Enable Wake-up On Pin Change bit
1 = Disabled
0 = Enabled
bit 6
GPPU: Enable Weak Pull-ups bit
1 = Disabled
0 = Enabled
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0
PS: Prescaler Rate Select bits
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
© 2008 Microchip Technology Inc.
DS41319B-page 17
PIC12F519
4.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used
to calibrate the 8 MHz internal oscillator macro. It
contains 7 bits of calibration that uses a two’s
complement scheme for controlling the oscillator speed.
See Register 4-3 for details.
REGISTER 4-3:
OSCCAL: OSCILLATOR CALIBRATION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
CAL: Oscillator Calibration bits
0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 =Minimum frequency
bit 0
Unimplemented: Read as ‘0’
DS41319B-page 18
x = Bit is unknown
© 2008 Microchip Technology Inc.
PIC12F519
4.6
4.6.1
Program Counter
EFFECTS OF RESET
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
For a GOTO instruction, bits of the PC are provided by the GOTO instruction word. The Program
Counter (PCL) is mapped to PC. Bit 5 of the STATUS register provides page information to bit 9 of the
PC (Figure 4-3).
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is pre-selected.
For a CALL instruction, or any instruction where the
PCL is the destination, bits of the PC again are
provided by the instruction word. However, PC
does not come from the instruction word, but is always
cleared (Figure 4-3).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PCL, ADDWF PCL
and BSF PCL,5.
Note:
Because PC is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
FIGURE 4-3:
LOADING OF PC
BRANCH INSTRUCTIONS
GOTO Instruction
10 9 8 7
PC
0
PCL
4.7
Stack
The PIC12F519 device has a two-deep, 12-bit wide
hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack
1 into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than two
sequential CALLs are executed, only the most recent two
return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
program memory.
Note 1: There are no Status bits to indicate stack
overflows or stack underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
Instruction Word
PA0
7
Therefore, upon a Reset, a GOTO instruction will
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
0
Status
CALL or Modify PCL Instruction
10 9 8 7
0
PCL
PC
PA0
Instruction Word
Reset to ‘0’
7
0
Status
© 2008 Microchip Technology Inc.
DS41319B-page 19
PIC12F519
4.8
EXAMPLE 4-1:
Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
NEXT
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although Status bits may be affected).
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
MOVLW
MOVWF
CLRF
0x10
FSR
INDF
INCF
BTFSC
GOTO
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF
;register
;inc pointer
;all done?
;NO, clear next
CONTINUE
The FSR is an 8-bit wide register. It is used in conjunction with the INDF Register to indirectly address the
data memory area.
:
:
;YES, continue
The FSR bits are used to select data memory
addresses 00h to 1Fh.
FSR is used to select between banks (0 = Bank 0,
1 = Bank 1).
FSR are unimplemented and read as ‘11’.
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
5
Bank Select
4
Indirect Addressing
(opcode)
5
0
Location Select
4
Bank
0
(FSR)
0
Location Select
1
00h
Data
Memory
0Fh
10h
1Fh
Bank 0
DS41319B-page 20
3Fh
Bank 1
© 2008 Microchip Technology Inc.
PIC12F519
5.0
FLASH DATA MEMORY
CONTROL
The Flash data memory is readable and writable during
normal operation (full VDD range). This memory is not
directly mapped in the register file space. Instead, it is
indirectly addressed through the Special Function
Registers (SFRs).
5.1
Reading Flash Data Memory
To read a Flash data memory location the user must:
• Write the EEADR register
• Set the RD bit of the EECON register
The value written to the EEADR register determines
which Flash data memory location is read. Setting the
RD bit of the EECON register initiates the read. Data
from the Flash data memory read is available in the
EEDATA register immediately. The EEDATA register
will hold this value until another read is initiated or it is
modified by a write operation. Program execution is
suspended while the read cycle is in progress. Execution will continue with the instruction following the one
that sets the WR bit. See Example 1 for sample code.
EXAMPLE 1:
READING FROM FLASH
DATA MEMORY
BANKSEL EEADR
;
MOVF DATA_EE_ADDR, W
;
MOVWF EEADR
;Data Memory
;Address to read
BANKSEL EECON1
;
BSF EECON, RD
;EE Read
MOVF EEDATA, W
;W = EEDATA
Note: Only a BSF command will work to enable the
Flash data memory read documented in
Example 1. No other sequence of commands will work, no exceptions.
5.2
Writing and Erasing Flash Data
Memory
Flash data memory is erased one row at a time and
written one byte at a time. The 64-byte array is made
up of eight rows. A row contains eight sequential bytes.
Row boundaries exist every eight bytes.
Generally, the procedure to write a byte of data to Flash
data memory is:
1.
2.
3.
Identify the row containing the address where
the byte will be written.
If there is other information in that row that must
be saved, copy those bytes from Flash data
memory to RAM.
Perform a row erase of the row of interest.
© 2008 Microchip Technology Inc.
4.
Write the new byte of data and any saved bytes
back to the appropriate addresses in Flash data
memory.
To prevent accidental corruption of the Flash Data
Memory, an unlock sequence is required to initiate a
write or erase cycle. This sequence requires that the bit
set instructions used to configure the EECON register
happen exactly as shown in Example 2 and Example 3,
depending on the operation requested.
5.2.1
ERASING FLASH DATA MEMORY
A row must be manually erased before writing new
data. The following sequence must be performed for a
single row erase.
1.
2.
3.
4.
Load EEADR with an address in the row to be
erased.
Set the FREE bit to enable the erase.
Set the WREN bit to enable write access to the
array.
Set the WR bit to initiate the erase cycle.
If the WREN bit is not set in the instruction cycle after
the FREE bit is set, the FREE bit will be cleared in
hardware.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Example 2.
Program execution is suspended while the erase cycle
is in progress. Execution will continue with the instruction following the one that sets the WR bit.
EXAMPLE 2:
ERASING A FLASH DATA
MEMORY ROW
BANKSEL
EEADR
MOVLW
EE_ADR_ERASE
; LOAD ADDRESS OF ROW TO
MOVWF
EEADR
;
BSF
EECON,FREE
; SELECT ERASE
BSF
EECON,WREN
; ENABLE WRITES
BSF
EECON,WR
; INITITATE ERASE
; ERASE
Note 1: The FREE bit may be set by any command normally used by the core. However, the WREN and WR bits can only be
set using a series of BSF commands, as
documented in Example 1. No other
sequence of commands will work, no
exceptions.
2: Bits of the EEADR register indicate
which row is to be erased.
DS41319B-page 21
PIC12F519
5.2.2
WRITING TO FLASH DATA
MEMORY
EXAMPLE 4:
WRITE VERIFY OF DATA
EEPROM
Once a cell is erased, new data can be written. Program execution is suspended during the write cycle.
The following sequence must be performed for a single
byte write.
MOVF
EEDATA, W
;EEDATA has not changed
BSF
EECON, RD
;Read the value written
XORWF
EEDATA, W
;
1.
2.
3.
BTFSS
STATUS, Z
;Is data the same
GOTO
WRITE_ERR
;No, handle error
Load EEADR with the address.
Load EEDATA with the data to write.
Set the WREN bit to enable write access to the
array.
Set the WR bit to initiate the erase cycle.
4.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Example 3.
EXAMPLE 3:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
;from previous write
;Yes, continue
5.4
Code Protection
Code protection does not prevent the CPU from performing read or write operations on the Flash data
memory. Refer to the code protection chapter for more
information.
WRITING A FLASH DATA
MEMORY ROW
EEADR
EE_ADR_WRITE
EEADR
EE_DATA_TO_WRITE
EEDATA
EECON,WREN
EECON,WR
;
;
;
;
;
;
LOAD ADDRESS
LOAD DATA
INTO EEDATA REGISTER
ENABLE WRITES
INITITATE ERASE
Note 1: Only a series of BSF commands will work
to enable the memory write sequence
documented in Example 2. No other
sequence of commands will work, no
exceptions.
2: For reads, erases and writes to the Flash
data memory, there is no need to insert a
NOP into the user code as is done on
mid-range devices. The instruction immediately
following
the
“BSF
EECON,WR/RD” will be fetched and
executed properly.
5.3
Write Verify
Depending on the application, good programming
practice may dictate that data written to the Flash data
memory be verified. Example 4 is an example of a write
verify.
DS41319B-page 22
© 2008 Microchip Technology Inc.
PIC12F519
6.0
I/O PORT
6.2
The Output Driver Control registers are loaded with
the contents of the W Register by executing the TRIS
f instruction. A ‘1’ from a TRISGPIO Register bit puts
the corresponding output driver in a high-impedance
(Input) mode. A ‘0’ puts the contents of the output data
latch on the selected pins, enabling the output buffer.
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
6.1
The TRISGPIO register is “write-only”. Bits are
set (output drivers disabled) upon Reset.
GPIO
Note:
GPIO is an 8-bit I/O register. Only the low-order 6 bits
are used (GP). Bits 7 and 6 are unimplemented
and read as ‘0’s. Please note that GP3 is an input-only
pin. The Configuration Word can set several I/O’s to
alternate functions. When acting as alternate functions,
the pins will read as ‘0’ during a port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also for wake-up on change. The wake-up on
change and weak pull-up functions are not pin selectable. If GP3/MCLR is configured as MCLR, weak pullup is always on and wake-up on change for this pin is
not enabled.
TABLE 6-1:
TRIS Registers
If the T0CS bit is set to ‘1’, it will override
the TRISGPIO function on the T0CKI pin.
WEAK PULL-UP ENABLED PINS
Pin
WPU
WU
GP0
Y
Y
GP1
Y
Y
GP2
N
N
GP3
Y(1)
Y
GP4
N
N
GP5
N
N
GP6
N
N
Note 1: When MCLRE = 1, the weak pull-up on GP3/MCLR is always
enabled.
2: WPU = Weak pull-up; WU = Wake-up.
© 2008 Microchip Technology Inc.
DS41319B-page 23
PIC12F519
REGISTER 6-1:
GPIO: GPIO REGISTER
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
GP5
GP4
GP3
GP2
GP1
GP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
GP: GPIO I/O Pin bits
1 = GPIO pin is >VIH min.
0 = GPIO pin is 4.5V, C1 = C2 ≈ 30 pF is
recommended.
Component values shown are for design
guidance only. Rs may be required to
avoid overdriving crystals with low drive
level specification. Since each crystal has
its own characteristics, the user should
consult the crystal manufacturer for
appropriate values of external components.
To internal
logic
C2(1)
Note 1:
2:
3:
See Capacitor Selection tables for
recommended values of C1 and C2.
A series resistor (RS) may be required for AT
strip cut crystals.
RF approx. value = 10 MΩ.
© 2008 Microchip Technology Inc.
DS41319B-page 39
PIC12F519
8.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators provide
a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 8-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a
parallel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator designs.
FIGURE 8-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
CLKIN
74AS04
8.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC circuit option
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, especially
for low CEXT values. The user also needs to take into
account variation due to tolerance of external R and C
components used.
Figure 8-5 shows how the R/C combination is
connected to the PIC12F519 device. For REXT values
below 3.0 kΩ, the oscillator operation may become
unstable, or stop completely. For very high REXT values
(e.g., 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. It is recommended keeping REXT
between 5.0 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), it is recommended using
values above 20 pF for noise and stability reasons. With
no or small external capacitance, the oscillation
frequency can vary dramatically due to changes in
external capacitances, such as PCB trace capacitance
or package lead frame capacitance. See Figure 11-1
and Figure 11-2.
PIC12F519
FIGURE 8-5:
10k
XTAL
EXTERNAL RC
OSCILLATOR MODE
VDD
10k
REXT
20 pF
20 pF
OSC1
Figure 8-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330Ω resistors provide the negative
feedback to bias the inverters in their linear region.
CEXT
330
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To Other
Devices
330
74AS04
74AS04
74AS04
CLKIN
0.1 mF
XTAL
DS41319B-page 40
PIC12F519
N
PIC16F519
VSS
8.2.5
FIGURE 8-4:
Internal
clock
INTERNAL 4/8 MHz RC
OSCILLATOR
The internal RC oscillator provides a fixed 4/8 MHz
(nominal) system clock at VDD = 3.5V and 25°C, (see
Section 11.0
“Electrical
Characteristics”
for
information on variation over voltage and temperature).
In addition, a calibration instruction is programmed into
the last address of memory, which contains the
calibration value for the internal RC oscillator. This
location is always non-code protected, regardless of the
code-protect settings. This value is programmed as a
MOVLW XX instruction where XX is the calibration value,
and is placed at the Reset vector. This will load the W
register with the calibration value upon Reset and the
© 2008 Microchip Technology Inc.
PIC12F519
PC will then roll over to the users program at address
0x000. The user then has the option of writing the value
to the OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
Note:
Erasing the device will also erase the
pre-programmed internal calibration value
for the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
For the PIC12F519 device, only bits of OSCCAL
are used for calibration. See Register 4-3 for more
information.
Note:
The bit 0 of the OSCCAL register is
unimplemented and should be written as
‘0’ when modifying OSCCAL for
compatibility with future devices.
TABLE 8-3:
Register
8.3
Reset
The device differentiates between various kinds of
Reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Time-out Reset during normal operation
WDT Time-out Reset during Sleep
Wake-up from Sleep on pin change
Some registers are not reset in any way, and they are
unknown on Power-on Reset (POR) and unchanged in
any other Reset. Most other registers are reset to
“Reset state” on Power-on Reset (POR), MCLR, WDT
or Wake-up on pin change Reset during normal
operation. They are not affected by a WDT Reset
during Sleep or MCLR Reset during Sleep, since these
Resets are viewed as resumption of normal operation.
The exceptions to this are TO, PD and GPWUF bits.
They are set or cleared differently in different Reset
situations. These bits are used in software to determine
the nature of Reset. See Table 8-3 for a full description
of Reset states of all registers.
RESET CONDITIONS FOR REGISTERS
Address
W
—
Power-on Reset
MCLR Reset, WDT Time-out,
Wake-up On Pin Change
qqqq qqq0(1)
qqqq qqq0(1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
1111 1111
STATUS
03h
0-01 1xxx
q-0q quuu(2), (3)
FSR
04h
110x xxxx
11uu uuuu
OSCCAL
05h
1111 111-
uuuu uuu-
PORTB
06h
--xx xxxx
--uu uuuu
OPTION
—
1111 1111
1111 1111
TRIS
—
--11 1111
--11 1111
EECON
21h
---0 x000
---0 q000
EEDATA
25h
xxxx xxxx
uuuu uuuu
EEADR
26h
--xx xxxx
--uu uuuu
Legend:
Note 1:
2:
3:
u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Bits of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory.
See Table 8-4 for Reset value for specific conditions.
If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
© 2008 Microchip Technology Inc.
DS41319B-page 41
PIC12F519
TABLE 8-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
Power-on Reset
0-01 1xxx
MCLR Reset during normal operation
0-0u uuuu
MCLR Reset during Sleep
0-01 0uuu
WDT Reset during Sleep
0-00 0uuu
WDT Reset normal operation
0-00 uuuu
Wake-up from Sleep on pin change
1-01 0uuu
Legend: u = unchanged, x = unknown
8.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 8-6.
FIGURE 8-6:
MCLR SELECT
GPPU
GP3/MCLR/VPP
MCLRE
8.4
Internal MCLR
Power-on Reset (POR)
The PIC12F519 device incorporates an on-chip
Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the internal POR,
program the GP3/MCLR/VPP pin as MCLR and tie
through a resistor to VDD, or program the pin as GP3, in
which case, an internal weak pull-up resistor is
implemented using a transistor (refer to Table 11-4 for
the pull-up resistor ranges). This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for VDD is specified. See
Section 11.0 “Electrical Characteristics” for details.
The Power-on Reset circuit and the Device Reset Timer
(see Section 8.5 “Device Reset Timer (DRT)”) circuit
are closely related. On power-up, the Reset latch is set
and the DRT is reset. The DRT timer begins counting
once it detects MCLR to be high. After the time-out
period, which is typically 18 ms or 1 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 8-8. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT after MCLR goes high.
In Figure 8-9, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be GP3). The VDD is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 8-10 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, VDD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-9).
Note:
When the devices start normal operation
(exit the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Note
AN522, “Power-Up Considerations” (DS00522)
When the devices start normal operation (exit the Reset
condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-7.
DS41319B-page 42
© 2008 Microchip Technology Inc.
PIC12F519
FIGURE 8-7:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
GP3/MCLR/VPP
MCLR Reset
MCLRE
Start-up Timer
WDT Reset
WDT Time-out
Pin Change
Sleep
S
Q
R
Q
(10 μs, 1 ms
or 18 ms)
CHIP Reset
Wake-up on pin Change Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
FIGURE 8-8:
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
FIGURE 8-9:
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
© 2008 Microchip Technology Inc.
DS41319B-page 43
PIC12F519
FIGURE 8-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
DS41319B-page 44
© 2008 Microchip Technology Inc.
PIC12F519
8.5
Device Reset Timer (DRT)
On the PIC12F519 device, the DRT runs any time the
device is powered up. DRT runs from Reset and varies
based on oscillator selection and Reset type (see
Table 8-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the devices in a Reset condition after MCLR has
reached a logic high (VIH MCLR) level. Programming
GP3/MCLR/VPP as MCLR and using an external RC
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/or
space restricted applications, as well as allowing the
use of the GP3/MCLR/VPP pin as a general purpose
input.
The Device Reset Time delays will vary from
chip-to-chip due to VDD, temperature and process
variation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.8.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 8-5:
DRT (DEVICE RESET TIMER
PERIOD)
Oscillator
Configuration
POR Reset
Subsequent
Resets
INTOSC, EXTRC
1 ms (typical)
10 μs (typical)
LP, XT
18 ms (typical)
18 ms (typical)
© 2008 Microchip Technology Inc.
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5)/OSC1/CLKIN pin
and the internal 4 or 8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by
programming the configuration WDTE as a ‘0’ (see
Section 8.1 “Configuration Bits”). Refer to the
PIC12F519 Programming Specification (DS41316) to
determine how to access the Configuration Word.
8.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writing
to the OPTION register. Thus, a time-out period of a
nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
DS41319B-page 45
PIC12F519
FIGURE 8-11:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 7-1)
0
Watchdog
Time
1
M
U
X
Postscaler
8-to-1 MUX
PS
PSA
WDT Enable
Configuration
Bit
To Timer0 (Figure 7-3)
0
1
MUX
PSA
WDT Time-out
Note 1:
TABLE 8-6:
Name
OPTION
Legend:
PSA, PS are bits in the OPTION register.
SUMMARY OF REGISTER ASSOCIATED WITH THE WATCHDOG TIMER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Shaded boxes = Not used by Watchdog Timer.
DS41319B-page 46
© 2008 Microchip Technology Inc.
PIC12F519
8.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF)
The TO, PD and (GPWUF) bits in the STATUS register
can be tested to determine if a Reset condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
8.8.2
The device can wake-up from Sleep through one of the
following events:
5.
6.
7.
TABLE 8-7:
TO/PD/(GPWUF) STATUS
AFTER RESET
GPWUF
TO
PD
Reset Caused By
0
0
0
WDT wake-up from Sleep
0
0
u
WDT time-out (not from
Sleep)
0
1
0
MCLR wake-up from Sleep
0
1
1
Power-up
0
u
u
MCLR not during Sleep
1
1
0
Wake-up from Sleep on pin
change
Legend: u = unchanged
Note 1: The TO, PD and GPWUF bits maintain
their status (u) until a Reset occurs. A
low-pulse on the MCLR input does not
change the TO, PD and GPWUF Status
bits.
8.8
WAKE-UP FROM SLEEP
An external Reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
A Watchdog Timer Time-out Reset (if WDT was
enabled).
A change on input pin GP0, GP1 and GP3 when
wake-up on change is enabled.
These events cause a device Reset. The TO, PD and
GPWUF bits can be used to determine the cause of
device Reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
Sleep at pins GP0, GP1 and GP3 (since the last file or
bit operation on GPIO port).
Note:
Caution: Right before entering Sleep,
read the input pins. When in Sleep, wake
up occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before
re-entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
8.8.1
SLEEP
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS) is set, the PD
bit (STATUS) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
Note:
A Reset generated by a WDT time-out
does not drive the MCLR pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
GP3/MCLR/VPP pin must be at a logic high level if
MCLR is enabled.
© 2008 Microchip Technology Inc.
DS41319B-page 47
PIC12F519
8.9
Program Verification/Code
Protection
FIGURE 8-12:
If the code protection bits have not been programmed,
the on-chip program and data memory can be read out
for verification purposes.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the setting of the program
memory’s code protection bit. If the code protect bit
specific to the FLASH data memory is programmed,
then none of the contents of this memory region can be
verified externally.
8.10
ID Locations
Four memory locations are designated as ID locations
where users can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations. The upper
bits should be programmed as 0s.
8.11
External
Connector
Signals
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
PIC12F519
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1/ICSPCLK
Data
GP0/ICSPDAT
VDD
To Normal
Connections
In-Circuit Serial Programming™
The PIC12F519 device can be serially programmed
while in the end application circuit. This is simply done
with two lines for clock and data, and three other lines
for power, ground and the programming voltage. This
allows
users
to
manufacture
boards
with
unprogrammed PIC12F519 device and then program
the PIC12F519 device just before shipping the product.
This also allows the most recent firmware, or a custom
firmware, to be programmed.
The PIC12F519 device is placed into a Program/Verify
mode by holding the GP1 and GP0 pins low while
raising the MCLR (VPP) pin from VIL to VIHH (see
programming specification). The GP1 pin becomes the
programming clock, and the GP0 pin becomes the
programming data. Both GP1 and GP0 pins are Schmitt
Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. Depending on the command, 14 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
details of serial programming, please refer to the
“PIC12F519 Memory Programming Specification,”
(DS41316).
A typical In-Circuit Serial Programming connection is
shown in Figure 8-12.
DS41319B-page 48
© 2008 Microchip Technology Inc.
PIC12F519
9.0
INSTRUCTION SET SUMMARY
The PIC12F519 instruction set is highly orthogonal and
is comprised of three basic categories.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC12F519 instruction is a 12-bit word divided
into an opcode, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The formats for each of the
categories is presented in Figure 9-1, while the various
opcode fields are summarized in Table 9-1.
For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
TABLE 9-1:
Description
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility with
all Microchip software tools.
d
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label
Label name
TOS
Top-of-Stack
PC
WDT
TO
Power-down bit
[
]
Options
(
)
Contents
italics
FIGURE 9-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
11
6
OPCODE
5
d
4
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11
OPCODE
8 7
5 4
b (BIT #)
0
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations – GOTO instruction
11
9
8
OPCODE
0
k (literal)
k = 9-bit immediate value
Watchdog Timer counter
Destination, either the W register or the specified
register file location
∈
where ‘h’ signifies a hexadecimal digit.
Time-out bit
PD
< >
0xhhh
Program Counter
dest
→
Figure 9-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
OPCODE FIELD
DESCRIPTIONS
Field
f
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 μs. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 μs.
Assigned to
Register bit field
In the set of
User defined term (font is courier)
© 2008 Microchip Technology Inc.
DS41319B-page 49
PIC12F519
TABLE 9-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
12-Bit Opcode
Description
Cycles
MSb
LSb
Status
Notes
Affected
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
0001 11df ffff C, DC, Z 1, 2, 4
Add W and f
1
0001 01df ffff
AND W with f
1
Z
2, 4
0000 011f ffff
Clear f
1
Z
4
0000 0100 0000
Clear W
1
Z
0010 01df ffff
Complement f
1
Z
0000 11df ffff
Decrement f
1
Z
2, 4
0010 11df ffff
Decrement f, Skip if 0
1(2)
None
2, 4
1
0010 10df ffff
Increment f
Z
2, 4
1(2)
0011 11df ffff
Increment f, Skip if 0
None
2, 4
1
0001 00df ffff
Inclusive OR W with f
Z
2, 4
1
0010 00df ffff
Move f
Z
2, 4
1
0000 001f ffff
Move W to f
None
1, 4
1
0000 0000 0000
No Operation
None
1
0011 01df ffff
Rotate left f through Carry
C
2, 4
1
0011 00df ffff
Rotate right f through Carry
C
2, 4
1
0000 10df ffff C, DC, Z 1, 2, 4
Subtract W from f
1
0011 10df ffff
Swap f
None
2, 4
1
0001 10df ffff
Exclusive OR W with f
Z
2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
0100 bbbf ffff
None
2, 4
1
Bit Clear f
BCF
f, b
0101 bbbf ffff
None
2, 4
1
Bit Set f
BSF
f, b
0110 bbbf ffff
None
Bit Test f, Skip if Clear
1(2)
BTFSC
f, b
1(2)
0111 bbbf ffff
None
f, b
Bit Test f, Skip if Set
BTFSS
LITERAL AND CONTROL OPERATIONS
ANDLW
k
AND literal with W
1
1110 kkkk kkkk
Z
CALL
1
k
Call Subroutine
2
1001 kkkk kkkk
None
CLRWDT
–
Clear Watchdog Timer
1
0000 0000 0100 TO, PD
None
GOTO
k
Unconditional branch
2
101k kkkk kkkk
Z
IORLW
k
Inclusive OR literal with W
1
1101 kkkk kkkk
None
MOVLW
k
Move literal to W
1
1100 kkkk kkkk
None
OPTION
–
Load OPTION register
1
0000 0000 0010
None
RETLW
k
Return, place literal in W
2
1000 kkkk kkkk
SLEEP
–
Go into Standby mode
1
0000 0000 0011 TO, PD
None
3
TRISGPIO f
Load TRISGPIO register
1
0000 0000 0fff
Z
XORLW
k
Exclusive OR literal to W
1
1111 kkkk kkkk
Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.6 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of GPIO. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS41319B-page 50
© 2008 Microchip Technology Inc.
PIC12F519
ADDWF
Add W and f
BCF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
(W) + (f) → (dest)
Operation:
0 → (f)
Status Affected: C, DC, Z
Status Affected:
None
Description:
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 31
0≤b≤7
Status Affected: Z
Operation:
1 → (f)
Description:
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Status Affected:
None
ANDWF
AND W with f
BTFSC
Syntax:
[ label ] ANDWF
ANDLW
Syntax:
f,d
Bit Clear f
Add the contents of the W register
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
AND literal with W
[ label ] ANDLW
k
Operands:
0 ≤ k ≤ 255
Operation:
(W).AND. (k) → (W)
f,d
f,b
f,b
Description: Bit ‘b’ in register ‘f’ is set.
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 31
0≤b≤7
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
Operation:
(W) .AND. (f) → (dest)
Operation:
skip if (f) = 0
Status Affected: Z
Status Affected:
None
Description:
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruction fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a two-cycle instruction.
The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
© 2008 Microchip Technology Inc.
DS41319B-page 51
PIC12F519
BTFSS
Bit Test f, Skip if Set
CLRW
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRW
0 ≤ f ≤ 31
0≤b VDD)...................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA
Max. output current sunk by any I/O pin .............................................................................................................. 25 mA
Max. output current sourced by any I/O pin ......................................................................................................... 25 mA
Max. output current sourced by I/O port .............................................................................................................. 75 mA
Max. output current sunk by I/O port ................................................................................................................... 75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2008 Microchip Technology Inc.
DS41319B-page 61
PIC12F519
PIC12F519 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
FIGURE 11-1:
6.0
INTOSC ONLY
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
8
4
10
20
25
Frequency (MHz)
FIGURE 11-2:
MAXIMUM OSCILLATOR FREQUENCY TABLE
Oscillator Mode
LP
XT
EXTRC
INTOSC
0
200 kHz
4 MHz
8 MHz
Frequency (MHz)
DS41319B-page 62
© 2008 Microchip Technology Inc.
PIC12F519
11.1
DC Characteristics
TABLE 11-1:
DC CHARACTERISTICS: PIC12F519 (INDUSTRIAL)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
DC CHARACTERISTICS
Param
Sym.
No.
D001
VDD
Characteristic
Min.
Typ(1) Max.
2.0
Supply Voltage
(2)
Units
Conditions
5.5
V
See Figure 11-1
D002
VDR
RAM Data Retention Voltage
—
1.5*
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 8.4 “Power-on
Reset (POR)” for details
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 8.4 “Power-on
Reset (POR)” for details
D005
IDDP
Supply Current During Prog/
Erase.
—
250*
—
μA
D010
IDD
Supply Current(3,4)
—
—
175
400
250
700
μA
μA
FOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
—
—
250
0.75
400
1.2
μA
mA
FOSC = 8 MHz, VDD = 2.0V
FOSC = 8 MHz, VDD = 5.0V
—
—
11
38
20
54
μA
μA
FOSC = 32 kHz, VDD = 2.0V
FOSC = 32 kHz, VDD = 5.0V
D020
IPD
Power-down Current(5)
—
—
0.1
0.35
1.2
2.2
μA
μA
VDD = 2.0V
VDD = 5.0V
D022
IWDT
WDT Current
—
—
1.0
7.0
3.0
16.0
μA
μA
VDD = 2.0V
VDD = 5.0V
*
Note 1:
2:
3:
4:
5:
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail for external clock modes; all I/O pins tri-stated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
© 2008 Microchip Technology Inc.
DS41319B-page 63
PIC12F519
TABLE 11-2:
DC CHARACTERISTICS: PIC12F519 (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +125°C (extended)
DC CHARACTERISTICS
Param
Sym.
No.
D001
VDD
Characteristic
Min.
Typ(1) Max.
2.0
Supply Voltage
(2)
5.5
Units
V
Conditions
See Figure 11-1
D002
VDR
RAM Data Retention Voltage
—
1.5*
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 8.4 “Power-on
Reset (POR)” for details
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 8.4 “Power-on
Reset (POR)” for details
D005
IDDP
Supply Current During Prog/
Erase.
—
250*
—
μA
D010
IDD
Supply Current(3,4)
—
—
175
400
250
700
μA
mA
FOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
—
—
250
0.75
400
1.2
μA
mA
FOSC = 8 MHz, VDD = 2.0V
FOSC = 8 MHz, VDD = 5.0V
—
—
11
38
24
110
μA
μA
FOSC = 32 kHz, VDD = 2.0V
FOSC = 32 kHz, VDD = 5.0V
D020
IPD
Power-down Current(5)
—
—
0.1
0.35
9.0
15.0
μA
μA
VDD = 2.0V
VDD = 5.0V
D022
IWDT
WDT Current
—
—
1.0
7.0
18
22
μA
μA
VDD = 2.0V
VDD = 5.0V
*
Note 1:
2:
3:
4:
5:
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail for external clock modes; all I/O pins tri-stated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
DS41319B-page 64
© 2008 Microchip Technology Inc.
PIC12F519
TABLE 11-3:
DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
-40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating voltage VDD range as described in DC specification.
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Min.
Typ†
Max.
Units
Conditions
Input Low Voltage
I/O ports
D030
with TTL buffer
D030A
Vss
—
0.8
V
For all 4.5 ≤ VDD ≤ 5.5V
Vss
—
0.15 VDD
V
Otherwise
D031
with Schmitt Trigger buffer
Vss
—
0.15 VDD
V
D032
MCLR, T0CKI
Vss
—
0.15 VDD
V
D033
OSC1 (EXTRC mode)
Vss
—
0.15 VDD
V
D033A
OSC1 (XT and LP modes)
Vss
—
0.3
V
2.0
—
VDD
V
4.5 ≤ VDD ≤ 5.5V
0.25 VDD
+ 0.8V
—
VDD
V
Otherwise
For entire VDD range
VIH
Input High Voltage
I/O ports
D040
—
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
0.85 VDD
—
VDD
V
D042
MCLR, T0CKI
0.85 VDD
—
VDD
V
D042A
OSC1 (EXTRC mode)
0.85 VDD
—
VDD
V
D043
OSC1 (XT and LP modes)
1.6
—
VDD
V
IPUR
I/O PORT weak pull-up current(5)
50
250
400
μA
IIL
Input Leakage Current(2), (3)
D070
(Note 1)
(Note 1)
VDD = 5V, VPIN = VSS
D060
I/O ports
—
—
±1
μA
Vss ≤ VPIN ≤ VDD, Pin at high-impedance
D061
GP3/MCLR(4)
—
±0.7
±5
μA
Vss ≤ VPIN ≤ VDD
D063
OSC1
—
—
±5
μA
Vss ≤ VPIN ≤ VDD, XT and LP osc configuration
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V, –40°C to +85°C
—
—
0.6
V
IOL = 7.0 mA, VDD = 4.5V, –40°C to +125°C
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V, –40°C to +85°C
VDD – 0.7
—
—
V
IOH = -2.5 mA, VDD = 4.5V, –40°C to +125°C
—
50
pF
Output Low Voltage
D080
I/O ports
D080A
Output High Voltage
I/O ports(3)
D090
D090A
Capacitive Loading Specs on Output Pins
D101
All I/O pins
—
Flash Data Memory
D120
ED
Byte endurance
100K
1M
—
E/W
–40°C ≤ TA ≤ +85°C
D120A
ED
Byte endurance
10K
100K
—
E/W
+85°C ≤ TA ≤ +125°C
D121
VDRW VDD for read/write
VMIN
—
5.5
V
Note
†
1:
2:
3:
4:
5:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F519 be driven
with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
This specification applies to GP3/MCLR configured as GP3 with internal pull-up disabled.
This specification applies to all weak pull-up devices, including the weak pull-up found on GP3/MCLR. The current value listed will be the
same whether or not the pin is configured as GP3 with pull-up enabled or MCLR.
© 2008 Microchip Technology Inc.
DS41319B-page 65
PIC12F519
TABLE 11-4:
VDD (Volts)
GP0/GP1
2.0
5.5
GP3
2.0
5.5
DS41319B-page 66
PULL-UP RESISTOR RANGES
Temperature
(°C)
Min.
Typ.
Max.
Units
–40
25
85
125
–40
25
85
125
73K
73K
82K
86K
15K
15K
19K
23K
105K
113K
123K
132K
21K
22K
26K
29K
186K
187K
190K
190K
33K
34K
35K
35K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
–40
25
85
125
–40
25
85
125
63K
77K
82K
86K
16K
16K
24K
26K
81K
93K
96K
100K
20K
21K
25K
27K
96K
116K
116K
119K
22K
23K
28K
29K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
© 2008 Microchip Technology Inc.
PIC12F519
11.2
Timing Parameter Symbology and Load Conditions – PIC12F519
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency
T Time
Lowercase subscripts (pp) and their meanings:
pp
2
to
mc
MCLR
ck
CLKOUT
osc
Oscillator
cy
Cycle time
os
OSC1
drt
Device Reset Timer
t0
T0CKI
io
I/O port
wdt
Watchdog Timer
Uppercase letters and their meanings:
S
F
Fall
P
Period
H
High
R
Rise
I
Invalid (high-impedance)
V
Valid
L
Low
Z
High-impedance
FIGURE 11-3:
LOAD CONDITIONS – PIC12F519
Legend:
CL
pin
CL = 50 pF for all pins except OSC2
15 pF for OSC2 in XT or LP modes
when external clock is used
to drive OSC1
VSS
FIGURE 11-4:
EXTERNAL CLOCK TIMING – PIC12F519
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
© 2008 Microchip Technology Inc.
DS41319B-page 67
PIC12F519
11.3
AC Characteristics
TABLE 11-5:
EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 11.0 “Electrical Characteristics”
Param
No.
Sym.
Characteristic
Min.
Typ(1)
1A
FOSC
External CLKIN Frequency(2)
DC
—
4
DC
—
200
DC
—
4
MHz EXTRC Oscillator mode
0.1
—
4
MHz XT Oscillator mode
Oscillator Frequency
1
TOSC
(2)
Max.
Units
Conditions
MHz XT Oscillator mode
kHz
LP Oscillator mode
DC
—
200
kHz
LP Oscillator mode
External CLKIN Period(2)
250
—
—
ns
XT Oscillator mode
5
—
—
μs
LP Oscillator mode
Oscillator Period(2)
250
—
—
ns
EXTRC Oscillator mode
250
—
10,000
ns
XT Oscillator mode
5
—
—
μs
LP Oscillator mode
2
TCY
Instruction Cycle Time
200
4/FOSC
DC
ns
3
TosL,
TosH
Clock in (OSC1) Low or High
Time
50*
—
—
ns
2*
—
—
μs
LP Oscillator
4
TosR,
TosF
Clock in (OSC1) Rise or Fall
Time
—
—
25*
ns
XT Oscillator
—
—
50*
ns
LP Oscillator
*
Note 1:
2:
XT Oscillator
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. When an external clock
input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41319B-page 68
© 2008 Microchip Technology Inc.
PIC12F519
TABLE 11-6:
CALIBRATED INTERNAL RC FREQUENCIES
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
-40°C ≤ TA ≤ +85°C (industrial),
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Param
No.
Freq.
Min.
Tolerance
F10
Sym.
FOSC
Characteristic
Internal Calibrated
INTOSC Frequency(1)
Typ†
Max.
Units
Conditions
±1%
7.92
8.00
8.08
MHz 3.5V, 25C
±2%
7.84
8.00
8.16
MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
±5%
7.60
8.00
8.40
MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
FIGURE 11-5:
I/O TIMING
Q1
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
19
18
New Value
Old Value
20, 21
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
© 2008 Microchip Technology Inc.
DS41319B-page 69
PIC12F519
TABLE 11-7:
TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
AC CHARACTERISTICS
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in
Param
No.
Sym.
Characteristic
Min.
Typ(1)
Max.
Units
17
TOSH2IOV
OSC1↑ (Q1 cycle) to Port Out Valid(2), (3)
—
—
100*
ns
18
TOSH2IOI
OSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hold
time)(2)
50
—
—
ns
19
TIOV2OSH
Port Input Valid to OSC1↑ (I/O in setup time)
20
—
—
ns
20
TIOR
Port Output Rise Time(3)
—
10
50**
ns
—
10
50**
ns
TIOF
21
Port Output Fall Time
(3)
TBD = To be determined.
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 11-3 for loading conditions.
FIGURE 11-6:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out(2)
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pin(1)
Note 1:
2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
Runs in MCLR or WDT Reset only in XT and LP.
DS41319B-page 70
© 2008 Microchip Technology Inc.
PIC12F519
TABLE 11-8:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F519
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in
Section TABLE 11-3: “DC CHARACTERISTICS: PIC12F519
(Industrial, Extended)”
AC CHARACTERISTICS
Param
No.
Units
Conditions
Min.
2000*
—
—
ns
VDD = 5.0V
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
9*
9*
18*
18*
30*
40*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
0.5*
0.5*
1.125*
1.125*
2*
2.5*
ms
ms
VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
—
—
2000*
ns
30
TMCL
MCLR Pulse Width (low)
TWDT
Watchdog Timer Time-out Period
(no prescaler)
32
TDRT
Device Reset Timer Period
Standard
Short
TIOZ
*
Note 1:
Max.
Characteristic
31
34
Typ(1)
Sym.
I/O High-impedance from MCLR
low
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
TABLE 11-9:
DRT (DEVICE RESET TIMER PERIOD)
Oscillator Configuration
POR Reset
Subsequent Resets
IntRC and ExtRC
1 ms (typical)
10 μs (typical)
XT and LP
18 ms (typical)
18 ms (typical)
FIGURE 11-7:
TIMER0 CLOCK TIMINGS
T0CKI
40
41
42
© 2008 Microchip Technology Inc.
DS41319B-page 71
PIC12F519
TABLE 11-10: TIMER0 CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in
Section TABLE 11-3: “DC CHARACTERISTICS: PIC12F519 (Industrial,
Extended)”
AC CHARACTERISTICS
Param
Sym.
No.
Characteristic
40
Tt0H
T0CKI High Pulse
Width
41
Tt0L
T0CKI Low Pulse
Width
42
Tt0P
T0CKI Period
*
Note 1:
Min.
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20*
10*
0.5 TCY + 20*
10*
20 or TCY + 40* N
Typ(1) Max. Units
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
Conditions
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
TABLE 11-11: FLASH DATA MEMORY WRITE/ERASE REQUIREMENTS
AC CHARACTERISTICS
Param
Sym.
No.
43
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in
Section TABLE 11-3: “DC CHARACTERISTICS: PIC12F519 (Industrial,
Extended)”
Min.
Typ(1)
Max.
Units
Conditions
TDW
Flash Data Memory
2
3.5
5
ms
Write Cycle Time
Flash Data Memory
2
3
4
ms
44
TDE
Erase Cycle Time
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS41319B-page 72
© 2008 Microchip Technology Inc.
PIC12F519
12.0
DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Note:
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or
(mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.
FIGURE 12-1:
TYPICAL IDD vs. FOSC OVER VDD (XT, EXTRC mode)
800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
700
600
IDD (μA)
500
5V
400
300
200
2V
100
0
1
0
3
2
5
4
FOSC (MHz)
MAXIMUM IDD vs. FOSC OVER VDD (XT, EXTRC mode)
FIGURE 12-2:
800
5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
700
600
IDD (μA)
500
400
300
2V
200
100
0
0
1
3
2
4
5
FOSC (MHz)
© 2008 Microchip Technology Inc.
DS41319B-page 73
PIC12F519
FIGURE 12-3:
IDD vs. VDD OVER FOSC (LP MODE)
120
Typical: Statistical Mean @25°C
Industrial: Mean (Worst-Case Temp) + 3σ
(-40°C to 85°C)
Extended: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
100
32 kHz Maximum Extended
IDD (μA)
80
60
32 kHz Maximum Industrial
32 kHz Typical
40
20
0
1
2
3
4
5
6
VDD (V)
DS41319B-page 74
© 2008 Microchip Technology Inc.
PIC12F519
FIGURE 12-4:
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
0.45
0.40
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
0.35
IPD (μA)
0.30
0.25
0.20
0.15
0.10
0.05
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 12-5:
18.0
16.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
14.0
Max. 125°C
IPD (μA)
12.0
10.0
8.0
6.0
4.0
Max. 85°C
2.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41319B-page 75
PIC12F519
FIGURE 12-6:
TYPICAL WDT IPD vs. VDD
9
8
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
7
IPD (μA)
6
5
4
3
2
1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 12-7:
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
25.0
20.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
IPD (μA)
Max. 125°C
15.0
10.0
Max. 85°C
5.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41319B-page 76
© 2008 Microchip Technology Inc.
PIC12F519
FIGURE 12-8:
WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)
50
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
Max. 125°C
45
40
Max. 85°C
35
Time (ms)
30
Typical. 25°C
25
20
Min. -40°C
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 12-9:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
0.8
0.7
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
Max. 125°C
0.6
VOL (V)
0.5
Max. 85°C
0.4
Typical 25°C
0.3
0.2
Min. -40°C
0.1
0.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
© 2008 Microchip Technology Inc.
DS41319B-page 77
PIC12F519
FIGURE 12-10:
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.45
Typical: Statistical Mean @25°C
Typical:
Statistical
Mean @25×C
Maximum:
Mean
(Worst-Case
Temp) + 3σ
Maximum: Meas(-40×C
+ 3 to 125×C)
(-40°C to 125°C)
0.40
Max. 125°C
0.35
Max. 85°C
VOL (V)
0.30
0.25
Typ. 25°C
0.20
0.15
Min. -40°C
0.10
0.05
0.00
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 12-11:
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.5
3.0
Max. -40°C
Typ. 25°C
2.5
Min. 125°C
VOH (V)
2.0
1.5
1.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
DS41319B-page 78
© 2008 Microchip Technology Inc.
PIC12F519
FIGURE 12-12:
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
5.5
5.0
Max. -40°C
Typ. 25°C
VOH (V)
4.5
Min. 125°C
4.0
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
FIGURE 12-13:
TTL INPUT THRESHOLD VIN vs. VDD
1.7
1.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
Max. -40°C
VIN (V)
1.3
Typ. 25°C
1.1
Min. 125°C
0.9
0.7
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41319B-page 79
PIC12F519
FIGURE 12-14:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
4.0
VIH Max. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3σ
(-40°C to 125°C)
3.5
VIH Min. -40°C
VIN (V)
3.0
2.5
2.0
VIL Max. -40°C
1.5
VIL Min. 125°C
1.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 12-15:
DEVICE RESET TIMER (XT AND LP) vs. VDD
45
40
35
Max. 125°C
DRT (ms)
30
25
Max. 85°C
20
Typical 25°C
15
Min. -40°C
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41319B-page 80
© 2008 Microchip Technology Inc.
PIC12F519
13.0
PACKAGING INFORMATION
13.1
Package Marking Information
8-Lead PDIP
Example
12F519-I
/P017
0610
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (3.90 mm)
XXXXXXXX
XXXXYYWW
NNN
8-Lead MSOP
XXXXXX
YWWNNN
8-Lead 2x3 DFN*
XXX
YWW
NN
e3
*
*
12F519-I
/SN0610
017
Example
519/MS
610017
Example
BY0
610
17
Legend: XX...X
Y
YY
WW
NNN
Note:
Example
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
© 2008 Microchip Technology Inc.
DS41319B-page 81
PIC12F519
3
& '
!&" & 4 # *!( !!&
4 % &
&# &
&& 255***'
'5 4
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
6&!
'!
9'&!
7"')
% !
7,8.
7
7
7:
;
<
&
&
&
=
=
## 4
4!!
-
1 !&
&
=
=
"# &
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.
-
-
## 4 >#&
.
#&
9
* 9 #>#&
:
* +
1,
-
!" #$% &" ' ()"&'"!&)
&#*& & & #
+% &, & !&
- '!
! #. #
&"#'
#% !
& "!
!
#% !
& "!
!!
&$# / !#
'!
#&
.0
1,21 !'!
& $ & "!
**&
"&&
!
* , #&
.
=
)
-
,
& &9&
9
-
,
& &&
.$
!# #
C
=
=
,
& &>#&
1,
-1,
!" #$% &" ' ()"&'"!&)
&#*& & & #
4 '
'
$
!#&) ! &#!
- 4 !! *!" &#
'!
#&
.0
1,2 1 !'!
& $ & "!
**&
"&&
!
.32 % '!
("!" *&
"&&
(%
%
' &
"
!!
* , -,
DS41319B-page 86
© 2008 Microchip Technology Inc.
PIC12F519
+
$ )*(',--%& +
3
& '
!&" & 4 # *!( !!&
4 % &
&# &
&& 255***'
'5 4
© 2008 Microchip Technology Inc.
DS41319B-page 87
PIC12F519
APPENDIX A:
REVISION HISTORY
Revision A (May 2007)
Original release of this document.
Revision B (September 2008)
Added DC and AC Characteristics graphs; Updated
Electrical Characteristics section; Updated Package
Drawings and made general edits.
DS41319B-page 88
© 2008 Microchip Technology Inc.
PIC12F519
INDEX
A
M
ALU ....................................................................................... 9
Assembler
MPASM Assembler..................................................... 58
Memory Map
PIC12F519 ................................................................. 13
Memory Organization ......................................................... 13
Data EEPROM Memory ............................................. 21
Program Memory (PIC12F519) .................................. 13
Microchip Internet Web Site................................................ 91
MPLAB ASM30 Assembler, Linker, Librarian ..................... 58
MPLAB ICD 2 In-Circuit Debugger ..................................... 59
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator...................................................... 59
MPLAB Integrated Development Environment Software.... 57
MPLAB PM3 Device Programmer ...................................... 59
MPLAB REAL ICE In-Circuit Emulator System .................. 59
MPLINK Object Linker/MPLIB Object Librarian .................. 58
B
Block Diagram
On-Chip Reset Circuit ................................................. 43
Timer0......................................................................... 31
TMR0/WDT Prescaler................................................. 35
Watchdog Timer.......................................................... 46
C
C Compilers
MPLAB C18 ................................................................ 58
MPLAB C30 ................................................................ 58
Carry ..................................................................................... 9
Clocking Scheme ................................................................ 12
Code Protection ............................................................ 37, 48
CONFIG1 Register.............................................................. 38
Configuration Bits................................................................ 37
Customer Change Notification Service ............................... 91
Customer Notification Service............................................. 91
Customer Support ............................................................... 91
D
DC and AC Characteristics ................................................. 73
Graphs and Tables ..................................................... 73
Development Support ......................................................... 57
Digit Carry ............................................................................. 9
E
Errata .................................................................................... 3
F
FSR ..................................................................................... 20
FSR Register ...................................................................... 20
Fuses. See Configuration Bits
G
GPIO ................................................................................... 23
I
I/O Interfacing ..................................................................... 25
I/O Port................................................................................ 23
I/O Ports .............................................................................. 23
I/O Programming Considerations........................................ 30
ID Locations .................................................................. 37, 48
INDF.................................................................................... 20
INDF Register ..................................................................... 20
Indirect Data Addressing..................................................... 20
Instruction Cycle ................................................................. 12
Instruction Flow/Pipelining .................................................. 12
Instruction Set Summary..................................................... 50
Internet Address.................................................................. 91
L
Loading of PC ..................................................................... 19
© 2008 Microchip Technology Inc.
O
OPTION Register................................................................ 17
OSC selection..................................................................... 37
OSCCAL Register............................................................... 18
Oscillator Configurations..................................................... 39
Oscillator Types
HS............................................................................... 39
LP ............................................................................... 39
RC .............................................................................. 39
XT ............................................................................... 39
P
PIC12F519 Device Varieties................................................. 7
PICSTART Plus Development Programmer....................... 60
POR
Device Reset Timer (DRT) ................................... 37, 45
PD............................................................................... 47
TO............................................................................... 47
Power-down Mode.............................................................. 47
Prescaler ............................................................................ 34
Program Counter ................................................................ 19
Q
Q cycles .............................................................................. 12
R
RC Oscillator....................................................................... 40
Reader Response............................................................... 92
Read-Modify-Write.............................................................. 30
Register File Map
PIC16C57/CR57......................................................... 14
Registers
CONFIG1 (Configuration Word Register 1)................ 38
Special Function ......................................................... 14
Reset .................................................................................. 37
S
Sleep ............................................................................ 37, 47
Software Simulator (MPLAB SIM) ...................................... 58
Special Features of the CPU .............................................. 37
Special Function Registers ................................................. 14
Stack................................................................................... 19
STATUS Register ........................................................... 9, 16
DS41319B-page 89
PIC12F519
T
Timer0
Timer0 (TMR0) Module ............................................... 31
TMR0 with External Clock........................................... 33
Timing Diagrams and Specifications................................... 67
Timing Parameter Symbology and Load Conditions........... 67
TRIS Registers.................................................................... 23
W
Wake-up from Sleep ........................................................... 47
Watchdog Timer (WDT) ................................................ 37, 45
Period.......................................................................... 45
Programming Considerations ..................................... 45
WWW Address.................................................................... 91
WWW, On-Line Support........................................................ 3
Z
Zero bit .................................................................................. 9
DS41319B-page 90
© 2008 Microchip Technology Inc.
PIC12F519
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2008 Microchip Technology Inc.
DS41319B-page 91
PIC12F519
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC12F519
Y
N
Literature Number: DS41319B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41319B-page 92
© 2008 Microchip Technology Inc.
PIC12F519
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
PIC12F519
PIC12F519T (Tape and Reel)
Temperature
Range:
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package:
MC
MS
P
SN
=
=
=
=
8L DFN 2x3 (DUAL Flatpack No-Leads)
MSOP (Pb-free)
300 mil PDIP (Pb-free)
3.90 mm SOIC, 8-LD (Pb-free)
Pattern:
Special Requirements
Note:
c)
PIC12F519-I/P = Industrial temp., PDIP
package (Pb-free)
PIC12F519T-I/SN = Tape and Reel, Industrial
temp., SOIC package
PIC12F519 - E/MS 303 = Extended temp.,
MSOP package, QTP pattern #303
Tape and Reel available for only the following packages: SOIC, DFN and
MSOP.
© 2008 Microchip Technology Inc.
DS41319B-page 93
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS41319B-page 94
© 2008 Microchip Technology Inc.
