PIC12F609/615/617
PIC12HV609/615
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
2010 Microchip Technology Inc.
DS41302D
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41302D-page 2
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
High-Performance RISC CPU:
Peripheral Features:
• Only 35 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Shunt Voltage Regulator (PIC12HV609/615 only):
- 5 volt regulation
- 4 mA to 50 mA shunt range
• 5 I/O Pins and 1 Input Only
• High Current Source/Sink for Direct LED Drive
- Interrupt-on-pin change or pins
- Individually programmable weak pull-ups
• Analog Comparator module with:
- One analog comparator
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Comparator inputs and output externally
accessible
- Built-In Hysteresis (software selectable)
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode
selected
- Option to use system clock as Timer1
• In-Circuit Serial ProgrammingTM (ICSPTM) via Two
Pins
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency: 4 MHz or
8 MHz
• Power-Saving Sleep mode
• Voltage Range:
- PIC12F609/615/617: 2.0V to 5.5V
- PIC12HV609/615: 2.0V to user defined
maximum (see note)
• Industrial and Extended Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR)
• Watchdog Timer (WDT) with independent
Oscillator for Reliable Operation
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• High Endurance Flash:
- 100,000 write Flash endurance
- Flash retention: > 40 years
• Self Read/ Write Program Memory (PIC12F617
only)
Low-Power Features:
• Standby Current:
- 50 nA @ 2.0V, typical
• Operating Current:
- 11 A @ 32 kHz, 2.0V, typical
- 260 A @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 A @ 2.0V, typical
Note:
PIC12F615/617/HV615 ONLY:
• Enhanced Capture, Compare, PWM module:
- 16-bit Capture, max. resolution 12.5 ns
- Compare, max. resolution 200 ns
- 10-bit PWM with 1 or 2 output channels, 1
output channel programmable “dead time,”
max. frequency 20 kHz, auto-shutdown
• A/D Converter:
- 10-bit resolution and 4 channels, samples
internal voltage references
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
Voltage across the shunt regulator should
not exceed 5V.
2010 Microchip Technology Inc.
DS41302D-page 3
PIC12F609/615/617/12HV609/615
Device
Program
Memory
Data Memory
Flash
(words)
SRAM (bytes)
Self Read/
Self Write
PIC12HV615
1024
64
—
—
—
—
PIC12F617
2048
128
YES
PIC12F609
1024
64
PIC12HV609
1024
64
PIC12F615
1024
64
I/O
10-bit A/D
Comparators ECCP
(ch)
Timers
8/16-bit
Voltage Range
5
0
1
2.0V-5.5V
0
1
—
—
1/1
5
1/1
2.0V-user defined
5
4
1
YES
2/1
2.0V-5.5V
5
4
1
YES
2/1
2.0V-user defined
5
4
1
YES
2/1
2.0V-5.5V
8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)
VDD
1
8
GP5/T1CKI/OSC1/CLKIN
2
GP4/CIN1-/T1G/OSC2/CLKOUT
3
PIC12F609/ 7
HV609
6
GP3/MCLR/VPP
4
5
VSS
GP0/CIN+/ICSPDAT
GP1/CIN0-/ICSPCLK
GP2/T0CKI/INT/COUT
PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
TABLE 1:
I/O
Pin
Comparators
Timer
Interrupts
Pull-ups
Basic
GP0
7
CIN+
—
IOC
Y
ICSPDAT
GP1
6
CIN0-
—
IOC
Y
ICSPCLK
GP2
5
COUT
T0CKI
INT/IOC
Y
—
—
IOC
Y(2)
MCLR/VPP
GP3
(1)
4
—
GP4
3
CIN1-
T1G
IOC
Y
OSC2/CLKOUT
GP5
2
—
T1CKI
IOC
Y
OSC1/CLKIN
—
1
—
—
—
—
VDD
—
8
—
—
—
—
VSS
Note 1:
2:
Input only.
Only when pin is configured for external MCLR.
DS41302D-page 4
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)
VDD
1
8
GP5/T1CKI/P1A*/OSC1/CLKIN
2
GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT
3
PIC12F615/ 7
617/HV615 6
GP3/T1G*/MCLR/VPP
4
5
*
VSS
GP0/AN0/CIN+/P1B/ICSPDAT
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
Alternate pin function.
PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
TABLE 2:
Pin
Analog
Comparator
s
Timer
CCP
Interrupts
Pull-ups
Basic
7
AN0
CIN+
—
P1B
IOC
Y
ICSPDAT
GP1
6
AN1
CIN0-
—
—
IOC
Y
ICSPCLK/VREF
GP2
5
AN2
COUT
T0CKI
CCP1/P1A
INT/IOC
Y
—
IOC
Y(2)
MCLR/VPP
I/O
GP0
(1)
4
—
—
GP4
3
AN3
CIN1-
T1G
P1B*
IOC
Y
OSC2/CLKOUT
GP5
2
—
—
T1CKI
P1A*
IOC
Y
OSC1/CLKIN
—
1
—
—
—
—
—
—
VDD
—
8
—
—
—
—
—
—
VSS
GP3
*
Note 1:
2:
T1G*
—
Alternate pin function.
Input only.
Only when pin is configured for external MCLR.
2010 Microchip Technology Inc.
DS41302D-page 5
PIC12F609/615/617/12HV609/615
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 7
2.0 Memory Organization ................................................................................................................................................................ 11
3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................................................................................. 27
4.0 Oscillator Module ....................................................................................................................................................................... 37
5.0 I/O Port ...................................................................................................................................................................................... 43
6.0 Timer0 Module .......................................................................................................................................................................... 53
7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57
8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65
9.0 Comparator Module ................................................................................................................................................................... 67
10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) ............................................................................... 79
11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ............... 89
12.0 Special Features of the CPU ................................................................................................................................................... 107
13.0 Voltage Regulator .................................................................................................................................................................... 127
14.0 Instruction Set Summary ........................................................................................................................................................ 129
15.0 Development Support ............................................................................................................................................................. 139
16.0 Electrical Specifications ........................................................................................................................................................... 143
17.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 171
18.0 Packaging Information ............................................................................................................................................................ 195
Appendix A: Data Sheet Revision History ......................................................................................................................................... 203
Appendix B: Migrating from other PIC® Devices ............................................................................................................................... 203
Index ................................................................................................................................................................................................. 205
The Microchip Web Site .................................................................................................................................................................... 209
Customer Change Notification Service ............................................................................................................................................. 209
Customer Support ............................................................................................................................................................................. 209
Reader Response ............................................................................................................................................................................. 210
Product Identification System ............................................................................................................................................................ 211
Worldwide Sales and Service ........................................................................................................................................................... 212
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DS41302D-page 6
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
1.0
DEVICE OVERVIEW
Block Diagrams and pinout descriptions of the devices
are as follows:
The PIC12F609/615/617/12HV609/615 devices are
covered by this data sheet. They are available in 8-pin
PDIP, SOIC, MSOP and DFN packages.
FIGURE 1-1:
• PIC12F609/HV609 (Figure 1-1, Table 1-1)
• PIC12F615/617/HV615 (Figure 1-2, Table 1-2)
PIC12F609/HV609 BLOCK DIAGRAM
INT
Configuration
13
8
Data Bus
Program Counter
Flash
1K X 14
Program
Memory
Program
Bus
GP0
GP1
GP2
GP3
GP4
GP5
RAM
64 Bytes
File
Registers
8-Level Stack
(13-Bit)
14
RAM Addr
GPIO
9
Addr MUX
Instruction Reg
7
Direct Addr
Indirect
Addr
8
FSR Reg
STATUS Reg
8
3
Power-up
Timer
OSC1/CLKIN
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Power-on
Reset
MUX
ALU
8
W Reg
Brown-out
Reset
OSC2/CLKOUT
Internal
Oscillator
Block
Shunt Regulator
(PIC12HV609 only)
MCLR
T1G
VDD
VSS
T1CKI
Timer0
Timer1
T0CKI
Comparator Voltage Reference
Absolute Voltage Reference
Analog Comparator
and Reference
CIN+
CIN0CIN1COUT
2010 Microchip Technology Inc.
DS41302D-page 7
PIC12F609/615/617/12HV609/615
FIGURE 1-2:
PIC12F615/617/HV615 BLOCK DIAGRAM
INT
Configuration
13
Flash
1K X 14
and
2K X 14**
Program
Memory
Program
Bus
8
Data Bus
GPIO
Program Counter
GP0
GP1
GP2
GP3
GP4
GP5
RAM
64 Bytes and
128 Bytes**
File
Registers
8-Level Stack
(13-Bit)
14
RAM Addr
9
Addr MUX
Instruction Reg
7
Direct Addr
Indirect
Addr
8
FSR Reg
STATUS Reg
8
3
Power-up
Timer
OSC1/CLKIN
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Power-on
Reset
ALU
8
W Reg
Brown-out
Reset
OSC2/CLKOUT
Internal
Oscillator
Block
T1G*
MUX
Shunt Regulator
(PIC12HV615 only)
MCLR
T1G
VDD
VSS
T1CKI
Timer0
Timer1
T0CKI
Comparator Voltage Reference
Analog-To-Digital Converter
Absolute Voltage Reference
ECCP
CCP1/P1A
P1B
P1A*
P1B*
DS41302D-page 8
Analog Comparator
and Reference
CIN+
CIN0CIN1COUT
AN0
AN1
AN2
AN3
VREF
*
**
Timer2
Alternate pin function.
For the PIC12F617 only.
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 1-1:
PIC12F609/HV609 PINOUT DESCRIPTION
Name
Function
Input
Type
Output
Type
GP0/CIN+/ICSPDAT
GP0
TTL
CMOS
CIN+
AN
—
ICSPDAT
ST
CMOS
GP1
TTL
CMOS
CIN0-
AN
—
Comparator inverting input
Serial Programming Clock
GP1/CIN0-/ICSPCLK
ICSPCLK
ST
—
GP2
ST
CMOS
T0CKI
ST
—
GP2/T0CKI/INT/COUT
INT
ST
—
COUT
—
CMOS
General purpose I/O with prog. pull-up and interrupt-on-change
Comparator non-inverting input
Serial Programming Data I/O
General purpose I/O with prog. pull-up and interrupt-on-change
General purpose I/O with prog. pull-up and interrupt-on-change
Timer0 clock input
External Interrupt
Comparator output
GP3
TTL
—
General purpose input with interrupt-on-change
MCLR
ST
—
Master Clear w/internal pull-up
VPP
HV
—
Programming voltage
GP3/MCLR/VPP
GP4/CIN1-/T1G/OSC2/
CLKOUT
Description
GP4
TTL
CMOS
CIN1-
AN
—
T1G
ST
—
OSC2
—
XTAL
General purpose I/O with prog. pull-up and interrupt-on-change
Comparator inverting input
Timer1 gate (count enable)
Crystal/Resonator
CLKOUT
—
CMOS
FOSC/4 output
GP5
TTL
CMOS
General purpose I/O with prog. pull-up and interrupt-on-change
T1CKI
ST
—
OSC1
XTAL
—
Crystal/Resonator
CLKIN
ST
—
External clock input/RC oscillator connection
VDD
VDD
Power
—
Positive supply
VSS
VSS
Power
—
Ground reference
GP5/T1CKI/OSC1/CLKIN
Legend: AN=Analog input or output
ST=Schmitt Trigger input with CMOS levels
2010 Microchip Technology Inc.
Timer1 clock input
CMOS = CMOS compatible input or output
TTL = TTL compatible input
HV= High Voltage
XTAL=Crystal
DS41302D-page 9
PIC12F609/615/617/12HV609/615
TABLE 1-2:
PIC12F615/617/HV615 PINOUT DESCRIPTION
Name
GP0/AN0/CIN+/P1B/ICSPDAT
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/
P1A
GP3/T1G*/MCLR/VPP
GP4/AN3/CIN1-/T1G/P1B*/OSC2/
CLKOUT
GP5/T1CKI/P1A*/OSC1/CLKIN
Function
Input
Type
Output
Type
GP0
TTL
CMOS
Description
General purpose I/O with prog. pull-up and interrupt-onchange
AN0
AN
—
A/D Channel 0 input
CIN+
AN
—
Comparator non-inverting input
P1B
—
CMOS
ICSPDAT
ST
CMOS
PWM output
Serial Programming Data I/O
GP1
TTL
CMOS
General purpose I/O with prog. pull-up and interrupt-onchange
AN1
AN
—
A/D Channel 1 input
CIN0-
AN
—
Comparator inverting input
VREF
AN
—
External Voltage Reference for A/D
ICSPCLK
ST
—
Serial Programming Clock
GP2
ST
CMOS
General purpose I/O with prog. pull-up and interrupt-onchange
AN2
AN
—
A/D Channel 2 input
T0CKI
ST
—
Timer0 clock input
INT
ST
—
COUT
—
CMOS
Comparator output
External Interrupt
CCP1
ST
CMOS
Capture input/Compare input/PWM output
P1A
—
CMOS
GP3
TTL
—
General purpose input with interrupt-on-change
T1G*
ST
—
Timer1 gate (count enable), alternate pin
PWM output
MCLR
ST
—
Master Clear w/internal pull-up
VPP
HV
—
Programming voltage
GP4
TTL
CMOS
General purpose I/O with prog. pull-up and interrupt-onchange
AN3
AN
—
A/D Channel 3 input
CIN1-
AN
—
Comparator inverting input
Timer1 gate (count enable)
T1G
ST
—
P1B*
—
CMOS
PWM output, alternate pin
OSC2
—
XTAL
Crystal/Resonator
CLKOUT
—
CMOS
FOSC/4 output
GP5
TTL
CMOS
General purpose I/O with prog. pull-up and interrupt-onchange
T1CKI
ST
—
P1A*
—
CMOS
OSC1
XTAL
—
Crystal/Resonator
Timer1 clock input
PWM output, alternate pin
CLKIN
ST
—
External clock input/RC oscillator connection
VDD
VDD
Power
—
Positive supply
VSS
VSS
Power
—
Ground reference
*
Legend:
Alternate pin function.
AN=Analog input or output
ST=Schmitt Trigger input with CMOS levels
DS41302D-page 10
CMOS=CMOS compatible input or output
TTL = TTL compatible input
HV= High Voltage
XTAL=Crystal
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.0
MEMORY ORGANIZATION
2.1
Program Memory Organization
FIGURE 2-2:
The PIC12F609/615/617/12HV609/615 has a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14 (0000h03FFh) for the PIC12F609/615/12HV609/615 is
physically implemented. For the PIC12F617, the first
2K x 14 (0000h-07FFh) is physically implemented.
Accessing a location above these boundaries will
cause a wrap-around within the first 1K x 14 space for
PIC12F609/615/12HV609/615 devices, and within the
first 2K x 14 space for the PIC12F617 device. The
Reset vector is at 0000h and the interrupt vector is at
0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
PC
CALL, RETURN
RETFIE, RETLW
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F617
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
On-Chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Wraps to 0000h-07FFh
13
1FFFh
Stack Level 1
Stack Level 2
2.2
Data Memory Organization
03FFh
The data memory (see Figure 2-3) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. For the PIC12F617, the register locations
20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general
purpose registers implemented as Static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
‘0’ when read. The RP0 bit of the STATUS register is the
bank select bit.
0400h
RP0
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
Wraps to 0000h-03FFh
1FFFh
0
Bank 0 is selected
1
Bank 1 is selected
Note:
2010 Microchip Technology Inc.
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
DS41302D-page 11
PIC12F609/615/617/12HV609/615
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615, and as 128 x 8 in the
PIC12F617. Each register is accessed, either directly
or indirectly, through the File Select Register (FSR)
(see Section 2.4 “Indirect Addressing, INDF and
FSR Registers”).
2.2.2
FIGURE 2-3:
DATA MEMORY MAP OF
THE PIC12F609/HV609
File
Address
File
Address
Indirect Addr.(1)
00h
Indirect Addr.(1)
80h
TMR0
01h
OPTION_REG
81h
PCL
02h
PCL
82h
STATUS
03h
STATUS
83h
FSR
04h
FSR
84h
GPIO
05h
TRISIO
85h
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
06h
86h
07h
87h
08h
88h
89h
09h
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
PCLATH
0Ah
PCLATH
8Ah
INTCON
0Bh
INTCON
8Bh
PIR1
0Ch
PIE1
8Ch
8Dh
0Dh
TMR1L
0Eh
TMR1H
0Fh
T1CON
10h
PCON
8Eh
8Fh
OSCTUNE
90h
11h
91h
12h
92h
13h
93h
94h
14h
15h
WPU
95h
16h
IOC
96h
17h
97h
18h
98h
VRCON
19h
99h
CMCON0
1Ah
9Ah
1Bh
9Bh
1Ch
9Ch
1Dh
9Dh
CMCON1
9Eh
1Eh
ANSEL
1Fh
20h
9Fh
A0h
3Fh
General
Purpose
Registers
64 Bytes
Accesses 70h-7Fh
40h
6Fh
70h
Accesses 70h-7Fh
EFh
F0h
FFh
7Fh
Bank 1
Bank 0
Unimplemented data memory locations, read as ‘0’.
Note
DS41302D-page 12
1:
Not a physical register.
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 2-4:
DATA MEMORY MAP OF
THE PIC12F615/617/HV615
File
Address
File
Address
Indirect Addr.(1)
00h
Indirect Addr.(1)
80h
TMR0
01h
OPTION_REG
81h
PCL
02h
PCL
82h
STATUS
03h
STATUS
83h
FSR
04h
FSR
84h
GPIO
05h
TRISIO
85h
06h
86h
07h
87h
08h
88h
89h
09h
PCLATH
0Ah
PCLATH
8Ah
INTCON
0Bh
INTCON
8Bh
PIR1
0Ch
PIE1
8Ch
8Dh
0Dh
PCON
TMR1L
0Eh
TMR1H
0Fh
T1CON
10h
TMR2
11h
T2CON
12h
PR2
92h
CCPR1L
13h
APFCON
93h
CCPR1H
14h
CCP1CON
15h
WPU
95h
PWM1CON
16h
IOC
96h
ECCPAS
17h
8Eh
8Fh
OSCTUNE
91h
94h
97h
(2)
18h
PMCON1
VRCON
19h
PMCON2
CMCON0
1Ah
PMADRL
1Bh
PMADRH
1Ch
PMDATL
1Dh
PMDATH
CMCON1
90h
(2)
(2)
(2)
(2)
(2)
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESH
1Eh
ADRESL
9Eh
ADCON0
1Fh
ANSEL
9Fh
A0h
20h
General
Purpose
Registers
32 Bytes(2)
General
Purpose
Registers
96 Bytes from
20h-7Fh(2)
Unimplemented for
PIC12F615/HV615
Unimplemented for
PIC12F615/HV615
BFh
C0h
3Fh
General
Purpose
Registers
64 Bytes
Accesses 70h-7Fh
40h
6Fh
70h
Accesses 70h-7Fh
FFh
7Fh
Bank 0
EFh
F0h
Bank 1
Unimplemented data memory locations, read as ‘0’.
Note
1:
Not a physical register.
2:
Used for the PIC12F617 only.
2010 Microchip Technology Inc.
DS41302D-page 13
PIC12F609/615/617/12HV609/615
TABLE 2-1:
Addr
Name
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
25, 115
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
53, 115
02h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
25, 115
03h
STATUS
0001 1xxx
18, 115
xxxx xxxx
25, 115
--x0 x000
43, 115
04h
FSR
05h
GPIO
IRP(1)
RP1(1)
RP0
TO
PD
Z
DC
C
GP4
GP3
GP2
GP1
GP0
Indirect Data Memory Address Pointer
—
—
GP5
06h
—
Unimplemented
—
—
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
---0 0000
25, 115
0Ah
PCLATH
—
—
—
0Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
20, 115
0Ch
PIR1
—
—
—
—
CMIF
—
—
TMR1IF
---- 0--0
22, 115
Write Buffer for upper 5 bits of Program Counter
0Dh
—
0Eh
TMR1L
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
11h
—
12h
—
13h
—
—
xxxx xxxx
57, 115
xxxx xxxx
57, 115
0000 0000
62, 115
Unimplemented
—
—
Unimplemented
—
—
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
—
Unimplemented
—
—
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
—
Unimplemented
—
—
19h
VRCON
1Ah
CMCON0
1Bh
1Ch
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1SYNC
TMR1CS
TMR1ON
CMVREN
—
VRR
FVREN
VR3
VR2
VR1
VR0
0-00 0000
76, 116
CMON
COUT
CMOE
CMPOL
—
CMR
—
CMCH
0000 -0-0
72, 116
—
CMCON1
T1OSCEN
—
—
—
—
T1ACS
CMHYS
—
—
T1GSS
CMSYNC
—
—
---0 0-10
73, 116
1Dh
—
Unimplemented
—
—
1Eh
—
Unimplemented
—
—
1Fh
—
Unimplemented
—
—
Legend:
1:
2:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
Read only register.
DS41302D-page 14
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 2-2:
Addr
Name
PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 25, 116
01h
TMR0
Timer0 Module’s Register
xxxx xxxx 53, 116
02h
PCL
Program Counter’s (PC) Least Significant Byte
03h
STATUS
04h
FSR
05h
GPIO
IRP(1)
RP1(1)
RP0
0000 0000 25, 116
TO
PD
Z
DC
C
0001 1xxx 18, 116
GP4
GP3
GP2
GP1
GP0
--x0 x000 43, 116
Indirect Data Memory Address Pointer
—
—
GP5
xxxx xxxx 25, 116
06h
—
Unimplemented
—
—
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah
PCLATH
—
0Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 20, 116
0Ch
PIR1
—
ADIF
CCP1IF
—
CMIF
—
TMR2IF
TMR1IF
-00- 0-00 22, 116
—
—
Write Buffer for upper 5 bits of Program Counter
0Dh
—
0Eh
TMR1L
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
T1GINV
---0 0000 25, 116
—
TMR1GE
—
xxxx xxxx 57, 116
xxxx xxxx 57, 116
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
0000 0000 62, 116
11h
TMR2(3)
12h
T2CON(3)
13h
CCPR1L(3)
Capture/Compare/PWM Register 1 Low Byte
14h
CCPR1H(3)
Capture/Compare/PWM Register 1 High Byte
15h
CCP1CON(3)
P1M
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
16h
PWM1CON(3)
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000
105,
116
17h
ECCPAS(3)
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
0000 0000
102,
116
—
—
18h
—
19h
VRCON
1Ah
CMCON0
1Bh
1Ch
Timer2 Module Register
—
TOUTPS3
0000 0000 65, 116
1Dh
—
1Eh
ADRESH(2, 3)
1Fh
ADCON0(3)
Legend:
Note 1:
2:
3:
XXXX XXXX 90, 116
Unimplemented
0-00 0000 89, 116
CMVREN
—
VRR
FVREN
VR3
VR2
VR1
VR0
0-00 0000 76, 116
CMON
COUT
CMOE
CMPOL
—
CMR
—
CMCH
0000 -0-0 72, 116
CMSYNC
---0 0-10 73, 116
—
CMCON1
-000 0000 66, 116
XXXX XXXX 90, 116
—
—
—
—
T1ACS
CMHYS
—
—
T1GSS
—
Unimplemented
—
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ADFM
VCFG
—
CHS2
CHS1
CHS0
GO/DONE
—
—
xxxx xxxx 85, 116
ADON
00-0 0000 84, 116
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
Read only register.
PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 15
PIC12F609/615/617/12HV609/615
TABLE 2-3:
Addr
Name
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 1
80h
INDF
81h
OPTION_RE
G
Addressing this location uses contents of FSR to address data memory (not a physical register)
82h
PCL
83h
STATUS
84h
FSR
85h
TRISIO
GPPU
INTEDG
T0CS
T0SE
PS2
PS1
PS0
TO
PD
Z
DC
C
0001 1xxx 18, 116
TRISIO4
TRISIO3(4)
TRISIO2
TRISIO1
TRISIO0
--11 1111 44, 116
Program Counter’s (PC) Least Significant Byte
IRP(1)
RP1(1)
RP0
—
TRISIO5
1111 1111 19, 116
0000 0000 25, 116
Indirect Data Memory Address Pointer
—
xxxx xxxx 25, 116
PSA
xxxx xxxx 25, 116
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah
PCLATH
—
—
—
8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF(3)
0000 0000 20, 116
8Ch
PIE1
—
—
—
—
CMIE
—
—
TMR1IE
---- 0--0 21, 116
—
—
—
—
—
POR
BOR
---- --qq 23, 116
—
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000 41, 116
8Dh
8Eh
—
PCON
8Fh
90h
—
OSCTUNE
Write Buffer for upper 5 bits of Program Counter
Unimplemented
—
—
Unimplemented
—
---0 0000 25, 116
—
—
—
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
WPU(2)
96h
IOC
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0
--11 -111 46, 116
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000 46, 116
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
ANSEL
Legend:
Note 1:
2:
3:
4:
—
—
—
—
ANS3
—
ANS1
ANS0
---- 1-11 45, 117
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
TRISIO3 always reads as ‘1’ since it is an input only pin.
DS41302D-page 16
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 2-4:
Addr
Name
PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 1
80h
INDF
81h
OPTION_REG
Addressing this location uses contents of FSR to address data memory (not a physical register)
82h
PCL
83h
STATUS
GPPU
INTEDG
T0CS
T0SE
xxxx xxxx 25, 116
PSA
PS2
PS1
PS0
1111 1111 19, 116
TO
PD
Z
DC
C
0001 1xxx 18, 116
TRISIO4
TRISIO3(4)
TRISIO2
TRISIO1
TRISIO0
Program Counter’s (PC) Least Significant Byte
84h
FSR
85h
TRISIO
IRP(1)
RP1(1)
RP0
0000 0000 25, 116
Indirect Data Memory Address Pointer
—
—
TRISIO5
xxxx xxxx 25, 116
--11 1111 44, 116
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah
PCLATH
—
8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF(3)
0000 0000 20, 116
8Ch
PIE1
—
ADIE
CCP1IE
—
CMIE
—
TMR2IE
TMR1IE
-00- 0-00 21, 116
—
—
—
—
—
POR
BOR
---- --qq 23, 116
—
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000 41, 116
8Dh
8Eh
—
PCON
8Fh
90h
—
OSCTUNE
91h
—
92h
PR2
93h
APFCON
94h
—
Write Buffer for upper 5 bits of Program Counter
95h
WPU(2)
96h
IOC
—
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
—
—
—
—
T1GSEL
—
—
P1BSEL
P1ASEL
---0 --00 21, 116
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0
--11 -111 46, 116
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000 46, 116
—
—
—
—
WREN
WR
RD
PMADRL2
PMADRL1
Unimplemented
—
Unimplemented
PMCON1(7)
99h
PMCON2(7)
Program Memory Control Register 2 (not a physical register).
9Ah
PMADRL(7)
PMADRL7 PMADRL6 PMADRL5 PMADRL4
—
PMADRL3
9Bh
PMADRH(7)
—
—
—
—
—
9Ch
PMDATL(7)
PMDATL7
PMDATL6
PMDATL5
PMDATL4
PMDATL3
9Dh
PMDATH(7)
—
—
9Eh
ADRESL(5, 6)
9Fh
ANSEL
4:
5:
6:
7:
—
1111 1111 65, 116
98h
Legend:
Note 1:
2:
3:
---0 0000 25, 116
Timer2 Module Period Register
—
97h
—
ADCS2
ADCS0
ANS3
—
29
---- ----
—
28
PMADRH2 PMADRH1 PMADRH0 ---- -000
28
PMDATL2
0000 0000
28
--00 0000
28
PMDATL1
PMDATL0
Program Memory Data Register High Byte.
ADCS1
—
---- -000
PMADRL0 0000 0000
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
—
—
ANS2
xxxx xxxx 85, 117
ANS1
ANS0
-000 1111 45, 117
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
TRISIO3 always reads as ‘1’ since it is an input only pin.
Read only register.
PIC12F615/617/HV615 only.
PIC12F617 only.
2010 Microchip Technology Inc.
DS41302D-page 17
PIC12F609/615/617/12HV609/615
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (RAM)
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, see the Section 14.0
“Instruction Set Summary”.
Note 1: Bits IRP and RP1 of the STATUS register
are not used by the PIC12F609/615/617/
12HV609/615 and should be maintained
as clear. Use of these bits is not recommended, since this may affect upward
compatibility with future products.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
REGISTER 2-1:
STATUS: STATUS REGISTER
Reserved
Reserved
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRP: This bit is reserved and should be maintained as ‘0’
bit 6
RP1: This bit is reserved and should be maintained as ‘0’
bit 5
RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h – FFh)
0 = Bank 0 (00h – 7Fh)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is
reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41302D-page 18
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.2.2.2
OPTION Register
Note:
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
•
•
•
•
Timer0/WDT prescaler
External GP2/INT interrupt
Timer0
Weak pull-ups on GPIO
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit to ‘1’ of the OPTION
register. See Section 6.1.3 “Software
Programmable Prescaler”.
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS: Prescaler Rate Select bits
BIT VALUE
000
001
010
011
100
101
110
111
2010 Microchip Technology Inc.
x = Bit is unknown
TIMER0 RATE WDT RATE
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS41302D-page 19
PIC12F609/615/617/12HV609/615
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO change and external
GP2/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3
GPIE: GPIO Change Interrupt Enable bit(1)
1 = Enables the GPIO change interrupt
0 = Disables the GPIO change interrupt
bit 2
T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 1
INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0
GPIF: GPIO Change Interrupt Flag bit
1 = When at least one of the GPIO pins changed state (must be cleared in software)
0 = None of the GPIO pins have changed state
Note 1:
2:
IOC register must also be enabled.
T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
DS41302D-page 20
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.2.2.4
PIE1 Register
The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-4.
REGISTER 2-4:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
R/W-0
—
ADIE(1)
CCP1IE(1)
—
CMIE
—
TMR2IE(1)
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIE: A/D Converter (ADC) Interrupt Enable bit(1)
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5
CCP1IE: CCP1 Interrupt Enable bit(1)
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 4
Unimplemented: Read as ‘0’
bit 3
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1)
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
x = Bit is unknown
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
2010 Microchip Technology Inc.
DS41302D-page 21
PIC12F609/615/617/12HV609/615
2.2.2.5
PIR1 Register
The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-5.
REGISTER 2-5:
U-0
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0
(1)
—
Note:
ADIF
R/W-0
CCP1IF
(1)
U-0
—
R/W-0
CMIF
U-0
R/W-0
(1)
—
TMR2IF
R/W-0
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIF: A/D Interrupt Flag bit(1)
1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started
bit 5
CCP1IF: CCP1 Interrupt Flag bit(1)
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 4
Unimplemented: Read as ‘0’
bit 3
CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed (must be cleared in software)
0 = Comparator output has not changed
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1)
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match has not occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 register overflowed (must be cleared in software)
0 = Timer1 has not overflowed
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
DS41302D-page 22
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.2.2.6
PCON Register
The Power Control (PCON) register (see Table 12-2)
contains flag bits to differentiate between a:
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
PCON: POWER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0(1)
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1:
Reads as ‘0’ if Brown-out Reset is disabled.
2010 Microchip Technology Inc.
DS41302D-page 23
PIC12F609/615/617/12HV609/615
2.2.2.7
APFCON Register
(PIC12F615/617/HV615 only)
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. For this device, the
P1A, P1B and Timer1 Gate functions can be moved
between different pins.
The APFCON register bits are shown in Register 2-7.
REGISTER 2-7:
APFCON:ALTERNATE PIN FUNCTION REGISTER(1)
U-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
—
—
T1GSEL
—
—
P1BSEL
P1ASEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4
T1GSEL: TMR1 Input Pin Select bit
1 = T1G function is on GP3/T1G(2)/MCLR/VPP
0 = T1G function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT
bit 3-2
Unimplemented: Read as ‘0’
bit 1
P1BSEL: P1B Output Pin Select bit
1 = P1B function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT
0 = P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT
bit 0
P1ASEL: P1A Output Pin Select bit
1 = P1A function is on GP5/T1CKI/P1A(2)/OSC1/CLKIN
0 = P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
x = Bit is unknown
Note 1: PIC12F615/617/HV615 only.
2: Alternate pin function.
DS41302D-page 24
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.3
2.3.2
PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-5 shows the two
situations for the loading of the PC. The upper example
in Figure 2-5 shows how the PC is loaded on a write to
PCL (PCLATH PCH). The lower example in
Figure 2-5 shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH PCH).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
The PIC12F609/615/617/12HV609/615 Family has an
8-level x 13-bit wide hardware stack (see Figure 2-1).
The stack space is not part of either program or data
space and the Stack Pointer is not readable or writable.
The PC is PUSHed onto the stack when a CALL
instruction is executed or an interrupt causes a branch.
The stack is POPed in the event of a RETURN, RETLW
or a RETFIE instruction execution. PCLATH is not
affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
8
PCLATH
5
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH
11
OPCODE
PCLATH
2.3.1
STACK
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register,
all 13 bits of the program counter will change to the
values contained in the PCLATH register and those
being written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
2.4
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit of the
STATUS register, as shown in Figure 2-6.
A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
MOVLW
MOVWF
NEXT
CLRF
INCF
BTFSS
GOTO
CONTINUE
INDIRECT ADDRESSING
0x40
FSR
INDF
FSR
FSR,7
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2010 Microchip Technology Inc.
DS41302D-page 25
PIC12F609/615/617/12HV609/615
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615
Direct Addressing
RP1(1)
RP0
6
Bank Select
From Opcode
Indirect Addressing
IRP(1)
0
7
Bank Select
Location Select
00
01
10
File Select Register
0
Location Select
11
00h
180h
NOT USED(2)
Data
Memory
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail, see Figure 2-3.
Note 1:
2:
The RP1 and IRP bits are reserved; always maintain these bits clear.
Accesses in this area are mirrored back into Bank 0 and Bank 1.
DS41302D-page 26
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
3.0
FLASH PROGRAM MEMORY
SELF READ/SELF WRITE
CONTROL (FOR PIC12F617
ONLY)
The Flash program memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers (see Registers 3-1 to 3-5). There
are six SFRs used to read and write this memory:
•
•
•
•
•
•
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
When interfacing the program memory block, the
PMDATL and PMDATH registers form a two-byte word
which holds the 14-bit data for read/write, and the
PMADRL and PMADRH registers form a two-byte
word which holds the 13-bit address of the Flash location being accessed. These devices have 2K words of
program Flash with an address range from 0000h to
07FFh.
3.1
PMADRH and PMADRL Registers
The PMADRH and PMADRL registers can address up
to a maximum of 8K words of program memory.
When selecting a program address value, the Most
Significant Byte (MSB) of the address is written to the
PMADRH register and the Least Significant Byte
(LSB) is written to the PMADRL register.
3.2
PMCON1 and PMCON2 Registers
PMCON1 is the control register for the data program
memory accesses.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
PMCON2 is not a physical register. Reading PMCON2
will read all ‘0’s. The PMCON2 register is used
exclusively in the Flash memory write sequence.
The program memory allows single word read and a
by four word write. A four word write automatically
erases the row of the location and writes the new data
(erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash program memory.
Depending on the settings of the Flash Program
Memory Enable (WRT) bits, the device may or
may not be able to write certain blocks of the program
memory, however, reads of the program memory are
allowed.
When the Flash program memory Code Protection
(CP) bit in the Configuration Word register is enabled,
the program memory is code-protected, and the
device programmer (ICSP™) cannot access data or
program memory.
2010 Microchip Technology Inc.
DS41302D-page 27
PIC12F609/615/617/12HV609/615
REGISTER 3-1:
PMDATL: PROGRAM MEMORY DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMDATL7
PMDATL6
PMDATL5
PMDATL4
PMDATL3
PMDATL2
PMDATL1
PMDATL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
PMDATL: 8 Least Significant Address bits to Write or Read from Program Memory
REGISTER 3-2:
PMADRL: PROGRAM MEMORY ADDRESS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMADRL7
PMADRL6
PMADRL5
PMADRL4
PMADRL3
PMADRL2
PMADRL1
PMADRL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
PMADRL: 8 Least Significant Address bits for Program Memory Read/Write Operation
REGISTER 3-3:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
PMDATH5
PMDATH4
PMDATH3
PMDATH2
PMDATH1
PMDATH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMDATH: 6 Most Significant Data bits from Program Memory
REGISTER 3-4:
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PMADRH2
PMADRH1
PMADRH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PMADRH: Specifies the 3 Most Significant Address bits or high bits for program memory reads.
DS41302D-page 28
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 3-5:
U-1
—
PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
WREN
R/S-0
WR
bit 7
R/S-0
RD
bit 0
bit 7
Unimplemented: Read as ‘1’
bit 6-3
Unimplemented: Read as ‘0’
bit 2
WREN: Program Memory Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle to program memory. (The bit is cleared by hardware when write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle to the Flash memory is complete
bit 0
RD: Read Control bit
1 = Initiates a program memory read (The read takes one cycle. The RD is cleared in hardware; the RD bit
can only be set (not cleared) in software).
0 = Does not initiate a Flash memory read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
2010 Microchip Technology Inc.
x = bit is unknown
DS41302D-page 29
PIC12F609/615/617/12HV609/615
3.3
Reading the Flash Program
Memory
To read a program memory location, the user must
write two bytes of the address to the PMADRL and
PMADRH registers, and then set control bit RD
(PMCON1). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle after to read the data. This causes the
second instruction immediately following the “BSF
PMCON1,RD” instruction to be ignored. The data is
available in the very next cycle in the PMDATL and
PMDATH registers; it can be read as two bytes in the
following instructions. PMDATL and PMDATH registers will hold this value until another read or until it is
written to by the user (during a write operation).
EXAMPLE 3-1:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
BSF
FLASH PROGRAM READ
PM_ADR
MS_PROG_PM_ADDR
PMADRH
LS_PROG_PM_ADDR
PMADRL
PMCON1
PMCON1, RD
;
;
;
;
;
;
;
Change STATUS bits RP1:0 to select bank with PMADRL
MS Byte of Program Address to read
LS Byte of Program Address to read
Bank to containing PMCON1
PM Read
NOP
; First instruction after BSF PMCON1,RD executes normally
NOP
;
;
;
;
;
;
BANKSEL PMDATL
MOVF
PMDATL, W
MOVF
PMDATH, W
DS41302D-page 30
Any instructions here are ignored as program
memory is read in second cycle after BSF PMCON1,RD
Bank to containing PMADRL
W = LS Byte of Program PMDATL
W = MS Byte of Program PMDATL
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 3-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1
Flash ADDR
Q2
Q3
Q4
PC
Flash DATA
Q1
Q2
Q4
PC + 1
INSTR (PC)
INSTR (PC - 1)
Executed here
Q3
Q1
Q2
Q3
Q4
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
Executed here
Q1
Q2
Q3
PC+3
PC
+3
PMDATH,PMDATL
INSTR (PC + 1)
Executed here
Q4
Q1
Q2
Q3
Q4
NOP
Executed here
Q2
Q3
Q4
PC + 5
PC + 4
INSTR (PC + 3)
Q1
INSTR (PC + 4)
INSTR (PC + 3)
Executed here
INSTR (PC + 4)
Executed here
RD bit
PMDATH
PMDATL
Register
PMRHLT
2010 Microchip Technology Inc.
DS41302D-page 31
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3.4
Writing the Flash Program
Memory
A word of the Flash program memory may only be
written to if the word is in an unprotected segment of
memory.
Flash program memory must be written in four-word
blocks. See Figure 3-2 and Figure 3-3 for more details.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where PMADRL = 00. All block writes to
program memory are done as 16-word erase by fourword write operations. The write operation is edgealigned and cannot occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 3-2). This is accomplished
by first writing the destination address to PMADRL and
PMADRH and then writing the data to PMDATL and
PMDATH. After the address and data have been set
up, then the following sequence of events must be
executed:
1.
2.
Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
Set the WR control bit of the PMCON1 register.
All four buffer register locations should be written to
with correct data. If less than four words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the
program location(s) not being written and loads it into
the PMDATL and PMDATH registers. Then the
sequence of events to transfer data to the buffer
registers must be executed.
which the erase takes place (i.e., the last word of the
sixteen-word block erase). This is not Sleep mode as
the clocks and peripherals will continue to run. After
the four-word write cycle, the processor will resume
operation with the third instruction after the PMCON1
write instruction. The above sequence must be
repeated for the higher 12 words.
3.5
Protection Against Spurious Write
There are conditions when the device should not write
to the program memory. To protect against spurious
writes, various mechanisms have been built in. On
power-up, WREN is cleared. Also, the Power-up Timer
(64 ms duration) prevents program memory writes.
The write initiate sequence and the WREN bit help
prevent an accidental write during brown-out, power
glitch or software malfunction.
3.6
Operation During Code-Protect
When the device is code-protected, the CPU is able to
read and write unscrambled data to the program
memory. The test mode access is disabled.
3.7
Operation During Write Protect
When the program memory is write-protected, the
CPU can read and execute from the program memory.
The portions of program memory that are write protected can be modified by the CPU using the PMCON
registers, but the protected program memory cannot
be modified using ICSP mode.
To transfer data from the buffer registers to the program
memory, the PMADRL and PMADRH must point to the
last location in the four-word block (PMADRL =
11). Then the following sequence of events must be
executed:
1.
2.
Write 55h, then AAh, to PMCON2 (Flash programming sequence).
Set control bit WR of the PMCON1 register to
begin the write operation.
The user must follow the same specific sequence to
initiate the write for each word in the program block,
writing each program word in sequence (000, 001,
010, 011). When the write is performed on the last
word (PMADRL = 11), a block of sixteen words is
automatically erased and the content of the four-word
buffer registers are written into the program memory.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
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FIGURE 3-2:
BLOCK WRITES TO 2K FLASH PROGRAM MEMORY
7
5
0
0 7
PMDATH
If at a new row
sixteen words of
Flash are erased,
then four buffers
are transferred
to Flash
automatically
after this word
is written
PMDATL
6
8
14
14
First word of block
to be written
14
PMADRL = 00
PMADRL = 10
PMADRL = 01
Buffer Register
Buffer Register
14
PMADRL = 11
Buffer Register
Buffer Register
Program Memory
FIGURE 3-3:
FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
PMADRH,PMADRL
PC + 1
Flash
ADDR
INSTR
(PC)
Flash
DATA
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INSTR
(PC + 1)
ignored
read
BSF PMCON1,WR INSTR (PC + 1)
Executed here
Executed here
PMDATH,PMDATL
Processor halted
PM Write Time
PC + 2
PC + 3
INSTR (PC+2)
NOP
Executed here
PC + 4
INSTR (PC+3)
(INSTR (PC + 2)
NOP
INSTR (PC + 3)
Executed here Executed here
Flash
Memory
Location
WR bit
PMWHLT
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An example of the complete four-word write sequence
is shown in Example 3-2. The initial address is loaded
into the PMADRH and PMADRL register pair; the eight
words of data are loaded using indirect addressing.
EXAMPLE 3-2:
LOOP
WRITING TO FLASH PROGRAM MEMORY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
;
A valid starting address (the least significant bits = '00')
;
is loaded in ADDRH:ADDRL
;
ADDRH, ADDRL and DATADDR are all located in data memory
;
BANKSEL PMADRH
MOVF
ADDRH,W
; Load initial address
MOVWF
PMADRH
;
MOVF
ADDRL,W
;
MOVWF
PMADRL
;
MOVF
DATAADDR,W ; Load initial data address
MOVWF
FSR
;
MOVF
INDF,W
; Load first data byte into lower
MOVWF
PMDATL
;
INCF
FSR,F
; Next byte
MOVF
INDF,W
; Load second data byte into upper
MOVWF
PMDATH
;
INCF
FSR,F
;
BANKSEL PMCON1
BSF
PMCON1,WREN ; Enable writes
BCF
INTCON,GIE ; Disable interrupts (if using)
BTFSC
INTCON,GIE ; See AN576
GOTO
$-2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
Required Sequence
MOVLW
55h
; Start of required write sequence:
MOVWF
PMCON2
; Write 55h
MOVLW
0AAh
;
MOVWF
PMCON2
; Write 0AAh
BSF
PMCON1,WR
; Set WR bit to begin write
NOP
; Required to transfer data to the buffer
NOP
; registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF
PMCON1,WREN ; Disable writes
BSF
INTCON,GIE ; Enable interrupts (comment out if not using interrupts)
BANKSEL PMADRL
MOVF
PMADRL, W
INCF
PMADRL,F
; Increment address
ANDLW
0x03
; Indicates when sixteen words have been programmed
SUBLW
0x03
;
0x0F = 16 words
;
0x0B = 12 words
;
0x07 = 8 words
;
0x03 = 4 words
BTFSS
STATUS,Z
; Exit on a match,
GOTO
LOOP
; Continue if more data needs to be written
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TABLE 3-1:
Name
PMCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
—
—
—
—
—
WREN
WR
RD
---- -000
---- -000
---- ----
---- ----
PMCON2
Program Memory Control Register 2 (not a physical register)
PMADRL
PMADRL7 PMADRL6 PMADRL5
PMADRH
PMDATL
PMDATH
Legend:
—
PMADRL3
PMADRL2
PMADRL1
PMADRL0
0000 0000
0000 0000
—
—
—
PMADRH2
PMADRH1
PMADRH0
---- -000
---- -000
PMDATL5
PMDATL4
PMDATL3
PMDATL2
PMDATL1
PMDATL0
0000 0000
0000 0000
PMDATH5
PMDATH4
PMDATH3
PMDATH2
PMDATH1
PMDATH0
--00 0000
--00 0000
—
PMDATL7 PMDATL6
—
PMADRL4
—
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by Program Memory module.
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NOTES:
DS41302D-page 36
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4.0
OSCILLATOR MODULE
The Oscillator module can be configured in one of eight
clock modes.
4.1
Overview
3.
4.
5.
The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1
illustrates a block diagram of the Oscillator module.
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured with a choice of
two selectable speeds: internal or external system clock
source.
EC – External clock with I/O on OSC2/CLKOUT.
LP – 32 kHz Low-Power Crystal mode.
XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
6. HS – High Gain Crystal or Ceramic Resonator
mode.
7. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
8. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
9. INTOSC – Internal oscillator with FOSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
10. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
Clock Source modes are configured by the FOSC
bits in the Configuration Word register (CONFIG). The
Internal Oscillator module provides a selectable
system clock mode of either 4 MHz (Postscaler) or
8 MHz (INTOSC).
FIGURE 4-1:
PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC
IOSCFS
(Configuration Word Register)
External Oscillator
OSC2
Sleep
INTOSC
Internal Oscillator
MUX
LP, XT, HS, RC, RCIO, EC
OSC1
System Clock
(CPU and Peripherals)
INTOSC
8 MHz
Postscaler
4 MHz
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4.2
Clock Source Modes
Clock Source modes can be classified as external or
internal.
• External Clock modes rely on external circuitry for
the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
• Internal clock sources are contained internally
within the Oscillator module. The Oscillator
module has two selectable clock frequencies:
4 MHz and 8 MHz
The system clock can be selected between external or
internal clock sources via the FOSC bits of the
Configuration Word register.
TABLE 4-1:
4.3
External Clock Modes
4.3.1
OSCILLATOR START-UP TIMER
(OST)
If the Oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 4-1.
OSCILLATOR DELAY EXAMPLES
Switch From
Switch To
Frequency
Oscillator Delay
Sleep/POR
INTOSC
125 kHz to 8 MHz
Oscillator Warm-Up Delay (TWARM)
Sleep/POR
EC, RC
DC – 20 MHz
2 instruction cycles
Sleep/POR
LP, XT, HS
32 kHz to 20 MHz
1024 Clock Cycles (OST)
4.3.2
EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 4-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 4-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
Clock from
Ext. System
PIC® MCU
I/O
Note 1:
OSC2/CLKOUT(1)
Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
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4.3.3
LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 4-3). The mode selects a low,
medium or high gain setting of the internal inverteramplifier to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of
the internal inverter-amplifier. LP mode current
consumption is the least of the three modes. This mode
is designed to drive only 32.768 kHz tuning-fork type
crystals (watch crystals).
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of
the internal inverter-amplifier. HS mode current
consumption is the highest of the three modes. This
mode is best suited for resonators that require a high
drive setting.
Figure 4-3 and Figure 4-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 4-3:
FIGURE 4-4:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC® MCU
OSC1/CLKIN
C1
PIC® MCU
OSC1/CLKIN
C1
To Internal
Logic
RP(3)
RF(2)
Sleep
To Internal
Logic
Quartz
Crystal
C2
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
RS(1)
RF(2)
Sleep
OSC2/CLKOUT
Note 1:
A series resistor (RS) may be required for
quartz crystals with low drive level.
2:
The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
2010 Microchip Technology Inc.
C2 Ceramic
RS(1)
Resonator
Note 1:
OSC2/CLKOUT
A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
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4.3.4
EXTERNAL RC MODES
4.4
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
The Oscillator module provides a selectable system
clock source of either 4 MHz or 8 MHz. The selectable
frequency is configured through the IOSCFS bit of the
Configuration Word.
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 4-5 shows the
external RC mode connections.
4.4.1
FIGURE 4-5:
VDD
EXTERNAL RC MODES
PIC® MCU
REXT
OSC1/CLKIN
Internal
Clock
CEXT
VSS
FOSC/4 or
I/O(2)
OSC2/CLKOUT
(1)
The frequency of the internal oscillator can be trimmed
with a calibration value in the OSCTUNE register.
INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is programmed using the oscillator selection
or the FOSC bits in the Configuration Word
register (CONFIG). See Section 12.0 “Special
Features of the CPU” for more information.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
Recommended values: 10 k REXT 100 k, 20 pF, 2-5V
Note 1:
2:
Alternate pin functions are listed in
Section 1.0 “Device Overview”.
Output depends upon RC or RCIO Clock
mode.
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
DS41302D-page 40
2010 Microchip Technology Inc.
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4.4.1.1
OSCTUNE Register
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
The oscillator is factory calibrated but can be adjusted
in software by writing to the OSCTUNE register
(Register 4-1).
REGISTER 4-1:
When the OSCTUNE register is modified, the frequency
will begin shifting to the new frequency. Code execution
continues during this shift. There is no indication that the
shift has occurred.
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TUN: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
TABLE 4-2:
Name
x = Bit is unknown
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
POR, BOR
Value on
all other
Resets(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG(2)
IOSCFS
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
—
—
OSCTUNE
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000
---u uuuu
Legend:
Note 1:
2:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 12-1) for operation of all register bits.
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NOTES:
DS41302D-page 42
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5.0
I/O PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are enabled,
some or all of the pins may not be available as general
purpose I/O. In general, when a peripheral is enabled,
the associated pin may not be used as a general
purpose I/O pin.
5.1
GPIO and the TRISIO Registers
GPIO is a 6-bit wide port with 5 bidirectional and 1 inputonly pin. The corresponding data direction register is
TRISIO (Register 5-2). Setting a TRISIO bit (= 1) will
make the corresponding GPIO pin an input (i.e., disable
the output driver). Clearing a TRISIO bit (= 0) will make
the corresponding GPIO pin an output (i.e., enables
output driver and puts the contents of the output latch on
the selected pin). The exception is GP3, which is input
only and its TRIS bit will always read as ‘1’. Example 51 shows how to initialize GPIO.
Note:
GPIO = PORTA
Reading the GPIO register (Register 5-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. GP3 reads ‘0’ when
MCLRE = 1.
The TRISIO register controls the direction of the
GPIO pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
Note:
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
EXAMPLE 5-1:
BANKSEL
CLRF
BANKSEL
CLRF
GPIO
GPIO
ANSEL
ANSEL
MOVLW
MOVWF
0Ch
TRISIO
TRISIO = TRISA
REGISTER 5-1:
INITIALIZING GPIO
;
;Init GPIO
;
;digital I/O, ADC clock
;setting ‘don’t care’
;Set GP as inputs
;and set GP
;as outputs
GPIO: GPIO REGISTER
U-0
U-0
R/W-x
R/W-x
R-x
R/W-x
R/W-x
R/W-x
—
—
GP5
GP4
GP3
GP2
GP1
GP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
GP: GPIO I/O Pin bit
1 = GPIO pin is > VIH
0 = GPIO pin is < VIL
2010 Microchip Technology Inc.
x = Bit is unknown
DS41302D-page 43
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REGISTER 5-2:
TRISIO: GPIO TRI-STATE REGISTER
U-0
U-0
R/W-1
R/W-1
R-1
R/W-1
R/W-1
R/W-1
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
TRISIO: GPIO Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
Note 1:
2:
5.2
TRISIO always reads ‘1’.
TRISIO always reads ‘1’ in XT, HS and LP Oscillator modes.
Additional Pin Functions
Every GPIO pin on the PIC12F609/615/617/12HV609/
615 has an interrupt-on-change option and a weak pullup option. The next three sections describe these
functions.
5.2.1
ANSEL REGISTER
The ANSEL register is used to configure the Input
mode of an I/O pin to analog. Setting the appropriate
ANSEL bit high will cause all digital reads on the pin to
be read as ‘0’ and allow analog functions on the pin to
operate correctly.
The state of the ANSEL bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
5.2.2
WEAK PULL-UPS
Each of the GPIO pins, except GP3, has an individually
configurable internal weak pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 5-5.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit of the
OPTION register). A weak pull-up is automatically
enabled for GP3 when configured as MCLR and
disabled when GP3 is an I/O. There is no software
control of the MCLR pull-up.
5.2.3
x = Bit is unknown
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set the GPIO Change Interrupt Flag bit
(GPIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a)
Any read of GPIO AND Clear flag bit GPIF. This
will end the mismatch condition;
OR
b)
Any write of GPIO AND Clear flag bit GPIF will
end the mismatch condition;
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these resets, the GPIF flag will continue to
be set if a mismatch is present.
Note:
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
INTERRUPT-ON-CHANGE
Each GPIO pin is individually configurable as an
interrupt-on-change pin. Control bits IOCx enable or
disable the interrupt function for each pin. Refer to
Register 5-6. The interrupt-on-change is disabled on a
Power-on Reset.
DS41302D-page 44
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 5-3:
ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609)
U-0
U-0
U-0
U-0
R/W-1
U-0
R/W-1
R/W-1
—
—
—
—
ANS3
—
ANS1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Read as ‘0’
bit 3
ANS3: Analog Select Between Analog or Digital Function on Pin GP4
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
bit 2
Unimplemented: Read as ‘0’
bit 1
ANS1: Analog Select Between Analog or Digital Function on Pin GP1
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
bit 0
ANS0: Analog Select Between Analog or Digital Function on Pin GP0
0 = Digital I/O. Pin is assigned to port or special function.
1 = Analog input. Pin is assigned as analog input.(1)
Note 1:
Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-onchange if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of
the voltage on the pin.
REGISTER 5-4:
ANSEL: ANALOG SELECT REGISTER (PIC12F615/617/HV615)
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCS: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0
ANS: Analog Select Between Analog or Digital Function on Pins GP4, GP2, GP1, GP0, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
Note 1:
Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-onchange if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of
the voltage on the pin.
2010 Microchip Technology Inc.
DS41302D-page 45
PIC12F609/615/617/12HV609/615
REGISTER 5-5:
WPU: WEAK PULL-UP GPIO REGISTER
U-0
U-0
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
WPU: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
bit 3
WPU: Weak Pull-up Register bit(3)
bit 2-0
WPU: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1:
2:
3:
4:
x = Bit is unknown
Global GPPU must be enabled for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
The GP3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled
as an input and reads as ‘0’.
WPU always reads ‘1’ in XT, HS and LP Oscillator modes.
REGISTER 5-6:
IOC: INTERRUPT-ON-CHANGE GPIO REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOC: Interrupt-on-change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1:
2:
x = Bit is unknown
Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
IOC always reads ‘1’ in XT, HS and LP Oscillator modes.
DS41302D-page 46
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
5.2.4
PIN DESCRIPTIONS AND
DIAGRAMS
Each GPIO pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the Comparator or the ADC, refer to the
appropriate section in this data sheet.
GP0/AN0(1)/CIN+/P1B(1)/ICSPDAT
5.2.4.1
Figure 5-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
•
•
•
•
•
Figure 5-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
•
•
•
•
•
a general purpose I/O
an analog input for the ADC(1)
an analog non-inverting input to the comparator
a PWM output(1)
In-Circuit Serial Programming data
FIGURE 5-1:
GP1/AN1(1)/CIN0-/VREF(1)/ICSPCLK
5.2.4.2
a general purpose I/O
an analog input for the ADC(1)
an analog inverting input to the comparator
a voltage reference input for the ADC(1)
In-Circuit Serial Programming clock
Note 1:
PIC12F615/617/HV615 only.
BLOCK DIAGRAM OF GP
Analog(1)
Input Mode
VDD
Data Bus
D
WR
WPU
Q
Weak
CK Q
GPPU
VDD
RD
WPU
D
WR
GPIO
Q
I/O Pin
CK Q
VSS
D
WR
TRISIO
Q
CK Q
RD
TRISIO
Analog(1)
Input Mode
RD
GPIO
D
WR
IOC
Q
Q
CK Q
D
EN
RD
IOC
Q
Interrupt-onChange
S(2)
R
RD GPIO
To Comparator
To A/D Converter(3)
1:
Comparator mode and ANSEL determines Analog Input mode.
2:
Set has priority over Reset.
3:
PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
D
EN
From other
GP pins (GP0)
GP pins (GP1)
Write ‘0’ to GBIF
Note
Q
Q1
DS41302D-page 47
PIC12F609/615/617/12HV609/615
GP2/AN2(1)/T0CKI/INT/COUT/
CCP1(1)/P1A(1)
5.2.4.3
Note 1:
Figure 5-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
•
•
•
•
•
•
•
PIC12F615/617/HV615 only.
a general purpose I/O
an analog input for the ADC(1)
the clock input for TMR0
an external edge triggered interrupt
a digital output from Comparator
a Capture input/Compare input/PWM output(1)
a PWM output(1)
FIGURE 5-2:
BLOCK DIAGRAM OF GP2
Analog(1)
Input Mode
VDD
Data Bus
D
WR
WPU
Q
Weak
CK Q
C1OE
Enable
GPPU
VDD
RD
WPU
C1OE
D
WR
GPIO
Q
0
I/O Pin
CK Q
D
WR
TRISIO
1
VSS
Q
CK Q
RD
TRISIO
Analog(1)
Input Mode
RD
GPIO
D
WR
IOC
Q
Q
CK Q
D
EN
RD
IOC
Q
Interrupt-onChange
Q
S(2)
R
Q1
D
EN
From other
GP pins
Write ‘0’ to GBIF
RD GPIO
To Timer0
To INT
To A/D Converter(3)
Note
DS41302D-page 48
1:
Comparator mode and ANSEL determines Analog Input mode.
2:
Set has priority over Reset.
3:
PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
5.2.4.4
GP3/T1G(1, 2)/MCLR/VPP
Figure 5-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• a Timer1 gate (count enable), alternate pin(1, 2)
• as Master Clear Reset with weak pull-up
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
FIGURE 5-3:
BLOCK DIAGRAM OF GP3
VDD
MCLRE
Weak
Data Bus
MCLRE
Reset
RD
TRISIO
Input
Pin
VSS
MCLRE
RD
GPIO
D
WR
IOC
CK
Q
Q
D
Q
EN
RD
IOC
Q
Interrupt-onChange
S(1)
R
VSS
Q
Q1
D
EN
From other
GP pins
RD GPIO
Write ‘0’ to GBIF
Note 1:
Set has priority over Reset
2010 Microchip Technology Inc.
DS41302D-page 49
PIC12F609/615/617/12HV609/615
5.2.4.5
GP4/AN3(2)/CIN1-/T1G/
P1B(1, 2)/OSC2/CLKOUT
Figure 5-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
•
•
•
•
Note 1: Alternate pin function.
a general purpose I/O
an analog input for the ADC(2)
Comparator inverting input
a Timer1 gate (count enable)
FIGURE 5-4:
• PWM output, alternate pin(1, 2)
• a crystal/resonator connection
• a clock output
2: PIC12F615/617/HV615 only.
BLOCK DIAGRAM OF GP4
Analog(3)
Input Mode
Data Bus
D
WR
WPU
CLK(1)
Modes
Q
VDD
CK Q
Weak
GPPU
RD
WPU
Oscillator
Circuit
OSC1
VDD
CLKOUT
Enable
D
WR
GPIO
Q
FOSC/4
CK Q
1
0
I/O Pin
CLKOUT
Enable
D
WR
TRISIO
Q
CK Q
VSS
INTOSC/
RC/EC(2)
CLKOUT
Enable
RD
TRISIO
Analog
Input Mode
RD
GPIO
D
Q
CK Q
WR
IOC
Q
D
EN
RD
IOC
Q
Interrupt-onChange
Q
S(4)
R
Q1
D
EN
From other
GP pins
Write ‘0’ to GBIF
RD GPIO
To T1G
To A/D Converter(5)
Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable.
2: With CLKOUT option.
3: Analog Input mode comes from ANSEL.
4: Set has priority over Reset.
5: PIC12F615/617/HV615 only.
DS41302D-page 50
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
5.2.4.6
GP5/T1CKI/P1A(1, 2)/OSC1/CLKIN
Note 1: Alternate pin function.
Figure 5-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
•
•
•
•
•
2: PIC12F615/617/HV615 only.
a general purpose I/O
a Timer1 clock input
PWM output, alternate pin(1, 2)
a crystal/resonator connection
a clock input
FIGURE 5-5:
BLOCK DIAGRAM OF GP5
INTOSC
Mode
TMR1LPEN(1)
Data Bus
D
WR
WPU
CK
VDD
Q
Weak
Q
GPPU
RD
WPU
Oscillator
Circuit
OSC2
D
WR
GPIO
CK
VDD
Q
Q
I/O Pin
D
WR
TRISIO
CK
Q
Q
VSS
INTOSC
Mode
RD
TRISIO
RD
GPIO
D
WR
IOC
CK
Q
Q
D
Q
EN
Q1
RD
IOC
Q
Q
Interrupt-onChange
S(2)
R
D
EN
From other
GP pins
RD GPIO
Write ‘0’ to GBIF
To Timer1
Note 1:
2:
Timer1 LP Oscillator enabled.
Set has priority over Reset.
2010 Microchip Technology Inc.
DS41302D-page 51
PIC12F609/615/617/12HV609/615
TABLE 5-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
-000 1111
—
ADCS2(1)
ADCS1(1)
ADCS0(1)
ANS3
ANS2(1)
ANS1
ANS0
-000 1111
CMCON0
CMON
COUT
CMOE
CMPOL
—
CMR
—
CMCH
0000 -0-0
0000 -0-0
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 0000
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000
--00 0000
ANSEL
IOC
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
GPIO
OPTION_REG
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--u0 u000
TRISIO
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111
--11 1111
WPU
—
—
WPU5
WPU4
WPU3
WPU2
WPU1
WPU0
--11 1111
--11 -111
T1GINV
TMR1GE
TICKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
uuuu uuuu
P1M
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0-00 0000
0-00 0000
—
—
—
T1GSEL
—
—
P1BSEL
P1ASEL
---0 --00
---0 --00
T1CON
CCP1CON(1)
APFCON(1)
Legend:
Note 1:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.
PIC12F615/617/HV615 only.
DS41302D-page 52
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
6.0
TIMER0 MODULE
6.1
Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the
following features:
When used as a timer, the Timer0 module can be used
as either an 8-bit timer or an 8-bit counter.
•
•
•
•
•
6.1.1
8-bit timer/counter register (TMR0)
8-bit prescaler (shared with Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
8-BIT TIMER MODE
When used as a timer, the Timer0 module will
increment every instruction cycle (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
Figure 6-1 is a block diagram of the Timer0 module.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
6.1.2
The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 6-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FOSC/4
Data Bus
0
8
1
Sync
2 TCY
1
T0CKI
pin
T0SE
TMR0
0
0
T0CS
Set Flag bit T0IF
on Overflow
8-bit
Prescaler
PSA
1
PSA
8
PS
Watchdog
Timer
WDTE
1
WDT
Time-out
0
PSA
Note 1:
2:
T0SE, T0CS, PSA, PS are bits in the OPTION register.
WDTE bit is in the Configuration Word register.
2010 Microchip Technology Inc.
DS41302D-page 53
PIC12F609/615/617/12HV609/615
6.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
6.1.3.1
Switching Prescaler Between
Timer0 and WDT Modules
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 6-1, must be executed.
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0 WDT)
BANKSEL
CLRWDT
CLRF
TMR0
BANKSEL
BSF
CLRWDT
OPTION_REG
OPTION_REG,PSA
MOVLW
ANDWF
IORLW
MOVWF
b’11111000’
OPTION_REG,W
b’00000101’
OPTION_REG
TMR0
DS41302D-page 54
;
;Clear WDT
;Clear TMR0 and
;prescaler
;
;Select WDT
;
;
;Mask prescaler
;bits
;Set WDT prescaler
;to 1:32
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 6-2).
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT TIMER0)
CLRWDT
;Clear WDT and
;prescaler
BANKSEL OPTION_REG
;
MOVLW
b’11110000’ ;Mask TMR0 select and
ANDWF
OPTION_REG,W ;prescaler bits
IORLW
b’00000011’ ;Set prescale to 1:16
MOVWF
OPTION_REG
;
6.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
Note:
6.1.5
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements as
shown in Section 16.0 “Electrical Specifications”.
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 6-1:
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
000
001
010
011
100
101
110
111
TABLE 6-1:
Name
INTCON
Legend:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 Module Register
OPTION_REG
TRISIO
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
TMR0
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Value on
POR, BOR
Value on
all other
Resets
xxxx xxxx
uuuu uuuu
0000 000x
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
—
—
--11 1111
--11 1111
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
module.
2010 Microchip Technology Inc.
DS41302D-page 55
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 56
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
7.0
TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
•
•
•
•
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
3-bit prescaler
Optional LP oscillator
Synchronous or asynchronous operation
Timer1 gate (count enable) via comparator or
T1G pin
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
Time base for the Capture/Compare function
Special Event Trigger (with ECCP)
Comparator output synchronization to Timer1
clock
7.2
Clock Source Selection
The TMR1CS bit of the T1CON register is used to select
the clock source. When TMR1CS = 0, the clock source
is FOSC/4. When TMR1CS = 1, the clock source is
supplied externally.
Clock Source
TMR1CS
T1ACS
FOSC/4
0
0
FOSC
0
1
T1CKI pin
1
x
Figure 7-1 is a block diagram of the Timer1 module.
7.1
Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer. When used with an external clock source, the
module can be used as either a timer or counter.
2010 Microchip Technology Inc.
DS41302D-page 57
PIC12F609/615/617/12HV609/615
FIGURE 7-1:
TIMER1 BLOCK DIAGRAM
TMR1GE
T1GINV
TMR1ON
Set flag bit
TMR1IF on
Overflow
To Comparator Module
Timer1 Clock
TMR1(2)
TMR1H
TMR1L
0
EN
Synchronized
clock input
1
Oscillator
(1)
T1SYNC
OSC1/T1CKI
1
Prescaler
1, 2, 4, 8
0
OSC2/T1G
Synchronize(3)
det
2
T1CKPS
TMR1CS
0
INTOSC
Without CLKOUT
T1OSCEN
FOSC
1
1
1
FOSC/4
Internal
Clock
0
COUT
0
T1GSEL(2)
T1GSS
T1ACS
GP3/T1G(4, 5)
Note 1:
2:
3:
4:
5:
ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
Timer1 register increments on rising edge.
Synchronize does not operate while in Sleep.
Alternate pin function.
PIC12F615/617/HV615 only.
DS41302D-page 58
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
7.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of TCY as determined by the Timer1 prescaler.
7.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run asynchronously.
7.5
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during
Sleep and can generate an interrupt on overflow,
which will wake-up the processor. However, special
precautions in software are needed to read/write the
timer (see Section 7.5.1 “Reading and Writing
Timer1 in Asynchronous Counter Mode”).
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce a single spurious
increment.
Note:
In asynchronous counter mode or when
using the internal oscillator and T1ACS=1,
Timer1 can not be used as a time base for
the capture or compare modes of the
ECCP module (for PIC12F615/617/
HV615 only).
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC without CLKOUT),
Timer1 can use the LP oscillator as a clock source.
In Counter mode, a falling edge must be registered by
the counter prior to the first incrementing rising edge
after one or more of the following conditions:
• Timer1 is enabled after POR or BOR Reset
• A write to TMR1H or TMR1L
• T1CKI is high when Timer1 is disabled and when
Timer1 is re-enabled T1CKI is low. See Figure 7-2.
7.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
7.4
Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in
between pins OSC1 (input) and OSC2 (output). The
oscillator is enabled by setting the T1OSCEN control
bit of the T1CON register. The oscillator will continue to
run during Sleep.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is derived from the internal
oscillator or when in LP oscillator mode. The user must
provide a software time delay to ensure proper
oscillator start-up.
Timer1 Operation in
Asynchronous Counter Mode
7.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TTMR1L register
pair.
TRISIO5 and TRISIO4 bits are set when the Timer1
oscillator is enabled. GP5 and GP4 bits read as ‘0’ and
TRISIO5 and TRISIO4 bits read as ‘1’.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
2010 Microchip Technology Inc.
DS41302D-page 59
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7.6
Timer1 Gate
Timer1 gate source is software configurable to be the
T1G pin (or the alternate T1G pin) or the output of the
Comparator. This allows the device to directly time
external events using T1G or analog events using the
Comparator. See the CMCON1 Register (Register 9-2)
for selecting the Timer1 gate source. This feature can
simplify the software for a Delta-Sigma A/D converter
and many other applications. For more information on
Delta-Sigma A/D converters, see the Microchip web site
(www.microchip.com).
Note:
TMR1GE bit of the T1CON register must
be set to use either T1G or COUT as the
Timer1 gate source. See Register 9-2 for
more information on selecting the Timer1
gate source.
7.9
ECCP Capture/Compare Time
Base (PIC12F615/617/HV615 only)
The ECCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For more information, see Section 11.0 “Enhanced
Capture/Compare/PWM (With Auto-Shutdown and
Dead Band) Module (PIC12F615/617/HV615 only)”.
Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it originates from the T1G
pin or the Comparator output. This configures Timer1
to measure either the active-high or active-low time
between events.
7.7
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
• Timer1 interrupt enable bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
7.8
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
The device will wake-up on an overflow and execute
the next instruction. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
DS41302D-page 60
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
7.10
ECCP Special Event Trigger
(PIC12F615/617/HV615 only)
If a ECCP is configured to trigger a special event, the
trigger will clear the TMR1H:TMR1L register pair. This
special event does not cause a Timer1 interrupt. The
ECCP module may still be configured to generate a
ECCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
Timer1 should be synchronized to the FOSC to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
For more information, see Section 11.0 “Enhanced
Capture/Compare/PWM (With Auto-Shutdown and
Dead Band) Module (PIC12F615/617/HV615 only)”.
7.11
Comparator Synchronization
The same clock used to increment Timer1 can also be
used to synchronize the comparator output. This
feature is enabled in the Comparator module.
When using the comparator for Timer1 gate, the
comparator output should be synchronized to Timer1.
This ensures Timer1 does not miss an increment if the
comparator changes.
For more information, see Section 9.0 “Comparator
Module”.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the ECCP, the write
will take precedence.
FIGURE 7-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
2010 Microchip Technology Inc.
DS41302D-page 61
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7.12
Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 7-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 7-1:
R/W-0
R/W-0
(1)
T1GINV
T1CON: TIMER 1 CONTROL REGISTER
(2)
TMR1GE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
T1GINV: Timer1 Gate Invert bit(1)
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 6
TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 is on if Timer1 gate is active
0 = Timer1 is on
bit 5-4
T1CKPS: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3
T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
For all other system clock modes:
This bit is ignored. LP oscillator is disabled.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4) or system clock (FOSC)(3)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1:
2:
3:
x = Bit is unknown
T1GINV bit inverts the Timer1 gate logic, regardless of source.
TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1
register, as a Timer1 gate source.
See T1ACS bit in CMCON1 register.
DS41302D-page 62
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 7-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7
APFCON(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
—
—
—
T1GSEL
—
—
P1BSEL
P1ASEL
---0 --00
---0 --00
CMCON0
CMON
COUT
CMOE
CMPOL
—
CMR
—
CMCH
0000 -0-0
0000 -0-0
CMCON1
—
—
—
T1ACS
CMHYS
—
T1GSS
CMSYNC
---0 0-10
---0 0-10
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000x
PIE1
—
ADIE(1)
CCP1IE(1)
—
CMIE
—
TMR2IE(1)
TMR1IE
-00- 0-00
-00- 0-00
PIR1
—
ADIF(1)
CCP1IF(1)
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00
-00- 0-00
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0000 0000
uuuu uuuu
T1CON
T1GINV
Legend:
Note
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
1:
PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 63
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 64
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
8.0
TIMER2 MODULE
(PIC12F615/617/HV615 ONLY)
The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
The Timer2 module is an 8-bit timer with the following
features:
•
•
•
•
•
8-bit timer register (TMR2)
8-bit period register (PR2)
Interrupt on TMR2 match with PR2
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
See Figure 8-1 for a block diagram of Timer2.
8.1
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescaler is then used to
increment the TMR2 register.
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
Note:
TMR2 is not cleared when T2CON is
written.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
TMR2
Output
FOSC/4
Prescaler
1:1, 1:4, 1:16
2
TMR2
Sets Flag
bit TMR2IF
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
T2CKPS
PR2
4
TOUTPS
2010 Microchip Technology Inc.
DS41302D-page 65
PIC12F609/615/617/12HV609/615
REGISTER 8-1:
T2CON: TIMER 2 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS: Timer2 Output Postscaler Select bits
0000 =1:1 Postscaler
0001 =1:2 Postscaler
0010 =1:3 Postscaler
0011 =1:4 Postscaler
0100 =1:5 Postscaler
0101 =1:6 Postscaler
0110 =1:7 Postscaler
0111 =1:8 Postscaler
1000 =1:9 Postscaler
1001 =1:10 Postscaler
1010 =1:11 Postscaler
1011 =1:12 Postscaler
1100 =1:13 Postscaler
1101 =1:14 Postscaler
1110 =1:15 Postscaler
1111 =1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS: Timer2 Clock Prescale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x =Prescaler is 16
TABLE 8-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Name
Bit 7
INTCON
GIE
—
—
ADIF(1)
PIE1
PIR1
x = Bit is unknown
Bit 6
Bit 5
Bit 4
PEIE
T0IE
ADIE(1)
CCP1IE(1)
CCP1IF(1)
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bit 3
Bit 2
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 0000
—
CMIE
—
TMR2IE(1)
TMR1IE
-00- 0-00
-00- 0-00
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00
-00- 0-00
PR2(1)
Timer2 Module Period Register
1111 1111
1111 1111
TMR2(1)
Holding Register for the 8-bit TMR2 Register
0000 0000
0000 0000
-000 0000
-000 0000
T2CON(1)
Legend:
Note 1:
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
For PIC12F615/617/HV615 only.
DS41302D-page 66
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
9.0
COMPARATOR MODULE
than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparator can be used to interface analog
circuits to a digital circuit by comparing two analog
voltages and providing a digital indication of their
relative magnitudes. The comparator is a very useful
mixed signal building block because it provides analog
functionality independent of the program execution.
The Analog Comparator module includes the following
features:
•
•
•
•
•
•
•
•
•
•
FIGURE 9-1:SINGLE COMPARATOR
Programmable input section
Comparator output is available internally/externally
Programmable output polarity
Interrupt-on-change
Wake-up from Sleep
PWM shutdown
Timer1 gate (count enable)
Output synchronization to Timer1 clock input
Programmable voltage reference
User-enable Comparator Hysteresis
9.1
VIN+
+
VIN-
–
VINVIN+
Output
Comparator Overview
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
The comparator is shown in Figure 9-1 along with the
relationship between the analog input levels and the
digital output. When the analog voltage at VIN+ is less
FIGURE 9-2:
Output
COMPARATOR SIMPLIFIED BLOCK DIAGRAM
CMPOL
D
Q1
Q
EN
To
Data Bus
RD_CMCON0
CMCH
Set CMIF
D
Q3*RD_CMCON0
CMON(1)
GP1/CIN0-
0
Q
EN
CL
Reset
MUX
GP4/CIN1-
1
CMVINTo PWM Auto-Shutdown
CMVIN+
CMSYNC
CMR
CMPOL
D
GP0/CIN+
FixedRef
CVREF
CMVREN
0
CMVREF
MUX
1
0
MUX
1
Note 1:
2:
3:
4:
2010 Microchip Technology Inc.
Q
0
MUX
1
CMOE
COUT(4)
From Timer1
Clock
SYNCCMOUT
To Timer1 Gate
When CMON = 0, the comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (FOSC).
Q1 is held high during Sleep mode.
Output shown for reference only. See I/O port pin diagram for more details.
DS41302D-page 67
PIC12F609/615/617/12HV609/615
9.2
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 9-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
Note 1: When reading a GPIO register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
A maximum source impedance of 10 k is
recommended for the analog sources. Also, any
external component connected to an analog input pin,
such as a capacitor or a Zener diode, should have very
little leakage current to minimize inaccuracies
introduced.
FIGURE 9-3:
ANALOG INPUT MODEL
VDD
VT 0.6V
RS < 10K
RIC
To Comparator
AIN
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE
±500 nA
VSS
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
= Interconnect Resistance
RIC
= Source Impedance
RS
VA
= Analog Voltage
= Threshold Voltage
VT
DS41302D-page 68
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
9.3
Comparator Control
The comparator has two control and Configuration
registers: CMCON0 and CMCON1. The CMCON1
register is used for controlling the interaction with
Timer1 and simultaneously reading the comparator
output.
The CMCON0 register (Register 9-1) contain the
control and Status bits for the following:
•
•
•
•
•
Enable
Input selection
Reference selection
Output selection
Output polarity
9.3.1
COMPARATOR INPUT SELECTION
The CMCH bit of the CMCON0 register directs one of
four analog input pins to the comparator inverting input.
Note:
9.3.3
To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
COMPARATOR REFERENCE
SELECTION
COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CMPOL bit of the CMCON0 register. Clearing CMPOL results in a non-inverted output. A complete table showing the output state versus input
conditions and the polarity bit is shown in Table 9-1.
TABLE 9-1:
COMPARATOR ENABLE
Setting the CMON bit of the CMCON0 register enables
the comparator for operation. Clearing the CMON bit
disables the comparator for minimum current
consumption.
9.3.2
9.3.5
Input Conditions
CMPOL
COUT
CMVIN- > CMVIN+
0
0
CMVIN- < CMVIN+
0
1
CMVIN-
> CMVIN+
1
1
CMVIN- < CMVIN+
1
0
Note:
9.4
OUTPUT STATE VS. INPUT
CONDITIONS
COUT refers to both the register bit and
output pin.
Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See Section 16.0
“Electrical Specifications” for more details.
Setting the CMR bit of the CMxCON0 register directs
an internal voltage reference or an analog input pin to
the non-inverting input of the comparator. See
Section 9.10 “Comparator Voltage Reference” for
more information on the internal voltage reference
module.
9.3.4
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the COUT bit of the CMCON0 register. In
order to make the output available for an external
connection, the following conditions must be true:
• CMOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CMON bit of the CMCON0 register must be set.
Note 1: The CMOE bit overrides the PORT data
latch. Setting the CMON has no impact
on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
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9.5
Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusiveor gate (see Figure 9-4 and Figure 9-5). One latch is
updated with the comparator output level when the
CMCON0 register is read. This latch retains the value
until the next read of the CMCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMCON0 register is read or the comparator output
returns to the previous state.
FIGURE 9-4:
Q1
Q3
CIN+
TRT
COUT
Set CMIF (edge)
CMIF
reset by software
FIGURE 9-5:
2: Comparator interrupts will operate
correctly regardless of the state of
CMOE.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the
interrupt flag can be reset without the additional step of
reading or writing the CMCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMCON1 register, to determine the actual change that
has occurred.
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
Q1
Q3
CIN+
Note 1: A write operation to the CMCON0 register
will also clear the mismatch condition
because all writes include a read
operation at the beginning of the write
cycle.
COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
TRT
COUT
Set CMIF (edge)
CMIF
cleared by CMCON0 read
reset by software
Note 1: If a change in the CMCON0 register
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF of the PIR1
register interrupt flag may not get set.
2: When a comparator is first enabled, bias
circuitry in the comparator module may
cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
interrupt
flags
before
enabling
comparator interrupts.
The CMIF bit of the PIR1 register is the Comparator
Interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is also possible to write a '1' to
this register, an interrupt can be generated.
The CMIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CMIF bit of
the PIR1 register will still be set if an interrupt condition
occurs.
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9.6
Operation During Sleep
The comparator, if enabled before entering Sleep
mode, remains active during Sleep. The additional
current consumed by the comparator is shown
separately
in
the
Section 16.0
“Electrical
Specifications”. If the comparator is not used to wake
the device, power consumption can be minimized while
in Sleep mode by turning off the comparator. The
comparator is turned off by clearing the CMON bit of the
CMCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CMIE bit of the PIE1 register
and the PEIE bit of the INTCON register must be set.
The instruction following the SLEEP instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
9.7
Effects of a Reset
A device Reset forces the CMCON1 register to its
Reset state. This sets the comparator and the voltage
reference to the OFF state.
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REGISTER 9-1:
CMCON0: COMPARATOR CONTROL REGISTER 0
R/W-0
R-0
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
CMON
COUT
CMOE
CMPOL
—
CMR
—
CMCH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CMON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 6
COUT: Comparator Output bit
If C1POL = 1 (inverted polarity):
COUT = 0 when CMVIN+ > CMVINCOUT = 1 when CMVIN+ < CMVINIf C1POL = 0 (non-inverted polarity):
COUT = 1 when CMVIN+ > CMVINCOUT = 0 when CMVIN+ < CMVIN-
bit 5
CMOE: Comparator Output Enable bit
1 = COUT is present on the COUT pin(1)
0 = COUT is internal only
bit 4
CMPOL: Comparator Output Polarity Select bit
1 = COUT logic is inverted
0 = COUT logic is not inverted
bit 3
Unimplemented: Read as ‘0’
bit 2
CMR: Comparator Reference Select bit (non-inverting input)
1 = CMVIN+ connects to CMVREF output
0 = CMVIN+ connects to CIN+ pin
bit 1
Unimplemented: Read as ‘0’
bit 0
CMCH: Comparator C1 Channel Select bit
0 = CMVIN- pin of the Comparator connects to CIN01 = CMVIN- pin of the Comparator connects to CIN1-
Note 1:
x = Bit is unknown
Comparator output requires the following three conditions: CMOE = 1, CMON = 1 and corresponding port
TRIS bit = 0.
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9.8
Comparator Gating Timer1
9.9
This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of the comparator. This requires
that Timer1 is on and gating is enabled. See
Section 7.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize the comparator with
Timer1 by setting the CMSYNC bit when the
comparator is used as the Timer1 gate source. This
ensures Timer1 does not miss an increment if the
comparator changes during an increment.
REGISTER 9-2:
Synchronizing Comparator Output
to Timer1
The comparator output can be synchronized with
Timer1 by setting the CMSYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of the Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See the Comparator Block Diagram (Figure 92) and the Timer1 Block Diagram (Figure 7-1) for more
information.
CMCON1: COMPARATOR CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
U-0
R/W-1
R/W-0
—
—
—
T1ACS
CMHYS
—
T1GSS
CMSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
T1ACS: Timer1 Alternate Clock Select bit
1 = Timer 1 Clock Source is System Clock (FOSC)
0 = Timer 1 Clock Source is Instruction Clock (FOSC\4)
bit 3
CMHYS: Comparator Hysteresis Select bit
1 = Comparator Hysteresis enabled
0 = Comparator Hysteresis disabled
bit 2
Unimplemented: Read as ‘0’
bit 1
T1GSS: Timer1 Gate Source Select bit(1)
1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input)
0 = Timer 1 Gate Source is comparator output
bit 0
CMSYNC: Comparator Output Synchronization bit(2)
1 = Output is synchronized with falling edge of Timer1 clock
0 = Output is asynchronous
Note 1:
2:
Refer to Section 7.6 “Timer1 Gate”.
Refer to Figure 9-2.
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9.10
Comparator Voltage Reference
9.10.3
OUTPUT CLAMPED TO VSS
The Comparator Voltage Reference module provides
an internally generated voltage reference for the
comparators. The following features are available:
The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
•
•
•
•
•
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
Independent from Comparator operation
16-level voltage range
Output clamped to VSS
Ratiometric with VDD
Fixed Reference (0.6)
The VRCON register (Register 9-3) controls the
Voltage Reference module shown in Register 9-6.
9.10.1
INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
9.10.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR bits of the VRCON
register.
The CVREF output voltage is determined by the
following equations:
EQUATION 9-1:
CVREF OUTPUT VOLTAGE
V RR = 1 (low range):
CVREF = (VR/24) V DD
V RR = 0 (high range):
CV REF = (VDD/4) + (VR VDD/32)
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 9-6.
• FVREN = 0
9.10.4
OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 16.0
“Electrical Specifications”.
9.10.5
FIXED VOLTAGE REFERENCE
The fixed voltage reference is independent of VDD, with
a nominal output voltage of 0.6V. This reference can be
enabled by setting the FVREN bit of the VRCON
register to ‘1’. This reference is always enabled when
the HFINTOSC oscillator is active.
9.10.6
FIXED VOLTAGE REFERENCE
STABILIZATION PERIOD
When the Fixed Voltage Reference module is enabled,
it will require some time for the reference and its
amplifier circuits to stabilize. The user program must
include a small delay routine to allow the module to
settle. See Section 16.0 “Electrical Specifications”
for the minimum delay requirement.
9.10.7
VOLTAGE REFERENCE
SELECTION
Multiplexers on the output of the Voltage Reference
module enable selection of either the CVREF or fixed
voltage reference for use by the comparators.
Setting the CMVREN bit of the VRCON register
enables current to flow in the CVREF voltage divider
and selects the CVREF voltage for use by the Comparator. Clearing the CMVREN bit selects the fixed voltage
for use by the Comparator.
When the CMVREN bit is cleared, current flow in the
CVREF voltage divider is disabled minimizing the power
drain of the voltage reference peripheral.
DS41302D-page 74
2010 Microchip Technology Inc.
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FIGURE 9-6:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
VRR
8R
CMVREN
Analog
MUX
15
CVREF(1)
To Comparators
and ADC Module
0
VR(1)
4
FVREN
Sleep
HFINTOSC enable
FixedRef
To Comparators
and ADC Module
Note 1:
0.6V
EN
Fixed Voltage
Reference
Care should be taken to ensure CVREF remains within the comparator common mode input range. See
Section 16.0 “Electrical Specifications” for more detail.
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REGISTER 9-3:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMVREN
—
VRR
FVREN
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
x = Bit is unknown
CMVREN: Comparator Voltage Reference Enable bit(1, 2)
1 = CVREF circuit powered on and routed to CVREF input of the Comparator
0 = 0.6 Volt constant reference routed to CVREF input of the Comparator
bit 6
Unimplemented: Read as ‘0’
bit 5
VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4
FVREN: 0.6V Reference Enable bit(2)
1 = Enabled
0 = Disabled
bit 3-0
VR: Comparator Voltage Reference CVREF Value Selection bits (0 VR 15)
When VRR = 1: CVREF = (VR/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR/32) * VDD
Note 1:
2:
When CMVREN is low, the CVREF circuit is powered down and does not contribute to IDD current.
When CMVREN is low and the FVREN bit is low, the CVREF signal should provide Vss to the comparator.
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9.11
Comparator Hysteresis
Each comparator has built-in hysteresis that is user
enabled by setting the CMHYS bit of the CMCON1
register. The hysteresis feature can help filter noise and
reduce multiple comparator output transitions when the
output is changing state.
FIGURE 9-7:
Figure 9-7 shows the relationship between the analog
input levels and digital output of a comparator with and
without hysteresis. The output of the comparator
changes from a low state to a high state only when the
analog voltage at VIN+ rises above the upper
hysteresis threshold (VH+). The output of the
comparator changes from a high state to a low state
only when the analog voltage at VIN+ falls below the
lower hysteresis threshold (VH-).
COMPARATOR HYSTERESIS
VIN+
+
VIN-
–
Output
V+
VH+
VINVHVIN+
Output
(Without Hysteresis)
Output
(With Hysteresis)
Note:
The black areas of the comparator output represents the uncertainty due to input offsets and response time.
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TABLE 9-2:
Name
ANSEL
CMCON0
SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND
VOLTAGE REFERENCE MODULES
Value on
POR, BOR
Bit 0
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
—
ADCS2(1)
ADCS1(1)
ADCS0(1)
ANS3
ANS2(1)
ANS1
ANS0
-000 1111
-000 1111
CMON
COUT
CMOE
CMPOL
—
CMR
—
CMCH
0000 -000
0000 -000
CMCON1
—
—
—
T1ACS
CMHYS
—
T1GSS
CMSYNC
0000 0000
0000 0000
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000x
PIE1
—
ADIE(1)
CCP1IE(1)
—
CMIE
—
TMR2IE(1)
TMR1IE
-00- 0-00
-00- 0-00
PIR1
—
ADIF(1)
CCP1IF(1)
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00
-00- 0-00
GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
TRISIO
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111
--11 1111
CMVREN
—
VRR
FVREN
VR3
VR2
VR1
VR0
0-00 0000
0-00 0000
VRCON
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
Note 1:
For PIC12F615/617/HV615 only.
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10.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
(PIC12F615/617/HV615 ONLY)
Note:
The ADRESL and ADRESH registers are
Read Only.
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 10-1 shows the block diagram of the ADC.
FIGURE 10-1:
ADC BLOCK DIAGRAM
VDD
VCFG = 0
VREF
GP0/AN0
GP1/AN1/VREF
000
GP2/AN2
010
011
VCFG = 1
001
GP4/AN3
100
CVREF
0.6V Reference
101
110
1.2V Reference
A/D
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
ADON
10
CHS
VSS
2010 Microchip Technology Inc.
ADRESH
ADRESL
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10.1
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
10.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding port
section for more information.
Note:
10.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 10.2
“ADC Operation” for more information.
10.1.3
The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connected to the ground reference.
10.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ANSEL register.
There are seven possible clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 10-3.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Section 16.0 “Electrical Specifications” for more
information. Table 10-1 gives examples of appropriate
ADC clock selections.
Note:
DS41302D-page 80
ADC VOLTAGE REFERENCE
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
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TABLE 10-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD)
ADC Clock Source
Device Frequency (FOSC)
ADCS
20 MHz
FOSC/2
000
100 ns
FOSC/4
100
200 ns(2)
001
400 ns
(2)
800 ns
(2)
FOSC/8
FOSC/16
101
FOSC/32
010
1.6 s
FOSC/64
110
3.2 s
FRC
x11
2-6 s(1,4)
Legend:
Note 1:
2:
3:
4:
8 MHz
(2)
4 MHz
1 MHz
(2)
2.0 s
1.0 s(2)
4.0 s
2.0 s
8.0 s(3)
2.0 s
4.0 s
16.0 s(3)
4.0 s
8.0 s(3)
32.0 s(3)
(3)
16.0 s
64.0 s(3)
2-6 s(1,4)
2-6 s(1,4)
250 ns
(2)
500 ns
500 ns(2)
1.0 s
(2)
8.0 s
(3)
2-6 s(1,4)
Shaded cells are outside of recommended range.
The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 10-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
10.1.5
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 10.1.5 “Interrupts” for more
information.
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10.1.6
RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 10-4 shows the two output formats.
FIGURE 10-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
10-bit A/D Result
Unimplemented: Read as ‘0’
MSB
(ADFM = 1)
bit 7
LSB
bit 0
Unimplemented: Read as ‘0’
10.2
10.2.1
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
10.2.2
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 10.2.6 “A/D Conversion Procedure”.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new
conversion result
10.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
Note:
bit 0
bit 7
bit 0
10-bit A/D Result
10.2.4
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
10.2.5
SPECIAL EVENT TRIGGER
The ECCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 counter resets to zero.
Using the Special Event Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
See Section 11.0 “Enhanced Capture/Compare/
PWM (With Auto-Shutdown and Dead Band)
Module (PIC12F615/617/HV615 only)” for more
information.
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
DS41302D-page 82
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
10.2.6
A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 10-1:
A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and GP0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL TRISIO
;
BSF
TRISIO,0
;Set GP0 to input
BANKSEL ANSEL
;
MOVLW
B’01110001’ ;ADC Frc clock,
IORWF
ANSEL
; and GP0 as analog
BANKSEL ADCON0
;
MOVLW
B’10000001’ ;Right justify,
MOVWF
ADCON0
;Vdd Vref, AN0, On
CALL
SampleTime
;Acquisiton delay
BSF
ADCON0,GO
;Start conversion
BTFSC
ADCON0,GO
;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;Store in GPR space
BANKSEL ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: See Section 10.3 “A/D Acquisition
Requirements”.
2010 Microchip Technology Inc.
DS41302D-page 83
PIC12F609/615/617/12HV609/615
10.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 10-1:
ADCON0: A/D CONTROL REGISTER 0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
VCFG
—
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ADFM: A/D Conversion Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5
Unimplemented: Read as ‘0’
bit 4-2
CHS: Analog Channel Select bits
000 = Channel 00 (AN0)
001 = Channel 01 (AN1)
010 = Channel 02 (AN2)
011 = Channel 03 (AN3)
100 = CVREF
101 = 0.6V Reference
110 = 1.2V Reference
111 = Reserved. Do not use.
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1:
When the CHS bits change to select the 1.2V or 0.6V reference, the reference output voltage will
have a transient. If the Comparator module uses this 0.6V reference voltage, the comparator output may
momentarily change state due to the transient.
DS41302D-page 84
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 10-2:
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ADRES9
ADRES8
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ADRES: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 10-3:
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY)
R-x
R-x
U-0
U-0
U-0
U-0
U-0
U-0
ADRES1
ADRES0
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
ADRES: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
bit 5-0
Unimplemented: Read as ‘0’
REGISTER 10-4:
x = Bit is unknown
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY)
U-0
U-0
U-0
U-0
U-0
U-0
R-x
R-x
—
—
—
—
—
—
ADRES9
ADRES8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
ADRES: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 10-5:
x = Bit is unknown
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ADRES: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
2010 Microchip Technology Inc.
DS41302D-page 85
PIC12F609/615/617/12HV609/615
10.3
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 10-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 10-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
EQUATION 10-1:
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 10-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V V DD
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + Temperature - 25°C 0.05µs/°C
The value for TC can be approximated with the following equations:
1
V AP PLIE D 1 – ------------ = V CHOLD
2047
;[1] VCHOLD charged to within 1/2 lsb
–TC
----------
RC
V AP P LI ED 1 – e = V CHOLD
;[2] VCHOLD charge response to VAPPLIED
– Tc
---------
1
RC
V AP P LIED 1 – e = V A P PLIE D 1 – ------------
2047
;combining [1] and [2]
Solving for TC:
T C = – C HOLD R IC + R SS + R S ln(1/2047)
= – 10pF 1k + 7k + 10k ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2µs + 1.37µs + 50°C- 25°C 0.05µs/°C
= 4.67µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41302D-page 86
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 10-4:
ANALOG INPUT MODEL
VDD
ANx
Rs
CPIN
5 pF
VA
VT = 0.6V
VT = 0.6V
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE
± 500 nA
CHOLD = 10 pF
VSS/VREF-
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
= Sample/Hold Capacitance
FIGURE 10-5:
6V
5V
VDD 4V
3V
2V
RSS
5 6 7 8 9 10 11
Sampling Switch
(k)
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
1 LSB ideal
3FBh
Full-Scale
Transition
004h
003h
002h
001h
000h
Analog Input Voltage
1 LSB ideal
VSS/VREF-
2010 Microchip Technology Inc.
Zero-Scale
Transition
VDD/VREF+
DS41302D-page 87
PIC12F609/615/617/12HV609/615
TABLE 10-2:
SUMMARY OF ASSOCIATED ADC REGISTERS
Name
Bit 7
ADCON0(1)
ADFM
VCFG
—
ADCS2(1)
ANSEL
(1,2)
ADRESH
Bit 6
Bit 5
Bit 4
Bit 3
—
CHS2
ADCS1(1)
ADCS0(1)
Value on
POR, BOR
Value on
all other
Resets
Bit 2
Bit 1
Bit 0
CHS1
CHS0
GO/DONE
ADON
00-0 0000 00-0 0000
ANS3
ANS2(1)
ANS1
ANS0
-000 1111 -000 1111
A/D Result Register High Byte
xxxx xxxx uuuu uuuu
ADRESL(1,2) A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--x0 x000 --x0 x000
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 0000
—
ADIE(1)
CCP1IE(1)
—
CMIE
—
TMR2IE(1)
TMR1IE
-00- 0-00 -00- 0-00
PIR1
—
ADIF(1)
CCP1IF(1)
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00 -00- 0-00
TRISIO
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
GPIO
INTCON
PIE1
Legend:
Note 1:
2:
TRISIO0 --11 1111 --11 1111
x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
For PIC12F615/617/HV615 only.
Read Only Register.
DS41302D-page 88
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
11.0
ENHANCED CAPTURE/
COMPARE/PWM (WITH AUTOSHUTDOWN AND DEAD BAND)
MODULE (PIC12F615/617/
HV615 ONLY)
The Enhanced Capture/Compare/PWM module is a
peripheral which allows the user to time and control
different events. In Capture mode, the peripheral
allows the timing of the duration of an event.The
Compare mode allows the user to trigger an external
REGISTER 11-1:
event when a predetermined amount of time has
expired. The PWM mode can generate a Pulse-Width
Modulated signal of varying frequency and duty cycle.
Table 11-1 shows the timer resources required by the
ECCP module.
TABLE 11-1:
ECCP MODE – TIMER
RESOURCES REQUIRED
ECCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
CCP1CON: ENHANCED CCP1 CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
P1M
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
P1M: PWM Output Configuration bits
If CCP1M = 00, 01, 10:
x = P1A assigned as Capture/Compare input; P1B assigned as port pins
If CCP1M = 11:
0 = Single output; P1A modulated; P1B assigned as port pins
1 = Half-Bridge output; P1A, P1B modulated with dead-band control
bit 6
Unimplemented: Read as ‘0’
bit 5-4
DC1B: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M: ECCP Mode Select bits
0000 =Capture/Compare/PWM off (resets ECCP module)
0001 =Unused (reserved)
0010 =Compare mode, toggle output on match (CCP1IF bit is set)
0011 =Unused (reserved)
0100 =Capture mode, every falling edge
0101 =Capture mode, every rising edge
0110 =Capture mode, every 4th rising edge
0111 =Capture mode, every 16th rising edge
1000 =Compare mode, set output on match (CCP1IF bit is set)
1001 =Compare mode, clear output on match (CCP1IF bit is set)
1010 =Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)
1011 =Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2 and starts
an A/D conversion, if the ADC module is enabled)
1100 =PWM mode; P1A active-high; P1B active-high
1101 =PWM mode; P1A active-high; P1B active-low
1110 =PWM mode; P1A active-low; P1B active-high
1111 =PWM mode; P1A active-low; P1B active-low
2010 Microchip Technology Inc.
DS41302D-page 89
PIC12F609/615/617/12HV609/615
11.1
11.1.2
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin CCP1. An event is defined as one of the
following and is configured by the CCP1M bits of
the CCP1CON register:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCP1IF of the PIR1 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value (see Figure 11-1).
11.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
Note:
If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 11-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
CCPR1H
and
Edge Detect
11.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE1 register clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR1 register
following any change in operating mode.
11.1.4
CCP PRESCALER
There are four prescaler settings specified by the
CCP1M bits of the CCP1CON register.
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler (see Example 11-1).
EXAMPLE 11-1:
CLRF
MOVLW
CCPR1L
Capture
Enable
TMR1H
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON
Set Flag bit CCP1IF
(PIR1 register)
CCP1
pin
TIMER1 MODE SELECTION
MOVWF
;Set Bank bits to point
;to CCP1CON
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; move value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
TMR1L
CCP1CON
System Clock (FOSC)
DS41302D-page 90
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 11-2:
Name
CCP1CON
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
P1M
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
CCP1M0 0-00 0000 0-00 0000
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx uuuu uuuu
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 0000
PIE1
—
ADIE(1)
CCP1IE(1)
—
CMIE
—
TMR2IE(1)
TMR1IE
-00- 0-00 -00- 0-00
PIR1
—
ADIF(1)
CCP1IF(1)
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00 -00- 0-00
INTCON
T1CON
T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TRISIO
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0 --11 1111 --11 1111
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture.
Note 1: For PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 91
PIC12F609/615/617/12HV609/615
11.2
11.2.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 module may:
•
•
•
•
•
Toggle the CCP1 output.
Set the CCP1 output.
Clear the CCP1 output.
Generate a Special Event Trigger.
Generate a Software Interrupt.
All Compare modes can generate an interrupt.
FIGURE 11-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCP1CON
Mode Select
Q
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
Special Event Trigger
Special Event Trigger will:
• Clear TMR1H and TMR1L registers.
• NOT set interrupt flag bit TMR1IF of the PIR1 register.
• Set the GO/DONE bit to start the ADC conversion.
11.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
Note:
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
11.2.4
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M = 1011), the CCP1 module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCP1 module does not assert control of the CCP1
pin in this mode (see the CCP1CON register).
Set CCP1IF Interrupt Flag
(PIR1)
4
CCPR1H CCPR1L
CCP1
Pin
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
11.2.3
The action on the pin is based on the value of the
CCP1M control bits of the CCP1CON register.
TIMER1 MODE SELECTION
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. This
allows the CCPR1H, CCPR1L register pair to
effectively provide a 16-bit programmable period
register for Timer1.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMRxIF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
DS41302D-page 92
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 11-3:
Name
CCP1CON
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
P1M
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
CCP1M0 0-00 0000 0-00 0000
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx uuuu uuuu
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 0000
PIE1
—
ADIE(1)
CCP1IE(1)
—
CMIE
—
TMR2IE(1)
TMR1IE
-00- 0-00 -00- 0-00
PIR1
—
ADIF(1)
CCP1IF(1)
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00 -00- 0-00
TMR1CS
TMR1ON 0000 0000 uuuu uuuu
INTCON
T1CON
T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR2
Timer2 Module Register
TRISIO
—
—
TRISIO5
0000 0000 0000 0000
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0 --11 1111 --11 1111
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Compare.
Note 1: For PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 93
PIC12F609/615/617/12HV609/615
11.3
PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCP1 pin. The duty cycle, period and
resolution are determined by the following registers:
•
•
•
•
PR2
T2CON
CCPR1L
CCP1CON
FIGURE 11-4:
CCP PWM OUTPUT
Period
Pulse Width
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCP1 pin. Since the CCP1 pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCP1 pin output driver.
Note:
The PWM output (Figure 11-4) has a time base
(period) and a time that the output stays high (duty
cycle).
TMR2 = PR2
TMR2 = CCPRxL:CCPxCON
TMR2 = 0
Clearing the CCP1CON register will
relinquish CCP1 control of the CCP1 pin.
Figure 11-3 shows a simplified block diagram of PWM
operation.
Figure 11-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 11.3.7
“Setup for PWM Operation”.
FIGURE 11-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON
Duty Cycle Registers
CCPR1L
CCPR1H(2) (Slave)
CCP1
R
Comparator
TMR2
(1)
Q
S
TRIS
Comparator
PR2
Note 1:
2:
Clear Timer2,
toggle CCP1 pin and
latch duty cycle
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPR1H is a read-only register.
DS41302D-page 94
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
11.3.1
PWM PERIOD
EQUATION 11-2:
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
EQUATION 11-1:
T OSC (TMR2 Prescale Value)
EQUATION 11-3:
(TMR2 Prescale Value)
DUTY CYCLE RATIO
CCPR1L:CCP1CON
Duty Cycle Ratio = ----------------------------------------------------------------------4 PR2 + 1
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H.
11.3.2
Pulse Width = CCPR1L:CCP1CON
PWM PERIOD
PWM Period = PR2 + 1 4 T OSC
Note:
PULSE WIDTH
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
The Timer2 postscaler (see Section 8.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
When the 10-bit time base matches the CCPR1H and
2-bit latch, then the CCP1 pin is cleared (see Figure 113).
PWM DUTY CYCLE
11.3.3
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the DC1B
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 11-4.
EQUATION 11-4:
TABLE 11-4:
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 11-5:
PWM RESOLUTION
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cycle
ratio.
PWM RESOLUTION
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
2010 Microchip Technology Inc.
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
DS41302D-page 95
PIC12F609/615/617/12HV609/615
11.3.4
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCP1
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
11.3.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 4.0 “Oscillator Module” for additional
details.
11.3.6
11.3.7
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
•
EFFECTS OF RESET
•
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
•
6.
•
•
DS41302D-page 96
SETUP FOR PWM OPERATION
Disable the PWM pin (CCP1) output drivers by
setting the associated TRIS bit.
Set the PWM period by loading the PR2 register.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
Set the PWM duty cycle by loading the CCPR1L
register and DC1B bits of the CCP1CON register.
Configure and start Timer2:
Clear the TMR2IF interrupt flag bit of the PIR1
register.
Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
Enable PWM output after a new PWM cycle has
started:
Wait until Timer2 overflows (TMR2IF bit of the
PIR1 register is set).
Enable the CCP1 pin output driver by clearing
the associated TRIS bit.
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
11.4
PWM (Enhanced Mode)
The PWM outputs are multiplexed with I/O pins and are
designated P1A and P1B. The polarity of the PWM pins
is configurable and is selected by setting the CCP1M
bits in the CCP1CON register appropriately.
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
output modes:
Table 11-6 shows the pin assignments for each
Enhanced PWM mode.
• Single PWM
• Half-Bridge PWM
Figure 11-5 shows an example of a simplified block
diagram of the Enhanced PWM module.
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
FIGURE 11-5:
Note:
To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
CCP1
CCP1M
4
P1M
Duty Cycle Registers
2
CCPR1L
(APFCON)
P1ASEL
CCP1/P1A
0
CCPR1H (Slave)
CCP1/P1A
TRISIO2
1
R
Comparator
TMR2
Q
(1)
(APFCON)
P1BSEL
S
P1B
0
Comparator
PR2
CCP1/P1A*
TRISIO5
Output
Controller
Clear Timer2,
toggle PWM pin and
latch duty cycle
TRISIO0
P1B
1
P1B*
TRISIO4
PWM1CON
Note
*
1:
Alternate pin function.
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 11-6:
EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode
P1M
CCP1/P1A
P1B
Single
00
Yes(1)
Yes(1)
Half-Bridge
10
Yes
Yes
2010 Microchip Technology Inc.
DS41302D-page 97
PIC12F609/615/617/12HV609/615
FIGURE 11-6:
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
Signal
P1M
PR2+1
Pulse
Width
0
Period
00
(Single Output)
P1A Modulated
Delay(1)
Delay(1)
P1A Modulated
10
(Half-Bridge)
P1B Modulated
P1A Active
Relationships:
P1B Inactive
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L:CCP1CON) * (TMR2 Prescale Value)
P1C Inactive
• Delay = 4 * TOSC * (PWM1CON)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
P1D Modulated
FIGURE 11-7:
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
Signal
P1M
PR2+1
Pulse
Width
0
Period
00
(Single Output)
P1A Modulated
P1A Modulated
Delay(1)
10
(Half-Bridge)
Delay(1)
P1B Modulated
P1A Active
Relationships:
P1B Inactive
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Pulse Width = TOSC * (CCPR1L:CCP1CON) * (TMR2 Prescale Value)
P1C Inactive
• Delay = 4 * TOSC * (PWM1CON)
Note
1:
DS41302D-page 98
Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
P1D Modulated
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
11.4.1
HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCP1/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see Figure 11-8).
This mode can be used for Half-Bridge applications, as
shown in Figure 11-9, or for Full-Bridge applications,
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in HalfBridge power devices. The value of the PDC bits of
the PWM1CON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains inactive during the entire cycle. See
Section 11.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 11-8:
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
FIGURE 11-9:
EXAMPLE OF HALFBRIDGE PWM OUTPUT
At this time, the TMR2 register is equal to the
PR2 register.
Output signals are shown as active-high.
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
P1A
Load
FET
Driver
+
P1B
-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET
Driver
FET
Driver
P1A
FET
Driver
Load
FET
Driver
P1B
2010 Microchip Technology Inc.
DS41302D-page 99
PIC12F609/615/617/12HV609/615
11.4.2
START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
Note:
When the microcontroller is released from
Reset, all of the I/O pins are in the highimpedance state. The external circuits
must keep the power switch devices in the
OFF state until the microcontroller drives
the I/O pins with the proper signal levels or
activates the PWM output(s).
The CCP1M bits of the CCP1CON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each PWM output pin (P1A
and P1B). The PWM output polarities must be selected
before the PWM pin output drivers are enabled.
Changing the polarity configuration while the PWM pin
output drivers are enable is not recommended since it
may result in damage to the application circuits.
The P1A and P1B output latches may not be in the proper
states when the PWM module is initialized. Enabling the
PWM pin output drivers at the same time as the
Enhanced PWM modes may cause damage to the
application circuit. The Enhanced PWM modes must be
enabled in the proper Output mode and complete a full
PWM cycle before configuring the PWM pin output
drivers. The completion of a full PWM cycle is indicated
by the TMR2IF bit of the PIR1 register being set as the
second PWM period begins.
11.4.3
OPERATION DURING SLEEP
When the device is placed in sleep, the allocated timer
will not increment and the state of the module will not
change. If the CCP1 pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
DS41302D-page 100
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
11.4.4
ENHANCED PWM AUTOSHUTDOWN MODE
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state. Refer to Figure 1.
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
When a shutdown event occurs, two things happen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 11.4.5 “Auto-Restart Mode”).
The auto-shutdown sources are selected using the
ECCPASx bits of the ECCPAS register. A shutdown
event may be generated by:
The enabled PWM pins are asynchronously placed in
their shutdown states. The state of P1A is determined by
the PSSAC bit. The state of P1B is determined by the
PSSBD bit. The PSSAC and PSSBD bits are located in
the ECCPAS register. Each pin may be placed into one
of three states:
• A logic ‘0’ on the INT pin
• Comparator
• Setting the ECCPASE bit in firmware
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
FIGURE 11-10:
AUTO-SHUTDOWN BLOCK DIAGRAM
ECCPAS
111
110
101
100
INT
011
010
From Comparator
PSSAC
001
000
P1A_DRV
PRSEN
1
0
PSSAC
R
From Data Bus
Write to ECCPASE
S
P1A
TRISx
D
Q
ECCPASE
PSSBD
P1B_DRV
1
0
PSSBD
TRISx
2010 Microchip Technology Inc.
P1B
DS41302D-page 101
PIC12F609/615/617/12HV609/615
REGISTER 11-2:
ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4
ECCPAS: ECCP Auto-shutdown Source Select bits
000 =Auto-Shutdown is disabled
001 =Comparator output change
010 =Auto-Shutdown is disabled
011 =Comparator output change(1)
100 =VIL on INT pin
101 =VIL on INT pin or Comparator change
110 =VIL on INT pin(1)
111 =VIL on INT pin or Comparator change
bit 3-2
PSSAC: Pin P1A Shutdown State Control bits
00 = Drive pin P1A to ‘0’
01 = Drive pin P1A to ‘1’
1x = Pin P1A tri-state
bit 1-0
PSSBD: Pin P1B Shutdown State Control bits
00 = Drive pin P1B to ‘0’
01 = Drive pin P1B to ‘1’
1x = Pin P1B tri-state
Note 1:
If CMSYNC is enabled, the shutdown will be delayed by Timer1.
Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal.
As long as the level is present, the autoshutdown will persist.
2: Writing to the ECCPASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
DS41302D-page 102
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 11-11:
PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
ECCPASE
Cleared by
Shutdown
Shutdown Firmware PWM
Event Occurs Event Clears
Resumes
Start of
PWM Period
11.4.5
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 11-12:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
Start of
PWM Period
2010 Microchip Technology Inc.
Shutdown
Shutdown
Event Occurs Event Clears
PWM
Resumes
DS41302D-page 103
PIC12F609/615/617/12HV609/615
11.4.6
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 11-13:
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
During this brief interval, a very high current (shootthrough current) will flow through both power switches,
shorting the bridge supply. To avoid this potentially
destructive shoot-through current from flowing during
switching, turning on either of the power switches is
normally delayed to allow the other switch to
completely turn off.
Period
Period
Pulse Width
P1A(2)
td
td
P1B(2)
(1)
(1)
(1)
td = Dead-Band Delay
Note 1:
2:
In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state
to the active state. See Figure 11-13 for illustration. The
lower seven bits of the associated PWMxCON register
(Register 11-3) sets the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
FIGURE 11-14:
EXAMPLE OF HALFBRIDGE PWM OUTPUT
At this time, the TMR2 register is equal to the
PR2 register.
Output signals are shown as active-high.
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
DS41302D-page 104
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 11-3:
PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0
PDC: PWM Delay Count bits
PDCn =Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should
transition active and the actual time it transitions active
TABLE 11-7:
Name
APFCON
(1)
CCP1CON
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
T1GSEL
—
—
P1BSEL
P1ASEL
P1M
—
DC1B1
DC1B0
CCPR1L(1)
Capture/Compare/PWM Register 1 Low Byte
CCPR1H(1)
Capture/Compare/PWM Register 1 High Byte
CMCON0
CMCON1
ECCPAS(1)
CMON
COUT
CMOE
CMPOL
—
—
—
T1ACS
Value on
all other
Resets
---0 --00 ---0 --00
CCP1M0 0-00 0000 0-00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
CMR
—
CMHYS
—
T1GSS
PSSAC1
PSSAC0
PSSBD1
CMCH
0000 -0-0 0000 -0-0
CMSYNC ---0 0-10 ---0 0-10
PSSBD0
0000 0000 0000 0000
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000 0000 0000
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 0000
PIE1
—
ADIE(1)
CCP1IE(1)
—
CMIE
—
TMR2IE(1)
TMR1IE
-00- 0-00 -00- 0-00
PIR1
—
ADIF(1)
CCP1IF(1)
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00 -00- 0-00
T2CON(1)
—
PWM1CON
INTCON
TMR2(1)
TRISIO
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
CCP1M3 CCP1M2 CCP1M1
Value on
POR, BOR
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Module Register
—
—
0000 0000 0000 0000
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111 --11 1111
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
Note 1: For PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 105
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 106
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.0
SPECIAL FEATURES OF THE
CPU
The PIC12F609/615/617/12HV609/615 has a host of
features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power-saving features and offer
code protection.
These features are:
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming
12.1
Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 12-1.
These bits are mapped in program memory location
2007h.
Note:
Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h3FFFh), which can be accessed only during
programming. See Memory Programming
Specification
(DS41204)
for more
information.
The PIC12F609/615/617/12HV609/615 has two timers
that offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in Reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 64 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can use the Powerup Timer to provide at least a 64 ms Reset. With these
three functions-on-chip, most applications need no
external Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer Wake-up
• An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 12-1).
2010 Microchip Technology Inc.
DS41302D-page 107
PIC12F609/615/617/12HV609/615
REGISTER 12-1:
U-1
—
U-1
—
U-1
—
CONFIG: CONFIGURATION WORD REGISTER (ADDRESS: 2007h) FOR
PIC12F609/615/HV609/615 ONLY
U-1
—
R/P-1
BOREN1
R/P-1
(1)
BOREN0
R/P-1
(1)
R/P-1
IOSCFS CP
(2)
R/P-1
MCLRE
(3)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 13
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 13-10
Unimplemented: Read as ‘1’
bit 9-8
BOREN: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
0x = BOR disabled
bit 7
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz
0 = 4 MHz
bit 6
CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5
MCLRE: MCLR Pin Function Select bit(3)
1 = MCLR pin function is MCLR
0 = MCLR pin function is digital input, MCLR internally tied to VDD
bit 4
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0
Note 1:
2:
3:
FOSC: Oscillator Selection bits
111 =RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110 =RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101 =INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on
GP5/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on
GP5/OSC1/CLKIN
011 =EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010 =HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire program memory will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
DS41302D-page 108
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 12-2:
U-1
U-1
—
—
R/P-1
CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) FOR PIC12F617 ONLY
R/P-1
R/P-1
R/P-1
R/P-1
WRT1 WRT0 BOREN1 BOREN0 IOSCFS
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
R/P-1
R/P-1
R/P-1
R/P-1
WDTE FOSC2 F0SC1 F0SC0
bit
13
bit 0
bit 13-12
Unimplemented: Read as ‘1’
bit 11-10
WRT: Flash Program Memory Self Write Enable bits
11 = Write protection off
10 = 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON1 control
01 = 000h to 3FFh write protected, 400h to 7FFh may be modified by PMCON1 control
00 = 000h to 7FFh write protected, entire program memory is write protected.
bit 9-8
BOREN: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR disabled during Sleep and enabled during operation
0X = BOR disabled
bit 7
IOSCFS: Internal Oscillator Frequency Select
1 = 8 MHz
0 = 4 MHz
bit 6
CP: Code Protection
1 = Program memory is not code protected
0 = Program memory is external read and write protected
bit 5
MCLRE: MCLR Pin Function Select
1 = MCLR pin is MCLR function and weak internal pull-up is enabled
0 = MCLR pin is alternate function, MCLR function is internally disabled
bit 4
PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0
FOSC: Oscillator Selection bits
000 =LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT
001 =XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT
010 =HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT
011 =EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN
100 =INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN
101 =INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/
CLKIN
110 =EXTRCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
111 =EXTRC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
Note 1:Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘1’
P = Programmable
-n = Value at POR
1 = bit is set
0 = bit is cleared
x = bit is unknown
2010 Microchip Technology Inc.
DS41302D-page 109
PIC12F609/615/617/12HV609/615
12.2
Calibration Bits
The 8 MHz internal oscillator is factory calibrated.
These calibration values are stored in fuses located in
the Calibration Word (2008h). The Calibration Word is
not erased when using the specified bulk erase
sequence in the Memory Programming Specification
(DS41204) and thus, does not require reprogramming.
12.3
Reset
The
PIC12F609/615/617/12HV609/615
device
differentiates between various kinds of Reset:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
•
•
•
•
•
Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
WDT wake-up does not cause register resets in the
same manner as a WDT Reset since wake-up is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 12-2. Software can use
these bits to determine the nature of the Reset. See
Table 12-5 for a full description of Reset states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 16.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1/
CLKIN pin
PWRT
On-Chip
RC OSC
11-bit Ripple Counter
Enable PWRT
Enable OST
Note
1:
Refer to the Configuration Word register (Register 12-1).
DS41302D-page 110
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.3.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 16.0 “Electrical
Specifications” for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until VDD
reaches VBOR (see Section 12.3.4 “Brown-out Reset
(BOR)”).
Note:
FIGURE 12-2:
VDD
PIC®
MCU
R1
1 kor greater)
R2
MCLR
SW1
(optional)
100
needed with capacitor)
C1
0.1 F
(optional, not critical)
The POR circuit does not produce an
internal Reset when VDD declines. To reenable the POR, VDD must reach Vss for
a minimum of 100 s.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
RECOMMENDED MCLR
CIRCUIT
12.3.3
POWER-UP TIMER (PWRT)
PIC12F609/615/617/12HV609/615 has a noise filter in
the MCLR Reset path. The filter will detect and ignore
small pulses.
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from an internal
RC oscillator. For more information, see Section 4.4
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should be enabled when Brown-out Reset is
enabled, although it is not required.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The Power-up Timer delay will vary from chip-to-chip
due to:
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to VDD. The use of an RC network, as shown in
Figure 12-2, is suggested.
• VDD variation
• Temperature variation
• Process variation
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
12.3.2
MCLR
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the GP3/MCLR pin
becomes an external Reset input. In this mode, the
GP3/MCLR pin has a weak pull-up to VDD.
2010 Microchip Technology Inc.
See DC parameters for details
“Electrical Specifications”).
Note:
(Section 16.0
Voltage spikes below VSS at the MCLR
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resistor of 50-100 should be used when
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to VSS.
DS41302D-page 111
PIC12F609/615/617/12HV609/615
12.3.4
BROWN-OUT RESET (BOR)
On any Reset (Power-on, Brown-out Reset, Watchdog
timer, etc.), the chip will remain in Reset until VDD rises
above VBOR (see Figure 12-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip
in Reset an additional 64 ms.
The BOREN0 and BOREN1 bits in the Configuration
Word register select one of three BOR modes. One
mode has been added to allow control of the BOR
enable for lower current during Sleep. By selecting
BOREN = 10, the BOR is automatically disabled
in Sleep to conserve power and enabled on wake-up.
See Register 12-1 for the Configuration Word
definition.
Note:
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
A brown-out occurs when VDD falls below VBOR for
greater than parameter TBOR (see Section 16.0
“Electrical Specifications”). The brown-out condition
will reset the device. This will occur regardless of VDD
slew rate. A Brown-out Reset may not occur if VDD falls
below VBOR for less than parameter TBOR.
FIGURE 12-3:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
64 ms(1)
VDD
Internal
Reset
VBOR
< 64 ms
64 ms(1)
VDD
Internal
Reset
Note 1:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
VBOR
64 ms(1)
64 ms delay only if PWRTE bit is programmed to ‘0’.
DS41302D-page 112
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.3.5
TIME-OUT SEQUENCE
12.3.6
On power-up, the time-out sequence is as follows:
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
• PWRT time-out is invoked after POR has expired.
• OST is activated after the PWRT time-out has
expired.
Bit 0 is BOR (Brown-out). BOR is unknown on Poweron Reset. It must then be set by the user and checked
on subsequent Resets to see if BOR = 0, indicating that
a Brown-out has occurred. The BOR Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BOREN = 00 in the
Configuration Word register).
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F609/615/617/
12HV609/615 device operating in parallel.
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Poweron Reset has occurred (i.e., VDD may have gone too
low).
Table 12-6 shows the Reset conditions for some
special registers, while Table 12-5 shows the Reset
conditions for all the registers.
TABLE 12-1:
POWER CONTROL (PCON)
REGISTER
For more information, see Section 12.3.4 “Brown-out
Reset (BOR)”.
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
TPWRT + 1024 •
TOSC
1024 • TOSC
TPWRT + 1024 •
TOSC
1024 • TOSC
1024 • TOSC
TPWRT
—
TPWRT
—
—
Oscillator Configuration
XT, HS, LP
RC, EC, INTOSC
TABLE 12-2:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
x
1
1
Power-on Reset
u
0
1
1
Brown-out Reset
u
u
0
u
WDT Reset
u
u
0
0
WDT Wake-up
u
u
u
u
MCLR Reset during normal operation
u
u
1
0
MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
TABLE 12-3:
Name
PCON
STATUS
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Value on
all other
Resets(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Shaded cells are not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2010 Microchip Technology Inc.
DS41302D-page 113
PIC12F609/615/617/12HV609/615
FIGURE 12-4:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
FIGURE 12-5:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
DS41302D-page 114
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 12-4:
Register
W
INDF
TMR0
INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609)
Address
Power-on
Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
Wake-up from Sleep through
Interrupt
Wake-up from Sleep through
WDT Time-out
—
xxxx xxxx
uuuu uuuu
uuuu uuuu
00h/80h
xxxx xxxx
xxxx xxxx
uuuu uuuu
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
GPIO
05h
--x0 x000
--u0 u000
--uu uuuu
PCLATH
0Ah/8Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh
0000 0000
0000 0000
uuuu uuuu(2)
PIR1
0Ch
----- 0--0
---- 0--0
---- u--u(2)
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
0000 0000
uuuu uuuu
-uuu uuuu
VRCON
19h
0-00 0000
0-00 0000
u-uu uuuu
CMCON0
1Ah
0000 -0-0
0000 -0-0
uuuu -u-u
CMCON1
1Ch
---0 0-10
---0 0-10
---u u-qu
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
TRISIO
85h
--11 1111
--11 1111
--uu uuuu
PIE1
8Ch
----- 0--0
---- 0--0
---- u--u
PCON
8Eh
---- --0x
---- --uu(1, 5)
---- --uu
OSCTUNE
90h
---0 0000
---u uuuu
---u uuuu
WPU
95h
--11 -111
--11 -111
--uu -uuu
IOC
96h
--00 0000
--00 0000
--uu uuuu
ANSEL
9Fh
---- 1-11
---- 1-11
---- q-qq
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
See Table 12-6 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
2010 Microchip Technology Inc.
DS41302D-page 115
PIC12F609/615/617/12HV609/615
TABLE 12-5:
Register
INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/617/HV615)
Address
Power-on Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
W
INDF
TMR0
Wake-up from Sleep through
Interrupt
Wake-up from Sleep through
WDT Time-out
—
xxxx xxxx
uuuu uuuu
uuuu uuuu
00h/80h
xxxx xxxx
xxxx xxxx
uuuu uuuu
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
GPIO
05h
--x0 x000
--u0 u000
--uu uuuu
PCLATH
0Ah/8Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh
0000 0000
0000 0000
uuuu uuuu(2)
PIR1
0Ch
-000 0-00
-000 0-00
-uuu u-uu(2)
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
0000 0000
uuuu uuuu
-uuu uuuu
(1)
11h
0000 0000
0000 0000
uuuu uuuu
12h
-000 0000
-000 0000
-uuu uuuu
(1)
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H(1)
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON(1)
15h
0-00 0000
0-00 0000
u-uu uuuu
PWM1CON(1)
16h
0000 0000
0000 0000
uuuu uuuu
ECCPAS(1)
17h
0000 0000
0000 0000
uuuu uuuu
VRCON
19h
0-00 0000
0-00 0000
u-uu uuuu
CMCON0
1Ah
0000 -0-0
0000 -0-0
uuuu -u-u
CMCON1
1Ch
---0 0-10
---0 0-10
---u u-qu
(1)
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0(1)
1Fh
00-0 0000
00-0 0000
uu-u uuuu
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
TRISIO
85h
--11 1111
--11 1111
--uu uuuu
PIE1
8Ch
-00- 0-00
-00- 0-00
-uu- u-uu
PCON
8Eh
---- --0x
OSCTUNE
90h
---0 0000
---u uuuu
---u uuuu
PR2
92h
1111 1111
1111 1111
1111 1111
APFCON
93h
---0 --00
---0 --00
---u --uu
WPU
95h
--11 -111
--11 -111
--uu -uuu
IOC
96h
--00 0000
--00 0000
--uu uuuu
(6)
98h
---- -000
---- -000
---- -uuu
PMCON2(6)
99h
---- ----
---- ----
---- ----
PMADRL(6)
9Ah
0000 0000
0000 0000
uuuu uuuu
TMR2
T2CON(1)
CCPR1L
ADRESH
PMCON1
Legend:
Note 1:
2:
3:
4:
5:
6:
---- --uu(1, 5)
---- --uu
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 12-6 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
For PIC12F617 only.
DS41302D-page 116
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 12-5:
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)(PIC12F615/617/HV615)
Register
PMADRH(6)
Address
Power-on Reset
MCLR Reset
WDT Reset (Continued)
Brown-out Reset(1)
Wake-up from Sleep through
Interrupt
Wake-up from Sleep through
WDT Time-out (Continued)
9Bh
---- -000
---- -000
---- -uuu
(6)
9Ch
0000 0000
0000 0000
uuuu uuuu
PMDATH(6)
9Dh
--00 0000
--00 0000
--uu uuuu
ADRESL(1)
9Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
9Fh
-000 1111
-000 1111
-uuu qqqq
PMDATL
ANSEL
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 12-6 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
For PIC12F617 only.
TABLE 12-6:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
Status
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during Sleep
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 uuuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --10
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from Sleep
PC + 1
(1)
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.
2010 Microchip Technology Inc.
DS41302D-page 117
PIC12F609/615/617/12HV609/615
12.4
Interrupts
The PIC12F609/615/617/12HV609/615 has 8 sources
of interrupt:
•
•
•
•
•
•
•
External Interrupt GP2/INT
Timer0 Overflow Interrupt
GPIO Change Interrupts
Comparator Interrupt
A/D Interrupt (PIC12F615/617/HV615 only)
Timer1 Overflow Interrupt
Timer2 Match Interrupt (PIC12F615/617/HV615
only)
• Enhanced CCP Interrupt (PIC12F615/617/HV615
only)
• Flash Memory Self Write (PIC12F617 only)
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIE1 register. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occur automatically:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• GPIO Change Interrupt
• Timer0 Overflow Interrupt
Figure 12-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
For additional information on Timer1, Timer2,
comparators, ADC, Enhanced CCP modules, refer to
the respective peripheral section.
12.4.1
GP2/INT INTERRUPT
The external interrupt on the GP2/INT pin is edgetriggered; either on the rising edge if the INTEDG bit of
the OPTION register is set, or the falling edge, if the
INTEDG bit is clear. When a valid edge appears on the
GP2/INT pin, the INTF bit of the INTCON register is set.
This interrupt can be disabled by clearing the INTE
control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
before re-enabling this interrupt. The GP2/INT interrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 12.7
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 12-9 for timing of wake-up from Sleep through
GP2/INT interrupt.
Note:
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
•
•
•
•
•
A/D Interrupt
Comparator Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
Enhanced CCP Interrupt
For external interrupt events, such as the INT pin or
GPIO change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
DS41302D-page 118
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.4.2
TIMER0 INTERRUPT
12.4.3
An overflow (FFh 00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 6.0 “Timer0 Module”
for operation of the Timer0 module.
An input change on GPIO sets the GPIF bit of the
INTCON register. The interrupt can be enabled/
disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note:
FIGURE 12-7:
GPIO INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
INTERRUPT LOGIC
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
T0IF
T0IE
(615/617 only) TMR2IF
TMR2IE
INTF
INTE
GPIF
GPIE
TMR1IF
TMR1IE
CMIF
CMIE
Wake-up (If in Sleep mode)(1)
Interrupt to CPU
PEIE
GIE
(615/617 only) ADIF
ADIE
(615/617 only) CCP1IF
CCP1IE
Note 1:
2010 Microchip Technology Inc.
Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”.
DS41302D-page 119
PIC12F609/615/617/12HV609/615
FIGURE 12-8:
INT PIN INTERRUPT TIMING
Q1 Q2
Q3
Q4 Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3 Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag
(INTCON reg.)
Interrupt Latency (2)
(5)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC
Instruction
Fetched
PC + 1
Inst (PC – 1)
0004h
PC + 1
—
Inst (PC + 1)
Inst (PC)
Instruction
Executed
Note 1:
PC
Dummy Cycle
Inst (PC)
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT is available only in INTOSC and RC Oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 16.0 “Electrical Specifications”.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-7:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
INTCON
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 0000
IOC
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000 --00 0000
PIR1
—
ADIF(1) CCP1IF(1)
—
CMIF
—
TMR2IF(1)
TMR1IF
-00- 0-00 -000 0-00
—
ADIE(1)
—
CMIE
—
TMR2IE(1) TMR1IE -00- 0-00 -000 0-00
PIE1
CCP1IE(1)
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
Note 1: PIC12F615/617/HV615 only.
DS41302D-page 120
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.5
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary
holding
registers
W_TEMP
and
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Figure 2-3). These 16 locations are
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in Example 12-1 can be used to:
•
•
•
•
•
Store the W register
Store the STATUS register
Execute the ISR code
Restore the Status (and Bank Select Bit register)
Restore the W register
Note:
The PIC12F609/615/617/12HV609/615
does not require saving the PCLATH.
However, if computed GOTOs are used in
both the ISR and the main code, the
PCLATH must be saved and restored in
the ISR.
EXAMPLE 12-1:
MOVWF
SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP
STATUS,W
MOVWF
STATUS_TEMP
:
:(ISR)
:
SWAPF
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
12.6
STATUS
W_TEMP,F
W_TEMP,W
;Copy W to TEMP
;Swap status to
;Swaps are used
;Save status to
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin and INTOSC. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped (for example, by
execution of a SLEEP instruction). During normal operation, a WDT time out generates a device Reset. If the
device is in Sleep mode, a WDT time out causes the
device to wake-up and continue with normal operation.
The WDT can be permanently disabled by programming the Configuration bit, WDTE, as clear
(Section 12.1 “Configuration Bits”).
2010 Microchip Technology Inc.
register
be saved into W
because they do not affect the status bits
bank zero STATUS_TEMP register
12.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time out.
DS41302D-page 121
PIC12F609/615/617/12HV609/615
12.6.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worstcase conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT time out occurs.
FIGURE 12-2:
WATCHDOG TIMER BLOCK DIAGRAM
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
SYNC 2
Cycles
1
T0CKI
pin
TMR0
0
0
T0CS
T0SE
Set Flag bit T0IF
on Overflow
8-bit
Prescaler
PSA
1
8
PSA
3
1
PS
WDT
Time-Out
Watchdog
Timer
0
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS are bits in the OPTION register.
TABLE 12-8:
WDT STATUS
Conditions
WDT
WDTE = 0
CLRWDT Command
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
TABLE 12-9:
Cleared until the end of OST
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
OPTION_REG
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
IOSCFS
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
—
—
CONFIG
Legend:
Note 1:
Shaded cells are not used by the Watchdog Timer.
See Register 12-1 for operation of all Configuration Word register bits.
DS41302D-page 122
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.7
Power-Down Mode (Sleep)
The Power-Down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
•
•
•
•
•
WDT will be cleared but keeps running.
PD bit in the STATUS register is cleared.
TO bit is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before SLEEP
was executed (driving high, low or high-impedance).
For lowest current consumption in this mode, all I/O pins
should be either at VDD or VSS, with no external circuitry
drawing current from the I/O pin and the comparators
and CVREF should be disabled. I/O pins that are highimpedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip pullups on GPIO should be considered.
The MCLR pin must be at a logic high level.
Note:
12.7.1
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from GP2/INT pin, GPIO change or a
peripheral interrupt.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
Timer1 interrupt. Timer1 must be operating as
an asynchronous counter.
ECCP Capture mode interrupt.
A/D conversion (when A/D clock source is RC).
Comparator output changes state.
Interrupt-on-change.
External Interrupt from INT pin.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
Note:
If the global interrupts are disabled (GIE is
cleared) and any interrupt source has both
its interrupt enable bit and the corresponding interrupt flag bits set, the device will
immediately wake-up from Sleep.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
12.7.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
Immediately wake-up from Sleep. The SLEEP
instruction is executed. Therefore, the WDT and
WDT prescaler and postscaler (if enabled) will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction. See
Figure 12-9 for more details.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
2010 Microchip Technology Inc.
DS41302D-page 123
PIC12F609/615/617/12HV609/615
FIGURE 12-9:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON reg.)
Interrupt Latency (3)
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
12.8
PC
Inst(PC) = Sleep
Inst(PC – 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
1:
XT, HS or LP Oscillator mode assumed.
2:
TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes.
3:
GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.
4:
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note:
12.9
The entire Flash program memory will be
erased when the code protection is turned
off. See the MemoryProgramming
Specification
(DS41204)
for
more
information.
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
DS41302D-page 124
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.10 In-Circuit Serial Programming™
12.11 In-Circuit Debugger
ThePIC12F609/615/617/12HV609/615
microcontrollers can be serially programmed while in
the end application circuit. This is simply done with five
connections for:
Since in-circuit debugging requires access to three pins,
MPLAB® ICD 2 development with an 14-pin device is
not practical. A special 28-pin PIC12F609/615/617/
12HV609/615 ICD device is used with MPLAB ICD 2 to
provide separate clock, data and MCLR pins and frees
all normally available pins to the user.
clock
data
power
ground
programming voltage
A special debugging adapter allows the ICD device to
be used in place of a PIC12F609/615/617/12HV609/
615 device. The debugging adapter is the only source
of the ICD device.
This allows customers to manufacture boards with
unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a Program/Verify mode by
holding the GP0 and GP1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH. See the Memory
Programming Specification (DS41284) for more
information. GP0 becomes the programming data and
GP1 becomes the programming clock. Both GP0 and
GP1 are Schmitt Trigger inputs in Program/Verify
mode.
A typical In-Circuit Serial Programming connection is
shown in Figure 12-10.
FIGURE 12-10:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
+5V
VSS
0V
VPP
MCLR/VPP/GP3/RA3
CLK
GP1
Data I/O
GP0
*
*
*
To Normal
Connections
* Isolation devices (as required)
Note:
TABLE 12-10: DEBUGGER RESOURCES
Resource
Description
I/O pins
ICDCLK, ICDDATA
Stack
1 level
Program Memory
Address 0h must be NOP
700h-7FFh
For more information, see “MPLAB® ICD 2 In-Circuit
Debugger User’s Guide” (DS51331), available on
Microchip’s web site (www.microchip.com).
FIGURE 12-11:
PIC12F617/
PIC12F615/12HV615
PIC12F609/12HV609
VDD
*
When the ICD pin on the PIC12F609/615/617/
12HV609/615 ICD device is held low, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB
ICD 2. When the microcontroller has this feature
enabled, some of the resources are not available for
general use. Table 12-10 shows which features are
consumed by the background debugger.
28 PIN ICD PINOUT
28-Pin PDIP
In-Circuit Debug Device
VDD
CS0
CS1
CS2
RA5
RA4
RA3
RC5
RC4
RC3
NC
ICDCLK
ICDMCLR
ICDDATA
1
2
3
28
27
26
4
5
25
24
6
7
8
9
10
11
PIC16F616-ICD
•
•
•
•
•
23
22
21
20
19
18
12
17
13
14
16
15
GND
RA0
RA1
SHUNTEN
RA2
RC0
RC1
RC2
NC
NC
NC
NC
NC
ICD
To erase the device VDD must be above
the Bulk Erase VDD minimum given in the
Memory
Programming
Specification
(DS41284)
2010 Microchip Technology Inc.
DS41302D-page 125
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 126
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
13.0
VOLTAGE REGULATOR
The PIC12HV609/HV615 devices include a permanent
internal 5 volt (nominal) shunt regulator in parallel with
the VDD pin. This eliminates the need for an external
voltage regulator in systems sourced by an
unregulated supply. All external devices connected
directly to the VDD pin will share the regulated supply
voltage and contribute to the total VDD supply current
(ILOAD).
13.1
An external current limiting resistor, RSER, located
between the unregulated supply, VUNREG, and the VDD
pin, drops the difference in voltage between VUNREG
and VDD. RSER must be between RMAX and RMIN as
defined by Equation 13-1.
EQUATION 13-1:
RMAX =
RSER LIMITING RESISTOR
(VUMIN - 5V)
1.05 • (4 MA + ILOAD)
Regulator Operation
A shunt regulator generates a specific supply voltage
by creating a voltage drop across a pass resistor RSER.
The voltage at the VDD pin of the microcontroller is
monitored and compared to an internal voltage reference. The current through the resistor is then adjusted,
based on the result of the comparison, to produce a
voltage drop equal to the difference between the supply
voltage VUNREG and the VDD of the microcontroller.
See Figure 13-1 for voltage regulator schematic.
FIGURE 13-1:
VOLTAGE REGULATOR
RSER
ILOAD
VDD
CBYPASS
ISHUNT
Feedback
Where:
RMAX = maximum value of RSER (ohms)
RMIN
= minimum value of RSER (ohms)
VUMIN = minimum value of VUNREG
VUMAX = maximum value of VUNREG
VDD
= regulated voltage (5V nominal)
1.05
= compensation for +5% tolerance of RSER
0.95
= compensation for -5% tolerance of RSER
13.2
VSS
Device
(VUMAX - 5V)
0.95 • (50 MA)
ILOAD = maximum expected load current in mA
including I/O pin currents and external
circuits connected to VDD.
VUNREG
ISUPPLY
RMIN =
Regulator Considerations
The supply voltage VUNREG and load current are not
constant. Therefore, the current range of the regulator
is limited. Selecting a value for RSER must take these
three factors into consideration.
Since the regulator uses the band gap voltage as the
regulated voltage reference, this voltage reference is
permanently enabled in the PIC12HV609/HV615
devices.
The shunt regulator will still consume current when
below operating voltage range for the shunt regulator.
13.3
Design Considerations
For more information on using the shunt regulator and
managing current load, see Application Note AN1035,
“Designing with HV Microcontrollers” (DS01035).
2010 Microchip Technology Inc.
DS41302D-page 127
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 128
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
14.0
INSTRUCTION SET SUMMARY
The PIC12F609/615/617/12HV609/615 instruction set
is highly orthogonal and is comprised of three basic
categories:
TABLE 14-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
Register file address (0x00 to 0x7F)
f
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 14-1, while the various opcode
fields are summarized in Table 14-1.
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
Table 14-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
PC
Program Counter
TO
Time-out bit
Carry bit
C
DC
Digit carry bit
Zero bit
Z
PD
Power-down bit
FIGURE 14-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
Literal and control operations
General
8
7
OPCODE
Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
0
b = 3-bit bit address
f = 7-bit file register address
13
14.1
0
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
For example, a CLRF GPIO instruction will read GPIO,
clear all the data bits, then write the result back to
GPIO. This example would have the unintended
consequence of clearing the condition that set the
GPIF flag.
2010 Microchip Technology Inc.
DS41302D-page 129
PIC12F609/615/617/12HV609/615
TABLE 14-2:
PIC12F609/615/617/12HV609/615 INSTRUCTION SET
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1:
2:
3:
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS41302D-page 130
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
14.2
Instruction Descriptions
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the
W register.
k
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 127
0b7
Operation:
0 (f)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[ label ] BSF
f,b
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d 0,1
Operands:
0 f 127
0b7
Operation:
(W) + (f) (destination)
Operation:
1 (f)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
Description:
Bit ‘b’ in register ‘f’ is set.
ANDLW
AND literal with W
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BTFSC f,b
Operands:
0 k 255
Operands:
Operation:
(W) .AND. (k) (W)
0 f 127
0b7
Status Affected:
Z
Operation:
skip if (f) = 0
Description:
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
two-cycle instruction.
ANDWF
f,d
k
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
Operation:
(W) .AND. (f) (destination)
f,d
Status Affected:
Z
Description:
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
2010 Microchip Technology Inc.
f,b
DS41302D-page 131
PIC12F609/615/617/12HV609/615
BTFSS
Bit Test f, Skip if Set
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
0b
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