M
PIC16C5X
EPROM/ROM-Based 8-Bit CMOS Microcontroller Series
•
•
•
•
•
Devices Included in this Data Sheet:
•
•
•
•
•
•
•
•
•
•
PIC16C52
PIC16C54s
PIC16CR54s
PIC16C55s
PIC16C56s
PIC16CR56s
PIC16C57s
PIC16CR57s
PIC16C58s
PIC16CR58s
Note:
Peripheral Features:
The letter "s" used following the part
numbers throughout this document
indicate plural, meaning there is more
than one part variety for the indicated
device.
High-Performance RISC CPU:
• Only 33 single word instructions to learn
• All instructions are single cycle (200 ns) except for
program branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
Device
12-bit wide instructions
8-bit wide data path
Seven or eight special function hardware registers
Two-level deep hardware stack
Direct, indirect and relative addressing modes for
data and instructions
EPROM/
RAM
ROM
Pins
I/O
PIC16C52
PIC16C54
PIC16C54A
18
18
18
12
12
12
384
512
512
25
25
25
PIC16C54B
PIC16C54C
18
18
12
12
512
512
25
25
PIC16CR54A
PIC16CR54B
PIC16CR54C
PIC16C55
PIC16C55A
PIC16C56
PIC16C56A
PIC16CR56A
PIC16C57
PIC16C57C
PIC16CR57B
PIC16CR57C
PIC16C58A
PIC16C58B
PIC16CR58A
PIC16CR58B
18
18
18
28
28
18
18
18
28
28
28
28
18
18
18
18
12
12
12
20
20
12
12
12
20
20
20
20
12
12
12
12
512
512
512
512
512
1K
1K
1K
2K
2K
2K
2K
2K
2K
2K
2K
25
25
25
24
24
25
25
25
72
72
72
72
73
73
73
73
1998 Microchip Technology Inc.
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Power-On Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options:
- RC:
Low-cost RC oscillator
- XT:
Standard crystal/resonator
- HS:
High-speed crystal/resonator
- LP:
Power saving, low-frequency crystal
CMOS Technology:
• Low-power, high-speed CMOS EPROM/ROM
technology
• Fully static design
• Wide-operating voltage and temperature range:
- EPROM Commercial/Industrial 2.0V to 6.25V
- ROM Commercial/Industrial 2.0V to 6.25V
- EPROM Extended 2.5V to 6.0V
- ROM Extended 2.5V to 6.0V
• Low-power consumption
- < 2 mA typical @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 0.6 µA typical standby current
(with WDT disabled) @ 3V, 0°C to 70°C
Note:
Preliminary
In this document, figure and table titles
refer to all varieties of the part number
indicated, (i.e., The title "Figure 14-1:
Load Conditions - PIC16C54A", also
refers to PIC16LC54A and PIC16LV54A
parts).
DS30453B-page 1
PIC16C5X
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
18
17
16
15
14
13
12
11
10
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
28
MCLR/VPP
2
27
OSC1/CLKIN
N/C
3
26
VSS
4
25
OSC2/CLKOUT
RC7
24
RC6
23
21
RC5
RC4
RC3
N/C
5
RA0
6
RA1
7
RA2
8
RA3
9
20
RC2
RB0
10
19
RB1
11
18
RC1
RC0
RB2
12
17
RB7
RB3
13
16
RB6
RB4
14
15
RB5
22
SSOP
SSOP
DS30453B-page 2
20
19
18
17
16
15
14
13
12
11
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4
Preliminary
VSS
T0CKI
VDD
VDD
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
VSS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16C55s
PIC16C57s
PIC16CR57s
•1
2
3
4
5
6
7
8
9
10
PIC16C54s
PIC16CR54s
PIC16C56s
PIC16CR56s
PIC16C58s
PIC16CR58s
RA2
RA3
T0CKI
MCLR/VPP
VSS
VSS
RB0
RB1
RB2
RB3
•1
VDD
T0CKI
PIC16C55s
PIC16C57s
PIC16CR57s
PIC16C52s
PIC16C54s
PIC16CR54s
PIC16C56s
PIC16CR56s
PIC16C58s
PIC16CR58s
•1
2
3
4
5
6
7
8
9
RA2
RA3
T0CKI
MCLR/VPP
VSS
RB0
RB1
RB2
RB3
PDIP, SOIC, Windowed CERDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
1998 Microchip Technology Inc.
PIC16C5X
Device Differences
Oscillator
Selection
(Program)
Oscillator
Process
Technology
(Microns)
3.0-6.25
User
See Note 1
2.5-6.25
Factory
See Note 1
Device
Voltage
Range
PIC16C52
PIC16C54
PIC16C54A
2.0-6.25
User
See Note 1
0.9
—
No
PIC16C54B
2.5-5.5
User
See Note 1
0.7
PIC16CR54B
Yes
ROM
Equivalent
MCLR
Filter
0.9
—
No
1.2
PIC16CR54A
No
PIC16C54C
2.5-5.5
User
See Note 1
0.7
PIC16CR54C
Yes
PIC16C55
2.5-6.25
Factory
See Note 1
1.7
—
No
PIC16C55A
2.5-5.5
User
See Note 1
0.7
—
Yes
PIC16C56
2.5-6.25
Factory
See Note 1
1.7
—
No
PIC16C56A
2.5-5.5
User
See Note 1
0.7
PIC16CR56A
Yes
PIC16C57
2.5-6.25
Factory
See Note 1
1.2
—
No
PIC16C57C
2.5-5.5
User
See Note 1
0.7
PIC16CR57C
Yes
PIC16C58A
2.0-6.25
User
See Note 1
0.9
PIC16CR58A
No(2)
PIC16C58B
2.5-5.5
User
See Note 1
0.7
PIC16CR58B
Yes
PIC16CR54A
2.5-6.25
Factory
See Note 1
1.2
N/A
Yes
PIC16CR54B
2.5-5.5
Factory
See Note 1
0.7
N/A
Yes
PIC16CR54C
2.5-5.5
Factory
See Note 1
0.7
N/A
Yes
PIC16CR56A
2.5-5.5
Factory
See Note 1
0.7
N/A
Yes
PIC16CR57B
2.5-6.25
Factory
See Note 1
0.9
N/A
Yes
PIC16CR57C
2.5-5.5
Factory
See Note 1
0.7
N/A
Yes
PIC16CR58A
2.5-6.25
Factory
See Note 1
0.9
N/A
Yes
PIC16CR58B
2.5-5.5
Factory
See Note 1
0.7
N/A
Yes
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note 2: In PIC16LV58A, MCLR Filter = Yes
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 3
PIC16C5X
Table of Contents
1.0
General Description .............................................................................................................................................5
2.0
PIC16C5X Device Varieties.................................................................................................................................7
3.0
Architectural Overview.........................................................................................................................................9
4.0
Memory Organization ........................................................................................................................................15
5.0
I/O Ports.............................................................................................................................................................25
6.0
Timer0 Module and TMR0 Register...................................................................................................................27
7.0
Special Features of the CPU .............................................................................................................................31
8.0
Instruction Set Summary ...................................................................................................................................43
9.0
Development Support ........................................................................................................................................55
10.0 Electrical Characteristics - PIC16C52................................................................................................................59
11.0 Electrical Characteristics - PIC16C54/55/56/57.................................................................................................67
12.0 DC and AC Characteristics - PIC16C54/55/56/57 .............................................................................................81
13.0 Electrical Characteristics - PIC16CR54A...........................................................................................................89
14.0 Electrical Characteristics - PIC16C54A ...........................................................................................................103
15.0 Electrical Characteristics - PIC16CR57B.........................................................................................................117
16.0 Electrical Characteristics - PIC16C58A ...........................................................................................................131
17.0 Electrical Characteristics - PIC16CR58A.........................................................................................................145
18.0 DC and AC Characteristics - PIC16C54A/CR57B/C58A/CR58A ....................................................................159
19.0 Electrical Characteristics PIC16C54B/C54C/CR54B/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ....................................171
20.0 DC and AC Characteristics PIC16C54B/C54C/CR54B/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ....................................183
21.0 Packaging Information .....................................................................................................................................195
Appendix A: Compatibility ...........................................................................................................................................207
Index .........................................................................................................................................................................209
On-Line Support ..........................................................................................................................................................211
PIC16C5X Product Identification System....................................................................................................................213
PIC16C54/55/56/57 Product Identification System .....................................................................................................214
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
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We appreciate your assistance in making this a better document.
DS30453B-page 4
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
1.0
GENERAL DESCRIPTION
1.1
The PIC16C5X from Microchip Technology is a family
of low-cost, high performance, 8-bit, fully static,
EPROM/ ROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single
word/single cycle instructions. All instructions are single cycle (200 ns) except for program branches which
take two cycles. The PIC16C5X delivers performance
an order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC16C5X products are equipped with special features that reduce system cost and power requirements.
The Power-On Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external reset circuitry.
There are four oscillator configurations to choose from,
including the power-saving LP (Low Power) oscillator
and cost saving RC oscillator. Power saving SLEEP
mode, Watchdog Timer and code protection features
improve system cost, power and reliability.
Applications
The PIC16C5X series fits perfectly in applications ranging from high-speed automotive and appliance motor
control to low-power remote transmitters/receivers,
pointing devices and telecom processors. The EPROM
technology makes customizing application programs
(transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small
footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high
performance, ease of use and I/O flexibility make the
PIC16C5X series very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic in larger
systems, coprocessor applications).
The UV erasable CERDIP packaged versions are ideal
for code development, while the cost-effective One
Time Programmable (OTP) versions are suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in OTP
microcontrollers while benefiting from the OTP’s
flexibility.
The PIC16C5X products are supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a ‘C’ compiler, fuzzy logic support
tools, a low-cost development programmer, and a full
featured programmer. All the tools are supported on
IBM PC and compatible machines.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 5
PIC16C5X
TABLE 1-1:
PIC16C5X FAMILY OF DEVICES
PIC16C52
Clock
Memory
Peripherals
Features
PIC16C54s
PIC16CR54s
PIC16C55s
PIC16C56s
Maximum Frequency
of Operation (MHz)
4
20
20
20
20
EPROM Program Memory
(x12 words)
384
512
—
512
1K
ROM Program Memory
(x12 words)
—
—
512
—
—
RAM Data Memory (bytes)
25
25
25
24
25
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
I/O Pins
12
12
12
20
12
Number of Instructions
33
33
33
33
33
Packages
18-pin DIP,
SOIC
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin DIP,
SOIC;
28-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code
protect and high I/O current capability.
PIC16CR56s
PIC16C57s
PIC16CR57s
PIC16C58s
PIC16CR58s
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
EPROM Program Memory
(x12 words)
—
2K
—
2K
—
Memory
ROM Program Memory
(x12 words)
1K
—
2K
—
2K
RAM Data Memory (bytes)
25
72
72
73
73
Peripherals
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
Clock
Features
I/O Pins
12
20
20
12
12
Number of Instructions
33
33
33
33
33
Packages
18-pin DIP,
SOIC;
20-pin SSOP
28-pin DIP,
SOIC;
28-pin SSOP
28-pin DIP,
SOIC;
28-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code
protect and high I/O current capability.
DS30453B-page 6
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
2.0
PIC16C5X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and
production requirements, the proper device option can
be selected using the information in this section. When
placing orders, please use the PIC16C5X Product
Identification System at the back of this data sheet to
specify the correct part number.
For the PIC16C5X family of devices, there are four
device types, as indicated in the device number:
1.
2.
3.
4.
5.
2.1
C, as in PIC16C54. These devices have
EPROM program memory and operate over the
standard voltage range.
LC, as in PIC16LC54A. These devices have
EPROM program memory and operate over an
extended voltage range.
LV, as in PIC16LV54A. These devices have
EPROM program memory and operate over a
2.0V to 3.8V range.
CR, as in PIC16CR54A. These devices have
ROM program memory and operate over the
standard voltage range.
LCR, as in PIC16LCR54B. These devices have
ROM program memory and operate over an
extended voltage range.
UV Erasable Devices (EPROM)
The UV erasable versions, offered in CERDIP
packages, are optimal for prototype development and
pilot programs
UV erasable devices can be programmed for any of
the four oscillator configurations. Microchip's
PICSTART and PRO MATE programmers both
support programming of the PIC16C5X. Third party
programmers also are available; refer to the Third
Party Guide for a list of sources.
2.2
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and
configuration bit options already programmed by the
factory. Certain code and prototype verification
procedures apply before production shipments are
available. Please contact your Microchip Technology
sales office for more details.
2.4
Serialized
Quick-Turnaround-Production
(SQTP SM) Devices
Microchip offers the unique programming service
where a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential. The devices are identical to the OTP
devices but with all EPROM locations and
configuration bit options already programmed by the
factory.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, giving the customer a low
cost option for high volume, mature products.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages,
permit the user to program them once. In addition to
the program memory, the configuration bits must be
programmed.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 7
PIC16C5X
NOTES:
DS30453B-page 8
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C5X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C5X uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (200ns @ 20MHz)
except for program branches.
The PIC16C52 addresses 384 x 12 of program
memory, the PIC16C54s/CR54s and PIC16C55s
address 512 x 12 of program memory, the
PIC16C56s/CR56s address 1K X 12 of program
memory,
and
the
PIC16C57s/CR57s
and
PIC16C58s/CR58s address 2K x 12 of program
memory. All program memory is internal.
The PIC16C5X device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand
is either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
The PIC16C5X can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C5X has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC16C5X simple yet efficient.
In addition, the learning curve is reduced significantly.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 9
PIC16C5X
FIGURE 3-1:
PIC16C5X SERIES BLOCK DIAGRAM
9-11
9-11
EPROM/ROM
384 X 12 TO
2048 X 12
T0CKI
PIN
STACK 1
STACK 2
CONFIGURATION WORD
“DISABLE”
PC
WATCHDOG
TIMER
12
“CODE
PROTECT”
2
OSCILLATOR/
TIMING &
CONTROL
INSTRUCTION
REGISTER
WDT TIME
OUT
9
12
OSC1 OSC2 MCLR
“OSC
SELECT”
CLKOUT
WDT/TMR0
PRESCALER
8
“SLEEP”
INSTRUCTION
DECODER
6
“OPTION”
OPTION REG.
DIRECT ADDRESS
DIRECT RAM
ADDRESS
FROM W
5
5-7
LITERALS
8
STATUS
TMR0
GENERAL
PURPOSE
REGISTER
FILE
(SRAM)
24, 25, 72 or
73 Bytes
FSR
8
W
DATA BUS
ALU
8
FROM W
4
4
“TRIS 5”
8
“TRIS 6”
TRISA
PORTA
4
RA3:RA0
DS30453B-page 10
FROM W
Preliminary
TRISB
FROM W
8
PORTB
8
RB7:RB0
8
“TRIS 7”
TRISC
8
PORTC
8
RC7:RC0
(28-Pin
Devices Only)
1998 Microchip Technology Inc.
PIC16C5X
TABLE 3-1:
Name
PINOUT DESCRIPTION - PIC16C52, PIC16C54s, PIC16CR54s, PIC16C56s,
PIC16CR56s, PIC16C58s, PIC16CR58s
DIP, SOIC SSOP I/O/P Input
No.
No. Type Levels
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
T0CKI
17
18
1
2
6
7
8
9
10
11
12
13
3
19
20
1
2
7
8
9
10
11
12
13
14
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
MCLR/VPP
4
4
I
ST
OSC1/CLKIN
OSC2/CLKOUT
16
15
18
17
I
O
ST
—
VDD
14
15,16
P
—
VSS
5
5,6
P
—
Legend: I = input, O = output, I/O = input/output,
P = power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input
1998 Microchip Technology Inc.
Description
Bi-directional I/O port
Bi-directional I/O port
Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
Master clear (reset) input/programming voltage input. This
pin is an active low reset to the device. Voltage on the
MCLR/VPP pin must not exceed VDD to avoid unintended
entering of programming mode.
Oscillator crystal input/external clock source input.
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Preliminary
DS30453B-page 11
PIC16C5X
TABLE 3-2:
Name
PINOUT DESCRIPTION
- PIC16C55s, PIC16C57s, PIC16CR57s
DIP, SOIC SSOP I/O/P Input
No.
No. Type Levels
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
T0CKI
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
MCLR
28
28
I
ST
OSC1/CLKIN
OSC2/CLKOUT
27
26
27
26
I
O
ST
—
VDD
2
3,4
P
—
VSS
4
1,14
P
—
N/C
3,5
—
—
—
Legend: I = input, O = output, I/O = input/output,
P = power, — = Not Used,
TTL = TTL input, ST = Schmitt Trigger input
DS30453B-page 12
Description
Bi-directional I/O port
Bi-directional I/O port
Bi-directional I/O port
Clock input to Timer0. Must be tied to VSS or VDD if not in use
to reduce current consumption.
Master clear (reset) input. This pin is an active low reset to the
device.
Oscillator crystal input/external clock source input.
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Unused, do not connect
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
Clocking Scheme/Instruction Cycle
3.1
3.2
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55H
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 13
PIC16C5X
NOTES:
DS30453B-page 14
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
4.0
MEMORY ORGANIZATION
FIGURE 4-2:
PIC16C5X memory is organized into program memory
and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one or
two STATUS register bits. For devices with a data
memory register file of more than 32 registers, a
banking scheme is used. Data memory banks are
accessed using the File Selection Register (FSR).
PIC16C54s/CR54s/C55s
PROGRAM MEMORY MAP
AND STACK
PC
9
CALL, RETLW
Stack Level 1
Stack Level 2
000h
The PIC16C52 has a 9-bit Program Counter (PC)
capable of addressing a 384 x 12 program memory
space (Figure 4-1). The PIC16C54s, PIC16CR54s and
PIC16C55s have a 9-bit Program Counter (PC)
capable of addressing a 512 x 12 program memory
space (Figure 4-2). The PIC16C56s and PIC16CR56s
have a 10-bit Program Counter (PC) capable of
addressing a 1K x 12 program memor y space
(Figure 4-3). The PIC16CR57s, PIC16C58s and
PIC16CR58s have an 11-bit Program Counter capable
of addressing a 2K x 12 program memory space
(Figure 4-4). Accessing a location above the physically
implemented address will cause a wraparound.
User Memory
Space
Program Memory Organization
FIGURE 4-3:
The reset vector for the PIC16C52 is at 17Fh. A NOP
at the reset vector location will cause a restart at
location 000h. The reset vector for the PIC16C54s,
PIC16CR54s and PIC16C55s is at 1FFh. The reset
vector for the PIC16C56s and PIC16CR56s is at
3 F F h . T h e r e s e t ve c t o r fo r t h e P I C 1 6 C 5 7 s ,
PIC16CR57s, PIC16C58s, and PIC16CR58s is at
7FFh.
FIGURE 4-1:
PIC16C52 PROGRAM
MEMORY MAP AND STACK
PC
On-chip
Program
Memory
0FFh
100h
Reset Vector
1FFh
PIC16C56s/CR56s
PROGRAM MEMORY MAP
AND STACK
PC
10
CALL, RETLW
Stack Level 1
Stack Level 2
000h
User Memory
Space
4.1
On-chip Program
Memory (Page 0)
0FFh
100h
1FFh
200h
On-chip Program
Memory (Page 1)
2FFh
300h
Reset Vector
3FFh
9
CALL, RETLW
Stack Level 1
Stack Level 2
User Memory
Space
000h
On-chip Program
Memory
Reset Vector
1998 Microchip Technology Inc.
17Fh
Preliminary
DS30453B-page 15
PIC16C5X
FIGURE 4-4:
PIC16C57s/CR57s/C58s/
CR58s PROGRAM MEMORY
MAP AND STACK
PC
11
CALL, RETLW
Stack Level 1
Stack Level 2
000h
On-chip Program
Memory (Page 0)
0FFh
100h
User Memory
Space
1FFh
200h
On-chip Program
Memory (Page 1)
2FFh
300h
3FFh
400h
On-chip Program
Memory (Page 2)
4FFh
500h
5FFh
600h
DS30453B-page 16
On-chip Program
Memory (Page 3)
6FFh
700h
Reset Vector
7FFh
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
4.2
Data Memory Organization
FIGURE 4-5:
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.
PIC16C52, PIC16C54s,
PIC16CR54s, PIC16C55s,
PIC16C56s, PIC16CR56s
REGISTER FILE MAP
File Address
The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
The general purpose registers are used for data and
control information under command of the instructions.
05h
PORTA
06h
PORTB
For the PIC16C52, PIC16C54s, PIC16CR54s,
PIC16C56s and PIC16CR56s, the register file is
composed of 7 special function registers and 25
general purpose registers (Figure 4-5).
07h
PORTC(2)
0Fh
10h
General
Purpose
Registers
For the PIC16C55s, the register file is composed of 8
special function registers and 24 general purpose
registers.
For the PIC16C57s and PIC16CR57s, the register file
is composed of 8 special function registers, 24 general
purpose registers and up to 48 additional general
purpose registers that may be addressed using a
banking scheme (Figure 4-6).
1Fh
Note 1:
2:
Not a physical register. See Section 4.7
PIC16C55s only, others are a general
purpose register.
For the PIC16C58s and PIC16CR58s, the register file
is composed of 7 special function registers, 25 general
purpose registers and up to 48 additional general
purpose registers that may be addressed using a
banking scheme (Figure 4-7).
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly or indirectly
through the file select register FSR (Section 4.7).
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 17
PIC16C5X
FIGURE 4-6:
PIC16C57s/CR57s REGISTER FILE MAP
FSR
00
01
10
11
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
07h
08h
Addresses map back to
addresses in Bank 0.
PORTC
General
Purpose
Registers
0Fh
10h
2Fh
4Fh
6Fh
30h
50h
70h
General
Purpose
Registers
1Fh
General
Purpose
Registers
General
Purpose
Registers
Bank 1
Note 1:
General
Purpose
Registers
7Fh
5Fh
3Fh
Bank 0
FIGURE 4-7:
60h
40h
20h
Bank 2
Bank 3
Not a physical register. See Section 4.7
PIC16C58s/CR58s REGISTER FILE MAP
FSR
00
01
10
11
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
40h
20h
60h
Addresses map back to
addresses in Bank 0.
07h
General
Purpose
Registers
2Fh
0Fh
General
Purpose
Registers
General
Purpose
Registers
3Fh
1Fh
Bank 0
DS30453B-page 18
70h
General
Purpose
Registers
General
Purpose
Registers
7Fh
5Fh
Bank 1
Note 1:
6Fh
4Fh
50h
30h
10h
Bank 2
Bank 3
Not a physical register. See Section 4.7
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions to control the
operation of the device (Table 4-1).
TABLE 4-1:
Address
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
N/A
TRIS
I/O control registers (TRISA, TRISB, TRISC)
1111 1111
1111 1111
N/A
OPTION
Contains control bits to configure Timer0 and Timer0/WDT prescaler
--11 1111
--11 1111
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
uuuu uuuu
01h
TMR0
8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
Low order 8 bits of PC
(1)
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
—
—
—
06h
PORTB
RB7
RB6
PORTC
RC7
RC6
(2)
07h
PA2
PA1
PA0
TO
1111 1111
1111 1111
0001 1xxx
000q quuu
1xxx xxxx
1uuu uuuu
---- xxxx
---- uuuu
RB0
xxxx xxxx
uuuu uuuu
RC0
xxxx xxxx
uuuu uuuu
PD
Z
DC
C
—
RA3
RA2
RA1
RA0
RB5
RB4
RB3
RB2
RB1
RC5
RC4
RC3
RC2
RC1
Indirect data memory address pointer
Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)
x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5
for an explanation of how to access these bits.
2: File address 07h is a general purpose register on the PIC16C52, PIC16C54s, PIC16CR54s, PIC16C56s, PIC16CR56s,
PIC16C58s and PIC16CR58s.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 19
PIC16C5X
4.3
STATUS Register
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bits for
program memories larger than 512 words.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
FIGURE 4-8:
R/W-0
PA2
bit7
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Section 8.0, Instruction Set Summary.
STATUS REGISTER (ADDRESS:03h)
R/W-0
PA1
6
R/W-0
PA0
5
R-1
TO
4
R-1
PD
3
R/W-x
Z
2
R/W-x
DC
1
R/W-x
C
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
PA2: This bit unused at this time.
Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.
bit 6-5:
PA1:PA0: Program page preselect bits (PIC16C56s/CR56s)(PIC16C57s/CR57s)(PIC16C58s/CR58s)
00 = Page 0 (000h - 1FFh) - PIC16C56s/CR56s, PIC16C57s/CR57s, PIC16C58s/CR58s
01 = Page 1 (200h - 3FFh) - PIC16C56s/CR56s, PIC16C57s/CR57s, PIC16C58s/CR58s
10 = Page 2 (400h - 5FFh) - PIC16C57s/CR57s, PIC16C58s/CR58s
11 = Page 3 (600h - 7FFh) - PIC16C57s/CR57s, PIC16C58s/CR58s
Each page is 512 words.
Using the PA1:PA0 bits as general purpose read/write bits in devices which do not use them for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF
SUBWF
1 = A carry occurred
1 = A borrow did not occur
0 = A carry did not occur
0 = A borrow occurred
DS30453B-page 20
Preliminary
RRF or RLF
Load bit with LSb or MSb, respectively
1998 Microchip Technology Inc.
PIC16C5X
4.4
OPTION Register
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION bits.
The OPTION register is a 6-bit wide, write-only
register which contains var ious control bits to
configure the Timer0/WDT prescaler and Timer0.
FIGURE 4-9:
U-0
—
bit7
OPTION REGISTER
U-0
—
W-1
T0CS
W-1
T0SE
W-1
PSA
W-1
PS2
W-1
PS1
6
5
4
3
2
1
bit 7-6:
Unimplemented.
bit 5:
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: Timer0 source edge select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3:
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT (not implemented on PIC16C52)
0 = Prescaler assigned to Timer0
bit 2-0:
PS2:PS0: Prescaler rate select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1998 Microchip Technology Inc.
W-1
PS0
bit0
W = Writable bit
U = Unimplemented bit
- n = Value at POR reset
WDT Rate (not implemented on PIC16C52)
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
DS30453B-page 21
PIC16C5X
4.5
Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
FIGURE 4-10: LOADING OF PC
BRANCH INSTRUCTIONS PIC16C52, PIC16C54s,
PIC16CR54s, PIC16C55s
GOTO Instruction
8
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC (Figure 4-10 and Figure 4-11).
For the PIC16C56s, PIC16CR56s, PIC16C57s,
PIC16CR57s, PIC16C58s and PIC16CR58s, a page
number must be supplied as well. Bit5 and bit6 of the
STATUS register provide page information to bit9 and
bit10 of the PC (Figure 4-11 and Figure 4-12).
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC
does not come from the instruction word, but is always
cleared (Figure 4-10 and Figure 4-11).
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5.
For the PIC16C56s, PIC16CR56s, PIC16C57s,
PIC16CR57s, PIC16C58s and PIC16CR58s, a page
number again must be supplied. Bit5 and bit6 of the
STATUS register provide page information to bit9 and
bit10 of the PC (Figure 4-11 and Figure 4-12).
Note:
7
0
PCL
PC
Instruction Word
CALL or Modify PCL Instruction
8
7
0
PCL
PC
Instruction Word
Reset to '0'
FIGURE 4-11: LOADING OF PC
BRANCH INSTRUCTIONS PIC16C56s/PIC16CR56s
GOTO Instruction
10
9
8 7
0
PC
PCL
Instruction Word
Because PC is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any program memory page (512 words long).
2
PA1:PA0
7
0
STATUS
CALL or Modify PCL Instruction
10
9
8 7
0
PC
PCL
Instruction Word
2
Reset to ‘0’
PA1:PA0
7
0
STATUS
DS30453B-page 22
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
FIGURE 4-12: LOADING OF PC
BRANCH INSTRUCTIONS PIC16C57s/PIC16CR57s, AND
PIC16C58s/PIC16CR58s
GOTO Instruction
10
9
8 7
0
PC
PCL
Instruction Word
2
PA1:PA0
7
0
8 7
0
PC
PCL
Instruction Word
2
Reset to ‘0’
PA1:PA0
7
If the Program Counter is pointing to the last address
of a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS
register will not be updated. Therefore, the next GOTO,
CALL, or Modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0
or PA1:PA0).
To prevent this, the page preselect bits must be
updated under program control.
CALL or Modify PCL Instruction
9
PAGING CONSIDERATIONS –
PIC16C56s/CR56s, PIC16C57s/CR57s AND
PIC16C58s/CR58s
For example, a NOP at location 1FFh (page 0)
increments the PC to 200h (page 1). A GOTO xxx at
200h will return the program to address 0xxh on page
0 (assuming that PA1:PA0 are clear).
STATUS
10
4.5.1
0
STATUS
4.5.2
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the reset vector.
The STATUS register page preselect bits are cleared
u p o n a R E S E T, w h i c h m e a n s t h a t p a g e 0 i s
pre-selected.
Therefore, upon a RESET, a GOTO instruction at the
reset vector location will automatically cause the
program to jump to page 0.
4.6
Stack
PIC16C5X devices have a 9-bit, 10-bit or 11-bit wide,
two-level hardware push/pop stack (Figure 4-2,
Figure 4-1, and Figure 4-3 respectively).
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
For the RETLW instruction, the PC is loaded with the
Top Of Stack (TOS) contents. All of the devices
covered in this data sheet have a two-level stack. The
stack has the same bit width as the device PC.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 23
PIC16C5X
4.7
Indirect Data Addressing; INDF and
FSR Registers
EXAMPLE 4-2:
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 4-1:
movlw
movwf
clrf
incf
btfsc
goto
NEXT
INDIRECT ADDRESSING
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 06h)
• A read of the INDR register now will return the
value of 0Ah.
:
;YES, continue
The FSR is either a 5-bit (PIC16C52, PIC16C54s,
PIC16CR54s, PIC16C55s), 6-bit (PIC16C56s,
PIC16CR56s), or 7-bit (PIC16C57s, PIC16CR57s,
PIC16C58s, PIC16CR58s) wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
The FSR bits are used to select data memory
addresses 00h to 1Fh.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
PIC16C52, PIC16C54s, PIC16CR54s, PIC16C55s:
These do not use banking. FSR are
unimplemented and read as '1's.
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
PIC16C57s,
PIC16CR57s,
PIC16C58s,
PIC16CR58s: FSR are the bank select bits and
are used to select the bank to be addressed (00 =
bank 0, 01 = bank 1, 10 = bank 2, 11 = bank 3).
FIGURE 4-13: DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
6 5
4
bank select
location select
Indirect Addressing
(opcode)
0
6
5
4
bank
00
01
10
(FSR)
0
location select
11
00h
Addresses map back
to addresses in Bank 0.
Data
Memory(1)
0Fh
10h
1Fh
Bank 0
3Fh
5Fh
Bank 1
7Fh
Bank 2
Bank 3
Note 1: For register map detail see Section 4.2.
DS30453B-page 24
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
5.0
I/O PORTS
5.5
As with any other register, the I/O registers can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB, TRISC) are all set.
5.1
PORTA
PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (RA3:RA0). Bits 7-4 are unimplemented and
read as '0's.
5.2
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All ports may be used for both input and
output operation. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit (in TRISA,
TRISB) must be cleared (= 0). For use as an input, the
corresponding TRIS bit must be set. Any I/O pin can
be programmed individually as input or output.
FIGURE 5-1:
Data
Bus
D
PORTC
WR
Port
PORTC is an 8-bit I/O register for PIC16C55s,
PIC16C57s and PIC16CR57s.
PORTC is a general purpose register for PIC16C52,
PIC16C54s, PIC16CR54s, PIC16C56s, PIC16C58s
and PIC16CR58s.
5.4
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
PORTB
PORTB is an 8-bit I/O register (PORTB).
5.3
I/O Interfacing
W
Reg
CK
VDD
Q
P
N
D
TRIS ‘f’
The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer.
I/O
pin(1)
Q
TRIS
Latch
TRIS Registers
Note:
Q
Data
Latch
CK
VSS
Q
Reset
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
TABLE 5-1:
Address
SUMMARY OF PORT REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
1111 1111
1111 1111
RA3
RA2
RA1
RA0
---- xxxx
---- uuuu
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
Bit 4
N/A
TRIS
05h
PORTA
—
—
—
—
06h
PORTB
RB7
RB6
RB5
07h
PORTC
RC7
RC6
RC5
Bit 3
I/O control registers (TRISA, TRISB, TRISC)
Value on
MCLR and
WDT Reset
Legend: Shaded boxes = unimplemented, read as ‘0’,
– = unimplemented, read as '0', x = unknown, u = unchanged
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 25
PIC16C5X
5.6
I/O Programming Considerations
5.6.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1:
;Initial PORT Settings
; PORTB Inputs
; PORTB Outputs
;PORTB have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- ---------BCF
PORTB, 7
;01pp pppp
11pp pppp
BCF
PORTB, 6
;10pp pppp
11pp pppp
MOVLW 03Fh
;
TRIS PORTB
;10pp pppp
10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a
bi-directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
5.6.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
Example 5-1 shows the effect of two sequential
read-modify-write instructions (e.g., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 5-2:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
MOVWF PORTB
PC + 1
MOVF PORTB,W
PC + 2
PC + 3
NOP
NOP
This example shows a write
to PORTB followed by a read
from PORTB.
RB7:RB0
Port pin
written here
Instruction
executed
DS30453B-page 26
MOVWF PORTB
(Write to
PORTB)
Port pin
sampled here
MOVF PORTB,W
(Read
PORTB)
Preliminary
NOP
1998 Microchip Technology Inc.
PIC16C5X
6.0
TIMER0 MODULE AND
TMR0 REGISTER
Counter mode is selected by setting the T0CS bit
(OPTION). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.1.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module, while Figure 6-2 shows the electrical structure
of the Timer0 input.
Timer mode is selected by clearing the T0CS bit
(OPTION). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-3 and Figure 6-4).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1:
A summary of registers associated with the Timer0
module is found in Table 6-1.
TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
PSout
1
1
T0CKI
pin
Programmable
Prescaler(2)
T0SE(1)
0
8
Sync with
Internal
Clocks
TMR0 reg
PSout
(2 cycle delay) Sync
3
T0CS(1)
PSA(1)
PS2, PS1, PS0(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6).
FIGURE 6-2:
ELECTRICAL STRUCTURE OF T0CKI PIN
RIN
T0CKI
pin
(1)
VSS
N
(1)
Schmitt Trigger
Input Buffer
VSS
Note 1: ESD protection circuits
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 27
PIC16C5X
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
T0
Timer0
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0+1
Instruction
Executed
FIGURE 6-4:
PC+3
MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
PC+5
MOVF TMR0,W
NT0
NT0+1
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+2
Read TMR0
reads NT0 + 2
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
Instruction
Execute
PC+3
MOVF TMR0,W
PC+4
PC+5
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
TABLE 6-1:
PC+2
MOVF TMR0,W
T0+1
T0
Timer0
Address
PC+2
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
REGISTERS ASSOCIATED WITH TIMER0
Name
01h
TMR0
N/A
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PS2
PS1
PS0
Timer0 - 8-bit real-time clock/counter
—
—
T0CS
T0SE
PSA
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
Legend: Shaded cells: Unimplemented bits,
- = unimplemented, x = unknown, u = unchanged,
DS30453B-page 28
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
6.1
Using Timer0 with an External Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 6-5:
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 29
PIC16C5X
6.2
Prescaler
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT) (WDT postscaler not implemented on
PIC16C52), respectively (Section 6.1.2). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
EXAMPLE 6-1:
1.CLRWDT
;Clear WDT
2.CLRF
TMR0
;Clear TMR0 & Prescaler
3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)
4.OPTION
; are required only if
; desired
5.CLRWDT
;PS are 000 or 001
6.MOVLW '00xx1xxx’b ;Set Postscaler to
7.OPTION
; desired WDT rate
The PSA and PS2:PS0 bits (OPTION) determine
prescaler assignment and prescale ratio.
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before switching
the prescaler.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a RESET, the prescaler contains all
'0's.
6.2.1
CHANGING PRESCALER
(TIMER0→WDT)
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
MOVLW
'xxxx0xxx'
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
FIGURE 6-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
0
T0CKI
pin
1
8
M
U
X
1
M
U
X
0
Sync
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
WDT not implemented on PIC16C52.
DS30453B-page 30
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
7.0
SPECIAL FEATURES OF THE
CPU
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake up from
SLEEP through external reset or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
What sets a microcontroller apart from other
processors are special circuits that deal with the
needs of real-time applications. The PIC16C5X family
of microcontrollers has a host of such features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code
protection. These features are:
7.1
Configuration Bits
Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type and one bit is the
Watchdog Timer enable bit. Nine bits are code
protection bits (Figure 7-1 and Figure 7-2) for the
PIC16C54, PIC16CR54, PIC16C56, PIC16CR56,
PIC16C58, and PIC16CR58 devices.
•
•
•
•
•
Oscillator selection
Reset
Power-On Reset (POR)
Device Reset Timer (DRT)
Watchdog Timer (WDT)
(not implemented on PIC16C52)
• SLEEP
• Code protection
• ID locations (not implemented on PIC16C52)
QTP or ROM devices have the oscillator configuration
programmed at the factory and these parts are tested
accordingly (see "Product Identification System"
diagrams in the back of this data sheet).
The PIC16C5X Family has a Watchdog Timer which
can be shut off only through configuration bit WDTE. It
runs off of its own RC oscillator for added reliability.
There is an 18 ms delay provided by the Device Reset
Timer (DRT), intended to keep the chip in reset until
the crystal oscillator is stable. With this timer on-chip,
most applications need no external reset circuitry.
FIGURE 7-1:
CONFIGURATION WORD FOR
PIC16CR54A/C54B/CR54B/C54C/CR54C/C55A/C56A/CR56A/C57C/
CR57B/CR57C/C58B/CR58A/CR58B
CP
CP
CP
CP
CP
CP
CP
CP
CP
bit11
10
9
8
7
6
5
4
3
WDTE FOSC1 FOSC0
2
1
bit0
Register:
Address(1):
CONFIG
FFFh
bit 11-3: CP: Code protection bits
1 = Code protection off
0 = Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to access the configuration word.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 31
PIC16C5X
FIGURE 7-2:
CONFIGURATION WORD FOR PIC16C52/C54/C54A/C55/C56/C57/C58A
—
—
—
—
—
—
—
—
CP
bit11
10
9
8
7
6
5
4
3
WDTE FOSC1 FOSC0
2
1
bit0
Register:
Address(1):
CONFIG
FFFh
bit 11-4: Unimplemented: Read as ’0’
bit 3:
CP: Code protection bit.
1 = Code protection off
0 = Code protection on
bit 2:
WDTE: Watchdog timer enable bit (not implemented on PIC16C52)
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator selection bits(2)
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the configuration word.
2: PIC16C52 supports XT and RC oscillator only.
PIC16LV54A supports XT, RC and LP oscillator only.
PIC16LV58A supports XT, RC and LP oscillator only.
DS30453B-page 32
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
7.2
Oscillator Configurations
7.2.1
OSCILLATOR TYPES
FIGURE 7-4:
PIC16C5Xs can be operated in four different oscillator
modes. The user can program two configuration bits
(FOSC1:FOSC0) to select one of these four modes:
•
•
•
•
LP:
XT:
HS:
RC:
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
Note:
Not all oscillator selections available for all
parts. See Section 7.1.
7.2.2
TABLE 7-1:
Osc
Type
XT
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 7-3). The
PIC16C5X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in XT, LP or HS modes, the
device can have an external clock source drive the
OSC1/CLKIN pin (Figure 7-4).
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
C1(1)
OSC1
PIC16C5X
SLEEP
XTAL
RS(2)
RF(3)
OSC2
HS
Note:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC16C5X, PIC16CR5X
Resonator
Freq
Cap. Range
C1
Cap. Range
C2
455 kHz
22-100 pF
22-100 pF
2.0 MHz
15-68 pF
15-68 pF
4.0 MHz
15-68 pF
15-68 pF
4.0 MHz
15-68 pF
15-68 pF
8.0 MHz
10-68 pF
10-68 pF
16.0 MHz
10-22 pF
10-22 pF
These values are for design guidance only.
Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values
of external components.
TABLE 7-2:
Osc
Type
OSC2
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC16C5X, PIC16CR5X
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
32 kHz(1)
15 pF
15 pF
100 kHz
15-30 pF
30-47 pF
200 kHz
15-30 pF
15-82 pF
200-300 pF
15-30 pF
XT
100 kHz
100-200 pF
15-30 pF
200 kHz
15-100 pF
15-30 pF
455 kHz
15-30 pF
15-30 pF
1 MHz
15-30 pF
15-30 pF
2 MHz
15-47 pF
15-47 pF
4 MHz
HS
4 MHz
15-30 pF
15-30 pF
8 MHz
15-30 pF
15-30 pF
20 MHz
15-30 pF
15-30 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
2: These values are for design guidance only.
Rs may be required in HS mode as well as
XT mode to avoid overdriving crystals with
low drive level specification. Since each
crystal has its own characteristics, the user
should consult the crystal manufacturer for
appropriate values of external components.
LP
To internal
logic
C2(1)
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen (approx.
value = 10 MΩ).
Note:
1998 Microchip Technology Inc.
OSC1
PIC16C5X
Clock from
ext. system
Open
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
FIGURE 7-3:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Preliminary
If you change from this device to
another device, please verify oscillator
characteristics in your application.
DS30453B-page 33
PIC16C5X
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
FIGURE 7-6:
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 7-5 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 7-5:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
(USING XT, HS OR LP
OSCILLATOR MODE)
+5V
To Other
Devices
10k
74AS04
4.7k
74AS04
PIC16C5X
OSC1
OSC2
100k
10k
20 pF
Note:
20 pF
If you change from this device to
another device, please verify oscillator
characteristics in your application.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
DS30453B-page 34
330
To Other
Devices
330
74AS04
74AS04
74AS04
PIC16C5X
OSC1
0.1 µF
OSC2
XTAL
100k
Note:
7.2.4
If you change from this device to
another device, please verify oscillator
characteristics in your application.
RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Figure 7-7 shows how the R/C combination is
connected to the PIC16C5X. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
10k
XTAL
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
(USING XT, HS OR LP
OSCILLATOR MODE)
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation.
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic.
FIGURE 7-7:
RC OSCILLATOR MODE
VDD
Rext
OSC1
N
Cext
Internal
clock
PIC16C5X
Fosc/4
OSC2/CLKOUT
If you change from this device to
another device, please verify oscillator
characteristics in your application.
1998 Microchip Technology Inc.
Reset
PIC16C5X devices may be reset in one of the
following ways:
•
•
•
•
•
Power-On Reset (POR)
MCLR reset (normal operation)
MCLR wake-up reset (from SLEEP)
WDT reset (normal operation)
WDT wake-up reset (from SLEEP)
Table 7-3 shows these reset conditions for the PCL
and STATUS registers.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in
any other reset. Most other registers are reset to a
“reset state” on Power-On Reset (POR), MCLR or
WDT reset. A MCLR or WDT wake-up from SLEEP
also results in a device reset, and not a continuation of
operation before SLEEP.
The TO and PD bits (STATUS ) are set or
cleared depending on the different reset conditions
(Section 7.7). These bits may be used to determine
the nature of the reset.
VSS
Note:
7.3
Table 7-4 lists a full description of reset states of all
registers. Figure 7-8 shows a simplified block diagram
of the on-chip reset circuit.
Preliminary
DS30453B-page 35
PIC16C5X
TABLE 7-3:
RESET CONDITIONS FOR SPECIAL REGISTERS
PCL
Addr: 02h
STATUS
Addr: 03h
Power-On Reset
1111 1111
0001 1xxx
MCLR reset (normal operation)
1111 1111
000u uuuu(1)
MCLR wake-up (from SLEEP)
1111 1111
0001 0uuu
WDT reset (normal operation)
1111 1111
0000 uuuu(2)
Condition
WDT wake-up (from SLEEP)
1111 1111
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.
2: The CLRWDT instruction will set the TO and PD bits.
TABLE 7-4:
0000 0uuu
RESET CONDITIONS FOR ALL REGISTERS
Register
Address
Power-On Reset
MCLR or WDT Reset
W
N/A
xxxx xxxx
uuuu uuuu
TRIS
N/A
1111 1111
1111 1111
OPTION
N/A
--11 1111
--11 1111
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL(1)
02h
1111 1111
1111 1111
STATUS(1)
03h
0001 1xxx
000q quuu
FSR
04h
1xxx xxxx
1uuu uuuu
PORTA
05h
---- xxxx
---- uuuu
PORTB
06h
xxxx xxxx
uuuu uuuu
PORTC(2)
07h
xxxx xxxx
uuuu uuuu
General Purpose Register Files
07-7Fh
xxxx xxxx
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented, read as '0',
q = see tables in Section 7.7 for possible values.
Note 1: See Table 7-3 for reset value for specific conditions.
2: General purpose register file on PIC16C52/C54s/CR54s/C56s/CR56s/C58s/CR58s
FIGURE 7-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
MCLR/VPP pin
WDT Time-out
RESET
WDT
On-Chip
RC OSC
8-bit Asynch
Ripple Counter
(Start-Up Timer)
S
Q
R
Q
CHIP RESET
DS30453B-page 36
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
7.4
Power-On Reset (POR)
FIGURE 7-9:
The PIC16C5X family incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature,
the user merely ties the MCLR/VPP pin to VDD. A
simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-8.
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the
on-chip reset signal.
A power-up example where MCLR is not tied to VDD is
shown in Figure 7-10. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
In Figure 7-11, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together). The
VDD is stable before the start-up timer times out and
there is no problem in getting a proper reset. However,
Figure 7-12 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses a high on the MCLR/VPP pin, and when the
MCLR/VPP pin (and VDD) actually reach their full value,
is too long. In this situation, when the start-up timer
times out, VDD has not reached the VDD (min) value
and the chip is, therefore, not guaranteed to function
correctly. For such situations, we recommend that
external RC circuits be used to achieve longer POR
delay times (Figure 7-9).
Note:
VDD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
VDD
D
R
R1
MCLR
C
PIC16C5X
• External Power-On Reset circuit is required
only if VDD power-up is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
• R < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device electrical specification.
• R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
When the device starts normal operation
(exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
For more information on PIC16C5X POR, see
Power-Up Considerations - AN522 in the Embedded
Control Handbook.
The POR circuit does not produce an internal reset
when VDD declines.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 37
PIC16C5X
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min
DS30453B-page 38
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
7.5
Device Reset Timer (DRT)
7.6
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
VDD to rise above VDD min., and for the oscillator to
stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after the voltage on the MCLR/VPP pin has
reached a logic high (VIH) level. Thus, external RC
networks connected to the MCLR input are not
required in most cases, allowing for savings in
cost-sensitive and/or space restricted applications.
The Device Reset time delay will vary from device to
device due to VDD, temperature, and process
variation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications
using the WDT to wake the PIC16C5X from SLEEP
mode automatically.
Watchdog Timer (WDT) (not
implemented on PIC16C52)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins have been stopped, for
example, by execution of a SLEEP instruction. During
normal operation or SLEEP, a WDT reset or wake-up
reset generates a device RESET.
The TO bit (STATUS) will be cleared upon a
Watchdog Timer reset.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a '0'
(Section 7.1). Refer to the PIC16C5X Programming
Specifications (Literature Number DS30190) to
determine how to access the configuration word.
7.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, time-out a
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and
part-to-part process variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 39
PIC16C5X
FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0
M
1
Watchdog
Postscaler
Postscaler
U
X
Timer
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
EPROM Bit
To TMR0
1
0
MUX
PSA
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 7-5:
Address
N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
—
—
T0CS
T0SE
PSA
PS2
PS1
PS0
--11 1111
Value on
MCLR and
WDT Reset
--11 1111
Legend: Shaded boxes = Not used by Watchdog Timer,
– = unimplemented, read as '0', u = unchanged
DS30453B-page 40
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
7.7
Time-Out Sequence and Power Down
Status Bits (TO/PD)
The TO and PD bits in the STATUS register can be
tested to determine if a RESET condition has been
caused by a power-up condition, a MCLR or Watchdog
Timer (WDT) reset, or a MCLR or WDT wake-up reset.
TABLE 7-6:
TO/PD STATUS AFTER
RESET
7.8
Reset on Brown-Out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
To reset PIC16C5X devices when a brown-out occurs,
external brown-out protection circuits may be built, as
shown in Figure 7-14 and Figure 7-15.
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 1
TO
PD
RESET was caused by
1
1
Power-up (POR)
u
u
1
0
0
1
0
0
MCLR reset (normal operation)(1)
MCLR wake-up reset (from SLEEP)
WDT reset (normal operation)
WDT wake-up reset (from SLEEP)
VDD
VDD
33k
Legend: u = unchanged
Note 1: The TO and PD bits maintain their status (u) until
a reset occurs. A low-pulse on the MCLR input
does not change the TO and PD status bits.
10k
Q1
MCLR
40k
PIC16C5X
These STATUS bits are only affected by events listed
in Table 7-7.
TABLE 7-7:
EVENTS AFFECTING TO/PD
STATUS BITS
Event
Power-up
WDT Time-out
SLEEP instruction
CLRWDT instruction
TO
PD
1
1
0
u
1
0
1
1
This circuit will activate reset when VDD goes below Vz +
0.7V (where Vz = Zener voltage).
Remarks
No effect on PD
FIGURE 7-15: BROWN-OUT PROTECTION
CIRCUIT 2
VDD
Legend: u = unchanged
Note:
VDD
A WDT time-out will occur regardless of
the status of the TO bit. A SLEEP instruction will be executed, regardless of the status of the PD bit.
R1
Q1
MCLR
R2
40k
Table 7-3 lists the reset conditions for the special
function registers, while Table 7-4 lists the reset
conditions for all the registers.
PIC16C5X
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
VDD •
1998 Microchip Technology Inc.
Preliminary
R1
R1 + R2
= 0.7V
DS30453B-page 41
PIC16C5X
7.9
Power-Down Mode (SLEEP)
7.10
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
7.9.1
SLEEP
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS) is set, the PD
bit (STATUS) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR/VPP pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level.
7.9.2
7.11
Microchip does not recommend code protecting windowed devices.
ID Locations (not implemented on
PIC16C52)
Four memory locations are designated as ID locations
where the user can store checksum or other
code-identification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as '1's.
Note:
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
Program Verification/Code Protection
Microchip will assign a unique pattern
number for QTP and SQTP requests and
for ROM devices. This pattern number will
be unique and traceable to the submitted
code.
An external reset input on MCLR/VPP pin.
A Watchdog Timer time-out reset (if WDT was
enabled).
Both of these events cause a device reset. The TO and
PD bits can be used to determine the cause of device
reset.
The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
DS30453B-page 42
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
8.0
INSTRUCTION SET SUMMARY
Each PIC16C5X instruction is a 12-bit word divided into an
OPCODE, which specifies the instruction type, and one or
more operands which further specify the operation of the
instruction. The PIC16C5X instruction set summary in
Table 8-2 groups the instructions into byte-oriented,
bit-oriented, and literal and control operations. Table 8-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register
designator and 'd' represents a destination designator. The
file register designator is used to specify which one of the
32 file registers is to be used by the instruction.
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles. One instruction cycle consists of
four oscillator periods. Thus, for an oscillator frequency
of 4 MHz, the normal instruction execution time is 1 µs.
If a conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
where 'h' signifies a hexadecimal digit.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Byte-oriented file register operations
0xhhh
FIGURE 8-1:
11
OPCODE FIELD
DESCRIPTIONS
Field
11
OPCODE
b
k
Bit address within an 8-bit file register
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
TOS
PC
WDT
TO
PD
dest
[ ]
( )
→
∈
italics
4
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Description
Register file address (0x00 to 0x7F)
Working register (accumulator)
label
5
d
Bit-oriented file register operations
f
W
d
6
OPCODE
For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.
TABLE 8-1:
GENERAL FORMAT FOR
INSTRUCTIONS
8 7
5 4
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register 'f')
Default is d = 1
Label name
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTO instruction
11
9
8
OPCODE
Top of Stack
Program Counter
Watchdog Timer Counter
Time-Out bit
Power-Down bit
Destination, either the W register or the specified
register file location
0
k (literal)
k = 9-bit immediate value
Options
Contents
Assigned to
Register bit field
In the set of
User defined term (font is courier)
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 43
PIC16C5X
TABLE 8-2:
INSTRUCTION SET SUMMARY
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f,d
f,d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
12-Bit Opcode
Description
Cycles MSb
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
LSb
Status
Affected Notes
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C,DC,Z
None
Z
1,2,4
2,4
4
1
1
1 (2)
1 (2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2,4
2,4
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
2,4
2,4
2,4
2,4
2,4
2,4
1,4
2,4
2,4
1,2,4
2,4
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW
k
k
k
k
k
k
k
k
–
f
k
AND literal with W
Call subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
Exclusive OR Literal to W
1
3
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.
(See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers)
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate
latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS30453B-page 44
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
ANDWF
AND W with f
Syntax:
Operands:
[ label ] ANDWF
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
f,d
Status Affected: C, DC, Z
Encoding:
0001
f,d
Status Affected: Z
11df
Encoding:
ffff
0001
01df
ffff
Description:
Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'.
Description:
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Words:
1
Words:
1
Cycles:
1
Example:
ADDWF
FSR, 0
Cycles:
1
Example:
ANDWF
Before Instruction
W
=
FSR =
W =
FSR =
0x17
0xC2
After Instruction
After Instruction
W
=
FSR =
W
=
FSR =
0xD9
0xC2
ANDLW
And literal with W
Syntax:
[ label ] ANDLW
Operands:
0 ≤ k ≤ 255
Operation:
(W).AND. (k) → (W)
k
Status Affected: Z
Encoding:
Description:
kkkk
1
Cycles:
1
Example:
ANDLW
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 31
0≤b≤7
Operation:
0 → (f)
Encoding:
Description:
=
=
0100
1
Cycles:
1
Example:
BCF
0x5F
bbbf
ffff
FLAG_REG,
7
Before Instruction
FLAG_REG = 0xC7
0xA3
After Instruction
After Instruction
W
f,b
Bit 'b' in register 'f' is cleared.
Words:
Before Instruction
W
0x17
0x02
Status Affected: None
kkkk
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Words:
1
Before Instruction
0x17
0xC2
1110
FSR,
FLAG_REG = 0x47
0x03
1998 Microchip Technology Inc.
Preliminary
DS30453B-page 45
PIC16C5X
BSF
Bit Set f
Syntax:
[ label ] BSF
BTFSS
Bit Test f, Skip if Set
Syntax:
Operands:
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0≤b≤7
Operands:
0 ≤ f ≤ 31
0≤b
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