PIC16C5X
EPROM/ROM-Based 8-bit CMOS Microcontroller Series
Devices Included in this Data Sheet:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PIC16C54
PIC16CR54
PIC16C55
PIC16C56
PIC16CR56
PIC16C57
PIC16CR57
PIC16C58
PIC16CR58
Note:
Peripheral Features:
PIC16C5X refers to all revisions of the part
(i.e., PIC16C54 refers to PIC16C54,
PIC16C54A, and PIC16C54C), unless
specifically called out otherwise.
High-Performance RISC CPU:
• Only 33 single word instructions to learn
• All instructions are single cycle except for program branches which are two-cycle
• Operating speed: DC - 40 MHz clock input
DC - 100 ns instruction cycle
Device
PIC16C54
PIC16C54A
PIC16C54C
PIC16CR54A
PIC16CR54C
PIC16C55
PIC16C55A
PIC16C56
PIC16C56A
PIC16CR56A
PIC16C57
PIC16C57C
PIC16CR57C
PIC16C58B
PIC16CR58B
12-bit wide instructions
8-bit wide data path
Seven or eight special function hardware registers
Two-level deep hardware stack
Direct, indirect and relative addressing modes for
data and instructions
Pins
I/O
18
18
18
18
18
28
28
18
18
18
28
28
28
18
18
12
12
12
12
12
20
20
12
12
12
20
20
20
12
12
1997-2013 Microchip Technology Inc.
EPROM/
RAM
ROM
512
512
512
512
512
512
512
1K
1K
1K
2K
2K
2K
2K
2K
25
25
25
25
25
24
24
25
25
25
72
72
72
73
73
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
• Programmable Code Protection
• Power saving SLEEP mode
• Selectable oscillator options:
- RC:
Low cost RC oscillator
- XT:
Standard crystal/resonator
- HS:
High speed crystal/resonator
- LP:
Power saving, low frequency crystal
CMOS Technology:
• Low power, high speed CMOS EPROM/ROM technology
• Fully static design
• Wide operating voltage and temperature range:
- EPROM Commercial/Industrial 2.0V to 6.25V
- ROM Commercial/Industrial 2.0V to 6.25V
- EPROM Extended 2.5V to 6.0V
- ROM Extended 2.5V to 6.0V
• Low power consumption
- < 2 mA typical @ 5V, 4 MHz
- 15 A typical @ 3V, 32 kHz
- < 0.6 A typical standby current
(with WDT disabled) @ 3V, 0C to 70C
Note:
Preliminary
In this document, figure and table titles
refer to all varieties of the part number indicated, (i.e., The title “Figure 15-1: Load
Conditions For Device Timing Specifications - PIC16C54A”, also refers to
PIC16LC54A and PIC16LV54A parts),
unless specifically called out otherwise.
DS30453E-page 1
PIC16C5X
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
18
17
16
15
14
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
13
12
RB7
RB6
RB5
RB4
11
10
T0CKI
•1
28
MCLR/VPP
VDD
2
27
OSC1/CLKIN
N/C
3
26
VSS
4
25
OSC2/CLKOUT
RC7
24
RC6
23
21
RC5
RC4
RC3
N/C
5
RA0
6
RA1
7
RA2
8
RA3
9
20
RC2
RB0
10
19
RB1
11
18
RC1
RC0
RB2
12
17
RB7
RB3
13
16
RB6
RB4
14
15
RB5
PIC16C55
PIC16C57
PIC16CR57
PIC16C54
PIC16CR54
PIC16C56
PIC16CR56
PIC16C58
PIC16CR58
1
2
3
4
5
6
7
8
9
RA2
RA3
T0CKI
MCLR/VPP
VSS
RB0
RB1
RB2
RB3
PDIP, SOIC, Windowed CERDIP
22
SSOP
SSOP
20
19
18
17
16
15
14
13
12
11
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4
VSS
T0CKI
VDD
VDD
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16C55
PIC16C57
PIC16CR57
PIC16C54
PIC16CR54
PIC16C56
PIC16CR56
PIC16C58
PIC16CR58
1
2
3
4
5
6
7
8
9
10
RA2
RA3
T0CKI
MCLR/VPP
VSS
VSS
RB0
RB1
RB2
RB3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
Device Differences
Device
PIC16C54
PIC16C54A
PIC16C54C
PIC16C55
PIC16C55A
PIC16C56
PIC16C56A
PIC16C57
PIC16C57C
PIC16C58B
PIC16CR54A
PIC16CR54C
PIC16CR56A
PIC16CR57C
PIC16CR58B
Voltage
Range
Oscillator
Selection
(Program)
Oscillator
Process
Technology
(Microns)
ROM
Equivalent
MCLR
Filter
2.5-6.25
2.0-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-5.5
2.5-6.25
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
Factory
User
User
Factory
User
Factory
User
Factory
User
User
Factory
Factory
Factory
Factory
Factory
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
1.2
0.9
0.7
1.7
0.7
1.7
0.7
1.2
0.7
0.7
1.2
0.7
0.7
0.7
0.7
PIC16CR54A
—
PIC16CR54C
—
—
—
PIC16CR56A
—
PIC16CR57C
PIC16CR58B
N/A
N/A
N/A
N/A
N/A
No
No
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note:
The table shown above shows the generic names of the PIC16C5X devices. For device varieties, please
refer to Section 2.0.
DS30453E-page 2
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16C5X Device Varieties ......................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................ 9
4.0 Oscillator Configurations ............................................................................................................................................................ 15
5.0 Reset .......................................................................................................................................................................................... 19
6.0 Memory Organization ................................................................................................................................................................. 25
7.0 I/O Ports ..................................................................................................................................................................................... 35
8.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 37
9.0 Special Features of the CPU...................................................................................................................................................... 43
10.0 Instruction Set Summary ............................................................................................................................................................ 49
11.0 Development Support................................................................................................................................................................. 61
12.0 Electrical Characteristics - PIC16C54/55/56/57 ......................................................................................................................... 67
13.0 Electrical Characteristics - PIC16CR54A ................................................................................................................................... 79
14.0 Device Characterization - PIC16C54/55/56/57/CR54A.............................................................................................................. 91
15.0 Electrical Characteristics - PIC16C54A.................................................................................................................................... 103
16.0 Device Characterization - PIC16C54A ..................................................................................................................................... 117
17.0 Electrical Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ........................................ 131
18.0 Device Characterization - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B .......................................... 145
19.0 Electrical Characteristics - PIC16C54C/C55A/C56A/C57C/C58B 40MHz ............................................................................... 155
20.0 Device Characterization - PIC16C54C/C55A/C56A/C57C/C58B 40MHz ................................................................................ 165
21.0 Packaging Information.............................................................................................................................................................. 171
Appendix A: Compatibility ............................................................................................................................................................. 182
On-Line Support................................................................................................................................................................................. 187
Reader Response .............................................................................................................................................................................. 188
Product Identification System ............................................................................................................................................................ 189
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 3
PIC16C5X
NOTES:
DS30453E-page 4
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
8-Bit EPROM/ROM-Based CMOS Microcontrollers
1.0
GENERAL DESCRIPTION
1.1
The PIC16C5X from Microchip Technology is a family
of low cost, high performance, 8-bit fully static,
EPROM/ROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single word/
single cycle instructions. All instructions are single
cycle except for program branches which take two
cycles. The PIC16C5X delivers performance in an
order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC16C5X products are equipped with special features that reduce system cost and power requirements.
The Power-on Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external RESET circuitry.
There are four oscillator configurations to choose from,
including the power saving LP (Low Power) oscillator
and cost saving RC oscillator. Power saving SLEEP
mode, Watchdog Timer and Code Protection features
improve system cost, power and reliability.
Applications
The PIC16C5X series fits perfectly in applications ranging from high speed automotive and appliance motor
control to low power remote transmitters/receivers,
pointing devices and telecom processors. The EPROM
technology makes customizing application programs
(transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small
footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low cost, low power, high
performance ease of use and I/O flexibility make the
PIC16C5X series very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic in larger
systems, co-processor applications).
The UV erasable CERDIP packaged versions are ideal
for code development, while the cost effective One
Time Programmable (OTP) versions are suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in OTP
microcontrollers, while benefiting from the OTP’s
flexibility.
The PIC16C5X products are supported by a full featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and
a full featured programmer. All the tools are supported
on IBM PC and compatible machines.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 5
PIC16C5X
TABLE 1-1:
PIC16C5X FAMILY OF DEVICES
Features
Maximum Operation Frequency
EPROM Program Memory (x12 words)
ROM Program Memory (x12 words)
RAM Data Memory (bytes)
PIC16C54
PIC16CR54
PIC16C55
PIC16C56
PIC16CR56
40 MHz
20 MHz
40 MHz
40 MHz
20 MHz
512
—
512
1K
—
—
512
—
—
1K
25
25
24
25
25
TMR0
TMR0
TMR0
TMR0
TMR0
I/O Pins
12
12
20
12
12
Number of Instructions
33
33
33
33
33
Timer Module(s)
Packages
18-pin DIP,
18-pin DIP,
28-pin DIP,
18-pin DIP,
18-pin DIP,
SOIC;
SOIC;
SOIC;
SOIC;
SOIC;
20-pin SSOP 20-pin SSOP 28-pin SSOP 20-pin SSOP 20-pin SSOP
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high
I/O current capability.
Features
PIC16C57
PIC16CR57
PIC16C58
PIC16CR58
40 MHz
20 MHz
40 MHz
20 MHz
2K
—
2K
—
ROM Program Memory (x12 words)
—
2K
—
2K
RAM Data Memory (bytes)
72
72
73
73
TMR0
TMR0
TMR0
TMR0
20
20
12
12
33
33
33
33
Maximum Operation Frequency
EPROM Program Memory (x12 words)
Timer Module(s)
I/O Pins
Number of Instructions
Packages
28-pin DIP, SOIC; 28-pin DIP, SOIC; 18-pin DIP, SOIC; 18-pin DIP, SOIC;
28-pin SSOP
28-pin SSOP
20-pin SSOP
20-pin SSOP
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high
I/O current capability.
DS30453E-page 6
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
2.0
PIC16C5X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in this section. When placing
orders, please use the PIC16C5X Product Identification System at the back of this data sheet to specify the
correct part number.
For the PIC16C5X family of devices, there are four
device types, as indicated in the device number:
1.
C, as in PIC16C54C. These devices have
EPROM program memory and operate over the
standard voltage range.
LC, as in PIC16LC54A. These devices have
EPROM program memory and operate over an
extended voltage range.
CR, as in PIC16CR54A. These devices have
ROM program memory and operate over the
standard voltage range.
LCR, as in PIC16LCR54A. These devices have
ROM program memory and operate over an
extended voltage range.
2.
3.
4.
2.1
UV Erasable Devices (EPROM)
The UV erasable versions offered in CERDIP packages, are optimal for prototype development and pilot
programs.
UV erasable devices can be programmed for any of the
four oscillator configurations. Microchip's
PICSTART Plus(1) and PRO MATE programmers
both support programming of the PIC16C5X. Third
party programmers also are available. Refer to the
Third Party Guide (DS00104) for a list of sources.
2.2
2.3
Quick-Turnaround-Production
(QTP) Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration bit options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your
Microchip Technology sales office for more details.
2.4
Serialized Quick-TurnaroundProduction (SQTPSM) Devices
Microchip offers the unique programming service
where a few user defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or sequential. The devices are identical to the OTP devices but
with all EPROM locations and configuration bit options
already programmed by the factory.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, giving the customer a low
cost option for high volume, mature products.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates, or small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must be programmed.
Note 1: PIC16LC54C and PIC16C54A devices
require OSC2 not to be connected while
programming with PICSTART® Plus
programmer.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 7
PIC16C5X
NOTES:
DS30453E-page 8
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C5X family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC16C5X uses a Harvard architecture in which
program and data are accessed on separate buses.
This improves bandwidth over traditional von Neumann
architecture where program and data are fetched on
the same bus. Separating program and data memory
further allows instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are 12
bits wide making it possible to have all single word
instructions. A 12-bit wide program memory access
bus fetches a 12-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a
single cycle except for program branches.
The PIC16C54/CR54 and PIC16C55 address 512 x 12
of program memory, the PIC16C56/CR56 address
1K x 12 of program memory, and the PIC16C57/CR57
and PIC16C58/CR58 address 2K x 12 of program
memory. All program memory is internal.
The PIC16C5X can directly or indirectly address its
register files and data memory. All special function registers including the program counter are mapped in the
data memory. The PIC16C5X has a highly orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C5X simple yet efficient. In addition, the learning
curve is reduced significantly.
1997-2013 Microchip Technology Inc.
The PIC16C5X device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic
unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the W (working) register. The other
operand is either a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1
(for PIC16C54/56/58) and Table 3-2 (for PIC16C55/
57).
Preliminary
DS30453E-page 9
PIC16C5X
FIGURE 3-1:
PIC16C5X SERIES BLOCK DIAGRAM
9-11
9-11
EPROM/ROM
512 X 12 TO
2048 X 12
T0CKI
PIN
STACK 1
STACK 2
CONFIGURATION WORD
“DISABLE”
“OSC
SELECT”
PC
WATCHDOG
TIMER
12
“CODE
PROTECT”
2
OSCILLATOR/
TIMING &
CONTROL
INSTRUCTION
REGISTER
WDT TIME
OUT
9
12
OSC1 OSC2 MCLR
CLKOUT
WDT/TMR0
PRESCALER
8
“SLEEP”
INSTRUCTION
DECODER
6
“OPTION”
OPTION REG.
DIRECT ADDRESS
DIRECT RAM
ADDRESS
FROM W
5
5-7
LITERALS
8
STATUS
TMR0
GENERAL
PURPOSE
REGISTER
FILE
(SRAM)
24, 25, 72 or
73 Bytes
FSR
8
W
DATA BUS
ALU
8
FROM W
4
4
“TRIS 5”
8
“TRIS 6”
TRISA
PORTA
4
RA
DS30453E-page 10
FROM W
Preliminary
TRISB
FROM W
8
PORTB
8
RB
8
“TRIS 7”
TRISC
8
PORTC
8
RC
(28-Pin
Devices Only)
1997-2013 Microchip Technology Inc.
PIC16C5X
TABLE 3-1:
Pin Name
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
T0CKI
PINOUT DESCRIPTION - PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58,
PIC16CR58
Pin Number
Pin
DIP
SOIC SSOP Type
Buffer
Description
Type
17
18
1
2
6
7
8
9
10
11
12
13
3
17
18
1
2
6
7
8
9
10
11
12
13
3
19
20
1
2
7
8
9
10
11
12
13
14
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
4
4
4
I
ST
Bi-directional I/O port
Bi-directional I/O port
Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
Master clear (RESET) input/programming voltage input.
This pin is an active low RESET to the device. Voltage on
the MCLR/VPP pin must not exceed VDD to avoid unintended entering of Programming mode.
OSC1/CLKIN
16
16
18
I
ST
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
15
15
17
O
—
Oscillator crystal output. Connects to crystal or resonator
in crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT, which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
14
14
15,16
P
—
Positive supply for logic and I/O pins.
VDD
VSS
5
5
5,6
P
—
Ground reference for logic and I/O pins.
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input
MCLR/VPP
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 11
PIC16C5X
TABLE 3-2:
PINOUT DESCRIPTION
- PIC16C55, PIC16C57, PIC16CR57
Pin Number
Pin Name
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
T0CKI
Pin Buffer
SSOP Type Type
DIP
SOIC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
28
28
28
I
ST
Description
Bi-directional I/O port
Bi-directional I/O port
Bi-directional I/O port
Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
Master clear (RESET) input. This pin is an active low
RESET to the device.
OSC1/CLKIN
27
27
27
I
ST
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
26
26
26
O
—
Oscillator crystal output. Connects to crystal or resonator
in crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
2
2
3,4
P
—
Positive supply for logic and I/O pins.
VDD
VSS
4
4
1,14
P
—
Ground reference for logic and I/O pins.
N/C
3,5
3,5
—
—
—
Unused, do not connect.
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input
MCLR
DS30453E-page 12
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1 and the instruction is fetched from program memory and latched into
the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks
and instruction execution flow are shown in Figure 3-2
and Example 3-1.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This instruction is then decoded and executed during the Q2, Q3
and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW H'55'
Fetch 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 13
PIC16C5X
NOTES:
DS30453E-page 14
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
4.0
OSCILLATOR
CONFIGURATIONS
4.1
Oscillator Types
FIGURE 4-2:
PIC16C5Xs can be operated in four different oscillator
modes. The user can program two configuration bits
(FOSC1:FOSC0) to select one of these four modes:
1.
2.
3.
4.
LP:
XT:
HS:
RC:
Note:
4.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 4-1:
Crystal Oscillator/Ceramic
Resonators
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
OSC1
PIC16C5X
SLEEP
XTAL
RF(3)
OSC2
To internal
logic
RS(2)
C2(1)
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
3: RF varies with the Oscillator mode chosen (approx. value = 10 M).
Osc
Type
OSC2
CAPACITOR SELECTION FOR
CERAMIC RESONATORS PIC16C5X, PIC16CR5X
Resonator
Freq
Cap. Range
C1
Cap. Range
C2
455 kHz
68-100 pF
68-100 pF
2.0 MHz
15-33 pF
15-33 pF
4.0 MHz
10-22 pF
10-22 pF
HS
8.0 MHz
10-22 pF
10-22 pF
16.0 MHz
10 pF
10 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
TABLE 4-2:
Osc
Type
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR PIC16C5X, PIC16CR5X
Crystal
Freq
Cap.Range
C1
Cap. Range
C2
15 pF
15 pF
32 kHz(1)
100 kHz
15-30 pF
200-300 pF
200 kHz
15-30 pF
100-200 pF
455 kHz
15-30 pF
15-100 pF
1 MHz
15-30 pF
15-30 pF
2 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
HS
4 MHz
15 pF
15 pF
8 MHz
15 pF
15 pF
20 MHz
15 pF
15 pF
Note 1: For VDD > 4.5V, C1 = C2 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.
LP
XT
Note:
1997-2013 Microchip Technology Inc.
OSC1
PIC16C5X
XT
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 4-1). The
PIC16C5X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications.
When in XT, LP or HS modes, the device can have an
external clock source drive the OSC1/CLKIN pin
(Figure 4-2).
C1(1)
Clock from
ext. system
Open
Not all oscillator selections available for all
parts. See Section 9.1.
FIGURE 4-1:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
Preliminary
If you change from this device to another
device, please verify oscillator characteristics in your application.
DS30453E-page 15
PIC16C5X
4.3
External Crystal Oscillator Circuit
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a
wide operating range and better stability. A welldesigned crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator
circuits can be used: one with parallel resonance, or
one with series resonance.
Figure 4-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 4-4:
Figure 4-3 shows an implementation example of a parallel resonant oscillator circuit. The circuit is designed
to use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 k resistor
provides the negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 4-3:
EXAMPLE OF EXTERNAL
PARALLEL RESONANT
CRYSTAL OSCILLATOR
CIRCUIT (USING XT, HS
OR LP OSCILLATOR
MODE)
EXAMPLE OF EXTERNAL
SERIES RESONANT
CRYSTAL OSCILLATOR
CIRCUIT (USING XT, HS
OR LP OSCILLATOR
MODE)
330K
330K
74AS04
74AS04
To Other
Devices
74AS04
PIC16C5X
CLKIN
0.1 F
XTAL
Open
OSC2
+5V
To Other
Devices
10K
74AS04
4.7K
PIC16C5X
CLKIN
74AS04
Open
OSC2
10K
XTAL
10K
20 pF
DS30453E-page 16
20 pF
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
4.4
FIGURE 4-5:
RC Oscillator
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C components used.
Figure 4-5 shows how the R/C combination is connected to the PIC16C5X. For REXT values below
2.2 k, the oscillator operation may become unstable,
or stop completely. For very high REXT values
(e.g., 1 M) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 3 k and 100 k.
RC OSCILLATOR MODE
VDD
REXT
Internal
clock
OSC1
N
CEXT
PIC16C5X
VSS
OSC2/CLKOUT
Fosc/4
Note:
If you change from this device to another
device, please verify oscillator characteristics in your application.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or package lead frame capacitance.
The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given REXT/
CEXT values as well as frequency variation due to operating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 17
PIC16C5X
NOTES:
DS30453E-page 18
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
5.0
RESET
The TO and PD bits (STATUS ) are set or cleared
depending on the different RESET conditions (Table 51). These bits may be used to determine the nature of
the RESET.
PIC16C5X devices may be RESET in one of the following ways:
•
•
•
•
•
Power-On Reset (POR)
MCLR Reset (normal operation)
MCLR Wake-up Reset (from SLEEP)
WDT Reset (normal operation)
WDT Wake-up Reset (from SLEEP)
Table 5-3 lists a full description of RESET states of all
registers. Figure 5-1 shows a simplified block diagram
of the On-chip Reset circuit.
Table 5-1 shows these RESET conditions for the PCL
and STATUS registers.
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-On Reset (POR), MCLR or
WDT Reset. A MCLR or WDT wake-up from SLEEP
also results in a device RESET, and not a continuation
of operation before SLEEP.
TABLE 5-1:
STATUS BITS AND THEIR SIGNIFICANCE
Condition
Power-On Reset
MCLR Reset (normal operation)
MCLR Wake-up (from SLEEP)
WDT Reset (normal operation)
WDT Wake-up (from SLEEP)
Legend: u = unchanged, x = unknown, — = unimplemented read as '0'.
TABLE 5-2:
TO
PD
1
u
1
u
1
0
0
0
1
0
SUMMARY OF REGISTERS ASSOCIATED WITH RESET
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
MCLR and
WDT Reset
03h
STATUS
PA2
PA1
PA0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
Legend:
u = unchanged, x = unknown, q = see Table 5-1 for possible values.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 19
PIC16C5X
TABLE 5-3:
RESET CONDITIONS FOR ALL REGISTERS
Register
Address
Power-On Reset
MCLR or WDT Reset
W
N/A
xxxx xxxx
TRIS
N/A
1111 1111
OPTION
N/A
--11 1111
INDF
00h
xxxx xxxx
TMR0
01h
xxxx xxxx
PCL
02h
1111 1111
STATUS
03h
0001 1xxx
(1)
FSR
04h
1xxx xxxx
PORTA
05h
---- xxxx
PORTB
06h
xxxx xxxx
PORTC(2)
07h
xxxx xxxx
General Purpose Register Files
07-7Fh
xxxx xxxx
Legend: x = unknown
u = unchanged
- = unimplemented, read as '0'
q = see tables in Table 5-1 for possible values.
uuuu
1111
--11
uuuu
uuuu
1111
000q
1uuu
---uuuu
uuuu
uuuu
uuuu
1111
1111
uuuu
uuuu
1111
quuu
uuuu
uuuu
uuuu
uuuu
uuuu
Note 1: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the
value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu.
2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
MCLR/VPP pin
WDT Time-out
RESET
WDT
On-Chip
RC OSC
8-bit Asynch
Ripple Counter
(Device Reset
Timer)
S
Q
R
Q
CHIP RESET
DS30453E-page 20
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
5.1
FIGURE 5-2:
Power-On Reset (POR)
The PIC16C5X family incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip
RESET for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin to VDD. A
simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 5-1.
The Power-On Reset circuit and the Device Reset
Timer (Section 5.2) circuit are closely related. On
power-up, the RESET latch is set and the DRT is
RESET. The DRT timer begins counting once it detects
MCLR to be high. After the time-out period, which is
typically 18 ms, it will RESET the reset latch and thus
end the on-chip RESET signal.
A power-up example where MCLR is not tied to VDD is
shown in Figure 5-3. VDD is allowed to rise and stabilize
before bringing MCLR high. The chip will actually come
out of reset TDRT msec after MCLR goes high.
In Figure 5-4, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together). The VDD
is stable before the start-up timer times out and there is
no problem in getting a proper RESET. However,
Figure 5-5 depicts a problem situation where VDD rises
too slowly. The time between when the DRT senses a
high on the MCLR/VPP pin, and when the MCLR/VPP
pin (and VDD) actually reach their full value, is too long.
In this situation, when the start-up timer times out, VDD
has not reached the VDD (min) value and the chip is,
therefore, not guaranteed to function correctly. For
such situations, we recommend that external RC circuits be used to achieve longer POR delay times
(Figure 5-2).
Note:
VDD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
D
R
R1
MCLR
C
PIC16C5X
• External Power-On Reset circuit is required
only if VDD power-up is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
• R < 40 k is recommended to make sure that
voltage drop across R does not violate the
device electrical specification.
• R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the
event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
When the device starts normal operation
(exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in RESET until the
operating conditions are met.
For more information on PIC16C5X POR, see PowerUp Considerations - AN522 in the Embedded Control
Handbook.
The POR circuit does not produce an internal RESET
when VDD declines.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 21
PIC16C5X
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
FIGURE 5-5:
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will RESET properly if, and only if, V1 VDD min
DS30453E-page 22
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
5.2
FIGURE 5-7:
Device Reset Timer (DRT)
The Device Reset Timer (DRT) provides an 18 ms
nominal time-out on RESET regardless of Oscillator
mode used. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the
DRT is active. The DRT delay allows VDD to rise above
VDD min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the device in
a RESET condition for approximately 18 ms after the
voltage on the MCLR/VPP pin has reached a logic high
(VIH) level. Thus, external RC networks connected to
the MCLR input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted
applications.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications
using the WDT to wake the PIC16C5X from SLEEP
mode automatically.
5.3
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
40K
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
VDD •
FIGURE 5-8:
Reset on Brown-Out
VDD
VDD
VDD
= 0.7V
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
bypass
capacitor
VDD
MCP809
To RESET PIC16C5X devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 5-6, Figure 5-7 and Figure 58.
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
R1
R1 + R2
VDD
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be RESET in the event of
a brown-out.
FIGURE 5-6:
PIC16C5X
RST
Vss
MCLR
PIC16C5X
This brown-out protection circuit employs Microchip Technology’s MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX families
of supervisors provide push-pull and open collector outputs with both "active high and active low"
RESET pins. There are 7 different trip point selections to accommodate 5V and 3V systems.
33K
10K
Q1
MCLR
40K
PIC16C5X
This circuit will activate RESET when VDD goes below Vz
+ 0.7V (where Vz = Zener voltage).
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 23
PIC16C5X
NOTES:
DS30453E-page 24
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
6.0
MEMORY ORGANIZATION
FIGURE 6-2:
PIC16C5X memory is organized into program memory
and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one or two
STATUS Register bits. For devices with a data memory
register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Selection Register (FSR).
PIC16C56/CR56
PROGRAM MEMORY MAP
AND STACK
PC
10
CALL, RETLW
Stack Level 1
Stack Level 2
000h
Program Memory Organization
The PIC16C54, PIC16CR54 and PIC16C55 have a 9bit Program Counter (PC) capable of addressing a 512
x 12 program memory space (Figure 6-1). The
PIC16C56 and PIC16CR56 have a 10-bit Program
Counter (PC) capable of addressing a 1K x 12 program
memory space (Figure 6-2). The PIC16CR57,
PIC16C58 and PIC16CR58 have an 11-bit Program
Counter capable of addressing a 2K x 12 program
memory space (Figure 6-3). Accessing a location
above the physically implemented address will cause a
wraparound.
User Memory
Space
6.1
FIGURE 6-3:
A NOP at the RESET vector location will cause a restart
at location 000h. The RESET vector for the PIC16C54,
PIC16CR54 and PIC16C55 is at 1FFh. The RESET
vector for the PIC16C56 and PIC16CR56 is at 3FFh.
The RESET vector for the PIC16C57, PIC16CR57,
PIC16C58, and PIC16CR58 is at 7FFh. See
Section 6.5 for additional information using CALL and
GOTO instructions.
On-chip Program
Memory (Page 0)
0FFh
100h
1FFh
200h
On-chip Program
Memory (Page 1)
2FFh
300h
RESET Vector
3FFh
PIC16C57/CR57/C58/
CR58 PROGRAM
MEMORY MAP AND
STACK
PC
11
CALL, RETLW
Stack Level 1
Stack Level 2
000h
FIGURE 6-1:
PIC16C54/CR54/C55
PROGRAM MEMORY MAP
AND STACK
On-chip Program
Memory (Page 0)
1FFh
200h
User Memory
Space
PC
9
CALL, RETLW
Stack Level 1
Stack Level 2
User Memory
Space
000h
On-chip
Program
Memory
0FFh
100h
RESET Vector
1FFh
1997-2013 Microchip Technology Inc.
0FFh
100h
On-chip Program
Memory (Page 1)
2FFh
300h
3FFh
400h
On-chip Program
Memory (Page 2)
4FFh
500h
5FFh
600h
Preliminary
On-chip Program
Memory (Page 3)
6FFh
700h
RESET Vector
7FFh
DS30453E-page 25
PIC16C5X
6.2
FIGURE 6-4:
Data Memory Organization
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers and General Purpose Registers.
PIC16C54, PIC16CR54,
PIC16C55, PIC16C56,
PIC16CR56 REGISTER
FILE MAP
File Address
The Special Function Registers include the TMR0 register, the Program Counter (PC), the Status Register,
the I/O registers (ports) and the File Select Register
(FSR). In addition, Special Purpose Registers are used
to control the I/O port configuration and prescaler
options.
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
The General Purpose Registers are used for data and
control information under command of the instructions.
05h
PORTA
06h
PORTB
For the PIC16C54, PIC16CR54, PIC16C56 and
PIC16CR56, the register file is composed of 7 Special
Function Registers and 25 General Purpose Registers
(Figure 6-4).
07h
PORTC(2)
08h
General
Purpose
Registers
For the PIC16C55, the register file is composed of 8
Special Function Registers and 24 General Purpose
Registers.
For the PIC16C57 and PIC16CR57, the register file is
composed of 8 Special Function Registers, 24 General
Purpose Registers and up to 48 additional General
Purpose Registers that may be addressed using a
banking scheme (Figure 6-5).
For the PIC16C58 and PIC16CR58, the register file is
composed of 7 Special Function Registers, 25 General
Purpose Registers and up to 48 additional General
Purpose Registers that may be addressed using a
banking scheme (Figure 6-6).
6.2.1
1Fh
Note 1: Not a physical register. See
Section 6.7.
2: PIC16C55 only, in all other devices this
is implemented as a a general purpose
register.
GENERAL PURPOSE REGISTER
FILE
The register file is accessed either directly or indirectly
through the File Select Register (FSR). The FSR Register is described in Section 6.7.
DS30453E-page 26
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 6-5:
PIC16C57/CR57 REGISTER FILE MAP
FSR
00
01
10
11
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
07h
PORTC
08h
General
Purpose
Registers
0Fh
10h
20h
60h
Addresses map back to
addresses in Bank 0.
2Fh
4Fh
6Fh
30h
50h
70h
General
Purpose
Registers
1Fh
40h
General
Purpose
Registers
3Fh
Bank 0
General
Purpose
Registers
5Fh
Bank 1
General
Purpose
Registers
7Fh
Bank 2
Bank 3
Note 1: Not a physical register. See Section 6.7.
FIGURE 6-6:
PIC16C58/CR58 REGISTER FILE MAP
FSR
00
01
10
11
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
PORTA
06h
PORTB
20h
40h
60h
Addresses map back to
addresses in Bank 0.
07h
General
Purpose
Registers
2Fh
0Fh
10h
4Fh
30h
General
Purpose
Registers
1Fh
50h
General
Purpose
Registers
3Fh
Bank 0
6Fh
70h
General
Purpose
Registers
5Fh
Bank 1
General
Purpose
Registers
7Fh
Bank 2
Bank 3
Note 1: Not a physical register. See Section 6.7.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 27
PIC16C5X
6.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions to control the operation of the device (Table 6-1).
The Special Registers can be classified into two sets.
The Special Function Registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
TABLE 6-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Details
on Page
N/A
TRIS
I/O Control Registers (TRISA, TRISB, TRISC)
1111 1111
35
N/A
OPTION
Contains control bits to configure Timer0 and Timer0/WDT prescaler
--11 1111
30
00h
INDF
Uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
32
01h
TMR0
Timer0 Module Register
xxxx xxxx
38
PCL
Low order 8 bits of PC
1111 1111
31
0001 1xxx
29
02h
(1)
03h
04h
STATUS
FSR
PA2
PA1
PA0
TO
PD
Z
DC
C
1xxx
Indirect data memory address pointer
xxxx(3)
32
05h
PORTA
—
—
—
—
RA3
RA2
RA1
RA0
---- xxxx
35
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
35
07h(2)
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
35
Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 6.5 for an explanation of how to access
these bits.
2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and
PIC16CR58.
3: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the value on RESET is
111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu.
DS30453E-page 28
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
6.3
STATUS Register
writable. Therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.
This register contains the arithmetic status of the ALU,
the RESET status and the page preselect bits for program memories larger than 512 words.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS Register
as 000u u1uu (where u = unchanged).
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
REGISTER 6-1:
R/W-0
PA2
bit 7
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS Register because these instructions do not affect the Z, DC
or C bits from the STATUS Register. For other instructions which do affect STATUS Bits, see Section 10.0,
Instruction Set Summary.
STATUS REGISTER (ADDRESS: 03h)
R/W-0
PA1
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 0
bit 7:
PA2: This bit unused at this time.
Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.
bit 6-5:
PA: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(PIC16C58/CR58)
00 = Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58
01 = Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58
10 = Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58
11 = Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58
Each page is 512 words.
Using the PA bits as general purpose read/write bits in devices which do not use them for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF
SUBWF
RRF or RLF
1 = A carry occurred
1 = A borrow did not occur
Loaded with LSb or MSb, respectively
0 = A carry did not occur
0 = A borrow occurred
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
1997-2013 Microchip Technology Inc.
Preliminary
x = bit is unknown
DS30453E-page 29
PIC16C5X
6.4
OPTION Register
The OPTION Register is a 6-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W Register will be transferred to the OPTION Register. A RESET sets the OPTION bits.
REGISTER 6-2:
OPTION REGISTER
U-0
—
bit 7
U-0
—
W-1
T0CS
W-1
TOSE
W-1
PSA
bit 7-6:
Unimplemented: Read as ‘0’
bit 5:
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: Timer0 source edge select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3:
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0:
PS: Prescaler rate select bits
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
W-1
PS2
W-1
PS1
W-1
PS0
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
DS30453E-page 30
Preliminary
x = bit is unknown
1997-2013 Microchip Technology Inc.
PIC16C5X
6.5
FIGURE 6-8:
Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next program instruction to be executed. The PC value is
increased by one, every instruction cycle, unless an
instruction changes the PC.
GOTO Instruction
PC
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC (Figure 6-7, Figure 6-8 and
Figure 6-9).
For the PIC16C56, PIC16CR56, PIC16C57,
PIC16CR57, PIC16C58 and PIC16CR58, a page number must be supplied as well. Bit5 and bit6 of the STATUS Register provide page information to bit9 and
bit10 of the PC (Figure 6-8 and Figure 6-9).
Because PC is cleared in the CALL
instruction, or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any program memory page (512 words long).
FIGURE 6-7:
2
PA
0
CALL or Modify PCL Instruction
10
8 7
0
PCL
Instruction Word
2
Reset to ‘0’
PA
7
0
0
STATUS
FIGURE 6-9:
LOADING OF PC
BRANCH INSTRUCTIONS
- PIC16C57/PIC16CR57,
AND PIC16C58/
PIC16CR58
GOTO Instruction
10
9
8 7
0
PC
PCL
Instruction Word
PA
7
0
0
PCL
STATUS
CALL or Modify PCL Instruction
Instruction Word
10
CALL or Modify PCL Instruction
Reset to '0'
9
0
PC
2
7
PC
8
0
PCL
STATUS
GOTO Instruction
PC
8 7
0
LOADING OF PC
BRANCH INSTRUCTIONS
- PIC16C54, PIC16CR54,
PIC16C55
8
9
7
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PCL, ADDWF PCL,
and BSF PCL,5.
Note:
10
0
Instruction Word
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC does
not come from the instruction word, but is always
cleared (Figure 6-7 and Figure 6-8).
For the PIC16C56, PIC16CR56, PIC16C57,
PIC16CR57, PIC16C58 and PIC16CR58, a page number again must be supplied. Bit5 and bit6 of the STATUS Register provide page information to bit9 and
bit10 of the PC (Figure 6-8 and Figure 6-9).
LOADING OF PC
BRANCH INSTRUCTIONS
- PIC16C56/PIC16CR56
7
9
8 7
0
PC
PCL
0
PCL
Instruction Word
Instruction Word
2
Reset to ‘0’
PA
7
0
STATUS
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 31
PIC16C5X
6.5.1
PAGING CONSIDERATIONS –
PIC16C56/CR56, PIC16C57/CR57
AND PIC16C58/CR58
If the Program Counter is pointing to the last address of
a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS Register will not be updated. Therefore, the next GOTO,
CALL or modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0 or
PA).
For example, a NOP at location 1FFh (page 0) increments the PC to 200h (page 1). A GOTO xxx at 200h
will return the program to address xxh on page 0
(assuming that PA are clear).
To prevent this, the page preselect bits must be
updated under program control.
6.5.2
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page (i.e., the RESET vector).
The STATUS Register page preselect bits are cleared
upon a RESET, which means that page 0 is preselected.
Therefore, upon a RESET, a GOTO instruction at the
RESET vector location will automatically cause the program to jump to page 0.
6.6
Stack
PIC16C5X devices have a 10-bit or 11-bit wide, twolevel hardware push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W Register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the program memory.
For the RETLW instruction, the PC is loaded with the
Top of Stack (TOS) contents. All of the devices covered
in this data sheet have a two-level stack. The stack has
the same bit width as the device PC, therefore, paging
is not an issue when returning from a subroutine.
DS30453E-page 32
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
6.7
EXAMPLE 6-2:
Indirect Data Addressing; INDF
and FSR Registers
The INDF Register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR Register (FSR
is a pointer). This is indirect addressing.
EXAMPLE 6-1:
MOVLW
MOVWF
CLRF
INCF
BTFSC
GOTO
NEXT
INDIRECT ADDRESSING
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
H'10'
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF Register
;inc pointer
;all done?
;NO, clear next
Register file 08 contains the value 10h
Register file 09 contains the value 0Ah
Load the value 08 into the FSR Register
A read of the INDF Register will return the value
of 10h
• Increment the value of the FSR Register by one
(FSR = 09h)
• A read of the INDF register now will return the
value of 0Ah.
CONTINUE
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF Register indirectly results in a
no-operation (although STATUS bits may be affected).
PIC16C54, PIC16CR54, PIC16C55, PIC16C56,
PIC16CR56: These do not use banking. FSR bits
are unimplemented and read as '1's.
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 6-2.
PIC16C57, PIC16CR57, PIC16C58, PIC16CR58:
FSR are the bank select bits and are used to
select the bank to be addressed (00 = bank 0,
01 = bank 1, 10 = bank 2, 11 = bank 3).
•
•
•
•
FIGURE 6-10:
(FSR)
6
:
;YES, continue
The FSR is either a 5-bit (PIC16C54, PIC16CR54,
PIC16C55, PIC16C56, PIC16CR56) or 7-bit
(PIC16C57, PIC16CR57, PIC16C58, PIC16CR58)
wide register. It is used in conjunction with the INDF
Register to indirectly address the data memory area.
The FSR bits are used to select data memory
addresses 00h to 1Fh.
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(opcode)
5
bank select
4
3
2
1
Indirect Addressing
(FSR)
0
6
location select
5
4
bank
00
01
10
3
2
1
0
location select
11
00h
Addresses map back to
addresses in Bank 0.
Data
Memory(1)
0Fh
10h
1Fh
3Fh
Bank 0
5Fh
Bank 1
7Fh
Bank 2
Bank 3
Note 1: For register map detail see Section 6.2.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 33
PIC16C5X
NOTES:
DS30453E-page 34
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
7.0
I/O PORTS
7.5
As with any other register, the I/O Registers can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB, TRISC) are all set.
7.1
PORTA
PORTA is a 4-bit I/O Register. Only the low order 4 bits
are used (RA). Bits 7-4 are unimplemented and
read as '0's.
7.2
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 7-1. All ports may be used for both input and
output operation. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB,
TRISC) must be cleared (= 0). For use as an input, the
corresponding TRIS bit must be set. Any I/O pin can be
programmed individually as input or output.
FIGURE 7-1:
PORTB
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
PORTB is an 8-bit I/O Register (PORTB).
7.3
Data
Bus
PORTC
D
PORTC is an 8-bit I/O Register for PIC16C55,
PIC16C57 and PIC16CR57.
WR
Port
PORTC is a General Purpose Register for PIC16C54,
PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and
PIC16CR58.
7.4
W
Reg
TRIS Registers
CK
VDD
Q
P
N
D
TRIS ‘f’
I/O
pin(1)
Q
TRIS
Latch
The Output Driver Control Registers are loaded with
the contents of the W Register by executing the
TRIS f instruction. A '1' from a TRIS Register bit puts
the corresponding output driver in a hi-impedance
(input) mode. A '0' puts the contents of the output data
latch on the selected pins, enabling the output buffer.
Note:
Q
Data
Latch
CK
VSS
Q
RESET
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS Registers are “write-only” and are set (output
drivers disabled) upon RESET.
TABLE 7-1:
SUMMARY OF PORT REGISTERS
Address
Name
N/A
TRIS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O Control Registers (TRISA, TRISB, TRISC)
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
1111 1111
1111 1111
05h
PORTA
—
—
—
—
RA3
RA2
RA1
RA0
---- xxxx
---- uuuu
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, — = unimplemented, read as '0', Shaded cells = unimplemented, read as ‘0’
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 35
PIC16C5X
7.6
7.6.1
EXAMPLE 7-1:
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a bi-directional I/O pin (say bit0) and it is defined as an input at
this time, the input signal present on the pin itself would
be read into the CPU and rewritten to the data latch of
this particular pin, overwriting the previous content. As
long as the pin stays in the Input mode, no problem
occurs. However, if bit0 is switched into Output mode
later on, the content of the data latch may now be
unknown.
;Initial PORT Settings
; PORTB Inputs
; PORTB Outputs
;PORTB have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- ---------BCF
PORTB, 7
;01pp pppp
11pp pppp
BCF
PORTB, 6
;10pp pppp
11pp pppp
MOVLW H'3F'
;
TRIS PORTB
;10pp pppp
10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
Example 7-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 72). Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next
instruction, which causes that file to be read into the
CPU, is executed. Otherwise, the previous state of that
pin may be read into the CPU rather than the new state.
When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing
this I/O port.
7.6.2
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 7-2:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
SUCCESSIVE OPERATIONS ON I/O
PORTS
MOVWF PORTB
PC + 1
MOVF PORTB,W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
This example shows a write
to PORTB followed by a read
from PORTB.
RB
Instruction
executed
DS30453E-page 36
Port pin
written here
Port pin
sampled here
MOVWF PORTB
(Write to
PORTB)
MOVF PORTB,W
(Read
PORTB)
Preliminary
NOP
1997-2013 Microchip Technology Inc.
PIC16C5X
8.0
TIMER0 MODULE AND TMR0
REGISTER
Counter mode is selected by setting the T0CS bit
(OPTION). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 8.1.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Note:
Figure 8-1 is a simplified block diagram of the Timer0
module, while Figure 8-2 shows the electrical structure
of the Timer0 input.
The prescaler assignment is controlled in software by
the control bit PSA (OPTION). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 8.2 details the operation
of the prescaler.
Timer mode is selected by clearing the T0CS bit
(OPTION). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 8-3 and Figure 8-4).
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 8-1:
The prescaler may be used by either the
Timer0 module or the Watchdog Timer, but
not both.
A summary of registers associated with the Timer0
module is found in Table 8-1.
TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
PSout
1
Sync with
Internal
Clocks
1
T0CKI
pin
Programmable
Prescaler(2)
T0SE(1)
8
0
TMR0 reg
PSout
(2 cycle delay) Sync
3
T0CS(1)
PSA(1)
PS2, PS1, PS0(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register
(Section 6.4).
2: The prescaler is shared with the Watchdog Timer (Figure 8-6).
FIGURE 8-2:
ELECTRICAL STRUCTURE OF T0CKI PIN
RIN
T0CKI
pin
(1)
VSS
N
(1)
Schmitt Trigger
Input Buffer
VSS
Note 1: ESD protection circuits.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 37
PIC16C5X
FIGURE 8-3:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
T0
Timer0
T0+1
Instruction
Executed
FIGURE 8-4:
PC
(Program
Counter)
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
MOVF TMR0,W
NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
NT0+2
Read TMR0
reads NT0 + 2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
PC+1
MOVWF TMR0
T0
PC+3
PC+4
MOVF TMR0,W
PC+5
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
TABLE 8-1:
PC+2
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+1
Instruction
Execute
Address
PC+3
TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2
Instruction
Fetch
Timer0
PC+2
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
REGISTERS ASSOCIATED WITH TIMER0
Name
01h
TMR0
N/A
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
xxxx xxxx
uuuu uuuu
PSA
PS2
PS1
PS0
--11 1111
--11 1111
Timer0 - 8-bit real-time clock/counter
—
—
T0CS
T0SE
Value on
MCLR and
WDT Reset
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells not used by Timer0.
DS30453E-page 38
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
8.1
Using Timer0 with an External
Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the
desired device.
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
8.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 8-5).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 20 ns) and low for
at least 2TOSC (and a small RC delay of 20 ns). Refer
to the electrical specification of the desired device.
FIGURE 8-5:
8.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 module is actually incremented. Figure 8-5 shows the delay
from the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output (1)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(3)
External Clock/Prescaler
Output After Sampling
(2)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: External clock if no prescaler selected, prescaler output otherwise.
2: The arrows indicate the points in time where sampling occurs.
3: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc (duration of Q = Tosc). Therefore,
the error in measuring the interval between two edges on Timer0 input = 4Tosc max.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 39
PIC16C5X
8.2
EXAMPLE 8-1:
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 9.2.1). For simplicity, this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler may
be used by either the Timer0 module or the WDT, but
not both. Thus, a prescaler assignment for the Timer0
module means that there is no prescaler for the WDT,
and vice-versa.
The PSA and PS bits (OPTION) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will clear
the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler
contains all '0's.
8.2.1
CLRWDT
CLRF
TMR0
MOVLW B'00xx1111’
;Clear WDT
;Clear TMR0 & Prescaler
;Last 3 instructions in
this example
OPTION
;are required only if
;desired
CLRWDT
;PS are 000 or
;001
MOVLW B'00xx1xxx’ ;Set Prescaler to
OPTION
;desired WDT rate
To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 8-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before switching the prescaler.
EXAMPLE 8-2:
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
SWITCHING PRESCALER
ASSIGNMENT
MOVLW
The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 8-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT.
DS30453E-page 40
CHANGING PRESCALER
(TIMER0WDT)
B'xxxx0xxx'
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
OPTION
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 8-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = FOSC/4)
Data Bus
0
T0CKI
pin
1
8
M
U
X
1
M
U
X
0
Sync
2
Cycles
TMR0 reg
T0SE
T0CS
PSA
0
Watchdog
Timer
M
U
X
1
8-bit Prescaler
8
8 - to - 1MUX
PS
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS are bits in the OPTION register.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 41
PIC16C5X
NOTES:
DS30453E-page 42
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC16C5X family of microcontrollers have a host of such features intended to maximize system reliability, minimize cost through
elimination of external components, provide power saving operating modes and offer code protection. These
features are:
•
•
•
•
•
•
•
•
Oscillator Selection (Section 4.0)
RESET (Section 5.0)
Power-On Reset (Section 5.1)
Device Reset Timer (Section 5.2)
Watchdog Timer (WDT) (Section 9.2)
SLEEP (Section 9.3)
Code protection (Section 9.4)
ID locations (Section 9.5)
The PIC16C5X Family has a Watchdog Timer which
can be shut off only through configuration bit WDTE. It
runs off of its own RC oscillator for added reliability.
There is an 18 ms delay provided by the Device Reset
Timer (DRT), intended to keep the chip in RESET until
the crystal oscillator is stable. With this timer on-chip,
most applications need no external RESET circuitry.
The SLEEP mode is designed to offer a very low current Power-down mode. The user can wake up from
SLEEP through external RESET or through a Watchdog Timer time-out. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 43
PIC16C5X
9.1
Configuration Bits
Configuration bits can be programmed to select various
device configurations. Two bits are for the selection of
the oscillator type and one bit is the Watchdog Timer
enable bit. Nine bits are code protection bits for the
PIC16C54A,
PIC16CR54A,
PIC16C54C,
PIC16CR54C,
PIC16C55A,
PIC16C56A,
PIC16CR56A,
PIC16C57C,
PIC16CR57C,
REGISTER 9-1:
CP
CP
PIC16C58B, and PIC16CR58B devices (Register 9-1).
One bit is for code protection for the PIC16C54,
PIC16C55, PIC16C56 and PIC16C57 devices
(Register 9-2).
QTP or ROM devices have the oscillator configuration
programmed at the factory and these parts are tested
accordingly (see "Product Identification System" diagrams in the back of this data sheet).
CONFIGURATION WORD FOR PIC16C54A/CR54A/C54C/CR54C/C55A/C56A/
CR56A/C57C/CR57C/C58B/CR58B
CP
CP
CP
CP
CP
CP
CP
WDTE
FOSC1
FOSC0
bit 11
bit 0
bit 11-3: CP: Code Protection Bit
1 = Code protection off
0 = Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection Bit
00 = LP oscillator
01 = XT oscillator
10 = HS oscillator
11 = RC oscillator
Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to
access the configuration word.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
DS30453E-page 44
Preliminary
x = bit is unknown
1997-2013 Microchip Technology Inc.
PIC16C5X
REGISTER 9-2:
—
—
CONFIGURATION WORD FOR PIC16C54/C55/C56/C57
—
—
—
—
—
—
CP
WDTE
FOSC1
bit 11
FOSC0
bit 0
bit 11-4: Unimplemented: Read as ‘0’
bit 3:
CP: Code protection bit.
1 = Code protection off
0 = Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator selection bits(2)
00 = LP oscillator
01 = XT oscillator
10 = HS oscillator
11 = RC oscillator
Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to
access the configuration word.
2: PIC16LV54A supports XT, RC and LP oscillator only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
1997-2013 Microchip Technology Inc.
Preliminary
x = bit is unknown
DS30453E-page 45
PIC16C5X
9.2
Watchdog Timer (WDT)
both. Thus, a prescaler assignment for the Timer0
module means that there is no prescaler for the WDT,
and vice-versa.
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external components. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKIN pin. That means that the
WDT will run even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation or SLEEP, a WDT Reset or Wake-up Reset
generates a device RESET.
The PSA and PS bits (OPTION) determine
prescaler assignment and prescale ratio (Section 6.4).
The WDT has a nominal time-out period of 18 ms (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writing to the OPTION register. Thus, time-out a period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see Device Characterization).
The TO bit (STATUS) will be cleared upon a Watchdog Timer Reset (Section 6.3).
The WDT can be permanently disabled by programming the configuration bit WDTE as a '0' (Section 9.1).
Refer to the PIC16C5X Programming Specifications
(Literature Number DS30190) to determine how to
access the configuration word.
9.2.1
Under worst case conditions (VDD = Min., Temperature
= Max., WDT prescaler = 1:128), it may take several
seconds before a WDT time-out occurs.
9.2.2
WDT PROGRAMMING
CONSIDERATIONS
WDT PERIOD
The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET.
An 8-bit counter is available as a prescaler for the
Timer0 module (Section 8.2), or as a postscaler for the
Watchdog Timer (WDT), respectively. For simplicity,
this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be
used by either the Timer0 module or the WDT, but not
FIGURE 9-1:
The SLEEP instruction RESETS the WDT and the prescaler, if assigned to the WDT. This gives the maximum
SLEEP time before a WDT Wake-up Reset.
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0
1
Watchdog
Timer
M
Prescaler
U
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
EPROM Bit
To TMR0
1
0
MUX
Note:
T0CS, T0SE, PSA, PS2:PS0 are bits in the
OPTION register.
TABLE 9-1:
PSA
WDT
Time-out
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Value on
Power-On MCLR and
Reset
WDT Reset
N/A
OPTION
—
—
Tosc
Tose
PSA
PS2
PS1
PS0
--11 1111 --11 1111
Legend: u = unchanged, - = unimplemented, read as '0'. Shaded cells not used by Watchdog Timer.
DS30453E-page 46
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
9.3
Power-Down Mode (SLEEP)
9.4
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
9.3.1
SLEEP
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS) is set, the PD
bit (STATUS) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR/VPP pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level
(MCLR = VIH).
9.3.2
Program Verification/Code
Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
9.5
Microchip does not recommend code protecting windowed devices.
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code-identification numbers. These locations are not accessible
during normal execution but are readable and writable
during program/verify.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as '1's.
Note:
WAKE-UP FROM SLEEP
Microchip will assign a unique pattern
number for QTP and SQTP requests and
for ROM devices. This pattern number will
be unique and traceable to the submitted
code.
The device can wake up from SLEEP through one of
the following events:
1.
2.
An external RESET input on MCLR/VPP pin.
A Watchdog Timer Time-out Reset (if WDT was
enabled).
Both of these events cause a device RESET. The TO
and PD bits can be used to determine the cause of
device RESET. The TO bit is cleared if a WDT timeout occurred (and caused wake-up). The PD bit, which
is set on power-up, is cleared when SLEEP is invoked.
The WDT is cleared when the device wakes from
SLEEP, regardless of the wake-up source.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 47
PIC16C5X
NOTES:
DS30453E-page 48
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
10.0
INSTRUCTION SET SUMMARY
Each PIC16C5X instruction is a 12-bit word divided into
an OPCODE, which specifies the instruction type and
one or more operands which further specify the operation of the instruction. The PIC16C5X instruction set
summary in Table 10-2 groups the instructions into
byte-oriented, bit-oriented, and literal and control operations. Table 10-1 shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator is used to specify
which one of the 32 file registers in that bank is to be
used by the instruction.
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time would be 1 s. If a conditional test is true or the program counter is changed as
a result of an instruction, the instruction execution time
would be 2 s.
Figure 10-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal number:
The destination designator specifies where the result of
the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
where 'h' signifies a hexadecimal digit.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Byte-oriented file register operations
0xhhh
FIGURE 10-1:
11
TABLE 10-1:
Field
OPCODE FIELD
DESCRIPTIONS
4
0
f (FILE #)
Bit-oriented file register operations
11
Register file address (0x00 to 0x1F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
The assembler will generate code with x = 0.
It is the recommended form of use for compatibility with all Microchip software tools.
d
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register 'f')
Default is d = 1
label Label name
TOS
Top of Stack
PC
Program Counter
WDT
Watchdog Timer Counter
TO
Time-out bit
PD
Power-down bit
dest
Destination, either the W register or the
specified register file location
[ ]
Options
( )
Contents
Assigned to
< >
Register bit field
In the set of
italics User defined term (font is courier)
1997-2013 Microchip Technology Inc.
5
d
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Description
f
W
b
k
x
6
OPCODE
For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.
GENERAL FORMAT FOR
INSTRUCTIONS
OPCODE
8 7
5 4
b (BIT #)
0
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTO instruction
Preliminary
11
9
8
OPCODE
0
k (literal)
k = 9-bit immediate value
DS30453E-page 49
PIC16C5X
TABLE 10-2:
Mnemonic,
Operands
INSTRUCTION SET SUMMARY
12-Bit Opcode
Description
Cycles
MSb
LSb
Status
Notes
Affected
0001 11df ffff C,DC,Z
ADDWF
f,d
Add W and f
1
1,2,4
0001 01df ffff
ANDWF
f,d
AND W with f
Z
1
2,4
0000 011f ffff
CLRF
f
Clear f
Z
1
4
0000 0100 0000
CLRW
–
Clear W
Z
1
0010 01df ffff
COMF
f, d
Complement f
Z
1
0000 11df ffff
DECF
f, d
Decrement f
Z
1
2,4
0010 11df ffff
DECFSZ
f, d
Decrement f, Skip if 0
None
1(2)
2,4
1
0010 10df ffff
INCF
f, d
Increment f
Z
2,4
1(2)
0011 11df ffff
INCFSZ
f, d
Increment f, Skip if 0
None
2,4
1
0001 00df ffff
IORWF
f, d
Inclusive OR W with f
Z
2,4
1
0010 00df ffff
MOVF
f, d
Move f
Z
2,4
1
0000 001f ffff
MOVWF
f
Move W to f
None
1,4
1
0000 0000 0000
NOP
–
No Operation
None
1
0011 01df ffff
RLF
f, d
Rotate left f through Carry
C
2,4
1
0011 00df ffff
RRF
f, d
Rotate right f through Carry
C
2,4
1
0000 10df ffff C,DC,Z
SUBWF
f, d
Subtract W from f
1,2,4
1
0011 10df ffff
SWAPF
f, d
Swap f
None
2,4
1
0001 10df ffff
XORWF
f, d
Exclusive OR W with f
Z
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
0100 bbbf ffff
None
2,4
BCF
f, b
Bit Clear f
1
0101 bbbf ffff
None
2,4
BSF
f, b
Bit Set f
1
0110 bbbf ffff
None
f, b
Bit Test f, Skip if Clear
1 (2)
BTFSC
1 (2)
0111 bbbf ffff
None
BTFSS
f, b
Bit Test f, Skip if Set
LITERAL AND CONTROL OPERATIONS
ANDLW
k
AND literal with W
1
1110 kkkk kkkk
Z
CALL
1
k
Call subroutine
2
1001 kkkk kkkk
None
CLRWDT
k
Clear Watchdog Timer
1
0000 0000 0100 TO, PD
None
GOTO
k
Unconditional branch
2
101k kkkk kkkk
Z
IORLW
k
Inclusive OR Literal with W
1
1101 kkkk kkkk
None
MOVLW
k
Move Literal to W
1
1100 kkkk kkkk
None
OPTION
k
Load OPTION register
1
0000 0000 0010
None
RETLW
k
Return, place Literal in W
2
1000 kkkk kkkk
SLEEP
–
Go into standby mode
1
0000 0000 0011 TO, PD
None
3
TRIS
f
Load TRIS register
1
0000 0000 0fff
Z
XORLW
k
Exclusive OR Literal to W
1
1111 kkkk kkkk
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for
GOTO (see Section 6.5 for more on program counter).
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and
is driven low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 5, 6 or 7 causes the contents of the W register to be written to the tristate
latches of PORTA, B or C respectively. A '1' forces the pin to a hi-impedance state and disables the output
buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS30453E-page 50
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
ADDWF
Add W and f
ANDWF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ANDWF
Operands:
0 f 31
d
Operands:
0 f 31
d
Operation:
(W) + (f) (dest)
Operation:
(W) .AND. (f) (dest)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
0001
11df
f,d
AND W with f
Encoding:
ffff
0001
f,d
01df
ffff
Description:
Add the contents of the W register
and register 'f'. If 'd' is 0 the result
is stored in the W register. If 'd' is
'1' the result is stored back in
register 'f'.
Description:
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0
the result is stored in the W register. If 'd' is '1' the result is stored
back in register 'f'.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Example:
ADDWF TEMP_REG, 0
Example:
ANDWF TEMP_REG, 1
Before Instruction
W
=
TEMP_REG =
After Instruction
W
=
TEMP_REG =
Before Instruction
W
=
TEMP_REG =
After Instruction
W
=
TEMP_REG =
0x17
0xC2
0xD9
0xC2
ANDLW
AND literal with W
Syntax:
[ label ] ANDLW
Operands:
0 k 255
Operation:
(W).AND. (k) (W)
Status Affected:
Z
Encoding:
Description:
1110
kkkk
k
kkkk
The contents of the W register are
AND’ed with the eight-bit literal 'k'.
The result is placed in the W register.
Words:
1
Cycles:
1
Example:
ANDLW H'5F'
0x17
0x02
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 31
0b7
Operation:
0 (f)
Status Affected:
None
Encoding:
Description:
0100
1
Cycles:
1
Example:
BCF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
Preliminary
bbbf
f,b
ffff
Bit 'b' in register 'f' is cleared.
Words:
Before Instruction
W
= 0xA3
After Instruction
W
= 0x03
1997-2013 Microchip Technology Inc.
0x17
0xC2
FLAG_REG,
7
0xC7
0x47
DS30453E-page 51
PIC16C5X
BSF
Bit Set f
BTFSS
Syntax:
[ label ] BSF
Syntax:
[ label ] BTFSS f,b
Operands:
0 f 31
0b7
Operands:
0 f 31
0b VDD) .................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................. ±20 mA
Max. output current sunk by any I/O pin ........................................................................................................... 25 mA
Max. output current sourced by any I/O pin ...................................................................................................... 20 mA
Max. output current sourced by a single I/O port (PORTA, B or C) .................................................................. 40 mA
Max. output current sunk by a single I/O port (PORTA, B or C)........................................................................ 50 mA
Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50 to 100 should be used when applying a “low” level to the MCLR pin rather
than pulling this pin directly to VSS.
2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 67
PIC16C5X
12.1
DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)
PIC16C54/55/56/57-RC, XT, 10, HS, LP
(Commercial)
Param
Symbol
No.
D001
VDD
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C TA +70°C for commercial
Characteristic/Device
Supply Voltage
PIC16C5X-RC
PIC16C5X-XT
PIC16C5X-10
PIC16C5X-HS
PIC16C5X-LP
Min
Typ†
Max
Units
3.0
3.0
4.5
4.5
2.5
—
—
—
—
—
6.25
6.25
5.5
5.5
6.25
V
V
V
V
V
Conditions
D002
VDR
RAM Data Retention Voltage(1)
1.5*
—
V
Device in SLEEP Mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
VSS
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 5.1 for details on
Power-on Reset
D010
IDD
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
15
3.3
3.3
10
10
20
32
mA
mA
mA
mA
mA
A
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
—
—
4.0
0.6
12
9
A
A
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
D020
IPD
*
Supply Current(2)
PIC16C5X-RC(3)
PIC16C5X-XT
PIC16C5X-10
PIC16C5X-HS
PIC16C5X-HS
PIC16C5X-LP
Power-down Current(2)
These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 68
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
12.2
DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI
(Industrial)
Param
Symbol
No.
D001
VDD
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +85°C for industrial
Characteristic/Device
Supply Voltage
PIC16C5X-RCI
PIC16C5X-XTI
PIC16C5X-10I
PIC16C5X-HSI
PIC16C5X-LPI
Min
Typ†
Max
Units
3.0
3.0
4.5
4.5
2.5
—
—
—
—
—
6.25
6.25
5.5
5.5
6.25
V
V
V
V
V
Conditions
D002
VDR
RAM Data Retention Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
VSS
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 5.1 for details on
Power-on Reset
D010
IDD
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
15
3.3
3.3
10
10
20
40
mA
mA
mA
mA
mA
A
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
—
—
4.0
0.6
14
12
A
A
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
D020
IPD
*
Supply Current(2)
PIC16C5X-RCI(3)
PIC16C5X-XTI
PIC16C5X-10I
PIC16C5X-HSI
PIC16C5X-HSI
PIC16C5X-LPI
Power-down Current(2)
These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 69
PIC16C5X
12.3
DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)
PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE
(Extended)
Param
Symbol
No.
D001
VDD
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C for extended
Characteristic/Device
Supply Voltage
PIC16C5X-RCE
PIC16C5X-XTE
PIC16C5X-10E
PIC16C5X-HSE
PIC16C5X-LPE
Min
Typ†
Max
Units
3.25
3.25
4.5
4.5
2.5
—
—
—
—
—
6.0
6.0
5.5
5.5
6.0
V
V
V
V
V
Conditions
D002
VDR
RAM Data Retention Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
VSS
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 5.1 for details on
Power-on Reset
D010
IDD
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
19
3.3
3.3
10
10
20
55
mA
mA
mA
mA
mA
A
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 16 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.25V,
WDT disabled
—
—
5.0
0.8
22
18
A
A
VDD = 3.25V, WDT enabled
VDD = 3.25V, WDT disabled
D020
IPD
*
Supply Current(2)
PIC16C5X-RCE(3)
PIC16C5X-XTE
PIC16C5X-10E
PIC16C5X-HSE
PIC16C5X-HSE
PIC16C5X-LPE
Power-down Current(2)
These parameters are characterized but not tested.
† Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 70
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
12.4
DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)
PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
DC CHARACTERISTICS
Param
Symbol
No.
D030
D040
VIL
VIH
D050
VHYS
D060
IIL
D080
D090
VOL
VOH
Characteristic/Device
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
Min
Typ†
Max
Units
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Input High Voltage
I/O ports
I/O ports
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
0.45 VDD
2.0
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
0.15 VDD*
—
—
V
Input Leakage Current(1,2)
I/O ports
–1
0.5
+1
A
MCLR
MCLR
T0CKI
OSC1
–5
—
–3
–3
—
0.5
0.5
0.5
—
+5
+3
+3
A
A
A
A
Output Low Voltage
I/O ports
OSC2/CLKOUT
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
PIC16C5X-RC
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
PIC16C5X-RC
Hysteresis of Schmitt
Trigger inputs
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
Conditions
Pin at hi-impedance
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
For all VDD(4)
4.0V < VDD 5.5V(4)
VDD > 5.5V
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
For VDD 5.5V:
VSS VPIN VDD,
pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS VPIN VDD
VSS VPIN VDD,
PIC16C5X-XT, 10, HS, LP
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C5X be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 71
PIC16C5X
12.5
DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)
DC CHARACTERISTICS
Param
Symbol
No.
D030
D040
VIL
VIH
D050
VHYS
D060
IIL
D080
D090
VOL
VOH
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C for extended
Min
Typ†
Max
Units
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
Vss
Vss
Vss
Vss
Vss
—
—
—
—
—
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
Input High Voltage
I/O ports
I/O ports
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
0.45 VDD
2.0
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD(4)
4.0V < VDD 5.5V(4)
VDD > 5.5 V
0.15 VDD*
—
—
V
Input Leakage Current (1,2)
I/O ports
–1
0.5
+1
A
MCLR
MCLR
T0CKI
OSC1
–5
—
–3
–3
—
0.5
0.5
0.5
—
+5
+3
+3
A
A
A
A
Output Low Voltage
I/O ports
OSC2/CLKOUT
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
PIC16C5X-RC
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
PIC16C5X-RC
Hysteresis of Schmitt
Trigger inputs
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
Conditions
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
For VDD 5.5 V:
VSS VPIN VDD,
pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS VPIN VDD
VSS VPIN VDD,
PIC16C5X-XT, 10, HS, LP
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C5X be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
DS30453E-page 72
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
12.6
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency
Lowercase letters (pp) and their meanings:
pp
2
to
ck CLKOUT
cy cycle time
drt device reset timer
io I/O port
Uppercase letters and their meanings:
S
F Fall
H High
I
Invalid (Hi-impedance)
L Low
FIGURE 12-1:
T
Time
mc
osc
os
t0
wdt
MCLR
oscillator
OSC1
T0CKI
watchdog timer
P
R
V
Z
Period
Rise
Valid
Hi-impedance
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54/55/56/57
Pin
CL =
CL
50 pF
for all pins and OSC2 for RC mode
0 - 15 pF for OSC2 in XT, HS or LP modes when
external clock is used to drive OSC1
VSS
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 73
PIC16C5X
12.7
Timing Diagrams and Specifications
FIGURE 12-2:
EXTERNAL CLOCK TIMING - PIC16C54/55/56/57
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 12-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57
AC Characteristics
Param
No.
1A
Symbol
FOSC
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Characteristic
Min
Typ†
Max
Units
External CLKIN Frequency(1)
DC
—
4.0
MHz XT OSC mode
DC
—
10
MHz 10 MHz mode
DC
—
20
MHz HS OSC mode (Comm/Ind)
Oscillator
Frequency(1)
Conditions
DC
—
16
MHz HS OSC mode (Ext)
DC
—
40
kHz
LP OSC mode
DC
—
4.0
MHz RC OSC mode
0.1
—
4.0
MHz XT OSC mode
4.0
—
10
MHz 10 MHz mode
4.0
—
20
MHz HS OSC mode (Comm/Ind)
4.0
—
16
MHz HS OSC mode (Ext)
DC
—
40
kHz
LP OSC mode
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453E-page 74
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
TABLE 12-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57
AC Characteristics
Param
No.
1
Symbol
TOSC
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Characteristic
External CLKIN Period(1)
Oscillator
Period(1)
Time(2)
2
Tcy
Instruction Cycle
3
TosL,
TosH
Clock in (OSC1) Low or High
Time
4
TosR,
TosF
Clock in (OSC1) Rise or Fall
Time
Min
Typ†
Max
Units
250
—
—
ns
Conditions
XT OSC mode
100
—
—
ns
10 MHz mode
50
—
—
ns
HS OSC mode (Comm/Ind)
62.5
—
—
ns
HS OSC mode (Ext)
25
—
—
s
LP OSC mode
250
—
—
ns
RC OSC mode
250
—
10,000
ns
XT OSC mode
100
—
250
ns
10 MHz mode
50
—
250
ns
HS OSC mode (Comm/Ind)
62.5
—
250
ns
HS OSC mode (Ext)
25
—
—
s
LP OSC mode
—
4/FOSC
—
—
85*
—
—
ns
XT oscillator
20*
—
—
ns
HS oscillator
2.0*
—
—
s
LP oscillator
—
—
25*
ns
XT oscillator
—
—
25*
ns
HS oscillator
—
—
50*
ns
LP oscillator
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 75
PIC16C5X
FIGURE 12-3:
CLKOUT AND I/O TIMING - PIC16C54/55/56/57
Q1
Q4
Q2
Q3
OSC1
10
11
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: Please refer to Figure 12-1 for load conditions.
TABLE 12-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57
AC Characteristics
Param
No.
10
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Symbol
Characteristic
Min
Typ†
Max
Units
15
30**
ns
TosH2ckL
OSC1 to CLKOUT(1)
—
CLKOUT(1)
—
15
30**
ns
—
5.0
15**
ns
—
5.0
15**
ns
11
TosH2ckH
OSC1 to
12
TckR
CLKOUT rise time(1)
13
TckF
CLKOUT fall time(1)
valid(1)
14
TckL2ioV
CLKOUT to Port out
15
TioV2ckH
Port in valid before CLKOUT(1)
16
TckH2ioI
Port in hold after CLKOUT(1)
valid(2)
—
—
40**
ns
0.25 TCY+30*
—
—
ns
0*
—
—
ns
17
TosH2ioV
OSC1 (Q1 cycle) to Port out
—
—
100*
ns
18
TosH2ioI
OSC1 (Q2 cycle) to Port input invalid
(I/O in hold time)
TBD
—
—
ns
19
TioV2osH
Port input valid to OSC1
(I/O in setup time)
TBD
—
—
ns
20
TioR
Port output rise time(2)
—
10
25**
ns
21
TioF
Port output fall time(2)
—
10
25**
ns
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x Tosc.
2: Please refer to Figure 12-1 for load conditions.
DS30453E-page 76
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 12-4:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING PIC16C54/55/56/57
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O pin
(Note 1)
Note 1: Please refer to Figure 12-1 for load conditions.
TABLE 12-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57
AC Characteristics
Param
No.
Symbol
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Characteristic
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
100*
—
—
ns
VDD = 5.0V
31
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
9.0*
18*
30*
ms
VDD = 5.0V (Comm)
32
TDRT
Device Reset Timer Period
9.0*
18*
30*
ms
VDD = 5.0V (Comm)
34
TioZ
I/O Hi-impedance from MCLR Low
—
—
100*
ns
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 77
PIC16C5X
FIGURE 12-5:
TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57
T0CKI
40
41
42
Note: Please refer to Figure 12-1 for load conditions.
TABLE 12-4:
TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57
AC Characteristics
Param
No.
40
Symbol
Tt0H
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Characteristic
T0CKI High Pulse Width
- No Prescaler
- With Prescaler
41
Tt0L
T0CKI Low Pulse Width
- No Prescaler
- With Prescaler
42
Tt0P
T0CKI Period
Min
Typ†
Max
Units
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
20 or TCY + 40*
N
—
—
ns
Conditions
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453E-page 78
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
13.0
ELECTRICAL CHARACTERISTICS - PIC16CR54A
Absolute Maximum Ratings(†)
Ambient Temperature under bias ..................................................................................................... –55°C to +125°C
Storage Temperature ....................................................................................................................... –65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS(1) ...................................................................................................... 0 to +14V
Voltage on all other pins with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)
Total power dissipation(2) ............................................................................................................................... 800 mW
Max. current out of VSS pin ............................................................................................................................. 150 mA
Max. current into VDD pin .................................................................................................................................. 50 mA
Max. current into an input pin (T0CKI only) 500 A
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD) 20 mA
Max. output current sunk by any I/O pin ........................................................................................................... 25 mA
Max. output current sourced by any I/O pin ...................................................................................................... 20 mA
Max. output current sourced by a single I/O port (PORTA or B) ....................................................................... 40 mA
Max. output current sunk by a single I/O port (PORTA or B) ............................................................................ 50 mA
Note 1: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus,
a series resistor of 50 to 100 should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to Vss.
2: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 79
PIC16C5X
13.1
DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)
PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
PIC16LCR54A-04
PIC16LCR54A-04I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
PIC16CR54A-04, 10, 20
PIC16CR54A-04I, 10I, 20I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
Param
No.
Symbol
VDD
D001
D001
D001A
Characteristic/Device
Min
Typ†
Max
Units
Conditions
Supply Voltage
PIC16LCR54A
2.0
—
6.25
V
PIC16CR54A
2.5
4.5
—
—
6.25
5.5
V
V
RC and XT modes
HS mode
D002
VDR
RAM Data Retention
Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
VSS
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 5.1 for details on
Power-on Reset
—
—
10
—
20
70
A
A
IDD
D005
Supply Current(2)
PICLCR54A
D005A
PIC16CR54A
—
—
—
2.0
0.8
90
3.6
1.8
350
mA
mA
A
—
—
4.8
9.0
10
20
mA
mA
Fosc = 32 kHz, VDD = 2.0V
Fosc = 32 kHz, VDD = 6.0V
RC(3) and XT modes:
FOSC = 4.0 MHz, VDD = 6.0V
FOSC = 4.0 MHz, VDD = 3.0V
FOSC = 200 kHz, VDD = 2.5V
HS mode:
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 80
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
13.1
DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)
PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
PIC16LCR54A-04
PIC16LCR54A-04I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
PIC16CR54A-04, 10, 20
PIC16CR54A-04I, 10I, 20I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
Param
No.
Symbol
IPD
D006
D006A
D007
D007A
Characteristic/Device
Min
Typ†
Max
Units
Conditions
PIC16LCR54A-Commercial
—
—
—
—
1.0
2.0
3.0
5.0
6.0
8.0*
15
25
A
A
A
A
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
PIC16CR54A-Commercial
—
—
—
—
1.0
2.0
3.0
5.0
6.0
8.0*
15
25
A
A
A
A
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
PIC16LCR54A-Industrial
—
—
—
—
—
1.0
2.0
3.0
3.0
5.0
8.0
10*
20*
18
45
A
A
A
A
A
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 4.0V, WDT enabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
PIC16CR54A-Industrial
—
—
—
—
—
1.0
2.0
3.0
3.0
5.0
8.0
10*
20*
18
45
A
A
A
A
A
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 4.0V, WDT enabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
Power-down Current(2)
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 81
PIC16C5X
13.2
DC Characteristics:PIC16CR54A-04E, 10E, 20E (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C for extended
PIC16CR54A-04E, 10E, 20E
(Extended)
Param
Symbol
No.
D001
VDD
Characteristic
Supply Voltage
RC, XT and LP modes
HS mode
Min
Typ†
Max
Units
3.25
4.5
—
—
6.0
5.5
V
V
Conditions
D002
VDR
RAM Data Retention Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
VSS
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure Power- 0.05*
on Reset
—
—
V/ms
See Section 5.1 for details on
Power-on Reset
D010
IDD
—
—
—
1.8
4.8
9.0
3.3
10
20
mA
mA
mA
FOSC = 4.0 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 16 MHz, VDD = 5.5V
—
—
5.0
0.8
22
18
A
A
VDD = 3.25V, WDT enabled
VDD = 3.25V, WDT disabled
D020
IPD
Supply Current(2)
RC(3) and XT modes
HS mode
HS mode
Power-down Current(2)
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design
guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode.The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 82
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
13.3
DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)
PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
DC CHARACTERISTICS
Param
Symbol
No.
D030
VIL
D040
VIH
D050
VHYS
D060
IIL
D080
VOL
D090
VOH
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
Min
Typ†
Max
Units
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
V
V
V
V
V
Input High Voltage
I/O ports
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
2.0
0.6 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.85 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
0.15 VDD*
—
—
V
Input Leakage Current(1,2)
I/O ports
–1.0
—
+1.0
A
MCLR
MCLR
T0CKI
OSC1
–5.0
—
–3.0
–3.0
—
0.5
0.5
0.5
—
+5.0
+3.0
+3.0
A
A
A
A
—
—
—
—
0.5
0.5
V
V
IOL = 10 mA, VDD = 6.0V
IOL = 1.9 mA, VDD = 6.0V,
RC mode only
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOH = –4.0 mA, VDD = 6.0V
IOH = –0.8 mA, VDD = 6.0V,
RC mode only
Hysteresis of Schmitt
Trigger inputs
Output Low Voltage
I/O ports
OSC2/CLKOUT
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
Conditions
Pin at hi-impedance
RC mode only(3)
XT, HS and LP modes
VDD = 3.0V to 5.5V(4)
Full VDD range(4)
RC mode only(3)
XT, HS and LP modes
For VDD 5.5V:
VSS VPIN VDD,
pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS VPIN VDD
VSS VPIN VDD,
XT, HS and LP modes
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 83
PIC16C5X
13.4
DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)
DC CHARACTERISTICS
Param
Symbol
No.
D030
VIL
D040
VIH
D050
VHYS
D060
IIL
D080
VOL
D090
VOH
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C for extended
Min
Typ†
Max
Units
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
Vss
Vss
Vss
Vss
Vss
—
—
—
—
—
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
Input High Voltage
I/O ports
I/O ports
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
0.45 VDD
2.0
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD(4)
4.0V < VDD 5.5V(4)
VDD > 5.5V
0.15 VDD*
—
—
V
Input Leakage Current(1,2)
I/O ports
–1.0
0.5
+1.0
A
MCLR
MCLR
T0CKI
OSC1
–5.0
—
–3.0
–3.0
—
0.5
0.5
0.5
—
+5.0
+3.0
+3.0
A
A
A
A
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC mode only
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
RC mode only
Hysteresis of Schmitt
Trigger inputs
Output Low Voltage
I/O ports
OSC2/CLKOUT
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
Conditions
RC mode only(3)
XT, HS and LP modes
RC mode only(3)
XT, HS and LP modes
For VDD 5.5V:
VSS VPIN VDD,
pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS VPIN VDD
VSS VPIN VDD,
XT, HS and LP modes
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
DS30453E-page 84
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
13.5
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency
Lowercase letters (pp) and their meanings:
pp
2 to
ck CLKOUT
cy cycle time
drt device reset timer
io I/O port
Uppercase letters and their meanings:
S
F Fall
H High
I
Invalid (Hi-impedance)
L
Low
FIGURE 13-1:
T
Time
mc
osc
os
t0
wdt
MCLR
oscillator
OSC1
T0CKI
watchdog timer
P
R
V
Z
Period
Rise
Valid
Hi-impedance
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16CR54A
Pin
CL = 50 pF
CL
0 -15 pF
for all pins and OSC2 for RC modes
for OSC2 in XT, HS or LP modes when
external clock is used to drive OSC1
VSS
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 85
PIC16C5X
13.6
Timing Diagrams and Specifications
FIGURE 13-2:
EXTERNAL CLOCK TIMING - PIC16CR54A
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 13-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A
AC Characteristics
Param
No.
Symbol
FOSC
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Characteristic
External CLKIN Frequency(1)
(1)
Oscillator Frequency
Min
Typ†
Max
Units
Conditions
DC
—
4.0
MHz XT OSC mode
DC
—
4.0
MHz HS OSC mode (04)
DC
—
10
MHz HS OSC mode (10)
DC
—
20
MHz HS OSC mode (20)
DC
—
200
kHz LP OSC mode
DC
—
4.0
MHz RC OSC mode
0.1
—
4.0
MHz XT OSC mode
4.0
—
4.0
MHz HS OSC mode (04)
4.0
—
10
MHz HS OSC mode (10)
4.0
—
20
MHz HS OSC mode (20)
5.0
—
200
kHz LP OSC mode
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453E-page 86
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
TABLE 13-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A
AC Characteristics
Param
No.
Symbol
1
TOSC
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
–40°C TA +125°C for extended
Characteristic
External CLKIN Period(1)
Oscillator Period(1)
2
3
4
Tcy
(2)
Instruction Cycle Time
TosL, TosH Clock in (OSC1) Low or High
Time
TosR, TosF Clock in (OSC1) Rise or Fall
Time
Min
Typ†
Max
Units
Conditions
250
—
—
ns
XT OSC mode
250
—
—
ns
HS OSC mode (04)
100
—
—
ns
HS OSC mode (10)
50
—
—
ns
HS OSC mode (20)
5.0
—
—
s
LP OSC mode
250
—
—
ns
RC OSC mode
250
—
10,000
ns
XT OSC mode
250
—
250
ns
HS OSC mode (04)
100
—
250
ns
HS OSC mode (10)
50
—
250
ns
HS OSC mode (20)
5.0
—
200
s
LP OSC mode
—
4/FOSC
—
—
50*
—
—
ns
XT oscillator
20*
—
—
ns
HS oscillator
2.0*
—
—
s
LP oscillator
—
—
25*
ns
XT oscillator
—
—
25*
ns
HS oscillator
—
—
50*
ns
LP oscillator
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 87
PIC16C5X
FIGURE 13-3:
CLKOUT AND I/O TIMING - PIC16CR54A
Q1
Q4
Q2
Q3
OSC1
10
11
CLKOUT
13
12
18
19
16
14
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: Please refer to Figure 13.1 for load conditions.
TABLE 13-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A
AC Characteristics
Param
No.
Symbol
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70C for commercial
–40C TA +85C for industrial
–40C TA +125C for extended
Characteristic
Min
Typ†
Max
Units
10
TosH2ckL
OSC1 to CLKOUT(1)
—
15
30**
ns
11
TosH2ckH
OSC1 to CLKOUT(1)
—
15
30**
ns
—
5.0
15**
ns
—
5.0
15**
ns
12
13
TckR
TckF
(1)
CLKOUT rise time
(1)
CLKOUT fall time
(1)
14
TckL2ioV
CLKOUT to Port out valid
15
TioV2ckH
Port in valid before CLKOUT(1)
16
TckH2ioI
Port in hold after CLKOUT(1)
(2)
—
—
40**
ns
0.25 TCY+30*
—
—
ns
0*
—
—
ns
—
—
100*
ns
17
TosH2ioV
OSC1 (Q1 cycle) to Port out valid
18
TosH2ioI
OSC1 (Q2 cycle) to Port input invalid
(I/O in hold time)
TBD
—
—
ns
19
TioV2osH
Port input valid to OSC1
(I/O in setup time)
TBD
—
—
ns
20
TioR
Port output rise time(2)
—
10
25**
ns
21
TioF
Port output fall time(2)
—
10
25**
ns
*
**
These parameters are characterized but not tested.
These parameters are design targets and are not tested. No characterization data available at this time.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
2: Please refer to Figure 13.1 for load conditions.
DS30453E-page 88
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 13-4:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: Please refer to Figure 13.1 for load conditions.
TABLE 13-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70°C for commercial
AC Characteristics
–40C TA +85C for industrial
–40C TA +125C for extended
Param
No.
Symbol
30
Characteristic
Min
Typ†
Max
Units
TmcL
MCLR Pulse Width (low)
1.0*
—
—
s
VDD = 5.0V
31
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7.0*
18*
40*
ms
VDD = 5.0V (Comm)
32
TDRT
Device Reset Timer Period
7.0*
18*
30*
ms
VDD = 5.0V (Comm)
34
TioZ
I/O Hi-impedance from MCLR Low
—
—
1.0*
s
*
Conditions
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 89
PIC16C5X
FIGURE 13-5:
TIMER0 CLOCK TIMINGS - PIC16CR54A
T0CKI
40
41
42
Note: Please refer to Figure 13.1 for load conditions.
TABLE 13-4:
TIMER0 CLOCK REQUIREMENTS - PIC16CR54A
AC Characteristics
Param
Symbol
No.
40
Tt0H
41
Tt0L
42
Tt0P
*
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
–40C TA +125C for extended
Characteristic
Min
T0CKI High Pulse Width
- No Prescaler
- With Prescaler
T0CKI Low Pulse Width
- No Prescaler
- With Prescaler
T0CKI Period
Typ† Max Units
0.5 TCY + 20*
10*
—
—
—
—
ns
ns
0.5 TCY + 20*
10*
20 or TCY + 40*
N
—
—
—
—
—
—
ns
ns
ns
Conditions
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453E-page 90
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
14.0
DEVICE CHARACTERIZATION - PIC16C54A
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range) and therefore outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean
– 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 14-1:
TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
Frequency normalized to +25C
FOSC (25C)
1.10
REXT 10k
CEXT = 100 pF
1.08
1.06
1.04
1.02
1.00
0.98
VDD = 5.5V
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(C)
TABLE 14-1:
RC OSCILLATOR FREQUENCIES
Average
FOSC @ 5 V, 25C
CEXT
REXT
20 pF
3.3K
5 MHz
27%
5K
3.8 MHz
21%
10K
2.2 MHz
21%
100K
262 kHz
31%
3.3K
1.6 MHz
13%
100 pF
300 pF
5K
1.2 MHz
13%
10K
684 kHz
18%
100K
71 kHz
25%
3.3K
660 kHz
10%
5.0K
484 kHz
14%
10K
267 kHz
15%
100K
29 kHz
19%
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is 3 standard deviations from the average value for VDD = 5V.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 91
PIC16C5X
FIGURE 14-2:
TYPICAL RC OSC
FREQUENCY vs. VDD,
CEXT = 20 PF
FIGURE 14-3:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
TYPICAL RC OSC
FREQUENCY vs. VDD,
CEXT = 100 PF
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
5.5
1.8
R = 3.3K
R = 3.3K
5.0
1.6
4.5
1.4
R = 5K
4.0
Fosc (MHz)
3.5
Fosc (MHz)
R = 5K
1.2
3.0
R = 10K
1.0
0.8
R = 10K
2.5
0.6
Measured on DIP Packages, T = 25C
2.0
0.4
Measured on DIP Packages, T = 25C
1.5
0.2
R = 100K
1.0
0.0
3.0
R = 100K
0.5
0.0
3.0
3.5
4.0
4.5
5.0
5.5
3.5
4.0
4.5
5.0
VDD (Volts)
5.5
6.0
6.0
VDD (Volts)
DS30453E-page 92
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 14-4:
TYPICAL RC OSC
FREQUENCY vs. VDD,
CEXT = 300 PF
TYPICAL IPD vs. VDD,
WATCHDOG DISABLED
FIGURE 14-5:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.5
800
700
2.0
R = 3.3K
T = 25C
600
1.5
Fosc (kHz)
IPD (A)
R = 5K
500
1.0
400
0.5
R = 10K
300
200
0.0
2.5
Measured on DIP Packages, T = 25C
3.0
3.5
4.0
4.5
5.0
5.5 6.0
VDD (Volts)
100
R = 100K
0
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
1997-2013 Microchip Technology Inc.
5.5
6.0
Preliminary
DS30453E-page 93
PIC16C5X
FIGURE 14-6:
MAXIMUM IPD vs. VDD,
WATCHDOG DISABLED
MAXIMUM IPD vs. VDD,
WATCHDOG ENABLED
FIGURE 14-8:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
60
100
50
+125°C
10
+85°C
40
+70°C
–55C
Ipd (A)
0°C
+85C
30
1
IPD (A)
–40°C
–55°C
+125C
–40C
+70C
20
0C
10
0
2.5 3.0
3.5
4.0
4.5 5.0
5.5 6.0
6.5
0
2.5
7.0
VDD (Volts)
FIGURE 14-7:
TYPICAL IPD vs. VDD,
WATCHDOG ENABLED
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.0
3.5
4.0 4.5 5.0
VDD (Volts)
5.5
6.0
6.5 7.0
IPD, with WDT enabled, has two components:
The leakage current, which increases with higher temperature, and the operating current of the WDT logic, which
increases with lower temperature. At –40C, the latter
dominates explaining the apparently anomalous behavior.
20
18
16
14
T = 25C
IPD (A)
12
10
8
6
4
2
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30453E-page 94
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 14-9:
VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.00
1.80
–40
M ax (
VTH (Volts)
1.60
1.40
C to +
2
Typ (+
85 C )
5 C )
1.20
1.00
40
Min (–
C to +
8 5 C )
0.80
0.60
2.5
3.0
3.5
4.0
4.5
5.5
5.0
6.0
VDD (Volts)
FIGURE 14-10:
VIH, VIL OF MCLR, T0CKI AND OSC1 (RC MODE) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
4.5
4.0
VIH, VIL (Volts)
3.5
VIH
m
3.0
to
40C
ax (–
VIH
+ 25
)
C
)
5C
to +8
C
(–40
min
VIH
2.5
typ
C
+85
2.0
to +85C)
VIL max (–40C
VIH typ +25C
1.5
1.0
0.5
VIL min (–40C to +85
C)
0.0
2.5
Note:
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
These input pins have Schmitt Trigger input buffers.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 95
PIC16C5X
FIGURE 14-11:
VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(XT, HS, AND LP MODES) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.4
3.2
3.0
2.8
VTH (Volts)
2.6
Ma x
2.4
(–40
o+
C t
(
Typ
2.2
+ 25
2.0
M in
1.8
(–
85
C)
C)
Ct
40
o +8
5 C
)
1.6
1.4
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 14-12:
TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10
IDD (mA)
1.0
0.1
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10K
100K
1M
10M
100M
External Clock Frequency (Hz)
DS30453E-page 96
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 14-13:
MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, –40C TO +85C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10
IDD (mA)
1.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
0.1
3.0
2.5
0.01
10K
100K
1M
10M
100M
External Clock Frequency (Hz)
MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55C TO +125C)
FIGURE 14-14:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10
IDD (mA)
1.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.1
0.01
10K
100K
1M
10M
100M
External Clock Frequency (Hz)
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 97
PIC16C5X
FIGURE 14-15:
WDT TIMER TIME-OUT
PERIOD vs. VDD(1)
FIGURE 14-16:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
TRANSCONDUCTANCE
(gm) OF HS OSCILLATOR
vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
50
9000
45
8000
Max –40C
40
7000
6000
30
Max +85C
gm (A/V)
WDT period (ms)
35
25
Max +70C
5000
Typ +25C
4000
20
Typ +25C
3000
15
Min +85C
MIn 0C
2000
10
MIn –40C
5
2.0
3.0
4.0
5.0
6.0
100
7.0
0
VDD (Volts)
2.0
Note 1: Prescaler set to 1:1.
DS30453E-page 98
3.0
4.0
5.0
6.0
7.0
VDD (Volts)
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 14-17:
TRANSCONDUCTANCE
(gm) OF LP OSCILLATOR
vs. VDD
FIGURE 14-18:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
TRANSCONDUCTANCE
(gm) OF XT OSCILLATOR
vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
45
2500
40
Max –40C
Max –40C
2000
35
30
25
gm (A/V)
gm (A/V)
1500
Typ +25C
20
Typ +25C
1000
15
Min +85C
500
10
Min +85C
5
0
2.0
0
2.0
3.0
4.0
5.0
6.0
7.0
3.0
4.0
5.0
6.0
7.0
VDD (Volts)
VDD (Volts)
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 99
PIC16C5X
FIGURE 14-19:
PORTA, B AND C IOH vs.
VOH, VDD = 3 V
PORTA, B AND C IOH vs.
VOH, VDD = 5 V
FIGURE 14-20:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
0
0
Min +85C
–5
–10
–10
IOH (mA)
IOH (mA)
Min +85C
Typ +25C
–20
Typ +25C
–15
Max –40C
–30
Max –40C
–20
–40
–25
1.5
0
0.5
1.0
1.5
2.0
2.5
2.5
3.0
3.5
4.0
4.5
5.0
VOH (Volts)
VOH (Volts)
DS30453E-page 100
2.0
3.0
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 14-21:
PORTA, B AND C IOL vs.
VOL, VDD = 3 V
FIGURE 14-22:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
PORTA, B AND C IOL vs.
VOL, VDD = 5 V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
45
90
Max –40C
40
Max –40C
80
35
70
30
60
25
50
IOL (mA)
IOL (mA)
Typ +25C
Typ +25C
20
40
Min +85C
15
30
Min +85C
10
20
5
10
0
0.0
0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
1997-2013 Microchip Technology Inc.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
Preliminary
DS30453E-page 101
PIC16C5X
TABLE 14-2:
INPUT CAPACITANCE FOR
PIC16C54/56
Typical Capacitance (pF)
Pin
18L PDIP
18L SOIC
RA port
5.0
4.3
RB port
5.0
4.3
MCLR
17.0
17.0
OSC1
4.0
3.5
OSC2/CLKOUT
4.3
3.5
T0CKI
3.2
2.8
All capacitance values are typical at 25C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
TABLE 14-3:
INPUT CAPACITANCE FOR
PIC16C55/57
Typical Capacitance (pF)
Pin
28L PDIP
(600 mil)
28L SOIC
RA port
5.2
4.8
RB port
5.6
4.7
RC port
5.0
4.1
MCLR
17.0
17.0
OSC1
6.6
3.5
OSC2/CLKOUT
4.6
3.5
T0CKI
4.5
3.5
All capacitance values are typical at 25C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
DS30453E-page 102
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
15.0
ELECTRICAL CHARACTERISTICS - PIC16C54A
Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... –55°C to +125°C
Storage temperature ....................................................................................................................... –65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS.......................................................................................................... 0 to +14V
Voltage on all other pins with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Max. current out of VSS pin ............................................................................................................................. 150 mA
Max. current into VDD pin ................................................................................................................................ 100 mA
Max. current into an input pin (T0CKI only) 500 A
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Max. output current sunk by any I/O pin ........................................................................................................... 25 mA
Max. output current sourced by any I/O pin ...................................................................................................... 20 mA
Max. output current sourced by a single I/O port (PORTA or B) ....................................................................... 50 mA
Max. output current sunk by a single I/O port (PORTA or B) ............................................................................ 50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 103
PIC16C5X
15.1
DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)
PIC16C54A-04I, 10I, 20I (Industrial)
PIC16LC54A-04 (Commercial)
PIC16LC54A-04I (Industrial)
PIC16LC54A-04
PIC16LC54A-04I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
PIC16C54A-04, 10, 20
PIC16C54A-04I, 10I, 20I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
Param
Symbol
No.
VDD
D001
D001A
Characteristic/Device
Min
Typ†
Max Units
Conditions
PIC16LC54A
3.0
2.5
—
—
6.25
6.25
V
V
XT and RC modes
LP mode
PIC16C54A
3.0
4.5
—
—
6.25
5.5
V
V
RC, XT and LP modes
HS mode
Supply Voltage
D002
VDR
RAM Data Retention
Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to
ensure Power-on Reset
—
Vss
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
—
0.5
2.5
mA
—
11
27
A
—
11
35
A
—
1.8
2.4
mA
—
—
—
2.4
4.5
14
8.0
16
29
mA
mA
A
—
17
37
A
IDD
D005
D005A
V/ms See Section 5.1 for details on
Power-on Reset
Supply Current(2)
PIC16LC5X
PIC16C5X
FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
FOSC = 32 kHz, VDD = 2.5V,
WDT disabled, LP mode, Commercial
FOSC = 32 kHz, VDD = 2.5V,
WDT disabled, LP mode, Industrial
FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
FOSC = 10 MHz, VDD = 5.5V, HS mode
FOSC = 20 MHz, VDD = 5.5V, HS mode
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled, LP mode, Commercial
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled, LP mode, Industrial
Legend:
*
†
Rows with standard voltage device data only are shaded for improved readability.
These parameters are characterized but not tested.
Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and
is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 104
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
15.1
DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)
PIC16C54A-04I, 10I, 20I (Industrial)
PIC16LC54A-04 (Commercial)
PIC16LC54A-04I (Industrial)
PIC16LC54A-04
PIC16LC54A-04I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
PIC16C54A-04, 10, 20
PIC16C54A-04I, 10I, 20I
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C TA +70°C for commercial
–40°C TA +85°C for industrial
Param
Symbol
No.
IPD
Characteristic/Device
Min
Typ†
Max Units
Conditions
PIC16LC5X
—
—
—
—
2.5
0.25
2.5
0.25
12
4.0
14
5.0
A
A
A
A
VDD = 2.5V, WDT enabled, Commercial
VDD = 2.5V, WDT disabled, Commercial
VDD = 2.5V, WDT enabled, Industrial
VDD = 2.5V, WDT disabled, Industrial
PIC16C5X
—
—
—
—
4.0
0.25
5.0
0.3
12
4.0
14
5.0
A
A
A
A
VDD = 3.0V, WDT enabled, Commercial
VDD = 3.0V, WDT disabled, Commercial
VDD = 3.0V, WDT enabled, Industrial
VDD = 3.0V, WDT disabled, Industrial
Power-down Current(2)
D006
D006A
Legend:
*
†
Rows with standard voltage device data only are shaded for improved readability.
These parameters are characterized but not tested.
Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and
is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 105
PIC16C5X
15.2
DC Characteristics:
PIC16C54A-04E, 10E, 20E (Extended)
PIC16LC54A-04E (Extended)
PIC16LC54A-04E
(Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125C for extended
PIC16C54A-04E, 10E, 20E
(Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125C for extended
Param
Symbol
No.
VDD
Characteristic
Min
Typ†
Max Units
Conditions
PIC16LC54A
3.0
2.5
—
—
6.25
6.25
V
V
XT and RC modes
LP mode
PIC16C54A
3.5
4.5
—
—
5.5
5.5
V
V
RC and XT modes
HS mode
Supply Voltage
D001
D001A
D002
VDR
RAM Data Retention Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
—
0.5
25
mA
—
11
27
A
—
11
35
A
—
11
37
A
—
1.8
3.3
mA
—
4.8
10
mA
—
9.0
20
mA
IDD
D010
Supply Current(2)
PIC16LC54A
D010A
PIC16C54A
Legend:
V/ms See Section 5.1 for details on
Power-on Reset
FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
FOSC = 32 kHz, VDD = 2.5V,
LP mode, Commercial
FOSC = 32 kHz, VDD = 2.5V,
LP mode, Industrial
FOSC = 32 kHz, VDD = 2.5V,
LP mode, Extended
FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
FOSC = 10 MHz, VDD = 5.5V,
HS mode
FOSC = 20 MHz, VDD = 5.5V,
HS mode
Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 106
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
15.2
DC Characteristics:
PIC16C54A-04E, 10E, 20E (Extended)
PIC16LC54A-04E (Extended)
PIC16LC54A-04E
(Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125C for extended
PIC16C54A-04E, 10E, 20E
(Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125C for extended
Param
Symbol
No.
IPD
Characteristic
Typ†
Max Units
Conditions
—
2.5
15
A
—
0.25
7.0
A
VDD = 2.5V, WDT enabled,
Extended
VDD = 2.5V, WDT disabled,
Extended
—
—
5.0
0.8
22
18*
A
A
VDD = 3.5V, WDT enabled
VDD = 3.5V, WDT disabled
Power-down Current(2)
D020
PIC16LC54A
D020A
PIC16C54A
Legend:
Min
Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 107
PIC16C5X
15.3
DC Characteristics: PIC16LV54A-02 (Commercial)
PIC16LV54A-02I (Industrial)
PIC16LV54A-02
PIC16LV54A-02I
(Commercial, Industrial)
Param
Symbol
No.
D001
VDD
Characteristic
Supply Voltage
RC and XT modes
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–20C TA +85C for industrial
Min
Typ† Max Units
2.0
—
3.8
V
Conditions
D002
VDR
RAM Data Retention
Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
D010
IDD
Supply Current(2)
RC(3) and XT modes
LP mode, Commercial
LP mode, Industrial
—
—
—
0.5
11
14
—
27
35
mA
A
A
FOSC = 2.0 MHz, VDD = 3.0V
FOSC = 32 kHz, VDD = 2.5V WDT disabled
FOSC = 32 kHz, VDD = 2.5V WDT disabled
Power-down Current(2,4)
Commercial
Commercial
Industrial
Industrial
—
—
—
—
2.5
0.25
3.5
0.3
12
4.0
14
5.0
A
A
A
A
VDD = 2.5V, WDT enabled
VDD = 2.5V, WDT disabled
VDD = 2.5V, WDT enabled
VDD = 2.5V, WDT disabled
D020
IPD
*
†
V/ms See Section 5.1 for details on
Power-on Reset
These parameters are characterized but not tested.
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
4: The oscillator start-up time can be as much as 8 seconds for XT and LP oscillator selection on wake-up from
SLEEP mode or during initial power-up.
DS30453E-page 108
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
15.4
DC Characteristics:
PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial)
PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial)
PIC16C54A-04E, 10E, 20E, PIC16LC54A-04E (Extended)
DC CHARACTERISTICS
Param
Symbol
No.
D030
VIL
D040
VIH
D050
VHYS
D060
IIL
D080
VOL
VOH
Characteristic
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0C TA +70C for commercial
–40C TA +85C for industrial
–20C TA +85C for industrial-PIC16LV54A-02I
–40°C TA +125C for extended
Min
Typ†
Max
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
Input High Voltage
I/O ports
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
0.2 VDD + 1
2.0
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
0.15 VDD*
—
—
V
Input Leakage Current(1,2)
I/O ports
-1.0
0.5
+1.0
A
MCLR
MCLR
T0CKI
OSC1
-5.0
—
-3.0
-3.0
—
0.5
0.5
0.5
+5.0
+3.0
+3.0
—
A
A
A
A
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC mode only
VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
IOH = -5.4 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V,
RC mode only
Hysteresis of Schmitt
Trigger inputs
Output Low Voltage
I/O ports
OSC2/CLKOUT
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
Units Conditions
Pin at hi-impedance
RC mode only(3)
XT, HS and LP modes
For all VDD(4)
4.0V < VDD 5.5V(4)
RC mode only(3)
XT, HS and LP modes
For VDD 5.5V:
VSS VPIN VDD,
pin at hi-impedance
VPIN = VSS +0.25V
VPIN = VDD
VSS VPIN VDD
VSS VPIN VDD,
XT, HS and LP modes
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only
and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltage.
2: Negative current is defined as coming out of the pin.
3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be
driven with external clock in RC mode.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 109
PIC16C5X
15.5
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency
Lowercase letters (pp) and their meanings:
pp
2 to
ck CLKOUT
cy cycle time
drt device reset timer
io I/O port
Uppercase letters and their meanings:
S
F Fall
H High
I
Invalid (Hi-impedance)
L
Low
FIGURE 15-1:
T
Time
mc
osc
os
t0
wdt
MCLR
oscillator
OSC1
T0CKI
watchdog timer
P
R
V
Z
Period
Rise
Valid
Hi-impedance
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54A
Pin
CL = 50 pF
CL
for all pins and OSC2 for RC modes
0 -15 pF for OSC2 in XT, HS or LP modes when
external clock is used to drive OSC1
VSS
DS30453E-page 110
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
15.6
Timing Diagrams and Specifications
FIGURE 15-2: EXTERNAL CLOCK TIMING - PIC16C54A
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 15-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
AC Characteristics
Param
No.
Symbol
FOSC
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
–20C TA +85C for industrial - PIC16LV54A-02I
–40C TA +125C for extended
Characteristic
Min
Typ†
Max
Units
External CLKIN Frequency(1)
DC
—
4.0
MHz XT OSC mode
Oscillator Frequency(1)
Conditions
DC
—
2.0
MHz XT OSC mode (PIC16LV54A)
DC
—
4.0
MHz HS OSC mode (04)
DC
—
10
MHz HS OSC mode (10)
DC
—
20
MHz HS OSC mode (20)
DC
—
200
kHz LP OSC mode
DC
—
4.0
MHz RC OSC mode
DC
—
2.0
MHz RC OSC mode (PIC16LV54A)
0.1
—
4.0
MHz XT OSC mode
0.1
—
2.0
MHz XT OSC mode (PIC16LV54A)
4.0
—
4.0
MHz HS OSC mode (04)
4.0
—
10
MHz HS OSC mode (10)
4.0
—
20
MHz HS OSC mode (20)
5.0
—
200
kHz LP OSC mode
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 111
PIC16C5X
TABLE 15-1:
EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
–20C TA +85C for industrial - PIC16LV54A-02I
–40C TA +125C for extended
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
1
TOSC
External CLKIN Period(1)
250
—
—
ns
XT OSC mode
500
—
—
ns
XT OSC mode (PIC16LV54A)
250
—
—
ns
HS OSC mode (04)
100
—
—
ns
HS OSC mode (10)
50
—
—
ns
HS OSC mode (20)
5.0
—
—
s
LP OSC mode
(1)
Oscillator Period
2
Tcy
3
Instruction Cycle Time
(2)
TosL, TosH Clock in (OSC1) Low or
High Time
4
TosR, TosF Clock in (OSC1) Rise or
Fall Time
Conditions
250
—
—
ns
RC OSC mode
500
—
—
ns
RC OSC mode (PIC16LV54A)
250
—
10,000
ns
XT OSC mode
500
—
—
ns
XT OSC mode (PIC16LV54A)
250
—
250
ns
HS OSC mode (04)
100
—
250
ns
HS OSC mode (10)
50
—
250
ns
HS OSC mode (20)
5.0
—
200
s
LP OSC mode
—
4/FOSC
—
—
85*
—
—
ns
XT oscillator
20*
—
—
ns
HS oscillator
2.0*
—
—
s
LP oscillator
—
—
25*
ns
XT oscillator
—
—
25*
ns
HS oscillator
—
—
50*
ns
LP oscillator
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453E-page 112
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 15-3:
CLKOUT AND I/O TIMING - PIC16C54A
Q1
Q4
Q2
Q3
OSC1
10
11
CLKOUT
13
12
18
19
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: Please refer to Figure 15-1 for load conditions.
TABLE 15-2:
CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A
AC Characteristics
Param
No.
Symbol
10
TosH2ckL
TosH2ckH
11
12
TckR
13
TckF
14
TckL2ioV
15
16
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
–20C TA +85C for industrial - PIC16LV54A-02I
–40C TA +125C for extended
Characteristic
Min
Typ†
Max
Units
OSC1 to CLKOUT(1)
—
15
30**
ns
(1)
—
15
30**
ns
—
5.0
15**
ns
CLKOUT fall time
—
5.0
15**
ns
CLKOUT to Port out valid(1)
—
—
40**
ns
0.25 TCY+30*
—
—
ns
0*
—
—
ns
OSC1 to CLKOUT
(1)
CLKOUT rise time
(1)
(1)
TioV2ckH
Port in valid before CLKOUT
TckH2ioI
(1)
Port in hold after CLKOUT
(2)
17
TosH2ioV
OSC1 (Q1 cycle) to Port out valid
—
—
100*
ns
18
TosH2ioI
OSC1 (Q2 cycle) to Port input invalid
(I/O in hold time)
TBD
—
—
ns
19
TioV2osH
Port input valid to OSC1
(I/O in setup time)
TBD
—
—
ns
20
TioR
—
10
25**
ns
—
10
25**
ns
21
TioF
Port output rise time(2)
(2)
Port output fall time
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
†
Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
2: Please refer to Figure 15-1 for load conditions.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 113
PIC16C5X
FIGURE 15-4:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54A
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: Please refer to Figure 15-1 for load conditions.
TABLE 15-3:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
AC Characteristics
–40C TA +85C for industrial
–20C TA +85C for industrial - PIC16LV54A-02I
–40C TA +125C for extended
Param
No.
Symbol
30
TmcL
31
Min
Typ†
Max
Units
Conditions
MCLR Pulse Width (low)
100*
1
—
—
—
—
ns
s
VDD = 5.0V
VDD = 5.0V (PIC16LV54A only)
Twdt
Watchdog Timer Time-out
Period (No Prescaler)
9.0*
18*
30*
ms
VDD = 5.0V (Comm)
32
TDRT
Device Reset Timer Period
9.0*
18*
30*
ms
VDD = 5.0V (Comm)
34
TioZ
I/O Hi-impedance from MCLR
Low
—
—
—
—
100*
1s
ns
—
(PIC16LV54A only)
*
Characteristic
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453E-page 114
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 15-5:
TIMER0 CLOCK TIMINGS - PIC16C54A
T0CKI
40
41
42
Note: Please refer to Figure 15-1 for load conditions.
TABLE 15-4:
TIMER0 CLOCK REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
–20C TA +85C for industrial - PIC16LV54A-02I
–40C TA +125C for extended
AC Characteristics
Param
Symbol
No.
40
41
42
Tt0H
Tt0L
Tt0P
Characteristic
Min
T0CKI High Pulse Width
- No Prescaler
- With Prescaler
T0CKI Low Pulse Width
- No Prescaler
- With Prescaler
T0CKI Period
Typ† Max Units
0.5 TCY + 20*
10*
—
—
—
—
ns
ns
0.5 TCY + 20*
10*
20 or TCY + 40*
N
—
—
—
—
—
—
ns
ns
ns
Conditions
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 115
PIC16C5X
NOTES:
DS30453E-page 116
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
16.0
DEVICE CHARACTERIZATION - PIC16C54A
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range) and therefore outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean
– 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 16-1:
TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
Fosc
Frequency normalized to +25C
Fosc (25C)
1.10
REXT 10 kW
1.08
CEXT = 100 pF
1.06
1.04
1.02
1.00
0.98
VDD = 5.5V
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0
20
10
25
30
40
50
70
60
T(C)
TABLE 16-1:
RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5 V, 25C
CEXT
REXT
20 pF
3.3K
5 MHz
27%
5K
3.8 MHz
21%
10K
2.2 MHz
21%
100K
262 kHz
31%
3.3K
1.6 MHz
13%
100 pF
300 pF
5K
1.2 MHz
13%
10K
684 kHz
18%
100K
71 kHz
25%
3.3K
660 kHz
10%
5.0K
484 kHz
14%
10K
267 kHz
15%
100K
29 kHz
19%
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is 3 standard deviation from average value for VDD = 5V.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 117
PIC16C5X
FIGURE 16-2:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
6
R=3.3K
5
R=5K
FOSC (MHz)
4
3
R=10K
2
1
R=100K
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 16-3:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
R=3.3K
6
5
R=5K
FOSC (MHz)
4
3
R=10K
2
1
R=100K
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (Volts)
DS30453E-page 118
Preliminary
1997-2013 Microchip Technology Inc.
6.0
PIC16C5X
FIGURE 16-4:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
700
R=3.3K
600
500
FOSC (kHz)
R=5K
400
300
R=10K
200
100
R=100K
0
2.5
3.0
1997-2013 Microchip Technology Inc.
3.5
4.0
4.5
VDD (Volts)
Preliminary
5.0
5.5
6.0
DS30453E-page 119
PIC16C5X
FIGURE 16-5:
TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.5
2.0
IPD (A)
1.5
1.0
0.5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 16-6:
TYPICAL IPD VS. VDD, WATCHDOG ENABLED (25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
25.00
20.00
15.00
10.00
5.00
0.00
2.5
3
3.5
4
4.5
5
5.5
6
VDD (Volts)
DS30453E-page 120
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 16-7:
VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS - VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.0
1.8
–4
M ax (
VTH (Volts)
1.6
1.4
0C to
2
Typ (+
+ 85 C
)
5 C )
1.2
1.0
4
Min (–
0C to
+ 8 5 C
)
0.8
0.6
2.5
3.0
3.5
4.0
4.5
5.5
5.0
6.0
VDD (Volts)
FIGURE 16-8:
VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP
MODES) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.4
3.2
3.0
2.8
VTH (Volts)
2.6
Ma x
2.4
0
(–4
o +8
C t
(
Typ
2.2
+ 25
C)
2.0
M in
1.8
)
5C
(– 4
to
0 C
+ 85
C)
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 121
PIC16C5X
FIGURE 16-9:
VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
4.5
4.0
VIH, VIL (Volts)
3.5
VIH
m
3.0
to
40C
ax (–
C)
+8 5
C
+25
)
typ
5C
to +8
C
(–40
min
VIH
2.5
VIH
2.0
C to +85C)
VIL max (–40
Vil typ +25C
1.5
1.0
0.5
VIL min (–40C to +8
5C)
0.0
2.5
Note:
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
These input pins have Schmitt Trigger input buffers.
DS30453E-page 122
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 16-10:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
IDD (A)
1000
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
100
10
0.1
FIGURE 16-11:
1
Freq (MHz)
10
MAXIMUM IDD vs. FREQUENCY
(WDT DISABLED, RC MODE @ 20 PF, –40C to +85C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
IDD (A)
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.1
1997-2013 Microchip Technology Inc.
1
Freq (MHz)
Preliminary
10
DS30453E-page 123
PIC16C5X
FIGURE 16-12:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
IDD (A)
1000
100
10
0.01
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
1
0.1
10
Freq (MHz)
FIGURE 16-13:
MAXIMUM IDD vs. FREQUENCY
(WDT DISABLED, RC MODE @ 100 PF, –40C to +85C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
IDD (A)
1000
100
10
0.01
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.1
1
10
Freq (MHz)
DS30453E-page 124
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 16-14:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
IDD (A)
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01
FIGURE 16-15:
0.1
Freq (MHz)
1
MAXIMUM IDD vs. FREQUENCY
(WDT DISABLED, RC MODE @ 300 PF, –40C to +85C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
IDD (A)
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01
1997-2013 Microchip Technology Inc.
0.1
Freq (MHz)
Preliminary
1
DS30453E-page 125
PIC16C5X
FIGURE 16-16:
WDT TIMER TIME-OUT
PERIOD vs. VDD(1)
FIGURE 16-17:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
TRANSCONDUCTANCE
(gm) OF HS OSCILLATOR
vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
50
9000
45
8000
Max –40C
40
7000
6000
30
Max +85C
gm (A/W)
WDT period (ms)
35
25
Max +70C
20
5000
Typ +25C
4000
Typ +25C
3000
MIn 0C
2000
Min +85C
15
10
MIn –40C
5
2.0
3.0
4.0
5.0
6.0
100
7.0
0
2.0
VDD (Volts)
4.0
5.0
6.0
7.0
VDD (Volts)
Note 1: Prescaler set to 1:1.
DS30453E-page 126
3.0
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 16-18:
TRANSCONDUCTANCE
(gm) OF LP OSCILLATOR
vs. VDD
FIGURE 16-19:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
TRANSCONDUCTANCE
(gm) OF XT OSCILLATOR
vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2500
45
40
Max –40C
Max –40C
2000
35
30
25
gm (A/V)
gm (A/V)
1500
Typ +25C
20
Typ +25C
1000
15
Min +85C
500
10
Min +85C
5
0
0
2.0
3.0
4.0
5.0
6.0
2.0
3.0
4.0
5.0
6.0
7.0
VDD (Volts)
7.0
VDD (Volts)
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 127
PIC16C5X
FIGURE 16-20:
PORTA, B AND C IOH vs.
VOH, VDD = 3V
FIGURE 16-21: PORTA, B AND C IOH vs. VOH,
VDD = 5V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
0
0
Min +85C
–5
–10
–10
IOH (mA)
IOH (mA)
Min +85C
Typ +25C
–20
Typ +25C
–15
Max –40C
–30
Max –40C
–20
–40
–25
1.5
0
0.5
1.0
1.5
2.0
2.5
2.5
3.0
3.5
4.0
4.5
5.0
VOH (Volts)
VOH (Volts)
DS30453E-page 128
2.0
3.0
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 16-22:
PORTA, B AND C IOL vs.
VOL, VDD = 3V
FIGURE 16-23:
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
PORTA, B AND C IOL vs.
VOL, VDD = 5V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
45
90
Max –40C
40
Max –40C
80
35
70
30
60
IOL (mA)
IOL (mA)
Typ +25C
25
Typ +25C
20
50
40
Min +85C
15
30
Min +85C
10
20
5
10
0
0.0
0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
TABLE 16-2:
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
INPUT CAPACITANCE FOR
PIC16C54A/C58A
Typical Capacitance (pF)
Pin
18L PDIP
18L SOIC
RA port
5.0
4.3
RB port
5.0
4.3
MCLR
17.0
17.0
OSC1
4.0
3.5
OSC2/CLKOUT
4.3
3.5
T0CKI
3.2
2.8
All capacitance values are typical at 25C. A part-to-part
variation of 25% (three standard deviations) should be
taken into account.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 129
PIC16C5X
NOTES:
DS30453E-page 130
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
17.0
ELECTRICAL CHARACTERISTICS - PIC16LC54A
Absolute Maximum Ratings(†)
Ambient temperature under bias............................................................................................................ –55°C to +125°C
Storage temperature ............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS................................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin ...................................................................................................................................150 mA
Max. current into VDD pin ......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only) 500 A
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin ............................................................................................................20 mA
Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA
Max. output current sunk by a single I/O (Port A, B or C) .......................................................................................50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 131
PIC16C5X
FIGURE 17-1:
PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH,
0C TA +70C (COMMERCIAL TEMPS)
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 17-2:
PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH,
-40C TA 0C, +70C TA +125C (OUTSIDE OF COMMERCIAL TEMPS)
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS30453E-page 132
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
FIGURE 17-3:
PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH,
0C TA +85C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 17-4:
PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH,
-40C TA 0C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.7
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 133
PIC16C5X
17.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
PIC16LC5X
PIC16LCR5X
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
PIC16C5X
PIC16CR5X
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
Param
Symbol
No.
VDD
D001
Characteristic/Device
Min
Typ† Max Units
Conditions
Supply Voltage
PIC16LC5X
2.5
2.7
2.5
—
—
—
5.5
5.5
5.5
V
V
V
–40C TA + 85C, 16LCR5X
–40C TA 0C, 16LC5X
0C TA + 85C 16LC5X
3.0
4.5
—
—
5.5
5.5
V
V
RC, XT, LP and HS mode
from 0 - 10 MHz
from 10 - 20 MHz
PIC16C5X
D001A
D002
VDR
RAM Data Retention Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
VSS
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
V/ms
See Section 5.1 for details on
Power-on Reset
Legend:
Rows with standard voltage device data only are shaded for improved readability.
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 134
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
17.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
PIC16LC5X
PIC16LCR5X
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
PIC16C5X
PIC16CR5X
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
Param
Symbol
No.
IDD
Characteristic/Device
PIC16LC5X
D010A
*
†
Typ† Max Units
Conditions
Supply Current(2,3)
D010
Legend:
Min
PIC16C5X
—
—
0.5
11
2.4
27
mA
A
—
14
35
A
—
—
—
—
1.8
2.6
4.5
14
2.4
3.6*
16
32
mA
mA
mA
A
—
17
40
A
FOSC = 4.0 MHz, VDD = 5.5V, XT and
RC modes
FOSC = 32 kHz, VDD = 2.5V, LP mode,
Commercial
FOSC = 32 kHz, VDD = 2.5V, LP mode,
Industrial
FOSC = 4 MHz, VDD = 5.5V, XT and RC
modes
FOSC = 10 MHz, VDD = 3.0V, HS mode
FOSC = 20 MHz, VDD = 5.5V, HS mode
FOSC = 32 kHz, VDD = 3.0V, LP mode,
Commercial
FOSC = 32 kHz, VDD = 3.0V, LP mode,
Industrial
Rows with standard voltage device data only are shaded for improved readability.
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 135
PIC16C5X
17.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
PIC16LC5X
PIC16LCR5X
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
PIC16C5X
PIC16CR5X
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
–40C TA +85C for industrial
Param
Symbol
No.
IPD
D020
D020A
Legend:
Characteristic/Device
Min
Typ† Max Units
Conditions
Power-down Current(2)
PIC16LC5X
—
—
—
—
0.25
0.25
1
1.25
2
3
5
8
A
A
A
A
VDD = 2.5V, WDT disabled, Commercial
VDD = 2.5V, WDT disabled, Industrial
VDD = 2.5V, WDT enabled, Commercial
VDD = 2.5V, WDT enabled, Industrial
PIC16C5X
—
—
—
—
—
—
—
—
0.25
0.25
1.8
2.0
4
4
9.8
12
4.0
5.0
7.0*
8.0*
12*
14*
27*
30*
A
A
A
A
A
A
A
A
VDD = 3.0V, WDT disabled, Commercial
VDD = 3.0V, WDT disabled, Industrial
VDD = 5.5V, WDT disabled, Commercial
VDD = 5.5V, WDT disabled, Industrial
VDD = 3.0V, WDT enabled, Commercial
VDD = 3.0V, WDT enabled, Industrial
VDD = 5.5V, WDT enabled, Commercial
VDD = 5.5V, WDT enabled, Industrial
Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
DS30453E-page 136
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
17.2
DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E (Extended)
PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended)
PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E
PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E
(Extended)
Param
Symbol
No.
D001
VDD
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C for extended
Characteristic
Min
Typ†
Max Units
3.0
4.5
—
—
5.5
5.5
V
V
RC, XT, LP, and HS mode
from 0 - 10 MHz
from 10 - 20 MHz
Supply Voltage
Conditions
D002
VDR
RAM Data Retention Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD start voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
D010
IDD
—
—
1.8
9.0
3.3
20
mA
mA
FOSC = 4.0 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
—
—
—
—
—
—
0.3
10
12
4.8
18
26
17
50*
60*
31*
68*
90*
A
A
A
A
A
A
VDD = 3.0V, WDT disabled
VDD = 4.5V, WDT disabled
VDD = 5.5V, WDT disabled
VDD = 3.0V, WDT enabled
VDD = 4.5V, WDT enabled
VDD = 5.5V, WDT enabled
D020
IPD
Supply Current(2)
XT and RC(3) modes
HS mode
Power-down Current(2)
V/ms See Section 5.1 for details on
Power-on Reset
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in k.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 137
PIC16C5X
17.3
DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial, Extended)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial, Extended)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
Symbol
No.
D030
D040
VIL
VIH
D050
VHYS
D060
IIL
Characteristic
Min
Typ†
Max
Units
Input Low Voltage
I/O Ports
I/O Ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.8 V
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
V
4.5V VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin ............................................................................................................20 mA
Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA
Max. output current sunk by a single I/O (Port A, B or C) .......................................................................................50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 155
PIC16C5X
FIGURE 19-1:
PIC16C54C/C55A/C56A/C57C/C58B-40 VOLTAGE-FREQUENCY GRAPH,
0C TA +70C
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
0
4
10
20
25
40
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
3: Operation between 20 to 40 MHz requires the following:
• VDD between 4.5V. and 5.5V
• OSC1 externally driven
• OSC2 not connected
• HS mode
• Commercial temperatures
Devices qualified for 40 MHz operation have -40 designation (ex: PIC16C54C-40/P).
4: For operation between DC and 20 MHz, see Section 17.1.
DS30453E-page 156
Preliminary
1997-2013 Microchip Technology Inc.
PIC16C5X
19.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial)(1)
PIC16C54C/C55A/C56A/C57C/C58B-40
(Commercial)
Param
Symbol
No.
D001
VDD
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0C TA +70C for commercial
Characteristic
Supply Voltage
(2)
Min
Typ†
Max Units
Conditions
4.5
—
5.5
V
HS mode from 20 - 40 MHz
D002
VDR
RAM Data Retention Voltage
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to ensure
Power-on Reset
—
Vss
—
V
See Section 5.1 for details on
Power-on Reset
D004
SVDD
VDD Rise Rate to ensure Power- 0.05*
on Reset
—
—
D010
IDD
Supply Current(3)
—
—
5.2
6.8
12.3
16
mA
mA
FOSC = 40 MHz, VDD = 4.5V, HS mode
FOSC = 40 MHz, VDD = 5.5V, HS mode
D020
IPD
Power-down Current(3)
—
—
1.8
9.8
7.0
27*
A
A
VDD = 5.5V, WDT disabled, Commercial
VDD = 5.5V, WDT enabled, Commercial
V/ms See Section 5.1 for details on
Power-on Reset
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
Note 1: Device operation between 20 MHz to 40 MHz requires the following: VDD between 4.5V to 5.5V, OSC1 pin
externally driven, OSC2 pin not connected, HS oscillator mode and commercial temperatures. For operation
between DC and 20 MHz, See Section 19.1.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current
consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
1997-2013 Microchip Technology Inc.
Preliminary
DS30453E-page 157
PIC16C5X
DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial)(1)
19.2
DC CHARACTERISTICS
Param
Symbol
No.
D030
VIL
D040
VIH
D050
VHYS
D060
IIL
D080
VOL
D090
VOH
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C TA +70C for commercial
Characteristic
Min
Typ†
Max
Units
Input Low Voltage
I/O Ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1
VSS
VSS
VSS
VSS
—
—
—
—
0.8
0.15 VDD
0.15 VDD
0.2 VDD
V
V
V
V
4.5V
工商网监
湘ICP备2023018690号
