PIC16C62X
Data Sheet
EPROM-Based 8-Bit
CMOS Microcontrollers
2003 Microchip Technology Inc.
DS30235J
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications. No
representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patents or other
intellectual property rights arising from such use or otherwise.
Use of Microchip’s products as critical components in life
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Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Accuron, Application Maestro, dsPIC, dsPICDEM,
dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM,
fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS30235J - page ii
2003 Microchip Technology Inc.
PIC16C62X
EPROM-Based 8-Bit CMOS Microcontrollers
Devices included in this data sheet:
Referred to collectively as PIC16C62X.
•
•
•
PIC16C620A
PIC16C621A
PIC16C622A
High Performance RISC CPU:
• Only 35 instructions to learn
• All single cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 40 MHz clock input
- DC - 100 ns instruction cycle
Program
Memory
Data
Memory
PIC16C620
512
80
PIC16C620A
512
96
PIC16CR620A
512
96
PIC16C621
1K
80
PIC16C621A
1K
96
PIC16C622
2K
128
PIC16C622A
2K
128
Device
•
•
•
•
Interrupt capability
16 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative addressing modes
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
2003 Microchip Technology Inc.
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
MCLR/VPP
VSS
RB0/INT
RB1
RB2
RB3
•1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
PIC16C62X
PIC16C620
PIC16C621
PIC16C622
PIC16CR620A
PDIP, SOIC, Windowed CERDIP
PIC16C62X
•
•
•
•
Pin Diagrams
20
19
18
17
16
15
14
13
12
11
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4
SSOP
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
MCLR/VPP
VSS
VSS
RB0/INT
RB1
RB2
RB3
•1
2
3
4
5
6
7
8
9
10
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
• Four user programmable ID locations
CMOS Technology:
• Low power, high speed CMOS EPROM
technology
• Fully static design
• Wide operating range
- 2.5V to 5.5V
• Commercial, industrial and extended temperature range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
DS30235J-page 1
PIC16C62X
Device Differences
Voltage Range
Oscillator
Process Technology
(Microns)
2.5 - 6.0
See Note 1
0.9
PIC16C621
2.5 - 6.0
See Note 1
0.9
PIC16C622(3)
2.5 - 6.0
See Note 1
0.9
PIC16C620A(4)
2.7 - 5.5
See Note 1
0.7
PIC16CR620A(2)
2.5 - 5.5
See Note 1
0.7
2.7 - 5.5
See Note 1
0.7
Device
PIC16C620(3)
(3)
PIC16C621A
(4)
PIC16C622A(4)
2.7 - 5.5
See Note 1
0.7
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
2: For ROM parts, operation from 2.5V - 3.0V will require the PIC16LCR62X parts.
3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X parts.
4: For OTP parts, operations from 2.7V - 3.0V will require the PIC16LC62XA parts.
DS30235J-page 2
2003 Microchip Technology Inc.
PIC16C62X
Table of Contents
1.0
General Description .................................................................................................................................................................. 5
2.0
PIC16C62X Device Varieties .................................................................................................................................................... 7
3.0
Architectural Overview .............................................................................................................................................................. 9
4.0
Memory Organization ............................................................................................................................................................. 13
5.0
I/O Ports.................................................................................................................................................................................. 25
6.0
Timer0 Module ........................................................................................................................................................................ 31
7.0
Comparator Module ................................................................................................................................................................ 37
8.0
Voltage Reference Module ..................................................................................................................................................... 43
9.0
Special Features of the CPU .................................................................................................................................................. 45
10.0 Instruction Set Summary ........................................................................................................................................................ 61
11.0 Development Support ............................................................................................................................................................. 75
12.0 Electrical Specifications .......................................................................................................................................................... 81
13.0 Device Characterization Information ..................................................................................................................................... 109
14.0 Packaging Information .......................................................................................................................................................... 113
Appendix A: Enhancements.............................................................................................................................................................. 119
Appendix B: Compatibility ................................................................................................................................................................. 119
Index ............................................................................................................................................................................................... 121
On-Line Support ................................................................................................................................................................................ 123
Systems Information and Upgrade Hot Line ..................................................................................................................................... 123
Reader Response ............................................................................................................................................................................. 124
Product Identification System ........................................................................................................................................................... 125
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2003 Microchip Technology Inc.
DS30235J-page 3
PIC16C62X
NOTES:
DS30235J-page 4
2003 Microchip Technology Inc.
PIC16C62X
1.0
GENERAL DESCRIPTION
The PIC16C62X devices are 18 and 20-Pin ROM/
EPROM-based members of the versatile PICmicro®
family of low cost, high performance, CMOS, fullystatic, 8-bit microcontrollers.
All PICmicro microcontrollers employ an advanced
RISC architecture. The PIC16C62X devices have
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.
PIC16C62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C620A, PIC16C621A and PIC16CR620A
have 96 bytes of RAM. The PIC16C622(A) has 128
bytes of RAM. Each device has 13 I/O pins and an 8bit timer/counter with an 8-bit programmable prescaler.
In addition, the PIC16C62X adds two analog comparators with a programmable on-chip voltage reference
module. The comparator module is ideally suited for
applications requiring a low cost analog interface (e.g.,
battery chargers, threshold detectors, white goods
controllers, etc).
customization of application programs (detection
levels, pulse generation, timers, etc.) extremely fast
and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low cost, low power, high
performance, ease of use and I/O flexibility make the
PIC16C62X very versatile.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for the PIC16C5X can be easily ported to
PIC16C62X family of devices (Appendix B). The
PIC16C62X family fills the niche for users wanting to
migrate up from the PIC16C5X family and not needing
various peripheral features of other members of the
PIC16XX mid-range microcontroller family.
1.2
Development Support
The PIC16C62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer. Third Party “C” compilers are
also available.
PIC16C62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power consumption. There are four oscillator options, of which the
single pin RC oscillator provides a low cost solution, the
LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (Power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and RESET.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost effective One-TimeProgrammable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16C62X midrange microcontroller families.
A simplified block diagram of the PIC16C62X is shown
in Figure 3-1.
The PIC16C62X series fits perfectly in applications
ranging from battery chargers to low power remote
sensors.
The
EPROM
technology
makes
2003 Microchip Technology Inc.
DS30235J-page 5
PIC16C62X
TABLE 1-1:
PIC16C62X FAMILY OF DEVICES
PIC16C620(3) PIC16C620A(1)(4) PIC16CR620A(2) PIC16C621(3) PIC16C621A(1)(4) PIC16C622(3) PIC16C622A(1)(4)
Clock
Maximum Frequency 20
of Operation (MHz)
40
20
20
40
20
40
Memory
EPROM Program
Memory
(x14 words)
512
512
1K
1K
2K
2K
512
Data Memory (bytes) 80
96
96
80
96
128
128
TMR0
TMR0
TMRO
TMR0
TMR0
TMR0
TMR0
Comparators(s)
2
2
2
2
2
2
2
Internal Reference
Voltage
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt Sources
4
4
4
4
4
4
4
I/O Pins
13
13
13
13
13
13
13
2.7-5.5
2.5-5.5
2.5-6.0
2.7-5.5
2.5-6.0
2.7-5.5
Yes
Peripherals Timer Module(s)
Features
Voltage Range (Volts) 2.5-6.0
Brown-out Reset
Yes
Yes
Yes
Yes
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
18-pin DIP,
SOIC;
SOIC;
20-pin SSOP 20-pin SSOP
Yes
Yes
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
2: For ROM parts, operation from 2.0V - 2.5V will require the PIC16LCR62XA parts.
3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X part.
4: For OTP parts, operation from 2.7V - 3.0V will require the PIC16LC62XA part.
DS30235J-page 6
2003 Microchip Technology Inc.
PIC16C62X
2.0
PIC16C62X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the Oscillator modes.
Microchip's
PICSTART
and
PRO MATE
programmers both support programming of the
PIC16C62X.
Note:
2.2
Microchip does not recommend code
protecting windowed devices.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
2003 Microchip Technology Inc.
2.3
Quick-Turnaround-Production
(QTP) Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP
devices, but with all EPROM locations and configuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.4
Serialized Quick-TurnaroundProductionSM (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
DS30235J-page 7
PIC16C62X
NOTES:
DS30235J-page 8
2003 Microchip Technology Inc.
PIC16C62X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C62X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single
cycle (200 ns @ 20 MHz) except for program branches.
The PIC16C620(A) and PIC16CR620A address
512 x 14 on-chip program memory. The PIC16C621(A)
addresses
1K x 14
program
memory.
The
PIC16C622(A) addresses 2K x 14 program memory.
All program memory is internal.
The PIC16C62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
The PIC16C62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C62X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
Addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C62X simple yet efficient. In addition, the
learning curve is reduced significantly.
2003 Microchip Technology Inc.
DS30235J-page 9
PIC16C62X
FIGURE 3-1:
BLOCK DIAGRAM
Device
Program
Memory
Data Memory
(RAM)
PIC16C620
PIC16C620A
PIC16CR620A
PIC16C621
PIC16C621A
PIC16C622
PIC16C622A
512 x 14
512 x 14
512 x 14
1K x 14
1K x 14
2K x 14
2K x 14
80 x 8
96 x 8
96 x 8
80 x 8
96 x 8
128 x 8
128 x 8
13
8
Data Bus
Program Counter
Voltage
Reference
EPROM
Program
Memory
Program
Bus
RAM
File
Registers
8-Level Stack
(13-bit)
14
RAM Addr (1)
9
Comparator
RA0/AN0
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
RA1/AN1
+
RA2/AN2/VREF
RA3/AN3
+
STATUS reg
TMR0
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
RA4/T0CKI
ALU
W reg
I/O Ports
Brown-out
Reset
PORTB
MCLR
VDD, VSS
Note 1: Higher order bits are from the STATUS register.
DS30235J-page 10
2003 Microchip Technology Inc.
PIC16C62X
TABLE 3-1:
Name
OSC1/CLKIN
PIC16C62X PINOUT DESCRIPTION
DIP/SOIC
Pin #
SSOP
Pin #
I/O/P Type
Buffer
Type
16
18
I
ST/CMOS
OSC2/CLKOUT
MCLR/VPP
Description
Oscillator crystal input/external clock source input.
15
17
O
—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
4
4
I/P
ST
Master Clear (Reset) input/programming voltage input.
This pin is an Active Low Reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
17
19
I/O
ST
Analog comparator input
RA1/AN1
18
20
I/O
ST
Analog comparator input
RA2/AN2/VREF
1
1
I/O
ST
Analog comparator input or VREF output
RA3/AN3
2
2
I/O
ST
Analog comparator input /output
3
3
I/O
ST
Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is
open drain type.
RA4/T0CKI
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT
RB0/INT can also be selected as an external
interrupt pin.
6
7
I/O
TTL/ST(1)
RB1
7
8
I/O
TTL
RB2
8
9
I/O
TTL
RB3
9
10
I/O
TTL
RB4
10
11
I/O
TTL
Interrupt-on-change pin.
RB5
11
12
I/O
TTL
Interrupt-on-change pin.
RB6
12
13
I/O
TTL/ST(2)
Interrupt-on-change pin. Serial programming clock.
RB7
13
14
I/O
TTL/ST(2)
Interrupt-on-change pin. Serial programming data.
VSS
5
5,6
P
—
Ground reference for logic and I/O pins.
VDD
14
15,16
P
—
Positive supply for logic and I/O pins.
Legend:
O = output
I/O = input/output
P = power
— = Not used
I = Input
ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
2003 Microchip Technology Inc.
DS30235J-page 11
PIC16C62X
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1
Note:
Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS30235J-page 12
2003 Microchip Technology Inc.
PIC16C62X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
The PIC16C62X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 512 x 14 (0000h - 01FFh) for the
PIC16C620(A) and PIC16CR620, 1K x 14 (0000h 03FFh) for the PIC16C621(A) and 2K x 14 (0000h 07FFh) for the PIC16C622(A) are physically
implemented. Accessing a location above these
boundaries will cause a wrap-around within the first
512 x 14 space (PIC16C(R)620(A)) or 1K x 14 space
(PIC16C621(A)) or 2K x 14 space (PIC16C622(A)).
The RESET vector is at 0000h and the interrupt vector
is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).
FIGURE 4-1:
FIGURE 4-2:
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C620/PIC16C620A/
PIC16CR620A
RESET Vector
000h
Interrupt Vector
0004
0005
On-Chip Program
Memory
PC
CALL, RETURN
RETFIE, RETLW
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C621/PIC16C621A
03FFh
13
0400h
Stack Level 1
1FFFh
Stack Level 2
FIGURE 4-3:
Stack Level 8
RESET Vector
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C622/PIC16C622A
000h
PC
CALL, RETURN
RETFIE, RETLW
Interrupt Vector
0004
0005
13
Stack Level 1
Stack Level 2
Stack Level 8
On-Chip Program
Memory
01FFh
RESET Vector
000h
Interrupt Vector
0004
0005
0200h
1FFFh
On-Chip Program
Memory
07FFh
0800h
1FFFh
2003 Microchip Technology Inc.
DS30235J-page 13
PIC16C62X
4.2
Data Memory Organization
The data memory (Figure 4-4, Figure 4-5, Figure 4-6
and Figure 4-7) is partitioned into two banks, which
contain the General Purpose Registers and the Special
Function Registers. Bank 0 is selected when the RP0
bit is cleared. Bank 1 is selected when the RP0 bit
(STATUS ) is set. The Special Function Registers
are located in the first 32 locations of each bank.
Register locations 20-7Fh (Bank0) on the
PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and
A0-BFh (Bank1) on the PIC16C622 and PIC16C622A
are General Purpose Registers implemented as static
RAM. Some Special Purpose Registers are mapped in
Bank 1.
4.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 80 x 8 in the
PIC16C620/621, 96 x 8 in the PIC16C620A/621A/
CR620A and 128 x 8 in the PIC16C622(A). Each is
accessed either directly or indirectly through the File
Select Register FSR (Section 4.4).
Addresses F0h-FFh of bank1 are implemented as
common ram and mapped back to addresses 70h-7Fh
in bank0 on the PIC16C620A/621A/622A/CR620A.
DS30235J-page 14
2003 Microchip Technology Inc.
PIC16C62X
FIGURE 4-4:
DATA MEMORY MAP FOR
THE PIC16C620/621
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
6Fh
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
CMCON
VRCON
File
Address
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
A0h
General
Purpose
Register
FIGURE 4-5:
DATA MEMORY MAP FOR
THE PIC16C622
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
CMCON
General
Purpose
Register
VRCON
General
Purpose
Register
70h
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2003 Microchip Technology Inc.
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS30235J-page 15
PIC16C62X
FIGURE 4-6:
DATA MEMORY MAP FOR THE
PIC16C620A/CR620A/621A
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
CMCON
VRCON
File
Address
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
A0h
General
Purpose
Register
FIGURE 4-7:
DATA MEMORY MAP FOR
THE PIC16C622A
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
VRCON
CMCON
General
Purpose
Register
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
6Fh
70h
7Fh
General
Purpose
Register
Bank 0
F0h
Accesses
70h-7Fh
FFh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS30235J-page 16
6Fh
70h
7Fh
General
Purpose
Register
Bank 0
F0h
Accesses
70h-7Fh
FFh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2003 Microchip Technology Inc.
PIC16C62X
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets (core and peripheral). The Special Function
Registers associated with the “core” functions are
described in this section. Those related to the operation
of the peripheral features are described in the section
of that peripheral feature.
The Special Function Registers are registers used by
the CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
SPECIAL REGISTERS FOR THE PIC16C62X
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS(1)
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
01h
TMR0
Timer0 Module’s Register
02h
PCL
Program Counter's (PC) Least Significant Byte
03h
STATUS
04h
FSR
05h
PORTA
—
—
—
RA4
RA3
RA2
RA1
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
07h-09h
Unimplemented
0Ah
PCLATH
—
0Bh
INTCON
0Ch
PIR1
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
CMCON
xxxx xxxx
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
RA0
---x 0000
---u 0000
RB0
xxxx xxxx
uuuu uuuu
C
Indirect data memory address pointer
Write buffer for upper 5 bits of program counter
—
—
---0 0000
---0 0000
—
—
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
—
CMIF
—
—
—
—
—
—
-0-- ----
-0-- ----
0Dh-1Eh Unimplemented
1Fh
xxxx xxxx
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
—
—
00-- 0000
00-- 0000
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
0000 0000
0000 0000
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
81h
OPTION
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
87h-89h
Unimplemented
8Ah
PCLATH
—
8Bh
INTCON
8Ch
PIE1
8Dh
Unimplemented
8Eh
PCON
8Fh-9Eh
Unimplemented
9Fh
VRCON
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
Program Counter's (PC) Least Significant Byte
IRP(2)
RP1(2)
RP0
TO
Indirect data memory address pointer
Write buffer for upper 5 bits of program counter
—
—
---0 0000
---0 0000
—
—
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
—
CMIE
—
—
—
—
—
—
-0-- ----
-0-- ----
—
—
—
—
—
—
POR
BOR
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
—
—
---- --0x
---- --uq
—
—
000- 0000
000- 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown,
q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during
normal operation.
2: IRP & RP1 bits are reserved; always maintain these bits clear.
2003 Microchip Technology Inc.
DS30235J-page 17
PIC16C62X
4.2.2.1
STATUS Register
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any STATUS bit. For other instructions not
affecting any STATUS bits, see the “Instruction Set
Summary”.
Note 1: The IRP and RP1 bits (STATUS)
are not used by the PIC16C62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved Reserved
IRP
RP1
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved on the PIC16C62X; always maintain this bit clear.
bit 6-5
RP: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X; always maintain this bit
clear.
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
DS30235J-page 18
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16C62X
4.2.2.2
OPTION Register
Note:
The OPTION register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
OPTION REGISTER (ADDRESS 81H)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
x = Bit is unknown
DS30235J-page 19
PIC16C62X
4.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.
REGISTER 4-3:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB pins changed state (must be cleared in software)
0 = None of the RB pins have changed state
Legend:
DS30235J-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16C62X
4.2.2.4
PIE1 Register
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 4-4:
PIE1 REGISTER (ADDRESS 8CH)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
CMIE
—
—
—
—
—
—
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
bit 5-0
Unimplemented: Read as '0'
Legend:
4.2.2.5
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
PIR1 Register
This register contains the individual flag bit for the
comparator interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 4-5:
PIR1 REGISTER (ADDRESS 0CH)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
CMIF
—
—
—
—
—
—
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
x = Bit is unknown
DS30235J-page 21
PIC16C62X
4.2.2.6
PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR Reset,
WDT Reset or a Brown-out Reset.
Note:
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR STATUS bit is a "don't
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming
BODEN
bit
in
the
Configuration word).
REGISTER 4-6:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
bit 7-2
Unimplemented: Read as '0'
bit 1
POR: Power-on Reset STATUS bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset STATUS bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
DS30235J-page 22
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16C62X
4.3
4.3.2
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 4-8 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH → PCH). The lower
example in the figure shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH →
PCH).
FIGURE 4-8:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
STACK
The PIC16C62X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
PCL
8
0
7
PC
GOTO,CALL
2
PCLATH
11
Opcode
PCLATH
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When
doing a table read using a computed GOTO method,
care should be exercised if the table location crosses a
PCL memory boundary (each 256 byte block). Refer to
the application note, “Implementing a Table Read"
(AN556).
2003 Microchip Technology Inc.
DS30235J-page 23
PIC16C62X
4.4
Indirect Addressing, INDF and
FSR Registers
EXAMPLE 4-1:
movlw
movwf
NEXT clrf
incf
btfss
goto
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no-operation (although STATUS bits may
be affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS), as shown in Figure 4-9. However, IRP
is not used in the PIC16C62X.
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,7
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
CONTINUE:
A simple program to clear RAM location 20h-7Fh using
indirect addressing is shown in Example 4-1.
FIGURE 4-9:
DIRECT/INDIRECT ADDRESSING PIC16C62X
Direct Addressing
RP1
RP0
(1)
bank select
6
from opcode
Indirect Addressing
(1)
0
IRP
7
bank select
location select
00
01
10
FSR register
0
location select
11
00h
180h
not used
Data
Memory
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7).
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
DS30235J-page 24
2003 Microchip Technology Inc.
PIC16C62X
5.0
I/O PORTS
Note:
The PIC16C62X have two ports, PORTA and PORTB.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1
PORTA and TRISA Registers
On RESET, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output
drivers. All pins have data direction bits (TRIS registers), which can configure these pins as input or output.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high impedance output and must be buffered prior
to any external load. The user must configure
TRISA bit as an input and use high impedance
loads.
A '1' in the TRISA register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the
selected pin(s).
In one of the Comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA bits must be
cleared to enable outputs to use this function.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.
FIGURE 5-1:
Data
Bus
BLOCK DIAGRAM OF
RA1:RA0 PINS
D
CK
Q
PORTA
MOVLW
0X07
;Turn comparators off and
MOVWF
CMCON
;enable pins for I/O
;functions
BSF
STATUS, RP0
;Select Bank1
MOVLW
0x1F
;Value used to initialize
MOVWF
TRISA
;Set RA as inputs
;TRISA are always
;read as '0'.
WR
TRISA
Q
I/O
Pin
WR
TRISA
CK
RD PORTA
VSS
VSS
Analog
Input Mode
RD TRISA
Schmitt Trigger
Input Buffer
Q
D
EN
D
EN
RA2
Pin
Q
TRIS Latch
Schmitt Trigger
Input Buffer
Q
P
N
VSS
Analog
Input Mode
VDD
Q
VSS
TRIS Latch
RD TRISA
VDD
CK
D
N
Q
Q
Data Latch
P
Q
CK
BLOCK DIAGRAM OF RA2 PIN
D
WR
PORTA
Data Latch
D
;Initialize PORTA by setting
;output data latches
;data direction
Data
Bus
VDD
INITIALIZING PORTA
CLRF
FIGURE 5-2:
Q
VDD
WR
PORTA
EXAMPLE 5-1:
RD PORTA
To Comparator
VROE
To Comparator
2003 Microchip Technology Inc.
VREF
DS30235J-page 25
PIC16C62X
FIGURE 5-3:
Data
Bus
BLOCK DIAGRAM OF RA3 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
PORTA
VDD
Q
CK
Data Latch
D
VDD
P
Q
RA3 Pin
N
WR
TRISA
CK
Q
VSS
VSS
TRIS Latch
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
FIGURE 5-4:
Data
Bus
BLOCK DIAGRAM OF RA4 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
PORTA
CK
Q
Data Latch
D
Q
RA4 Pin
N
WR
TRISA
CK
Q
VSS
VSS
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
DS30235J-page 26
2003 Microchip Technology Inc.
PIC16C62X
TABLE 5-1:
PORTA FUNCTIONS
Bit #
Buffer
Type
RA0/AN0
bit0
ST
Input/output or comparator input
RA1/AN1
bit1
ST
Input/output or comparator input
RA2/AN2/VREF
bit2
ST
Input/output or comparator input or VREF output
RA3/AN3
bit3
ST
Input/output or comparator input/output
bit4
ST
Input/output or external clock input for TMR0 or comparator output.
Output is open drain type.
Name
RA4/T0CKI
Function
Legend: ST = Schmitt Trigger input
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
—
—
—
RA4
RA3
RA2
RA1
RA0
---x 0000
---u 0000
—
—
TRISA
4
TRISA
3
TRISA
2
TRISA
1
TRISA ---1 1111
0
---1 1111
—
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
05h
PORTA
85h
TRISA
1Fh
CMCON C2OUT C1OUT
9Fh
VRCON
VREN
VROE
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note:
Shaded bits are not used by PORTA.
2003 Microchip Technology Inc.
DS30235J-page 27
PIC16C62X
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a High Impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (e.g., any RB pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON).
FIGURE 5-5:
RBPU
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552, “Implementing Wake-Up on Key Strokes.)
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 5-6:
BLOCK DIAGRAM OF
RB PINS
VDD
RBPU(1)
BLOCK DIAGRAM OF
RB PINS
weak
P pull-up
VCC
VDD
(1)
weak
P pull-up
Data Bus
VCC
Data Latch
D
Q
WR PORTB
Data Bus
WR PORTB
D
I/O
pin
CK Q
VSS
WR TRISB
TRIS Latch
D
Q
WR TRISB
TTL
Input
Buffer
CK Q
RD TRISB
VSS
Q
TTL
Input
Buffer
CK Q
RD TRISB
ST
Buffer
Q
RD PORTB
Latch
Q
I/O
pin
CK Q
Data Latch
D
Q
D
EN
D
RB0/INT
Set RBIF
EN
RD PORTB
From other
RB pins
Q
ST
Buffer
RD PORTB
Note 1: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION).
D
EN
RD PORTB
RB in Serial Programming mode
Note 1: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION).
DS30235J-page 28
2003 Microchip Technology Inc.
PIC16C62X
TABLE 5-3:
PORTB FUNCTIONS
Name
Bit #
Buffer Type
Function
RB0/INT
bit0
TTL/ST(1)
Input/output or external interrupt input. Internal software programmable
weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6
bit6
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock pin.
RB7
bit7
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
86h
TRISB
TRISB7
TRISB6
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
1111 1111
81h
OPTION
RBPU
INTEDG
1111 1111
1111 1111
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: u = unchanged, x = unknown
Note 1: Shaded bits are not used by PORTB.
2003 Microchip Technology Inc.
DS30235J-page 29
PIC16C62X
5.3
I/O Programming Considerations
5.3.1
EXAMPLE 5-2:
BI-DIRECTIONAL I/O PORTS
READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit0 is switched into Output mode later on,
the content of the data latch may now be unknown.
; Initial PORT settings:
;
PORTB Inputs
;
PORTB Outputs
Reading the port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
; RB7 to be latched as the pin value (High).
; PORTB have external pull-up and are not
; connected to other circuitry
;
PORT pins
----------
---------
BCF
PORTB, 7
; 01pp pppp
11pp pppp
BCF
PORTB, 6
; 10pp pppp
11pp pppp
BSF
STATUS,RP0
;
BCF
TRISB, 7
; 10pp pppp
11pp pppp
BCF
TRISB, 6
; 10pp pppp
10pp pppp
; Note that the user may have expected the pin
; values to be 00pp pppp. The 2nd BCF caused
5.3.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-7).
Therefore, care must be exercised if a write followed by a
read operation is carried out on the same I/O port. The
sequence of instructions should be such to allow the pin
voltage to stabilize (load dependent) before the next
instruction which causes that file to be read into the CPU
is executed. Otherwise, the previous state of that pin may
be read into the CPU rather than the new state. When in
doubt, it is better to separate these instructions with a NOP
or another instruction not accessing this I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
SUCCESSIVE I/O OPERATION
Q1
PC
PC
Instruction
Instruction
fetched
fetched
PORT latch
;
;
Example 5-2 shows the effect of two sequential readmodify-write instructions (ex., BCF, BSF, etc.) on an
I/O port.
FIGURE 5-7:
;
Q2
Q3 Q4
Q3
PC
PC
MOVWF,PORTB
PORTB
MOVWF
Write
to
Write to
PORTB
PORTB
Q1
Q2 Q3
Q2
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q4
Q4
Q1
Q2
Q2
Q3 Q4
Q3
PC+1
PC
+1
PC+2
PC
+2
PC+3
PC
+3
MOVF,PORTB,
PORTB,W W
MOVF
ReadPORTB
PORTB
Read
NOP
NOP
NOP
NOP
This example shows write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1
cycle to output valid.
RB
RB
Port
pin
Port pin
TTPD
PD
DS30235J-page 30
Note:
Therefore, at higher clock frequencies, a write followed by a read may
be problematic.
sampled here
sampled
here
Execute
Execute
Execute
Execute
Execute
Execute
MOVWF
MOVWF
MOVF
MOVF
NOP
NOP
PORTB
PORTB
PORTB, W
PORTB,
W
2003 Microchip Technology Inc.
PIC16C62X
6.0
TIMER0 MODULE
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 6.3 details the operation of the
prescaler.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
6.1
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON). The T0IF bit
(INTCON) must be cleared in software by the
Timer0 module interrupt service routine before reenabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP, since the timer is shut
off during SLEEP. See Figure 6-4 for Timer0 interrupt
timing.
Timer mode is selected by clearing the T0CS bit
(OPTION). In Timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 6-2 and Figure 6-3). The user can work
around this by writing an adjusted value to TMR0.
Counter mode is selected by setting the T0CS bit. In
this mode, Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
bit (OPTION). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
FIGURE 6-1:
TIMER0 Interrupt
TIMER0 BLOCK DIAGRAM
Data Bus
RA4/T0CKI
pin
FOSC/4
0
PSout
1
1
Programmable
Prescaler
0
TMR0
PSout
(2 Tcy delay)
T0SE
PS
8
Sync with
Internal
clocks
Set Flag bit T0IF
on Overflow
PSA
T0CS
Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with Watchdog Timer (Figure 6-6).
FIGURE 6-2:
PC
(Program
Counter)
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
T0
T0+1
Instruction
Executed
2003 Microchip Technology Inc.
NT0
T0+2
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0+1
Read TMR0
reads NT0
NT0+2
T0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
DS30235J-page 31
PIC16C62X
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W
Instruction
Fetch
T0+1
T0
TMR0
Instruction
Execute
Write TMR0
executed
FIGURE 6-4:
NT0+1
NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
FFh
1
T0IF bit
(INTCON)
00h
01h
02h
1
GIE bit
(INTCON)
Interrupt Latency Time(2)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3TCY, where TCY = instruction cycle time.
3: CLKOUT is available only in RC Oscillator mode.
DS30235J-page 32
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PIC16C62X
6.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 6-5:
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
6.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 6-5 shows the delay from
the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output after sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
2003 Microchip Technology Inc.
DS30235J-page 33
PIC16C62X
6.3
Prescaler
The PSA and PS bits (OPTION) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 6-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.
FIGURE 6-6:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x....etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will clear
the prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= Fosc/4)
0
T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8-to-1MUX
PS
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS are bits in the OPTION register.
DS30235J-page 34
2003 Microchip Technology Inc.
PIC16C62X
6.3.1
SWITCHING PRESCALER
ASSIGNMENT
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
RESET,
the
following
instruction
sequence
(Example 6-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.)
EXAMPLE 6-1:
1.BCF
STATUS, RP0
MOVWF
BCF
STATUS, RP0
b'xxxx0xxx'
;Select TMR0, new
;prescale value and
;clock source
OPTION_REG
STATUS, RP0
;Clear WDT
TMR0
;Clear TMR0 & Prescaler
4.BSF
STATUS, RP0
;Bank 1
5.MOVLW
'00101111’b;
;These 3 lines (5, 6, 7)
6.MOVWF
OPTION
;are required only if
;desired PS are
'00101xxx’b
;Set Postscaler to
7.CLRWDT
9.MOVWF
BSF
MOVLW
;Clear WDT and
;prescaler
;Skip if already in
;Bank 0
3.CLRF
10.BCF
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
CHANGING PRESCALER
(TIMER0→WDT)
2.CLRWDT
8.MOVLW
EXAMPLE 6-2:
;000 or 001
OPTION
;desired WDT rate
STATUS, RP0
;Return to Bank 0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
Address Name
Bit 7
01h
TMR0
Timer0 module register
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
xxxx xxxx uuuu uuuu
TRISA0 ---1 1111 ---1 1111
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note:
Shaded bits are not used by TMR0 module.
2003 Microchip Technology Inc.
DS30235J-page 35
PIC16C62X
NOTES:
DS30235J-page 36
2003 Microchip Technology Inc.
PIC16C62X
7.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The OnChip Voltage Reference (Section 8.0) can also be an
input to the comparators.
REGISTER 7-1:
The CMCON register, shown in Register 7-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 7-1.
CMCON REGISTER (ADDRESS 1Fh)
R-0
R-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
C2OUT: Comparator 2 output
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VIN-
bit 6
C1OUT: Comparator 1 output
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VIN-
bit 5-4
Unimplemented: Read as ‘0’
bit 3
CIS: Comparator Input Switch
When CM: = 001:
1 = C1 VIN- connects to RA3
0 = C1 VIN- connects to RA0
When CM = 010:
1 = C1 VIN- connects to RA3
C2 VIN- connects to RA2
0 = C1 VIN- connects to RA0
C2 VIN- connects to RA1
bit 2-0
CM: Comparator mode.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
x = Bit is unknown
DS30235J-page 37
PIC16C62X
7.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 7-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
FIGURE 7-1:
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 12-2.
Note:
Comparator interrupts should be disabled
during a Comparator mode change otherwise a false interrupt may occur.
COMPARATOR I/O OPERATING MODES
A
VIN-
A
VIN+
A
VIN-
A
VIN+
+
Off
(Read as '0')
C1
+
Off
(Read as '0')
C2
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
D
VIN-
D
VIN+
+
C1
Off
(Read as '0')
C2
Off
(Read as '0')
+
CM = 000
Comparators Reset
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
A
A
A
CM = 111
Comparators Off
VINVIN+
VINVIN+
RA0/AN0 A
+
C1OUT
C1
+
C2OUT
C2
CIS=0 VIN-
RA3/AN3 A
CIS=1 VIN+
RA1/AN1 A
CIS=0
RA2/AN2 A
CIS=1
VINVIN+
+
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
VIN-
+
D
VIN+
A
VIN-
A
VIN+
+
C1OUT
C1
+
RA0/AN0
RA3/AN3
C2OUT
C2
CM = 011
C2
C2OUT
From VREF Module
Four Inputs Multiplexed to
Two Comparators
-
C1OUT
-
CM = 100
Two Independent Comparators
C1
RA1/AN1
CM = 010
A
VIN-
D
VIN+
A
VIN-
A
VIN+
RA2/AN2
RA4 Open Drain
+
C1
C1OUT
C2
C2OUT
+
CM = 110
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
A
VIN-
A
VIN+
+
C1
Off
(Read as '0')
RA0/AN0
RA3/AN3
+
C2
C2OUT
RA1/AN1
RA2/AN2
A
CIS=0
VINCIS=1
VIN+
-
A
VIN-
-
A
VIN+
A
+
+
CM = 101
One Independent Comparator
C1
C1OUT
C2
C2OUT
CM = 001
Three Inputs Multiplexed to
Two Comparators
A = Analog Input, Port Reads Zeros Always
D = Digital Input
CIS = CMCON, Comparator Input Switch
DS30235J-page 38
2003 Microchip Technology Inc.
PIC16C62X
The code example in Example 7-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 7-1:
INITIALIZING
COMPARATOR MODULE
MOVLW
0x03
;Init comparator mode
MOVWF
CMCON
;CM = 011
CLRF
PORTA
;Init PORTA
BSF
STATUS,RP0
;Select Bank1
MOVLW
0x07
;Initialize data direction
MOVWF
TRISA
;Set RA as inputs
7.3
Comparator Reference
An external or internal reference signal may be used
depending on the comparator Operating mode. The
analog signal that is present at VIN- is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 7-2).
FIGURE 7-2:
SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
;RA as outputs
;TRISA always read ‘0’
BCF
STATUS,RP0
;Select Bank 0
CALL
DELAY 10
;10µs delay
VVININ–
-
MOVF
CMCON,F
;Read CMCON to end change condition
BCF
PIR1,CMIF
;Clear pending interrupts
VVININ+
+
BSF
STATUS,RP0
;Select Bank 1
BSF
PIE1,CMIE
;Enable comparator interrupts
BCF
STATUS,RP0
;Select Bank 0
BSF
INTCON,PEIE ;Enable peripheral interrupts
BSF
INTCON,GIE
7.2
Output
utput
;Global interrupt enable
Comparator Operation
A single comparator is shown in Figure 7-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 7-2 represent
the uncertainty due to input offsets and response time.
7.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the
comparators operate from the same or different
reference sources. However, threshold detector
applications may require the same reference. The
reference signal must be between VSS and VDD, and
can be applied to either pin of the comparator(s).
7.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 10, Instruction Sets, contains a
detailed description of the Voltage Reference Module
that provides this signal. The internal reference signal
is used when the comparators are in mode
CM=010 (Figure 7-1). In this mode, the internal
voltage reference is applied to the VIN+ pin of both
comparators.
2003 Microchip Technology Inc.
DS30235J-page 39
PIC16C62X
7.4
Comparator Response Time
7.5
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal
reference is changed, the maximum delay of the
internal voltage reference must be considered when
using the comparator outputs. Otherwise the maximum
delay of the comparators should be used (Table 12-2).
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM = 110, multiplexors in the
output path of the RA3 and RA4 pins will switch and the
output of each pin will be the unsynchronized output of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and the
response time given in the specifications. Figure 7-3
shows the comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4 pins while in this mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is
specified.
FIGURE 7-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
PORT PINS
MULTIPLEX
+
-
To RA3 or
RA4 Pin
Bus
Data
Q
RD CMCON
Set
CMIF
Bit
D
EN
Q
FROM
OTHER
COMPARATOR
D
EN
CL
RD CMCON
NRESET
DS30235J-page 40
2003 Microchip Technology Inc.
PIC16C62X
7.6
Comparator Interrupts
wake up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM = 111, before entering SLEEP.
If the device wakes up from SLEEP, the contents of the
CMCON register are not affected.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that has occurred. The
CMIF bit, PIR1, is the comparator interrupt flag.
The CMIF bit must be RESET by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
7.8
The CMIE bit (PIE1) and the PEIE bit
(INTCON) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
Note:
A device RESET forces the CMCON register to its
RESET state. This forces the comparator module to be
in the comparator RESET mode, CM = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered-down during the RESET interval.
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1)
interrupt flag may not get set.
7.9
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Comparator Operation During
SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
FIGURE 7-4:
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup may occur. A
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
7.7
Effects of a RESET
ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10K
AIN
CPIN
5 pF
VA
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend
CPIN
VT
ILEAKAGE
RIC
RS
VA
2003 Microchip Technology Inc.
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
DS30235J-page 41
PIC16C62X
TABLE 7-1:
Address
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000 00-- 0000
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000 000- 0000
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
—
CMIF
—
—
—
—
—
—
-0-- ---- -0-- ----
8Ch
PIE1
—
CMIE
—
—
—
—
—
—
-0-- ---- -0-- ----
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0 ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as "0"
DS30235J-page 42
2003 Microchip Technology Inc.
PIC16C62X
8.0
VOLTAGE REFERENCE
MODULE
8.1
The Voltage Reference can output 16 distinct voltage
levels for each range. The equations used to calculate
the output of the Voltage Reference are as follows:
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Register 8-1. The block diagram
is given in Figure 8-1.
REGISTER 8-1:
Configuring the Voltage Reference
if VRR = 1: VREF = (VR/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output (Table 12-1).
Example 8-1 shows an example of how to configure the
Voltage Reference for an output voltage of 1.25V with VDD
= 5.0V.
VRCON REGISTER(ADDRESS 9Fh)
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
VREN: VREF Enable
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5
VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4
Unimplemented: Read as '0'
bit 3-0
VR: VREF value selection 0 ≤ VR [3:0] ≤ 15
when VRR = 1: VREF = (VR/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR/ 32) * VDD
Legend:
FIGURE 8-1:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VREF
VRR
VR3
(From VRCON)
16-1 Analog Mux
VR0
Note:
R is defined in Table 12-2.
2003 Microchip Technology Inc.
DS30235J-page 43
PIC16C62X
EXAMPLE 8-1:
MOVLW
8.4
VOLTAGE REFERENCE
CONFIGURATION
0x02
Effects of a RESET
A device RESET disables the voltage reference by
clearing bit VREN (VRCON). This reset also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON) and selects the high voltage
range by clearing bit VRR (VRCON). The VREF
value select bits, VRCON, are also cleared.
; 4 Inputs Muxed
MOVWF
CMCON
; to 2 comps.
BSF
STATUS,RP0
; go to Bank 1
MOVLW
0x0F
; RA3-RA0 are
MOVWF
TRISA
; inputs
MOVLW
0xA6
; enable VREF
8.5
MOVWF
VRCON
; low range
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA bit is set and the VROE bit, VRCON, is
set. Enabling the voltage reference output onto the
RA2 pin with an input signal present will increase
current consumption. Connecting RA2 as a digital
output with VREF enabled will also increase current
consumption.
; set VR=6
BCF
STATUS,RP0
; go to Bank 0
CALL
DELAY10
; 10µs delay
8.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to the
construction of the module. The transistors on the top
and bottom of the resistor ladder network (Figure 8-1)
keep VREF from approaching VSS or VDD. The voltage
reference is VDD derived and therefore, the VREF output
changes with fluctuations in VDD. The tested absolute
accuracy of the voltage reference can be found in
Table 12-2.
8.3
Connection Considerations
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
voltage reference output for external connections to
VREF. Figure 8-2 shows an example buffering
technique.
Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the voltage
reference should be disabled.
FIGURE 8-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
R(1)
RA
VREF
Module
•
+
–
•
VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON and VRCON.
TABLE 8-1:
Address
Name
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR
Value On
All Other
RESETS
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
9Fh
VRCON
VREN
VROE
VRR
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
Note:
- = Unimplemented, read as "0"
DS30235J-page 44
2003 Microchip Technology Inc.
PIC16C62X
9.0
SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real-time
applications are what sets a microcontroller apart from
other processors. The PIC16C62X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
OSC selection
RESET
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID Locations
In-Circuit Serial Programming™
2003 Microchip Technology Inc.
The PIC16C62X devices have a Watchdog Timer
which is controlled by configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in RESET while the
power supply stabilizes. There is also circuitry to
RESET the device if a brown-out occurs, which provides at least a 72 ms RESET. With these three
functions on-chip, most applications need no external
RESET circuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
DS30235J-page 45
PIC16C62X
9.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
REGISTER 9-1:
CP1
CP0 (2)
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
CONFIGURATION WORD (ADDRESS 2007h)
CP1
CP0 (2)
CP1
CP0 (2)
BODEN
CP1
CP0 (2)
PWRTE
WDTE
F0SC1
bit 13
bit 13-8,
5-4:
F0SC0
bit 0
CP: Code protection bit pairs (2)
Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFh code protected
Code protection for 1K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
Code protection for 0.5K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = Program memory code protection off
00 = 0000h-01FFh code protected
bit 7
Unimplemented: Read as ‘0’
bit 6
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3
PWRTE: Power-up Timer Enable bit (1, 3)
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the
value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Detect Reset is
enabled.
2: All of the CP pairs have to be given the same value to enable the code protection scheme
listed.
3: Unprogrammed parts default the Power-up Timer disabled.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
DS30235J-page 46
x = bit is unknown
2003 Microchip Technology Inc.
PIC16C62X
9.2
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
LP
XT
HS
RC
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
9.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 9-1). The PIC16C62X oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 9-2).
FIGURE 9-1:
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR) (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
To internal logic
C1
XTAL
RF
SLEEP
OSC2
C2
RS
See Note
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Ranges Characterized:
The PIC16C62X devices can be operated in four
different oscillator options. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
TABLE 9-1:
PIC16C62X
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
22 - 100 pF
15 - 68 pF
15 - 68 pF
22 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Higher capacitance increases the stability of the oscillator but also increases the start-up time. These
values are for design guidance only. Since each
resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
TABLE 9-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Mode
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
68 - 100 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
XT
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
HS
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level
specification. Since each crystal has its own
characteristics, the user should consult the crystal
manufacturer for appropriate values of external
components.
See Table 9-1 and Table 9-2 for recommended
values of C1 and C2.
Note:
A series resistor may be required for
AT strip cut crystals.
FIGURE 9-2:
clock from
ext. system
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
PIC16C62X
Open
OSC2
2003 Microchip Technology Inc.
DS30235J-page 47
PIC16C62X
9.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance or one with parallel
resonance.
Figure 9-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
FIGURE 9-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16C62X
CLKIN
74AS04
10k
XTAL
20 pF
Figure 9-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 9-4:
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 9-5 shows how the
R/C combination is connected to the PIC16C62X. For
REXT values below 2.2 kΩ, the oscillator operation may
become unstable or stop completely. For very high
REXT values (e.g., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend to keep REXT between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
See Section 13.0 for RC frequency variation from part
to part due to normal process variation. The variation is
larger for larger R (since leakage current variation will
affect RC frequency more for large R) and for smaller
C (since variation of input capacitance will affect RC
frequency more).
See Section 13.0 for variation of oscillator frequency
due to VDD for given REXT/CEXT values, as well as
frequency variation due to operating temperature for
given R, C and VDD values.
10k
20 pF
9.2.4
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (Figure 3-2 for
waveform).
FIGURE 9-5:
RC OSCILLATOR MODE
VDD
PIC16C62X
REXT
OSC1
330 kΩ
330 kΩ
74AS04
74AS04
To Other
Devices
74AS04
Internal Clock
CEXT
PIC16C62X
CLKIN
VDD
FOSC/4 OSC2/CLKOUT
0.1 µF
XTAL
DS30235J-page 48
2003 Microchip Technology Inc.
PIC16C62X
9.3
RESET
The PIC16C62X differentiates between various kinds
of RESET:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
WDT wake-up (SLEEP)
Brown-out Reset (BOR)
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 9-6.
Some registers are not affected in any RESET
condition Their status is unknown on POR and
unchanged in any other RESET. Most other registers
are reset to a “RESET state” on Power-on Reset,
FIGURE 9-6:
MCLR Reset, WDT Reset and MCLR Reset during
SLEEP. They are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. TO and PD bits are set or cleared differently
in different RESET situations as indicated in Table 9-2.
These bits are used in software to determine the nature
of the RESET. See Table 9-5 for a full description of
RESET states of all registers.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 12-5 for pulse width
specification.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR/
VPP Pin
WDT
Module
SLEEP
WDT
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
BODEN
S
Q
R
Q
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 9-1 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2003 Microchip Technology Inc.
DS30235J-page 49
PIC16C62X
9.4
9.4.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
The Power-up Time delay will vary from chip-to-chip
and due to VDD, temperature and process variation.
See DC parameters for details.
9.4.3
POWER-ON RESET (POR)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The on-chip POR circuit holds the chip in RESET until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, just tie the
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. See Electrical Specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
The POR circuit does not produce an internal RESET
when VDD declines.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
On any RESET (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in RESET until VDD rises above
BVDD. The Power-up Timer will now be invoked and will
keep the chip in RESET an additional 72 ms.
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as PWRT
is active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
disable (if set) or enable (if cleared or programmed) the
Power-up Timer. The Power-up Timer should always
be enabled when Brown-out Reset is enabled.
FIGURE 9-7:
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-Up Timer will execute a
72 ms RESET. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-7
shows typical Brown-out situations.
BROWN-OUT SITUATIONS
VDD
INTERNAL
RESET
BVDD
72 ms
VDD
INTERNAL
RESET
BVDD
