PIC16C62B-04/SS

PIC16C62B/72A 28-Pin 8-Bit CMOS Microcontrollers Pin Diagram • High-performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches, which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) • Interrupt capability • Eight level deep hardware stack • Direct, indirect, and relative addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Brown-out detection circuitry for Brown-out Reset (BOR) • Programmable code-protection • Power saving SLEEP mode • Selectable oscillator options • Low-power, high-speed CMOS EPROM technology • Fully static design • In-Circuit Serial Programming(ICSP) • Wide operating voltage range: 2.5V to 5.5V • High Sink/Source Current 25/25 mA • Commercial, Industrial and Extended temperature ranges • Low-power consumption: - < 2 mA @ 5V, 4 MHz - 22.5 A typical @ 3V, 32 kHz - < 1 A typical standby current  1998-2013 Microchip Technology Inc. SDIP, SOIC, SSOP, Windowed CERDIP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL •1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16C72A Microcontroller Core Features: 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA Peripheral Features: • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture, Compare, PWM module • Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit • 8-bit multi-channel Analog-to-Digital converter • Synchronous Serial Port (SSP) with Enhanced SPI and I2C Preliminary DS35008C-page 1 PIC16C62B/72A Pin Diagrams MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL •1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16C62B SDIP, SOIC, SSOP, Windowed CERDIP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA Key Features PIC® Mid-Range Reference Manual (DS33023) PIC16C62B PIC16C72A Operating Frequency DC - 20 MHz DC - 20 MHz Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) Program Memory (14-bit words) 2K 2K Data Memory (bytes) 128 128 Interrupts 7 8 I/O Ports Ports A,B,C Ports A,B,C Timers 3 3 Capture/Compare/PWM modules 1 1 Serial Communications SSP 8-bit Analog-to-Digital Module DS35008C-page 2 SSP — Preliminary 5 input channels  1998-2013 Microchip Technology Inc. PIC16C62B/72A Table of Contents 1.0 Device Overview .................................................................................................................................................... 5 2.0 Memory Organization ............................................................................................................................................. 7 3.0 I/O Ports ............................................................................................................................................................... 19 4.0 Timer0 Module ..................................................................................................................................................... 25 5.0 Timer1 Module ..................................................................................................................................................... 27 6.0 Timer2 Module ..................................................................................................................................................... 31 7.0 Capture/Compare/PWM (CCP) Module ............................................................................................................... 33 8.0 Synchronous Serial Port (SSP) Module ............................................................................................................... 39 9.0 Analog-to-Digital Converter (A/D) Module ............................................................................................................ 49 10.0 Special Features of the CPU................................................................................................................................ 55 11.0 Instruction Set Summary ...................................................................................................................................... 67 12.0 Development Support........................................................................................................................................... 75 13.0 Electrical Characteristics ...................................................................................................................................... 81 14.0 DC and AC Characteristics Graphs and Tables................................................................................................. 103 15.0 Packaging Information........................................................................................................................................ 105 Appendix A: Revision History ................................................................................................................................... 111 Appendix B: Conversion Considerations .................................................................................................................. 111 Appendix C: Migration from Base-line to Mid-Range Devices .................................................................................. 112 Index ........................................................................................................................................................................... 113 On-Line Support.......................................................................................................................................................... 117 Reader Response ....................................................................................................................................................... 118 PIC16C62B/72A Product Identification System .......................................................................................................... 119 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 3 PIC16C62B/72A NOTES: DS35008C-page 4 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 1.0 DEVICE OVERVIEW ommended reading for a better understanding of the device architecture and operation of the peripheral modules. This document contains device-specific information. Additional information may be found in the PIC® MCU Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly rec- FIGURE 1-1: There are two devices (PIC16C62B, PIC16C72A) covered by this datasheet. The PIC16C62B does not have the A/D module implemented. Figure 1-1 is the block diagram for both devices. The pinouts are listed in Table 1-1. PIC16C62B/PIC16C72A BLOCK DIAGRAM 13 8 Data Bus Program Counter PORTA RA0/AN0(2) RA1/AN1(2) RA2/AN2(2) RA3/AN3/VREF(2) RA4/T0CKI RA5/SS/AN4(2) EPROM 2K x 14 Program Memory Program Bus RAM 128 x 8 File Registers 8 Level Stack (13-bit) 14 RAM Addr(1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 MUX Power-up Timer Oscillator Start-up Timer Instruction Decode & Control ALU Power-on Reset Timing Generation MCLR RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 8 Watchdog Timer Brown-out Reset OSC1/CLKIN OSC2/CLKOUT PORTC W reg VDD, VSS Timer0 Timer1 Timer2 CCP1 Synchronous Serial Port A/D(2) Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C62B.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 5 PIC16C62B/72A TABLE 1-1 PIC16C62B/PIC16C72A PINOUT DESCRIPTION DIP Pin# SOIC Pin# I/O/P Type OSC1/CLKIN 9 9 I OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. RA0/AN0(4) 2 2 I/O TTL RA0 can also be analog input 0 RA1/AN1(4) 3 3 I/O TTL RA1 can also be analog input 1 4 4 I/O TTL RA2 can also be analog input 2 5 5 I/O TTL RA3 can also be analog input 3 or analog reference voltage RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/SS/AN4(4) 7 7 I/O TTL RA5 can also be analog input 4 or the slave select for the synchronous serial port. Pin Name Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. PORTA is a bi-directional I/O port. RA2/AN2(4) RA3/AN3/VREF (4) PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O TTL/ST(1) RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3 24 24 I/O TTL RB4 25 25 I/O TTL Interrupt on change pin. RB5 26 26 I/O TTL Interrupt on change pin. RB6 27 27 I/O TTL/ST(2) RB7 28 28 I/O TTL/ST(2) RB0 can also be the external interrupt pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6 17 17 I/O ST ST RC7 18 18 I/O VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: I = input Note 1: 2: 3: 4: O = output I/O = input/output P = power or program — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. The A/D module is not available on the PIC16C62B. DS35008C-page 6 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 2.0 MEMORY ORGANIZATION FIGURE 2-1: There are two memory blocks in each of these microcontrollers. Each block (Program Memory and Data Memory) has its own bus, so that concurrent access can occur. PC CALL, RETURN RETFIE, RETLW Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). 2.1 PROGRAM MEMORY MAP AND STACK 13 Stack Level 1 Program Memory Organization Stack Level 8 The reset vector is at 0000h and the interrupt vector is at 0004h. User Memory Space The PIC16C62B/72A devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Each device has 2K x 14 words of program memory. Accessing a location above 07FFh will cause a wraparound. Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory 07FFh 0800h 1FFFh  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 7 PIC16C62B/72A 2.2 Data Memory Organization FIGURE 2-2: The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1(1) = 00  = 01  = 10  = 11  RP0 REGISTER FILE MAP File Address (STATUS) Bank0 Bank1 Bank2 (not implemented) Bank3 (not implemented) File Address 00h INDF(1) 01h TMR0 INDF(1) 80h OPTION_REG 81h 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h Note 1: Maintain this bit clear to ensure upward compatibility with future products. 07h PORTC TRISC 87h 08h — — 88h Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some “high use” Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. 09h — — 89h 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Dh — — 8Dh 0Eh TMR1L PCON 8Eh 0Fh TMR1H — 8Fh 10h T1CON — 90h 11h TMR2 — 91h 12h T2CON PR2 92h 13h SSPBUF SSPADD 93h 14h SSPCON SSPSTAT 94h 15h CCPR1L — 95h 16h CCPR1H — 96h 17h CCP1CON — 97h 18h — — 98h 19h — — 99h 1Ah — — 9Ah 1Bh — — 9Bh 1Ch — — 9Ch 1Dh — — 9Dh 1Eh ADRES(2) — 9Eh 1Fh ADCON0(2) ADCON1(2) 9Fh General Purpose Registers A0h — C0h 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 2.5). 20h General Purpose Registers BFh — 7Fh — Bank 0 FFh Bank 1 Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C62B, read as '0'. DS35008C-page 8 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1 Addr The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section. SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (4) Bank 0 00h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h PCL(1) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS(1) 04h FSR(1) 05h PORTA(6,7) 06h PORTB(6,7) PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC(6,7) PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h-09h — 0Ah PCLATH(1,2) 0Bh INTCON(1) 0Ch PIR1 0Dh IRP(5) RP0 TO PD Z DC C Indirect data memory address pointer — — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 Unimplemented — — — — PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 ADIF (3) Write Buffer for the upper 5 bits of the Program Counter — GIE — — RP1(5) Unimplemented ---0 0000 ---0 0000 — — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON 11h TMR2 — — T1CKPS1 T1CKPS0 T1OSCEN TMR1CS TMR1ON T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register1 (LSB) 16h CCPR1H Capture/Compare/PWM Register1 (MSB) 17h CCP1CON — 1Eh ADRES(3) 1Fh ADCON0(3) — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL — SSPOV — SSPEN CCP1X CKP CCP1Y SSPM3 xxxx xxxx uuuu uuuu SSPM2 SSPM1 SSPM0 xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 — A/D Result Register ADCS0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu Unimplemented ADCS1 --00 0000 --uu uuuu 0000 0000 0000 0000 12h 18h-1Dh T1SYNC Timer2 module’s register — xxxx xxxx uuuu uuuu CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as ’0’. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 5: The IRP and RP1 bits are reserved. Always maintain these bits clear. 6: On any device reset, these pins are configured as inputs. 7: This is the value that will be in the port output latch.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 9 PIC16C62B/72A TABLE 2-1 Addr SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (4) Bank 1 80h INDF(1) 81h OPTION_REG 82h PCL(1) 83h STATUS(1) 84h FSR(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP(5) RP1(5) RP0 TO 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h-89h — — (1,2) 8Ah PCLATH INTCON(1) PIE1 8Dh 8Eh --11 1111 --11 1111 PCON — — — — — PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 ADIE (3) Write Buffer for the upper 5 bits of the Program Counter — GIE — — 8Fh-91h PORTA Data Direction Register Unimplemented 8Bh 8Ch — Unimplemented — — ---0 0000 ---0 0000 — — — — — POR BOR Unimplemented — ---- --qq ---- --uu — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT 95h-9Eh 9Fh — ADCON1(3) SMP CKE D/A P S R/W UA BF Unimplemented — — — — — PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 — — ---- -000 ---- -000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC whose contents are transferred to the upper byte of the program counter. 3: A/D not implemented on the PIC16C62B, maintain as ’0’. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 5: The IRP and RP1 bits are reserved. Always maintain these bits clear. 6: On any device reset, these pins are configured as inputs. 7: This is the value that will be in the port output latch. DS35008C-page 10 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 2.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, the write to these three bits is disabled. These bits are set or cleared according to the device logic. The TO and PD bits are not writable. The result of an instruction with the STATUS register as destination may be different than intended. Note 1: The IRP and RP1 bits are reserved. Maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). REGISTER 2-1: R/W-0 IRP R/W-0 RP1 STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC bit7 bit 7: R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) (reserved, maintain clear) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes Note: RP1 is reserved, maintain clear bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 11 PIC16C62B/72A 2.2.2.2 OPTION_REG REGISTER Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. OPTION_REG REGISTER (ADDRESS 81h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit7 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled for all PORTB inputs bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module R = Readable bit W = Writable bit - n = Value at POR reset bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 DS35008C-page 12 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 2.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register, which contains various interrupt enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON REGISTER (ADDRESS 0Bh, 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit0 R = Readable bit W = Writable bit - n = Value at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: IINTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (software must clear bit) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (software must clear bit) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 input pins have changed state (clear by reading PORTB) 0 = None of the RB7:RB4 input pins have changed state  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 13 PIC16C62B/72A 2.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. REGISTER 2-4: Bit PEIE (INTCON) must be set to enable any peripheral interrupt. PIE1 REGISTER (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE(1) — — SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: Unimplemented: Read as ‘0’ bit 6: ADIE(1): A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 5-4: Unimplemented: Read as ‘0’ bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear. DS35008C-page 14 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts. REGISTER 2-5: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1 REGISTER (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF(1) — — SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: Unimplemented: Read as ‘0’ bit 6: ADIF(1): A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 5-4: Unimplemented: Read as ‘0’ bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 15 PIC16C62B/72A 2.2.2.6 PCON REGISTER Note: The Power Control register (PCON) contains flag bits to allow differentiation between a Power-on Reset (POR), Brown-Out Reset (BOR) and resets from other sources. . REGISTER 2-6: On Power-on Reset, the state of the BOR bit is unknown and is not predictable. If the BODEN bit in the configuration word is set, the user must first set the BOR bit on a POR, and check it on subsequent resets. If BOR is cleared while POR remains set, a Brown-out reset has occurred. If the BODEN bit is clear, the BOR bit may be ignored. PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS35008C-page 16 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 2.3 PCL and PCLATH 2.4 The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register and is readable and writable. The high byte is called the PCH register. This register contains the PC bits and is not directly accessible. All updates to the PCH register go through the PCLATH register. 2.3.1 STACK The stack allows any combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Program Memory Paging The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper bit of the address is provided by PCLATH. The user must ensure that the page select bit is programmed to address the proper program memory page. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped from the stack. Therefore, manipulation of the PCLATH bit is not required for the return instructions. Mid-range devices have an 8 level deep hardware stack. The stack space is not part of either program or data space and the stack pointer is not accessible. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 17 PIC16C62B/72A 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-1: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). NEXT Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next : ;YES, continue An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS), as shown in Figure 2-3. However, IRP is not used in the PIC16C62B/72A. DIRECT/INDIRECT ADDRESSING Direct Addressing RP1:RP0 0x20 FSR INDF FSR FSR,4 NEXT CONTINUE A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-1. FIGURE 2-3: movlw movwf clrf incf btfss goto HOW TO CLEAR RAM USING INDIRECT ADDRESSING 6 Indirect Addressing from opcode 0 IRP (1) 7 FSR register 0 (1) bank select bank select location select 00 00h 01 80h 10 100h location select 11 180h not used (2) (2) Data Memory 7Fh Bank 0 FFh 17Fh Bank 1 1FFh Bank 2 Bank 3 Note 1: Maintain clear for upward compatibility with future products. 2: Not implemented. DS35008C-page 18 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 3.0 I/O PORTS FIGURE 3-1: Some I/O port pins are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PIC® MCU Mid-Range Reference Manual, (DS33023). 3.1 Data Bus BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS D Q VDD WR Port Q CK PORTA and the TRISA Register Data Latch PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, (i.e., put the contents of the output latch on the selected pin). D WR TRIS Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. Pin RA5 is multiplexed with the SSP to become the RA5/SS pin. On the PIC16C72A device, other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). N Q I/O pin(1) VSS Q CK Analog input mode (72A only) TRIS Latch The PORTA register reads the state of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Note: P TTL input buffer RD TRIS Q D EN RD PORT To A/D Converter (72A only) Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 3-2: Data Bus On a Power-on Reset, pins with analog functions are configured as analog inputs with digital input buffers disabled . A digital read of these pins will return ’0’. WR PORT BLOCK DIAGRAM OF RA4/T0CKI PIN D Q CK Q N I/O pin(1) Data Latch The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. WR TRIS D Q CK Q VSS Schmitt Trigger input buffer TRIS Latch RD TRIS Q D EN EN RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 19 PIC16C62B/72A TABLE 3-1 PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input(1) RA1/AN1 bit1 TTL Input/output or analog input(1) RA2/AN2 bit2 TTL Input/output or analog input(1) RA3/AN3/VREF bit3 TTL RA4/T0CKI bit4 ST Input/output or analog input(1) or VREF(1) Input/output or external clock input for Timer0 Output is open drain type bit5 TTL Input/output or slave select input for synchronous serial port or analog input(1) RA5/SS/AN4 Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: The PIC16C62B does not implement the A/D module. TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address Name 05h PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu --11 1111 --11 1111 ---- -000 ---- -000 (for PIC16C72A only) 05h PORTA (for PIC16C62B only) 85h TRISA — — 9Fh ADCON1(1) — — PORTA Data Direction Register — — — PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: The PIC16C62B does not implement the A/D module. Maintain this register clear. DS35008C-page 20 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, (i.e., put the contents of the output latch on the selected pin). Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: FIGURE 3-3: A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. BLOCK DIAGRAM OF RB3:RB0 PINS VDD RBPU(2) Data Bus WR Port weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRIS Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. b) The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. RB0/INT is an external interupt pin and is configured using the INTEDG bit (OPTION_REG). RB0/INT is discussed in detail in Section 10.10.1. TTL Input Buffer CK a) FIGURE 3-4: BLOCK DIAGRAM OF RB7:RB4 PINS VDD RD TRIS Q RD Port D RBPU(2) EN Data Bus WR Port RB0/INT Schmitt Trigger Buffer Data Latch D Q I/O pin(1) CK TRIS Latch D Q RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG). weak P pull-up WR TRIS TTL Input Buffer CK RD TRIS Q Latch D EN RD Port ST Buffer Q1 Set RBIF From other RB7:RB4 pins Q D RD Port EN Q3 RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG).  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 21 PIC16C62B/72A TABLE 3-3 PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Input/output pin (with interrupt on change). RB6 bit6 TTL/ST(2) Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt on change). RB7 bit7 TTL/ST(2) Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB 1111 1111 1111 1111 81h OPTION_REG 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS35008C-page 22 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 3.3 PORTC and the TRISC Register PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override maybe in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORT/PERIPHERAL Select(2) Peripheral Data Out Data Bus WR PORT D VDD 0 Q P 1 CK Q Data Latch WR TRIS D CK I/O pin(1) Q Q N TRIS Latch VSS Schmitt Trigger RD TRIS Peripheral OE(3) RD PORT Peripheral input Q D EN Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 23 PIC16C62B/72A TABLE 3-5 PORTC FUNCTIONS Name Bit# RC0/T1OSO/T1CKI bit0 Buffer Function Type ST TRISC Override Input/output port pin or Timer1 oscillator output/Timer1 clock input Yes RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input Yes RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output No RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. No RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). No RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output No RC6 bit6 ST Input/output port pin No RC7 bit7 ST Input/output port pin No Legend: ST = Schmitt Trigger input TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC 1111 1111 1111 1111 PORTC Data Direction Register Legend: x = unknown, u = unchanged. DS35008C-page 24 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the Electrical Specifications section of this manual, and in the PIC® MCU Mid-Range Reference Manual, (DS33023). The Timer0 module timer/counter has the following features: • 8-bit timer/counter - Read and write - INT on overflow • 8-bit software programmable prescaler • INT or EXT clock select - EXT clock edge select 4.2 An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. There is only one prescaler available which is shared between the Timer0 module and the Watchdog Timer. A prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). 4.1 The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG) determine the prescaler assignment and prescale ratio. Timer0 Operation Timer0 can operate as a timer or as a counter. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Timer mode is selected by clearing bit T0CS (OPTION_REG). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. Counter mode is selected by setting bit T0CS (OPTION_REG). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed below. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. FIGURE 4-1: Prescaler Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment or ratio. TIMER0 BLOCK DIAGRAM Data Bus FOSC/4 0 PSout 1 1 Programmable Prescaler RA4/T0CKI pin 0 8 Sync with Internal clocks TMR0 PSout (TCY delay) T0SE 3 PS2, PS1, PS0 PSA T0CS Set interrupt flag bit T0IF on overflow Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 25 PIC16C62B/72A 4.2.1 4.3 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program execution). Note: The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON). The interrupt can be masked by clearing bit T0IE (INTCON). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. To avoid an unintended device RESET, a specific instruction sequence (shown in the PIC® MCU Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. FIGURE 4-2: Timer0 Interrupt BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus CLKOUT (= Fosc/4) 0 RA4/T0CKI pin 8 M U X 1 M U X 0 1 SYNC 2 TCY TMR0 reg T0SE T0CS Set flag bit T0IF on Overflow PSA Prescaler 0 1 Watchdog Timer 8-bit Prescaler M U X 8 8 - to - 1MUX PS2:PS0 PSA 1 0 WDT Enable bit MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG). TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0 Address Name 01h TMR0 0Bh,8Bh INTCON 81h OPTION_REG 85h TRISA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 module’s register GIE PEIE RBPU INTEDG — — Value on: POR, BOR Value on all other resets xxxx xxxx uuuu uuuu T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 --11 1111 --11 1111 PORTA Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. DS35008C-page 26 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 5.0 TIMER1 MODULE 5.1 The Timer1 module timer/counter has the following features: • • • • • 16-bit timer/counter Readable and writable Internal or external clock select Interrupt on overflow from FFFFh to 0000h Reset from CCP module trigger Timer1 Operation Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON). Timer1 has a control register, shown in Register 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON). Figure 5-1 is a simplified block diagram of the Timer1 module. Additional information on timer modules is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC value is ignored. Timer1 also has an internal “reset input”. This reset can be generated by the CCP module as a special event trigger (Section 7.0). REGISTER 5-1:T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC R/W-0 R/W-0 TMR1CS TMR1ON bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled (TRISC ignored) 0 = Oscillator is shut off (The oscillator is turned off to reduce power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 27 PIC16C62B/72A FIGURE 5-1: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1H Synchronized clock input 0 TMR1 TMR1L 1 TMR1ON on/off T1SYNC T1OSC RC0/T1OSO/T1CKI RC1/T1OSI 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Synchronize Prescaler 1, 2, 4, 8 det 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS35008C-page 28 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 5.2 5.3 Timer1 Oscillator Timer1 Interrupt A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON). When the Timer1 oscillator is enabled, RC0 and RC1 pins become T1OSO and T1OSI inputs, overriding TRISC. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit TMR1IF (PIR1). This interrupt can be enabled by setting TMR1 interrupt enable bit TMR1IE (PIE1). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator. 5.4 If the CCP module is configured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. TABLE 5-1 Note: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq C1 C2 LP 32 kHz 100 kHz 200 kHz 33 pF 15 pF 15 pF 33 pF 15 pF 15 pF The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1). Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A  20 PPM 100 kHz Epson C-2 100.00 KC-P  20 PPM 200 kHz STD XTL 200.000 kHz  20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. TABLE 5-2 Resetting Timer1 using a CCP Trigger Output In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1. REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u INTCON 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 10h T1CON Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 29 PIC16C62B/72A NOTES: DS35008C-page 30 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 6.0 TIMER2 MODULE Additional information on timer modules is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). The Timer2 module timer has the following features: • 8-bit timer (TMR2 register) - Readable and writable • 8-bit period register (PR2) - Readable and writable • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on match (TMR2 = PR2) • Timer2 can be used by SSP and CCP FIGURE 6-1: Sets flag bit TMR2IF TIMER2 BLOCK DIAGRAM TMR2 output (1) Reset Postscaler 1:1 to 1:16 Timer2 has a control register, shown in Register 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON) to minimize power consumption. EQ 4 Figure 6-1 is a simplified block diagram of the Timer2 module. TMR2 reg Comparator Prescaler 1:1, 1:4, 1:16 FOSC/4 2 PR2 reg Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. REGISTER 6-1:T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON R/W-0 R/W-0 T2CKPS1 T2CKPS0 bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16  1998-2013 Microchip Technology Inc. Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset DS35008C-page 31 PIC16C62B/72A 6.1 Timer2 Operation 6.2 The Timer2 output is also used by the CCP module to generate the PWM "On-Time", and the PWM period with a match with PR2. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1)). Timer2 Interrupt The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset. 6.3 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate shift clock. The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -00- 0000 0000 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000 11h TMR2 12h T2CON 92h PR2 Legend: 0000 0000 0000 0000 Timer2 module’s register — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 Timer2 Period Register x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. DS35008C-page 32 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 7.0 CAPTURE/COMPARE/PWM (CCP) MODULE Additional information on the CCP module is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). The CCP (Capture/Compare/PWM) module contains a 16-bit register, which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave duty cycle register. Table 7-1 shows the timer resources of the CCP module modes. TABLE 7-1 Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 7-2 CCP MODE - TIMER RESOURCE CCP Mode Timer Resource Capture Compare PWM Timer1 Timer1 Timer2 INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time-base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None. REGISTER 7-1:CCP1CON REGISTER (ADDRESS 17h) U-0 — bit7 U-0 — R/W-0 R/W-0 R/W-0 CCP1X CCP1Y CCP1M3 R/W-0 CCP1M2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 33 PIC16C62B/72A 7.1 Capture Mode 7.1.4 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register, when an event occurs on pin RC2/CCP1. An event is defined as: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON). When a capture is made, the interrupt request flag bit ,CCP1IF (PIR1), is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. FIGURE 7-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Prescaler  1, 4, 16 Set flag bit CCP1IF (PIR1) RC2/CCP1 Pin CCPR1H and edge detect CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. EXAMPLE 7-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW CCP1CON NEW_CAPT_PS MOVWF CCP1CON ;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value CCPR1L Capture Enable TMR1H TMR1L CCP1CON Q’s 7.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC bit. Note: 7.1.2 If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work consistently. 7.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should clear CCP1IE (PIE1) before changing the capture mode to avoid false interrupts. Clear the interrupt flag bit, CCP1IE before setting CCP1IE. DS35008C-page 34 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 7.2 7.2.1 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • driven High • driven Low • remains Unchanged FIGURE 7-2: COMPARE MODE OPERATION BLOCK DIAGRAM TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 7.2.4 SOFTWARE INTERRUPT MODE SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. Set flag bit CCP1IF (PIR1) CCPR1H CCPR1L Q S Output Logic match RC2/CCP1 R Pin TRISC Output Enable CCP1CON Mode Select Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. When a generated software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). Special Event Trigger Address Note: 7.2.3 Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1), and set bit GO/DONE (ADCON0), which starts an A/D conversion TABLE 7-3 The user must configure the RC2/CCP1 pin as an output by clearing the TRISC bit. 7.2.2 The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON). The interrupt flag bit, CCP1IF, is set on all compare matches. CCP PIN CONFIGURATION Comparator TMR1H TMR1L The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCP1 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Bit 6 Bit 5 Bit 4 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h Legend: CCP1CON — — — Bit 2 Bit 1 Bit 0 Value on all other resets Bit 7 — Bit 3 Value on POR, BOR Name RBIF 0000 000x 0000 000u T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 35 PIC16C62B/72A 7.3 PWM Mode 7.3.1 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 7-3 shows a simplified block diagram of the CCP module in PWM mode. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3. FIGURE 7-3: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into CCPR1H Note: CCP1CON CCPR1L 7.3.2 CCPR1H (Slave) R Comparator Q RC2/CCP1 TMR2 (Note 1) S Clear Timer, CCP1 pin and latch D.C. PR2 A PWM output (Figure 7-4) has a time base (period) and a time that the output stays high (on-time). The frequency of the PWM is the inverse of the period (1/period). PWM OUTPUT The PWM on-time is specified by writing to the CCPR1L register and to the CCP1CON bits. Up to 10-bit resolution is available. CCPR1L contains eight MSbs and CCP1CON contains two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON. The following equation is used to calculate the PWM duty cycle in time: CCPR1L and CCP1CON can be written to at any time, but the on-time value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base. FIGURE 7-4: PWM ON-TIME PWM on-time = (CCPR1L:CCP1CON) • Tosc • (TMR2 prescale value) TRISC Comparator The Timer2 postscaler (see Section 6.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM on-time. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: Period log ( Resolution = On-Time Fosc Fpwm ) bits log(2) TMR2 = PR2 Note: TMR2 = Duty Cycle TMR2 = PR2 If the PWM on-time value is larger than the PWM period, the CCP1 pin will not be cleared. For an example PWM period and on-time calculation, see the PIC® MCU Mid-Range Reference Manual, (DS33023). DS35008C-page 36 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM on-time by writing to the CCPR1L register and CCP1CON bits. Make the CCP1 pin an output by clearing the TRISC bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. TABLE 7-4 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 7-5 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 5.5 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’s period register 1111 1111 1111 1111 12h T2CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h Legend: CCP1CON — — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 37 PIC16C62B/72A NOTES: DS35008C-page 38 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 8.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 8.1 SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) For more information on SSP operation (including an I2C Overview), refer to the PIC® MCU Mid-Range Reference Manual, (DS33023). Also, refer to Application Note AN578, “Use of the SSP Module in the I 2C MultiMaster Environment.” 8.2 ister, and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: • SDI must have TRISC set • SDO must have TRISC cleared • SCK (master operation) must have TRISC cleared • SCK (Slave mode) must have TRISC set • SS must have TRISA set (if used) Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON = 0100) the SPI module will reset if the SS pin is set to VDD. Note: If the SPI is used in Slave Mode with CKE = '1', then the SS pin control must be enabled. SPI Mode This section contains register definitions and operational characteristics of the SPI module. FIGURE 8-1: Additional information on SPI operation may be found in the PIC® MCU Mid-Range Reference Manual, (DS33023). 8.2.1 SSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read OPERATION OF SSP MODULE IN SPI MODE Write SSPBUF reg A block diagram of the SSP Module in SPI Mode is shown in Figure 8-1. The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, three pins are used: • Serial Data Out (SDO)RC5/SDO • Serial Data In (SDI)RC4/SDI/SDA • Serial Clock (SCK)RC3/SCK/SCL SSPSR reg RC4/SDI/SDA Shift Clock bit0 RC5/SDO Additionally, a fourth pin may be used when in a slave mode of operation: SS Control Enable RA5/SS/AN4 • Slave Select (SS)RA5/SS/AN4 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON) and SSPSTAT. These control bits allow the following to be specified: • • • • Master Operation (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock Edge (Output data on rising/falling edge of SCK) • Clock Rate (master operation only) • Slave Select Mode (Slave mode only) Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TMR2 output 2 Prescaler TCY 4, 16, 64 TRISC To enable the serial port, SSP Enable bit, SSPEN (SSPCON) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON reg-  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 39 PIC16C62B/72A TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION Value on POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 8Ch 13h SSPBUF 14h SSPCON WCOL 94h SSPSTAT 85h TRISA 87h TRISC Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN SMP CKE — — D/A 0000 000x 0000 000u xxxx xxxx uuuu uuuu CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 P S R/W UA BF 0000 0000 0000 0000 PORTA Data Direction Register PORTC Data Direction Register --11 1111 --11 1111 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. DS35008C-page 40 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 8.3 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to support firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON). FIGURE 8-2: SSP BLOCK DIAGRAM (I2C MODE) SSPSR reg MSb LSb Match detect Addr Match When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and load the SSPBUF register with the received value in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. This happens if either of the following conditions occur: SSPADD reg Start and Stop bit detect Set, Reset S, P bits (SSPSTAT reg) a) b) The SSP module has five registers for I2C operation. These are the: • • • • • SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The SSP module will override the input state with the output data when required (slave-transmitter). shift clock RC4/ SDI/ SDA Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be operated as open drain outputs, provided these pins are programmed to inputs by setting the appropriate TRISC bits. 8.3.1 Write SSPBUF reg RC3/SCK/SCL • I 2C Slave mode (7-bit address) • I 2C Slave mode (10-bit address) • I 2C Slave mode (7-bit address), with start and stop bit interrupts enabled for firmware master mode support • I 2C Slave mode (10-bit address), with start and stop bit interrupts enabled for firmware master mode support • I 2C start and stop bit interrupts enabled for firmware master mode support, slave mode idle Additional information on SSP I2C operation may be found in the PIC® MCU Mid-Range Reference Manual, (DS33023). Internal Data Bus Read The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow one of the following I 2C modes to be selected: SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not accessible SSP Address Register (SSPADD) The buffer full bit BF (SSPSTAT) was set before the transfer was completed. The overflow bit SSPOV (SSPCON) was set before the transfer was completed. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1) is set. Table 8-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the SSP module, is shown in timing parameter #100, THIGH, and parameter #101, TLOW.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 41 PIC16C62B/72A 8.3.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1), is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal TABLE 8-2 ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. 2. 3. 4. 5. 6. 7. 8. 9. Receive first (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV SSPSR  SSPBUF Generate ACK Pulse 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 Yes No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. DS35008C-page 42 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 8.3.1.2 RECEPTION When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT) is set or bit SSPOV (SSPCON) is set. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 8-3: Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. S 1 2 3 4 5 6 7 SSPIF (PIR1) BF (SSPSTAT) 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 8 7 Cleared in software 9 P Bus Master terminates transfer SSPBUF register is read SSPOV (SSPCON) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 43 PIC16C62B/72A 8.3.1.3 TRANSMISSION shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 8-4). When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and the CKP will be cleared by hardware, holding SCL low. Slave devices cause the master to wait by holding the SCL line low. The transmit data is loaded into the SSPBUF register, which in turn loads the SSPSR register. When bit CKP (SSPCON) is set, pin RC3/SCK/SCL releases SCL. When the SCL line goes high, the master may resume operating the SCL line and receiving data. The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are Receiving Address SCL A7 S As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP. I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) FIGURE 8-4: SDA An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. A6 1 2 Data in sampled R/W = 1 A5 A4 A3 A2 A1 3 4 5 6 7 Transmitting Data ACK 8 9 D7 1 SCL held low while CPU responds to SSPIF ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P cleared in software SSPIF (PIR1) BF (SSPSTAT) SSPBUF is written in software From SSP interrupt service routine CKP (SSPCON) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) DS35008C-page 44 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 8.3.2 8.3.3 MASTER OPERATION MULTI-MASTER OPERATION In multi-master operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. Master operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared by a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear. In master operation, the SCL and SDA lines are manipulated in software by clearing the corresponding TRISC bit(s). The output level is always low, irrespective of the value(s) in PORTC. So when transmitting data, a '1' data bit must have the TRISC bit set (input) and a '0' data bit must have the TRISC bit cleared (output). The same scenario is true for the SCL line with the TRISC bit. In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC). There are two stages where this arbitration can be lost, these are: The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): • Address Transfer • Data Transfer • START condition • STOP condition • Byte transfer completed When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. Master operation can be done with either the slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. For more information on master operation, see AN578 - Use of the SSP Module in the of I2C Multi-Master Environment. For more information on master operation, see AN554 - Software Implementation of I2C Bus Master. REGISTERS ASSOCIATED WITH I2C OPERATION TABLE 8-3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets 0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 2 93h SSPADD Synchronous Serial Port (I C mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL 0000 0000 0000 0000 94h SSPSTAT (1) 0000 0000 0000 0000 87h TRISC 1111 1111 1111 1111 SMP SSPOV SSPEN CKE (1) D/A CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W PORTC Data Direction register UA BF Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: Maintain these bits clear in I2C mode.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 45 PIC16C62B/72A REGISTER 8-1: R/W-0 R/W-0 SMP CKE SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R-0 R-0 R-0 R-0 R-0 R-0 D/A P S R/W UA BF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode I2C Mode This bit must be maintained clear bit 6: CKE: SPI Clock Edge Select SPI Mode CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK I2C Mode This bit must be maintained clear bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS35008C-page 46 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A REGISTER 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master operation, clock = FOSC/4 0001 = SPI master operation, clock = FOSC/16 0010 = SPI master operation, clock = FOSC/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master operation (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 47 PIC16C62B/72A NOTES: DS35008C-page 48 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 9.0 Note: ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE This section applies to the PIC16C72A only. Additional information on the A/D module is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). The A/D module has three registers. These registers are: The analog-to-digital (A/D) converter module has five input channels. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D converter has the feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. • A/D Result Register (ADRES) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The ADCON0 register, shown in Figure 9-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 9-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O. REGISTER 9-1:ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 ADCS1 ADCS0 bit7 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 — R/W-0 ADON bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an internal RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 49 PIC16C62B/72A REGISTER 9-2:ADCON1 REGISTER (ADDRESS 9Fh) U-0 — bit7 U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D VREF VDD RA3 VDD RA3 VDD RA3 VDD A = Analog input D = Digital I/O DS35008C-page 50 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit, ADCON0, is cleared, and the A/D interrupt flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 9-1. 1. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. 2. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 9.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 3. 4. 5. Configure the A/D module: • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit Wait the required acquisition time. Start conversion: • Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR 6. 7. FIGURE 9-1: • Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. A/D BLOCK DIAGRAM CHS2:CHS0 100 RA5/AN4 VIN 011 (Input voltage) RA3/AN3/VREF 010 RA2/AN2 A/D Converter 001 RA1/AN1 000 VDD 000 010 100 11x 001 011 101 VREF (Reference voltage) RA0/AN0 or or or or or PCFG2:PCFG0  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 51 PIC16C62B/72A 9.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed), this acquisition must pass before the conversion can be started. To calculate the minimum acquisition time, TACQ, see Equation 9-1. This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. In general; = 10k Assuming RS Vdd = 3.0V (RSS = 10k Temp. = 50C (122F) TACQ 13.0 Sec By increasing VDD and reducing RS and Temp., TACQ can be substantially reduced. FIGURE 9-2: ANALOG INPUT MODEL VDD Rs ANx CPIN 5 pF VA Sampling Switch VT = 0.6V VT = 0.6V RIC  1k SS RSS CHOLD = DAC capacitance = 51.2 pF I leakage ± 500 nA VSS Legend CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) VDD 6V 5V 4V 3V 2V 5 6 7 8 9 10 11 RSS (k) EQUATION 9-1: TACQ ACQUISITION TIME = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF TAMP = 5S TC = - (51.2pF)(1k + RSS + RS) In(1/511) TCOFF = (Temp -25C)(0.05S/C) DS35008C-page 52 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 9.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • 2TOSC 8TOSC 32TOSC Internal RC oscillator The A/D module can operate during sleep mode, but the RC oscillator must be selected as the A/D clock source prior to the SLEEP instruction. Table 9-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins) may cause the input buffer to consume current that is out of the devices specification. TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Operation ADCS1:ADCS0 2TOSC 00 8TOSC 01 32TOSC Configuring Analog Port Pins The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. TABLE 9-1 9.3 10 Device Frequency 20 MHz 100 ns(2) ns(2) 400 1.6 s 5 MHz ns(2) 400 1.6 s 6.4 s 1.25 MHz 333.33 kHz 1.6 s 6 s 6.4 s 24 s(3) 25.6 s(3) 96 s(3) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1) 2 - 6 s(1,4) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. RC(5) Legend: Note 1: 2: 3: 4: 11  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 53 PIC16C62B/72A 9.4 Note: 9.5 A/D Conversions GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead. The appropriate analog input channel must be selected and the minimum acquisition time must pass before the “special event trigger” sets the GO/DONE bit (starts a conversion). The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON) be programmed as 1011 and that the A/D module be enabled (ADON bit is set). When the trigger occurs, the TABLE 9-2 If the A/D module is not enabled (ADON is cleared), then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter. SUMMARY OF A/D REGISTERS Address Name 0Bh,8Bh INTCON 0Ch PIR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 CHS2 CHS1 CHS0 GO/DONE — ADON — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 8Ch PIE1 1Eh ADRES 1Fh ADCON0 ADCS1 ADCS0 9Fh ADCON1 A/D Result Register — — 05h PORTA — — 85h TRISA — — RA5 RA4 RA3 PORTA Data Direction Register RA2 RA1 xxxx xxxx uuuu uuuu 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. DS35008C-page 54 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 10.0 SPECIAL FEATURES OF THE CPU other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only and is designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. The PIC16C62B/72A devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. • Oscillator Mode Selection • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • SLEEP • Code protection • ID locations • In-circuit serial programming™ (ICSP) Additional information on special features is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). 10.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. These devices have a Watchdog Timer, which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming. FIGURE 10-1: CONFIGURATION WORD CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE bit13 WDTE FOSC1 FOSC0 bit0 bit 13-8 5-4: CP1:CP0: Code Protection bits (2) 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Register: Address: CONFIG 2007h Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE. All of the CP1:CP0 pairs must be given the same value to enable the code protection scheme listed.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 55 PIC16C62B/72A 10.2 Oscillator Configurations 10.2.1 OSCILLATOR TYPES TABLE 10-1 Ranges Tested: The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC 10.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC2 To internal logic Note1: See Table 10-1 and Table 10-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen. FIGURE 10-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 Clock from ext. system PIC16CXXX Open OSC2 Preliminary  0.3%  0.5%  0.5%  0.5%  0.5% CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Osc Type Crystal Freq Cap. Range C1 Cap. Range C2 LP 32 kHz 33 pF 33 pF XT HS 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes at bottom of page. PIC16CXXX C2(1) Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX TABLE 10-2 SLEEP RS(2) OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF Resonators did not have built-in capacitors. OSC1 RF(3) OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF Resonators Used: FIGURE 10-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) XTAL Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz These values are for design guidance only. See notes at bottom of page. In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 10-2). The PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can use an external clock source to drive the OSC1/CLKIN pin (Figure 10-3). DS35008C-page 56 Mode XT HS CRYSTAL OSCILLATOR/CERAMIC RESONATORS C1(1) CERAMIC RESONATORS Crystals Used 32 kHz Epson C-001R32.768K-A ± 20 PPM 200 kHz STD XTL 200.000KHz ± 20 PPM 1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM 20 MHz EPSON CA-301 20.000M-C ± 30 PPM Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: Oscillator performance should be verified when migrating between devices (including PIC16C62A to PIC16C62B and PIC16C72 to PIC16C72A)  1998-2013 Microchip Technology Inc. PIC16C62B/72A 10.2.3 RC OSCILLATOR 10.3 For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 10-4 shows how the R/C combination is connected to the PIC16CXXX. FIGURE 10-4: RC OSCILLATOR MODE VDD Rext OSC1 Cext Internal clock PIC16CXX VSS Fosc/4 Recommended values: OSC2/CLKOUT 3 k  Rext  100 k Cext > 20pF Reset The PIC16CXXX differentiates between various kinds of reset: • • • • • • Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged by any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP, and on Brown-out Reset (BOR). They are not affected by a WDT Wake-up from SLEEP, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared depending on the reset situation, as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 10-5. The PIC devices have a MCLR noise filter in the MCLR reset path. The filter will ignore small pulses. However, a valid MCLR pulse must meet the minimum pulse width (TmcL, Specification #30). No internal reset source (WDT, BOR, POR) willdrive the MCLR pin low.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 57 PIC16C62B/72A FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset S BODEN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. DS35008C-page 58 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 10.4 10.5 Power-On Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified (SVDD, parameter D004). For a slow rise time, see Figure 10-6. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. FIGURE 10-6: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD D Power-up Timer (PWRT) The Power-up Timer provides a fixed nominal time-out (TPWRT, parameter #33) from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See DC parameters for details. 10.6 Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (TOST, parameter #32). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. Note: The OST delay may not occur when the device wakes from SLEEP. R R1 10.7 MCLR C PIC16CXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device’s electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).  1998-2013 Microchip Technology Inc. Brown-Out Reset (BOR) The configuration bit, BODEN, can enable or disable the Brown-Out Reset circuit. If VPP falls below Vbor (parameter #35, about 100S), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a reset may not occur. Once the brown-out occurs, the device will remain in brown-out reset until VDD rises above VBOR. The power-up timer then keeps the device in reset for TPWRT (parameter #33, about 72mS). If VDD should fall below VBOR during TPWRT, the brown-out reset process will restart when VDD rises above VBOR with the power-up timer reset. The power-up timer is always enabled when the brown-out reset circuit is enabled, regardless of the state of the PWRT configuration bit. Preliminary DS35008C-page 59 PIC16C62B/72A 10.8 Time-out Sequence Table 10-5 shows the reset conditions for the STATUS, PCON and PC registers, while Table 10-6 shows the reset conditions for all the registers. When a POR reset occurs, the PWRT delay starts (if enabled). When PWRT ends, the OST counts 1024 oscillator cycles (LP, XT, HS modes only). When OST completes, the device comes out of reset. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. 10.9 Power Control/Status Register (PCON) The BOR bit is unknown on Power-on Reset. If the Brown-out Reset circuit is used, the BOR bit must be set by the user and checked on subsequent resets to see if it was cleared, indicating a Brown-out has occurred. If MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16CXXX device operating in parallel. POR (Power-on Reset Status bit) is cleared on a Power-on Reset and unaffected otherwise. The user Status Register IRP RP1 RP0 TO PD Z DC C POR BOR PCON Register TABLE 10-3 TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Configuration Brown-out Wake-up from SLEEP PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — TABLE 10-4 STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 10-5 RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu PC + 1 uuu0 0uuu ---- --uu 000h 0001 1uuu ---- --u0 uuu1 0uuu ---- --uu Condition WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP PC + 1(1) Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). DS35008C-page 60 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A TABLE 10-6 Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt W 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu INDF 62B 72A N/A N/A N/A TMR0 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PCL 62B 72A 0000h 0000h PC + 1(2) STATUS 62B 72A 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PORTA(4) 62B 72A --0x 0000 --0u 0000 --uu uuuu PORTB(5) 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PORTC(5) 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PCLATH 62B 72A ---0 0000 ---0 0000 ---u uuuu INTCON 62B 72A 0000 000x 0000 000u uuuu uuuu(1) 62B 72A ---- 0000 ---- 0000 ---- uuuu(1) 62B 72A -0-- 0000 -0-- 0000 -u-- uuuu(1) 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PIR1 TMR1L TMR1H 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu T1CON 62B 72A --00 0000 --uu uuuu --uu uuuu TMR2 62B 72A 0000 0000 0000 0000 uuuu uuuu T2CON 62B 72A -000 0000 -000 0000 -uuu uuuu SSPBUF 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 62B 72A 0000 0000 0000 0000 uuuu uuuu CCPR1L 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 62B 72A --00 0000 --00 0000 --uu uuuu ADRES 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 62B 72A 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 62B 72A 1111 1111 1111 1111 uuuu uuuu TRISA 62B 72A --11 1111 --11 1111 --uu uuuu TRISB 62B 72A 1111 1111 1111 1111 uuuu uuuu TRISC 62B 72A 1111 1111 1111 1111 uuuu uuuu 62B 72A ---- 0000 ---- 0000 ---- uuuu PIE1 62B 72A -0-- 0000 -0-- 0000 -u-- uuuu PCON 62B 72A ---- --0q ---- --uq ---- --uq PR2 62B 72A 1111 1111 1111 1111 1111 1111 SSPADD 62B 72A 0000 0000 0000 0000 uuuu uuuu SSPSTAT 62B 72A 0000 0000 0000 0000 uuuu uuuu ADCON1 62B 72A ---- -000 ---- -000 ---- -uuu Legend: Note 1: 2: 3: 4: 5: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). See Table 10-5 for reset value for specific condition. On any device reset, these pins are configured as inputs. This is the value that will be in the port output latch.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 61 PIC16C62B/72A 10.10 Interrupts The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupts, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine, the source of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit must be cleared in software before re-enabling interrupts to avoid recursive interrupts. A global interrupt enable bit, GIE (INTCON) enables or disables all interrupts. When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt flag bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles, depending on when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit, which reenables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. FIGURE 10-7: INTERRUPT LOGIC T0IF T0IE INTF INTE ADIF(1) ADIE(1) SSPIF SSPIE CCP1IF CCP1IE Wake-up (If in SLEEP mode) Interrupt to CPU RBIF RBIE PEIE GIE TMR2IF TMR2IE TMR1IF TMR1IE Note 1: The A/D module is not implemented on the PIC16C62B. DS35008C-page 62 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 10.10.1 INT INTERRUPT 10.11 The external interrupt on RB0/INT pin is edge triggered: either rising, if bit INTEDG (OPTION_REG) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 10.13 for details on SLEEP mode. During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. 10.10.2 TMR0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set flag bit T0IF (INTCON). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON). (Section 4.0) Example 10-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The example: a) b) c) d) e) f) 10.10.3 PORTB INTCON CHANGE Context Saving During Interrupts Stores the W register. Stores the STATUS register in bank 0. Stores the PCLATH register. Executes the interrupt service routine code (User-generated). Restores the STATUS register (and bank select bit). Restores the W and PCLATH registers. An input change on PORTB sets flag bit RBIF (INTCON). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON). (Section 3.2) EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF SWAPF CLRF MOVWF : :(ISR) : SWAPF W_TEMP STATUS,W STATUS STATUS_TEMP ;Copy ;Swap ;bank ;Save STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W  1998-2013 Microchip Technology Inc. W to TEMP register, could be bank one or zero status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register Preliminary DS35008C-page 63 PIC16C62B/72A 10.12 Watchdog Timer (WDT) The WDT time-out period (TWDT, parameter #31) is multiplied by the prescaler ratio, when the prescaler is assigned to the WDT. The prescaler assignment (assigned to either the WDT or Timer0) and prescaler ratio are set in the OPTION_REG register. The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. The WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. . The WDT can be permanently disabled by clearing configuration bit WDTE (Section 10.1). FIGURE 10-8: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 4-2) 0 WDT Timer Postscaler M U X 1 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure 4-2) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. FIGURE 10-9: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name 2007h Config. bits 81h OPTION_REG Bit 7 RBPU Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. DS35008C-page 64 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 10.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS) is cleared, the TO (STATUS) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC, parameter D042). 10.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some Peripheral Interrupts. External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device resumes execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, a NOP should follow the SLEEP instruction. 10.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP capture mode interrupt. Special event trigger (Timer1 in asynchronous mode using an external clock. CCP1 is in compare mode). SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in slave mode (SPI/I2C). USART RX or TX (synchronous slave mode). Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 65 PIC16C62B/72A FIGURE 10-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON) Interrupt Latency (Note 2) GIE bit (INTCON) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 10.14 PC+1 PC+2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference. Program Verification/Code Protection If the code protection bits have not been programmed, the on-chip program memory can be read out for verification purposes. Note: 10.15 Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. For ROM devices, these values are submitted along with the ROM code. 10.16 In-Circuit Serial Programming™ PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three more lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSP™) Guide, DS30277. DS35008C-page 66 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 11.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 11-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 11-2 lists the instructions recognized by the MPASM assembler. Figure 11-1 shows the general formats that the instructions can have. Note: All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 11-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. TABLE 11-1 Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) Description f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address OPCODE FIELD DESCRIPTIONS Field To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions. 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 8 7 OPCODE 0 k (literal) k = 8-bit immediate value PC Program Counter TO Time-out bit PD Power-down bit Z Zero bit DC Digit Carry bit OPCODE C Carry bit k = 11-bit immediate value CALL and GOTO instructions only 13 The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations 11 10 0 k (literal) A description of each instruction is available in the PIC® MCU Mid-Range Reference Manual, (DS33023). All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 67 PIC16C62B/72A TABLE 11-2 PIC16CXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z C C C,DC,Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk 1,2 1,2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W C,DC,Z Z TO,PD Z TO,PD C,DC,Z Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS35008C-page 68 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 11.1 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [label] ADDLW Syntax: [label] ANDWF Operands: 0  k  255 Operands: 0  f  127 d  Operation: (W) .AND. (f)  (destination) Status Affected: Z Description: AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. k Operation: (W) + k  (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. f,d BCF Bit Clear f Syntax: [label] BCF 0  f  127 d  Operands: 0  f  127 0b7 Operation: (W) + (f)  (destination) Operation: 0  (f) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. Description: Bit 'b' in register 'f' is cleared. ANDLW AND Literal with W BSF Bit Set f Syntax: [label] ANDLW Syntax: [label] BSF Operands: 0  f  127 0b7 Operation: 1  (f) ADDWF Add W and f Syntax: [label] ADDWF Operands: f,d k Operands: 0  k  255 Operation: (W) .AND. (k)  (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register.  1998-2013 Microchip Technology Inc. f,b f,b Status Affected: None Description: Bit 'b' in register 'f' is set. Preliminary DS35008C-page 69 PIC16C62B/72A BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [label] BTFSS f,b Syntax: [label] CLRF Operands: 0  f  127 0b VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA and PORTB (combined) .................................................................................200 mA Maximum current sourced by PORTA and PORTB (combined)............................................................................200 mA Maximum current sunk by PORTC........................................................................................................................200 mA Maximum current sourced by PORTC ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 81 PIC16C62B/72A FIGURE 13-1: PIC16C62B/72A-20 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC16CXXX PIC16CXXX-20 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 20 MHz Frequency FIGURE 13-2: PIC16LC62B/72A AND PIC16C62B/72A/JW VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V 4.5 V 4.0 V PIC16LCXXX-04 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz 10 MHz Frequency FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Fmax is no greater than 10 MHz. DS35008C-page 82 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A FIGURE 13-3: PIC16C62B/72A-04 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC16CXXX-04 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz Frequency  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 83 PIC16C62B/72A 13.1 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA +125°C for extended Min Typ† Max Units 4.0 4.5 5.5 5.5 5.5 V V V Conditions D001 D001A VDD Supply Voltage VBOR* - D002* VDR RAM Data Retention Voltage (Note 1) - 1.5 - V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal - VSS - V D004* SVDD D004A* VDD Rise Rate to ensure internal Power-on Reset signal 0.05 TBD - - D005 VBOR Brown-out Reset voltage trip point 3.65 - 4.35 V D010 IDD Supply Current (Note 2, 5) - 2.7 5 mA XT, RC osc modes FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 mA HS osc mode FOSC = 20 MHz, VDD = 5.5V D021 D021B - 10.5 1.5 1.5 2.5 42 16 19 19 A A A A VDD = 4.0V, WDT enabled,-40C to +85C VDD = 4.0V, WDT disabled, 0C to +70C VDD = 4.0V, WDT disabled,-40C to +85C VDD = 4.0V, WDT disabled,-40C to +125C Module Differential Current (Note 6) D022* IWDT Watchdog Timer D022A* IBOR Brown-out Reset - 6.0 TBD 20 200 A A WDTE BIT SET, VDD = 4.0V BODEN bit set, VDD = 5.0V D013 D020 IPD Power-down Current (Note 3, 5) XT, RC and LP osc mode HS osc mode BOR enabled (Note 7) See section on Power-on Reset for details V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details BODEN bit set * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will perform a brown-out reset when VDD falls below VBOR. DS35008C-page 84 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 13.2 DC Characteristics: PIC16LC62B/72A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial Min Typ† Max Units 2.5 VBOR* - 5.5 5.5 V V Conditions D001 VDD Supply Voltage D002* VDR RAM Data Retention Voltage (Note 1) - 1.5 - V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal - VSS - V D004* SVDD D004A* VDD Rise Rate to ensure internal Power-on Reset signal 0.05 TBD - - D005 VBOR Brown-out Reset voltage trip point 3.65 - 4.35 V D010 IDD Supply Current (Note 2, 5) - 2.0 3.8 mA XT, RC osc modes FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP OSC MODE FOSC = 32 kHz, VDD = 3.0V, WDT disabled - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C - 6.0 TBD 20 200 A A WDTE BIT SET, VDD = 4.0V BODEN bit set, VDD = 5.0V D010A D020 D021 D021A IPD Power-down Current (Note 3, 5) Module Differential Current (Note 6) D022* IWDT Watchdog Timer D022A* IBOR Brown-out Reset LP, XT, RC osc modes (DC - 4 MHz) BOR enabled (Note 7) See section on Power-on Reset for details V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWRTE bit set) See section on Power-on Reset for details BODEN bit set * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will perform a brown-out reset when VDD falls below VBOR.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 85 PIC16C62B/72A 13.3 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) PIC16LC62B/72A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Sym Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA +125°C for extended Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2 Characteristic Min Typ† Max Units Conditions Input Low Voltage VIL I/O ports D030 D030A with TTL buffer VSS Vss - 0.15VDD 0.8V V V For entire VDD range 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP modes) Vss - 0.3VDD V Note1 2.0 - VDD V 4.5V  VDD  5.5V 0.25VD + 0.8V - Vdd V For entire VDD range For entire VDD range Input High Voltage VIH D040 I/O ports - with TTL buffer D040A D D041 with Schmitt Trigger buffer 0.8VDD - VDD V D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP modes) 0.7VDD - VDD V D043 OSC1 (in RC mode) 0.9VDD - Vdd V I/O ports - - 1 A Vss VPIN VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc modes 50 250 400 A VDD = 5V, VPIN = VSS - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C Note1 Input Leakage Current (Notes 2, 3) D060 IIL D070 IPURB D080 VOL PORTB weak pull-up current Output Low Voltage I/O ports * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the device be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS35008C-page 86 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A DC CHARACTERISTICS Param No. Sym D083 Characteristic OSC2/CLKOUT (RC osc mode) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA +125°C for extended Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2 Min Typ† Max Units Conditions - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C - - 8.5 V RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. Output High Voltage D090 VOH D092 D150* I/O ports (Note 3) OSC2/CLKOUT (RC osc mode) VOD Open-Drain High Voltage Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin - - 15 pF D101 CIO All I/O pins and OSC2 (in RC mode) - - 50 pF D102 Cb SCL, SDA in I2C mode - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the device be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 87 PIC16C62B/72A 13.4 AC (Timing) Characteristics 13.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T Time osc OSC1 T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR P Period Uppercase letters and their meanings: S F Fall H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance AA output access High High BUF Bus free Low Low Hold SU Setup DAT DATA input hold STO STOP condition STA START condition I2C only TCC:ST (I2C specifications only) CC HD ST DS35008C-page 88 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A 13.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 13-1 apply to all timing specifications unless otherwise noted. Figure 13-4 specifies the load conditions for the timing specifications. TABLE 13-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA +125°C for extended Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. LC parts operate for commercial/industrial temp’s only. FIGURE 13-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS CL = 50 pF 15 pF  1998-2013 Microchip Technology Inc. Preliminary for all pins except OSC2/CLKOUT for OSC2 output DS35008C-page 89 PIC16C62B/72A 13.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 13-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 13-2: Param No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Sym Fosc Characteristic External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) Min Typ† Max Units Conditions DC — 4 MHz RC and XT osc modes DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz 250 — — ns RC and XT osc modes LP osc mode 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3* TosL, TosH External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator 4* TosR, TosF External Clock in (OSC1) Rise or Fall Time 2.5 — — s LP oscillator 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS35008C-page 90 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A FIGURE 13-6: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 13-4 for load conditions. TABLE 13-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym No. Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 16* TckH2ioI Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid 18* TosH2ioI 18A* Port in hold after CLKOUT  OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) 0 — — ns — 50 150 ns PIC16CXX 100 — — ns PIC16LCXX 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16CXX — 10 40 ns PIC16LCXX — — 80 ns TioF Port output fall time PIC16CXX — 10 40 ns — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns 20A* 21* PIC16LCXX 21A* * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ††These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 91 PIC16C62B/72A FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 13-4 for load conditions. FIGURE 13-8: BROWN-OUT RESET TIMING BVDD VDD TABLE 13-4: Param No. 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Sym Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +125°C 32 Tost Oscillator Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O Hi-impedance from MCLR Low or WDT reset — — 2.1 s 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS35008C-page 92 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A FIGURE 13-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 13-4 for load conditions. TABLE 13-5: Param No. 40* TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Sym Tt0H Characteristic T0CKI High Pulse Width No Prescaler With Prescaler 41* Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* Tt0P T0CKI Period 45* 46* 47* Tt1H Tt1L Tt1P T1CKI High Time T1CKI Low Time T1CKI input period Max Units 0.5TCY + 20 — — ns 10 — — ns 0.5TCY + 20 — — ns 10 — — ns — ns — ns N = prescale value (2, 4,..., 256) Must also meet parameter 47 0.5TCY + 20 — — ns 15 — — ns PIC16LCXX 25 — — ns Asynchronous PIC16CXX 30 — — ns PIC16LCXX 50 — — ns 0.5TCY + 20 — — ns Synchronous, Prescaler = 1 Synchronous, Prescaler = 2,4,8 PIC16CXX 15 — — ns PIC16LCXX 25 — — ns Asynchronous PIC16CXX 30 — — ns PIC16LCXX 50 — — ns — — ns PIC16CXX GREATER OF: 30 OR TCY + 40 N PIC16LCXX GREATER OF: 50 OR TCY + 40 N 60 — — PIC16LCXX 100 — — ns DC — 200 kHz 2Tosc — 7Tosc — TCKEZtmr1 Delay from external clock edge to timer increment Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) PIC16CXX Timer1 oscillator input frequency range (oscillator enabled by setting bit T1OSCEN) Must also meet parameter 42 — PIC16CXX Ft1 Must also meet parameter 42 — Synchronous, Prescaler = 1 Synchronous Conditions TCY + 40 Synchronous, Prescaler = 2,4,8 Asynchronous 48 Typ† Greater of: 20 or TCY + 40 N No Prescaler With Prescaler Min ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 93 PIC16C62B/72A FIGURE 13-10: CAPTURE/COMPARE/PWM TIMINGS CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 13-4 for load conditions. TABLE 13-6: Param No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS Sym TccL TccH Characteristic CCP1 input low time CCP1 input high time Min No Prescaler With Prescaler 0.5TCY + 20 — — ns PIC16CXX 10 — — ns PIC16LCXX 20 — — ns 0.5TCY + 20 — — ns 10 — — ns No Prescaler With Prescaler PIC16CXX PIC16LCXX 52* TccP CCP1 input period 53* TccR CCP1 output rise time 54* TccF CCP1 output fall time Typ† Max Units 20 — — ns 3TCY + 40 N — — ns PIC16CXX — 10 25 ns PIC16LCXX — 25 45 ns PIC16CXX — 10 25 ns PIC16LCXX — 25 45 ns Conditions N = prescale value (1,4, or 16) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS35008C-page 94 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A FIGURE 13-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 13-4 for load conditions. TABLE 13-7: Param. No. EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Symbol Characteristic Min 70 TssL2scH, SS to SCK or SCK input TssL2scL TCY 71 TscH 71A 72 TscL 72A Typ† Max Units — — ns SCK input high time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns SCK input low time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns 100 — — ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — — ns 75 TdoR SDO data output rise time PIC16CXX — 10 25 ns — 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 78 TscR SCK output rise time (master mode) PIC16CXX — 10 25 ns PIC16LCXX — 20 45 ns PIC16LCXX 79 TscF 80 TscH2doV, SDO data output valid TscL2doV after SCK edge SCK output fall time (master mode) Conditions — 10 25 ns PIC16CXX — — 50 ns PIC16LCXX — — 100 ns Note 1 Note 1 Note 1 † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 95 PIC16C62B/72A FIGURE 13-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO LSb BIT6 - - - - - -1 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: TABLE 13-8: Param. No. 71 EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Symbol TscH 71A 72 Refer to Figure 13-4 for load conditions. TscL 72A Characteristic Min Typ† Max Units SCK input high time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns SCK input low time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns 100 — — ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — — ns 75 TdoR SDO data output rise time — 10 25 ns 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 20 45 ns — 10 25 ns — — 50 ns — 100 ns — — ns 79 TscF 80 TscH2doV, SDO data output valid TscL2doV after SCK edge 81 PIC16CXX PIC16LCXX PIC16CXX PIC16LCXX SCK output fall time (master mode) PIC16CXX PIC16LCXX TdoV2scH, SDO data output setup to SCK edge TdoV2scL TCY Conditions Note 1 Note 1 Note 1 † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. DS35008C-page 96 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A FIGURE 13-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: TABLE 13-9: Param. No. Refer to Figure 13-4 for load conditions. EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0) Symbol Characteristic Min 70 TssL2scH, SS to SCK or SCK input TssL2scL TCY 71 TscH 71A 72 TscL 72A Typ† Max Units — — ns SCK input high time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns SCK input low time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns 100 — — ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — — ns 75 TdoR SDO data output rise time PIC16CXX — 10 25 ns 20 45 ns PIC16LCXX 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 20 45 ns — 10 25 ns — — 50 ns — 100 ns — — ns 79 TscF 80 TscH2doV, SDO data output valid TscL2doV after SCK edge 83 PIC16CXX PIC16LCXX SCK output fall time (master mode) PIC16CXX PIC16LCXX TscH2ssH, SS after SCK edge TscL2ssH 1.5TCY + 40 Conditions Note 1 Note 1 Note 1 † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 97 PIC16C62B/72A FIGURE 13-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 NOTE: Refer to Figure 13-4 for load conditions. TABLE 13-10: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. No. Symbol Characteristic Min TCY Typ† Max Units 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns SCK input low time (slave mode) Continuous 1.25TCY + 30 — — ns Single Byte 40 — — ns Note 1 Note 1 71A 72 TscL 72A — — Conditions ns 73A TB2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — — ns 75 TdoR SDO data output rise time — 10 25 ns 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) 80 TscH2doV, SDO data output valid TscL2doV after SCK edge TssL2doV 82 83 SDO data output valid after SS edge TscH2ssH, SS after SCK edge TscL2ssH PIC16CXX PIC16LCXX PIC16CXX — 20 45 ns — 10 25 ns PIC16CXX — — 50 ns PIC16LCXX — — 100 ns PIC16CXX — — 50 ns PIC16LCXX — — 100 ns 1.5TCY + 40 — — ns PIC16LCXX Note 1 † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. DS35008C-page 98 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A FIGURE 13-15: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 13-4 for load conditions. TABLE 13-11: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90* TSU:STA 91* THD:STA 92* TSU:STO 93 THD:STO * Characteristic START condition 100 kHz mode Min Ty Max Unit p s 4700 — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns These parameters are characterized but not tested.  1998-2013 Microchip Technology Inc. Preliminary DS35008C-page 99 PIC16C62B/72A FIGURE 13-16: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 13-4 for load conditions. TABLE 13-12: I2C BUS DATA REQUIREMENTS Param. No. 100* Sym THIGH Characteristic Clock high time Min Max Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.5TCY — SSP Module 101* TLOW Clock low time SSP Module 102* 103* 90* 91* 106* 107* 92* 109* 110* TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Cb Conditions SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF START condition setup time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s Only relevant for repeated START condition START condition hold time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 100 kHz mode 250 — ns 400 kHz mode 100 — ns STOP condition setup 100 kHz mode time 400 kHz mode 4.7 — s 0.6 — s Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF Data input setup time Bus free time Bus capacitive loading Cb is specified to be from 10-400 pF After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT  250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. DS35008C-page 100 Preliminary  1998-2013 Microchip Technology Inc. PIC16C62B/72A TABLE 13-13: A/D CONVERTER CHARACTERISTICS: PIC16C72A-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C72A-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC72A-04 (COMMERCIAL, INDUSTRIAL) Param Sym No. Characteristic Min Typ† Max Units Conditions — — 8-bits bit VREF = VDD = 5.12V, VSS  VAIN  VREF A01 NR A02 EABS Total Absolute error — —