PIC16C63-10I/SP

PIC16C6X 8-Bit CMOS Microcontrollers Devices included in this data sheet: • PIC16C61 • PIC16C64A • PIC16C62 • PIC16CR64 • PIC16C62A • PIC16C65 • PIC16CR62 • PIC16C65A • PIC16C63 • PIC16CR65 • PIC16CR63 • PIC16C66 • PIC16C64 • PIC16C67 • Low-power, high-speed CMOS EPROM/ROM technology • Fully static design • Wide operating voltage range: 2.5V to 6.0V • Commercial, Industrial, and Extended temperature ranges • Low-power consumption:  < 2 mA @ 5V, 4 MHz  15 A typical @ 3V, 32 kHz  < 1 A typical standby current PIC16C6X Microcontroller Core Features: PIC16C6X Peripheral Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two-cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • Interrupt capability • Eight level deep hardware stack • Direct, indirect, and relative addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code-protection • Power saving SLEEP mode • Selectable oscillator options • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture/Compare/PWM (CCP) module(s) • Capture is 16-bit, max resolution is 12.5 ns, Compare is 16-bit, max resolution is 200 ns, PWM max resolution is 10-bit. • Synchronous Serial Port (SSP) with SPI and I2C • Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) • Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls • Brown-out detection circuitry for Brown-out Reset (BOR) PIC16C6X Features Program Memory (EPROM) x 14 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 1K 2K 2K — 4K — 2K 2K — 4K 4K — 8K 8K (ROM) x 14 — — — 2K — 4K — — 2K — — 4K — — Data Memory (Bytes) x 8 36 128 128 128 192 192 128 128 128 192 192 192 368 368 I/O Pins 13 22 22 22 22 22 33 33 33 33 33 33 22 33 Parallel Slave Port — — — — — — Yes Yes Yes Yes Yes Yes — Yes Capture/Compare/PWM Module(s) — 1 1 1 2 2 1 1 1 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 Timer Modules 1 3 3 Serial Communication — SPI/ I2C SPI/ I2C SPI/ SPI/I2C, SPI/I2C, SPI/ I2C USART USART I2C SPI/ I2C SPI/ SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, I2C USART USART USART USART USART In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes Yes Yes Brown-out Reset — — Yes Yes Yes Yes — Yes Interrupt Sources 3 7 7 7 10 10 8 8 Sink/Source Current (mA) 25/20 25/25 25/25 25/25 25/25  1997-2013 Microchip Technology Inc. 3 Yes Yes Yes Yes Yes Yes — Yes Yes Yes Yes 8 11 11 11 10 11 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 25/25 DS30234E-page 1 PIC16C6X Pin Diagrams PDIP, SOIC, Windowed CERDIP SDIP, SOIC, SSOP, Windowed CERDIP (300 mil) RA2 1 18 RA1 RA3 2 17 RA0 RA4/T0CKI 3 16 OSC1/CLKIN MCLR/VPP 4 15 OSC2/CLKOUT VSS 5 14 VDD RB0/INT 6 13 RB7 RB1 7 12 RB6 RB2 8 11 RB5 RB3 9 10 RB4 MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS PIC16C61 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 OSC1/CLKIN OSC2/CLKOUT 9 10 20 19 RC0/T1OSI/T1CKI RC1/T1OSO RC2/CCP1 RC3/SCK/SCL 11 12 13 14 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA PIC16C62 SDIP, SOIC, SSOP, Windowed CERDIP (300 mil) MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL 1 2 3 4 28 27 26 25 5 6 7 8 9 10 11 12 13 14 24 23 22 21 20 19 18 17 16 15 SDIP, SOIC, Windowed CERDIP (300 mil) RB7 RB6 RB5 MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS VSS OSC1/CLKIN RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC6 RC5/SDO RC4/SDI/SDA PIC16C62A PIC16CR62 1 2 3 4 28 27 26 25 5 6 7 8 9 10 11 12 13 14 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA PIC16C63 PIC16CR63 PIC16C66 PDIP, Windowed CERDIP MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSI/T1CKI RC1/T1OSO RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC16C64 DS30234E-page 2 RB7 MCLR/VPP RB6 RA0 RB5 RA1 RB4 RA2 RB3 RA3 RB2 RA4/T0CKI RB1 RA5/SS RB0/INT RE0/RD VDD RE1/WR VSS RE2/CS VDD RD7/PSP7 VSS RD6/PSP6 RD5/PSP5 OSC1/CLKIN RD4/PSP4 OSC2/CLKOUT RC7 RC0/T1OSO/T1CKI RC6 RC1/T1OSI RC5/SDO RC2/CCP1 RC4/SDI/SDA RC3/SCK/SCL RD3/PSP3 RD0/PSP0 RD2/PSP2 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC16C64A PIC16CR64 RB7 MCLR/VPP RB6 RA0 RB5 RA1 RB4 RA2 RB3 RA3 RB2 RA4/T0CKI RB1 RA5/SS RB0/INT RE0/RD VDD RE1/WR VSS RE2/CS VDD RD7/PSP7 VSS RD6/PSP6 RD5/PSP5 OSC1/CLKIN RD4/PSP4 OSC2/CLKOUT RC7 RC0/T1OSO/T1CKI RC6 RC1/T1OSI/CCP2 RC5/SDO RC2/CCP1 RC4/SDI/SDA RC3/SCK/SCL RD3/PSP3 RD0/PSP0 RD2/PSP2 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 PIC16C65 PIC16C65A PIC16CR65 PIC16C67  1997-2013 Microchip Technology Inc. PIC16C6X PLCC RC7 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 6 5 4 3 2 1 44 43 42 41 40 MQFP RA3 RA2 RA1 RA0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC RC6 RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSO NC Pin Diagrams (Cont.’d) 1 2 3 4 5 6 7 8 9 10 11 PIC16C64 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSI/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS RE1/WR RE0/RD RA5/SS RA4/T0CKI RA4/T0CKI RA5/SS RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSI/T1CKI NC 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 PIC16C64 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7 28 27 26 25 24 23 22 21 20 19 18 22 21 20 19 18 17 16 15 14 13 12 NC RC6 RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSO RA3 RA2 RA1 RA0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC MQFP, TQFP (PIC16C64A only) 1 2 3 4 5 6 7 8 9 10 11 PIC16C64A PIC16CR64 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS RE1/WR RE0/RD RA5/SS RA4/T0CKI RA4/T0CKI RA5/SS RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC 7 8 9 10 11 12 13 14 15 16 17 PIC16C64A PIC16CR64 39 38 37 36 35 34 33 32 31 30 29 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7 39 38 37 36 35 34 33 32 31 30 29 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT 28 27 26 25 24 23 22 21 20 19 18 RC7 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 6 5 4 3 2 1 44 43 42 41 40 RC6 RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI NC RA3 RA2 RA1 RA0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC PLCC NC RC6 RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI RA3 RA2 RA1 RA0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC MQFP, TQFP (Not on PIC16C65) 1 2 3 4 5 6 7 8 9 10 11 PIC16C65 PIC16C65A PIC16CR65 PIC16C67 22 21 20 19 18 17 16 15 14 13 12 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/CS RE1/WR RE0/RD RA5/SS RA4/T0CKI RA4/T0CKI RA5/SS RE0/RD RE1/WR RE2/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC RA3 RA2 RA1 RA0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC 7 8 9 10 11 12 13 14 15 16 17 PIC16C65 PIC16C65A PIC16CR65 PIC16C67 NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI /CCP2 RA3 RA2 RA1 RA0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC  1997-2013 Microchip Technology Inc. 33 32 31 30 29 28 27 26 25 24 23 28 27 26 25 24 23 22 21 20 19 18 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 6 5 4 3 2 1 44 43 42 41 40 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC PLCC DS30234E-page 3 PIC16C6X Table Of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 General Description ....................................................................................................................................................................... 5 PIC16C6X Device Varieties ........................................................................................................................................................... 7 Architectural Overview ................................................................................................................................................................... 9 Memory Organization................................................................................................................................................................... 19 I/O Ports....................................................................................................................................................................................... 51 Overview of Timer Modules ......................................................................................................................................................... 63 Timer0 Module ............................................................................................................................................................................. 65 Timer1 Module ............................................................................................................................................................................. 71 Timer2 Module ............................................................................................................................................................................. 75 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................... 77 Synchronous Serial Port (SSP) Module ....................................................................................................................................... 83 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module........................................................................ 105 Special Features of the CPU ..................................................................................................................................................... 123 Instruction Set Summary............................................................................................................................................................ 143 Development Support ................................................................................................................................................................ 159 Electrical Characteristics for PIC16C61 ..................................................................................................................................... 163 DC and AC Characteristics Graphs and Tables for PIC16C61.................................................................................................. 173 Electrical Characteristics for PIC16C62/64 ................................................................................................................................ 183 Electrical Characteristics for PIC16C62A/R62/64A/R64 ............................................................................................................ 199 Electrical Characteristics for PIC16C65 ..................................................................................................................................... 215 Electrical Characteristics for PIC16C63/65A ............................................................................................................................. 231 Electrical Characteristics for PIC16CR63/R65........................................................................................................................... 247 Electrical Characteristics for PIC16C66/67 ................................................................................................................................ 263 DC and AC Characteristics Graphs and Tables for: PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64, PIC16C65A, PIC16C66, PIC16C67 ........................................................................................................................................... 281 25.0 Packaging Information ............................................................................................................................................................... 291 Appendix A: Modifications .............................................................................................................................................................. 307 Appendix B: Compatibility .............................................................................................................................................................. 307 Appendix C: What’s New................................................................................................................................................................ 308 Appendix D: What’s Changed ........................................................................................................................................................ 308 Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 309 Pin Compatibility ................................................................................................................................................................................ 315 Index .................................................................................................................................................................................................. 317 List of Equation and Examples........................................................................................................................................................... 326 List of Figures..................................................................................................................................................................................... 326 List of Tables...................................................................................................................................................................................... 330 Reader Response .............................................................................................................................................................................. 334 PIC16C6X Product Identification System........................................................................................................................................... 335 For register and module descriptions in this data sheet, device legends show which devices apply to those sections. For example, the legend below shows that some features of only the PIC16C62A, PIC16CR62, PIC16C63, PIC16C64A, PIC16CR64, and PIC16C65A are described in this section. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30234E-page 4  1997-2013 Microchip Technology Inc. PIC16C6X 1.0 GENERAL DESCRIPTION The PIC16CXX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C61 device has 36 bytes of RAM and 13 I/O pins. In addition a timer/counter is available. The PIC16C62/62A/R62 devices have 128 bytes of RAM and 22 I/O pins. In addition, several peripheral features are available, including: three timer/counters, one Capture/Compare/PWM module and one serial port. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The PIC16C63/R63 devices have 192 bytes of RAM, while the PIC16C66 has 368 bytes. All three devices have 22 I/O pins. In addition, several peripheral features are available, including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also know as a Serial Communications Interface or SCI. The PIC16C64/64A/R64 devices have 128 bytes of RAM and 33 I/O pins. In addition, several peripheral features are available, including: three timer/counters, one Capture/Compare/PWM module and one serial port. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. An 8-bit Parallel Slave Port is also provided. The PIC16C65/65A/R65 devices have 192 bytes of RAM, while the PIC16C67 has 368 bytes. All four devices have 33 I/O pins. In addition, several peripheral features are available, including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Universal Synchronous Asynchronous Receiver Transmit-  1997-2013 Microchip Technology Inc. ter (USART) is also known as a Serial Communications Interface or SCI. An 8-bit Parallel Slave Port is also provided. The PIC16C6X device family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers a power saving mode. The user can wake the chip from SLEEP through several external and internal interrupts, and resets. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup. A UV erasable CERDIP packaged version is ideal for code development, while the cost-effective One-Time-Programmable (OTP) version is suitable for production in any volume. The PIC16C6X family fits perfectly in applications ranging from high-speed automotive and appliance control to low-power remote sensors, keyboards and telecom processors. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high performance, ease-of-use, and I/O flexibility make the PIC16C6X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, serial communication, capture and compare, PWM functions, and co-processor applications). 1.1 Family and Upward Compatibility Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to PIC16CXX family of devices (Appendix B). 1.2 Development Support PIC16C6X devices are supported by the complete line of Microchip Development tools. Please refer to Section 15.0 for more details about Microchip’s development tools. DS30234E-page 5 PIC16C6X TABLE 1-1: PIC16C6X FAMILY OF DEVICES PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63 Maximum Frequency of Operation (MHz) 20 20 20 20 20 EPROM Program Memory (x14 words) 1K 2K — 4K — ROM Program Memory (x14 words) — — 2K — 4K Data Memory (bytes) 36 128 128 192 192 Timer Module(s) TMR0 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/ Peripherals PWM Module(s) — 1 1 2 2 Serial Port(s) (SPI/I2C, USART) — SPI/I2C SPI/I2C SPI/I2C, USART SPI/I2C USART Clock Memory Features Parallel Slave Port — — — — — Interrupt Sources 3 7 7 10 10 I/O Pins 13 22 22 22 22 Voltage Range (Volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Yes Brown-out Reset — Yes Yes Yes Yes Packages 18-pin DIP, SO 28-pin SDIP, SOIC, SSOP 28-pin SDIP, SOIC, SSOP 28-pin SDIP, 28-pin SDIP, SOIC SOIC PIC16C64A Clock Memory PIC16C65A PIC16CR65 PIC16C66 PIC16C67 20 20 20 20 20 20 EPROM Program Memory (x14 words) 2K — 4K — 8K 8K ROM Program Memory (x14 words) — 2K — 4K — — Data Memory (bytes) 128 128 192 192 368 368 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 1 1 2 2 2 2 SPI/I2C SPI/I2C SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART Capture/Compare/PWM ModPeripherals ule(s) Serial Port(s) (SPI/I2C, USART) Features PIC16CR64 Maximum Frequency of Operation (MHz) Parallel Slave Port Yes Yes Yes Yes — Yes Interrupt Sources 8 8 11 11 10 11 I/O Pins 33 33 33 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Yes Yes Packages 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, 44-pin MQFP, TQFP MQFP, TQFP MQFP, TQFP PLCC, MQFP, TQFP 28-pin SDIP, 40-pin DIP; SOIC 44-pin PLCC, MQFP, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7. DS30234E-page 6  1997-2013 Microchip Technology Inc. PIC16C6X 2.0 PIC16C6X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C6X Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C6X family of devices, there are four device “types” as indicated in the device number: 1. 2. 3. 4. 2.1 C, as in PIC16C64. These devices have EPROM type memory and operate over the standard voltage range. LC, as in PIC16LC64. These devices have EPROM type memory and operate over an extended voltage range. CR, as in PIC16CR64. These devices have ROM program memory and operate over the standard voltage range. LCR, as in PIC16LCR64. These devices have ROM program memory and operate over an extended voltage range. UV Erasable Devices The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C6X. 2.2 One-Time-Programmable (OTP) Devices 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number. ROM devices do not allow serialization information in the program memory space. The user may have this information programmed in the data memory space. For information on submitting ROM code, please contact your regional sales office. 2.5 Read Only Memory (ROM) Devices Microchip offers masked ROM versions of several of the highest volume parts, thus giving customers a low cost option for high volume, mature products. For information on submitting ROM code, please contact your regional sales office. The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.  1997-2013 Microchip Technology Inc. DS30234E-page 7 PIC16C6X NOTES: DS30234E-page 8  1997-2013 Microchip Technology Inc. PIC16C6X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data may be fetched from the same memory using the same bus. Separating program and data busses further allows instructions to be sized differently than 8-bit wide data words. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (200 ns @ 20 MHz) except for program branches. The PIC16C61 addresses 1K x 14 of program memory. The PIC16C62/62A/R62/64/64A/R64 address 2K x 14 of program memory, and the PIC16C63/R63/65/65A/R65 devices address 4K x 14 of program memory. The PIC16C66/67 address 8K x 14 program memory. All program memory is internal. The PIC16CXX device contains an 8-bit ALU and working register (W). The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register), the other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending upon the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. Bits C and DC operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. The PIC16CXX can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of “special optimal situations” makes programming with the PIC16CXX simple yet efficient, thus significantly reducing the learning curve.  1997-2013 Microchip Technology Inc. DS30234E-page 9 PIC16C6X FIGURE 3-1: PIC16C61 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RAM File Registers 36 x 8 8 Level Stack (13-bit) 1K x 14 8 Data Bus Program Counter EPROM RAM Addr (1) RA4/T0CKI PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg RB0/INT RB7:RB1 STATUS reg 8 Power-up Timer Instruction Decode & Control Timing Generation 3 Oscillator Start-up Timer Power-on Reset Watchdog Timer MUX ALU 8 W reg OSC1/CLKIN OSC2/CLKOUT Timer0 MCLR VDD, VSS Note 1: Higher order bits are from the STATUS register. DS30234E-page 10  1997-2013 Microchip Technology Inc. PIC16C6X FIGURE 3-2: PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM 13 Program Bus 14 PORTA RA0 RA1 RA2 RA3 RAM File Registers 128 x 8 8 Level Stack (13-bit) 2K x 14 8 Data Bus Program Counter EPROM/ ROM Program Memory RAM Addr(1) RA4/T0CKI RA5/SS PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 PORTC Power-up Timer 3 Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation Watchdog Timer Brown-out Reset(3) OSC1/CLKIN OSC2/CLKOUT MCLR RC0/T1OSO/T1CKI(4) RC1/T1OSI(4) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 MUX ALU 8 W reg PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VDD, VSS Parallel Slave Port PORTE RE0/RD Timer1 Timer2 RE1/WR CCP1 RE2/CS (Note 2) Timer0 Note 1: 2: 3: 4: Synchronous Serial Port Higher order bits are from the STATUS register. PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C62/62A/R62. Brown-out Reset is not available on the PIC16C62/64. Pin functions T1OSI and T1OSO are swapped on the PIC16C62/64.  1997-2013 Microchip Technology Inc. DS30234E-page 11 PIC16C6X FIGURE 3-3: PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RAM File Registers 192 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr(1) RA5/SS PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 PORTC Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT 3 Oscillator Start-up Timer Power-on Reset Watchdog Timer ALU 8 W reg PORTD Brown-out Reset(3) MCLR RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MUX VDD, VSS Parallel Slave Port RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE RE0/RD RE1/WR Timer0 Timer1 Timer2 RE2/CS (Note 2) USART Synchronous Serial Port CCP1 CCP2 Note 1: Higher order bits are from the STATUS register. 2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C63/R63. 3: Brown-out Reset is not available on the PIC16C65. DS30234E-page 12  1997-2013 Microchip Technology Inc. PIC16C6X FIGURE 3-4: PIC16C66/67 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RAM File Registers 368 x 8 8 Level Stack (13-bit) 8K x 14 8 Data Bus Program Counter EPROM RAM Addr(1) RA5/SS PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 PORTC Power-up Timer 3 Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation Watchdog Timer OSC1/CLKIN OSC2/CLKOUT ALU 8 W reg PORTD Brown-out Reset MCLR RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MUX VDD, VSS Parallel Slave Port RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE RE0/RD RE1/WR Timer0 Timer1 Timer2 RE2/CS (Note 2) USART Synchronous Serial Port CCP1 CCP2 Note 1: Higher order bits are from the STATUS register. 2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C66.  1997-2013 Microchip Technology Inc. DS30234E-page 13 PIC16C6X TABLE 3-1: PIC16C61 PINOUT DESCRIPTION Pin Name DIP Pin# SOIC Pin# Pin Type Buffer Type Description ST/CMOS(1) Oscillator crystal input/external clock source input. OSC1/CLKIN 16 16 I OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 4 4 I/P ST Master clear reset input or programming voltage input. This pin is an active low reset to the device. RA0 17 17 I/O TTL RA1 18 18 I/O TTL RA2 1 1 I/O TTL RA3 2 2 I/O TTL RA4/T0CKI 3 3 I/O ST PORTA is a bi-directional I/O port. RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 6 6 I/O TTL/ST(2) RB1 7 7 I/O TTL RB2 8 8 I/O TTL RB3 9 9 I/O TTL RB4 10 10 I/O TTL Interrupt on change pin. RB5 11 11 I/O TTL Interrupt on change pin. RB6 12 12 I/O TTL/ST(3) RB7 13 13 I/O TTL/ST(3) VSS 5 5 P — Ground reference for logic and I/O pins. VDD 14 14 P — Positive supply for logic and I/O pins. RB0 can also be the external interrupt pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 2: This buffer is a Schmitt Trigger input when configured as the external interrupt. 3: This buffer is a Schmitt Trigger input when used in serial programming mode. DS30234E-page 14  1997-2013 Microchip Technology Inc. PIC16C6X TABLE 3-2: PIC16C62/62A/R62/63/R63/66 PINOUT DESCRIPTION Pin Name Pin# Pin Type Buffer Type Description OSC1/CLKIN 9 I ST/CMOS(3) OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 I/P ST Master clear reset input or programming voltage input. This pin is an active low reset to the device. RA0 2 I/O TTL RA1 3 I/O TTL RA2 4 I/O TTL RA3 5 I/O TTL RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. RA5/SS 7 I/O TTL RA5 can also be the slave select for the synchronous serial port. Oscillator crystal input/external clock source input. PORTA is a bi-directional I/O port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 I/O TTL/ST(4) RB1 22 I/O TTL RB2 23 I/O TTL RB3 24 I/O TTL RB4 25 I/O TTL Interrupt on change pin. RB5 26 I/O TTL Interrupt on change pin. RB6 27 I/O TTL/ST(5) RB7 28 I/O TTL/ST(5) RB0 can also be the external interrupt pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO(1)/T1CKI 11 I/O ST RC0 can also be the Timer1 oscillator output(1) or Timer1 clock input. RC1/T1OSI(1)/CCP2(2) 12 I/O ST RC1 can also be the Timer1 oscillator input(1) or Capture2 input/Compare2 output/PWM2 output(2). RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK(2) 17 I/O ST RC6 can also be the USART Asynchronous Transmit(2) or Synchronous Clock(2). RC7/RX/DT(2) 18 I/O ST RC7 can also be the USART Asynchronous Receive(2) or Synchronous Data(2). VSS 8,19 P — Ground reference for logic and I/O pins. VDD 20 P — Positive supply for logic and I/O pins. Legend: I = input Note 1: 2: 3: 4: 5: O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Pin functions T1OSO and T1OSI are reversed on the PIC16C62. The USART and CCP2 are not available on the PIC16C62/62A/R62. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode.  1997-2013 Microchip Technology Inc. DS30234E-page 15 PIC16C6X TABLE 3-3: PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION Pin Name DIP Pin# PLCC Pin# TQFP MQFP Pin# Pin Type Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear reset input or programming voltage input. This pin is an active low reset to the device. RA0 2 3 19 I/O TTL RA1 3 4 20 I/O TTL RA2 4 5 21 I/O TTL RA3 5 6 22 I/O TTL RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. RA5/SS 7 8 24 I/O TTL RA5 can also be the slave select for the synchronous serial port. PORTA is a bi-directional I/O port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(4) RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt on change pin. RB5 38 42 15 I/O TTL Interrupt on change pin. RB6 39 43 16 I/O TTL/ST(5) RB7 40 44 17 I/O TTL/ST(5) RB0 can also be the external interrupt pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO(1)/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output(1) or Timer1 clock input. RC1/T1OSI(1)/CCP2(2) 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input(1) or Capture2 input/Compare2 output/PWM2 output(2). RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK(2) 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit(2) or Synchronous Clock(2). RC7/RX/DT(2) 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive(2) or Synchronous Data(2). Legend: I = input Note 1: 2: 3: 4: 5: 6: O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Pin functions T1OSO and T1OSI are reversed on the PIC16C64. CCP2 and the USART are not available on the PIC16C64/64A/R64. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). DS30234E-page 16  1997-2013 Microchip Technology Inc. PIC16C6X TABLE 3-3: Pin Name PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION (Cont.’d) DIP Pin# PLCC Pin# TQFP MQFP Pin# Pin Type Buffer Type Description PORTD can be a bi-directional I/O port or parallel slave port for interfacing to a microprocessor bus. RD0/PSP0 19 21 38 I/O ST/TTL(6) RD1/PSP1 20 22 39 I/O ST/TTL(6) RD2/PSP2 21 23 40 I/O ST/TTL(6) RD3/PSP3 22 24 41 I/O ST/TTL(6) RD4/PSP4 27 30 2 I/O ST/TTL(6) RD5/PSP5 28 31 3 I/O ST/TTL(6) RD6/PSP6 29 32 4 I/O ST/TTL(6) RD7/PSP7 30 33 5 I/O ST/TTL(6) RE0/RD 8 9 25 I/O ST/TTL(6) RE0 can also be read control for the parallel slave port. RE1/WR 9 10 26 I/O ST/TTL(6) RE1 can also be write control for the parallel slave port. RE2/CS 10 11 27 I/O ST/TTL(6) VSS 12,31 13,34 6,29 P — VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17, 28,40 12,13, 33,34 — — These pins are not internally connected. These pins should be left unconnected. PORTE is a bi-directional I/O port. RE2 can also be select control for the parallel slave port. Ground reference for logic and I/O pins. Legend: I = input Note 1: 2: 3: 4: 5: 6: O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Pin functions T1OSO and T1OSI are reversed on the PIC16C64. CCP2 and the USART are not available on the PIC16C64/64A/R64. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in serial programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus).  1997-2013 Microchip Technology Inc. DS30234E-page 17 PIC16C6X 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clock and instruction execution flow is shown in Figure 3-5. Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-5: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC (Program counter) OSC2/CLKOUT (RC mode) PC PC+1 Fetch INST (PC) Execute INST (PC-1) EXAMPLE 3-1: 1. MOVLW 55h PC+2 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW Tcy0 Tcy1 Fetch 1 Execute 1 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Fetch 2 Tcy2 Tcy3 Tcy4 Tcy5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30234E-page 18  1997-2013 Microchip Technology Inc. PIC16C6X 4.0 MEMORY ORGANIZATION FIGURE 4-2: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Program Memory Organization The PIC16C6X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The amount of program memory available to each device is listed below: Device PIC16C61 PIC16C62 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63 PIC16C64 PIC16C64A PIC16CR64 PIC16C65 PIC16C65A PIC16CR65 PIC16C66 PIC16C67 Program Memory Address Range 1K x 14 2K x 14 2K x 14 2K x 14 4K x 14 4K x 14 2K x 14 2K x 14 2K x 14 4K x 14 4K x 14 4K x 14 8K x 14 8K x 14 0000h-03FFh 0000h-07FFh 0000h-07FFh 0000h-07FFh 0000h-0FFFh 0000h-0FFFh 0000h-07FFh 0000h-07FFh 0000h-07FFh 0000h-0FFFh 0000h-0FFFh 0000h-0FFFh 0000h-1FFFh 0000h-1FFFh For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 4-1: PC 13 CALL, RETURN RETFIE, RETLW Stack Level 1    Stack Level 8 User Memory Space 4.1 PIC16C62/62A/R62/64/64A/ R64 PROGRAM MEMORY MAP AND STACK Reset Vector 0000h Peripheral Interrupt Vector 0004h 0005h On-chip Program Memory 07FFh 0800h 1FFFh FIGURE 4-3: PIC16C63/R63/65/65A/R65 PROGRAM MEMORY MAP AND STACK PC 13 CALL, RETURN RETFIE, RETLW Stack Level 1    Stack Level 8 PIC16C61 PROGRAM MEMORY MAP AND STACK Reset Vector 0000h Peripheral Interrupt Vector 0004h 0005h PC User Memory Space User Memory Space 13 CALL, RETURN RETFIE, RETLW Stack Level 1    Stack Level 8 Reset Vector 0000h Peripheral Interrupt Vector 0004h 0005h On-chip Program Memory On-chip Program Memory (Page 0) 07FFh 0800h On-chip Program Memory (Page 1) 0FFFh 1000h 03FFh 0400h 1FFFh 1FFFh  1997-2013 Microchip Technology Inc. DS30234E-page 19 PIC16C6X FIGURE 4-4: PIC16C66/67 PROGRAM MEMORY MAP AND STACK User Memory Space PC 13 CALL, RETURN RETFIE, RETLW Stack Level 1    Stack Level 8 For the PIC16C61, general purpose register locations 8Ch-AFh of Bank 1 are not physically implemented. These locations are mapped into 0Ch-2Fh of Bank 0. FIGURE 4-5: PIC16C61 REGISTER FILE MAP File Address Reset Vector 0000h Peripheral Interrupt Vector 0004h 0005h On-chip Program Memory (Page 0) 07FFh 0800h On-chip Program Memory (Page 1) 0FFFh 1000h On-chip Program Memory (Page 2) INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 07h 87h 08h 88h 89h 09h 0Ah 0Bh 17FFh 1800h File Address 00h PCLATH PCLATH 8Ah INTCON INTCON 8Bh 8Ch 0Ch On-chip Program Memory (Page 3) General Purpose Register Mapped in Bank 0(2) 1FFFh 4.2 Data Memory Organization 2Fh AFh 30h B0h Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1:RP0 (STATUS) = 00  Bank0 = 01  Bank1 = 10  Bank2 = 11  Bank3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 4.2.1 7Fh FFh Bank 0 Bank 1 Unimplemented data memory location; read as '0'. Note 1: Not a physical register. 2: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register. GENERAL PURPOSE REGISTERS These registers are accessed either directly or indirectly through the File Select Register (FSR) (Section 4.5). DS30234E-page 20  1997-2013 Microchip Technology Inc. PIC16C6X FIGURE 4-6: PIC16C62/62A/R62/64/64A/ R64 REGISTER FILE MAP File Address File Address FIGURE 4-7: PIC16C63/R63/65/65A/R65 REGISTER FILE MAP File Address File Address 00h INDF(1) INDF(1) 80h 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 07h PORTC TRISC 87h 07h PORTC TRISC 87h 08h PORTD(2) TRISD(2) 88h 08h PORTD(2) TRISD(2) 88h PORTE(2) TRISE(2) 89h 09h PORTE(2) TRISE(2) 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Ch PIR1 PIE1 8Ch 8Dh 0Dh PIR2 PIE2 8Dh 8Eh 0Eh TMR1L PCON 8Eh TMR1H 8Fh 0Fh TMR1H 8Fh 10h T1CON 90h 10h T1CON 90h 11h TMR2 91h 11h TMR2 91h 09h 0Dh 0Eh 0Fh TMR1L PCON 12h T2CON PR2 92h 12h T2CON PR2 92h 13h SSPBUF SSPADD 93h 13h SSPBUF SSPADD 93h 14h SSPCON SSPSTAT 94h 14h SSPCON SSPSTAT 94h 15h CCPR1L 95h 15h CCPR1L 95h 16h CCPR1H 96h 16h CCPR1H 96h 17h CCP1CON 97h 17h CCP1CON 97h 98h 18h RCSTA TXSTA 98h 19h TXREG SPBRG 99h 1Ah RCREG 1Bh CCPR2L 9Bh 18h 9Ah 1Fh 9Fh 1Ch CCPR2H 9Ch 20h A0h 1Dh CCP2CON 9Dh General Purpose Register General Purpose Register 7Fh BFh C0h FFh Bank 1 Bank 0 Unimplemented data memory location; read as '0'. Note 1: Not a physical register. 2: PORTD and PORTE are not available on the PIC16C62/62A/R62.  1997-2013 Microchip Technology Inc. 1Eh 9Eh 1Fh 9Fh 20h 7Fh General Purpose Register General Purpose Register A0h FFh Bank 1 Bank 0 Unimplemented data memory location; read as '0'. Note 1: Not a physical register 2: PORTD and PORTE are not available on the PIC16C63/R63. DS30234E-page 21 PIC16C6X FIGURE 4-8: PIC16C66/67 DATA MEMORY MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) PORTE (1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register 7Fh * OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD (1) TRISE (1) PCLATH INTCON PIE1 PIE2 PCON PR2 SSPADD SSPSTAT TXSTA SPBRG 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Indirect addr.(*) TMR0 PCL STATUS FSR PORTB PCLATH INTCON General Purpose Register 16 Bytes A0h General Purpose Register 80 Bytes 96 Bytes Bank 0 Indirect addr.(*) accesses 70h-7Fh in Bank 0 Bank 1 EFh F0h FFh General Purpose Register 80 Bytes accesses 70h-7Fh in Bank 0 Bank 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h 16Fh 170h 17Fh Indirect addr.(*) OPTION PCL STATUS FSR TRISB PCLATH INTCON General Purpose Register 16 Bytes 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register 80 Bytes accesses 70h-7Fh in Bank 0 Bank 3 1EFh 1F0h 1FFh Unimplemented data memory locations, read as '0'. Not a physical register. These registers are not implemented on the PIC16C66. Note: DS30234E-page 22 The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require relocation of data memory usage in the user application code if upgrading to the PIC16C66/67.  1997-2013 Microchip Technology Inc. PIC16C6X 4.2.2 SPECIAL FUNCTION REGISTERS: The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. TABLE 4-1: Address Name The special function registers can be classified into two sets (core and peripheral). The registers associated with the “core” functions are described in this section and those related to the operation of the peripheral features are described in the section of that peripheral feature. SPECIAL FUNCTION REGISTERS FOR THE PIC16C61 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 03h(1) STATUS 04h(1) FSR IRP(4) RP1(4) RP0 TO 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer 05h PORTA 06h PORTB — — — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read ---x xxxx ---u uuuu xxxx xxxx uuuu uuuu 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — 0Bh(1) INTCON GIE — T0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF ---0 0000 ---0 0000 RBIF 0-00 000x 0-00 000u Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR 85h TRISA 86h TRISB 87h – Unimplemented — — 88h – Unimplemented — — 89h – Unimplemented — — RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 TO PD Z DC C Indirect data memory address pointer — — — PCLATH — — — 8Bh(1) INTCON GIE — T0IE 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register ---1 1111 ---1 1111 PORTB Data Direction Control Register 8Ah(1,2) 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF ---0 0000 ---0 0000 0-00 000x 0-00 000u Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'. Shaded locations are unimplemented and read as ‘0’ Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 23 PIC16C6X TABLE 4-2: SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu IRP (5) RP1(5) RP0 TO PD Z DC C Indirect data memory address pointer — — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (6) (6) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 Write Buffer for the upper 5 bits of the Program Counter 0Dh — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM1 (LSB) 16h CCPR1H Capture/Compare/PWM1 (MSB) 17h CCP1CON 18h-1Fh — Unimplemented — — — xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 SSPOV — Unimplemented — --00 0000 --uu uuuu 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL — xxxx xxxx uuuu uuuu Timer2 module’s register — ---0 0000 ---0 0000 SSPEN CCP1X CKP SSPM3 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C62, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear. 6: PIE1 and PIR1 are reserved on the PIC16C62/62A/R62, always maintain these bits clear. DS30234E-page 24  1997-2013 Microchip Technology Inc. PIC16C6X TABLE 4-2: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 (Cont.’d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h — Unimplemented — — 89h — Unimplemented — — (1,2) Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP(5) RP1(5) RP0 — 1111 1111 1111 1111 0000 0000 0000 0000 TO PD Z DC C Indirect data memory address pointer — 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 Write Buffer for the upper 5 bits of the Program Counter PCLATH — — — 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 (6) (6) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 — — — — — POR BOR(4) ---- --qq ---- --uu 8Ah 8Dh — 8Eh PCON 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h Unimplemented ---0 0000 ---0 0000 — — PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT 95h-9Fh — — — Unimplemented — 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF --00 0000 --00 0000 — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C62, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear. 6: PIE1 and PIR1 are reserved on the PIC16C62/62A/R62, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 25 PIC16C6X TABLE 4-3: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu IRP (4) RP1(4) RP0 TO PD Z DC C Indirect data memory address pointer — — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (5) (5) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — —– — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON — — — Write Buffer for the upper 5 bits of the Program Counter xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 Timer2 module’s register — SSPBUF 14h SSPCON Synchronous Serial Port Receive Buffer/Transmit Register 15h CCPR1L Capture/Compare/PWM1 (LSB) 16h CCPR1H Capture/Compare/PWM1 (MSB) 17h CCP1CON SSPOV --00 0000 --uu uuuu 0000 0000 0000 0000 13h WCOL ---0 0000 ---0 0000 SSPEN CKP SSPM3 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 SPEN RX9 SREN CREN — FERR OERR RX9D --00 0000 --00 0000 18h RCSTA 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM2 (MSB) 1Dh CCP2CON 1Eh-1Fh — — — Unimplemented CCP2X 0000 -00x 0000 -00x xxxx xxxx uuuu uuuu CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear. 5: PIE1 and PIR1 are reserved on the PIC16C63/R63, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 26 PIC16C6X TABLE 4-3: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 (Cont.’d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h — Unimplemented — — 89h — Unimplemented — — (1,2) Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP(4) RP1(4) RP0 — TO PD Z DC C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 Write Buffer for the upper 5 bits of the Program Counter PCLATH — — 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 (5) (5) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 8Ah 92h — 1111 1111 1111 1111 0000 0000 0000 0000 Indirect data memory address pointer — 0000 0000 0000 0000 PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT — — ---0 0000 ---0 0000 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h(2) TXSTA 99h(2) SPBRG CSRC TX9 TXEN Baud Rate Generator Register SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear. 5: PIE1 and PIR1 are reserved on the PIC16C63/R63, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 27 PIC16C6X TABLE 4-4: SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h PORTD PORTD Data Latch when written: PORTD pins when read 09h PORTE — — — 0Ah(1,2) PCLATH — — — 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF (6) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 IRP (5) RP1(5) RP0 TO PD Z — — C — — RE1 RE0 Write Buffer for the upper 5 bits of the Program Counter 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM1 (LSB) 16h CCPR1H Capture/Compare/PWM1 (MSB) 17h CCP1CON — --xx xxxx --uu uuuu xxxx xxxx uuuu uuuu RE2 — Unimplemented — — — — xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 SSPOV — Unimplemented — --00 0000 --uu uuuu 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL ---- -xxx ---- -uuu ---0 0000 ---0 0000 xxxx xxxx uuuu uuuu Timer2 module’s register — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read 0Dh 18h-1Fh DC Indirect data memory address pointer SSPEN CCP1X CKP SSPM3 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C64, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear. 6: PIE1 and PIR1 are reserved on the PIC16C64/64A/R64, always maintain these bits clear. DS30234E-page 28  1997-2013 Microchip Technology Inc. PIC16C6X TABLE 4-4: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 (Cont.’d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h TRISD PORTD Data Direction Register 89h TRISE IBF OBF IBOV 8Ah(1,2) PCLATH — — — 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE (6) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 — — — — — POR Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP(5) RP1(5) RP0 — 1111 1111 1111 1111 0000 0000 0000 0000 TO PD Z DC C 0001 1xxx 000q quuu Indirect data memory address pointer — 0000 0000 0000 0000 xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 1111 1111 1111 1111 PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Dh — 8Eh PCON 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h Unimplemented — — PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT 95h-9Fh — — — Unimplemented BOR (4) — ---- --qq ---- --uu 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF --00 0000 --00 0000 — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C64, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear. 6: PIE1 and PIR1 are reserved on the PIC16C64/64A/R64, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 29 PIC16C6X TABLE 4-5: SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h PORTD PORTD Data Latch when written: PORTD pins when read 09h PORTE — — — 0Ah(1,2) PCLATH — — — 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF (6) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — —– — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM1 (LSB) 16h CCPR1H Capture/Compare/PWM1 (MSB) 17h CCP1CON 18h RCSTA 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 xxxx xxxx uuuu uuuu IRP(5) RP1(5) RP0 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer — — — — — xxxx xxxx uuuu uuuu RE2 RE1 RE0 Write Buffer for the upper 5 bits of the Program Counter xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 SSPOV SSPEN CKP SSPM3 xxxx xxxx uuuu uuuu SSPM0 xxxx xxxx uuuu uuuu — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 SPEN RX9 SREN CREN — FERR OERR RX9D CCPR2L Capture/Compare/PWM2 (LSB) CCPR2H Capture/Compare/PWM2 (MSB) 1Dh CCP2CON Unimplemented — CCP2X 0000 0000 0000 0000 xxxx xxxx uuuu uuuu — — --00 0000 --uu uuuu 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL ---- -xxx ---- -uuu ---0 0000 ---0 0000 T1CKPS1 1Ch — — --xx xxxx --uu uuuu Timer2 module’s register — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read 1Bh 1Eh-1Fh TO --00 0000 --00 0000 0000 -00x 0000 -00x xxxx xxxx uuuu uuuu CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C65, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear. 6: PIE1 and PIR1 are reserved on the PIC16C65/65A/R65, always maintain these bits clear. DS30234E-page 30  1997-2013 Microchip Technology Inc. PIC16C6X TABLE 4-5: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 (Cont.’d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h TRISD PORTD Data Direction Register 89h TRISE IBF OBF IBOV 8Ah(1,2) PCLATH — — — 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE (6) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR(4) ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP(5) RP1(5) RP0 — TO PD Z DC C --11 1111 --11 1111 1111 1111 1111 1111 PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Write Buffer for the upper 5 bits of the Program Counter Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register PR2 — 1111 1111 1111 1111 0000 0000 0000 0000 Indirect data memory address pointer — 0000 0000 0000 0000 ---0 0000 ---0 0000 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA 99h SPBRG CSRC TX9 TXEN Baud Rate Generator Register SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C65, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear. 6: PIE1 and PIR1 are reserved on the PIC16C65/65A/R65, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 31 PIC16C6X TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 02h (1) 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h(5) PORTE — — — 0Ah(1,2) PCLATH — — — 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(6) (4) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — —– — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM1 (LSB) 16h CCPR1H Capture/Compare/PWM1 (MSB) 17h CCP1CON 18h RCSTA 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM2 (MSB) 1Dh CCP2CON 1Eh-1Fh IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer — — — — xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read — — — --xx xxxx --uu uuuu xxxx xxxx uuuu uuuu RE2 RE1 RE0 Write Buffer for the upper 5 bits of the Program Counter xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 SSPOV SSPEN CKP SSPM3 xxxx xxxx uuuu uuuu SSPM0 xxxx xxxx uuuu uuuu — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 SPEN RX9 SREN CREN — FERR OERR RX9D Unimplemented — CCP2X 0000 0000 0000 0000 xxxx xxxx uuuu uuuu — — --00 0000 --uu uuuu 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL ---- -xxx ---- -uuu ---0 0000 ---0 0000 xxxx xxxx uuuu uuuu Timer2 module’s register — 0001 1xxx 000q quuu --00 0000 --00 0000 0000 -00x 0000 -00x xxxx xxxx uuuu uuuu CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: PIE1 and PIR1 are reserved on the PIC16C66/67, always maintain these bits clear. 5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'. 6: PSPIF (PIR1) and PSPIE (PIE1) are reserved on the PIC16C66, maintain these bits clear. DS30234E-page 32  1997-2013 Microchip Technology Inc. PIC16C6X TABLE 4-6: Address Name SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS 84h(1) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 89h(5) TRISE IBF OBF IBOV 8Ah(1,2) PCLATH — — — 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0000 0000 0000 0000 Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 — (6) 1111 1111 1111 1111 0000 0000 0000 0000 TO PD Z DC C Indirect data memory address pointer — 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 1111 1111 1111 1111 PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Ch PIE1 (4) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — PSPIE 92h PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT SMP CKE 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF 0000 0000 0000 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA 99h SPBRG CSRC TX9 TXEN Baud Rate Generator Register SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: PIE1 and PIR1 are reserved on the PIC16C66/67, always maintain these bits clear. 5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'. 6: PSPIF (PIR1) and PSPIE (PIE1) are reserved on the PIC16C66, maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 33 PIC16C6X TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets(3) Bank 2 100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 (1) 103h STATUS 104h(1) FSR 105h — 106h IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer PORTB 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu Unimplemented — PORTB Data Latch when written: PORTB pins when read — xxxx xxxx uuuu uuuu 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — (1,2) 10Ah PCLATH — — — 10Bh(1) INTCON GIE PEIE T0IE 10Ch10Fh — Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF Unimplemented ---0 0000 ---0 0000 0000 000x 0000 000u — — Bank 3 180h(1) INDF 181h OPTION 182h(1) PCL 183h(1) STATUS 184h(1) FSR Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu 185h — 186h TRISB 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,2) PCLATH 18Bh(1) 18Ch19Fh INTCON — Unimplemented — PORTB Data Direction Register — — — GIE PEIE T0IE Unimplemented — 1111 1111 1111 1111 Write Buffer for the upper 5 bits of the Program Counter INTE RBIE T0IF INTF RBIF ---0 0000 ---0 0000 0000 000x 0000 000u — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: PIE1 and PIR1 are reserved on the PIC16C66/67, always maintain these bits clear. 5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'. 6: PSPIF (PIR1) and PSPIE (PIE1) are reserved on the PIC16C66, maintain these bits clear. DS30234E-page 34  1997-2013 Microchip Technology Inc. PIC16C6X 4.2.2.1 STATUS REGISTER Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The STATUS register, shown in Figure 4-9, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the “Instruction Set Summary.” Note 1: For those devices that do not use bits IRP and RP1 (STATUS), maintain these bits clear to ensure upward compatibility with future products. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 4-9: R/W-0 IRP STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC bit7 R/W-x C bit0 R = Readable bit W = Writable bit - n = Value at POR reset x = unknown bit 7: IRP: RegIster Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF, ADDLW,SUBLW, and SUBWF instructions) (For borrow the polarity is reversed). 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (for ADDWF, ADDLW,SUBLW, and SUBWF instructions)( For borrow the polarity is reversed). 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result Note: a subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  1997-2013 Microchip Technology Inc. DS30234E-page 35 PIC16C6X 4.2.2.2 OPTION REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for TMR0 register, assign the prescaler to the Watchdog Timer. FIGURE 4-10: OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit7 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 DS30234E-page 36 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128  1997-2013 Microchip Technology Inc. PIC16C6X 4.2.2.3 INTCON REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The INTCON Register is a readable and writable register which contains the various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). FIGURE 4-11: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset x = unknown bit 7: GIE:(1) Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE:(2) Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear the interrupt) 0 = None of the RB7:RB4 pins have changed state Note 1: For the PIC16C61/62/64/65, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may unintentionally be re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 13.5 for a detailed description. 2: The PEIE bit (bit6) is unimplemented on the PIC16C61, read as '0'. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  1997-2013 Microchip Technology Inc. DS30234E-page 37 PIC16C6X 4.2.2.4 PIE1 REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Bit PEIE (INTCON) must be set to enable any peripheral interrupt. This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch) RW-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30234E-page 38 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset  1997-2013 Microchip Technology Inc. PIC16C6X FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear. bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset FIGURE 4-14: PIE1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 8Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE — — — SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: Reserved: Always maintain this bit clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  1997-2013 Microchip Technology Inc. R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset DS30234E-page 39 PIC16C6X FIGURE 4-15: PIE1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: Reserved: Always maintain this bit clear. bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30234E-page 40 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset  1997-2013 Microchip Technology Inc. PIC16C6X 4.2.2.5 PIR1 REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 This register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. FIGURE 4-16: PIR1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register overflow occurred R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  1997-2013 Microchip Technology Inc. DS30234E-page 41 PIC16C6X FIGURE 4-17: PIR1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear. bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register overflow occurred R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234E-page 42  1997-2013 Microchip Technology Inc. PIC16C6X FIGURE 4-18: PIR1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF — — — SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place bit 6: Reserved: Always maintain this bit clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register occurred R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  1997-2013 Microchip Technology Inc. DS30234E-page 43 PIC16C6X FIGURE 4-19: PIR1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place bit 6: Reserved: Always maintain this bit clear. bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register overflow occurred R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234E-page 44  1997-2013 Microchip Technology Inc. PIC16C6X 4.2.2.6 PIE2 REGISTER Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 This register contains the CCP2 interrupt enable bit. FIGURE 4-20: PIE2 REGISTER (ADDRESS 8Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE bit7 bit0 bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt  1997-2013 Microchip Technology Inc. R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset DS30234E-page 45 PIC16C6X 4.2.2.7 PIR2 REGISTER . Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 This register contains the CCP2 interrupt flag bit. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. FIGURE 4-21: PIR2 REGISTER (ADDRESS 0Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IF bit7 bit0 bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234E-page 46  1997-2013 Microchip Technology Inc. PIC16C6X 4.2.2.8 PCON REGISTER Note: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The Power Control register (PCON) contains a flag bit to allow differentiation between a Power-on Reset to an external MCLR reset or WDT reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Poweron Reset condition. FIGURE 4-22: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a “don't care” and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word). PCON REGISTER FOR PIC16C62/64/65 (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR — bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset q = value depends on conditions bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: Reserved This bit should be set upon a Power-on Reset by user software and maintained as set. Use of this bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. FIGURE 4-23: PCON REGISTER FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset q = value depends on conditions bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)  1997-2013 Microchip Technology Inc. DS30234E-page 47 PIC16C6X 4.3 PCL and PCLATH Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-24 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH  PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH  PCH). FIGURE 4-24: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC 8 PCLATH 5 Instruction with PCL as destination ALU PCLATH PCH 12 11 10 PCL 8 7 0 PC PCLATH 11 Opcode PCLATH 4.3.1 Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address 4.4 Program Memory Paging Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PIC16C6X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper two bits of the address are provided by PCLATH. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH bits are not required for the return instructions (which POPs the address from the stack). Note: GOTO, CALL 2 Note 1: There are no status bits to indicate stack overflows or stack underflow conditions. PIC16C6X devices with 4K or less of program memory ignore paging bit PCLATH. The use of PCLATH as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products. COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 word block). Refer to the application note “Implementing a Table Read” (AN556). 4.3.2 STACK The PIC16CXX family has an 8 deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or a POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30234E-page 48  1997-2013 Microchip Technology Inc. PIC16C6X Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that the PCLATH is saved and restored by the interrupt service routine (if interrupts are used). 4.5 EXAMPLE 4-1: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ORG 0x500 BSF PCLATH,3 BCF PCLATH,4 CALL SUB1_P1 : : : ORG 0x900 SUB1_P1: : : RETURN Indirect Addressing, INDF and FSR Registers Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS), as shown in Figure 4-25. ;Select page 1 (800h-FFFh) ;Only on >4K devices ;Call subroutine in ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-2. ;return to Call subroutine ;in page 0 (000h-7FFh) EXAMPLE 4-2: movlw movwf clrf incf btfss goto NEXT INDIRECT ADDRESSING 0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next CONTINUE : ;YES, continue FIGURE 4-25: DIRECT/INDIRECT ADDRESSING Direct Addressing RP1: RP0 bank select 6 Indirect Addressing 0 from opcode IRP 7 bank select location select 00 01 10 FSR 0 location select 11 00h 80h 100h 180h 7Fh FFh 17Fh 1FFh Data Memory Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8.  1997-2013 Microchip Technology Inc. DS30234E-page 49 PIC16C6X NOTES: DS30234E-page 50  1997-2013 Microchip Technology Inc. PIC16C6X 5.0 I/O PORTS FIGURE 5-1: BLOCK DIAGRAM OF THE RA3:RA0 PINS AND THE RA5 PIN Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Some pins for these I/O ports are multiplexed with an alternate function(s) for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 PORTA and TRISA Register Data bus D VDD WR Port Pin RA4/T0CKI is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can configure these pins as output or input. Q CK Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 All devices have a 6-bit wide PORTA, except for the PIC16C61 which has a 5-bit wide PORTA. Q Q N Q VSS TRIS Latch TTL input buffer D WR TRIS CK Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin. Reading PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with Timer0 module clock input to become the RA4/T0CKI pin. EXAMPLE 5-1: BCF BCF CLRF BSF MOVLW MOVWF INITIALIZING PORTA STATUS, RP0 STATUS, RP1 PORTA STATUS, RP0 0xCF TRISA ; ; ; ; ; ; ; ; ; ; ; ; ; PIC16C66/67 only Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA as inputs RA as outputs TRISA are always read as '0'. P Data Latch I/O pin(1) RD TRIS Q D EN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. 2: The PIC16C61 does not have an RA5 pin. FIGURE 5-2: Data bus WR PORT BLOCK DIAGRAM OF THE RA4/T0CKI PIN D Q CK Q N I/O pin(1) Data Latch WR TRIS D Q CK Q VSS Schmitt Trigger input buffer TRIS Latch RD TRIS Q D ENEN RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.  1997-2013 Microchip Technology Inc. DS30234E-page 51 PIC16C6X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Type RA0 RA1 RA2 RA3 RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST RA5/SS (1) bit5 TTL Function Input/output Input/output Input/output Input/output Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: The PIC16C61 does not have PORTA or TRISA, read as ‘0’. TABLE 5-2: REGISTERS/BITS ASSOCIATED WITH PORTA Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 05h PORTA — — RA5(1) RA4 RA3 RA2 RA1 RA0 85h TRISA — — PORTA Data Direction Register(1) Value on: POR, BOR Value on all other resets --xx xxxx --uu uuuu --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: PORTA and TRISA are not implemented on the PIC16C61, read as '0'. DS30234E-page 52  1997-2013 Microchip Technology Inc. PIC16C6X 5.2 PORTB and TRISB Register Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). EXAMPLE 5-2: INITIALIZING PORTB BCF CLRF STATUS, RP0 PORTB BSF MOVLW STATUS, RP0 0xCF MOVWF TRISB ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB as inputs RB as outputs RB as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are also disabled on a Power-on Reset. Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB port change interrupt with flag bit RBIF (INTCON). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook, Application Note, “Implementing Wake-up on Key Stroke” (AN552). Note: For PIC16C61/62/64/65, if a change on the I/O pin should occur when a read operation is being executed (start of the Q2 cycle), then interrupt flag bit RBIF may not get set. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. FIGURE 5-3: BLOCK DIAGRAM OF THE RB7:RB4 PINS FOR PIC16C61/62/64/65 VDD RBPU(2) Data bus weak P pull-up Data Latch D Q WR Port I/O pin(1) CK TRIS Latch D Q WR TRIS TTL Input Buffer CK RD TRIS Q ST Buffer Latch D EN RD Port Set RBIF From other RB7:RB4 pins Q D EN RD Port RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RPBU bit (OPTION).  1997-2013 Microchip Technology Inc. DS30234E-page 53 PIC16C6X FIGURE 5-4: BLOCK DIAGRAM OF THE RB7:RB4 PINS FOR PIC16C62A/63/R63/64A/65A/ R65/66/67 FIGURE 5-5: VDD RBPU(2) weak P pull-up VDD RBPU(2) Data Latch D WR Port D WR Port WR TRIS TRIS Latch D Q TTL Input Buffer I/O pin(1) TRIS Latch D Q I/O pin(1) CK Q CK Q CK WR TRIS Data Latch Data bus weak P pull-up Data bus BLOCK DIAGRAM OF THE RB3:RB0 PINS TTL Input Buffer CK ST Buffer RD TRIS Q RD TRIS Latch Q D EN RD Port EN RD Port Q1 D RB0/INT Set RBIF Schmitt Trigger Buffer Q From other RB7:RB4 pins RD Port D RD Port EN Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RPBU bit (OPTION). Q3 RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RPBU bit (OPTION). TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Type RB0/INT bit0 TTL/ST(1) RB1 RB2 RB3 RB4 bit1 bit2 bit3 bit4 TTL TTL TTL TTL RB5 bit5 TTL RB6 bit6 TTL/ST(2) RB7 bit7 TTL/ST(2) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. TABLE 5-4: Address SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name 06h, 106h PORTB 86h, 186h TRISB 81h, 181h OPTION Value on: POR, BOR Value on all other resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuuu 1111 1111 1111 1111 T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30234E-page 54  1997-2013 Microchip Technology Inc. PIC16C6X 5.3 PORTC and TRISC Register FIGURE 5-6: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PORTC is an 8-bit wide bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. EXAMPLE 5-3: INITIALIZING PORTC BCF BCF CLRF STATUS, RP0 STATUS, RP1 PORTC BSF MOVLW STATUS, RP0 0xCF MOVWF TRISC TABLE 5-5: ; ; ; ; ; ; ; ; ; ; ; ; PIC16C66/67 only Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC as inputs RC as outputs RC as inputs PORTC BLOCK DIAGRAM PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT D VDD 0 Q P 1 CK Q Data Latch WR TRIS D CK I/O pin(1) Q Q N TRIS Latch VSS Schmitt Trigger RD TRIS Peripheral OE(3) RD PORT Peripheral input Q D EN Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. PORTC FUNCTIONS FOR PIC16C62/64 Name Bit# Buffer Type Function RC0/T1OSI/T1CKI bit0 ST RC1/T1OSO bit1 ST Input/output port pin or Timer1 oscillator input or Timer1 clock input Input/output port pin or Timer1 oscillator output RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC3/SCK/SCL bit3 ST RC4/SDI/SDA RC5/SDO bit4 ST bit5 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or synchronous serial port data output RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend: ST = Schmitt Trigger input  1997-2013 Microchip Technology Inc. DS30234E-page 55 PIC16C6X TABLE 5-6: PORTC FUNCTIONS FOR PIC16C62A/R62/64A/R64 Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture input/Compare output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I2C modes. Input/output port pin or Timer1 oscillator output or Timer1 clock input RC3/SCK/SCL bit3 ST RC4/SDI/SDA RC5/SDO bit4 ST bit5 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or synchronous serial port data output RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend: ST = Schmitt Trigger input TABLE 5-7: PORTC FUNCTIONS FOR PIC16C63/R63/65/65A/R65/66/67 Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output RC2/CCP1 bit2 ST RC3/SCK/SCL bit3 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA RC5/SDO bit4 ST bit5 ST RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART Synchronous Clock RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive, or USART Synchronous Data RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). Input/output port pin or synchronous serial port data output Legend: ST = Schmitt Trigger input TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name 07h PORTC 87h TRISC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PORTC Data Direction Register Legend: x = unknown, u = unchanged. DS30234E-page 56  1997-2013 Microchip Technology Inc. PIC16C6X 5.4 PORTD and TRISD Register FIGURE 5-7: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Data bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as input or output. D WR PORT PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE). In this mode, the input buffers are TTL. PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Q I/O pin(1) CK Data Latch D WR TRIS Q Schmitt Trigger input buffer CK TRIS Latch RD TRIS Q D EN EN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 5-9: PORTD FUNCTIONS Name Bit# Buffer Type RD0/PSP0 bit0 ST/TTL(1) Function Input/output port pin or parallel slave port bit0 RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1 RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2 RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3 RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4 RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5 RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6 RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7 Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port mode. TABLE 5-10: Address Name 08h PORTD 88h TRISD 89h TRISE SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 PORTD Data Direction Register IBF OBF IBOV PSPMODE — PORTE Data Direction Bits Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTD.  1997-2013 Microchip Technology Inc. DS30234E-page 57 PIC16C6X 5.5 PORTE and TRISE Register FIGURE 5-8: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Data bus PORTE has three pins, RE2/CS, RE1/WR, and RE0/RD which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. PORTE BLOCK DIAGRAM (IN I/O PORT MODE) D WR PORT Q I/O pin(1) CK Data Latch I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE) is set. In this mode, the user must make sure that the TRISE bits are set (pins are configured as digital inputs). In this mode the input buffers are TTL. D WR TRIS Q Schmitt Trigger input buffer CK TRIS Latch Figure 5-9 shows the TRISE register, which controls the parallel slave port operation and also controls the direction of the PORTE pins. RD TRIS Q D ENEN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 5-9: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — bit2 bit1 bit0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4: PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' PORTE Data Direction Bits bit 2: Bit2: Direction Control bit for pin RE2/CS 1 = Input 0 = Output bit 1: Bit1: Direction Control bit for pin RE1/WR 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD 1 = Input 0 = Output DS30234E-page 58  1997-2013 Microchip Technology Inc. PIC16C6X TABLE 5-11: PORTE FUNCTIONS Name Bit# Buffer Type RE0/RD bit0 ST/TTL(1) Function Input/output port pin or Read control input in parallel slave port mode. RD 1 = Not a read operation 0 = Read operation. The system reads the PORTD register (if chip selected) RE1/WR bit1 ST/TTL(1) Input/output port pin or Write control input in parallel slave port mode. WR 1 = Not a write operation 0 = Write operation. The system writes to the PORTD register (if chip selected) RE2/CS bit2 ST/TTL(1) Input/output port pin or Chip select control input in parallel slave port mode. CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port (PSP) mode. TABLE 5-12: Address SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 09h PORTE — — — — — 89h TRISE IBF OBF IBOV PSPMODE — Bit 2 Bit 1 Bit 0 RE2 RE1 RE0 PORTE Data Direction Bits Value on: POR, BOR Value on all other resets ---- -xxx ---- -uuu 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells not used by PORTE.  1997-2013 Microchip Technology Inc. DS30234E-page 59 PIC16C6X 5.6 I/O Programming Considerations EXAMPLE 5-4: Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 5.6.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-4 shows the effect of two sequential read-modify-write instructions on an I/O port. READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ;Initial PORT settings: PORTB Inputs ; PORTB Outputs ;PORTB have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp pppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high). A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip. 5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-10). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-10: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched PC PC + 1 MOVWF PORTB MOVF PORTB,W write to PORTB Q1 Q2 Q3 Q4 PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) RB7:RB0 where TCY = instruction cycle TPD = propagation delay Port pin sampled here TPD Instruction executed NOP MOVWF PORTB write to PORTB DS30234E-page 60 Note: MOVF PORTB,W Therefore, at higher clock frequencies, a write followed by a read may be problematic.  1997-2013 Microchip Technology Inc. PIC16C6X 5.7 Parallel Slave Port Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 PORTD operates as an 8-bit wide parallel slave port (microprocessor port) when control bit PSPMODE (TRISE) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input (RE0/RD) and WR control input pin (RE1/WR). It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE) must be configured as inputs (set). There are actually two 8-bit latches, one for data-out (from the PIC16/17) and one for data input. The user writes 8-bit data to PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored since the microprocessor is controlling the direction of data flow. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR lines become high (level triggered), then the Input Buffer Full status flag bit IBF (TRISE) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 5-12). The interrupt flag bit PSPIF (PIR1) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The input Buffer Overflow status flag bit IBOV (TRISE) is set if a second write to the Parallel Slave Port is attempted when the previous byte has not been read out of the buffer. FIGURE 5-11: PORTD AND PORTE AS A PARALLEL SLAVE PORT Data bus D WR PORT Q RDx pin CK TTL Q RD PORT D EN EN One bit of PORTD Set interrupt flag PSPIF (PIR1) Read TTL RD Chip Select TTL CS TTL WR Write Note: I/O pin has protection diodes to VDD and VSS. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full status flag bit OBF (TRISE) is cleared immediately (Figure 5-13) indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in Parallel Slave Port mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1).  1997-2013 Microchip Technology Inc. DS30234E-page 61 PIC16C6X FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD IBF OBF PSPIF TABLE 5-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on: POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu PORTE Data Direction Bits 89h TRISE 0Ch PIR1 8Ch PIE1 IBF OBF IBOV PSPMODE — 0000 -111 0000 -111 PSPIF (1) RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TRM1IF 0000 0000 0000 0000 PSPIE (1) RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP. Note 1: These bits are reserved, always maintain these bits clear. 2: These bits are implemented on the PIC16C65/65A/R65/67 only. DS30234E-page 62  1997-2013 Microchip Technology Inc. PIC16C6X 6.0 OVERVIEW OF TIMER MODULES Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 All PIC16C6X devices have three timer modules except for the PIC16C61, which has one timer module. Each module can generate an interrupt to indicate that an event has occurred (i.e., timer overflow). Each of these modules are detailed in the following sections. The timer modules are: 6.3 Timer2 Overview Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Timer2 is an 8-bit timer with a programmable prescaler and a programmable postscaler, as well as an 8-bit Period Register (PR2). Timer2 can be used with the CCP module (in PWM mode) as well as the Baud Rate Generator for the Synchronous Serial Port (SSP). The prescaler option allows Timer2 to increment at the following rates: 1:1, 1:4, and 1:16. • Timer0 module (Section 7.0) • Timer1 module (Section 8.0) • Timer2 module (Section 9.0) The postscaler allows TMR2 register to match the period register (PR2) a programmable number of times before generating an interrupt. The postscaler can be programmed from 1:1 to 1:16 (inclusive). 6.1 6.4 Timer0 Overview CCP Overview Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The Timer0 module is a simple 8-bit overflow counter. The clock source can be either the internal system clock (Fosc/4) or an external clock. When the clock source is an external clock, the Timer0 module can be selected to increment on either the rising or falling edge. The CCP module(s) can operate in one of three modes: 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). The Timer0 module also has a programmable prescaler option. This prescaler can be assigned to either the Timer0 module or the Watchdog Timer. Bit PSA (OPTION) assigns the prescaler, and bits PS2:PS0 (OPTION) determine the prescaler value. TMR0 can increment at the following rates: 1:1 when the prescaler is assigned to Watchdog Timer, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256. Synchronization of the external clock occurs after the prescaler. When the prescaler is used, the external clock frequency may be higher then the device’s frequency. The maximum frequency is 50 MHz, given the high and low time requirements of the clock. 6.2 Timer1 Overview Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Capture mode captures the 16-bit value of TMR1 into the CCPRxH:CCPRxL register pair. The capture event can be programmed for either the falling edge, rising edge, fourth rising edge, or sixteenth rising edge of the CCPx pin. Compare mode compares the TMR1H:TMR1L register pair to the CCPRxH:CCPRxL register pair. When a match occurs, an interrupt can be generated and the output pin CCPx can be forced to a given state (High or Low) and Timer1 can be reset. This depends on control bits CCPxM3:CCPxM0. PWM mode compares the TMR2 register to a 10-bit duty cycle register (CCPRxH:CCPRxL) as well as to an 8-bit period register (PR2). When the TMR2 register = Duty Cycle register, the CCPx pin will be forced low. When TMR2 = PR2, TMR2 is cleared to 00h, an interrupt can be generated, and the CCPx pin (if an output) will be forced high. Timer1 is a 16-bit timer/counter. The clock source can be either the internal system clock (Fosc/4), an external clock, or an external crystal. Timer1 can operate as either a timer or a counter. When operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. Asynchronous operation allows Timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power savings of SLEEP mode. TImer1 also has a prescaler option which allows TMR1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. TMR1 can be used in conjunction with the Capture/ Compare/PWM module. When used with a CCP module, Timer1 is the time-base for 16-bit capture or 16-bit compare and must be synchronized to the device.  1997-2013 Microchip Technology Inc. DS30234E-page 63 PIC16C6X NOTES: DS30234E-page 64  1997-2013 Microchip Technology Inc. PIC16C6X 7.0 TIMER0 MODULE (OPTION). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler. The Timer0 module has the following features: • 8-bit timer/counter register, TMR0 - Read and write capability - Interrupt on overflow from FFh to 00h • 8-bit software programmable prescaler • Internal or external clock select - Edge select for external clock Figure 7-1 is a simplified block diagram of the Timer0 module. 7.1 The TMR0 interrupt is generated when the register (TMR0) overflows from FFh to 00h. This overflow sets interrupt flag bit T0IF (INTCON). The interrupt can be masked by clearing enable bit T0IE (INTCON). Flag bit T0IF must be cleared in software by the TImer0 interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. Figure 7-4 displays the Timer0 interrupt timing. Counter mode is selected by setting bit T0CS. In this mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge select bit T0SE FIGURE 7-1: TMR0 Interrupt Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Timer mode is selected by clearing bit T0CS (OPTION). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register. TIMER0 BLOCK DIAGRAM Data bus RA4/T0CKI pin FOSC/4 0 PSout 1 1 Programmable Prescaler 8 Sync with Internal clocks 0 TMR0 reg PSout (2 cycle delay) T0SE 3 Set bit T0IF on overflow PSA PS2, PS1, PS0 T0CS Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................20 mA Maximum current sunk byPORTA ..........................................................................................................................80 mA Maximum current sourced by PORTA .....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB...................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 15-1: OSC CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C61-04 PIC16C61-20 PIC16LC61-04 JW Devices RC VDD: IDD: IPD: Freq: 4.0V to 6.0V 3.3 mA max. at 5.5V 14 A max. at 4V 4 MHz max. VDD: IDD: IPD: Freq: 4.5V to 5.5V 1.8 mA typ. at 5.5V 1.0 A typ. at 4V 4 MHz max. VDD: IDD: IPD: Freq: 3.0V to 6.0V 1.4 mA typ. at 3.0V 0.6 A typ. at 3V 4 MHz max. VDD: IDD: IPD: Freq: 4.0V to 6.0V 3.3 mA max. at 5.5V 14 A max. at 4V 4 MHz max. XT VDD: IDD: IPD: Freq: 4.0V to 6.0V 3.3 mA max. at 5.5V 14 A max. at 4V 4 MHz max. VDD: 4.5V to 5.5V IDD: 1.8 mA typ. at 5.5V IPD: 1.0 A typ. at 4V Freq: 4 MHz max. VDD: IDD: IPD: Freq: 3.0V to 6.0V 1.4 mA typ. at 3.0V 0.6 A typ. at 3V 4 MHz max. VDD: IDD: IPD: Freq: 4.0V to 6.0V 3.3 mA max. at 5.5V 14 A max. at 4V 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IPD: 1.0 A typ. at 4.5V IPD: Freq: 4 MHz max. LP VDD: 4.0V to 6.0V IDD: 15 A typ. at 32 kHz, 4.0V IPD: 0.6 A typ. at 4.0V Freq: 200 kHz max. 1.0 A typ. at 4.5V VDD: 4.5V to 5.5V Not recommended for use in HS mode Freq: 20 MHz max. Not recommended for use in LP mode IDD: 30 mA max. at 5.5V IPD: 1.0 A typ. at 4.5V Freq: 20 MHz max. VDD: 3.0V to 6.0V IDD: 32 A max. at 32 kHz, 3.0V IPD: 9 A max. at 3.0V Freq: 200 kHz max. VDD: 3.0V to 6.0V IDD: 32 A max. at 32 kHz, 3.0V IPD: 9 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 159 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.1 DC Characteristics: PIC16C61-04 (Commercial, Industrial, Extended) PIC16C61-20 (Commercial, Industrial, Extended) DC CHARACTERISTICS Param No. D001 D001A D002* D003 D004* D010 Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions Supply Voltage VDD RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2) D013 1.5 6.0 5.5 - V V V XT, RC and LP osc configuration HS osc configuration VDR 4.0 4.5 - VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - - 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V (Note 4) - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C IDD V/ms See section on Power-on Reset for details D020 Power-down Current IPD 7 28 A D021 (Note 3) 1.0 14 A D021A 1.0 16 A D021B 1.0 20 A * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. DS30234E-page 160  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.2 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic D001 D002* Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2) D003 D004* D010 PIC16LC61-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions VDD VDR 3.0 - 1.5 6.0 - V V XT, RC, and LP osc configuration VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - - 1.4 2.5 mA FOSC = 4 MHz, VDD = 3.0V (Note 4) - 15 32 A FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP osc configuration VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C IDD D010A D020 D021 D021A * † Note 1: 2: 3: 4: V/ms See section on Power-on Reset for details 5 20 A 0.6 9 A 0.6 12 A These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Power-down Current (Note 3)  1997-2013 Microchip Technology Inc. IPD DS30234E-page 161 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.3 DC Characteristics: PIC16C61-04 (Commercial, Industrial, Extended) PIC16C61-20 (Commercial, Industrial, Extended) PIC16LC61-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Sym Min Typ† Max Units Conditions VIL Vss VSS Vss Vss Vss VIH 2.0 0.25VDD + 0.8V D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current IPURB Input Leakage Current (Notes 2, 3) I/O ports IIL D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC osc config) D083A VOL - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V  VDD  5.5V - VDD VDD V V 4.5V  VDD  5.5V For entire VDD range VDD VDD VDD VDD † 400 V V V V A For entire VDD range Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration 0.85VDD 0.85VDD 0.7VDD 0.9VDD 50 250 - - 1 A - - 5 5 A A - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V Note1 Note1 VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * † The parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 162  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Sym Min Typ† Max Units Conditions VOH D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* D100 Open-Drain High Voltage Capacitive Loading Specs on Output Pins OSC2 pin VOD COSC2 VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V - - 14 V 15 pF IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. D101 * † All I/O pins and OSC2 (in RC mode) CIO 50 pF The parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 163 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 15-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF DS30234E-page 164 for all pins except OSC2/CLKOUT for OSC2 output  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.5 Timing Diagrams and Specifications FIGURE 15-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 15-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) Typ† Max Units Conditions DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode 0.1 — 4 MHz XT osc mode 1 — 4 MHz HS osc mode (-04) HS osc mode (-20) 1 — 20 MHz 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 1,000 ns HS osc mode (-04) 50 — 1,000 ns HS osc mode (-20) 5 — — s LP osc mode TCY = 4/Fosc 2 TCY Instruction Cycle Time (Note 1) 1.0 TCY DC s 3 TosL, TosH External Clock in (OSC1) High or Low Time 50 — — ns XT oscillator 2.5 — — s LP oscillator TosR, TosF External Clock in (OSC1) Rise or Fall Time 4 10 — — ns HS oscillator 25 — — ns XT oscillator 50 — — ns LP oscillator 15 — — ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 165 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 15-1 for load conditions. TABLE 15-3: Parameter No. CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic Min Typ† Max 10* TosH2ckL 11* TosH2ckH 12* OSC1 to CLKOUT — 15 30 ns Note 1 OSC1 to CLKOUT — 15 30 ns Note 1 TckR CLKOUT rise time — 5 15 ns Note 1 13* TckF CLKOUT fall time — 5 15 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  16* TckH2ioI Port in hold after CLKOUT  17* TosH2ioV OSC1 (Q1 cycle) to Port out valid 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) 19* TioV2osH Port input valid to OSC1(I/O in setup time) 20* TioR Port output rise time 21* TioF Port output fall time Units Conditions 0.25TCY + 25 — — ns Note 1 0 — — ns Note 1 — — 80 - 100 ns TBD — — ns TBD — — ns PIC16C61 — 10 25 ns PIC16LC61 — — 60 ns PIC16C61 — 10 25 ns PIC16LC61 — — 60 ns 22††* Tinp RB0/INT pin high or low time 20 — — ns 23††* Trbp RB7:RB4 change int high or low time 20 — — ns * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 166  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 15-1 for load conditions. TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No. Sym Characteristic Min 30* TmcL MCLR Pulse Width (low) 200 — — ns VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +125°C * † 32 Tost 33* Tpwrt 34* TIOZ Typ† Max Units Conditions TOSC = OSC1 period Oscillation Start-up Timer Period — 1024TOSC — Power-up Timer Period 28 72 132 ms I/O Hi-impedance from MCLR Low — — 100 ns VDD = 5V, -40°C to +125°C These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 167 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-5: TIMER0 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 TMR0 Note: Refer to Figure 15-1 for load conditions. TABLE 15-5: Parameter No. 40* TIMER0 EXTERNAL CLOCK REQUIREMENTS Sym Characteristic Tt0H T0CKI High Pulse Width Min No Prescaler With Prescaler 41* Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* Tt0P T0CKI Period No Prescaler With Prescaler * † Typ† Max Units Conditions 0.5TCY + 20 — — ns 10 — — ns 0.5TCY + 20 — — ns 10 — — ns TCY + 40 — — ns Greater of: 20 ns or TCY + 40 N — — ns Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 168  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C61 Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution while 'max' or 'min' represents (mean +3) and (mean -3) respectively where  is standard deviation. The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC FOSC (25C) Frequency Normalized TO +25C 1.050 REXT  10 k CEXT = 100 pF 1.025 1.00 VDD = 5.5V 0.975 0.950 0.925 VDD = 3.5V 0.900 0.875 0.850 0 10 20 25 30 40 50 60 70 T (C) TABLE 16-1: RC OSCILLATOR FREQUENCIES Cext Rext 20 pF 4.7k 10k 100k 3.3k 4.7k 10k 100k 3.3k 4.7k 10k 100k 100 pF 300 pF Average Fosc @ 5V, 25C 4.52 MHz 2.47 MHz 290.86 kHz 1.92 MHz 1.48 MHz 788.77 kHz 88.11 kHz 726.89 kHz 573.95 kHz 307.31 kHz 33.82 kHz  17.35%  10.10%  11.90%  9.43%  9.83%  10.92%  16.03%  10.97%  10.14%  10.43%  11.24% The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V.  1997-2013 Microchip Technology Inc. DS30234E-page 169 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD 8.0 5.0 R = 3.3k 4.5 R = 4.7k 7.0 4.0 6.0 R = 4.7k 5.0 3.0 Fosc (MHz) Fosc (MHz) 3.5 R = 10k 2.5 4.0 R = 10k 2.0 3.0 1.5 2.0 1.0 Cext = 300 pF, T = 25C 1.0 0.5 R = 100k R = 100k 0.0 3.0 3.5 4.0 4.5 5.0 5.5 0.0 3.0 6.0 3.5 4.0 VDD (Volts) 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD 2.0 FIGURE 16-5: TYPICAL IPD VS. VDD WATCHDOG TIMER DISABLED 25C 0.6 R = 3.3k 1.8 1.6 0.5 1.4 R = 4.7k 1.2 0.4 1.0 IPD (A) Fosc (MHz) Data based on matrix samples. See first page of this section for details. Cext = 20 pF, T = 25C 0.8 R = 10k 0.3 0.6 0.2 0.4 Cext = 100 pF, T = 25C 0.2 0.1 R = 100k 0.0 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30234E-page 170  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-6: TYPICAL IPD VS. VDD WATCHDOG TIMER ENABLED 25C FIGURE 16-7: MAXIMUM IPD VS. VDD WATCHDOG DISABLED 25 14 125C 12 20 10 IPD (A) IPD (A) 15 8 6 10 70C 5 2 0 3.0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 0C -40C -55C 6.0 VDD (Volts)  1997-2013 Microchip Technology Inc. DS30234E-page 171 Data based on matrix samples. See first page of this section for details. 85C 4 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-8: MAXIMUM IPD VS. VDD WATCHDOG ENABLED* FIGURE 16-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD 45 -55C -40C 40 2.00 1.80 IPD (A) 30 125C 25 VTH (Volts) 35 Max (-40C to 85C) 1.60 25C, Typ 1.40 1.20 Min (-40C to 85C) 1.00 20 0.80 15 0.60 2.5 0C 70C 85C 3.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 6.0 10 Data based on matrix samples. See first page of this section for details. 5 0 3.0 3.5 4.0 4.5 5.0 VDD (Volts) 5.5 6.0 *IPD, with Watchdog Timer enabled, has two components: The leakage current which increases with higher temperature and the operating current of the Watchdog Timer logic which increases with lower temperature. At -40C, the latter dominates explaining the apparently anomalous behavior. DS30234E-page 172  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD 4.5 VIH, Max (-40C to 85C) VIH, Typ (25C) 4.0 VIH, Min (-40C to 85C) VIH, VIL (Volts) 3.5 3.0 2.5 2.0 1.5 VIL, Max (-40C to 85C) 1.0 VIL, Typ (25C) VIL, Min (-40C to 85C) 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FIGURE 16-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) VS. VDD 3.6 Max (-40C to 85C) 3.4 Typ (25C) 3.2 Min (-40C to 85C) 3.0 VTH (Volts) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts)  1997-2013 Microchip Technology Inc. DS30234E-page 173 Data based on matrix samples. See first page of this section for details. VDD (Volts) These pins have Schmitt Trigger input buffers. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-12: TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 IDD (A) 1,000 100 1 10,000 100,000 1,000,000 100,000,000 10,000,000 Frequency (Hz) FIGURE 16-13: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -40 TO +85C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 IDD (A) Data based on matrix samples. See first page of this section for details. 10 100 10 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz) DS30234E-page 174  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-14: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -55 TO +125C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 IDD (A) 1,000 10 10,000 100,000 1,000,000 100,000,000 10,000,000 Frequency (Hz) FIGURE 16-15: WDT TIMER TIME-OUT PERIOD VS. VDD FIGURE 16-16: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR VS. VDD 50 9000 45 8000 40 7000 Max. -40C 6000 gm (A/V) WDT period (ms) 35 30 Max. 85C 5000 4000 25 Typ. 25C Max. 70C 3000 20 Typ. 25C MIn. 85C 2000 15 Min. 0C 1000 10 Min. -40C 0 5 2 2 3 4 5 6 7 3 4 5 6 7 VDD (Volts) VDD (Volts)  1997-2013 Microchip Technology Inc. DS30234E-page 175 Data based on matrix samples. See first page of this section for details. 100 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-17: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR VS. VDD FIGURE 16-19: IOH VS. VOH, VDD = 3V 0 225 -5 200 MIn. 85C Max. -40C 175 150 -10 IOH (mA) gm (A/V) Typ. 25C 125 100 Typ. 25C -15 MIn. 85C 75 -20 25 Max. -40C 0 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 -25 6.0 0 FIGURE 16-18: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR VS. VDD 0.5 1.0 1.5 VOH (Volts) 2.0 2.5 3.0 FIGURE 16-20: IOH VS. VOH, VDD = 5V 0 2500 -5 Max. -40C -10 200 IOH (mA) -15 1500 gm (A/V) Data based on matrix samples. See first page of this section for details. 50 Typ. 25C -20 Min @ 85C -25 Typ @ 25C -30 100 -35 MIn. 85C -40 Max @ -40C 500 -45 -50 0.0 0.5 0 2 3 4 5 VDD (Volts) DS30234E-page 176 6 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 7 VOH (Volts)  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-21: IOL VS. VOL, VDD = 3V FIGURE 16-22: IOL VS. VOL, VDD = 5V 90 35 80 Min @ -40C 30 Min @ -40C 70 25 60 Typ @ 25C Typ @ 25C IOL (mA) IOL (mA) 20 15 50 Min @ +85C 40 Min @ +85C 30 10 5 10 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOL (Volts) TABLE 16-2: VOL (Volts) INPUT CAPACITANCE* Pin Name RA port Typical Capacitance (pF) 18L PDIP 18L SOIC 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1/CLKIN 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 *All capacitance values are typical at 25C. A part to part variation of 25% (three standard deviations) should be taken into account.  1997-2013 Microchip Technology Inc. DS30234E-page 177 Data based on matrix samples. See first page of this section for details. 20 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 178  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C62/64 Absolute Maximum Ratings † Ambient temperature under bias...............................................................................................................-55°C to +85°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)............................................................................................... 0V to +14V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE* (combined) ................................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE* (combined) ...........................................................200 mA Maximum current sunk by PORTC and PORTD* (combined)...............................................................................200 mA Maximum current sourced by PORTC and PORTD* (combined) .........................................................................200 mA * PORTD and PORTE not available on the PIC16C62. Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 17-1: OSC CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C62-04 PIC16C64-04 PIC16C62-10 PIC16C64-10 PIC16C62-20 PIC16C64-20 PIC16LC62-04 PIC16LC64-04 JW Devices RC VDD: 4.0V to 6.0V IDD: 3.8 mA max. at 5.5V IPD: 21 A max. at 4V Freq:4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq:4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq:4 MHz max. VDD: 3.0V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 13.5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 3.8 mA max. at 5.5V IPD: 21 A max. at 4V Freq:4 MHz max. XT VDD: 4.0V to 6.0V IDD: 3.8 mA max. at 5.5V IPD: 21 A max. at 4V Freq:4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq:4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq:4 MHz max. VDD: 3.0V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 13.5 A max. at 3.0V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 3.8 mA max. at 5.5V IPD: 21 A max. at 4V Freq:4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V LP IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq:4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq:200 kHz max. Not recommended for use in LP mode Not recommended for use in LP mode VDD: 4.5V to 5.5V IDD: 30 mA max. at 5.5V Not recommended for use in HS mode IPD: 1.5 A typ. at 4.5V VDD: 3.0V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 13.5 A max. at 3.0V Freq:200 kHz max. VDD: 3.0V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD:13.5 A max. at 3.0V Freq:200 kHz max. Freq: 20 MHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 179 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C62/64-04 (Commercial, Industrial) PIC16C62/64-10 (Commercial, Industrial) PIC16C62/64-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to VPOR ensure internal Poweron Reset signal - VSS - V D004* VDD rise rate to ensure SVDD internal Power-on Reset signal 0.05 - - D010 Supply Current (Note 2, 5) - 2.7 5.0 mA XT, RC, osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V - 10.5 1.5 1.5 42 21 24 A A A VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C IDD D013 D020 D021 D021A Power-down Current (Note 3, 5) IPD XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. DS30234E-page 180  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.2 DC Characteristics: DC CHARACTERISTICS Param No. D001 D002* D003 D004* D010 Characteristic PIC16LC62/64-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Poweron Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2, 5) D010A VDD VDR 3.0 - 1.5 6.0 - V V LP, XT, RC osc configuration (DC - 4 MHz) VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C IDD V/ms See section on Power-on Reset for details D020 Power-down Current IPD 7.5 30 A D021 (Note 3, 5) 0.9 13.5 A D021A 0.9 18 A * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 181 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.3 DC Characteristics: PIC16C62/64-04 (Commercial, Industrial) PIC16C62/64-10 (Commercial, Industrial) PIC16C62/64-20 (Commercial, Industrial) PIC16LC62/64-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D083 OSC2/CLKOUT (RC osc config) D090 Output High Voltage I/O ports (Note 3) D092 OSC2/CLKOUT (RC osc config) D150* Open-Drain High Voltage Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.2 Sym Min Typ Max Units Conditions † VIL VSS VSS VSS Vss Vss - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V  VDD  5.5V Note1 2.0 0.25VDD + 0.8V - VDD VDD V V 4.5V  VDD  5.5V For entire VDD range VDD VDD VDD VDD 400 V V V A VIH IPURB IIL VOL VOH VOD 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 200 For entire VDD range - - 1 A - - 5 5 A A - - 0.6 V - - 0.6 V VDD-0.7 - - V VDD-0.7 - - V - - 14 V Note1 VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 182  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 17.1 and Section 17.2 Sym Min Typ Max Units Conditions † D100 Capacitive Loading Specs on Output Pins OSC2 pin COSC2 D101 D102 SCL, SDA in I2C mode All I/O pins and OSC2 (in RC mode) CIO Cb - - 15 pF - - 50 400 pF pF In XT, HS and LP modes when external clock is used to drive OSC1. * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 183 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 17-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports Note 1: PORTD and PORTE are not implemented on the PIC16C62. for OSC2 output DS30234E-page 184  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.5 Timing Diagrams and Specifications FIGURE 17-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 17-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) Typ† Max Units Conditions DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode XT osc mode 0.1 — 4 MHz 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 1,000 ns HS osc mode (-20) 5 — — s LP osc mode TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns 3 TosL, TosH External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator 2.5 — — s LP oscillator TosR, TosF External Clock in (OSC1) Rise or Fall Time 4 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 185 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 17-1 for load conditions. TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameters Sym Min Typ† Max 10* TosH2ckL OSC1 to CLKOUT Characteristic — 75 200 Units Conditions ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 — — 0.5TCY + 20 ns Note 1 TOSC + 200 — — ns Note 1 Note 1 14* TckL2ioV CLKOUT  to Port out valid 15* TioV2ckH Port in valid before CLKOUT  16* TckH2ioI Port in hold after CLKOUT  0 — — ns 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port PIC16C62/64 input invalid (I/O in hold time) PIC16LC62/64 100 — — ns 200 — — ns 0 — — ns PIC16C62/64 — 10 40 ns PIC16LC62/64 — — 80 ns PIC16C62/64 — 10 40 ns 19* TioV2osH Port input valid to OSC1 (I/O in setup time) 20* TioR Port output rise time 21* TioF Port output fall time — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns PIC16LC62/64 * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 186  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 17-1 for load conditions. TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No. Sym Characteristic Min 30* TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40°C to +85°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +85°C * † 32 Tost 33* Tpwrt 34* TIOZ Typ† Max Units Conditions Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C I/O Hi-impedance from MCLR Low — — 100 ns These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 187 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSI/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 17-1 for load conditions. TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.5TCY + 20 — — ns 10 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1P T1CKI input period Synchronous PIC16C6X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC6X 50 OR TCY + 40 N Asynchronous PIC16C6X 60 PIC16LC6X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Tt0L Typ† Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) — — — — — 200 ns ns kHz — 7Tosc — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 188  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 54 53 Note: Refer to Figure 17-1 for load conditions. TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Parameter No. Sym Characteristic 50* TccL CCP1 input low time Min No Prescaler With Prescaler PIC16C62/64 PIC16LC62/64 51* TccH CCP1 input high time No Prescaler With Prescaler PIC16C62/64 PIC16LC62/64 52* TccP CCP1 input period 53 TccR CCP1 output rise time 54 * † TccF CCP1 output fall time PIC16C62/64 Typ† Max Units Conditions 0.5TCY + 20 — — ns 10 — — ns 20 — — ns 0.5TCY + 20 — — ns 10 — — ns 20 — — ns 3TCY + 40 N — — ns — 10 25 ns PIC16LC62/64 — 25 45 ns PIC16C62/64 — 10 25 ns PIC16LC62/64 — 25 45 ns N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 189 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-7: PARALLEL SLAVE PORT TIMING (PIC16C64) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 17-1 for load conditions TABLE 17-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64) Parameter No. Sym 62 TdtV2wrH 63* TwrH2dtI * † Characteristic Min Typ† Max Units Data in valid before WR or CS (setup time) 20 — — ns WR or CS to data–in invalid PIC16C64 (hold time) PIC16LC64 20 — — ns 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns 65 TrdH2dtI RD or CS to data–out invalid 10 — 30 ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 190  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 17-1 for load conditions TABLE 17-8: Parameter No. 70 † SPI MODE REQUIREMENTS Sym TssL2scH, TssL2scL Characteristic Min Typ† Max Units SS to SCK or SCK input TCY — — ns 71 TscH SCK input high time (slave mode) TCY + 20 — — ns 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 — — ns 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns Conditions Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 191 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-9: I2C BUS START/STOP BITS TIMING SCL 91 93 92 90 SDA STOP Condition START Condition Note: Refer to Figure 17-1 for load conditions TABLE 17-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 92 93 THD:STA TSU:STO THD:STO DS30234E-page 192 Characteristic Min Typ Max START condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-10: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 17-1 for load conditions TABLE 17-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time Min Max Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP Module 101 TLOW Clock low time 1.5TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF START condition setup time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s Only relevant for repeated START condition START condition hold time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SSP Module 102 103 90 91 106 107 92 109 110 TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Cb Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns STOP condition setup time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF Bus capacitive loading Cb is specified to be from 10 to 400 pF After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT  250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 193 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 194  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.0 ELECTRICAL CHARACTERISTICS FOR PIC16C62A/R62/64A/R64 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)............................................................................................... 0V to +14V Voltage on RA4 with respect to Vss ................................................................................................................ 0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (combined)..................................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) ............................................................200 mA Maximum current sunk by PORTC and PORTD (combined) ................................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) ...........................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 18-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C62A-04 PIC16CR62-04 PIC16C64A-04 PIC16CR64-04 PIC16C62A-10 PIC16CR62-10 PIC16C64A-10 PIC16CR64-10 PIC16C62A-20 PIC16CR62-20 PIC16C64A-20 PIC16CR64-20 PIC16LC62A-04 PIC16LCR62-04 PIC16LC64A-04 PIC16LCR64-04 RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq:4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq:4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.0 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5 A max. at 3.0V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V OSC XT HS VDD: 4.5V to 5.5V JW Devices VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V Not recommended for use IDD: 20 mA max. at 5.5V in HS mode IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. LP VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Freq: 10 MHz max. Not recommended for use in LP mode Freq: 20 MHz max. Not recommended for use in LP mode Freq: 20 MHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 195 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C62A/R62/64A/R64-04 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-10 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Range Only - 2.7 5 mA - 10 20 mA - 350 425 A BOR enabled, VDD = 5.0V - 10.5 1.5 1.5 2.5 42 16 19 19 A A A A VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -0C to +70C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +125C - 350 425 A BOR enabled, VDD = 5.0V D010 Supply Current (Note 2, 5) IDD D013  IBOR D015* Brown-out Reset Current (Note 6) D020 D021 D021A D021B Power-down Current (Note IPD 3, 5) D023* Brown-out Reset Current (Note 6)  IBOR XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details XT, RC, osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration FOSC = 20 MHz, VDD = 5.5V * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 196  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.2 DC Characteristics: PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D001 D002* D003 D004* D005 D010 Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2, 5) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions VDD VDR 2.5 - 1.5 6.0 - V V LP, XT, RC osc configuration (DC - 4 MHz) VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - BVDD IDD 3.7 - 4.0 2.0 4.3 3.8 V mA BODEN bit in configuration word enabled XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled IBOR - 350 425 A BOR enabled, VDD = 5.0V IPD - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C D010A D015* D020 D021 D021A Brown-out Reset Current (Note 6) Power-down Current (Note 3, 5) V/ms See section on Power-on Reset for details Brown-out Reset Current IBOR 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. D023*  1997-2013 Microchip Technology Inc. DS30234E-page 197 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.3 DC Characteristics: PIC16C62A/R62/64A/R64-04 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-10 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-20 (Commercial, Industrial, Extended) PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.2 Sym Min Typ Max Units Conditions † VIL Vss VSS Vss Vss Vss VIH 2.0 0.25VDD + 0.8V D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current IPURB Input Leakage Current (Notes 2, 3) I/O ports IIL D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC osc config) D083A VOL - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V  VDD  5.5V - VDD VDD V V 4.5V  VDD  5.5V For entire VDD range VDD VDD VDD VDD 400 V V V V A For entire VDD range Vss VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 - - 1 A - - 5 5 A A - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V Note1 Note1 VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 198  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. D090 Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 18.1 and Section 18.2 Sym Min Typ Max Units Conditions † VOH D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* D100 Open-Drain High Voltage VOD Capacitive Loading Specs on Output Pins OSC2 pin COSC2 VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V - - 14 V - - 15 pF IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. 50 pF All I/O pins and OSC2 (in RC mode) CIO Cb 400 pF SCL, SDA in I2C mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. D101 D102  1997-2013 Microchip Technology Inc. DS30234E-page 199 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 18-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin VSS CL Pin VSS RL = 464 CL = 50 pF Note 1: PORTD and PORTE are not implemented on the PIC16C62A/R62. DS30234E-page 200 15 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports for OSC2 output  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.5 Timing Diagrams and Specifications FIGURE 18-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 18-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode LP osc mode Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) Max Units Conditions 5 — 200 kHz 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC TosL, TosH External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator 2.5 — — s LP oscillator TosR, TosF External Clock in (OSC1) Rise or Fall Time 2 TCY 3 4 Typ† 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 201 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 10 11 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 18-1 for load conditions. TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameters Sym Min Typ† Max 10* TosH2ckL OSC1 to CLKOUT Characteristic — 75 200 Units Conditions ns 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 Note 1 Note 1 13* TckF CLKOUT fall time — 35 100 ns 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input PIC16C62A/ invalid (I/O in hold time) R62/64A/R64 100 — — ns PIC16LC62A/ R62/64A/R64 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C62A/ R62/64A/R64 — 10 40 ns PIC16LC62A/ R62/64A/R64 — — 80 ns PIC16C62A/ R62/64A/R64 — 10 40 ns PIC16LC62A/ R62/64A/R64 — — 80 ns 21* TioF Port output fall time 22††* Tinp RB0/INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change int high or low time TCY — — ns * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 202  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 18-1 for load conditions. FIGURE 18-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 18-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +125°C 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O Hi-impedance from MCLR Low or WDT Reset — — 2.1 s TBOR Brown-out Reset Pulse Width 100 — — s 35 * † Min VDD  BVDD (param. D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 203 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 18-1 for load conditions. TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.5TCY + 20 — — ns 10 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1P T1CKI input period Synchronous PIC16C6X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC6X 50 OR TCY + 40 N Asynchronous PIC16C6X 60 PIC16LC6X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Tt0L Typ† Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) — — — — — 200 ns ns kHz — 7Tosc — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 204  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 18-1 for load conditions. TABLE 18-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Parameter Sym Characteristic No. 50* TccL CCP1 input low time Min No Prescaler With Prescaler PIC16C62A/R62/ 64A/R64 PIC16LC62A/R62/ 64A/R64 51* TccH CCP1 input high time No Prescaler 53* TccR CCP1 output rise time 54* * † TccF CCP1 output fall time — — ns 10 — — ns 20 — — ns — — ns 10 — — ns 20 — — ns 3TCY + 40 N — — ns PIC16C62A/R62/ 64A/R64 — 10 25 ns PIC16LC62A/R62/ 64A/R64 — 25 45 ns PIC16C62A/R62/ 64A/R64 — 10 25 ns PIC16LC62A/R62/ 64A/R64 — 25 45 ns PIC16LC62A/R62/ 64A/R64 TccP CCP1 input period 0.5TCY + 20 0.5TCY + 20 With Prescaler PIC16C62A/R62/ 64A/R64 52* Typ† Max Units Conditions N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 205 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-8: PARALLEL SLAVE PORT TIMING (PIC16C64A/R64) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 18-1 for load conditions TABLE 18-7: Parameter No. 62 63* 64 65* * † PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64A/R64) Sym Characteristic Min Typ† Max Units 20 — — ns 25 — — ns PIC16C64A/R64 20 — — ns PIC16LC64A.R64 35 — — ns — — 80 ns — — 90 ns 10 — 30 ns TdtV2wrH Data in valid before WR or CS (setup time) TwrH2dtI TrdL2dtV TrdH2dtI WR or CS to data–in invalid (hold time) RD and CS to data–out valid RD or CS to data–out invalid Conditions Extended Range Only Extended Range Only These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 206  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 18-1 for load conditions TABLE 18-8: Parameter No. 70* * † SPI MODE REQUIREMENTS Sym TssL2scH, TssL2scL Characteristic Min Typ† Max Units SS to SCK or SCK input TCY — — ns 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 — — ns 74* TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 — — ns 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 207 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-10: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 18-1 for load conditions TABLE 18-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90* TSU:STA 91* 92* 93* THD:STA TSU:STO THD:STO Characteristic Min Typ Max START condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns *These parameters are characterized but not tested. DS30234E-page 208  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 92 91 SDA In 110 109 109 SDA Out Note: Refer to Figure 18-1 for load conditions TABLE 18-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100* THIGH Clock high time 101* 102* 103* TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90* TSU:STA START condition setup time 91* THD:STA START condition hold time 106* THD:DAT Data input hold time 107* TSU:DAT Data input setup time 92* TSU:STO STOP condition setup time 109* TAA 110* TBUF Output valid from clock Bus free time Min Max Units Conditions 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 — — s 400 kHz mode 1.3 — s SSP Module 100 kHz mode 400 kHz mode 1.5TCY — 20 + 0.1Cb — 1000 300 ns ns 100 kHz mode 400 kHz mode — 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 — — 4.7 1.3 — — — — — 0.9 — — — — 3500 — — — s s s s ns s ns ns s s ns ns s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10-400 pF Cb is specified to be from 10-400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT  250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 209 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 210  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C65 Absolute Maximum Ratings † Ambient temperature under bias...............................................................................................................-55°C to +85°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)............................................................................................... 0V to +14V Voltage on RA4 with respect to Vss ................................................................................................................ 0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (combined)..................................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) ............................................................200 mA Maximum current sunk by PORTC and PORTD (combined) ................................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) ...........................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 19-1: OSC CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C65-10 PIC16C65-20 RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 3.0V to 6.0V IDD: 3.8 mA max. at 3V IPD: 800 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 3.0V to 6.0V IDD: 3.8 mA max. at 3V IPD: 800 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V IPD 1.0 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. LP PIC16C65-04 VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Not recommended for use in LP mode PIC16LC65-04 JW Devices VDD: 4.5V to 5.5V Not recommended for use in HS mode Freq: 20 MHz max. VDD: 3.0V to 6.0V IDD: 105 A max. Not recommended for at 32 kHz, 3.0V use in LP mode IPD: 800 A max. at 3.0V Freq: 200 kHz max. IDD: 30 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 3.0V to 6.0V IDD: 105 A max. at 32 kHz, 3.0V IPD: 800 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 211 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C65-04 (Commercial, Industrial) PIC16C65-10 (Commercial, Industrial) PIC16C65-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D010 Supply Current (Note 2, 5) IDD - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V - 10.5 1.5 1.5 800 800 800 A A A VDD = 4.0V, WDT enabled,-40C to +85C VDD = 4.0V, WDT disabled,-0C to +70C VDD = 4.0V, WDT disabled,-40C to +85C D013 D020 D021 D021A Power-down Current (Note 3, 5) IPD XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. DS30234E-page 212  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.2 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic D001 D002* Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current (Note 2, 5) D003 D004* D010 D010A PIC16LC65-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions VDD VDR 3.0 - 1.5 6.0 - V V LP, XT, RC osc configuration (DC - 4 MHz) VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 105 A LP osc configuration FOSC = 32 kHz, VDD = 4.0V, WDT disabled VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C IDD V/ms See section on Power-on Reset for details D020 Power-down Current IPD 7.5 800 A D021 (Note 3, 5) 0.9 800 A D021A 0.9 800 A * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 213 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.3 DC Characteristics: PIC16C65-04 (Commercial, Industrial) PIC16C65-10 (Commercial, Industrial) PIC16C65-20 (Commercial, Industrial) PIC16LC65-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D030 D030A D031 D032 D033 D040 D040A D041 D042 D042A D043 D070 Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1(in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D083 OSC2/CLKOUT (RC osc config) D090 Output High Voltage I/O ports (Note 3) D092 OSC2/CLKOUT (RC osc config) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.2 Sym Min Typ Max Units Conditions † VIL VSS VSS VSS Vss Vss VIH 2.0 0.25VDD + 0.8V IPURB IIL VOL VOH - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V  VDD  5.5V - VDD VDD V V 4.5V  VDD  5.5V For entire VDD range VDD VDD VDD VDD 400 V V V A 0.8VDD 0.8VDD 0.7 VDD 0.9VDD 50 250 Note1 For entire VDD range - - 1 A - - 5 5 A A - - 0.6 V - - 0.6 V VDD-0.7 - - V VDD-0.7 - - V Note1 VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS, and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin 14 V D150* Open-Drain High Voltage VOD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 214  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. D100 Characteristic Capacitive Loading Specs on Output Pins OSC2 pin Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 19.1 and Section 19.2 Sym Min Typ Max Units Conditions † COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. 50 pF All I/O pins and OSC2 (in RC mode) CIO Cb 400 pF SCL, SDA in I2C mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. D101 D102  1997-2013 Microchip Technology Inc. DS30234E-page 215 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 19-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 CL Pin RL VSS CL Pin RL = 464 VSS CL = 50 pF 15 pF DS30234E-page 216 for all pins except OSC2/CLKOUT but including D and E outputs as ports for OSC2 output  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.5 Timing Diagrams and Specifications FIGURE 19-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 19-2: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode LP osc mode Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) Max Units Conditions 5 — 200 kHz 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC TosL, TosH External Clock in (OSC1) High or Low Time 50 — — ns XT oscillator 2.5 — — s LP oscillator TosR, TosF External Clock in (OSC1) Rise or Fall Time 2 TCY 3 4 Typ† 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 217 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 19-1 for load conditions. TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No. Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16C65 100 — — ns PIC16LC65 200 — — ns 0 — — ns PIC16C65 — 10 25 ns PIC16LC65 — — 60 ns PIC16C65 — 10 25 ns PIC16LC65 — — 60 ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 20* TioR Port output rise time 21* TioF Port output fall time 22††* Tinp RB0/INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change int high or low time TCY — — ns * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 218  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 19-1 for load conditions. TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No. Sym Characteristic Min 30* TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40°C to +85°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +85°C * † Typ† Max Units Conditions 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period or WDT reset 28 72 132 ms VDD = 5V, -40°C to +85°C 34 TIOZ I/O Hi-impedance from MCLR Low — — 100 ns These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 219 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 19-1 for load conditions. TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.5TCY + 20 — — ns 10 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1P T1CKI input period Synchronous PIC16C6X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC6X 50 OR TCY + 40 N Asynchronous PIC16C6X 60 PIC16LC6X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Tt0L Typ† Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) — — — — — 200 ns ns kHz — 7Tosc — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 220  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 19-1 for load conditions. TABLE 19-6: Parameter No. 50* 51* Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min With Prescaler 0.5TCY + 20 — — ns 10 — — ns PIC16LC65 20 — — ns 0.5TCY + 20 — — ns PIC16C65 10 — — ns PIC16LC65 20 — — ns 3TCY + 40 N — — ns No Prescaler With Prescaler TccP CCP1 and CCP2 input period 53 TccR CCP1 and CCP2 output rise time TccF CCP1 and CCP2 output fall time Typ† Max Units Conditions PIC16C65 No Prescaler 52* 54 * † CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) PIC16C65 — 10 25 ns PIC16LC65 — 25 45 ns PIC16C65 — 10 25 ns PIC16LC65 — 25 45 ns N = prescale value (1,4, or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 221 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-7: PARALLEL SLAVE PORT TIMING RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 19-1 for load conditions TABLE 19-7: Parameter No. * † PARALLEL SLAVE PORT REQUIREMENTS Sym Characteristic Min 62 TdtV2wrH Data in valid before WR or CS (setup time) 63* TwrH2dtI WR or CS to data–in invalid (hold time) 64 TrdL2dtV RD and CS to data–out valid 65 TrdH2dtI RD or CS to data–out invalid Typ† Max Units 20 — — ns PIC16C65 20 — — ns PIC16LC65 35 — — ns — — 80 ns 10 — 30 ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 222  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 19-1 for load conditions TABLE 19-8: Parameter No. 70 † SPI MODE REQUIREMENTS Sym TssL2scH, TssL2scL Characteristic Min Typ† Max Units SS to SCK or SCK input TCY — — ns 71 TscH SCK input high time (slave mode) TCY + 20 — — ns 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 — — ns 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns Conditions Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 223 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-9: I2C BUS START/STOP BITS TIMING SCL 91 93 92 90 SDA STOP Condition START Condition Note: Refer to Figure 19-1 for load conditions TABLE 19-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90 TSU:STA 91 92 93 THD:STA TSU:STO THD:STO DS30234E-page 224 Characteristic Min Typ Max START condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-10: I2C BUS DATA TIMING 103 102 100 101 SCL 106 90 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 19-1 for load conditions TABLE 19-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time Min Max Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Devce must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP Module 101 TLOW Clock low time 1.5TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF START condition setup time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s Only relevant for repeated START condition START condition hold time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SSP Module 102 103 90 91 106 107 92 109 110 TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Cb Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns STOP condition setup time 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF Bus capacitive loading Cb is specified to be from 10-400 pF After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 225 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 19-1 for load conditions TABLE 19-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter Sym No. 120 Min TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid 121 Tckrf 122 †: Characteristic Tdtrf Typ† Max Units Conditions PIC16C65 — — 80 ns PIC16LC65 — — 100 ns ns Clock out rise time and fall time (Master Mode) PIC16C65 — — 45 PIC16LC65 — — 50 ns Data out rise time and fall time PIC16C65 — — 45 ns PIC16LC65 — — 50 ns Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 19-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 19-1 for load conditions TABLE 19-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. †: Sym Characteristic Min Typ† Max Units Conditions 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK  (DT hold time) 15 — — ns Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 226  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.0 ELECTRICAL CHARACTERISTICS FOR PIC16C63/65A Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)............................................................................................... 0V to +14V Voltage on RA4 with respect to Vss ................................................................................................................ 0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined) ..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined) .............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16C63. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 20-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C63-04 PIC16C65A-04 PIC16C63-10 PIC16C65A-10 PIC16C63-20 PIC16C65A-20 PIC16LC63-04 PIC16LC65A-04 JW Devices RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V OSC IPD: 1.5 A typ. at 4.5V IPD 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. LP VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Freq: 10 MHz max. Not recommended for use in LP mode VDD: 4.5V to 5.5V Not recommended for use in HS mode Freq: 20 MHz max. Not recommended for use in LP mode IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 227 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C63/65A-04 (Commercial, Industrial, Extended) PIC16C63/65A-10 (Commercial, Industrial, Extended) PIC16C63/65A-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled 3.7 4.0 4.4 V Extended Range Only - 2.7 5 mA XT, RC, osc config FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 mA HS osc config FOSC = 20 MHz, VDD = 5.5V IBOR - 350 425 A BOR enabled, VDD = 5.0V D020 Power-down Current D021 (Note 3, 5) D021A D021B IPD - 10.5 1.5 1.5 2.5 42 16 19 19 A A A A VDD = 4.0V, WDT enabled,-40C to +85C VDD = 4.0V, WDT disabled,-0C to +70C VDD = 4.0V, WDT disabled,-40C to +85C VDD = 4.0V, WDT disabled,-40C to +125C D023* IBOR - 350 425 A BOR enabled, VDD = 5.0V D010 Supply Current (Note 2, 5) IDD D013 D015* Brown-out Reset Current (Note 6) Brown-out Reset Current (Note 6) XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 228  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.2 DC Characteristics: PIC16LC63/65A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D001 D002* D003 D004* D005 D010 Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2, 5) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions VDD VDR 2.5 - 1.5 6.0 - V V LP, XT, RC osc configuration (DC - 4 MHz) VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - BVDD IDD 3.7 - 4.0 2.0 4.3 3.8 V mA BODEN configuration bit is enabled XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled IBOR - 350 425 A BOR enabled, VDD = 5.0V IPD - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C D010A D015* D020 D021 D021A Brown-out Reset Current (Note 6) Power-down Current (Note 3, 5) V/ms See section on Power-on Reset for details Brown-out Reset Current IBOR 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. D023*  1997-2013 Microchip Technology Inc. DS30234E-page 229 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.3 DC Characteristics: PIC16C63/65A-04 (Commercial, Industrial, Extended) PIC16C63/65A-10 (Commercial, Industrial, Extended) PIC16C63/65A-20 (Commercial, Industrial, Extended) PIC16LC63/65A-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D030 D030A D031 D032 D033 D040 D040A D041 D042 D042A D043 D070 Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2 Sym Min Typ Max Units Conditions † VIL VSS VSS VSS Vss Vss VIH 2.0 0.25VDD + 0.8V D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current IPURB Input Leakage Current (Notes 2, 3) I/O ports IIL D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC osc config) D083A VOL - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V For entire VDD range 4.5V  VDD  5.5V - VDD VDD V V 4.5V  VDD  5.5V For entire VDD range VDD VDD VDD VDD 400 V V V V A For entire VDD range 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 - - 1 A - - 5 5 A A - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V Note1 Note1 VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 230  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 20.1 and Section 20.2 Sym Min Typ Max Units Conditions † VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V - - 14 V D100 Open-Drain High Voltage VOD Capacitive Loading Specs on Output Pins OSC2 pin COSC2 - - 15 pF D101 D102 SCL, SDA in I2C mode All I/O pins and OSC2 (in RC mode) CIO Cb - - 50 400 pF pF D090 VOH D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 231 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 20-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS Note 1: PORTD and PORTE are not implemented on the PIC16C63. DS30234E-page 232 CL = 50 pF 15 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports for OSC2 output  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.5 Timing Diagrams and Specifications FIGURE 20-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 20-2: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode XT osc mode Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 TCY 3* TosL, TosH 4* TosR, TosF Typ† Max Units Conditions 0.1 — 4 MHz 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator External Clock in (OSC1) Rise or Fall Time 2.5 — — s LP oscillator 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 233 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 20-1 for load conditions. TABLE 20-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No. Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16C63/65A 100 — — ns PIC16LC63/65A 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time ns PIC16C63/65A — 10 40 PIC16LC63/65A — — 80 ns PIC16C63/65A — 10 40 ns 21* TioF Port output fall time — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns PIC16LC63/65A Note 1 * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 234  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 20-1 for load conditions. FIGURE 20-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 20-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +125°C Typ† Max Units Conditions Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C TIOZ I/O Hi-impedance from MCLR Low or WDT reset — — 2.1 s TBOR Brown-out Reset Pulse Width 100 — — s 32 Tost 33* Tpwrt 34 35 * † Min VDD  BVDD (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 235 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 20-1 for load conditions. TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.5TCY + 20 — — ns 10 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1P T1CKI input period Synchronous PIC16C6X Greater of: 30 OR TCY + 40 N PIC16LC6X Greater of: 50 OR TCY + 40 N Asynchronous PIC16C6X 60 PIC16LC6X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Tt0L Typ† Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) — — — — — 200 ns ns kHz — 7Tosc — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 236  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 54 53 Note: Refer to Figure 20-1 for load conditions. TABLE 20-6: Parameter No. 50* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic Min TccL CCP1 and CCP2 input low time No Prescaler TccH CCP1 and CCP2 input high time No Prescaler With Prescaler PIC16C63/65A PIC16LC63/65A 51* With Prescaler PIC16C63/65A PIC16LC63/65A 52* TccP CCP1 and CCP2 input period 53* TccR CCP1 and CCP2 output rise time 54* * † TccF CCP1 and CCP2 output fall time Typ† Max Units Conditions 0.5TCY + 20 — — ns 10 — — ns ns 20 — — 0.5TCY + 20 — — ns 10 — — ns 20 — — ns 3TCY + 40 N — — ns PIC16C63/65A — 10 25 ns PIC16LC63/65A — 25 45 ns PIC16C63/65A — 10 25 ns PIC16LC63/65A — 25 45 ns N = prescale value (1,4, or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 237 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-8: PARALLEL SLAVE PORT TIMING (PIC16C65A) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 20-1 for load conditions TABLE 20-7: Parameter No. 62* 63* 64 65* * † PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65A) Sym Characteristic Min TdtV2wrH Data in valid before WR or CS (setup time) TwrH2dtI TrdL2dtV TrdH2dtI WR or CS to data–in invalid (hold time) RD and CS to data–out valid RD or CS to data–out invalid Typ† Max Units 20 — — ns 25 — — ns PIC16C65A 20 — — ns PIC16LC65A 35 — — ns — — 80 ns — — 90 ns 10 — 30 ns Conditions Extended Range Only Extended Range Only These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 238  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 20-1 for load conditions TABLE 20-8: Parameter No. 70* * † SPI MODE REQUIREMENTS Sym TssL2scH, TssL2scL Characteristic Min Typ† Max Units SS to SCK or SCK input TCY — — ns 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 — — ns 74* TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 — — ns 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 239 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-10: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 20-1 for load conditions TABLE 20-9: Parameter No. Sym 90* TSU:STA 91* 92* 93 * I2C BUS START/STOP BITS REQUIREMENTS THD:STA TSU:STO THD:STO Characteristic Min Typ Max START condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns These parameters are characterized but not tested. DS30234E-page 240  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 20-1 for load conditions TABLE 20-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100* THIGH Clock high time 101* 102* 103* TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90* TSU:STA START condition setup time 91* THD:STA START condition hold time 106* THD:DAT Data input hold time 107* TSU:DAT Data input setup time 92* TSU:STO STOP condition setup time 109* TAA 110* TBUF Output valid from clock Bus free time Min Max Units Conditions 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 — — s 400 kHz mode 1.3 — s SSP Module 100 kHz mode 400 kHz mode 1.5TCY — 20 + 0.1Cb — 1000 300 ns ns 100 kHz mode 400 kHz mode — 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 — — 4.7 1.3 — — — — — 0.9 — — — — 3500 — — — s s s s ns s ns ns s s ns ns s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10-400 pF Cb is specified to be from 10-400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 241 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 20-1 for load conditions TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter No. 120* Sym Characteristic Min Typ† TckH2dtV Max Units Conditions SYNC XMIT (MASTER & SLAVE) PIC16C63/65A Clock high to data out valid PIC16LC63/65A — — 80 — — 100 ns — — 45 ns ns 121* Tckrf Clock out rise time and fall time (Master Mode) PIC16C63/65A PIC16LC63/65A — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16C63/65A — — 45 ns PIC16LC63/65A — — 50 ns * †: These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 20-13: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 20-1 for load conditions TABLE 20-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. * †: Sym Characteristic Min Typ† Max Units Conditions 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 242  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.0 ELECTRICAL CHARACTERISTICS FOR PIC16CR63/R65 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)............................................................................................... 0V to +14V Voltage on RA4 with respect to Vss ................................................................................................................ 0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined) ..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined) .............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16CR63. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 21-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16CR63-04 PIC16CR65-04 PIC16CR63-10 PIC16CR65-10 PIC16CR63-20 PIC16CR65-20 PIC16LCR63-04 PIC16LCR65-04 JW Devices RC VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 3.0V to 5.5V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 3.0V to 5.5V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V OSC IPD: 1.5 A typ. at 4.5V IPD 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. LP VDD: 4.0V to 5.5V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Freq: 10 MHz max. Not recommended for use in LP mode VDD: 4.5V to 5.5V Not recommended for use in HS mode Freq: 20 MHz max. Not recommended for use in LP mode IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 3.0V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. VDD: 3.0V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 243 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16CR63/R65-04 (Commercial, Industrial) PIC16CR63/R65-10 (Commercial, Industrial) PIC16CR63/R65-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 5.5 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled D010 Supply Current (Note 2, 5) IDD - 2.7 5 mA XT, RC, osc config FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 mA HS osc config FOSC = 20 MHz, VDD = 5.5V IBOR - 350 425 A BOR enabled, VDD = 5.0V D020 Power-down Current D021 (Note 3, 5) D021A IPD - 10.5 1.5 1.5 42 16 19 A A A VDD = 4.0V, WDT enabled,-40C to +85C VDD = 4.0V, WDT disabled,-0C to +70C VDD = 4.0V, WDT disabled,-40C to +85C D023* IBOR - 350 425 A BOR enabled, VDD = 5.0V D013 D015* Brown-out Reset Current (Note 6) Brown-out Reset Current (Note 6) XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 244  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.2 DC Characteristics: PIC16LCR63/R65-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D001 D002* D003 D004* D005 D010 Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2, 5) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions VDD VDR 3.0 - 1.5 5.5 - V V LP, XT, RC osc configuration (DC - 4 MHz) VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - BVDD IDD 3.7 - 4.0 2.0 4.3 3.8 V mA BODEN configuration bit is enabled XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled IBOR - 350 425 A BOR enabled, VDD = 5.0V IPD - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C D010A D015* D020 D021 D021A Brown-out Reset Current (Note 6) Power-down Current (Note 3, 5) V/ms See section on Power-on Reset for details Brown-out Reset Current IBOR 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. D023*  1997-2013 Microchip Technology Inc. DS30234E-page 245 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.3 DC Characteristics: PIC16CR63/R65-04 (Commercial, Industrial) PIC16CR63/R65-10 (Commercial, Industrial) PIC16CR63/R65-20 (Commercial, Industrial) PIC16LCR63/R65-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D030 D030A D031 D032 D033 D040 D040A D041 D042 D042A D043 D070 Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 21.1 and Section 21.2 Sym Min Typ Max Units Conditions † VIL VSS VSS VSS Vss Vss VIH 2.0 0.25VDD + 0.8V D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current IPURB Input Leakage Current (Notes 2, 3) I/O ports IIL D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D083 OSC2/CLKOUT (RC osc config) D090 Output High Voltage I/O ports (Note 3) D092 OSC2/CLKOUT (RC osc config) D150* Open-Drain High Voltage VOL VOH VOD - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V Note1 - VDD VDD V V 4.5V  VDD  5.5V For entire VDD range VDD VDD VDD VDD 400 V V V V A For entire VDD range Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 - - 1 A - - 5 5 A A - - 0.6 V - - 0.6 V VDD-0.7 - - V VDD-0.7 - - V - - 14 V For entire VDD range 4.5V  VDD  5.5V Note1 VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C RA4 pin * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 246  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 21.1 and Section 21.2 Sym Min Typ Max Units Conditions † D100 Capacitive Loading Specs on Output Pins OSC2 pin COSC2 - - 15 pF D101 D102 SCL, SDA in I2C mode All I/O pins and OSC2 (in RC mode) CIO Cb - - 50 400 pF pF In XT, HS and LP modes when external clock is used to drive OSC1. * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 247 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 21-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS Note 1: PORTD and PORTE are not implemented on the PIC16CR63. DS30234E-page 248 CL = 50 pF 15 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports for OSC2 output  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.5 Timing Diagrams and Specifications FIGURE 21-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 21-2: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode XT osc mode Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 TCY 3* TosL, TosH 4* TosR, TosF Typ† Max Units Conditions 0.1 — 4 MHz 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator External Clock in (OSC1) Rise or Fall Time 2.5 — — s LP oscillator 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 249 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 21-1 for load conditions. TABLE 21-3: Param No. CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic Min Typ† Max 10* TosH2ckL 11* 12* TckR 13* Units Conditions OSC1 to CLKOUT — 75 200 ns Note 1 TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 CLKOUT rise time — 35 100 ns Note 1 TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16CR63/R65 100 — — ns PIC16LCR63/R65 200 — — ns 0 — — ns PIC16CR63/R65 — 10 40 ns PIC16LCR63/R65 — — 80 ns PIC16CR63/R65 — 10 40 ns PIC16LCR63/R65 — — 80 ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 20* TioR Port output rise time 21* TioF Port output fall time 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 250  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 21-1 for load conditions. FIGURE 21-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 21-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +125°C Typ† Max Units Conditions Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C TIOZ I/O Hi-impedance from MCLR Low or WDT reset — — 2.1 s TBOR Brown-out Reset Pulse Width 100 — — s 32 Tost 33* Tpwrt 34 35 * † Min VDD  BVDD (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 251 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 21-1 for load conditions. TABLE 21-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.5TCY + 20 — — ns 10 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1P T1CKI input period Synchronous PIC16C6X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC6X 50 OR TCY + 40 N Asynchronous PIC16C6X 60 PIC16LC6X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Tt0L Typ† Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) — — — — — 200 ns ns kHz — 7Tosc — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 252  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 21-1 for load conditions. TABLE 21-6: Param No. 50* 51* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic TccL CCP1 and CCP2 input low time TccH CCP1 and CCP2 input high time Min With Prescaler TccP CCP1 and CCP2 input period 53* TccR CCP1 and CCP2 output rise time * † — — 10 — — ns PIC16LCR63/R65 20 — — ns TccF CCP1 and CCP2 output fall time ns ns 0.5TCY + 20 — — PIC16CR63/R65 10 — — ns PIC16LCR63/R65 20 — — ns 3TCY + 40 N — — ns No Prescaler 52* 54* 0.5TCY + 20 PIC16CR63/R65 No Prescaler With Prescaler Typ† Max Units Conditions PIC16CR63/R65 — 10 25 ns PIC16LCR63/R65 — 25 45 ns PIC16CR63/R65 — 10 25 ns PIC16LCR63/R65 — 25 45 ns N = prescale value (1,4, or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 253 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-8: PARALLEL SLAVE PORT TIMING (PIC16CR65) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 21-1 for load conditions TABLE 21-7: Parameter No. Sym Characteristic Min 62* TdtV2wrH Data in valid before WR or CS (setup time) 63* TwrH2dtI WR or CS to data–in invalid (hold time) 64 TrdL2dtV RD and CS to data–out valid TrdH2dtI RD or CS to data–out invalid 65* * † PARALLEL SLAVE PORT REQUIREMENTS (PIC16CR65) Typ† Max Units 20 — — ns PIC16CR65 20 — — ns PIC16LCR65 35 — — ns — — 80 ns 10 — 30 ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 254  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 SDO 77 75, 76 SDI 74 73 Note: Refer to Figure 21-1 for load conditions TABLE 21-8: Parameter No. 70* * † SPI MODE REQUIREMENTS Sym TssL2scH, TssL2scL Characteristic Min Typ† Max Units SS to SCK or SCK input TCY — — ns 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 — — ns 74* TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 — — ns 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 255 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-10: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 21-1 for load conditions TABLE 21-9: Parameter No. Sym 90* TSU:STA 91* 92* 93 * I2C BUS START/STOP BITS REQUIREMENTS THD:STA TSU:STO THD:STO Characteristic Min Typ Max START condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns These parameters are characterized but not tested. DS30234E-page 256  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-11: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 21-1 for load conditions TABLE 21-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100* THIGH Clock high time 101* 102* 103* TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90* TSU:STA START condition setup time 91* THD:STA START condition hold time 106* THD:DAT Data input hold time 107* TSU:DAT Data input setup time 92* TSU:STO STOP condition setup time 109* TAA 110* TBUF Output valid from clock Bus free time Min Max Units Conditions 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 — — s 400 kHz mode 1.3 — s SSP Module 100 kHz mode 400 kHz mode 1.5TCY — 20 + 0.1Cb — 1000 300 ns ns 100 kHz mode 400 kHz mode — 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 — — 4.7 1.3 — — — — — 0.9 — — — — 3500 — — — s s s s ns s ns ns s s ns ns s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10-400 pF Cb is specified to be from 10-400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 257 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 21-1 for load conditions TABLE 21-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120* Sym Characteristic Min Typ† TckH2dtV Max Units Conditions SYNC XMIT (MASTER & SLAVE) PIC16CR63/R65 Clock high to data out valid PIC16LCR63/R65 — — 80 — — 100 ns — — 45 ns ns 121* Tckrf Clock out rise time and fall time (Master Mode) PIC16CR63/R65 PIC16LCR63/R65 — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16CR63/R65 — — 45 ns PIC16LCR63/R65 — — 50 ns * †: These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 21-13: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 21-1 for load conditions TABLE 21-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. * †: Sym Characteristic Min Typ† Max Units Conditions 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 258  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.0 ELECTRICAL CHARACTERISTICS FOR PIC16C66/67 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)............................................................................................... 0V to +14V Voltage on RA4 with respect to Vss ................................................................................................................ 0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)  20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined) ..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined) .............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16C66. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 22-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C66-04 PIC16C67-04 PIC16C66-10 PIC16C67-10 PIC16C66-20 PIC16C67-20 PIC16LC66-04 PIC16LC67-04 JW Devices RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3V IPD: 5 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V OSC IPD: 1.5 A typ. at 4.5V IPD 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. LP VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Freq: 10 MHz max. Not recommended for use in LP mode VDD: 4.5V to 5.5V Not recommended for use in HS mode Freq: 20 MHz max. Not recommended for use in LP mode IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 259 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C66/67-04 (Commercial, Industrial, Extended) PIC16C66/67-10 (Commercial, Industrial, Extended) PIC16C66/67-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled 3.7 4.0 4.4 V Extended Range Only - 2.7 5 mA XT, RC, osc config FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 mA HS osc config FOSC = 20 MHz, VDD = 5.5V IBOR - 350 425 A BOR enabled, VDD = 5.0V D020 Power-down Current D021 (Note 3, 5) D021A D021B IPD - 10.5 1.5 1.5 2.5 42 16 19 19 A A A A VDD = 4.0V, WDT enabled,-40C to +85C VDD = 4.0V, WDT disabled,-0C to +70C VDD = 4.0V, WDT disabled,-40C to +85C VDD = 4.0V, WDT disabled,-40C to +125C D023* IBOR - 350 425 A BOR enabled, VDD = 5.0V D010 Supply Current (Note 2, 5) IDD D013 D015* Brown-out Reset Current (Note 6) Brown-out Reset Current (Note 6) XT, RC and LP osc configuration HS osc configuration See section on Power-on Reset for details V/ms See section on Power-on Reset for details * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 260  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.2 DC Characteristics: PIC16LC66/67-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. D001 D002* D003 D004* D005 D010 Characteristic Supply Voltage RAM Data Retention Voltage (Note 1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Brown-out Reset Voltage Supply Current (Note 2, 5) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym Min Typ† Max Units Conditions VDD VDR 2.5 - 1.5 6.0 - V V LP, XT, RC osc configuration (DC - 4 MHz) VPOR - VSS - V See section on Power-on Reset for details SVDD 0.05 - - BVDD IDD 3.7 - 4.0 2.0 4.3 3.8 V mA BODEN configuration bit is enabled XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled IBOR - 350 425 A BOR enabled, VDD = 5.0V IPD - 7.5 0.9 0.9 30 5 5 A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, 0C to +70C VDD = 3.0V, WDT disabled, -40C to +85C D010A D015* D020 D021 D021A Brown-out Reset Current (Note 6) Power-down Current (Note 3, 5) V/ms See section on Power-on Reset for details Brown-out Reset Current IBOR 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. D023*  1997-2013 Microchip Technology Inc. DS30234E-page 261 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.3 DC Characteristics: PIC16C66/67-04 (Commercial, Industrial, Extended) PIC16C66/67-10 (Commercial, Industrial, Extended) PIC16C66/67-20 (Commercial, Industrial, Extended) PIC16LC66/67-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Input Low Voltage I/O ports with TTL buffer D030 D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT, HS and LP) Input High Voltage I/O ports D040 with TTL buffer D040A D041 D042 D042A D043 D070 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 22.1 and Section 22.2 Sym Min Typ Max Units Conditions † VIL VSS VSS VSS Vss Vss VIH 2.0 0.25VDD + 0.8V D060 with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current IPURB Input Leakage Current (Notes 2, 3) I/O ports IIL D061 D063 MCLR, RA4/T0CKI OSC1 D080 Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC osc config) D083A VOL - 0.15VDD 0.8V 0.2VDD 0.2VDD 0.3VDD V V V V V Note1 - VDD VDD V V 4.5V  VDD  5.5V For entire VDD range VDD VDD VDD VDD 400 V V V V A For entire VDD range 0.8VDD 0.8VDD 0.7VDD 0.9VDD 50 250 - - 1 A - - 5 5 A A - - 0.6 V - - 0.6 V - - 0.6 V - - 0.6 V For entire VDD range 4.5V  VDD  5.5V Note1 VDD = 5V, VPIN = VSS Vss VPIN VDD, Pin at hiimpedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 262  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports (Note 3) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 22.1 and Section 22.2 Sym Min Typ Max Units Conditions † VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V VDD-0.7 - - V - - 14 V D100 Open-Drain High Voltage VOD Capacitive Loading Specs on Output Pins OSC2 pin COSC2 - - 15 pF D101 D102 SCL, SDA in I2C mode All I/O pins and OSC2 (in RC mode) CIO Cb - - 50 400 pF pF D090 VOH D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1. * † These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 263 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA BUF output access Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO STOP condition FIGURE 22-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS Note 1: PORTD and PORTE are not implemented on the PIC16C66. DS30234E-page 264 CL = 50 pF 15 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports for OSC2 output  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.5 Timing Diagrams and Specifications FIGURE 22-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 22-2: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode XT osc mode Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 TCY 3* TosL, TosH 4* TosR, TosF Typ† Max Units Conditions 0.1 — 4 MHz 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator External Clock in (OSC1) Rise or Fall Time 2.5 — — s LP oscillator 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 265 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 22-1 for load conditions. TABLE 22-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No. Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16C66/67 100 — — ns PIC16LC66/67 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time ns PIC16C66/67 — 10 40 PIC16LC66/67 — — 80 ns PIC16C66/67 — 10 40 ns 21* TioF Port output fall time — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns PIC16LC66/67 Note 1 * † These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 266  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 22-1 for load conditions. FIGURE 22-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 22-4: 35 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No. Sym Characteristic 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +125°C Typ† Max Units Conditions Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C TIOZ I/O Hi-impedance from MCLR Low or WDT reset — — 2.1 s TBOR Brown-out Reset Pulse Width 100 — — s 32 Tost 33* Tpwrt 34 35 * † Min VDD  BVDD (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 267 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 22-1 for load conditions. TABLE 22-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* 42* 45* 46* 47* 48 * † Min No Prescaler With Prescaler No Prescaler With Prescaler T0CKI Low Pulse Width Max Units Conditions 0.5TCY + 20 — — ns 10 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns 0.5TCY + 20 10 TCY + 40 Tt0P T0CKI Period No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C6X 15 Prescaler = PIC16LC6X 25 2,4,8 Asynchronous PIC16C6X 30 PIC16LC6X 50 Tt1P T1CKI input period Synchronous PIC16C6X Greater of: 30 OR TCY + 40 N Greater of: PIC16LC6X 50 OR TCY + 40 N Asynchronous PIC16C6X 60 PIC16LC6X 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Tt0L Typ† Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) — — — — — 200 ns ns kHz — 7Tosc — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 268  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 54 53 Note: Refer to Figure 22-1 for load conditions. TABLE 22-6: Parameter No. 50* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym Characteristic Min TccL CCP1 and CCP2 input low time No Prescaler TccH CCP1 and CCP2 input high time No Prescaler With Prescaler PIC16C66/67 PIC16LC66/67 51* With Prescaler PIC16C66/67 PIC16LC66/67 52* TccP CCP1 and CCP2 input period 53* TccR CCP1 and CCP2 output rise time 54* * † TccF CCP1 and CCP2 output fall time Typ† Max Units Conditions 0.5TCY + 20 — — ns 10 — — ns ns 20 — — 0.5TCY + 20 — — ns 10 — — ns 20 — — ns 3TCY + 40 N — — ns PIC16C66/67 — 10 25 ns PIC16LC66/67 — 25 45 ns PIC16C66/67 — 10 25 ns PIC16LC66/67 — 25 45 ns N = prescale value (1,4, or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 269 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-8: PARALLEL SLAVE PORT TIMING (PIC16C67) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 22-1 for load conditions TABLE 22-7: Parameter No. 62* 63* 64 65* * † PARALLEL SLAVE PORT REQUIREMENTS (PIC16C67) Sym Characteristic Min TdtV2wrH Data in valid before WR or CS (setup time) TwrH2dtI TrdL2dtV TrdH2dtI WR or CS to data–in invalid (hold time) RD and CS to data–out valid RD or CS to data–out invalid Typ† Max Units 20 — — ns 25 — — ns PIC16C67 20 — — ns PIC16LC67 35 — — ns — — 80 ns — — 90 ns 10 — 30 ns Conditions Extended Range Only Extended Range Only These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 270  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-9: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSB SDO LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 22-1 for load conditions. FIGURE 22-10: SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO BIT6 - - - - - -1 MSB LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure 22-1 for load conditions.  1997-2013 Microchip Technology Inc. DS30234E-page 271 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-11: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSB SDO LSB BIT6 - - - - - -1 77 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 22-1 for load conditions. FIGURE 22-12: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN 77 BIT6 - - - -1 LSB IN 74 Refer to Figure 22-1 for load conditions. DS30234E-page 272  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 TABLE 22-8: Parameter No. 70* * † SPI MODE REQUIREMENTS Sym TssL2scH, TssL2scL Characteristic Min Typ† Max Units SS to SCK or SCK input TCY — — ns 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns 74* TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — — ns 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns 81* TdoV2scH, TdoV2scL SDO data output setup to SCK edge TCY — — ns 82* TssL2doV SDO data output valid after SS edge — — 50 ns 83* TscH2ssH, TscL2ssH SS after SCK edge 1.5TCY + 40 — — ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 273 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-13: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 22-1 for load conditions TABLE 22-9: Parameter No. Sym 90* TSU:STA 91* 92* 93 * I2C BUS START/STOP BITS REQUIREMENTS THD:STA TSU:STO THD:STO Characteristic Min Typ Max START condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns These parameters are characterized but not tested. DS30234E-page 274  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-14: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 22-1 for load conditions TABLE 22-10: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100* THIGH Clock high time 101* 102* 103* TLOW TR TF Clock low time SDA and SCL rise time SDA and SCL fall time 90* TSU:STA START condition setup time 91* THD:STA START condition hold time 106* THD:DAT Data input hold time 107* TSU:DAT Data input setup time 92* TSU:STO STOP condition setup time 109* TAA 110* TBUF Output valid from clock Bus free time Min Max Units Conditions 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz SSP Module 100 kHz mode 1.5TCY 4.7 — — s 400 kHz mode 1.3 — s SSP Module 100 kHz mode 400 kHz mode 1.5TCY — 20 + 0.1Cb — 1000 300 ns ns 100 kHz mode 400 kHz mode — 20 + 0.1Cb 300 300 ns ns 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 — — 4.7 1.3 — — — — — 0.9 — — — — 3500 — — — s s s s ns s ns ns s s ns ns s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Cb is specified to be from 10-400 pF Cb is specified to be from 10-400 pF Only relevant for repeated START condition After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 275 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 22-1 for load conditions TABLE 22-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter No. 120* Sym Characteristic Min Typ† TckH2dtV Max Units Conditions SYNC XMIT (MASTER & SLAVE) PIC16C66/67 Clock high to data out valid PIC16LC66/67 — — 80 — — 100 ns — — 45 ns ns 121* Tckrf Clock out rise time and fall time (Master Mode) PIC16C66/67 PIC16LC66/67 — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16C66/67 — — 45 ns PIC16LC66/67 — — 50 ns * †: These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 22-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 22-1 for load conditions TABLE 22-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter No. * †: Sym Characteristic Min Typ† Max Units Conditions 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 276  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR: PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64, PIC16C65A, PIC16C66, PIC16C67 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25C, while 'max' or 'min' represents (mean +3) and (mean -3) respectively where  is standard deviation. FIGURE 23-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE) 35 30 IPD(nA) 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 FIGURE 23-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE) 10.000 85C 70C IPD(A) 1.000 25C 0.100 0C -40C 0.010 0.001 2.5 3.0  1997-2013 Microchip Technology Inc. 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 DS30234E-page 277 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-3: TYPICAL IPD vs. VDD @ 25C (WDT ENABLED, RC MODE) FIGURE 23-5: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 22 pF, T = 25C 6.0 25 5.5 5.0 4.5 Fosc(MHz) IPD(A) 20 15 10 R = 5k 4.0 3.5 3.0 R = 10k 2.5 2.0 5 1.5 1.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 2.5 VDD(Volts) FIGURE 23-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE) 35 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 0C Cext = 100 pF, T = 25C 2.4 2.2 R = 3.3k 2.0 20 1.8 70C Fosc(MHz) IPD(A) 6.0 Shaded area is beyond recommended range. 25 15 85C 10 5 1.6 R = 5k 1.4 1.2 1.0 R = 10k 0.8 0.6 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.4 6.0 R = 100k 0.2 VDD(Volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 23-7: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 300 pF, T = 25C 1000 900 800 Fosc(kHz) Data based on matrix samples. See first page of this section for details. 5.5 FIGURE 23-6: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD -40C 30 R = 100k 0.5 6.0 R = 3.3k 700 600 R = 5k 500 400 R = 10k 300 200 R = 100k 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) DS30234E-page 278  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC MODE) FIGURE 23-10: TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) 1400 1200 30 25 Device NOT in Brown-out Reset 800 20 600 400 200 0 2.5 IPD(A) IPD(A) 1000 Device in Brown-out Reset 15 10 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 5 6.0 0 2.5 The shaded region represents the built-in hysteresis of the brown-out reset circuitry. FIGURE 23-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT ENABLED (85C TO -40C, RC MODE) 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 FIGURE 23-11: MAXIMUM IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C TO -40C, RC MODE) 1600 1400 1200 45 40 Device NOT in Brown-out Reset 800 35 30 400 Device in Brown-out Reset 20 15 200 4.3 0 2.5 25 3.0 3.5 4.0 4.5 VDD(Volts) 10 5.0 5.5 6.0 The shaded region represents the built-in hysteresis of the brown-out reset circuitry.  1997-2013 Microchip Technology Inc. 5 0 2.5 3.0 3.5 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 DS30234E-page 279 Data based on matrix samples. See first page of this section for details. 600 IPD(A) IPD(A) 1000 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V 1400 IDD(A) 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Frequency(MHz) 3.5 4.0 4.5 Shaded area is beyond recommended range FIGURE 23-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40C TO 85C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V 1400 IDD(A) Data based on matrix samples. See first page of this section for details. 4.0V 1200 3.5V 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 Frequency(MHz) DS30234E-page 280 3.0 3.5 4.0 4.5 Shaded area is beyond recommended range  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(A) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range 600 800 1000 1200 1400 1600 1800 Frequency(kHz) FIGURE 23-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO 85C) 1600 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 IDD(A) 3.5V 3.0V 800 2.5V 600 400 200 0 0 200 400 Shaded area is beyond recommended range  1997-2013 Microchip Technology Inc. 600 800 1000 1200 1400 1600 1800 Frequency(kHz) DS30234E-page 281 Data based on matrix samples. See first page of this section for details. 6.0V PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V IDD(A) 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 23-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO 85C) 1200 6.0V 5.5V 5.0V 4.5V 4.0V 800 3.5V IDD(A) Data based on matrix samples. See first page of this section for details. 1000 3.0V 600 2.5V 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) DS30234E-page 282  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-18: TYPICAL IDD vs. CAPACITANCE @ 500 kHz (RC MODE) FIGURE 23-19: TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD 600 4.0 500 3.5 3.0 gm(mA/V) 4.0V 400 IDD(A) Max -40C 5.0V 3.0V 300 200 2.5 Typ 25C 2.0 Min 85C 1.5 1.0 100 0.5 100 pF TABLE 23-1: 0.0 3.0 300 pF RC OSCILLATOR FREQUENCIES 300 pF 5k 4.12 MHz ± 1.4% 10k 2.35 MHz ± 1.4% 100k 268 kHz ± 1.1% 5.5 6.0 6.5 7.0 80 70 60 1.80 MHz ± 1.0% 1.27 MHz ± 1.0% 30 10k 688 kHz ± 1.2% 20 100k 77.2 kHz ± 1.0% 10 3.3k 707 kHz ± 1.4% ± 1.2% 10k 269 kHz ± 1.6% 100k 28.3 kHz ± 1.1% The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is ±3 standard deviation from average value for VDD = 5V. Typ 25C 50 5k 501 kHz Max -40C 90 3.3k 5k 5.0 100 gm(A/V) 100 pF 4.5 110 Rext Fosc @ 5V, 25C 22 pF 4.0 FIGURE 23-20: TRANSCONDUCTANCE(gm) OF LP OSCILLATOR vs. VDD Average Cext 3.5 VDD(Volts) Shaded area is beyond recommended range Capacitance(pF) 40 0 2.0 Min 85C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD(Volts) Shaded areas are beyond recommended range FIGURE 23-21: TRANSCONDUCTANCE(gm) OF XT OSCILLATOR vs. VDD 1000 900 Max -40C 800 gm(A/V) 700 600 Typ 25C 500 400 300 Min 85C 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD(Volts) Shaded areas are beyond recommended range  1997-2013 Microchip Technology Inc. DS30234E-page 283 Data based on matrix samples. See first page of this section for details. 0 20 pF PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-22: TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C) FIGURE 23-24: TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25C) 3.5 70 3.0 60 50 Startup Time(ms) Startup Time(Seconds) 2.5 2.0 32 kHz, 33 pF/33 pF 1.5 1.0 40 200 kHz, 68 pF/68 pF 30 200 kHz, 47 pF/47 pF 20 1 MHz, 15 pF/15 pF 10 0.5 4 MHz, 15 pF/15 pF 200 kHz, 15 pF/15 pF 0.0 2.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 6.0 4.0 4.5 VDD(Volts) 5.0 5.5 6.0 VDD(Volts) FIGURE 23-23: TYPICAL XTAL STARTUP TIME vs. VDD (HS MODE, 25C) TABLE 23-2: Osc Type 7 LP Startup Time(ms) Data based on matrix samples. See first page of this section for details. 6 20 MHz, 33 pF/33 pF 5 XT 4 8 MHz, 33 pF/33 pF HS 3 20 MHz, 15 pF/15 pF 8 MHz, 15 pF/15 pF 2 1 4.0 4.5 DS30234E-page 284 5.0 VDD(Volts) 5.5 6.0 CAPACITOR SELECTION FOR CRYSTAL OSCILLATORS Crystal Freq Cap. Range C1 Cap. Range C2 33 pF 32 kHz 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF Crystals Used 32 kHz Epson C-001R32.768K-A ± 20 PPM 200 kHz STD XTL 200.000KHz ± 20 PPM 1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM 20 MHz EPSON CA-301 20.000M-C ± 30 PPM  1997-2013 Microchip Technology Inc. PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-25: TYPICAL IDD vs. FREQUENCY (LP MODE, 25°C) FIGURE 23-27: TYPICAL IDD vs. FREQUENCY (XT MODE, 25°C) 1800 1600 6.0V 1400 5.5V 120 100 5.0V 1200 4.5V 1000 4.0V 60 40 20 0 0 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V IDD(A) IDD(A) 80 3.5V 800 3.0V 600 2.5V 400 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 23-26: MAXIMUM IDD vs. FREQUENCY (LP MODE, 85°C TO -40°C) FIGURE 23-28: MAXIMUM IDD vs. FREQUENCY (XT MODE, -40°C TO 85°C) 1800 6.0V 1600 120 1400 100 1200 80 1000 4.0V 800 3.5V 40 20 0 0 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 5.5V 5.0V 4.5V 3.0V 600 2.5V 400 200 50 100 Frequency(kHz) 150 200 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz)  1997-2013 Microchip Technology Inc. DS30234E-page 285 Data based on matrix samples. See first page of this section for details. 60 IDD(A) IDD(A) 140 PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-29: TYPICAL IDD vs. FREQUENCY (HS MODE, 25°C) 7.0 FIGURE 23-30: MAXIMUM IDD vs. FREQUENCY (HS MODE, -40°C TO 85°C) 7.0 6.0 6.0 5.0 IDD(mA) IDD(mA) 5.0 4.0 3.0 2.0 1.0 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4.0 3.0 2.0 1.0 4 6 8 10 12 Frequency(MHz) 14 16 18 20 0.0 1 2 6.0V 5.5V 5.0V 4.5V 4.0V 4 6 8 10 12 14 16 18 20 Data based on matrix samples. See first page of this section for details. Frequency(MHz) DS30234E-page 286  1997-2013 Microchip Technology Inc. PIC16C6X 24.0 PACKAGING INFORMATION 24.1 18-Lead Plastic Dual In-line (300 mil) (P) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  E1 C E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 e1 B A1 A2 A D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max  0 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.048 0.355 1.524 0.203 22.479 20.320 7.620 6.096 2.489 7.620 7.874 3.048 18 0.889 0.127  1997-2013 Microchip Technology Inc. Inches Notes Min Max 10 0 10 4.064 – 3.810 0.559 1.524 0.381 23.495 20.320 8.255 7.112 2.591 7.620 9.906 3.556 18 – – – 0.015 0.120 0.014 0.060 0.008 0.885 0.800 0.300 0.240 0.098 0.300 0.310 0.120 18 0.035 0.005 0.160 – 0.150 0.022 0.060 0.015 0.925 0.800 0.325 0.280 0.102 0.300 0.390 0.140 18 – – Reference Typical Reference Typical Reference Notes Reference Typical Reference Typical Reference DS30234E-page 287 PIC16C6X 24.2 28-Lead Plastic Dual In-line (300 mil) (SP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1  E C eA eB Pin No. 1 Indicator Area B2 D B1 S Base Plane Seating Plane L Detail A B3 A1 A2 A e1 B Detail A D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max Inches Notes Min Max  0 10 0 10 A A1 A2 B B1 B2 B3 C D D1 E E1 e1 eA eB L N S 3.632 0.381 3.175 0.406 1.016 0.762 0.203 0.203 34.163 33.020 7.874 7.112 2.540 7.874 8.128 3.175 28 0.584 4.572 – 3.556 0.559 1.651 1.016 0.508 0.331 35.179 33.020 8.382 7.493 2.540 7.874 9.652 3.683 28 1.220 0.143 0.015 0.125 0.016 0.040 0.030 0.008 0.008 1.385 1.300 0.310 0.280 0.100 0.310 0.320 0.125 28 0.023 0.180 – 0.140 0.022 0.065 0.040 0.020 0.013 1.395 1.300 0.330 0.295 0.100 0.310 0.380 0.145 28 0.048 DS30234E-page 288 Typical 4 places 4 places Typical Reference Typical Reference Notes Typical 4 places 4 places Typical Reference Typical Reference  1997-2013 Microchip Technology Inc. PIC16C6X 24.3 40-Lead Plastic Dual In-line (600 mil) (P) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1  E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Min Max  0 10 0 10 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.175 0.355 1.270 0.203 51.181 48.260 15.240 13.462 2.489 15.240 15.240 2.921 40 1.270 0.508 5.080 – 4.064 0.559 1.778 0.381 52.197 48.260 15.875 13.970 2.591 15.240 17.272 3.683 40 – – – 0.015 0.125 0.014 0.050 0.008 2.015 1.900 0.600 0.530 0.098 0.600 0.600 0.115 40 0.050 0.020 0.200 – 0.160 0.022 0.070 0.015 2.055 1.900 0.625 0.550 0.102 0.600 0.680 0.145 40 – –  1997-2013 Microchip Technology Inc. Notes Typical Typical Reference Typical Reference Notes Typical Typical Reference Typical Reference DS30234E-page 289 PIC16C6X 24.4 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e B h x 45 N Index Area E H  C Chamfer h x 45 L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Symbol Min Max Inches Notes Min Max  0 8 0 8 A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 11.353 7.416 1.270 10.007 0.381 0.406 18 – 2.642 0.300 0.483 0.318 11.735 7.595 1.270 10.643 0.762 1.143 18 0.102 0.093 0.004 0.014 0.009 0.447 0.292 0.050 0.394 0.015 0.016 18 – 0.104 0.012 0.019 0.013 0.462 0.299 0.050 0.419 0.030 0.045 18 0.004 DS30234E-page 290 Reference Notes Reference  1997-2013 Microchip Technology Inc. PIC16C6X 24.5 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e B h x 45 N Index Area E H  C Chamfer h x 45 L 1 2 3 D Seating Plane Base Plane CP A1 A Package Group: Plastic SOIC (SO) Millimeters Inches Symbol Min Max Min Max  0 8 0 8 A A1 B C D E e H h L N CP 2.362 0.101 0.355 0.241 17.703 7.416 1.270 10.007 0.381 0.406 28 – 2.642 0.300 0.483 0.318 18.085 7.595 1.270 10.643 0.762 1.143 28 0.102 0.093 0.004 0.014 0.009 0.697 0.292 0.050 0.394 0.015 0.016 28 – 0.104 0.012 0.019 0.013 0.712 0.299 0.050 0.419 0.030 0.045 28 0.004  1997-2013 Microchip Technology Inc. Notes Typical Notes Typical DS30234E-page 291 PIC16C6X 24.6 18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  E1 C E eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A3 A e1 B A2 D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Min Max  0 10 0 10 A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 — 0.381 3.810 3.810 0.355 1.270 0.203 22.352 20.320 7.620 5.588 2.540 7.366 7.620 3.175 18 0.508 0.381 5.080 1.778 4.699 4.445 0.585 1.651 0.381 23.622 20.320 8.382 7.874 2.540 8.128 10.160 3.810 18 1.397 1.270 — 0.015 0.150 0.150 0.014 0.050 0.008 0.880 0.800 0.300 0.220 0.100 0.290 0.300 0.125 18 0.020 0.015 0.200 0.070 0.185 0.175 0.023 0.065 0.015 0.930 0.800 0.330 0.310 0.100 0.320 0.400 0.150 18 0.055 0.050 DS30234E-page 292 Notes Typical Typical Reference Reference Typical Notes Typical Typical Reference Reference Typical  1997-2013 Microchip Technology Inc. PIC16C6X 24.7 28-Lead Ceramic CERDIP Dual In-line with Window (300 mil)) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 E  C Pin No. 1 Indicator Area eA eB D D1 Base Plane Seating Plane L B1 A1 A2 A e1 B D2 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Min Max  0 10 0 10 A A1 A2 B B1 C D D2 E E1 e eA eB L N D1 3.30 0.38 2.92 0.35 1.14 0.20 34.54 32.97 7.62 6.10 2.54 7.62 — 2.92 28 0.13 5.84 — 4.95 0.58 1.78 0.38 37.72 33.07 8.25 7.87 2.54 7.62 11.43 5.08 28 — .130 0.015 0.115 0.014 0.045 0.008 1.360 1.298 0.300 0.240 0.100 0.300 — 0.115 28 0.005 0.230 — 0.195 0.023 0.070 0.015 1.485 1.302 0.325 0.310 0.100 0.300 0.450 0.200 28 —  1997-2013 Microchip Technology Inc. Notes Typical Typical Reference Typical Reference Notes Typical Typical Reference Typical Reference DS30234E-page 293 PIC16C6X 24.8 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 E  C Pin No. 1 Indicator Area eA eB D S S1 Base Plane Seating Plane L B1 A1 A3 A A2 e1 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol Min Max  0 A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 4.318 0.381 3.810 3.810 0.355 1.270 0.203 51.435 48.260 15.240 12.954 2.540 14.986 15.240 3.175 40 1.016 0.381 DS30234E-page 294 Inches Notes Min Max 10 0 10 5.715 1.778 4.699 4.445 0.585 1.651 0.381 52.705 48.260 15.875 15.240 2.540 16.002 18.034 3.810 40 2.286 1.778 0.170 0.015 0.150 0.150 0.014 0.050 0.008 2.025 1.900 0.600 0.510 0.100 0.590 0.600 0.125 40 0.040 0.015 0.225 0.070 0.185 0.175 0.023 0.065 0.015 2.075 1.900 0.625 0.600 0.100 0.630 0.710 0.150 40 0.090 0.070 Typical Typical Reference Reference Typical Notes Typical Typical Reference Reference Typical  1997-2013 Microchip Technology Inc. PIC16C6X 24.9 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N C E1 E eA eB  Pin #1 Indicator Area D S1 S Base Plane Seating Plane L B1 A3 A2 A A1 e1 B D1 Package Group: Ceramic Side Brazed Dual In-Line (CER) Millimeters Inches Symbol  A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 Min Max 0 3.937 1.016 2.921 1.930 0.406 1.219 0.228 35.204 32.893 7.620 7.366 2.413 7.366 7.594 3.302 28 1.143 0.533 10 5.030 1.524 3.506 2.388 0.508 1.321 0.305 35.916 33.147 8.128 7.620 2.667 7.874 8.179 4.064 28 1.397 0.737  1997-2013 Microchip Technology Inc. Notes Typical Typical Reference Typical Reference Min Max 0 0.155 0.040 0.115 0.076 0.016 0.048 0.009 1.386 1.295 0.300 0.290 0.095 0.290 0.299 0.130 28 0.045 0.021 10 0.198 0.060 0.138 0.094 0.020 0.052 0.012 1.414 1.305 0.320 0.300 0.105 0.310 0.322 0.160 28 0.055 0.029 Notes DS30234E-page 295 PIC16C6X 24.10 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N Index area E H  C L 1 2 3 B e A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Inches Symbol Min Max Min Max  0 8 0 8 A A1 B C D E e H L N CP 1.730 0.050 0.250 0.130 10.070 5.200 0.650 7.650 0.550 28 - 1.990 0.210 0.380 0.220 10.330 5.380 0.650 7.900 0.950 28 0.102 0.068 0.002 0.010 0.005 0.396 0.205 0.026 0.301 0.022 28 - 0.078 0.008 0.015 0.009 0.407 0.212 0.026 0.311 0.037 28 0.004 DS30234E-page 296 Notes Reference Notes Reference  1997-2013 Microchip Technology Inc. PIC16C6X 24.11 44-Lead Plastic Leaded Chip Carrier (Square) (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D -A- D1 -D- 3 -F- 0.812/0.661 N Pics .032/.026 1.27 .050 2 Sides 0.177 .007 S B D-E S -HA A1 3 D3/E3 D2 0.38 .015 3 -G- 8 F-G S 0.177 .007 S B A S 2 Sides 9 0.101 Seating .004 Plane D -C- 4 E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.254 .010 Max 2 0.254 .010 Max 11 0.508 .020 0.508 .020 -H- 11 -H- 2 0.812/0.661 3 .032/.026 1.524 .060 Min 6 6 -C1.651 .065 1.651 .065 R 1.14/0.64 .045/.025 R 1.14/0.64 .045/.025 5 0.533/0.331 .021/.013 0.64 Min .025 0.177 F-G S , D-E S .007 M A Package Group: Plastic Leaded Chip Carrier (PLCC) Millimeters Symbol Min Max Inches Notes Min Max A 4.191 4.572 0.165 0.180 A1 D D1 D2 D3 E E1 E2 E3 N CP LT 2.413 17.399 16.510 15.494 12.700 17.399 16.510 15.494 12.700 44 – 0.203 2.921 17.653 16.663 16.002 12.700 17.653 16.663 16.002 12.700 44 0.102 0.381 0.095 0.685 0.650 0.610 0.500 0.685 0.650 0.610 0.500 44 – 0.008 0.115 0.695 0.656 0.630 0.500 0.695 0.656 0.630 0.500 44 0.004 0.015  1997-2013 Microchip Technology Inc. Reference Reference Notes Reference Reference DS30234E-page 297 PIC16C6X 24.12 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 4 D D1 5 0.20 M C A-B S D S 0.20 M H A-B S D S 7 0.20 min. 0.05 mm/mm A-B D3 0.13 R min. Index area 6 9 PARTING LINE b 0.13/0.30 R  L C E3 E1 E 1.60 Ref. 0.20 M C A-B S D S 4 TYP 4x 10 e 0.20 M H A-B S B D S 5 7 0.05 mm/mm D A2 A Base Plane Seating Plane A1 Package Group: Plastic MQFP Millimeters Symbol Min Max  0 A A1 A2 b C D D1 D3 E E1 E3 e L N CP 2.000 0.050 1.950 0.300 0.150 12.950 9.900 8.000 12.950 9.900 8.000 0.800 0.730 44 0.102 DS30234E-page 298 Inches Notes Min Max 7 0 7 2.350 0.250 2.100 0.450 0.180 13.450 10.100 8.000 13.450 10.100 8.000 0.800 1.030 44 – 0.078 0.002 0.768 0.011 0.006 0.510 0.390 0.315 0.510 0.390 0.315 0.031 0.028 44 0.004 0.093 0.010 0.083 0.018 0.007 0.530 0.398 0.315 0.530 0.398 0.315 0.032 0.041 44 – Typical Reference Reference Notes Typical Reference Reference  1997-2013 Microchip Technology Inc. PIC16C6X 24.13 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 1.0ø (0.039ø) Ref. Pin#1 2 11/13(4x) Pin#1 2 E 0 Min E1  11/13(4x) Detail B e 3.0ø (0.118ø) Ref. Option 1 (TOP side) A1 A2 Detail B Detail A R1 0.08 Min R 0.08/0.20 Option 2 (TOP side) A L Base Metal b Lead Finish L c 1.00 Ref. Gage Plane 0.250 c1 L1 1.00 Ref b1 Detail A S 0.20 Min Detail B Package Group: Plastic TQFP Millimeters Inches Symbol Min Max Min Max A A1 A2 D D1 E E1 L e b b1 c c1 N 1.00 0.05 0.95 11.75 9.90 11.75 9.90 0.45 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.75 Notes 0.039 0.002 0.037 0.463 0.390 0.463 0.390 0.018 0.047 0.006 0.041 0.482 0.398 0.482 0.398 0.030 0.45 0.40 0.20 0.16 44 0.012 0.012 0.004 0.004 44 0.80 BSC 0.30 0.30 0.09 0.09 44 Notes 0.031 BSC 0.018 0.016 0.008 0.006 44  0 7 0 7 Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per side. D1 and E1 dimensions including mold mismatch. 2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m (0.003”)max. 3: This outline conforms to JEDEC MS-026.  1997-2013 Microchip Technology Inc. DS30234E-page 299 PIC16C6X 24.14 Package Marking Information 18-Lead PDIP Example MMMMMMMMMMMMM XXXXXXXXXXXXXXXX PIC16C61-04/P AABBCDE 9450CBA 18-Lead SOIC Example MMMMMMMMMM XXXXXXXXXXXX XXXXXXXXXXXX PIC16C61 -20/SO AABBCDE 9449CBA 18-Lead CERDIP Windowed Example MMMMMM XXXXXXXX PIC16C61 /JW 9440CBT AABBCDE 28-Lead PDIP (.300 MIL) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX PIC16C63-04I/SP AABBCAE Legend: MM...M XX...X AA BB C D1 D2 E Note: 9452CAN Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01’) Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. Mask revision number for microcontroller Mask revision number for EEPROM Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30234E-page 300  1997-2013 Microchip Technology Inc. PIC16C6X Package Marking Information (Cont’d) 28-Lead SOIC Example MMMMMMMMMMMMMMMMMMXX XXXXXXXXXXXXXXXXXXXX PIC16C62-20/S0111 AABBCAE 9515SBA 28-Lead CERDIP Skinny Windowed Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC16C62/JW AABBCDE 9517SBT 28-Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX XXXXXXXXXXX PIC16C66/JW AABBCDE 28-Lead SSOP 9517CAT Example XXXXXXXXXXXX XXXXXXXXXXXX PIC16C62 20I/SS025 AABBCAE 9517SBP Example 40-Lead PDIP MMMMMMMMMMMMMM XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX AABBCDE Legend: Note: PIC16C65-04/P 9510CAA MM...M XX...X AA BB C Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01’) Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 E Mask revision number for microcontroller Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  1997-2013 Microchip Technology Inc. DS30234E-page 301 PIC16C6X Package Marking Information (Cont’d) 40-Lead CERDIP Windowed Example PIC16C67/JW MMMMMMMMM XXXXXXXXXXX XXXXXXXXXXX 9450CAT AABBCDE 44-Lead PLCC Example MMMMMMMM XXXXXXXXXX PIC16C64 -20/L XXXXXXXXXX AABBCDE 9442CAN Example 44-Lead MQFP MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE PIC16C64 -04/PQ 9444CAP 44-Lead TQFP Example MMMMMMMM XXXXXXXXXX XXXXXXXXXX AABBCDE Legend: Note: PIC16C64A -10/TQ AABBCDE MM...M XX...X AA BB C Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01’) Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 E Mask revision number for microcontroller Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30234E-page 302  1997-2013 Microchip Technology Inc. PIC16C6X APPENDIX A: MODIFICATIONS APPENDIX B: COMPATIBILITY The following are the list of modifications over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. PA2, PA1, PA0 bits are removed from STATUS register. Data memory paging is redefined slightly. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake-up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT), are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. Timer0 pin is also a port pin (RA4/T0CKI) now. FSR is made a full 8-bit register. “In-circuit programming” is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out). Power Control register (PCON) is added with a Power-on Reset status bit (POR).(Not on the PIC16C61). Brown-out Reset has been added to the following devices: PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/ 67.  1997-2013 Microchip Technology Inc. 2. 3. 4. 5. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h. DS30234E-page 303 PIC16C6X APPENDIX C: WHAT’S NEW APPENDIX D: WHAT’S CHANGED Added PIC16CR63 and PIC16CR65 devices. Minor changes, spelling and grammatical changes. Added PIC16C66 and PIC16C67 devices. The PIC16C66/67 devices have 368 bytes of data memory distributed in 4 banks and 8K of program memory in 4 pages. These two devices have an enhanced SPI that supports both clock phase and polarity. The USART has been enhanced. Divided SPI section into SPI for the PIC16C66/67 (Section 11.3) and SPI for all other devices (Section 11.2). When upgrading to the PIC16C66/67 please note that the upper 16 bytes of data memory in banks 1,2, and 3 are mapped into bank 0. This may require relocation of data memory usage in the user application code. Q-cycles for instruction execution were added to Section 14.0 Instruction Set Summary. Added the following note for the USART. This applies to all devices except the PIC16C66 and PIC16C67. For the PIC16C63/R63/65/65A/R65 the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information or use the PIC16C66/67. APPENDIX E: REVISION E January 2013 - Added a note to each package drawing. DS30234E-page 304  1997-2013 Microchip Technology Inc. PIC16C6X APPENDIX F: PIC16/17 MICROCONTROLLERS F.1 PIC12CXXX Family of Devices PIC12C508 Clock Memory Peripherals Features PIC12C509 PIC12C671 PIC12C672 Maximum Frequency of Operation (MHz) 4 4 4 4 EPROM Program Memory 512 x 12 1024 x 12 1024 x 14 2048 x 14 Data Memory (bytes) 25 41 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 A/D Converter (8-bit) Channels — — 4 4 Wake-up from SLEEP on pin change Yes Yes Yes Yes I/O Pins 5 5 5 5 Input Pins 1 1 1 1 Internal Pull-ups Yes Yes Yes Yes Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Number of Instructions 33 33 35 35 Packages 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GP0. F.2 PIC14C000 Family of Devices PIC14C000 Clock Memory Peripherals Features Maximum Frequency of Operation (MHz) 20 EPROM Program Memory (x14 words) 4K Data Memory (bytes) 192 Timer Module(s) TMR0 ADTMR Serial Port(s) (SPI/I2C, USART) I2C with SMBus Support Slope A/D Converter Channels 8 External; 6 Internal Interrupt Sources 11 I/O Pins 22 Voltage Range (Volts) 2.7-6.0 In-Circuit Serial Programming Yes Additional On-chip Features Internal 4MHz Oscillator, Bandgap Reference,Temperature Sensor, Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE, Comparators with Programmable References (2) Packages 28-pin DIP (.300 mil), SOIC, SSOP  1997-2013 Microchip Technology Inc. DS30234E-page 305 PIC16C6X F.3 PIC16C15X Family of Devices PIC16C154 Clock Memory PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 20 20 20 20 20 20 EPROM Program Memory (x12 words) 512 — 1K — 2K — ROM Program Memory (x12 words) — 512 — 1K — 2K RAM Data Memory (bytes) 25 25 25 25 73 73 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 12 12 Voltage Range (Volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 Number of Instructions 33 33 33 33 33 33 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP Peripherals Timer Module(s) Features PIC16CR154 Maximum Frequency of Operation (MHz) All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. F.4 PIC16C5X Family of Devices PIC16C52 Clock Memory PIC16C54A 20 20 20 EPROM Program Memory (x12 words) 384 512 512 — 512 1K ROM Program Memory (x12 words) — — — 512 — — RAM Data Memory (bytes) 25 25 25 25 24 25 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 12 12 12 12 20 12 2.5-6.25 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 Number of Instructions 33 33 33 33 33 33 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 20-pin SSOP PIC16CR57B PIC16C58A PIC16CR58A Maximum Frequency of Operation (MHz) 20 20 20 20 EPROM Program Memory (x12 words) 2K — 2K — ROM Program Memory (x12 words) — 2K — 2K RAM Data Memory (bytes) 72 72 73 73 TMR0 TMR0 TMR0 TMR0 12 Peripherals Timer Module(s) Features PIC16C56 20 PIC16C57 Memory PIC16C55 20 I/O Pins Clock PIC16CR54A 4 Peripherals Timer Module(s) Features PIC16C54 Maximum Frequency of Operation (MHz) I/O Pins 20 20 12 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 Number of Instructions 33 33 33 33 Packages 28-pin DIP, SOIC, SSOP 28-pin DIP, SOIC, SSOP 18-pin DIP, SOIC; 18-pin DIP, SOIC; 20-pin SSOP 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability. DS30234E-page 306  1997-2013 Microchip Technology Inc. PIC16C6X F.5 PIC16C55X Family of Devices PIC16C556(1) PIC16C554 Clock Memory 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K Data Memory (bytes) 80 80 128 Timer Module(s) TMR0 TMR0 TMR0 — — — — — — Peripherals Comparators(s) Internal Reference Voltage Features PIC16C558 Maximum Frequency of Operation (MHz) Interrupt Sources 3 3 3 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 Brown-out Reset — — — Packages 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. F.6 PIC16C62X and PIC16C64X Family of Devices PIC16C620 Clock Memory PIC16C622 PIC16C642 PIC16C662 20 20 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K 4K 4K Data Memory (bytes) 80 80 128 176 176 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 2 2 2 2 2 Peripherals Comparators(s) Features PIC16C621 Maximum Frequency of Operation (MHz) Internal Reference Voltage Yes Yes Yes Yes Yes Interrupt Sources 4 4 4 4 5 I/O Pins 13 13 13 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 3.0-6.0 3.0-6.0 Brown-out Reset Yes Yes Yes Yes Yes Packages 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 18-pin DIP, SOIC; 20-pin SSOP 28-pin PDIP, SOIC, Windowed CDIP 40-pin PDIP, Windowed CDIP; 44-pin PLCC, MQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7.  1997-2013 Microchip Technology Inc. DS30234E-page 307 PIC16C6X F.7 PIC16C7XX Family of Devces PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72(1) Maximum Frequency of Operation (MHz) 20 20 20 20 20 20 EPROM Program Memory (x14 words) 512 1K 1K 2K 2K — ROM Program Memory (14K words) — — — — — 2K Data Memory (bytes) 36 36 68 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/ Peripherals PWM Module(s) — — — — 1 1 Serial Port(s) (SPI/I2C, USART) — — — — SPI/I2C SPI/I2C Parallel Slave Port — Clock Memory A/D Converter (8-bit) Channels 4 Features — — — — — 4 4 4 5 5 Interrupt Sources 4 4 4 4 8 8 I/O Pins 13 13 13 13 22 22 Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown-out Reset Yes — Yes Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C73A Clock Memory PIC16C76 PIC16C77 20 20 20 EPROM Program Memory (x14 words) 4K 4K 8K 8K Data Memory (bytes) 192 192 368 368 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 2 2 2 SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART Yes Capture/Compare/PWM Mod- 2 Peripherals ule(s) Serial Port(s) USART) (SPI/I2C, SPI/I2C, USART Parallel Slave Port Features PIC16C74A Maximum Frequency of Oper- 20 ation (MHz) Yes — A/D Converter (8-bit) Channels 5 — 8 5 8 Interrupt Sources 11 12 11 12 I/O Pins 22 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Packages 28-pin SDIP, SOIC 40-pin DIP; 44-pin PLCC, MQFP, TQFP 28-pin SDIP, SOIC 40-pin DIP; 44-pin PLCC, MQFP, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. DS30234E-page 308  1997-2013 Microchip Technology Inc. PIC16C6X F.8 PIC16C8X Family of Devices PIC16F83 Maximum Frequency of Operation (MHz) Clock Memory Peripherals Features PIC16CR83 10 10 PIC16F84 10 PIC16CR84 10 Flash Program Memory 512 — 1K — EEPROM Program Memory — — — — ROM Program Memory — 512 — 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 Timer Module(s) TMR0 TMR0 TMR0 TMR0 Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0 Packages 18-pin DIP, SOIC 18-pin DIP, SOIC 18-pin DIP, SOIC 18-pin DIP, SOIC All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7. F.9 PIC16C9XX Family Of Devices PIC16C923 Clock Memory 8 8 EPROM Program Memory 4K 4K Data Memory (bytes) 176 176 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/PWM Module(s) 1 1 SPI/I2C SPI/I2C Parallel Slave Port — — A/D Converter (8-bit) Channels — 5 LCD Module 4 Com, 32 Seg 4 Com, 32 Seg Serial Port(s) Peripherals (SPI/I2C, USART) Features PIC16C924 Maximum Frequency of Operation (MHz) Interrupt Sources 8 9 I/O Pins 25 25 Input Pins 27 27 Voltage Range (Volts) 3.0-6.0 3.0-6.0 In-Circuit Serial Programming Yes Yes Brown-out Reset — — Packages 64-pin SDIP(1), TQFP; 68-pin PLCC, Die 64-pin SDIP(1), TQFP; 68-pin PLCC, Die All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7.  1997-2013 Microchip Technology Inc. DS30234E-page 309 PIC16C6X F.10 PIC17CXXX Family of Devices PIC17C42A Clock Memory Clock Memory PIC17CR43 PIC17C44 33 33 33 33 EPROM Program Memory (words) 2K — 4K — 8K ROM Program Memory (words) — 2K — 4K — RAM Data Memory (bytes) 232 232 454 454 454 Timer Module(s) TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 Captures/PWM Module(s) 2 2 2 2 2 Serial Port(s) (USART) Yes Yes Yes Yes Yes Hardware Multiply Yes Yes Yes Yes Yes External Interrupts Yes Yes Yes Yes Yes Interrupt Sources 11 11 11 11 11 I/O Pins 33 33 33 33 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Number of Instructions 58 58 58 58 58 Packages 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP 40-pin DIP; 44-pin PLCC, MQFP, TQFP PIC17C752 PIC17C756 Maximum Frequency of Operation (MHz) 33 33 EPROM Program Memory (words) 8K 16K ROM Program Memory (words) — — RAM Data Memory (bytes) 454 902 Timer Module(s) TMR0, TMR1, TMR2, TMR3 TMR0, TMR1, TMR2, TMR3 Peripherals Features PIC17C43 33 Peripherals Features PIC17CR42 Maximum Frequency of Operation (MHz) Captures/PWM Module(s) 4/3 4/3 Serial Port(s) (USART) 2 2 Hardware Multiply Yes Yes External Interrupts Yes Yes Interrupt Sources 18 18 I/O Pins 50 50 Voltage Range (Volts) 3.0-6.0 3.0-6.0 Number of Instructions 58 58 Packages 64-pin DIP; 68-pin LCC, 68-pin TQFP 64-pin DIP; 68-pin LCC, 68-pin TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. DS30234E-page 310  1997-2013 Microchip Technology Inc. PIC16C6X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55. Pin compatibility does not mean that the devices offer the same features. As an example, the PIC16C54 is pin compatible with the PIC16C71, but does not have an A/D converter, weak pull-ups on PORTB, or interrupts. TABLE F-1: PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC12C508, PIC12C509, PIC12C671, PIC12C672 8-pin PIC16C154, PIC16CR154, PIC16C156, PIC16CR156, PIC16C158, PIC16CR158, PIC16C52, PIC16C54, PIC16C54A, PIC16CR54A, PIC16C56, PIC16C58A, PIC16CR58A, PIC16C61, PIC16C554, PIC16C556, PIC16C558 PIC16C620, PIC16C621, PIC16C622 PIC16C641, PIC16C642, PIC16C661, PIC16C662 PIC16C710, PIC16C71, PIC16C711, PIC16C715 PIC16F83, PIC16CR83, PIC16F84A, PIC16CR84 18-pin, 20-pin PIC16C55, PIC16C57, PIC16CR57B 28-pin PIC16CR62, PIC16C62A, PIC16C63, PIC16CR63, PIC16C66, PIC16C72, PIC16C73A, PIC16C76 28-pin PIC16CR64, PIC16C64A, PIC16C65A, PIC16CR65, PIC16C67, PIC16C74A, PIC16C77 40-pin PIC17CR42, PIC17C42A, PIC17C43, PIC17CR43, PIC17C44 40-pin PIC16C923, PIC16C924 64/68-pin PIC17C756, PIC17C752 64/68-pin  1997-2013 Microchip Technology Inc. DS30234E-page 311 PIC16C6X NOTES: DS30234E-page 312  1997-2013 Microchip Technology Inc. PIC16C6X INDEX Numerics 9-bit Receive Enable bit, RX9 ........................................... 106 9-bit Transmit Enable bit, TX9 .......................................... 105 9th bit of received data, RX9D .......................................... 106 9th bit of transmit data, TX9D ........................................... 105 A Absolute Maximum Ratings .............................. 163, 183, 199, 215, 231, 247, 263 ACK..................................................................... 96, 100, 101 ALU ....................................................................................... 9 Application Notes AN552 (Implementing Wake-up on Key Stroke) ......... 53 AN556 (Implementing a Table Read) ......................... 48 AN594 (Using the CCP Modules) ............................... 77 Architectural Overview .......................................................... 9 B Baud Rate Formula ........................................................... 107 Baud Rate Generator ........................................................ 107 Baud Rates Asynchronous Mode ................................................. 108 Error, Calculating ...................................................... 107 RX Pin Sampling, Timing Diagrams.................. 110, 111 Sampling ................................................................... 110 Synchronous Mode ................................................... 108 BF ......................................................................... 84, 89, 100 Block Diagrams Capture Mode Operation ............................................ 78 Compare Mode ........................................................... 79 Crystal Oscillator, Ceramic Resonator...................... 125 External Brown-out Protection .................................. 135 External Parallel Resonant Crystal Circuit ................ 127 External Power-on Reset .......................................... 135 External Series Resonant Crystal Circuit.................. 127 I2C Mode..................................................................... 99 In-circuit Programming Connections......................... 142 Interrupt Logic ........................................................... 137 On-chip Reset Circuit................................................ 128 Parallel Slave Port, PORTD-PORTE .......................... 61 PIC16C61 ................................................................... 10 PIC16C62 ................................................................... 11 PIC16C62A ................................................................. 11 PIC16C63 ................................................................... 12 PIC16C64 ................................................................... 11 PIC16C64A ................................................................. 11 PIC16C65 ................................................................... 12 PIC16C65A ................................................................. 12 PIC16C66 ................................................................... 13 PIC16C67 ................................................................... 13 PIC16CR62................................................................. 11 PIC16CR63................................................................. 12 PIC16CR64................................................................. 11 PIC16CR65................................................................. 12 PORTC ....................................................................... 55 PORTD (I/O Mode) ..................................................... 57 PORTE (I/O Mode) ..................................................... 58 PWM ........................................................................... 80 RA3:RA0 pins ............................................................. 51 RA4/T0CKI pin ............................................................ 51 RA5 pin ....................................................................... 51 RB3:RB0 pins ............................................................. 54 RB7:RB4 pins ....................................................... 53, 54 RC Oscillator Mode................................................... 127  1997-2013 Microchip Technology Inc. SPI Master/Slave Connection..................................... 87 SSP in I2C Mode ........................................................ 99 SSP in SPI Mode.................................................. 86, 91 Timer0 ........................................................................ 65 Timer0/WDT Prescaler ............................................... 68 Timer1 ........................................................................ 72 Timer2 ........................................................................ 75 USART Receive ....................................................... 114 USART Transmit ...................................................... 112 Watchdog Timer ....................................................... 140 BOR .................................................................................. 129 BOR ............................................................................ 47, 131 BRGH ............................................................................... 105 Brown-out Reset (BOR).................................................... 129 Brown-out Reset Status bit, BOR ....................................... 47 Buffer Full Status bit, BF............................................... 84, 89 C C ......................................................................................... 35 C Compiler........................................................................ 161 Capture Block Diagram ............................................................ 78 Mode........................................................................... 78 Pin Configuration ........................................................ 78 Prescaler .................................................................... 79 Software Interrupt ....................................................... 78 Capture Interrupt ................................................................ 78 Capture/Compare/PWM (CCP) Capture Mode............................................................. 78 Capture Mode Block Diagram .................................... 78 CCP1 .......................................................................... 77 CCP2 .......................................................................... 77 Compare Mode........................................................... 79 Compare Mode Block Diagram .................................. 79 Overview..................................................................... 63 Prescaler .................................................................... 79 PWM Block Diagram .................................................. 80 PWM Mode................................................................. 80 PWM, Example Frequencies/Resolutions .................. 81 Section........................................................................ 77 Carry..................................................................................... 9 Carry bit .............................................................................. 35 CCP Module Interaction...................................................... 77 CCP pin Configuration........................................................ 78 CCP to Timer Resource Use .............................................. 77 CCP1 Interrupt Enable bit, CCP1IE.................................... 38 CCP1 Interrupt Flag bit, CCP1IF ........................................ 41 CCP1 Mode Select bits....................................................... 78 CCP1CON ............................................ 24, 26, 28, 30, 32, 34 CCP1IE............................................................................... 38 CCP1IF ............................................................................... 41 CCP1M3:CCM1M0............................................................. 78 CCP1X:CCP1Y................................................................... 78 CCP2 Interrupt Enable bit, CCP2IE.................................... 45 CCP2 Interrupt Flag bit, CCP2IF ........................................ 46 CCP2 Mode Select bits....................................................... 78 CCP2CON ............................................ 24, 26, 28, 30, 32, 34 CCP2IE............................................................................... 45 CCP2IF ............................................................................... 46 CCP2M3:CCP2M0.............................................................. 78 CCP2X:CCP2Y................................................................... 78 CCPR1H............................................... 24, 26, 28, 30, 32, 34 CCPR1L ............................................... 24, 26, 28, 30, 32, 34 CCPR2H............................................... 24, 26, 28, 30, 32, 34 CCPR2L ............................................... 24, 26, 28, 30, 32, 34 CKE .................................................................................... 89 CKP .............................................................................. 85, 90 DS30234E-page 313 PIC16C6X Clearing Interrupts............................................................... 53 Clock Polarity Select bit, CKP ....................................... 85, 90 Clock Polarity, SPI Mode .................................................... 87 Clock Source Select bit, CSRC......................................... 105 Clocking Scheme ................................................................ 18 Code Examples Changing Between Capture Prescalers ...................... 79 Ensuring Interrupts are Globally Disabled ................ 136 Indirect Addressing ..................................................... 49 Initializing PORTA ....................................................... 51 Initializing PORTB ....................................................... 53 Initializing PORTC....................................................... 55 Loading the SSPBUF Register ................................... 86 Loading the SSPBUF register ..................................... 91 Reading a 16-bit Free-running Timer .......................... 73 Read-Modify-Write on an I/O Port............................... 60 Saving Status, W, and PCLATH Registers ............... 139 Subroutine Call, Page0 to Page1................................ 49 Code Protection ................................................................ 142 Compare Block Diagram............................................................. 79 Mode ........................................................................... 79 Pin Configuration ........................................................ 79 Software Interrupt ....................................................... 79 Special Event Trigger.................................................. 79 Computed GOTO ................................................................ 48 Configuration Bits.............................................................. 123 Configuration Word, Diagram............................................ 124 Connecting Two Microcontrollers........................................ 87 Continuous Receive Enable bit, CREN............................. 106 CREN ................................................................................ 106 CSRC ................................................................................ 105 D D/A ................................................................................ 84, 89 Data/Address bit, D/A.................................................... 84, 89 Data Memory Organization................................................................ 20 Section ........................................................................ 20 Data Sheet Compatibility ............................................................. 307 Modifications ............................................................. 307 What’s New ............................................................... 308 DC ....................................................................................... 35 DC CHARACTERISTICS .. 164, 184, 200, 216, 232, 248, 264 Development Support ....................................................... 159 Development Tools ........................................................... 159 Device Drawings 18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) ............................................... 296 18-Lead Plastic Dual In-line (300 mil) ....................... 291 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body).................................... 294 28-Lead Ceramic CERDIP Dual In-line with Window (300 mil)) ..................................................... 297 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil) ............................................... 299 28-Lead Plastic Dual In-line (300 mil) ....................... 292 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)..................................... 295 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm)............................... 300 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) ............................................... 298 40-Lead Plastic Dual In-line (600 mil) ....................... 293 44-Lead Plastic Leaded Chip Carrier (Square) ......... 301 DS30234E-page 314 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) ....... 302, 303 Device Varieties.................................................................... 7 Digit Carry............................................................................. 9 Digit Carry bit ...................................................................... 35 Direct Addressing ............................................................... 49 E Electrical Characteristics .. 163, 183, 199, 215, 231, 247, 263 External Clock Synchronization, TMR0 .............................. 67 F Family of Devices PIC12CXXX.............................................................. 309 PIC14C000 ............................................................... 309 PIC16C15X............................................................... 310 PIC16C55X............................................................... 311 PIC16C5X................................................................. 310 PIC16C62X and PIC16C64X.................................... 311 PIC16C6X..................................................................... 6 PIC16C7XX .............................................................. 312 PIC16C8X................................................................. 313 PIC16C9XX .............................................................. 313 PIC17CXX ................................................................ 314 FERR ................................................................................ 106 Framing Error bit, FERR ................................................... 106 FSR......................... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 Fuzzy Logic Dev. System (fuzzyTECH-MP)........... 159, 161 G General Description .............................................................. 5 General Purpose Registers ................................................ 20 GIE...................................................................................... 37 Global Interrupt Enable bit, GIE.......................................... 37 Graphs PIC16C6X................................................................. 281 PIC16C61 ................................................................. 173 H High Baud Rate Select bit, BRGH .................................... 105 I I/O Ports, Section................................................................ 51 I2C Addressing................................................................ 100 Addressing I2C Devices.............................................. 96 Arbitration ................................................................... 98 Block Diagram ............................................................ 99 Clock Synchronization ................................................ 98 Combined Format ....................................................... 97 I2C Operation.............................................................. 99 I2C Overview............................................................... 95 Initiating and Terminating Data Transfer .................... 95 Master Mode............................................................. 103 Master-Receiver Sequence ........................................ 97 Master-Transmitter Sequence .................................... 97 Mode........................................................................... 99 Mode Selection........................................................... 99 Multi-master................................................................ 98 Multi-Master Mode .................................................... 103 Reception ................................................................. 101 Reception Timing Diagram ....................................... 101 SCL and SDA pins.................................................... 100 Slave Mode............................................................... 100 START ........................................................................ 95 STOP.................................................................... 95, 96  1997-2013 Microchip Technology Inc. PIC16C6X Transfer Acknowledge ................................................ 96 Transmission............................................................. 102 ID Locations ...................................................................... 142 IDLE_MODE ..................................................................... 104 In-circuit Serial Programming............................................ 142 INDF...................................................... 24, 26, 28, 30, 32, 34 Indirect Addressing ............................................................. 49 Instruction Cycle ................................................................. 18 Instruction Flow/Pipelining .................................................. 18 Instruction Format ............................................................. 143 Instruction Set ADDLW ..................................................................... 145 ADDWF..................................................................... 145 ANDLW ..................................................................... 145 ANDWF..................................................................... 145 BCF........................................................................... 146 BSF ........................................................................... 146 BTFSC ...................................................................... 146 BTFSS ...................................................................... 147 CALL ......................................................................... 147 CLRF......................................................................... 148 CLRW ....................................................................... 148 CLRWDT................................................................... 148 COMF ....................................................................... 149 DECF ........................................................................ 149 DECFSZ.................................................................... 149 GOTO ....................................................................... 150 INCF.......................................................................... 150 INCFSZ ..................................................................... 151 IORLW ...................................................................... 151 IORWF ...................................................................... 152 MOVF........................................................................ 152 MOVLW .................................................................... 152 MOVWF .................................................................... 152 NOP .......................................................................... 153 OPTION .................................................................... 153 RETFIE ..................................................................... 153 RETLW ..................................................................... 154 RETURN ................................................................... 154 RLF ........................................................................... 155 RRF........................................................................... 155 SLEEP ...................................................................... 156 SUBLW ..................................................................... 156 SUBWF ..................................................................... 157 SWAPF ..................................................................... 157 TRIS.......................................................................... 157 XORLW..................................................................... 158 XORWF..................................................................... 158 Section ...................................................................... 143 Summary Table......................................................... 144 INTCON .................. 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 INTE .................................................................................... 37 INTEDG .............................................................................. 36 Interrupt Edge Select bit, INTEDG ...................................... 36 Interrupt on Change Feature............................................... 53 Interrupts Section ...................................................................... 136 CCP ............................................................................ 78 CCP1 .......................................................................... 38 CCP1 Flag bit.............................................................. 41 CCP2 Enable bit ......................................................... 45 CCP2 Flag bit.............................................................. 46 Context Saving.......................................................... 139 Parallel Slave Port Flag bit.......................................... 43 Parallel Slave Prot Read/Write Enable bit .................. 39 Port RB ....................................................................... 53 RB0/INT .............................................................. 54, 138  1997-2013 Microchip Technology Inc. RB0/INT Timing Diagram ......................................... 138 Receive Flag bit.......................................................... 42 Timer0 ........................................................................ 65 Timer0, Timing............................................................ 66 Timing Diagram, Wake-up from SLEEP ................... 142 TMR0........................................................................ 138 USART Receive Enable bit ........................................ 39 USART Transmit Enable bit ....................................... 39 USART Transmit Flag bit............................................ 42 Wake-up ................................................................... 141 Wake-up from SLEEP .............................................. 141 INTF.................................................................................... 37 IRP...................................................................................... 35 L Loading the Program Counter ............................................ 48 M MPASM Assembler................................................... 159, 160 MPLAB-C.......................................................................... 161 MPSIM Software Simulator....................................... 159, 161 O OERR ............................................................................... 106 One-Time-Programmable Devices ....................................... 7 OPCODE .......................................................................... 143 Open-Drain ......................................................................... 51 OPTION ................................................ 25, 27, 29, 31, 33, 34 Oscillator Start-up Timer (OST) ................................ 123, 129 Oscillators Block Diagram, External Parallel Resonant Crystal . 127 Capacitor Selection .................................................... 73 Configuration ............................................................ 125 External Crystal Circuit ............................................. 127 HS..................................................................... 125, 130 LP ..................................................................... 125, 130 RC, Block Diagram ................................................... 127 RC, Section .............................................................. 127 XT ............................................................................. 125 Overrun Error bit, OERR................................................... 106 P P ................................................................................... 84, 89 Packaging Information...................................................... 291 Parallel Slave Port PORTD ....................................................................... 57 Section........................................................................ 61 Parallel Slave Port Interrupt Flag bit, PSPIF....................... 43 Parallel Slave Port Read/Write Interrupt Enable bit, PSPIE 39 PCL......................... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 PCLATH ........... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 48 PCON ........................................... 25, 27, 29, 31, 33, 34, 130 PD............................................................................... 35, 131 PEIE ................................................................................... 37 Peripheral Interrupt Enable bit, PEIE.................................. 37 PICDEM-1 Low-Cost PIC16/17 Demo Board ........... 159, 160 PICDEM-2 Low-Cost PIC16CXX Demo Board......... 159, 160 PICDEM-3 Low-Cost PIC16C9XXX Demo Board ............ 160 PICMASTER In-Circuit Emulator...................................... 159 PICSTART Low-Cost Development System..................... 159 PIE1 ...................................................... 25, 27, 29, 31, 33, 34 PIE2 ...................................................... 25, 27, 29, 31, 33, 34 Pin Compatible Devices.................................................... 315 Pin Functions MCLR/VPP .................................................................. 16 DS30234E-page 315 PIC16C6X OSC1/CLKIN............................................................... 16 OSC2/CLKOUT........................................................... 16 PORTA........................................................................ 52 PORTB........................................................................ 54 PORTC ....................................................................... 55 PORTD ....................................................................... 57 PORTE........................................................................ 59 RA4/T0CKI ............................................................ 16, 52 RA5/SS ................................................................. 16, 52 RB0/INT ................................................................ 16, 54 RB6 ........................................................................... 142 RB7 ........................................................................... 142 RC0/T1OSI/T1CKI ...................................................... 55 RC0/T1OSO/T1CKI .............................................. 16, 55 RC1/T1OSI ................................................................. 55 RC1/T1OSI/CCP2 ................................................. 16, 55 RC1/T1OSO................................................................ 55 RC2/CCP1 ...................................................... 16, 55, 56 RC3/SCK/SCL ................................................ 16, 55, 56 RC4/SDI/SDA ................................................. 16, 55, 56 RC5/SDO ........................................................ 16, 55, 56 RC6/TX/CK ..................................... 16, 55, 56, 105–120 RC7/RX/DT ..................................... 16, 55, 56, 105–120 RD7/PSP7:RD0/PSP0 .......................................... 17, 57 RE0/RD ........................................................... 17, 59, 61 RE1/WR .......................................................... 17, 59, 61 RE2/CS ........................................................... 17, 59, 61 SCK....................................................................... 86–88 SDI ........................................................................ 86–88 SDO ...................................................................... 86–88 SS ......................................................................... 86–88 VDD.............................................................................. 17 VSS .............................................................................. 17 PIR1 ...................................................... 24, 26, 28, 30, 32, 34 PIR2 ...................................................... 24, 26, 28, 30, 32, 34 POP..................................................................................... 48 POR ............................................................................ 47, 131 POR Time-Out Sequence on Power-Up ........................... 134 Port RB Interrupt ................................................................. 53 PORTA............................................ 24, 26, 28, 30, 32, 34, 51 PORTB............................................ 24, 26, 28, 30, 32, 34, 53 PORTB Interrupt on Change............................................. 138 PORTB Pull-up Enable bit, RBPU....................................... 36 PORTC............................................ 24, 26, 28, 30, 32, 34, 55 PORTD............................................ 24, 26, 28, 30, 32, 34, 57 PORTE............................................ 24, 26, 28, 30, 32, 34, 58 Ports Bi-directional ............................................................... 60 I/O Programming Considerations................................ 60 PORTA........................................................................ 16 PORTB........................................................................ 16 PORTC ....................................................................... 16 PORTD ....................................................................... 17 PORTE........................................................................ 17 Successive Operations on an I/O Port ........................ 60 Power/Control Status Register, PCON ............................. 130 Power-down bit ................................................................... 35 Power-down Mode ............................................................ 141 Power-on Reset (POR) ..................................................... 129 Power-on Reset Status bit, POR......................................... 47 Power-up Timer (PWRT)........................................... 123, 129 PR2 ....................................................... 25, 27, 29, 31, 33, 34 Prescaler ............................................................................. 68 Prescaler Assignment bit, PSA ........................................... 36 Prescaler Rate Select bits, PS2:PS0 .................................. 36 PRO MATE Universal Programmer .................................. 159 Program Memory DS30234E-page 316 Map....................................................................... 19, 20 Organization ............................................................... 19 Paging ........................................................................ 48 Section........................................................................ 19 Programming While In-circuit............................................ 142 PS2:PS0 ............................................................................. 36 PSA..................................................................................... 36 PSPIE ................................................................................. 39 PSPIF ................................................................................. 43 Pull-ups............................................................................... 53 PUSH.................................................................................. 48 PWM Block Diagram ............................................................ 80 Calculations ................................................................ 81 Mode........................................................................... 80 Output Timing ............................................................. 80 PWM Least Significant bits ................................................. 78 Q Quadrature Clocks.............................................................. 18 Quick-Turnaround-Production .............................................. 7 R R/W bit ............................................ 84, 89, 96, 100, 101, 102 RA0 pin ............................................................................... 51 RA1 pin ............................................................................... 51 RA2 pin ............................................................................... 51 RA3 pin ............................................................................... 51 RA4/T0CKI pin.................................................................... 51 RA5 pin ............................................................................... 51 RB Port Change Interrupt Enable bit, RBIE........................ 37 RB Port Change Interrupt Flag bit, RBIF ............................ 37 RB0..................................................................................... 54 RB0/INT ............................................................................ 138 RB0/INT External Interrupt Enable bit, INTE ...................... 37 RB0/INT External Interrupt Flag bit, INTF........................... 37 RB1..................................................................................... 54 RB2..................................................................................... 54 RB3..................................................................................... 54 RB4..................................................................................... 53 RB5..................................................................................... 53 RB6..................................................................................... 53 RB7..................................................................................... 53 RBIE ................................................................................... 37 RBIF.................................................................................... 37 RBPU............................................................................ 36, 53 RC Oscillator..................................................................... 130 RCIE ................................................................................... 39 RCIF ................................................................................... 42 RCREG................................................. 24, 26, 28, 30, 32, 34 RCSTA.......................................... 24, 26, 28, 30, 32, 34, 106 RCV_MODE ..................................................................... 104 Read Only Memory............................................................... 7 Read/Write bit Information, R/W ................................... 84, 89 Receive and Control Register........................................... 106 Receive Overflow Detect bit, SSPOV ................................. 85 Receive Overflow Indicator bit, SSPOV.............................. 90 Register Bank Select bit, Indirect........................................ 35 Register Bank Select bits. Direct ........................................ 35  1997-2013 Microchip Technology Inc. PIC16C6X Registers CCP1CON Diagram .............................................................. 78 Section ................................................................ 78 Summary .................................... 24, 26, 28, 30, 32 CCP2CON Diagram .............................................................. 78 Section ................................................................ 78 Summary ................................................ 26, 30, 32 CCPR1H Summary .................................... 24, 26, 28, 30, 32 CCPR1L Summary .................................... 24, 26, 28, 30, 32 CCPR2H Summary ................................................ 26, 30, 32 CCPR2L Summary ................................................ 26, 30, 32 FSR Indirect Addressing ............................................. 49 Summary .............................. 24, 26, 28, 30, 32, 34 INDF Indirect Addressing ............................................. 49 Summary .............................. 24, 26, 28, 30, 32, 34 INTCON Diagram .............................................................. 37 Section ................................................................ 37 Summary .............................. 24, 26, 28, 30, 32, 34 OPTION Diagram .............................................................. 36 Section ................................................................ 36 Summary .............................. 25, 27, 29, 31, 33, 34 PCL Section ................................................................ 48 Summary .............................. 24, 26, 28, 30, 32, 34 PCLATH Section ................................................................ 48 Summary .............................. 24, 26, 28, 30, 32, 34 PCON Diagram .............................................................. 47 Section ................................................................ 47 Summary .................................... 25, 27, 29, 31, 33 PIE1 Diagram .............................................................. 40 Section ................................................................ 38 Summary .................................... 25, 27, 29, 31, 33 PIE2 Diagram .............................................................. 45 Section ................................................................ 45 Summary ................................................ 27, 31, 33 PIR1 Diagram .............................................................. 44 Section ................................................................ 41 Summary .................................... 24, 26, 28, 30, 32 PIR2 Diagram .............................................................. 46 Section ................................................................ 46 Summary ................................................ 26, 30, 32 PORTA Section ................................................................ 51 Summary .................................... 24, 26, 28, 30, 32 PORTB Section ................................................................ 53 Summary .............................. 24, 26, 28, 30, 32, 34 PORTC Section ................................................................ 55 Summary .................................... 24, 26, 28, 30, 32  1997-2013 Microchip Technology Inc. PORTD Section ............................................................... 57 Summary ................................................ 28, 30, 32 PORTE Section ............................................................... 58 Summary ................................................ 28, 30, 32 PR2 Summary .................................... 25, 27, 29, 31, 33 RCREG Summary ................................................ 26, 30, 32 RCSTA Diagram ............................................................ 106 Summary ................................................ 26, 30, 32 SPBRG Summary ................................................ 27, 31, 33 SSPBUF Section ............................................................... 86 Summary .................................... 24, 26, 28, 30, 32 SSPCON Diagram .............................................................. 85 Summary .................................... 24, 26, 28, 30, 32 SSPSR Section ............................................................... 86 SSPSTAT ................................................................... 89 Diagram .............................................................. 84 Section ............................................................... 84 Summary .................................... 25, 27, 29, 31, 33 STATUS Diagram .............................................................. 35 Section ............................................................... 35 Summary .............................. 24, 26, 28, 30, 32, 34 T1CON Diagram .............................................................. 71 Section ............................................................... 71 Summary .................................... 24, 26, 28, 30, 32 T2CON Diagram .............................................................. 75 Section ............................................................... 75 Summary .................................... 24, 26, 28, 30, 32 TMR0 Summary .............................. 24, 26, 28, 30, 32, 34 TMR1H Summary .................................... 24, 26, 28, 30, 32 TMR1L Summary .................................... 24, 26, 28, 30, 32 TMR2.......................................................................... 75 Summary .................................... 24, 26, 28, 30, 32 TRISA Section ............................................................... 51 Summary .................................... 25, 27, 29, 31, 33 TRISB Section ............................................................... 53 Summary .............................. 25, 27, 29, 31, 33, 34 TRISC Section ............................................................... 55 Summary .................................... 25, 27, 29, 31, 33 TRISD Section ............................................................... 57 Summary ................................................ 29, 31, 33 TRISE Diagram .............................................................. 58 Section ............................................................... 58 Summary ................................................ 29, 31, 33 TXREG Summary ................................................ 26, 30, 32 DS30234E-page 317 PIC16C6X TXSTA Diagram ............................................................ 105 Section .............................................................. 105 Summary....................................................... 31, 33 W................................................................................... 9 Special Function Registers, Initialization Conditions ................................................................. 132 Special Function Registers, Reset Conditions .......... 131 Special Function Register Summary... 24, 26, 28, 30, 32 File Maps .................................................................... 21 Resets ............................................................................... 128 ROM...................................................................................... 7 RP0 bit .......................................................................... 20, 35 RP1 ..................................................................................... 35 RX9 ................................................................................... 106 RX9D................................................................................. 106 S S.................................................................................... 84, 89 SCI - See Universal Synchronous Asynchronous Receiver Transmitter (USART) SCK..................................................................................... 86 SCL ................................................................................... 100 SDI ...................................................................................... 86 SDO .................................................................................... 86 Serial Port Enable bit, SPEN............................................. 106 Serial Programming .......................................................... 142 Serial Programming, Block Diagram ................................. 142 Serialized Quick-Turnaround-Production .............................. 7 Single Receive Enable bit, SREN ..................................... 106 Slave Mode SCL ........................................................................... 100 SDA........................................................................... 100 SLEEP Mode............................................................. 123, 141 SMP .................................................................................... 89 Software Simulator (MPSIM)............................................. 161 SPBRG.................................................. 25, 27, 29, 31, 33, 34 Special Features, Section ................................................. 123 SPEN ................................................................................ 106 SPI Block Diagram....................................................... 86, 91 Master Mode ............................................................... 92 Master Mode Timing ................................................... 93 Mode ........................................................................... 86 Serial Clock ................................................................. 91 Serial Data In .............................................................. 91 Serial Data Out ........................................................... 91 Slave Mode Timing ..................................................... 94 Slave Mode Timing Diagram....................................... 93 Slave Select ................................................................ 91 SPI clock ..................................................................... 92 SPI Mode .................................................................... 91 SSPCON ..................................................................... 90 SSPSTAT.................................................................... 89 SPI Clock Edge Select bit, CKE.......................................... 89 SPI Data Input Sample Phase Select bit, SMP................... 89 SPI Mode ............................................................................ 86 SREN ................................................................................ 106 SS ....................................................................................... 86 SSP Module Overview ........................................................ 83 Section ........................................................................ 83 SSPBUF...................................................................... 92 SSPCON ..................................................................... 90 SSPSR ........................................................................ 92 SSPSTAT.................................................................... 89 DS30234E-page 318 SSP in I2C Mode - See I2C SSPADD ......................................... 25, 27, 29, 31, 33, 34, 99 SSPBUF ......................................... 24, 26, 28, 30, 32, 34, 99 SSPCON................................... 24, 26, 28, 30, 32, 34, 85, 90 SSPEN.......................................................................... 85, 90 SSPIE ................................................................................. 38 SSPIF ................................................................................. 41 SSPM3:SSPM0 ............................................................ 85, 90 SSPOV ................................................................. 85, 90, 100 SSPSTAT ................................. 25, 27, 29, 31, 33, 34, 84, 99 SSPSTAT Register ............................................................. 89 Stack................................................................................... 48 Start bit, S ..................................................................... 84, 89 STATUS.................. 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 Status bits ................................................................. 130, 131 Status Bits During Various Resets.................................... 131 Stop bit, P ..................................................................... 84, 89 Switching Prescalers .......................................................... 69 SYNC,USART Mode Select bit, SYNC............................. 105 Synchronizing Clocks, TMR0.............................................. 67 Synchronous Serial Port (SSP) Block Diagram, SPI Mode........................................... 86 SPI Master/Slave Diagram ......................................... 87 SPI Mode.................................................................... 86 Synchronous Serial Port Enable bit, SSPEN................ 85, 90 Synchronous Serial Port Interrupt Enable bit, SSPIE ......... 38 Synchronous Serial Port Interrupt Flag bit, SSPIF ............. 41 Synchronous Serial Port Mode Select bits, SSPM3:SSPM0 ............................................................ 85, 90 Synchronous Serial Port Module ........................................ 83 Synchronous Serial Port Status Register ........................... 89 T T0CS................................................................................... 36 T0IE .................................................................................... 37 T0IF .................................................................................... 37 T0SE................................................................................... 36 T1CKPS1:T1CKPS0........................................................... 71 T1CON.................................................. 24, 26, 28, 30, 32, 34 T1OSCEN........................................................................... 71 T1SYNC.............................................................................. 71 T2CKPS1:T2CKPS0........................................................... 75 T2CON............................................ 24, 26, 28, 30, 32, 34, 75 TIme-out ........................................................................... 130 Time-out bit......................................................................... 35 Time-out Sequence .......................................................... 130 Timer Modules Overview, all ............................................................... 63 Timer0 Block Diagram .................................................... 65 Counter Mode..................................................... 65 External Clock .................................................... 67 Interrupt .............................................................. 65 Overview............................................................. 63 Prescaler ............................................................ 68 Section................................................................ 65 Timer Mode ........................................................ 65 Timing DiagramTiiming Diagrams Timer0 ................................................................ 65 TMR0 register..................................................... 65 Timer1 Block Diagram .................................................... 72 Capacitor Selection ............................................ 73 Counter Mode, Asynchronous ............................ 73 Counter Mode, Synchronous.............................. 72 External Clock .................................................... 73 Oscillator............................................................. 73  1997-2013 Microchip Technology Inc. PIC16C6X Overview ............................................................. 63 Prescaler............................................................. 72 Read/Write in Asynchronous Counter Mode ...... 73 Section ................................................................ 71 Synchronizing with External Clock...................... 72 Timer Mode......................................................... 72 TMR1 Register Pair ............................................ 71 Timer2 Block Diagram .................................................... 75 Overview ............................................................. 63 Postscaler ........................................................... 75 Prescaler............................................................. 75 Timer0 Clock Synchronization, Delay ................................. 67 TImer0 Interrupt ................................................................ 138 Timer1 Clock Source Select bit, TMR1CS .......................... 71 Timer1 External Clock Input Synchronization Control bit, T1SYNC ........................................................... 71 Timer1 Input Clock Prescale Select bits ............................. 71 Timer1 Mode Selection ....................................................... 78 Timer1 On bit, TMR1ON ..................................................... 71 Timer1 Oscillator Enable Control bit, T1OSCEN ................ 71 Timer2 Clock Prescale Select bits, T2CKPS1:T2CKPS0 ........................................................... 75 Timer2 Module .................................................................... 75 Timer2 On bit, TMR2ON ..................................................... 75 Timer2 Output Postscale Select bits, TOUTPS3:TOUTPS0 .......................................................... 75 Timing Diagrams Brown-out Reset ....................................................... 129 I2C Clock Synchronization .......................................... 98 I2C Data Transfer Wait State ...................................... 96 I2C Multi-Master Arbitration......................................... 98 I2C Reception (7-bit Address) ................................... 101 PIC16C61 CLKOUT and I/O .............................................. 170 External Clock................................................... 169 Oscillator Start-up Timer ................................... 171 Power-up Timer ................................................ 171 Reset ................................................................ 171 Timer0............................................................... 172 Watchdog Timer ............................................... 171 PIC16C62 Capture/Compare/PWM ................................... 193 CLKOUT and I/O .............................................. 190 External Clock................................................... 189 I2C Bus Data ..................................................... 197 I2C Bus Start/Stop Bits ..................................... 196 Oscillator Start-up Timer ................................... 191 Power-up Timer ................................................ 191 Reset ................................................................ 191 SPI Mode .......................................................... 195 Timer0............................................................... 192 Timer1............................................................... 192 Watchdog Timer ............................................... 191 PIC16C62A Brown-out Reset ............................................... 207 Capture/Compare/PWM ................................... 209 CLKOUT and I/O .............................................. 206 External Clock................................................... 205 I2C Bus Data ..................................................... 213 I2C Bus Start/Stop Bits ..................................... 212 Oscillator Start-up Timer ................................... 207 Power-up Timer ................................................ 207 Reset ................................................................ 207 SPI Mode .......................................................... 211 Timer0............................................................... 208 Timer1............................................................... 208  1997-2013 Microchip Technology Inc. Watchdog Timer ............................................... 207 PIC16C63 Brown-out Reset............................................... 239 Capture/Compare/PWM ................................... 241 CLKOUT and I/O .............................................. 238 External Clock .................................................. 237 I2C Bus Data..................................................... 245 I2C Bus Start/Stop Bits ..................................... 244 Oscillator Start-up Timer................................... 239 Power-up Timer................................................ 239 Reset ................................................................ 239 SPI Mode.......................................................... 243 Timer0 .............................................................. 240 Timer1 .............................................................. 240 USART Synchronous Receive (Master/Slave) ................................................. 246 Watchdog Timer ............................................... 239 PIC16C64 Capture/Compare/PWM ................................... 193 CLKOUT and I/O .............................................. 190 External Clock .................................................. 189 I2C Bus Data..................................................... 197 I2C Bus Start/Stop Bits ..................................... 196 Oscillator Start-up Timer................................... 191 Parallel Slave Port............................................ 194 Power-up Timer................................................ 191 Reset ................................................................ 191 SPI Mode.......................................................... 195 Timer0 .............................................................. 192 Timer1 .............................................................. 192 Watchdog Timer ............................................... 191 PIC16C64A Brown-out Reset............................................... 207 Capture/Compare/PWM ................................... 209 CLKOUT and I/O .............................................. 206 External Clock .................................................. 205 I2C Bus Data..................................................... 213 I2C Bus Start/Stop Bits ..................................... 212 Oscillator Start-up Timer................................... 207 Parallel Slave Port............................................ 210 Power-up Timer................................................ 207 Reset ................................................................ 207 SPI Mode.......................................................... 211 Timer0 .............................................................. 208 Timer1 .............................................................. 208 Watchdog Timer ............................................... 207 PIC16C65 Capture/Compare/PWM ................................... 225 CLKOUT and I/O .............................................. 222 External Clock .................................................. 221 I2C Bus Data..................................................... 229 I2C Bus Start/Stop Bits ..................................... 228 Oscillator Start-up Timer................................... 223 Parallel Slave Port............................................ 226 Reset ................................................................ 223 SPI Mode.......................................................... 227 Timer0 .............................................................. 224 Timer1 .............................................................. 224 USART Synchronous Receive (Master/Slave) .................................................. 230 Watchdog Timer ............................................... 223 PIC16C65A Brown-out Reset............................................... 239 Capture/Compare/PWM ................................... 241 CLKOUT and I/O .............................................. 238 External Clock .................................................. 237 I2C Bus Data..................................................... 245 DS30234E-page 319 PIC16C6X I2C Bus Start/Stop Bits...................................... 244 Oscillator Start-up Timer ................................... 239 Parallel Slave Port ............................................ 242 Power-up Timer ................................................ 239 Reset................................................................. 239 SPI Mode .......................................................... 243 Timer0............................................................... 240 Timer1............................................................... 240 USART Synchronous Receive (Master/Slave)................................................... 246 Watchdog Timer................................................ 239 PIC16C66 Brown-out Reset ............................................... 271 Capture/Compare/PWM.................................... 273 CLKOUT and I/O............................................... 270 External Clock................................................... 269 I2C Bus Data ..................................................... 279 I2C Bus Start/Stop Bits...................................... 278 Oscillator Start-up Timer ................................... 271 Power-up Timer ................................................ 271 Reset................................................................. 271 Timer0............................................................... 272 Timer1............................................................... 272 USART Synchronous Receive (Master/Slave)................................................... 280 Watchdog Timer................................................ 271 PIC16C67 Brown-out Reset ............................................... 271 Capture/Compare/PWM.................................... 273 CLKOUT and I/O............................................... 270 External Clock................................................... 269 I2C Bus Data ..................................................... 279 I2C Bus Start/Stop Bits...................................... 278 Oscillator Start-up Timer ................................... 271 Parallel Slave Port ............................................ 274 Power-up Timer ................................................ 271 Reset................................................................. 271 Timer0............................................................... 272 Timer1............................................................... 272 USART Synchronous Receive (Master/Slave)................................................... 280 Watchdog Timer................................................ 271 PIC16CR62 Capture/Compare/PWM.................................... 209 CLKOUT and I/O............................................... 206 External Clock................................................... 205 I2C Bus Data ..................................................... 213 I2C Bus Start/Stop Bits...................................... 212 Oscillator Start-up Timer ................................... 207 Power-up Timer ................................................ 207 Reset................................................................. 207 SPI Mode .......................................................... 211 Timer0............................................................... 208 Timer1............................................................... 208 Watchdog Timer................................................ 207 DS30234E-page 320 PIC16CR63 Brown-out Reset............................................... 255 Capture/Compare/PWM ................................... 257 CLKOUT and I/O .............................................. 254 External Clock .................................................. 253 I2C Bus Data..................................................... 261 I2C Bus Start/Stop Bits ..................................... 260 Oscillator Start-up Timer................................... 255 Power-up Timer ................................................ 255 Reset ................................................................ 255 SPI Mode.......................................................... 259 Timer0 .............................................................. 256 Timer1 .............................................................. 256 USART Synchronous Receive (Master/Slave) ................................................. 262 Watchdog Timer ............................................... 255 PIC16CR64 Capture/Compare/PWM ................................... 209 CLKOUT and I/O .............................................. 206 External Clock .................................................. 205 I2C Bus Data..................................................... 213 I2C Bus Start/Stop Bits ..................................... 212 Oscillator Start-up Timer................................... 207 Parallel Slave Port ............................................ 210 Power-up Timer ................................................ 207 Reset ................................................................ 207 SPI Mode.......................................................... 211 Timer0 .............................................................. 208 Timer1 .............................................................. 208 Watchdog Timer ............................................... 207 PIC16CR65 Brown-out Reset............................................... 255 Capture/Compare/PWM ................................... 257 CLKOUT and I/O .............................................. 254 External Clock .................................................. 253 I2C Bus Data..................................................... 261 I2C Bus Start/Stop Bits ..................................... 260 Oscillator Start-up Timer................................... 255 Parallel Slave Port ............................................ 258 Power-up Timer ................................................ 255 Reset ................................................................ 255 SPI Mode.......................................................... 259 Timer0 .............................................................. 256 Timer1 .............................................................. 256 USART Synchronous Receive (Master/Slave) .................................................. 262 Watchdog Timer ............................................... 255 Power-up Timer ........................................................ 223 PWM Output ............................................................... 80 RB0/INT Interrupt...................................................... 138 RX Pin Sampling............................................... 110, 111 SPI Master Mode ........................................................ 93 SPI Mode, Master/Slave Mode, No SS Control............................................................. 88 SPI Mode, Slave Mode With SS Control .................... 88 SPI Slave Mode (CKE = 1) ......................................... 94 SPI Slave Mode Timing (CKE = 0) ............................. 93 Timer0 with External Clock......................................... 67 TMR0 Interrupt Timing................................................ 66 USART Asynchronous Master Transmission ........... 113 USART Asynchronous Master Transmission (Back to Back) .......................................................... 113 USART Asynchronous Reception............................. 114 USART Synchronous Reception in Master Mode............................................................. 119 USART Synchronous Tranmission ........................... 117 Wake-up from SLEEP Through Interrupts ................ 142  1997-2013 Microchip Technology Inc. PIC16C6X TMR0 .................................................... 24, 26, 28, 30, 32, 34 TMR0 Clock Source Select bit, T0CS ................................. 36 TMR0 Interrupt .................................................................... 65 TMR0 Overflow Interrupt Enable bit, T0IE .......................... 37 TMR0 Overflow Interrupt Flag bit, T0IF .............................. 37 TMR0 Prescale Selection Table ......................................... 36 TMR0 Source Edge Select bit, T0SE.................................. 36 TMR1 Overflow Interrupt Enable bit, TMR1IE .................... 38 TMR1 Overflow Interrupt Flag bit, TMR1IF ......................... 41 TMR1CS ............................................................................. 71 TMR1H.................................................. 24, 26, 28, 30, 32, 34 TMR1IE ............................................................................... 38 TMR1IF ............................................................................... 41 TMR1L .................................................. 24, 26, 28, 30, 32, 34 TMR1ON ............................................................................. 71 TMR2 .................................................... 24, 26, 28, 30, 32, 34 TMR2 Register .................................................................... 75 TMR2 to PR2 Match Interrupt Enable bit, TMR2IE ............. 38 TMR2 to PR2 Match Interrupt Flag bit, TMR2IF ................. 41 TMR2IE ............................................................................... 38 TMR2IF ............................................................................... 41 TMR2ON ............................................................................. 75 TO ............................................................................... 35, 131 TOUTPS3:TOUTPS0 .......................................................... 75 Transmit Enable bit, TXEN ............................................... 105 Transmit Shift Register Status bit, TRMT ......................... 105 Transmit Status and Control Register ............................... 105 TRISA ............................................. 25, 27, 29, 31, 33, 34, 51 TRISB ............................................. 25, 27, 29, 31, 33, 34, 53 TRISC ....................................... 25, 27, 29, 31, 33, 34, 55, 94 TRISD ............................................. 25, 27, 29, 31, 33, 34, 57 TRISE ............................................. 25, 27, 29, 31, 33, 34, 58 TRMT ................................................................................ 105 TX9 ................................................................................... 105 TX9D ................................................................................. 105 TXEN ................................................................................ 105 TXIE .................................................................................... 39 TXIF .................................................................................... 42 TXREG.................................................. 24, 26, 28, 30, 32, 34 TXSTA .......................................... 25, 27, 29, 31, 33, 34, 105 Synchronous Slave Mode Reception ......................................................... 120 Section ............................................................. 120 Setting Up Reception........................................ 120 Setting Up Transmission .................................. 120 Transmit............................................................ 120 Transmit Block Diagram ........................................... 112 Update Address bit, UA ................................................ 84, 89 USART Receive Interrupt Enable bit, RCIE........................ 39 USART Receive Interrupt Flag bit, RCIF............................ 42 USART Transmit Interrupt Enable bit, TXIE ....................... 39 USART Transmit Interrupt Flag bit, TXIF............................ 42 UV Erasable Devices............................................................ 7 W Wake-up from Sleep ......................................................... 141 Wake-up on Key Depression .............................................. 53 Wake-up Using Interrupts................................................. 141 Watchdog Timer (WDT) Block Diagram .......................................................... 140 Period ....................................................................... 140 Programming Considerations ................................... 140 Section...................................................................... 140 WCOL........................................................................... 85, 90 Weak Internal Pull-ups........................................................ 53 Write Collision Detect bit, WCOL.................................. 85, 90 X XMIT_MODE .................................................................... 104 XT ..................................................................................... 130 Z Z ......................................................................................... 35 Zero bit ........................................................................... 9, 35 U UA ................................................................................. 84, 89 Universal Synchronous Asynchronous Receiver Transmitter (USART) Asynchronous Mode Setting Up Transmission................................... 113 Timing Diagram, Master Transmission ............. 113 Transmitter........................................................ 112 Asynchronous Receiver Setting Up Reception ........................................ 115 Timing Diagram ................................................ 114 Asynchronous Receiver Mode Block Diagram .................................................. 114 Section .............................................................. 114 Section ...................................................................... 105 Synchronous Master Mode Reception.......................................................... 118 Section .............................................................. 116 Setting Up Reception ........................................ 118 Setting Up Transmission................................... 116 Timing Diagram, Reception .............................. 119 Timing Diagram, Transmission ......................... 117 Transmission .................................................... 116  1997-2013 Microchip Technology Inc. DS30234E-page 321 PIC16C6X LIST OF EQUATION AND EXAMPLES Figure 4-15: Example 3-1: Instruction Pipeline Flow ............................. 18 Example 4-1: Call of a Subroutine in Page 1 from Page 0 ................................................ 49 Example 4-2: Indirect Addressing ..................................... 49 Example 5-1: Initializing PORTA....................................... 51 Example 5-2: Initializing PORTB....................................... 53 Example 5-3: Initializing PORTC ...................................... 55 Example 5-4: Read-Modify-Write Instructions on an I/O Port ....................................................... 60 Example 7-1: Changing Prescaler (Timer0WDT) .......... 69 Example 7-2: Changing Prescaler (WDTTimer0) .......... 69 Example 8-1: Reading a 16-bit Free-running Timer ..................................... 73 Example 10-1: Changing Between Capture Prescalers ..................................... 79 Example 10-2: PWM Period and Duty Cycle Calculation ........................................ 81 Example 11-1: Loading the SSPBUF (SSPSR) Register ....................................... 86 Example 11-2: Loading the SSPBUF (SSPSR) Register (PIC16C66/67) .............. 91 Example 12-1: Calculating Baud Rate Error ..................... 107 Example 13-1: Saving Status and W Registers in RAM ...................................... 139 Example 13-2: Saving Status, W, and PCLATH Registers in RAM (All other PIC16C6X devices) ................... 139 Figure 4-16: Figure 4-17: Figure 4-18: Figure 4-19: Figure 4-20: Figure 4-21: Figure 4-22: Figure 4-23: Figure 4-24: Figure 4-25: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: LIST OF FIGURES Figure 5-8: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 4-13: Figure 4-14: PIC16C61 Block Diagram ........................... 10 PIC16C62/62A/R62/64/64A/R64 Block Diagram ............................................ 11 PIC16C63/R63/65/65A/R65 Block Diagram ............................................ 12 PIC16C66/67 Block Diagram ...................... 13 Clock/Instruction Cycle ............................... 18 PIC16C61 Program Memory Map and Stack .................................................... 19 PIC16C62/62A/R62/64/64A/ R64 Program Memory Map and Stack ....... 19 PIC16C63/R63/65/65A/R65 Program Memory Map and Stack .............................. 19 PIC16C66/67 Program Memory Map and Stack ............................................ 20 PIC16C61 Register File Map ...................... 20 PIC16C62/62A/R62/64/64A/ R64 Register File Map ................................ 21 PIC16C63/R63/65/65A/R65 Register File Map........................................ 21 PIC16C66/67 Data Memory Map................ 22 STATUS Register (Address 03h, 83h, 103h, 183h) ................. 35 OPTION Register (Address 81h, 181h) ................................... 36 INTCON Register (Address 0Bh, 8Bh, 10Bh 18Bh)................. 37 PIE1 Register for PIC16C62/62A/R62 (Address 8Ch)............................................. 38 PIE1 Register for PIC16C63/R63/66 (Address 8Ch)............................................. 39 PIE1 Register for PIC16C64/64A/R64 (Address 8Ch)............................................. 39 DS30234E-page 322 Figure 5-9: Figure 5-10: Figure 5-11: Figure 5-12: Figure 5-13: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 8-1: Figure 8-2: Figure 9-1: Figure 9-2: Figure 10-1: Figure 10-2: Figure 10-3: Figure 10-4: Figure 10-5: Figure 11-1: PIE1 Register for PIC16C65/65A/R65/67 (Address 8Ch) ............................................ 40 PIR1 Register for PIC16C62/62A/R62 (Address 0Ch) ............................................ 41 PIR1 Register for PIC16C63/R63/66 Address 0Ch).............................................. 42 PIR1 Register for PIC16C64/64A/R64 (Address 0Ch) ............................................ 43 PIR1 Register for PIC16C65/65A/R65/67 (Address 0Ch) ............................................ 44 PIE2 Register (Address 8Dh) ..................... 45 PIR2 Register (Address 0Dh) ..................... 46 PCON Register for PIC16C62/64/65 (Address 8Eh)............................................. 47 PCON Register for PIC16C62A/R62/63/ R63/64A/R64/65A/R65/66/67 (Address 8Eh)............................................. 47 Loading of PC in Different Situations.......... 48 Direct/Indirect Addressing .......................... 49 Block Diagram of the RA3:RA0 Pins and the RA5 Pin ................. 51 Block Diagram of the RA4/T0CKI Pin......... 51 Block Diagram of the RB7:RB4 Pins for PIC16C61/62/64/65....... 53 Block Diagram of the RB7:RB4 Pins for PIC16C62A/63/R63/ 64A/65A/R65/66/67 .................................... 54 Block Diagram of the RB3:RB0 Pins............................................. 54 PORTC Block Diagram............................... 55 PORTD Block Diagram (In I/O Port Mode)....................................... 57 PORTE Block Diagram (In I/O Port Mode)...................................... 58 TRISE Register (Address 89h) ................... 58 Successive I/O Operation........................... 60 PORTD and PORTE as a Parallel Slave Port ................................................... 61 Parallel Slave Port Write Waveforms ......... 62 Parallel Slave Port Read Waveforms ......... 62 Timer0 Block Diagram ................................ 65 Timer0 Timing: Internal Clock/No Prescaler .................................................... 65 Timer0 Timing: Internal Clock/Prescale 1:2...................................... 66 TMR0 Interrupt Timing................................ 66 Timer0 Timing With External Clock ............ 67 Block Diagram of the Timer0/WDT Prescaler .................................................... 68 T1CON: Timer1 Control Register (Address 10h) ............................................. 71 Timer1 Block Diagram ................................ 72 Timer2 Block Diagram ................................ 75 T2CON: Timer2 Control Register (Address 12h) ............................................. 75 CCP1CON Register (Address 17h) / CCP2CON Register (Address 1Dh) ........... 78 Capture Mode Operation Block Diagram ............................................ 78 Compare Mode Operation Block Diagram ............................................ 79 Simplified PWM Block Diagram.................. 80 PWM Output............................................... 80 SSPSTAT: Sync Serial Port Status Register (Address 94h)............................... 84  1997-2013 Microchip Technology Inc. PIC16C6X Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 11-8: Figure 11-9: Figure 11-10: Figure 11-11: Figure 11-12: Figure 11-13: Figure 11-14: Figure 11-15: Figure 11-16: Figure 11-17: Figure 11-18: Figure 11-19: Figure 11-20: Figure 11-21: Figure 11-22: Figure 11-23: Figure 11-24: Figure 11-25: Figure 11-26: Figure 11-27: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8: Figure 12-9: Figure 12-10: Figure 12-11: Figure 12-12: Figure 12-13: Figure 12-14: Figure 13-1: SSPCON: Sync Serial Port Control Register (Address 14h) .................. 85 SSP Block Diagram (SPI Mode) ................. 86 SPI Master/Slave Connection..................... 87 SPI Mode Timing, Master Mode or Slave Mode w/o SS Control........................ 88 SPI Mode Timing, Slave Mode with SS Control .................................................. 88 SSPSTAT: Sync Serial Port Status Register (Address 94h)(PIC16C66/67)....... 89 SSPCON: Sync Serial Port Control Register (Address 14h)(PIC16C66/67)....... 90 SSP Block Diagram (SPI Mode) (PIC16C66/67)............................................ 91 SPI Master/Slave Connection (PIC16C66/67)............................................ 92 SPI Mode Timing, Master Mode (PIC16C66/67)............................................ 93 SPI Mode Timing (Slave Mode With CKE = 0) (PIC16C66/67) ............................ 93 SPI Mode Timing (Slave Mode With CKE = 1) (PIC16C66/67) ............................ 94 Start and Stop Conditions........................... 95 7-bit Address Format .................................. 96 I2C 10-bit Address Format .......................... 96 Slave-receiver Acknowledge ...................... 96 Data Transfer Wait State ............................ 96 Master-transmitter Sequence ..................... 97 Master-receiver Sequence.......................... 97 Combined Format ....................................... 97 Multi-master Arbitration (Two Masters)............................................. 98 Clock Synchronization ................................ 98 SSP Block Diagram (I2C Mode).................. 99 I2C Waveforms for Reception (7-bit Address) .......................................... 101 I2C Waveforms for Transmission (7-bit Address) .......................................... 102 Operation of the I2C Module in IDLE_MODE, RCV_MODE or XMIT_MODE ............................................ 104 TXSTA: Transmit Status and Control Register (Address 98h) ................ 105 RCSTA: Receive Status and Control Register (Address 18h) ................ 106 RX Pin Sampling Scheme (BRGH = 0) PIC16C63/R63/65/65A/R65) .................... 110 RX Pin Sampling Scheme (BRGH = 1) (PIC16C63/R63/65/65A/R65) ................... 110 RX Pin Sampling Scheme (BRGH = 1) (PIC16C63/R63/65/65A/R65) ................... 110 RX Pin Sampling Scheme (BRGH = 0 or = 1) (PIC16C66/67).......................................... 111 USART Transmit Block Diagram .............. 112 Asynchronous Master Transmission......... 113 Asynchronous Master Transmission (Back to Back) .......................................... 113 USART Receive Block Diagram ............... 114 Asynchronous Reception.......................... 114 Synchronous Transmission ...................... 117 Synchronous Transmission through TXEN ........................................... 117 Synchronous Reception (Master Mode, SREN) .............................. 119 Configuration Word for PIC16C61 ............ 123  1997-2013 Microchip Technology Inc. Figure 13-2: Figure 13-3: Figure 13-4: Figure 13-5: Figure 13-6: Figure 13-7: Figure 13-8: Figure 13-9: Figure 13-10: Figure 13-11: Figure 13-12: Figure 13-13: Figure 13-14: Figure 13-15: Figure 13-16: Figure 13-17: Figure 13-18: Figure 13-19: Figure 13-20: Figure 13-21: Figure 13-22: Figure 13-23: Figure 14-1: Figure 16-1: Figure 16-2: Figure 16-3: Figure 16-4: Figure 16-5: Figure 17-1: Figure 17-2: Figure 17-3: Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 17-8: Figure 17-9: Configuration Word for PIC16C62/64/65....................................... 124 Configuration Word for PIC16C62A/R62/63/R63/64A/R64/ 65A/R65/66/67 ......................................... 124 Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration)........... 125 External Clock Input Operation (HS, XT or LP OSC Configuration)........... 125 External Parallel Resonant Crystal Oscillator Circuit ........................... 127 External Series Resonant Crystal Oscillator Circuit ........................... 127 RC Oscillator Mode .................................. 127 Simplified Block Diagram of On-chip Reset Circuit ............................... 128 Brown-out Situations ................................ 129 Time-out Sequence on Power-up (MCLR not Tied to VDD): Case 1 .............. 134 Time-out Sequence on Power-up (MCLR Not Tied To VDD): Case 2 ............ 134 Time-out Sequence on Power-up (MCLR Tied to VDD) ................................. 134 External Power-on Reset Circuit (For Slow VDD Power-up) ......................... 135 External Brown-out Protection Circuit 1 ................................... 135 External Brown-out Protection Circuit 2 ................................... 135 Interrupt Logic for PIC16C61.................... 137 Interrupt Logic for PIC16C6X ................... 137 INT Pin Interrupt Timing ........................... 138 Watchdog Timer Block Diagram............... 140 Summary of Watchdog Timer Registers ........................................ 140 Wake-up from Sleep Through Interrupt...................................... 142 Typical In-circuit Serial Programming Connection......................... 142 General Format for Instructions................ 143 Load Conditions for Device Timing Specifications ........................................... 168 External Clock Timing .............................. 169 CLKOUT and I/O Timing .......................... 170 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing....................................................... 171 Timer0 External Clock Timings ................ 172 Typical RC Oscillator Frequency vs. Temperature .................... 173 Typical RC Oscillator Frequency vs. VDD ................................... 174 Typical RC Oscillator Frequency vs. VDD ................................... 174 Typical RC Oscillator Frequency vs. VDD ................................... 174 Typical IPD vs. VDD Watchdog Timer Disabled 25C .......................................... 174 Typical IPD vs. VDD Watchdog Timer Enabled 25C ........................................... 175 Maximum IPD vs. VDD Watchdog Disabled ................................................... 175 Maximum IPD vs. VDD Watchdog Enabled*................................................... 176 VTH (Input Threshold Voltage) of I/O Pins vs. VDD ....................................... 176 DS30234E-page 323 PIC16C6X Figure 17-10: VIH, VIL of MCLR, T0CKI and OSC1 (in RC Mode) vs. VDD ............................... 177 Figure 17-11: VTH (Input Threshold Voltage) of OSC1 Input (in XT, HS, and LP Modes) vs. VDD ............................ 177 Figure 17-12: Typical IDD vs. Frequency (External Clock, 25C) .............................. 178 Figure 17-13: Maximum IDD vs. Frequency (External Clock, -40 to +85C)................. 178 Figure 17-14: Maximum IDD vs. Frequency (External Clock, -55 to +125C)............... 179 Figure 17-15: WDT Timer Time-out Period vs. VDD ........ 179 Figure 17-16: Transconductance (gm) of HS Oscillator vs. VDD ...................................... 179 Figure 17-17: Transconductance (gm) of LP Oscillator vs. VDD ...................................... 180 Figure 17-18: Transconductance (gm) of XT Oscillator vs. VDD ...................................... 180 Figure 17-19: IOH vs. VOH, VDD = 3V .............................. 180 Figure 17-20: IOH vs. VOH, VDD = 5V .............................. 180 Figure 17-21: IOL vs. VOL, VDD = 3V ............................... 181 Figure 17-22: IOL vs. VOL, VDD = 5V ............................... 181 Figure 18-1: Load Conditions for Device Timing Specifications ................................ 188 Figure 18-2: External Clock Timing ............................... 189 Figure 18-3: CLKOUT and I/O Timing........................... 190 Figure 18-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ............................ 191 Figure 18-5: Timer0 and Timer1 External Clock Timings ........................................... 192 Figure 18-6: Capture/Compare/PWM Timings (CCP1) ...................................................... 193 Figure 18-7: Parallel Slave Port Timing (PIC16C64) ............................................... 194 Figure 18-8: SPI Mode Timing ...................................... 195 Figure 18-9: I2C Bus Start/Stop Bits Timing.................. 196 Figure 18-10: I2C Bus Data Timing ................................. 197 Figure 19-1: Load Conditions for Device Timing Specifications ................................ 204 Figure 19-2: External Clock Timing ............................... 205 Figure 19-3: CLKOUT and I/O Timing........................... 206 Figure 19-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ............................ 207 Figure 19-5: Brown-out Reset Timing ........................... 207 Figure 19-6: Timer0 and Timer1 External Clock Timings ........................................... 208 Figure 19-7: Capture/Compare/PWM Timings (CCP1) ...................................................... 209 Figure 19-8: Parallel Slave Port Timing (PIC16C64A/R64)..................................... 210 Figure 19-9: SPI Mode Timing ...................................... 211 Figure 19-10: I2C Bus Start/Stop Bits Timing.................. 212 Figure 19-11: I2C Bus Data Timing ................................. 213 Figure 20-1: Load Conditions for Device Timing Specifications............................................ 220 Figure 20-2: External Clock Timing ............................... 221 Figure 20-3: CLKOUT and I/O Timing........................... 222 Figure 20-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ....................................................... 223 Figure 20-5: Timer0 and Timer1 External Clock Timings ..................................................... 224 Figure 20-6: Capture/Compare/PWM Timings (CCP1 and CCP2) .................................... 225 DS30234E-page 324 Figure 20-7: Figure 20-8: Figure 20-9: Figure 20-10: Figure 20-11: Figure 20-12: Figure 21-1: Figure 21-2: Figure 21-3: Figure 21-4: Figure 21-5: Figure 21-6: Figure 21-7: Figure 21-8: Figure 21-9: Figure 21-10: Figure 21-11: Figure 21-12: Figure 21-13: Figure 22-1: Figure 22-2: Figure 22-3: Figure 22-4: Figure 22-5: Figure 22-6: Figure 22-7: Figure 22-8: Figure 22-9: Figure 22-10: Figure 22-11: Figure 22-12: Figure 22-13: Figure 23-1: Figure 23-2: Figure 23-3: Figure 23-4: Figure 23-5: Figure 23-6: Figure 23-7: Figure 23-8: Figure 23-9: Figure 23-10: Figure 23-11: Parallel Slave Port Timing ........................ 226 SPI Mode Timing ...................................... 227 I2C Bus Start/Stop Bits Timing ................. 228 I2C Bus Data Timing................................. 229 USART Synchronous Transmission (Master/Slave) Timing .............................. 230 USART Synchronous Receive (Master/Slave) Timing .............................. 230 Load Conditions for Device Timing Specifications ........................................... 236 External Clock Timing............................... 237 CLKOUT and I/O Timing .......................... 238 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing....................................................... 239 Brown-out Reset Timing ........................... 239 Timer0 and Timer1 External Clock Timings ..................................................... 240 Capture/Compare/PWM Timings (CCP1 and CCP2)................................... 241 Parallel Slave Port Timing (PIC16C65A) ............................................ 242 SPI Mode Timing ...................................... 243 I2C Bus Start/Stop Bits Timing ................. 244 I2C Bus Data Timing................................. 245 USART Synchronous Transmission (Master/Slave) Timing .............................. 246 USART Synchronous Receive (Master/Slave) Timing .............................. 246 Load Conditions for Device Timing Specifications ........................................... 252 External Clock Timing............................... 253 CLKOUT and I/O Timing .......................... 254 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing....................................................... 255 Brown-out Reset Timing ........................... 255 Timer0 and Timer1 External Clock Timings ..................................................... 256 Capture/Compare/PWM Timings (CCP1 and CCP2).................................... 257 Parallel Slave Port Timing (PIC16CR65) ............................................ 258 SPI Mode Timing ...................................... 259 I2C Bus Start/Stop Bits Timing ................. 260 I2C Bus Data Timing................................. 261 USART Synchronous Transmission (Master/Slave) Timing .............................. 262 USART Synchronous Receive (Master/Slave) Timing .............................. 262 Load Conditions for Device Timing Specifications ........................................... 268 External Clock Timing............................... 269 CLKOUT and I/O Timing .......................... 270 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing....................................................... 271 Brown-out Reset Timing ........................... 271 Timer0 and Timer1 External Clock Timings ..................................................... 272 Capture/Compare/PWM Timings (CCP1 and CCP2).................................... 273 Parallel Slave Port Timing (PIC16C67) .... 274 SPI Master Mode Timing (CKE = 0) ......... 275 SPI Master Mode Timing (CKE = 1) ......... 275 SPI Slave Mode Timing (CKE = 0) ........... 276  1997-2013 Microchip Technology Inc. PIC16C6X Figure 23-12: Figure 23-13: Figure 23-14: Figure 23-15: Figure 23-16: Figure 24-1: Figure 24-2: Figure 24-3: Figure 24-4: Figure 24-5: Figure 24-6: Figure 24-7: Figure 24-8: Figure 24-9: Figure 24-10: Figure 24-11: Figure 24-12: Figure 24-13: Figure 24-14: Figure 24-15: Figure 24-16: Figure 24-17: Figure 24-18: Figure 24-19: Figure 24-20: Figure 24-21: Figure 24-22: Figure 24-23: Figure 24-24: Figure 24-25: Figure 24-26: Figure 24-27: Figure 24-28: SPI Slave Mode Timing (CKE = 1) ........... 276 I2C Bus Start/Stop Bits Timing.................. 278 I2C Bus Data Timing ................................. 279 USART Synchronous Transmission (Master/Slave) Timing............................... 280 USART Synchronous Receive (Master/Slave) Timing............................... 280 Typical IPD vs. VDD (WDT Disabled, RC Mode) ....................... 281 Maximum IPD vs. VDD (WDT Disabled, RC Mode) ....................... 281 Typical IPD vs. VDD @ 25C (WDT Enabled, RC Mode)........................ 282 Maximum IPD vs. VDD (WDT Enabled, RC Mode)........................ 282 Typical RC Oscillator Frequency vs. VDD .................................... 282 Typical RC Oscillator Frequency vs. VDD .................................... 282 Typical RC Oscillator Frequency vs. VDD .................................... 282 Typical IPD vs. VDD Brown-out Detect Enabled (RC Mode)....................... 283 Maximum IPD vs. VDD Brown-out Detect Enabled (85C to -40C, RC Mode) ........................ 283 Typical IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, RC Mode) ................................................ 283 Maximum IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C to -40C, RC Mode) ......................... 283 Typical IDD vs. Frequency (RC Mode @ 22 pF, 25°C) ....................... 284 Maximum IDD vs. Frequency (RC Mode @ 22 pF, -40°C to 85°C) ......... 284 Typical IDD vs. Frequency (RC Mode @ 100 pF, 25°C) ..................... 285 Maximum IDD vs. Frequency (RC Mode @ 100 pF, -40°C to 85°C) ....... 285 Typical IDD vs. Frequency (RC Mode @ 300 pF, 25°C) ..................... 286 Maximum IDD vs. Frequency (RC Mode @ 300 pF, -40°C to 85°C) ....... 286 Typical IDD vs. Capacitance @ 500 kHz (RC Mode) ................................................ 287 Transconductance(gm) of HS Oscillator vs. VDD ...................................... 287 Transconductance(gm) of LP Oscillator vs. VDD ...................................... 287 Transconductance(gm) of XT Oscillator vs. VDD ...................................... 287 Typical XTAL Startup Time vs. VDD (LP Mode, 25C) ....................................... 288 Typical XTAL Startup Time vs. VDD (HS Mode, 25C) ...................................... 288 Typical XTAL Startup Time vs. VDD (XT Mode, 25C)....................................... 288 Typical Idd vs. Frequency (LP Mode, 25°C) ....................................... 289 Maximum IDD vs. Frequency (LP Mode, 85°C to -40°C)......................... 289 Typical IDD vs. Frequency (XT Mode, 25°C)....................................... 289 Maximum IDD vs. Frequency (XT Mode, -40°C to 85°C)......................... 289  1997-2013 Microchip Technology Inc. Figure 24-29: Typical IDD vs. Frequency (HS Mode, 25°C) ...................................... 290 Figure 24-30: Maximum IDD vs. Frequency (HS Mode, -40°C to 85°C)........................ 290 DS30234E-page 325 PIC16C6X LIST OF TABLES Table 12-2: Table 1-1: Table 3-1: Table 3-2: Table 12-3: Table 12-4: Table 3-3: Table 4-1: Table 4-2: Table 4-3: Table 4-4: Table 4-5: Table 4-6: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 5-8: Table 5-9: Table 5-10: Table 5-11: Table 5-12: Table 5-13: Table 7-1: Table 8-1: Table 8-2: Table 9-1: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 10-5: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 11-5: Table 12-1: PIC16C6X Family of Devices ....................... 6 PIC16C61 Pinout Description ..................... 14 PIC16C62/62A/R62/63/R63/66 Pinout Description....................................... 15 PIC16C64/64A/R64/65/65A/R65/67 Pinout Description....................................... 16 Special Function Registers for the PIC16C61 ................................................... 23 Special Function Registers for the PIC16C62/62A/R62 .................................... 24 Special Function Registers for the PIC16C63/R63............................................ 26 Special Function Registers for the PIC16C64/64A/R64 .................................... 28 Special Function Registers for the PIC16C65/65A/R65 .................................... 30 Special Function Registers for the PIC16C66/67 .............................................. 32 PORTA Functions ....................................... 52 Registers/Bits Associated with PORTA ....................................................... 52 PORTB Functions ....................................... 54 Summary of Registers Associated with PORTB ....................................................... 54 PORTC Functions for PIC16C62/64 ........... 55 PORTC Functions for PIC16C62A/R62/64A/R64 .......................... 56 PORTC Functions for PIC16C63/R63/65/65A/R65/66/67.............. 56 Summary of Registers Associated with PORTC ....................................................... 56 PORTD Functions....................................... 57 Summary of Registers Associated with PORTD ....................................................... 57 PORTE Functions ....................................... 59 Summary of Registers Associated with PORTE ....................................................... 59 Registers Associated with Parallel Slave Port ...................................... 62 Registers Associated with Timer0 .............. 69 Capacitor Selection for the Timer1 Oscillator......................................... 73 Registers Associated with Timer1 as a Timer/Counter ......................... 74 Registers Associated with Timer2 as a Timer/Counter ......................... 76 CCP Mode - Timer Resource ..................... 77 Interaction of Two CCP Modules ................ 77 Example PWM Frequencies and Resolutions at 20 MHz......................... 81 Registers Associated with Timer1, Capture and Compare ................................ 81 Registers Associated with PWM and Timer2.................................................. 82 Registers Associated with SPI Operation .................................................... 88 Registers Associated with SPI Operation (PIC16C66/67) ........................... 94 I2C Bus Terminology................................... 95 Data Transfer Received Byte Actions ...................................................... 100 Registers Associated with I2C Operation .................................................. 103 Baud Rate Formula................................... 107 DS30234E-page 326 Table 12-5: Table 12-6: Table 12-7: Table 12-8: Table 12-9: Table 12-10: Table 12-11: Table 13-1: Table 13-2: Table 13-3: Table 13-4: Table 13-5: Table 13-6: Table 13-7: Table 13-8: Table 13-9: Table 13-10: Table 13-11: Table 13-12: Table 14-1: Table 14-2: Table 15-1: Table 16-1: Table 16-2: Table 16-3: Table 16-4: Table 16-5: Table 17-1: Table 17-2: Registers Associated with Baud Rate Generator......................................... 107 Baud Rates for Synchronous Mode.......... 108 Baud Rates for Asynchronous Mode (BRGH = 0)............................................... 108 Baud Rates for Asynchronous Mode (BRGH = 1)............................................... 109 Registers Associated with Asynchronous Transmission .................... 113 Registers Associated with Asynchronous Reception.......................... 115 Registers Associated with Synchronous Master Transmission .......... 117 Registers Associated with Synchronous Master Reception ............... 118 Registers Associated with Synchronous Slave Transmission ............ 121 Registers Associated with Synchronous Slave Reception ................. 121 Ceramic Resonators PIC16C61 ............... 126 Ceramic Resonators PIC16C62/62A/R62/63/R63/ 64/64A/R64/65/65A/R65/66/67 ................ 126 Capacitor Selection for Crystal Oscillator for PIC16C61............................ 126 Capacitor Selection for Crystal Oscillator for PIC16C62/62A/R62/63/R63/ 64/64A/R64/65/65A/R65/66/67 ................ 126 Time-out in Various Situations, PIC16C61/62/64/65.................................. 130 Time-out in Various Situations, PIC16C62A/R62/63/R63/ 64A/R64/65A/R65/66/67 .......................... 130 Status Bits and Their Significance, PIC16C61 ................................................. 130 Status bits and Their Significance, PIC16C62/64/65....................................... 130 Status Bits and Their Significance for PIC16C62A/R62/63/R63/ 64A/R64/65A/R65/66/67 .......................... 131 Reset Condition for Special Registers on PIC16C61/62/64/65............. 131 Reset Condition for Special Registers on PIC16C62A/R62/63/R63/ 64A/R64/65A/R65/66/67 .......................... 131 Initialization Conditions for all Registers.............................................. 132 Opcode Field Descriptions ....................... 143 PIC16CXX Instruction Set ........................ 144 Development Tools from Microchip .......... 162 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................. 163 External Clock Timing Requirements ........................................... 169 CLKOUT and I/O Timing Requirements ........................................... 170 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements................. 171 Timer0 External Clock Requirements....... 172 RC Oscillator Frequencies........................ 173 Input Capacitance* ................................... 181  1997-2013 Microchip Technology Inc. PIC16C6X Table 18-1: Table 18-2: Table 18-3: Table 18-4: Table 18-5: Table 18-6: Table 18-7: Table 18-8: Table 18-9: Table 18-10: Table 19-1: Table 19-2: Table 19-3: Table 19-4: Table 19-5: Table 19-6: Table 19-7: Table 19-8: Table 19-9: Table 19-10: Table 20-1: Table 20-2: Table 20-3: Table 20-4: Table 20-5: Table 20-6: Table 20-7: Table 20-8: Table 20-9: Table 20-10: Table 20-11: Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................. 183 External Clock Timing Requirements ........................................... 189 CLKOUT and I/O Timing Requirements ........................................... 190 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements................. 191 Timer0 and Timer1 External Clock Requirements ................................. 192 Capture/Compare/PWM Requirements (CCP1) .............................. 193 Parallel Slave Port Requirements (PIC16C64) 194 SPI Mode Requirements........................... 195 I2C Bus Start/Stop Bits Requirements ........................................... 196 I2C Bus Data Requirements ..................... 197 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................. 199 External Clock Timing Requirements ........................................... 205 CLKOUT and I/O Timing Requirements ........................................... 206 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements ................................. 207 Timer0 and Timer1 External Clock Requirements ................................. 208 Capture/Compare/PWM Requirements (CCP1) .............................. 209 Parallel Slave Port Requirements (PIC16C64A/R64)..................................... 210 SPI Mode Requirements........................... 211 I2C Bus Start/Stop Bits Requirements ........................................... 212 I2C Bus Data Requirements ..................... 213 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................. 215 External Clock Timing Requirements ........................................... 221 CLKOUT and I/O Timing Requirements ........................................... 222 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements................. 223 Timer0 and Timer1 External Clock Requirements ................................. 224 Capture/Compare/PWM Requirements (CCP1 and CCP2)............. 225 Parallel Slave Port Requirements............. 226 SPI Mode Requirements........................... 227 I2C Bus Start/Stop Bits Requirements ........................................... 228 i2C Bus Data Requirements...................... 229 USART Synchronous Transmission Requirements ........................................... 230  1997-2013 Microchip Technology Inc. Table 20-12: Table 21-1: Table 21-2: Table 21-3: Table 21-4: Table 21-5: Table 21-6: Table 21-7: Table 21-8: Table 21-9: Table 21-10: Table 21-11: Table 21-12: Table 22-1: Table 22-2: Table 22-3: Table 22-4: Table 22-5: Table 22-6: Table 22-7: Table 22-8: Table 22-9: Table 22-10: Table 22-11: Table 22-12: Table 23-1: Table 23-2: Table 23-3: Table 23-4: USART Synchronous Receive Requirements ........................................... 230 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................. 231 External Clock Timing Requirements ........................................... 237 CLKOUT and I/O Timing Requirements ........................................... 238 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements ............... 239 Timer0 and Timer1 External Clock Requirements ................................. 240 Capture/Compare/PWM Requirements (CCP1 and CCP2) ............ 241 Parallel Slave Port Requirements (PIC16C65A) ............................................ 242 SPI Mode Requirements .......................... 243 I2C Bus Start/Stop Bits Requirements ........................................... 244 I2C Bus Data Requirements ..................... 245 USART Synchronous Transmission Requirements..................... 246 USART Synchronous Receive Requirements .......................................... 246 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................. 247 External Clock Timing Requirements ........................................... 253 CLKOUT and I/O Timing Requirements ........................................... 254 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements................................. 255 Timer0 and Timer1 External Clock Requirements ................................. 256 Capture/Compare/PWM Requirements (CCP1 and CCP2) ............ 257 Parallel Slave Port Requirements (PIC16CR65)............................................ 258 SPI Mode Requirements .......................... 259 I2C Bus Start/Stop Bits Requirements ........................................... 260 I2C Bus Data Requirements ..................... 261 USART Synchronous Transmission Requirements ........................................... 262 USART Synchronous Receive Requirements .......................................... 262 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices) .............................. 263 External Clock Timing Requirements ........................................... 269 CLKOUT and I/O Timing Requirements ........................................... 270 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements................................. 271 DS30234E-page 327 PIC16C6X Table 23-5: Table 23-6: Table 23-7: Table 23-8: Table 23-9: Table 23-10: Table 23-11: Table 23-12: Table 24-1: Table 24-2: Table E-1: Timer0 and Timer1 External Clock Requirements ................................. 272 Capture/Compare/PWM Requirements (CCP1 and CCP2) ............. 273 Parallel Slave Port Requirements (PIC16C67) 274 SPI Mode Requirements........................... 277 I2C Bus Start/Stop Bits Requirements ........................................... 278 I2C Bus Data Requirements ..................... 279 USART Synchronous Transmission Requirements ........................................... 280 USART Synchronous Receive Requirements ........................................... 280 RC Oscillator Frequencies ........................ 287 Capacitor Selection for Crystal Oscillators ................................................. 288 Pin Compatible Devices............................ 315 DS30234E-page 328  1997-2013 Microchip Technology Inc. PIC16C6X ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how Microchip products provide project solutions. The web site, like the BBS, is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products Connecting to the Microchip BBS Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications network. Internet: You can telnet or ftp to the Microchip BBS at the address: mchipbbs.microchip.com CompuServe Communications Network: When using the BBS via the Compuserve Network, in most cases, a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore you do not need CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS.  1997-2013 Microchip Technology Inc. The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem. CompuServe service allow multiple users various baud rates depending on the local point of access. The following connect procedure applies in most locations. 1. Set your modem to 8-bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. 2. Dial your local CompuServe access number. 3. Depress the key and a garbage string will appear because CompuServe is expecting a 7E1 setting. 4. Type +, depress the key and “Host Name:” will appear. 5. Type MCHIPBBS, depress the key and you will be connected to the Microchip BBS. In the United States, to find the CompuServe phone number closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. After the system responds with “Host Name:”, type NETWORK, depress the key and follow CompuServe's directions. For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe number. Microchip regularly uses the Microchip BBS to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for Microchip systems software products. For each SIG, a moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files are accepted from the user community in general to limit the spread of computer viruses. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world. 970301 Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB, are trademarks and SQTP is a service mark of Microchip in the U.S.A. fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated. All other trademarks mentioned herein are the property of their respective companies. DS30234E-page 329 PIC16C6X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C6X Y N Literature Number: DS30234E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30234E-page 330  1997-2013 Microchip Technology Inc. PIC16C6X PIC16C6X Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO. -XX X /XX XXX Pattern: 3-Digit Pattern Code for QTP (blank otherwise) Package: L SP P SO PQ TQ JW* SS = = = = = = = = PLCC Skinny DIP PDIP SOIC (Gull Wing, 300 mil body) MQFP (Metric PQFP) TQFP Windowed CERDIP Shrink SOIC (Gull Wing, 300 mil body) Temperature Range: I E = = = 0°C to +70°C (T for tape/reel) – 40°C to +85°C (S for tape/reel) – 40°C to +125°C Frequency Range: 04 04 10 20 = = = = 200 kHz (PIC16C6X-04) 4 MHz 10 MHz 20 MHz Device: PIC16C6X :VDD range 4.0V to 6.0V PIC16C6XT :VDD range 4.0V to 6.0V (Tape and Reel) PIC16LC6X :VDD range 2.5V to 6.0V PIC16LC6XT :VDD range 2.5V to 6.0V (Tape and Reel) PIC16CR6X :VDD range 4.0V to 6.0V PIC16CR6XT :VDD range 4.0V to 6.0V (Tape and Reel) PIC16LCR6X :VDD range 2.5V to 6.0V PIC16LCR6XT:VDD range 2.5V to 6.0V Examples: a)PIC16C62A - 04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301 b)PIC16LC65A - 04I/PQ = Industrial temp., MQFP package, 4 MHz, extended VDD limits c)PIC16C67 - 10E/P = Extended temp., PDIP package, 10 MHz, normal VDD limits * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. The Microchip Website at www.microchip.com 2. Your local Microchip sales office (see following page)  1997-2013 Microchip Technology Inc. DS30234E-page 331 PIC16C6X DS30234E-page 332  1997-2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1997-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769652 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  1997-2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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