PIC16C64X & PIC16C66X
8-Bit EPROM Microcontrollers with Analog Comparators
Devices included in this data sheet:
•
•
•
•
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
PIC16C641
PIC16C642
PIC16C661
PIC16C662
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Device
Data
Memory x8
PIC16C641
2K
128
PIC16C642
4K
176
PIC16C661
2K
128
PIC16C662
4K
176
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative addressing modes
Peripheral Features:
• Up to 33 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
1996 Microchip Technology Inc.
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5
RC4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
RA5
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
RC1
RC2
RC3
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16C66X
Program
Memory x14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16C64X
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
RA5
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
RC1
RC2
RC3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
• Four user programmable ID locations
• Program Memory Parity Error checking circuitry
with Parity Error Reset (PER)
• CMOS Technology:
• Low-power, high-speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range: 3.0V to 6.0V
• Commercial, Industrial and Automotive
temperature ranges
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 1
PIC16C64X & PIC16C66X
Pin Diagrams (Cont.’d)
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
RC2
RC1
NC
TQFP
44 43 42 41 40 39 38 37 36 35 34
RC7
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
11
PIC16C66X
33
32
31
30
29
28
27
26
25
24
23
NC
RC0
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5
RA4/T0CKI
12 1314 15 16 17 1819 20 21 22
RA3/AN3
RA2/AN2/VREF
RA1/AN1
RA0/AN0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC
RA3/AN3
RA2/AN2/VREF
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
PLCC
RA4/T0CKI
RA5
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
NC
6 5 4 3 2 1 44 43 42 4140
39
38
37
36
35
34
33
32
31
30
16
29
17
18 19 20 21 2223 24 2526 27 28
7
8
9
10
11
12
13
14
15
PIC16C66X
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
NC
RC6
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
RC2
RC1
DS30559A-page 2
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Table of Contents
1.0
General Description .......................................................................................................................................... 5
2.0
PIC16C64X & PIC16C66X Device Varieties .................................................................................................... 7
3.0
Architectural Overview...................................................................................................................................... 9
4.0
Memory Organization ..................................................................................................................................... 17
5.0
I/O Ports.......................................................................................................................................................... 29
6.0
Timer0 Module................................................................................................................................................ 41
7.0
Comparator Module ........................................................................................................................................ 47
8.0
Voltage Reference Module ............................................................................................................................. 53
9.0
Special Features of the CPU .......................................................................................................................... 55
10.0
Instruction Set Summary ................................................................................................................................ 73
11.0
Development Support ..................................................................................................................................... 87
12.0
Electrical Specifications .................................................................................................................................. 91
13.0
Device Characterization Information............................................................................................................. 103
14.0
Packaging Information .................................................................................................................................. 105
Appendix A: Enhancements...................................................................................................................................... 115
Appendix B: Compatibility ......................................................................................................................................... 115
Appendix C: What’s New .......................................................................................................................................... 116
Appendix D: What’s Changed ................................................................................................................................... 116
Appendix E: PIC16/17 Microcontrollers ..................................................................................................................... 117
Pin Compatibility ......................................................................................................................................................... 125
Index ........................................................................................................................................................................... 127
List of Examples.......................................................................................................................................................... 129
List of Figures.............................................................................................................................................................. 129
List of Tables............................................................................................................................................................... 130
On-Line Support.......................................................................................................................................................... 131
Reader Response ....................................................................................................................................................... 132
PIC16C64X & PIC16C66X Product Identification System .......................................................................................... 135
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 3
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 4
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
1.0
GENERAL DESCRIPTION
PIC16C64X & PIC16C66X devices are 28-pin and
40-pin EPROM-based members of the versatile
PIC16CXXX family of low-cost, high-performance,
CMOS, fully-static, 8-bit microcontrollers.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXXX family has
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single-cycle, except for program branches (which require
two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.
PIC16CXXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in its class.
The PIC16C641 has 128 bytes of RAM and the
PIC16C642 has 176 bytes of RAM. Both devices have
22 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, they have two analog
comparators with a programmable on-chip voltage reference module. Program Memory has internal parity
error detection circuitry with a Parity Error Reset. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc.).
The PIC16C661 has 128 bytes of RAM and the
PIC16C662 has 176 bytes of RAM. Both devices have
33 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. They also have an 8-bit Parallel
Slave Port. In addition, the devices have two analog
comparators with a programmable on-chip voltage reference module. Program Memory has internal parity
error detection circuitry with a Parity Error Reset. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc.).
A highly reliable Watchdog Timer (WDT) with its own
on-chip RC oscillator provides protection against software lock-up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
The PIC16CXXX series fit perfectly in applications
ranging from battery chargers to low-power remote
sensors.
The
EPROM
technology
makes
customization of application programs (detection
levels, pulse generation, timers, etc.) extremely fast
and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low-cost, low-power,
high-performance, ease of use, and I/O flexibility make
the PIC16C64X & PIC16C66X very versatile.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to the
PIC16C64X & PIC16C66X (Appendix B).
1.2
Development Support
PIC16C64X & PIC16C66X devices are supported by
the complete line of Microchip Development tools,
including:
• MPLAB Integrated Development Environment
including MPLAB-Simulator.
• MPASM Universal Assembler and MPLAB-C Universal C compiler.
• PRO MATE II and PICSTART Plus device programmers.
• PICMASTER In-circuit Emulator System
• fuzzyTECH-MP Fuzzy Logic Development Tools
• DriveWay Visual Programming Tool
Please refer to Section 11.0 for more details about
these and other Microchip development tools.
PIC16CXXX devices have special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and resets.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 5
DS30559A-page 6
Preliminary
4K
2K
20
20
20
PIC16C642
PIC16C661
PIC16C662
E
M
176
128
176
128
O
PR
Da
o
ta
Pr
Ti
TMR0
TMR0
TMR0
TMR0
er
m
(b
2
2
2
2
M
Yes
Yes
Yes
Yes
m
Co
t
In
al
Yes
Pa
l
le
5
5
4
4
l
ra
t
In
33
33
22
22
3.0-6.0
3.0-6.0
3.0-6.0
R
Br
Pa
t
se
e
tR
ou
wn
o
ge
an
)
lts
o
(V
a
ck
ge
s
Features
Yes
Yes
40-pin PDIP, Windowed CDIP;
44-pin PLCC, TQFP
40-pin PDIP, Windowed CDIP;
44-pin PLCC, TQFP
Yes 28-pin PDIP, SOIC, Windowed CDIP
Yes 28-pin PDIP, SOIC, Windowed CDIP
e
g
lta
Vo
3.0-6.0
Pi
ns
es
rc
u
So
I/O
pt
P
ru
er
ve
a
Sl
t
or
ge
ta
l
Vo
Peripherals
e
nc
e
er
f
Re
Yes
-
-
n
er
)
(s
or
t
ra
pa
s)
e(
l
du
o
s)
o
em
M
e
yt
am
y
or
em
M
(M
r
og
n
io
Memory
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current
capability.
All PIC16CXXX Family devices use serial programming with clock pin RB6 and data pin RB7.
4K
2K
20
PIC16C641
a
M
um
xim
en
qu
e
Fr
cy
p
fO
at
er
ry
TABLE 1-1:
)
Hz
Clock
PIC16C64X & PIC16C66X
PIC16C64X & PIC16C66X DEVICE FEATURES
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
2.0
PIC16C64X & PIC16C66X
DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements the proper device option can be selected
using the information in the Product Identification System page at the end of this data sheet. When placing
orders, please use that page of the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART Plus and PRO MATE II
programmers both support programming of the
PIC16C64X & PIC16C66X.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
1996 Microchip Technology Inc.
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the
OTP devices but with all EPROM locations and configuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.4
Serialized Quick-TurnaroundProduction (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 7
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 8
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C64X &
PIC16C66X devices can be attributed to a number of
architectural features commonly found in RISC microprocessors. To begin with, the PIC16C64X &
PIC16C66X use a Harvard architecture in which program and data are accessed from separate memories
using separate buses. This improves bandwidth over
traditional von Neumann architecture where program
and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than an 8-bit wide data
word. Instruction opcodes are 14-bits wide making it
possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently,
all instructions (35) execute in a single cycle (200 ns @
20 MHz) except for program branches, which require
two cycles.
The PIC16C641 and PIC16C661 both address 2K x 14
on-chip program memory while the PIC16C642 and
PIC16C662 address 4K x 14. All program memory is
internal.
PIC16C64X & PIC16C66X devices contain an 8-bit
ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and
any register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift, and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
PIC16C64X & PIC16C66X devices can directly or indirectly address their register files or data memory. All
special function registers including the program
counter are mapped in the data memory. These
devices have an orthogonal (symmetrical) instruction
set that makes it possible to carry out any operation on
any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’
make programming with the PIC16C64X & PIC16C66X
simple yet efficient. In addition, the learning curve is
reduced significantly.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 9
PIC16C64X & PIC16C66X
FIGURE 3-1:
PIC16C641/642 BLOCK DIAGRAM
PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM
PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM
13
8
Data Bus
Program Counter
Voltage
Reference
EPROM
Program
Memory
Program
Bus
8 Level Stack
(13-bit)
RAM
Comparator
File
Registers
RA0/AN0
RA1/AN1
+
14
Instruction reg
7
RA3/AN3
+
Addr MUX
8
Direct Addr
RA2/AN2/VREF
9
RAM Bank
Select
Indirect
Addr
FSR reg
Timer0
STATUS reg
RA4/T0CKI
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
ALU
PORTA
W reg
Watchdog
Timer
RA5
Brown-out
Reset
Parity Error
Reset
MCLR
PORTB
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
VDD, VSS
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
DS30559A-page 10
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 3-2:
PIC16C661/662 BLOCK DIAGRAM
PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM
PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM
13
8
Data Bus
Program Counter
Voltage
Reference
EPROM
Program
Memory
Program
Bus
RAM
8 Level Stack
(13-bit)
Comparator
File
Registers
RA0/AN0
RA1/AN1
+
14
Instruction reg
Direct Addr
RA2/AN2/VREF
9
RAM Bank
Select
7
8
RA3/AN3
+
Addr MUX
Indirect
Addr
FSR reg
Timer0
STATUS reg
RA4/T0CKI
3
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MUX
Power-up
Timer
PORTA
ALU
Oscillator
Start-up Timer
Power-on
Reset
W reg
Watchdog
Timer
RA5
Brown-out
Reset
Parity Error
Reset
MCLR
PORTB
VDD, VSS
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Parallel
Slave
Port
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
PORTE
RE0/RD
RE1/WR
PORTD
RE2/CS
1996 Microchip Technology Inc.
Preliminary
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
DS30559A-page 11
PIC16C64X & PIC16C66X
TABLE 3-1:
PIC16C641/642 PINOUT DESCRIPTION
Pin #
I/O/P
Type
OSC1/CLKIN
OSC2/CLKOUT
9
10
I
O
MCLR/VPP
1
I/P
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
RA5
7
I/O
RB0/INT
21
I/O
RB1
RB2
RB3
RB4
RB5
RB6
22
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST(2)
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
RB7
28
I/O
TTL/ST(2)
Interrupt on change pin. Serial programming data.
Name
Buffer
Type
Description
ST/CMOS Oscillator crystal input or external clock source input.
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
ST
Master clear (reset) input or programming voltage input. This pin is
an active low reset to the device.
PORTA is a bi-directional I/O port.
ST
Analog comparator input.
ST
Analog comparator input.
ST
Analog comparator input or VREF output.
ST
Analog comparator input or comparator output.
ST
Can be selected to be the clock input to the Timer0 timer/counter
or a comparator output. Output is open drain type.
ST
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
(1)
RB0 can also be selected as an external interrupt pin.
TTL/ST
TTL
TTL
TTL
TTL
TTL
PORTC is a bi-directional I/O port.
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
VSS
VDD
Legend:
11
I/O
ST
12
I/O
ST
13
I/O
ST
14
I/O
ST
15
I/O
ST
16
I/O
ST
17
I/O
ST
18
I/O
ST
8,19
P
—
Ground reference for logic and I/O pins.
20
P
—
Positive supply for logic and I/O pins.
O = output
I/O = input/output
P = power
I = input
— = not used
ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
DS30559A-page 12
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
TABLE 3-2:
PIC16C661/662 PINOUT DESCRIPTION
DIP
Pin #
QFP
Pin #
PLCC
Pin #
I/O/P
Type
OSC1/CLKIN
13
30
14
I
OSC2/CLKOUT
14
31
15
MCLR/VPP
1
18
2
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
2
3
4
5
6
19
20
21
22
23
3
4
5
6
7
RA5
7
24
8
RB0/INT
33
8
36
RB1
RB2
RB3
RB4
RB5
RB6
34
35
36
37
38
39
9
10
11
14
15
16
37
38
39
41
42
43
RB7
40
17
44
Name
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
Legend:
Buffer
Type
Description
ST/CMOS Oscillator crystal input or external clock source
input.
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2
pin outputs CLKOUT which has 1/4 the frequency of
OSC1, and denotes the instruction cycle rate.
I/P
ST
Master clear (reset) input or programming voltage
input. This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
I/O
ST
Analog comparator input.
I/O
ST
Analog comparator input.
I/O
ST
Analog comparator input or VREF output.
I/O
ST
Analog comparator input or comparator output.
I/O
ST
Can be selected to be the clock input to the
Timer0 timer/counter or a comparator output.
Output is open drain type.
I/O
ST
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on
all inputs.
(1)
I/O
RB0 can also be selected as an external
TTL/ST
interrupt pin.
I/O
TTL
I/O
TTL
I/O
TTL
I/O
TTL
Interrupt on change pin.
I/O
TTL
Interrupt on change pin.
(2)
I/O
Interrupt on change pin. Serial programming
TTL/ST
clock.
(2)
I/O
Interrupt on change pin. Serial programming
TTL/ST
data.
PORTC is a bi-directional I/O port.
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O
ST
I/O = input/output
P = power
— = not used
ST = Schmitt Trigger input
15
32
16
16
35
18
17
36
19
18
37
20
23
42
25
24
43
26
25
44
27
26
1
29
O = output
I = input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used
in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 13
PIC16C64X & PIC16C66X
DIP
Pin #
Name
QFP
Pin #
PLCC
Pin #
I/O/P
Type
Buffer
Type
Description
PORTD can be a bi-directional I/O port or parallel
slave port for interfacing to a microprocessor bus.
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/RD
RE1/WR
RE2/CS
VSS
VDD
NC
Legend:
Note 1:
2:
3:
19
20
21
22
27
28
29
30
38
39
40
41
2
3
4
5
21
22
23
24
30
31
32
33
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
ST/TTL(3)
PORTE is a bi-directional I/O port.
RE0/RD read control for parallel slave port.
ST/TTL(3)
RE1/WR write control for parallel slave port.
RE2/CS select control for parallel slave port.
ST/TTL(3)
—
Ground reference for logic and I/O pins.
—
Positive supply for logic and I/O pins.
—
Not Connected.
ST/TTL(3)
8
25
9
I/O
9
26
10
I/O
10
27
11
I/O
12,31 6,29 13,34
P
11,32 7,28 12,35
P
—
12,13, 1,17
—
33,34 28,40
O = output
I/O = input/output
P = power
I = input
— = not used
ST = Schmitt Trigger input
TTL = TTL input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used
in the Parallel Slave Port Mode (for interfacing to a microprocessor port).
DS30559A-page 14
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
Clocking Scheme/Instruction Cycle
3.1
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3, and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-3.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Tcy0
Tcy1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL SUB_1
4. BSF
PC+1
Fetch 2
Tcy2
Tcy3
Tcy4
Tcy5
Execute 2
Fetch 3
Execute 3
Fetch 4
PORTA, BIT3 (Forced NOP)
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 15
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 16
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
FIGURE 4-2:
The PIC16C64X & PIC16C66X have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16C641 and PIC16C661
only the first 2K x 14 (0000h - 07FFh) is physically
implemented. For the PIC16C642 and PIC16C662 only
the first 4K x 14 (0000h - 0FFh) is physically implemented. Accessing a location above the 2K or 4K
boundary will cause a wrap-around. The reset vector is
at 0000h and the interrupt vector is at 0004h (Figure 41 and Figure 4-2). See Section 4.4 for Program Memory paging.
FIGURE 4-1:
PIC16C642/662 PROGRAM
MEMORY MAP AND STACK
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
PIC16C641/661 PROGRAM
MEMORY MAP AND STACK
Reset Vector
0000h
Interrupt Vector
0004h
0005h
User Memory Space
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Page0
On-chip Program
Memory
Reset Vector
User Memory Space
On-chip Program
Memory
0000h
07FFh
0800h
Page1
0FFFh
1000h
Interrupt Vector
0004h
0005h
1FFFh
On-chip Program
Memory
TEST
2000h
Configuration Word
2007h
TEST
07FFh
3FFFh
0800h
1FFFh
TEST
2000h
Configuration Word
2007h
TEST
1996 Microchip Technology Inc.
3FFFh
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 17
PIC16C64X & PIC16C66X
4.2
Data Memory Organization
FIGURE 4-3:
The data memory (Figure 4-4) is partitioned into two
banks which contain the general purpose registers and
the special function registers. Bank 0 is selected when
bit RP0 (STATUS) is cleared. Bank 1 is selected
when the RP0 bit is set. The Special Function Registers are located in the first 32 locations of each Bank.
Register locations A0h-EFh (Bank 1) are general purpose registers implemented as static RAM. Some special function registers are mapped in Bank 1.
4.2.1
PIC16C641/661 DATA
MEMORY MAP
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
GENERAL PURPOSE REGISTER FILE
The register file is organized as 176 x 8 for the
PIC16C642/662, and 128 x8 for the PIC16C641/661.
Each is accessed either directly, or indirectly through
the File Select Register FSR (Section 4.5).
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PCON
CMCON
VRCON
General
Purpose
Register
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
Mapped
in Page 0
7Fh
Bank 0
EFh
F0h
FFh
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2: Not implemented on the PIC16C641.
DS30559A-page 18
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 4-4:
PIC16C642/662 DATA
MEMORY MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
4.2.2
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(2)
TRISE(2)
PCLATH
INTCON
PIE1
PCON
CMCON
VRCON
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the
CPU and Peripheral Modules for controlling the desired
operation of the device (Table 4-1). These registers are
static RAM.
The special function registers can be classified into two
sets (core and peripheral). The special function registers associated with the “core” functions are described
in this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
A0h
General
Purpose
Register
General
Purpose
Register
EFh
Mapped
in Bank 0
7Fh
F0h
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2: Not implemented on the PIC16C642.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 19
PIC16C64X & PIC16C66X
TABLE 4-1:
SPECIAL FUNCTION REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR,
PER
Value on
all other
resets(1)
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h
TMR0
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h
STATUS
04h
FSR
05h
PORTA
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--xx 0000 --xu 0000
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
06h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
06h
PORTD(3)
PORTD Data Latch when written: PORTD pins when read
06h
PORTE(3)
—
—
—
0Ah
PCLATH
—
—
—
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(4)
CMIF
—
—
—
—
—
—
00-- ---- 00-- ----
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000 00-- 0000
—
—
xxxx xxxx uuuu uuuu
RE2
RE1
RE0
Write buffer for upper 5 bits of program counter
---0 0000 ---0 0000
0Dh-1Eh Unimplemented
1Fh
CMCON
---- -xxx ---- -uuu
—
—
Bank 1
80h
INDF
81h
OPTION
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
86h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
86h
TRISD(3)
PORTD Data Direction Register
86h
TRISE(3)
IBF
OBF
IBOV
8Ah
PCLATH
—
—
—
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
PSPIE(4)
CMIE
—
—
—
MPEEN
—
—
—
VREN
VROE
VRR
—
8Ch
PIE1
8Dh
Unimplemented
8Eh
PCON
8Fh-9Eh
Unimplemented
9Fh
VRCON
Note
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111 0000 -111
INTF
RBIF
0000 000x 0000 000x
—
—
—
00-- ---- 00-- ----
—
PER
POR
BOR
u--- -qqq u--- -uuu
VR3
VR2
VR1
VR0
000- 0000 000- 0000
Write buffer for upper 5 bits of program counter
---0 0000 ---0 0000
—
—
—
—
Legend: - = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: The IRP and RP1 bits are reserved, always maintain these bits clear.
3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642.
4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.
DS30559A-page 20
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.1
It is recommended, therefore, that only BCF, BSF,
SWAPF, and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary.”
STATUS REGISTER
The STATUS register, shown in Figure 4-5, contains
the arithmetic status of the ALU, the RESET status, and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The IRP and RP1 bits (STATUS) are
reserved on the PIC16C64X &
PIC16C66X and should be maintained
clear. Use of these bits as general purpose R/W bits is NOT recommended,
since this may affect upward compatibility
with future products.
Note 2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
FIGURE 4-5:
R/W-0
IRP
bit7
bit 7:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
Bit IRP is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. Bit RP1 is reserved on the PIC16C64X & PIC16C66X, always maintain this bit
clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 21
PIC16C64X & PIC16C66X
4.2.2.2
OPTION REGISTER
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 4-6:
R/W-1
RBPU
bit7
Note:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT.
R/W-1
PS1
R/W-1
PS0
bit0
OPTION REGISTER (ADDRESS 81h)
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
DS30559A-page 22
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.3
INTCON REGISTER
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all non-peripheral interrupt sources.
FIGURE 4-7:
R/W-0
GIE
bit7
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (See Section 5.2 to clear interrupt)
0 = None of the RB7:RB4 pins have changed state
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 23
PIC16C64X & PIC16C66X
4.2.2.4
PIE1 REGISTER
This register contains the individual enable bits for the
comparator and Parallel Slave Port interrupts.
FIGURE 4-8:
R/W-0
PSPIE(1)
bit7
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
CMIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
U-0
—
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 5-0: Unimplemented: Read as '0'
Note 1: Bit PSPIE is reserved on the PIC16C641/642, always maintain this bit clear.
DS30559A-page 24
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
comparator and Parallel Slave Port interrupts.
FIGURE 4-9:
R/W-0
PSPIF(1)
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
CMIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Interrupt Flag bit
1 = A read or write operation has taken place (must be cleared in software)
0 = No read or write operation has taken place
bit 6:
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5-0: Unimplemented: Read as '0'
Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 25
PIC16C64X & PIC16C66X
4.2.2.6
PCON REGISTER
Note:
The PCON register contains flag bits to differentiate
between a Power-on Reset (POR), an external MCLR
reset, WDT reset, Brown-out Reset (BOR), and Parity
Error Reset (PER). The PCON register also contains a
status bit, MPEEN, which reflects the value of the
MPEEN bit in Configuration Word. See Table 9-4 for
status of these bits on various resets.
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR status bit is a “don't
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
programming the BODEN bit in the
Configuration word).
FIGURE 4-10: PCON REGISTER (ADDRESS 8Eh)
R-U
MPEEN
bit7
bit 7:
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
PER
R/W-0
POR
R/W-u
BOR
bit0
R= Readable bit
W= Writable bit
U= Unimplemented bit,
read as ‘0’
- n= Value at POR reset
MPEEN: Memory Parity Error Circuitry Status bit
Reflects the value of Configuration Word bit, MPEEN
bit 6-3: Unimplemented: Read as '0'
bit 2:
PER: Memory Parity Error Reset Status bit
1 = No error occurred
0 = Program memory fetch parity error occurred
(must be set in software after a Parity Error Reset occurs)
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS30559A-page 26
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
4.3
PCL and PCLATH
4.3.2
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is readable and
writable. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-11 shows the two
situations for the loading of the PC. The upper example
in the figure shows how the PC is loaded on a write to
PCL (PCLATH → PCH). The lower example in
the figure shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH → PCH).
FIGURE 4-11: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
5
8
PCLATH
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PIC16C64X & PIC16C66X devices have an 8 level
deep x 13-bit wide hardware stack (Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
Note 2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
PCL
8
4.4
0
7
PC
Program Memory Paging
GOTO, CALL
2
PCLATH
11
Opcode
PCLATH
4.3.1
STACK
COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When
doing a table read using a computed GOTO method,
care should be exercised if the table location crosses a
PCL memory boundary (each 256 byte block). Refer to
the application note “Implementing a Table Read”
(AN556).
PIC16C642 and PIC16C662 devices have 4K of program memory, but the CALL and GOTO instructions only
have an 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. To allow CALL and GOTO instructions to
address the entire 4K program memory address range,
there must be another bit to specify the program memory page. This paging bit comes from the PCLATH
bit (Figure 4-11). When doing a CALL or GOTO instruction, the user must ensure that this page select bit
(PCLATH) is programmed so that the desired program memory page is addressed. If a return from a
CALL instruction (or interrupt) is executed, the entire
13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH bit is not required for the
return instructions (which POPs the address from the
stack).
Note:
1996 Microchip Technology Inc.
Preliminary
The PIC16C64X & PIC16C66X ignore the
PCLATH bit, which is used for program
memory pages 2 and 3 (1000h - 1FFFh).
The use of PCLATH as a general purpose read/write bit is not recommended
since this may affect upward compatibility
with future products.
DS30559A-page 27
PIC16C64X & PIC16C66X
4.5
Indirect Addressing, INDF, and FSR
Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 4-1:
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS), as
shown in Figure 4-12. However, bit IRP is not used in
the PIC16C64X & PIC16C66X.
movlw
movwf
clrf
incf
btfss
goto
NEXT
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no goto next
;yes continue
CONTINUE:
FIGURE 4-12: DIRECT/INDIRECT ADDRESSING
Direct Addressing
(1)RP1
RP0
bank select
6
from opcode
Indirect Addressing
IRP(1)
0
7
bank select
location select
00
01
10
FSR register
0
location select
11
00h
00h
not used
Data
Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-3 and Figure 4-4.
Note 1: Bits RP1 and IRP are reserved, always maintain these bits clear.
DS30559A-page 28
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.0
I/O PORTS
FIGURE 5-1:
The PIC16C641 and PIC16C642 have three ports,
PORTA, PORTB, and PORTC. PIC16C661 and
PIC16C662 devices have five ports, PORTA through
PORTE. Some pins for these I/O ports are multiplexed
with alternate functions for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
Data
bus
D
Q
VDD
WR
Port
CK
Q
PORTA and TRISA Registers
PORTA is a 6-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Pin RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers)
which can configure these pins as input or output.
P
Data Latch
D
5.1
BLOCK DIAGRAM OF
RA1:RA0 PINS
WR
TRIS
Q
N
CK
Q
VSS
TRIS Latch
Analog
Input Mode
RD TRIS
Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit
in the TRISA register puts the contents of the output
latch on the selected pin.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control) register. When selected as
comparator inputs, these pins will read as '0's.
I/O Pin
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORT
To Comparator
Note: I/O pins have protection diodes to VDD and VSS.
Note:
On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is
a very hi-impedance output. The user must set the
TRISA bit and use hi-impedance loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
1996 Microchip Technology Inc.
INITIALIZING PORTA
CLRF
PORTA
MOVLW
MOVWF
BSF
MOVLW
0x07
CMCON
STATUS, RP0
0x1F
MOVWF
TRISA
Preliminary
This document was created with FrameMaker 4 0 4
;Initialize PORTA by
;clearing output latches
;Turn comparators off,
;enable pins for I/O
;Select bank1
;Value to initialize
;data direction
;Set RA as inputs
;TRISA are clear
DS30559A-page 29
PIC16C64X & PIC16C66X
FIGURE 5-2:
Data
bus
BLOCK DIAGRAM OF RA2 PIN
D
Q
VDD
WR
Port
CK
Q
P
Data Latch
D
WR
TRIS
Q
RA2 Pin
N
CK
Q
VSS
TRIS Latch
Analog
Input Mode
RD TRIS
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORT
To Comparator
VROE
VREF
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 5-3:
Data
bus
BLOCK DIAGRAM OF RA3 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
Port
CK
VDD
Q
P
Data Latch
D
WR
TRIS
Q
N
CK
RA3 Pin
Q
VSS
TRIS Latch
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRIS
Q
D
EN
RD PORT
To Comparator
DS30559A-page 30
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 5-4:
Data
bus
BLOCK DIAGRAM OF RA4 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
Port
CK
Q
Data Latch
D
Q
N
WR
TRIS
CK
RA4 Pin
Q
VSS
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRIS
Q
D
EN
RD PORT
TMR0 Clock Input
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit #
Buffer
Type
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Input/output or comparator input.
Input/output or comparator input.
Input/output or comparator input or VREF output.
Input/output or comparator input/output.
Input/output or external clock input for TMR0 or comparator output. Output is open drain type.
Input/output.
RA5
bit5
ST
Legend: ST = Schmitt Trigger input
TABLE 5-2:
Address Name
05h
85h
1Fh
9Fh
Legend:
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx 0000 --uu
PORTA
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11
CMCON C2OUT C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000 00-VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000 000x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
1996 Microchip Technology Inc.
Preliminary
0000
1111
0000
0000
DS30559A-page 31
PIC16C64X & PIC16C66X
PORTB and TRISB Registers
5.2
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. Setting
a bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the
TRISB register puts the contents of the output latch on
the selected pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION) bit. The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in (INTCON)).
FIGURE 5-5:
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6:
VDD
RBPU(2)
Data bus
WR Port
BLOCK DIAGRAM OF
RB7:RB4 PINS
weak
P pull-up
Data Latch
D
Q
RBPU(2)
WR TRIS
I/O
pin(1)
CK
D
VDD
Data bus
BLOCK DIAGRAM OF
RB3:RB0 PINS
Q
TTL
Input
Buffer
CK
weak
P pull-up
Data Latch
D
Q
WR Port
RD TRIS
I/O
pin(1)
CK
Q
TRIS Latch
D
Q
WR TRIS
RD Port
TTL
Input
Buffer
CK
RD TRIS
D
EN
RB0/INT
ST
Buffer
ST
Buffer
RD Port
Latch
Q
RD Port
D
Note 1: I/O pins have diode protection to VDD and VSS.
EN
2: TRISB = '1' enables weak pull-up if RBPU = '0'
(OPTION).
Set RBIF
From other
RB7:RB4 pins
Q
D
EN
RB7:RB6 in serial programming mode
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = '1' enables weak pull-up if RBPU = '0'
(OPTION).
DS30559A-page 32
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
EXAMPLE 5-2:
INITIALIZING PORTB
CLRF
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
TABLE 5-3:
Name
;
;
;
;
;
;
;
;
;
;
PORTB FUNCTIONS
Bit #
RB0/INT
Initialize PORTB by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
Buffer Type
bit0
Function
Input/output or external interrupt input. Internal software programmable
weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6
bit6
Input/output pin (with interrupt on change). Internal software programmable
TTL/ST(2)
weak pull-up. Serial programming clock pin.
(2)
RB7
bit7
Input/output
pin (with interrupt on change). Internal software programmable
TTL/ST
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
TTL/ST
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name
06h
86h
81h
(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PORTB
TRISB
OPTION
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend: x = unknown, u = unchanged, shaded cells are not used by PORTB.
1996 Microchip Technology Inc.
Preliminary
Value on
all other
resets
uuuu uuuu
1111 1111
1111 1111
DS30559A-page 33
PIC16C64X & PIC16C66X
5.3
PORTC and TRISC Registers
FIGURE 5-7:
PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the
TRISC register. PORTC pins have Schmitt Trigger
input buffers.
EXAMPLE 5-3:
CLRF
BSF
MOVLW
MOVWF
Data
bus
PORTC BLOCK DIAGRAM (IN
I/O PORT MODE)
D
WR
PORT
I/O pin(1)
CK
INITIALIZING PORTC
PORTC
STATUS, RP0
0xCF
TRISC
;
;
;
;
;
;
;
;
;
;
Q
Data Latch
Initialize PORTC by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RC as inputs
RC as outputs
RC as inputs
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0
bit0
ST
Input/output
RC1
bit1
ST
Input/output
RC2
bit2
ST
Input/output
RC3
bit3
ST
Input/output
RC4
bit4
ST
Input/output
RC5
bit5
ST
Input/output
RC6
bit6
ST
Input/output
RC7
bit7
ST
Input/output
Legend: ST = Schmitt Trigger input
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
87h
TRISC
TRISC7
TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
1111 1111
Legend: x = unknown, u = unchanged.
DS30559A-page 34
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.4
PORTD and TRISD Registers
(PIC16C661 and PIC16C662 only)
FIGURE 5-8:
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
Data
bus
D
WR
PORT
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE). In this mode, the input buffers
are TTL.
PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
Q
I/O pin(1)
CK
Data Latch
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
RD0/PSP0
bit0
ST/TTL(1)
Input/output port pin or parallel slave port bit0
bit1
ST/TTL(1)
Input/output port pin or parallel slave port bit1
bit2
(1)
Input/output port pin or parallel slave port bit2
(1)
RD1/PSP1
RD2/PSP2
ST/TTL
Function
RD3/PSP3
bit3
ST/TTL
Input/output port pin or parallel slave port bit3
RD4/PSP4
bit4
ST/TTL(1)
Input/output port pin or parallel slave port bit4
bit5
(1)
Input/output port pin or parallel slave port bit5
(1)
Input/output port pin or parallel slave port bit6
RD5/PSP5
RD6/PSP6
ST/TTL
bit6
ST/TTL
ST/TTL(1)
RD7/PSP7
bit7
Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
88h
TRISD
TRISD3 TRISD2 TRISD1 TRISD0 1111 1111
1111 1111
89h
TRISE
TRISD7 TRISD6 TRISD5
IBF
OBF
IBOV
TRISD4
PSPMODE
—
TRISE2 TRISE1 TRISE0 0000 -111
0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 35
PIC16C64X & PIC16C66X
5.5
PORTE and TRISE Register
(PIC16C661 and PIC16C662 only)
Figure 5-9 shows the TRISE register, which also controls the parallel slave port operation.
PORTE has three pins RE0/RD, RE1/WR, and RE2/
CS, which are individually configurable as inputs or
outputs. These pins have Schmitt Trigger input buffers.
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE) is set. In
this mode, the user must make sure that the
TRISE bits are set (pins are configured as digital
inputs). In this mode the input buffers are TTL.
FIGURE 5-9:
R-0
IBF
bit7
TRISE REGISTER (ADDRESS 89h)
R-0
OBF
R/W-0
IBOV
R/W-0
PSPMODE
U-0
—
R/W-1
TRISE2
R/W-1
TRISE1
R/W-1
TRISE0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
Unimplemented: Read as '0'
bit 2:
TRISE2: Direction control bit for pin RE2/CS
1 = Input
0 = Output
bit 1:
TRISE1: Direction control bit for pin RE1/WR
1 = Input
0 = Output
bit 0:
TRISE0: Direction control bit for pin RE0/RD
1 = Input
0 = Output
DS30559A-page 36
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
FIGURE 5-10: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
Data Bus
D
Q
CK
Q
I/O pin
WR PORT
Data Latch
WR TRIS
D
Q
CK
Q
Schmitt
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note: I/O pins have protection diodes to VDD and VSS.
TABLE 5-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
RE0/RD
bit0
ST/TTL(1)
Function
Input/output port pin or read control input in parallel slave port mode:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR
bit1
ST/TTL(1)
Input/output port pin or write control input in parallel slave port mode:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
bit2
ST/TTL(1)
Input/output port pin or chip select control input in parallel slave port
mode:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
RE2/CS
TABLE 5-10:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
0000 -111
0000 -111
Address
Name
09h
89h
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 37
PIC16C64X & PIC16C66X
5.6
I/O Programming Considerations
5.6.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-4:
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content
of the data latch may now be unknown.
Reading the port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(e.g., BCF, BSF, etc.) on a port, the value of the port
pins is read, the desired operation is done to this value,
and this value is then written to the port latch.
Example 5-4 shows the effect of two sequential
read-modify-write instructions on an I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
;Initial PORT settings: PORTB Inputs
;
PORTB Outputs
;PORTB have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------BCF PORTB, 7
; 01pp pppp
11pp pppp
BCF PORTB, 6
; 10pp pppp
11pp pppp
BCF STATUS, RP1 ;
BSF STATUS, RP0 ;
BCF TRISB, 7
; 10pp pppp
11pp pppp
BCF TRISB, 6
; 10pp pppp
10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
5.6.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-11). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into the CPU is executed. Otherwise,
the previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with an NOP or another
instruction not accessing this I/O port.
FIGURE 5-11: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
PC
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
PC + 2
PC + 3
NOP
NOP
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Instruction
executed
NOP
MOVWF PORTB
write to
PORTB
DS30559A-page 38
Note:
MOVF PORTB,W
Preliminary
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
5.7
Parallel Slave Port
(PIC16C661 and PIC16C662 only)
An interrupt is generated and latched into flag bit
PSPIF (PIR1) when a read or a write operation is
completed. Flag bit PSPIF must be cleared by user
software. The interrupt can be disabled by clearing the
interrupt enable bit PSPIE (PIE1).
PORTD operates as an 8-bit wide parallel slave port, or
as a microprocessor port when control bit PSPMODE
(TRISE) is set. In slave mode it is asynchronously
readable and writable by the external world through
RD control input pin (RE0/RD) and WR control input pin
(RE1/WR).
FIGURE 5-12: PORTD AND PORTE AS A
PARALLEL SLAVE PORT
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE)
must be configured as inputs (set).
Data bus
D
WR
PORT
Q
RDx
pin
CK
TTL
Q
RD
PORT
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored
since the microprocessor is controlling the direction of
data flow.
D
EN
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1)
Input Buffer Full Status Flag bit IBF (TRISE) is set
if a received word is waiting to be read by the CPU.
Once the PORTD input latch is read, bit IBF is cleared.
IBF is a read only status bit. Output Buffer Full Status
Flag bit OBF (TRISE) is set if a word written to
PORTD latch is waiting to be read by the external bus.
Once the PORTD output latch is read by the microprocessor, bit OBF is cleared. Input Buffer Overflow Status
flag bit IBOV (TRISE) is set if a second write to the
microprocessor port is attempted when the previous
word has not been read by the CPU (the first word is
retained in the buffer).
Read
TTL
RD
Chip Select
TTL
CS
TTL
WR
Write
Note: I/O pins have protection diodes to VDD and VSS.
When not in Parallel Slave Port mode, bits IBF and
OBF are held clear. However, if flag bit IBOV was previously set, it must be cleared in software.
TABLE 5-11:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h
PORTD
PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0
xxxx xxxx
uuuu uuuu
09h
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
0000 -111
0000 -111
PIR1
PSPIF(1)
CMIF
—
—
—
—
—
—
00-- ----
00-- ----
PIE1
PSPIE(1)
CMIE
—
—
—
—
—
—
00-- ----
00-- ----
0Ch
8Ch
TRISE2 TRISE1 TRISE0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP.
Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 39
PIC16C64X & PIC16C66X
NOTES:
DS30559A-page 40
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
6.0
TIMER0 MODULE
(OPTION). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are discussed in detail in Section 6.2.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Read and write capability
- Interrupt on overflow from FFh to 00h
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit
PSA (OPTION). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, …,
1:256 are selectable. Section 6.3 details the operation
of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the register
(TMR0) overflows from FFh to 00h. This overflow sets
interrupt flag bit T0IF (INTCON). The interrupt can
be masked by clearing enable bit T0IE (INTCON).
Flag bit T0IF must be cleared in software by the Timer0
interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot wake the processor
from SLEEP since the timer is shut off during SLEEP.
Figure 6-4 displays the Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS. In this
mode, Timer0 will increment either on every rising or
falling edge of pin RA4/T0CKI. The incrementing edge
is determined by the source edge select bit T0SE
FIGURE 6-1:
Timer0 Interrupt
6.1
TIMER0 BLOCK DIAGRAM
Data bus
RA4/T0CKI
pin
FOSC/4
0
PSout
1
Sync with
Internal
clocks
1
Programmable
Prescaler
8
0
TMR0 reg
PSout
(2 cycle delay)
T0SE
3
Set bit T0IF
on overflow
PSA
PS2, PS1, PS0
T0CS
Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION C2 VIN–
0 = C2 VIN+ < C2 VIN–
bit 6:
C1OUT: Comparator 1 output
1 = C1 VIN+ > C1 VIN–
0 = C1 VIN+ < C1 VIN–
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
bit0
R =Readable bit
W =Writable bit
U =Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 5-4: Unimplemented: Read as '0'
bit 3:
CIS: Comparator Input Switch
When CM2:CM0: = 001:
Then:
1 = C1 VIN– connects to RA3
0 = C1 VIN– connects to RA0
When CM2:CM0 = 010:
Then:
1 = C1 VIN– connects to RA3
C2 VIN– connects to RA2
0 = C1 VIN– connects to RA0
C2 VIN– connects to RA1
bit 2-0: CM2:CM0: Comparator mode
Figure 7-2 shows the comparator modes and CM2:CM0 bit settings.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 47
PIC16C64X & PIC16C66X
7.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 7-2 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the comparator
FIGURE 7-2:
RA3/AN3
RA1/AN1
RA2/AN2
RA3/AN3
A
VIN-
A
VIN+
A
VIN-
A
VIN+
RA0/AN0
C1
Off (Read as '0')
A
VIN-
A
VIN+
A
VIN-
RA3/AN3
RA1/AN1
C2
Off (Read as '0')
RA2/AN2
RA0/AN0
C1
RA2/AN2
A
VIN+
C2
D
VIN-
D
VIN+
D
VIN-
D
VIN+
C1
Off (Read as '0')
C2
Off (Read as '0')
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 010
C1OUT
RA3/AN3
RA1/AN1
RA1/AN1
Comparator interrupts should be disabled
during a comparator mode change otherwise a false interrupt may occur.
Comparators Off
CM2:CM0 = 111
Two Independent Comparators
CM2:CM0 = 100
RA0/AN0
Note:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
CM2:CM0 = 000
RA0/AN0
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 12-2.
RA2/AN2
C2OUT
A
A
VIN-
CIS = 0
CIS = 1
VIN+
C1
C1OUT
C2
C2OUT
A
A
VIN-
CIS = 0
CIS = 1
VIN+
From VREF Module
Two Common Reference Comparators
CM2:CM0 = 011
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
VIN-
D
VIN+
A
VIN-
A
VIN+
Two Common Reference Comparators with Outputs
CM2:CM0 = 110
RA0/AN0
C1
C1OUT
RA3/AN3
RA1/AN1
C2
C2OUT
RA2/AN2
A
VIN-
D
VIN+
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
RA4 Open Drain
Three Inputs Multiplexed to Two Comparators
CM2:CM0 = 001
One Independent Comparator
CM2:CM0 = 101
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
A
VIN-
A
VIN+
RA0/AN0
C1
Off (Read as '0')
RA3/AN3
RA1/AN1
C2
C2OUT
RA2/AN2
A
A
CIS = 0
CIS = 1
VINVIN+
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
A = Analog Input, port reads zeros always.
D = Digital Input.
CIS (CMCON) is the Comparator Input Switch.
DS30559A-page 48
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
The code example in Example 7-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital outputs. RA0 and RA1
are configured as the V- inputs and RA2 as the V+ input
to both comparators.
EXAMPLE 7-1:
INITIALIZING THE
COMPARATOR MODULE
FLAG_REG
CLRF
CLRF
ANDLW
IORWF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
EQU 0x20
FLAG_REG
PORTA
0xC0
FLAG_REG,F
0x03
CMCON
STATUS,RP0
0x07
TRISA
BCF
CALL
MOVF
STATUS,RP0
DELAY_10µs
CMCON,F
BCF
BSF
BSF
BCF
BSF
BSF
PIR1,CMIF
STATUS,RP0
PIE1,CMIE
STATUS,RP0
INTCON,PEIE
INTCON,GIE
7.2
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal that is present at VIN– is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 7-3).
FIGURE 7-3:
;Init Flag Register
;Init PORTA
;Mask Comp bits
;Bits to Flag_Reg
;Init Comp Mode
;CM2:CM0 = 011
;Select Bank 1
;Init Data direction
;RA to inputs
;RA to outputs
;TRISA read '0'
;Select Bank 0
;10 µs delay
;Read CMCON to end
;change condition
;Clear Pending Ints
;Select Bank 1
;Enable Comp Ints
;Select Bank 0
;Enable Periph Ints
;Global Int enable
Comparator Operation
A single comparator is shown in Figure 7-3 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN–, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN–, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 7-3 represents
the uncertainty due to input offsets and response time.
1996 Microchip Technology Inc.
7.3
SINGLE COMPARATOR
VINVIN+
Output
VINVIN+
Output
7.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD, and can be applied to either
pin of the comparator(s).
7.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 8.0, contains a detailed description of the Voltage Reference Module that provides this
signal. The internal reference signal is used when the
comparators
are
in
mode
CM2:CM0 = 010
(Figure 7-2). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.
Preliminary
DS30559A-page 49
PIC16C64X & PIC16C66X
7.4
Comparator Response Time
7.5
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is guaranteed to have a valid level.
If the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 12-2 and Table 12-3).
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When CM2:CM0 = 110, multiplexors in the
output path of the RA3 and RA4 pins will switch and the
output of each pin will be the unsynchronized output of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 7-4 shows the comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4 pins while in this mode.
Note 1: When reading the PORTA register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
Note 2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is specified.
FIGURE 7-4:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
To RA3 or RA4 pin
To Data Bus
Q
D
EN
RD CMCON
Q
Set CMIF bit
D
RD CMCON
EN
CL
From other Comparator
DS30559A-page 50
NRESET
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
7.6
Comparator Interrupts
comparators, CM2:CM0 = 111, before entering sleep.
If the device wakes up from sleep, the contents of the
CMCON register are not affected.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator. User
software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that has occurred. The
CMIF bit (PIR1), is the comparator interrupt flag
and must be cleared in user software.
7.8
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM2:CM0 = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at reset time. The comparators will be powered
down during the reset interval.
To enable the Comparator interrupt the following bits
must be set:
• CMIE (PIE1)
• PEIE (INTCON)
• GIE (INTCON)
7.9
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake up the device from SLEEP mode when enabled.
While the comparator is powered up, higher sleep
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
FIGURE 7-5:
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 7-5. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
7.7
Effects of a RESET
ANALOG INPUT MODEL
VDD
VT = 0.6V
RS
RC < 10k
AIN
VA
CPIN
5 pF
VT = 0.6V
ILEAKAGE
±500 nA
VSS
Legend CPIN
VT
ILEAKAGE
RIC
RS
VA
1996 Microchip Technology Inc.
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to various junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Preliminary
DS30559A-page 51
PIC16C64X & PIC16C66X
TABLE 7-1:
REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
CMIF
—
—
—
—
—
—
00-- ----
00-- ----
8Ch
PIE1
PSPIE(1)
CMIE
—
—
—
—
—
—
00-- ----
00-- ----
85h
TRISA
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
--11 1111
Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.
DS30559A-page 52
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
8.0
VOLTAGE REFERENCE
MODULE
The VRCON register, shown in Figure 8-1, controls the
operation of the Voltage Reference Module. The block
diagram is given in Figure 8-2.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference module is not
being used.
FIGURE 8-1:
R/W-0
VREN
bit7
VRCON REGISTER (ADDRESS 9Fh)
R/W-0
VROE
R/W-0
VRR
U-0
—
R/W-0
VR3
R/W-0
VR2
bit 7:
VREN: VREF Enable
1 = VREF circuit powered up
0 = VREF circuit powered down, no IDD drain
bit 6:
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5:
VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4:
Unimplemented: Read as '0'
R/W-0
VR1
R/W-0
VR0
bit0
R =Readable bit
W =Writable bit
U =Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit 3-0: VR3:VR0: VREF value selection 0 ≤ VR3:VR0 ≤ 15
When: VRR = 1
Then: VREF = (VR3:VR0/ 24) • VDD
When: VRR = 0
Then: VREF = 1/4 • VDD + (VR3:VR0/ 32) • VDD
FIGURE 8-2:
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VREF
Note:
16-1 Analog Mux
VRR
VR3
VR2 (From VRCON)
VR1
VR0
R is defined in Table 12-3.
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 53
PIC16C64X & PIC16C66X
Configuring the Voltage Reference
8.1
the VREF output changes with fluctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 12-3.
The Voltage Reference Module can output 16 distinct
voltage levels for each range.
8.3
The equations used to calculate the output of the
Voltage Reference are as follows:
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference Module should be disabled.
If VRR = 1
Then VREF = (VR3:VR0/24) • VDD
If VRR = 0
Then VREF = (VDD • 1/4) + (VR3:VR0/32) • VDD
A device reset disables the Voltage Reference by clearing bit VREN (VRCON). This reset also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON) and selects the high voltage
range by clearing bit VRR (VRCON). The VREF
value select bits, VRCON, are also cleared.
VOLTAGE REFERENCE
CONFIGURATION
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
0x02
CMCON
STATUS,RP0
0x07
TRISA
0xA6
VRCON
STATUS,RP0
DELAY_10µs
;
;
;
;
;
;
;
;
8.2
Voltage Reference Accuracy/Error
8.5
4 inputs muxed
to 2 comparators
Select Bank 1
RA3:RA0 to outputs
Connection Considerations
The Voltage Reference Module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA bit is set and bit VROE is set. Enabling the
Voltage Reference output onto the RA2 pin with an
input signal present will increase current consumption.
Connecting RA2 as a digital output with VREF enabled
will also increase current consumption.
enable Vref low
range, VR3:VR0 = 6
Select Bank 0
; 10 µs delay
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 8-3 shows an example buffering
technique.
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 8-2) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
FIGURE 8-3:
Effects of a Reset
8.4
The settling time of the Voltage Reference must be
considered when changing the VREF output
(Table 12-2). Example 8-1 shows an example of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
EXAMPLE 8-1:
Operation During Sleep
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC16C662
VREF
Module
R(1)
Pin RA2
VREF output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON and VRCON.
TABLE 8-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR,
BOR
Value on
all other
resets
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
85h
TRISA
—
—
--11 1111
--11 1111
DS30559A-page 54
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.0
SPECIAL FEATURES OF THE
CPU
What sets apart a microcontroller from other
processors are special circuits to deal with the needs of
real-time applications. The PIC16C64X & PIC16C66X
families have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving
operating modes and offer code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
Oscillator selection
Resets
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
Brown-out Reset (BOR)
Parity Error Reset (PER)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID Locations
In-circuit serial programming
1996 Microchip Technology Inc.
The PIC16C64X & PIC16C66X has a Watchdog Timer
which is enabled by a configuration bit (WDTE). It runs
off its own RC oscillator for added reliability. There are
two timers that offer necessary delays on power-up.
One is the Oscillator Start-up Timer (OST), intended to
keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in reset while the power
supply stabilizes. Circuitry has been provided for
checking program memory parity with a reset when an
error is indicated. There is also circuitry to reset the
device if a brown-out occurs which provides at least a
72 ms reset. With these three functions on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Preliminary
This document was created with FrameMaker 4 0 4
DS30559A-page 55
PIC16C64X & PIC16C66X
Configuration Bits
9.1
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h–3FFFh), which can be accessed only during
programming.
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
FIGURE 9-1:
CP1
CP0
CONFIGURATION WORD
CP1
CP0
CP1
CP0
MPEEN
BODEN CP1
CP0
PWRTE
bit13
bit 13-8
5-4:
FOSC1 FOSC0
bit0
CONFIG
REGISTER:
Address
2007h
CP1:CP0: Code protection bits(2)
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7:
MPEEN: Memory Parity Error Enable
1 = Memory Parity Checking is enabled
0 = Memory Parity Checking is disabled
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note
WDTE
1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the
Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS30559A-page 56
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.2
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
TABLE 9-1:
The PIC16CXXX can be operated in four different
oscillator modes. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
LP
XT
HS
RC
9.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 9-2). The PIC16CXXX oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 9-3).
FIGURE 9-2:
Ranges tested:
Mode
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
XT
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Resonators used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
RF
TABLE 9-2:
RS
see Note
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
(PRELIMINARY)
Freq
OSC1
OSC2
LP
32 kHz
200 kHz
100 kHz
2 MHz
4 MHz
8 MHz
10 MHz
20 MHz
68 - 100 pF
15 - 30 pF
68 - 150 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
XT
PIC16CXXX
HS
A series resistor may be required for
AT strip cut crystals.
FIGURE 9-3:
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level specification. Since each crystal has its own
characteristics, the user should consult the crystal
manufacturer for appropriate values of external
components.
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
Crystals used:
PIC16CXXX
Open
±0.3%
±0.5%
±0.5%
±0.5%
±0.5%
Mode
SLEEP
See Table 9-1 or Table 9-2 for recommended values of C1 and C2.
clock from
ext. system
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
OSC2
Note:
22 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
To internal logic
XTAL
C2
OSC1
Note: Recommended values of C1 and C2 are identical
to the ranges tested table.
Higher capacitance increases the stability of the
oscillator but also increases the start-up time.
These values are for design guidance only. Since
each resonator has its own characteristics, the
user should consult the resonator manufacturer for
appropriate values of external components.
OSC1
C1
Freq
HS
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
(PRELIMINARY)
OSC2
1996 Microchip Technology Inc.
32.768 kHz
100 kHz
200 kHz
2.0 MHz
4.0 MHz
10.0 MHz
20.0 MHz
Preliminary
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
ECS ECS-20-S-2
ECS ECS-40-S-4
ECS ECS-100-S-4
ECS ECS-200-S-4
± 20 PPM
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
± 50 PPM
± 50 PPM
DS30559A-page 57
PIC16C64X & PIC16C66X
9.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
9.2.4
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types
of crystal oscillator circuits can be used: one with series
resonance, or one with parallel resonance.
Figure 9-4 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This could
be used for external oscillator designs.
FIGURE 9-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CXXX
CLKIN
74AS04
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
Cext values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 9-6 shows how the R/C combination is connected to the PIC16CXXX. For Rext values
below 2.2 kΩ, the oscillator operation may become
unstable, or stop completely. For very high Rext values
(e.g. 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or package lead frame capacitance.
See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
10k
XTAL
10k
20 pF
See characterization data for desired device for variation of oscillator frequency due to VDD for given Rext/
Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values.
20 pF
Figure 9-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 9-5:
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-3 for
waveform).
FIGURE 9-6:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
RC OSCILLATOR MODE
V DD
Rext
OSC1
330 kΩ
330 kΩ
74AS04
74AS04
To Other
Devices
74AS04
PIC16CXXX
CLKIN
Cext
Internal
clock
PIC16CXXX
VSS
0.1 µF
Fosc/4
OSC2/CLKOUT
XTAL
DS30559A-page 58
Preliminary
1996 Microchip Technology Inc.
PIC16C64X & PIC16C66X
9.3
Reset
The PIC16CXXX differentiates between various kinds
of reset:
a)
b)
c)
d)
e)
f)
Power-on reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset (normal operation)
Brown-out Reset (BOR)
Parity Error Reset (PER)
A simplified block diagram of the on-chip reset circuit is
shown in Figure 9-7.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
FIGURE 9-7:
state” on Power-on reset, MCLR, WDT reset,
Brown-out Reset, Parity Error Reset, and on MCLR
reset during SLEEP. They are not affected by a WDT
wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different reset situations as indicated in
Table 9-4. These bits are used in software to determine
the nature of the reset. See Table 9-6 for a full description of reset states of all registers.
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 12-6 for pulse width
specification.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
MPEEN
Program
Memory
Parity
WDT SLEEP
Module
WDT Time-out
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 9-3 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1996 Microchip Technology Inc.
Preliminary
DS30559A-page 59
PIC16C64X & PIC16C66X
9.4
9.4.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST), Brown-out Reset (BOR),
and Parity Error Reset (PER)
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variations. See DC
parameters for details.
POWER-ON RESET (POR)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
9.4.3
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.6V to 1.8V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset. A maximum rise time for VDD
is required. See Electrical Specifications for details.
The OST time-out is invoked only for XT, LP, and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
delay on power-up only, from POR or BOR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as PWRT is active. The
PWRT delay allows VDD to rise to an acceptable level.
A configuration bit, PWRTE can disable (if set) or
enable (if cleared or programmed) the Power-up Timer.
The Power-up Timer should always be enabled when
Brown-out Reset is enabled.
FIGURE 9-8:
BROWN-OUT RESET (BOR)
PIC16C64X & PIC16C66X devices have on-chip
Brown-out Reset circuitry. A configuration bit, BODEN,
can disable (if clear/programmed) or enable (if set) the
Brown-out Reset circuitry. If VDD falls below 4.0V
(Parameter D005 in ES section) for greater than
parameter 35 in Table 12-6, the brown-out situation will
reset the chip. A reset is not guaranteed to occur if VDD
falls below 4.0V for less than parameter 35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will now be invoked and will
keep the chip in reset an additional 72 ms. If VDD drops
below BVDD while the Power-up Timer is running, the
chip will go back into a Brown-out Reset and the
Power-up Timer will be initialized. Once VDD rises
above BVDD, the Power-up Timer will execute a 72 ms
time delay. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-8
shows typical Brown-out situations.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting.”
9.4.2
OSCILLATOR START-UP TIMER (OST)
BROWN-OUT SITUATIONS
VDD
Internal
Reset
BVDD Max.
BVDD Min.
72 ms
VDD
Internal
Reset
BVDD Max.
BVDD Min.
