PIC16C71X
8-Bit CMOS Microcontrollers with A/D Converter
Devices included in this data sheet:
PIC16C71X Peripheral Features:
•
•
•
•
• Timer0: 8-bit timer/counter with 8-bit prescaler
• 8-bit multichannel analog-to-digital converter
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• 13 I/O Pins with Individual Direction Control
PIC16C710
PIC16C71
PIC16C711
PIC16C715
PIC16C71X Microcontroller Core Features:
710
71
711 715
Program Memory (EPROM)
x 14
512
1K
1K
2K
Data Memory (Bytes) x 8
36
36
68
128
I/O Pins
13
13
13
13
Timer Modules
1
1
1
1
A/D Channels
4
4
4
4
In-Circuit Serial Programming
Yes Yes Yes Yes
Brown-out Reset
Yes
—
Interrupt Sources
4
4
Yes Yes
4
4
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
•1
18
RA1/AN1
RA3/AN3/VREF
RA2/AN2
2
17
RA0/AN0
RA4/T0CKI
3
16
OSC1/CLKIN
MCLR/VPP
4
15
OSC2/CLKOUT
VSS
5
RB0/INT
6
RB1
RB2
7
8
RB3
14
VDD
13
RB7
12
11
RB6
RB5
9
10
RB4
SSOP
•1
20
RA1/AN1
RA3/AN3/VREF
RA2/AN2
2
19
RA0/AN0
RA4/T0CKI
3
18
OSC1/CLKIN
MCLR/VPP
4
VSS
5
VSS
6
RB0/INT
RB1
7
8
RB2
RB3
PIC16C710
PIC16C711
PIC16C715
1997 Microchip Technology Inc.
PIC16C7X Features
PIC16C710
PIC16C71
PIC16C711
PIC16C715
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 2K x 14 words of Program Memory,
up to 128 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• Wide operating voltage range: 2.5V to 6.0V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Program Memory Parity Error Checking Circuitry
with Parity Error Reset (PER) (PIC16C715)
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
17
OSC2/CLKOUT
16
VDD
15
VDD
14
13
RB7
RB6
9
12
RB5
10
11
RB4
DS30272A-page 1
PIC16C71X
Table of Contents
1.0 General Description .................................................................................................................................................................... 3
2.0 PIC16C71X Device Varieties...................................................................................................................................................... 5
3.0 Architectural Overview................................................................................................................................................................ 7
4.0 Memory Organization ............................................................................................................................................................... 11
5.0 I/O Ports.................................................................................................................................................................................... 25
6.0 Timer0 Module.......................................................................................................................................................................... 31
7.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 37
8.0 Special Features of the CPU .................................................................................................................................................... 47
9.0 Instruction Set Summary .......................................................................................................................................................... 69
10.0 Development Support ............................................................................................................................................................... 85
11.0 Electrical Characteristics for PIC16C710 and PIC16C711 ....................................................................................................... 89
12.0 DC and AC Characteristics Graphs and Tables for PIC16C710 and PIC16C711.................................................................. 101
13.0 Electrical Characteristics for PIC16C715................................................................................................................................ 111
14.0 DC and AC Characteristics Graphs and Tables for PIC16C715 ............................................................................................ 125
15.0 Electrical Characteristics for PIC16C71.................................................................................................................................. 135
16.0 DC and AC Characteristics Graphs and Tables for PIC16C71 .............................................................................................. 147
17.0 Packaging Information ............................................................................................................................................................ 155
Appendix A: ...................................................................................................................................................................................... 161
Appendix B: Compatibility................................................................................................................................................................. 161
Appendix C: What’s New .................................................................................................................................................................. 162
Appendix D: What’s Changed .......................................................................................................................................................... 162
Index .................................................................................................................................................................................................. 163
PIC16C71X Product Identification System......................................................................................................................................... 173
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30272A-page 2
1997 Microchip Technology Inc.
PIC16C71X
1.0
GENERAL DESCRIPTION
The PIC16C71X is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converters, in the
PIC16CXX mid-range family.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
PIC16CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C710/71 devices have 36 bytes of RAM, the
PIC16C711 has 68 bytes of RAM and the PIC16C715
has 128 bytes of RAM. Each device has 13 I/O pins. In
addition a timer/counter is available. Also a 4-channel
high-speed 8-bit A/D is provided. The 8-bit resolution is
ideally suited for applications requiring low-cost analog
interface, e.g. thermostat control, pressure sensing,
etc.
The PIC16C71X family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard
crystal, and the HS is for High Speed crystals. The
SLEEP (power-down) feature provides a power saving
mode. The user can wake up the chip from SLEEP
through several external and internal interrupts and
resets.
1997 Microchip Technology Inc.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
A UV erasable CERDIP packaged version is ideal for
code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production
in any volume.
The PIC16C71X family fits perfectly in applications
ranging from security and remote sensors to appliance
control and automotive. The EPROM technology
makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for
all applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC16C71X very versatile even in areas
where no microcontroller use has been considered
before (e.g. timer functions, serial communication, capture and compare, PWM functions and coprocessor
applications).
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).
1.2
Development Support
PIC16C71X devices are supported by the complete
line of Microchip Development tools.
Please refer to Section 10.0 for more details about
Microchip’s development tools.
DS30272A-page 3
PIC16C71X
TABLE 1-1:
PIC16C71X FAMILY OF DEVICES
PIC16C710
Clock
Memory
Memory
PIC16C72
PIC16CR72(1)
20
20
20
20
20
EPROM Program Memory
(x14 words)
512
1K
1K
2K
2K
—
ROM Program Memory
(14K words)
—
—
—
—
—
2K
Data Memory (bytes)
36
36
68
128
128
128
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
—
—
—
—
1
1
Serial Port(s)
(SPI/I2C, USART)
—
—
—
—
SPI/I2C
SPI/I2C
Parallel Slave Port
—
—
—
—
—
—
A/D Converter (8-bit) Channels 4
4
4
4
5
5
Interrupt Sources
4
4
4
4
8
8
I/O Pins
13
13
13
13
22
22
Voltage Range (Volts)
2.5-6.0
3.0-6.0
2.5-6.0
2.5-5.5
2.5-6.0
3.0-5.5
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
—
Yes
Yes
Yes
Yes
Packages
18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP,
SOIC;
SOIC
SOIC;
SOIC;
SOIC, SSOP SOIC, SSOP
20-pin SSOP
20-pin SSOP 20-pin SSOP
PIC16C74A
PIC16C76
PIC16C77
Maximum Frequency
of Operation (MHz)
20
20
20
20
EPROM Program Memory
(x14 words)
4K
4K
8K
8K
Data Memory (bytes)
192
192
376
376
Timer Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
2
2
2
2
Serial Port(s)
(SPI/I2C, USART)
SPI/I2C, USART
SPI/I2C, USART
SPI/I2C, USART
SPI/I2C, USART
Parallel Slave Port
—
Capture/Compare/PWM
Peripherals Module(s)
Features
PIC16C715
20
PIC16C73A
Clock
PIC16C711
Maximum Frequency
of Operation (MHz)
Capture/Compare/PWM
Peripherals Module(s)
Features
PIC16C71
Yes
—
Yes
A/D Converter (8-bit) Channels 5
8
5
8
Interrupt Sources
11
12
11
12
I/O Pins
22
33
22
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
Yes
Yes
Yes
Packages
28-pin SDIP,
SOIC
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
28-pin SDIP,
SOIC
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
DS30272A-page 4
1997 Microchip Technology Inc.
PIC16C71X
2.0
PIC16C71X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C71X Product Identification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For the PIC16C71X family, there are two device “types”
as indicated in the device number:
1.
2.
2.1
C, as in PIC16C71. These devices have
EPROM type memory and operate over the
standard voltage range.
LC, as in PIC16LC71. These devices have
EPROM type memory and operate over an
extended voltage range.
UV Erasable Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
Microchip's PICSTART Plus and PRO MATE II
programmers both support programming of the
PIC16C71X.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1997 Microchip Technology Inc.
DS30272A-page 5
PIC16C71X
NOTES:
DS30272A-page 6
1997 Microchip Technology Inc.
PIC16C71X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which,
program and data are accessed from separate memories using separate buses. This improves bandwidth
over traditional von Neumann architecture in which program and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35)
execute in a single cycle (200 ns @ 20 MHz) except for
program branches.
The table below lists program memory (EPROM) and
data memory (RAM) for each PIC16C71X device.
Device
PIC16C710
PIC16C71
PIC16C711
PIC16C715
Program
Memory
512 x 14
1K x 14
1K x 14
2K x 14
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
Data Memory
36 x 8
36 x 8
68 x 8
128 x 8
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function registers, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
1997 Microchip Technology Inc.
DS30272A-page 7
PIC16C71X
FIGURE 3-1:
Device
PIC16C71X BLOCK DIAGRAM
Program Memory Data Memory (RAM)
PIC16C710
PIC16C71
PIC16C711
PIC16C715
512 x 14
1K x 14
1K x 14
2K x 14
36 x 8
36 x 8
68 x 8
128 x 8
13
8
Data Bus
Program Counter
PORTA
EPROM
Program
Memory
Program
Bus
RAM
File
Registers
8 Level Stack
(13-bit)
14
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
RB0/INT
RB7:RB1
STATUS reg
8
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
ALU
8
W reg
Watchdog
Timer
Brown-out
Reset(2)
Timer0
MCLR
VDD, VSS
A/D
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C71.
DS30272A-page 8
1997 Microchip Technology Inc.
PIC16C71X
TABLE 3-1:
Pin Name
PIC16C710/71/711/715 PINOUT DESCRIPTION
DIP SSOP
Pin# Pin#(4)
SOIC
Pin#
I/O/P
Type
Buffer
Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input.
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
4
4
4
I/P
ST
Master
clear (reset) input or programming voltage input. This pin is
MCLR/VPP
an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
17
19
17
I/O
TTL
RA0 can also be analog input0
RA1/AN1
18
20
18
I/O
TTL
RA1 can also be analog input1
RA2/AN2
1
1
1
I/O
TTL
RA2 can also be analog input2
RA3/AN3/VREF
2
2
2
I/O
TTL
RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI
3
3
3
I/O
ST
RA4 can also be the clock input to the Timer0 module. Output is
open drain type.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0 can also be the external interrupt pin.
RB0/INT
6
7
6
I/O
TTL/ST(1)
RB1
7
8
7
I/O
TTL
RB2
8
9
8
I/O
TTL
RB3
9
10
9
I/O
TTL
RB4
10
11
10
I/O
TTL
Interrupt on change pin.
RB5
11
12
11
I/O
TTL
Interrupt on change pin.
RB6
12
13
12
I/O
TTL/ST(2)
Interrupt on change pin. Serial programming clock.
RB7
13
14
13
I/O
TTL/ST(2)
Interrupt on change pin. Serial programming data.
VSS
5
4, 6
5
P
—
Ground reference for logic and I/O pins.
VDD
14 15, 16
14
P
—
Positive supply for logic and I/O pins.
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: The PIC16C71 is not available in SSOP package.
OSC1/CLKIN
16
18
16
I
OSC2/CLKOUT
15
17
15
O
1997 Microchip Technology Inc.
DS30272A-page 9
PIC16C71X
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO) then
two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
1. MOVLW 55h
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
Tcy0
Tcy1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
Tcy2
Tcy3
Tcy4
Tcy5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30272A-page 10
1997 Microchip Technology Inc.
PIC16C71X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
The PIC16C71X family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The amount of program memory available to
each device is listed below:
PIC16C71/711 PROGRAM
MEMORY MAP AND STACK
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Program
Memory
Address Range
PIC16C710
512 x 14
0000h-01FFh
PIC16C71
1K x 14
0000h-03FFh
PIC16C711
1K x 14
0000h-03FFh
PIC16C715
2K x 14
0000h-07FFh
For those devices with less than 8K program memory,
accessing a location above the physically implemented
address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
Stack Level 8
User Memory
Space
Device
FIGURE 4-1:
FIGURE 4-2:
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
03FFh
PIC16C710 PROGRAM
MEMORY MAP AND STACK
0400h
PC
CALL, RETURN
RETFIE, RETLW
1FFFh
13
FIGURE 4-3:
PIC16C715 PROGRAM
MEMORY MAP AND STACK
Stack Level 1
PC
CALL, RETURN
RETFIE, RETLW
Stack Level 8
User Memory
Space
Reset Vector
0000h
13
Stack Level 1
Stack Level 8
Interrupt Vector
On-chip Program
Memory
0004h
0005h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
01FFh
0200h
1FFFh
On-chip Program
Memory
07FFh
0800h
1FFFh
1997 Microchip Technology Inc.
DS30272A-page 11
PIC16C71X
4.2
Data Memory Organization
The data memory is partitioned into two Banks which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
RP0 (STATUS) = 1 → Bank 1
RP0 (STATUS) = 0 → Bank 0
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers. Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR
(Section 4.5).
FIGURE 4-4:
PIC16C710/71 REGISTER FILE
MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
ADCON0
ADRES
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCON(2)
ADCON1
ADRES
PCLATH
INTCON
PCLATH
INTCON
General
Purpose
Register
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
Mapped
in Bank 0(3)
2Fh
AFh
30h
B0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
2: The PCON register is not implemented on the
PIC16C71.
3: These locations are unimplemented in Bank 1.
Any access to these locations will access the
corresponding Bank 0 register.
DS30272A-page 12
1997 Microchip Technology Inc.
PIC16C71X
FIGURE 4-5:
PIC16C711 REGISTER FILE
MAP
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
ADCON0
ADRES
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCON
ADCON1
ADRES
PCLATH
INTCON
PCLATH
INTCON
General
Purpose
Register
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
Mapped
in Bank 0(2)
4Fh
CFh
50h
D0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
2: These locations are unimplemented in Bank 1.
Any access to these locations will access the
corresponding Bank 0 register.
FIGURE 4-6:
PIC16C715 REGISTER FILE
MAP
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
ADRES
ADCON0
General
Purpose
Register
ADCON1
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
1997 Microchip Technology Inc.
DS30272A-page 13
PIC16C71X
4.2.2
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral features are described in the section of that peripheral
feature.
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
Address Name
PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(1)
Bank 0
00h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h(3)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h(3)
STATUS
04h(3)
FSR
RP1(5)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
05h
PORTA
06h
PORTB
07h
IRP(5)
—
—
—
—
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
---x 0000 ---u 0000
xxxx xxxx uuuu uuuu
Unimplemented
ADCS1
0001 1xxx 000q quuu
—
08h
ADCON0
ADCS0
(6)
09h(3)
ADRES
0Ah(2,3)
PCLATH
—
—
—
0Bh(3)
INTCON
GIE
ADIE
T0IE
CHS1
CHS0
GO/DONE
ADIF
ADON
—
00-0 0000 00-0 0000
xxxx xxxx uuuu uuuu
A/D Result Register
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
---0 0000 ---0 0000
RBIF
0000 000x 0000 000u
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
Bank 1
80h(3)
INDF
81h
OPTION
82h
(3)
PCL
(3)
STATUS
(3)
FSR
83h
84h
85h
TRISA
86h
TRISB
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(5)
(5)
RP1
RP0
TO
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
—
—
1111 1111 1111 1111
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
---1 1111 ---1 1111
PORTB Data Direction Control Register
1111 1111 1111 1111
87h(4)
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
88h
ADCON1
—
—
—
—
—
—
PCFG1
PCFG0
---- --00 ---- --00
89h(3)
xxxx xxxx uuuu uuuu
A/D Result Register
PCLATH
—
—
—
(3)
INTCON
GIE
ADIE
T0IE
8Ah
8Bh
ADRES
(2,3)
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
---0 0000 ---0 0000
0000 000x
0000 000u
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter.
3: These registers can be addressed from either bank.
4: The PCON register is not physically implemented in the PIC16C71, read as ’0’.
5: The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear.
6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented,
read as '0'.
DS30272A-page 14
1997 Microchip Technology Inc.
PIC16C71X
TABLE 4-2:
Address Name
PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR, PER
Value on all
other resets
(3)
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h(1)
PCL
Program Counter's (PC) Least Significant Byte
03h(1)
STATUS
04h(1)
FSR
05h
PORTA
06h
PORTB
IRP(4)
RP1(4)
RP0
TO
0000 0000 0000 0000
PD
Z
DC
C
0001 1xxx 000q quuu
PORTA Data Latch when written: PORTA pins when read
---x 0000 ---u 0000
Indirect data memory address pointer
—
—
—
xxxx xxxx uuuu uuuu
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
(1,2)
0Ah
PCLATH
—
—
—
0Bh(1)
INTCON
GIE
PEIE
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
—
ADIF
—
—
—
—
—
—
-0-- ---- -0-- ----
---0 0000 ---0 0000
0Dh
—
Unimplemented
—
—
0Eh
—
Unimplemented
—
—
0Fh
—
Unimplemented
—
—
10h
—
Unimplemented
—
—
11h
—
Unimplemented
—
—
12h
—
Unimplemented
—
—
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
—
Unimplemented
—
—
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRES
1Fh
ADCON0
A/D Result Register
ADCS1
ADCS0
xxxx xxxx uuuu uuuu
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.
1997 Microchip Technology Inc.
DS30272A-page 15
PIC16C71X
TABLE 4-2:
Address Name
PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR, PER
Value on all
other resets
(3)
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
83h
STATUS
84h(1)
FSR
(4)
IRP
(4)
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
85h
TRISA
86h
TRISB
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
—
Unimplemented
—
—
89h
8Ah(1,2)
—
1111 1111 1111 1111
0000 0000 0000 0000
Indirect data memory address pointer
—
0000 0000 0000 0000
PORTA Data Direction Register
--11 1111 --11 1111
PORTB Data Direction Register
PCLATH
—
8Bh(1)
INTCON
8Ch
PIE1
1111 1111 1111 1111
—
—
Write Buffer for the upper 5 bits of the PC
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
—
ADIE
—
—
—
—
—
—
-0-- ---- -0-- ----
—
—
—
PER
POR
BOR
u--- -1qq u--- -1uu
---0 0000 ---0 0000
8Dh
—
8Eh
PCON
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
---- --00
---- --00
9Fh
ADCON1
Unimplemented
MPEEN
—
—
—
—
—
—
—
—
PCFG1
PCFG0
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.
DS30272A-page 16
1997 Microchip Technology Inc.
PIC16C71X
4.2.2.1
STATUS REGISTER
Applicable Devices
710 71 711 715
The STATUS register, shown in Figure 4-7, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
Note 1: For those devices that do not use bits IRP
and RP1 (STATUS), maintain these
bits clear to ensure upward compatibility
with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
FIGURE 4-7:
R/W-0
IRP
bit7
bit 7:
STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
1997 Microchip Technology Inc.
DS30272A-page 17
PIC16C71X
4.2.2.2
OPTION REGISTER
Applicable Devices
Note:
710 71 711 715
The OPTION register is a readable and writable register which contains various control bits to configure the
TMR0/WDT prescaler, the External INT Interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-8:
R/W-1
RBPU
bit7
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer by setting bit PSA
(OPTION).
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R/W-1
PS0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS30272A-page 18
1997 Microchip Technology Inc.
PIC16C71X
4.2.2.3
INTCON REGISTER
Applicable Devices
Note:
710 71 711 715
The INTCON Register is a readable and writable register which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
FIGURE 4-9:
R/W-0
GIE
bit7
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
ADIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
GIE:(1) Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables A/D interrupt
0 = Disables A/D interrupt
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: For the PIC16C71, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 8.5
for a detailed description.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
1997 Microchip Technology Inc.
DS30272A-page 19
PIC16C71X
4.2.2.4
PIE1 REGISTER
Applicable Devices
Note:
710 71 711 715
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
Peripheral interrupts.
FIGURE 4-10: PIE1 REGISTER (ADDRESS 8Ch)
U-0
—
bit7
R/W-0
ADIE
U-0
—
U-0
—
U-0
—
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
U-0
—
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
DS30272A-page 20
1997 Microchip Technology Inc.
PIC16C71X
4.2.2.5
PIR1 REGISTER
Applicable Devices
Note:
710 71 711 715
This register contains the individual flag bits for the
Peripheral interrupts.
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
FIGURE 4-11: PIR1 REGISTER (ADDRESS 0Ch)
U-0
—
bit7
R/W-0
ADIF
U-0
—
U-0
—
U-0
—
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
U-0
—
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-0: Unimplemented: Read as '0'
1997 Microchip Technology Inc.
DS30272A-page 21
PIC16C71X
4.2.2.6
PCON REGISTER
Applicable Devices
Note:
710 71 711 715
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset
(BOR) condition from a Power-on Reset condition. For
the PIC16C715 the PCON register also contains status
bits MPEEN and PER. MPEEN reflects the value of the
MPEEN bit in the configuration word. PER indicates a
parity error reset has occurred.
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
clear, indicating a brown-out has occurred.
The BOR status bit is a don't care and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
FIGURE 4-12: PCON REGISTER (ADDRESS 8Eh), PIC16C710/711
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
POR
bit7
R/W-q
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh), PIC16C715
R-U
MPEEN
bit7
bit 7:
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
PER
R/W-0
POR
R/W-q
BOR(1)
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
MPEEN: Memory Parity Error Circuitry Status bit
Reflects the value of configuration word bit, MPEEN
bit 6-3: Unimplemented: Read as '0'
bit 2:
PER: Memory Parity Error Reset Status bit
1 = No Error occurred
0 = Program Memory Fetch Parity Error occurred (must be set in software after a Parity Error Reset)
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS30272A-page 22
1997 Microchip Technology Inc.
PIC16C71X
4.3
PCL and PCLATH
4.3.2
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the
PC will be cleared. Figure 4-14 shows the two situations for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to
PCL (PCLATH → PCH). The lower example in the
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH → PCH).
FIGURE 4-14: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
8
7
0
PC
5
8
PCLATH
Instruction with
PCL as
Destination
ALU
PCLATH
PCH
12
11 10
PCL
8
GOTO, CALL
PCLATH
11
Opcode
PCLATH
4.3.1
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
4.4
0
7
PC
2
The PIC16CXX family has an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
PCL
12
STACK
Program Memory Paging
The PIC16C71X devices ignore both paging bits
(PCLATH, which are used to access program
memory when more than one page is available. The
use of PCLATH as general purpose read/write
bits for the PIC16C71X is not recommended since this
may affect upward compatibility with future products.
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
1997 Microchip Technology Inc.
DS30272A-page 23
PIC16C71X
4.5
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt service routine (if interrupts are used).
EXAMPLE 4-1:
ORG 0x500
BSF
PCLATH,3
BCF
PCLATH,4
CALL
SUB1_P1
:
:
:
ORG 0x900
SUB1_P1:
:
:
RETURN
Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS), as shown in Figure 4-15. However, IRP
is not used in the PIC16C71X devices.
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh)
;Only on >4K devices
;Call subroutine in
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
;return to Call subroutine
;in page 0 (000h-7FFh)
EXAMPLE 4-2:
movlw
movwf
clrf
incf
btfss
goto
NEXT
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
FIGURE 4-15:
;yes continue
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
RP1:RP0
6
bank select
location select
(1)
0
IRP
7
bank select
00
00h
01
80h
10
FSR register
0
location select
11
100h
180h
Not
Used
Data
Memory
7Fh
FFh
Bank 0
Bank 1
17Fh
Bank 2
1FFh
Bank 3
For register file map detail see Figure 4-4.
Note 1:
The RP1 and IRP bits are reserved, always maintain these bits clear.
DS30272A-page 24
1997 Microchip Technology Inc.
PIC16C71X
5.0
I/O PORTS
Applicable Devices
FIGURE 5-1:
710 71 711 715
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1
BLOCK DIAGRAM OF
RA3:RA0 PINS
Data
bus
D
Q
VDD
WR
Port
Q
CK
Data Latch
PORTA is a 5-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers) which can configure
these pins as output or input.
D
WR
TRIS
TRIS Latch
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
To A/D Converter
On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 5-1:
STATUS, RP0
PORTA
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISA
Q
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTA by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA as inputs
RA as outputs
TRISA are always
read as '0'.
D
EN
Note 1: I/O pins have protection diodes to VDD and
VSS.
FIGURE 5-2:
Data
bus
WR
PORT
BLOCK DIAGRAM OF RA4/
T0CKI PIN
D
Q
CK
Q
N
I/O pin(1)
Data Latch
INITIALIZING PORTA
BCF
CLRF
TTL
input
buffer
RD TRIS
RD PORT
I/O pin(1)
VSS
Analog
input
mode
Q
CK
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
N
Q
Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Note:
P
PORTA and TRISA Registers
WR
TRIS
D
Q
CK
Q
VSS
Schmitt
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
1997 Microchip Technology Inc.
DS30272A-page 25
PIC16C71X
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Function
Input/output or analog input
Input/output or analog input
Input/output or analog input
Input/output or analog input/VREF
Input/output or external clock input for Timer0
Output is open drain type
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name
05h
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RA4
RA3
RA2
RA1
RA0
---x 0000
---u 0000
---1 1111
---1 1111
PCFG1
PCFG0
---- --00
---- --00
PORTA
—
—
—
85h
TRISA
—
—
—
9Fh
ADCON1
—
—
—
PORTA Data Direction Register
—
—
—
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS30272A-page 26
1997 Microchip Technology Inc.
PIC16C71X
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
EXAMPLE 5-2:
INITIALIZING PORTB
BCF
CLRF
STATUS, RP0
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 5-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
Data bus
WR Port
weak
P pull-up
Data Latch
D
Q
I/O
pin(1)
CK
TRIS Latch
D
Q
WR TRIS
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, "Implementing Wake-Up on Key
Stroke" (AN552).
Note:
VDD
RBPU(2)
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON).
For the PIC16C71
if a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then interrupt flag bit
RBIF may not get set.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
TTL
Input
Buffer
CK
RD TRIS
Q
RD Port
D
EN
RB0/INT
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = ’1’ enables weak pull-up if
RBPU = ’0’ (OPTION).
1997 Microchip Technology Inc.
DS30272A-page 27
PIC16C71X
FIGURE 5-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
(PIC16C71)
FIGURE 5-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
(PIC16C710/711/715)
VDD
RBPU(2)
VDD
weak
P pull-up
Data Latch
D
Q
Data bus
WR Port
RBPU(2)
Data bus
I/O
pin(1)
CK
WR Port
TRIS Latch
D
Q
WR TRIS
weak
P pull-up
Data Latch
D
Q
I/O
pin(1)
CK
TRIS Latch
D
Q
TTL
Input
Buffer
CK
RD TRIS
Q
WR TRIS
ST
Buffer
RD TRIS
Latch
D
Q
EN
RD Port
TTL
Input
Buffer
CK
Latch
D
EN
RD Port
Set RBIF
ST
Buffer
Q1
Set RBIF
From other
RB7:RB4 pins
Q
D
From other
RB7:RB4 pins
Q
D
RD Port
EN
EN
RD Port
RB7:RB6 in serial programming mode
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = ’1’ enables weak pull-up if
RBPU = ’0’ (OPTION).
Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = ’1’ enables weak pull-up if
RBPU = ’0’ (OPTION).
TABLE 5-3:
Name
Q3
PORTB FUNCTIONS
Bit#
Buffer
Function
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6
bit6
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7
bit7
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
RB0/INT
bit0
DS30272A-page 28
1997 Microchip Technology Inc.
PIC16C71X
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
06h, 106h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
86h, 186h
TRISB
1111 1111
1111 1111
81h, 181h
OPTION
1111 1111
1111 1111
PORTB Data Direction Register
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
1997 Microchip Technology Inc.
DS30272A-page 29
PIC16C71X
5.3
I/O Programming Considerations
5.3.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-3:
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched to an output, the content of the data
latch may now be unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-3 shows the effect of two sequential readmodify-write instructions on an I/O port.
FIGURE 5-6:
;Initial PORT settings: PORTB Inputs
;
PORTB Outputs
;PORTB have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------BCF PORTB, 7
; 01pp pppp
11pp pppp
BCF PORTB, 6
; 10pp pppp
11pp pppp
BSF STATUS, RP0 ;
BCF TRISB, 7
; 10pp pppp
11pp pppp
BCF TRISB, 6
; 10pp pppp
10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-6). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file
to be read into the CPU is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
PC
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
PC + 2
PC + 3
NOP
NOP
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Instruction
executed
NOP
MOVWF PORTB
write to
PORTB
DS30272A-page 30
Note:
MOVF PORTB,W
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
1997 Microchip Technology Inc.
PIC16C71X
6.0
TIMER0 MODULE
Applicable Devices
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 6.2.
710 71 711 715
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit
PSA (OPTION). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 6.3 details the operation
of the prescaler.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
6.1
Timer mode is selected by clearing bit T0CS
(OPTION). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 6-2 and
Figure 6-3). The user can work around this by writing
an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Source Edge Select bit T0SE (OPTION). Clearing
FIGURE 6-1:
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON). The interrupt can be masked by
clearing bit T0IE (INTCON). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP. See
Figure 6-4 for Timer0 interrupt timing.
TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
PSout
1
Sync with
Internal
clocks
1
Programmable
Prescaler
RA4/T0CKI
pin
8
0
TMR0
PSout
(2 cycle delay)
T0SE
3
Set interrupt
flag bit T0IF
on overflow
PSA
PS2, PS1, PS0
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION).
2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).
FIGURE 6-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
T0
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0+1
Instruction
Executed
1997 Microchip Technology Inc.
PC+2
MOVF TMR0,W
PC+3
MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
Read TMR0
reads NT0 + 1
NT0+2
T0
Read TMR0
reads NT0 + 2
DS30272A-page 31
PIC16C71X
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
PC+3
Instruction
Execute
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
NT0+1
NT0
Write TMR0
executed
FIGURE 6-4:
PC+4
MOVF TMR0,W
T0+1
T0
TMR0
PC+2
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
T0IF bit
(INTCON)
FFh
00h
01h
02h
1
1
GIE bit
(INTCON)
INSTRUCTION
FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS30272A-page 32
1997 Microchip Technology Inc.
PIC16C71X
6.2
Using Timer0 with an External Clock
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the
desired device.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
6.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay
from the external clock edge to the timer incrementing.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1997 Microchip Technology Inc.
DS30272A-page 33
PIC16C71X
6.3
Prescaler
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF
1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler is not readable or writable.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 6-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
The PSA and PS2:PS0 bits (OPTION) determine
the prescaler assignment and prescale ratio.
FIGURE 6-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION).
DS30272A-page 34
1997 Microchip Technology Inc.
PIC16C71X
6.3.1
SWITCHING PRESCALER ASSIGNMENT
Note:
The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program
execution.
EXAMPLE 6-1:
BCF
CLRF
BSF
CLRWDT
MOVLW
MOVWF
BCF
To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 6-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must be
followed even if the WDT is disabled.
CHANGING PRESCALER (TIMER0→WDT)
STATUS, RP0
TMR0
STATUS, RP0
b'xxxx1xxx'
OPTION_REG
STATUS, RP0
;Bank 0
;Clear TMR0 & Prescaler
;Bank 1
;Clears WDT
;Selects new prescale value
;and assigns the prescaler to the WDT
;Bank 0
To change prescaler from the WDT to the Timer0
module use the sequence shown in Example 6-2.
EXAMPLE 6-2:
CLRWDT
BSF
MOVLW
MOVWF
BCF
CHANGING PRESCALER (WDT→TIMER0)
STATUS, RP0
b'xxxx0xxx'
OPTION_REG
STATUS, RP0
TABLE 6-1:
;Clear WDT and prescaler
;Bank 1
;Select TMR0, new prescale value and
;clock source
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Address
Name
Bit 7
Bit 6
01h
TMR0
0Bh,8Bh,
INTCON
81h
OPTION RBPU INTEDG
85h
TRISA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
—
ADIE
—
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
---1 1111
---1 1111
—
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1997 Microchip Technology Inc.
DS30272A-page 35
PIC16C71X
NOTES:
DS30272A-page 36
1997 Microchip Technology Inc.
PIC16C71X
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
Applicable Devices
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
710 71 711 715
The A/D module has three registers. These registers
are:
The analog-to-digital (A/D) converter module has four
analog inputs.
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s positive supply voltage (VDD)
or the voltage level on the RA3/AN3/VREF pin.
FIGURE 7-1:
The ADCON0 register, shown in Figure 7-1 and
Figure 7-2, controls the operation of the A/D module.
The ADCON1 register, shown in Figure 7-3 configures
the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.
ADCON0 REGISTER (ADDRESS 08h), PIC16C710/71/711
R/W-0 R/W-0
ADCS1 ADCS0
U-0
— (1)
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE
bit7
R/W-0
ADIF
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n =Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an RC oscillation)
bit 5:
Unimplemented: Read as '0'.
bit 4-3: CHS1:CHS0: Analog Channel Select bits
00 = channel 0, (RA0/AN0)
01 = channel 1, (RA1/AN1)
10 = channel 2, (RA2/AN2)
11 = channel 3, (RA3/AN3)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1:
ADIF: A/D Conversion Complete Interrupt Flag bit
1 = conversion is complete (must be cleared in software)
0 = conversion is not complete
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is
unimplemented, read as '0'.
1997 Microchip Technology Inc.
DS30272A-page 37
PIC16C71X
FIGURE 7-2:
ADCON0 REGISTER (ADDRESS 1Fh), PIC16C715
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
—
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE
U-0
—
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an RC oscillation)
bit 5:
Unused
bit 6-3: CHS1:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 0, (RA0/AN0)
101 = channel 1, (RA1/AN1)
110 = channel 2, (RA2/AN2)
111 = channel 3, (RA3/AN3)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)
bit 1:
Unimplemented: Read as '0'
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
FIGURE 7-3:
U-0
—
bit7
ADCON1 REGISTER, PIC16C710/71/711 (ADDRESS 88h),
PIC16C715 (ADDRESS 9Fh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PCFG1
R/W-0
PCFG0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n =Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1-0: PCFG1:PCFG0: A/D Port Configuration Control bits
PCFG1:PCFG0
00
01
10
11
RA1 & RA0
A
A
A
D
RA2
A
A
D
D
RA3
A
VREF
D
D
VREF
VDD
RA3
VDD
VDD
A = Analog input
D = Digital I/O
DS30272A-page 38
1997 Microchip Technology Inc.
PIC16C71X
2.
The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 7-4.
3.
4.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 7.1.
After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:
1.
5.
OR
6.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 7-4:
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
7.
• Waiting for the A/D interrupt
Read A/D Result register (ADRES), clear bit
ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
A/D BLOCK DIAGRAM
CHS1:CHS0
11
VIN
RA3/AN3/VREF
10
(Input voltage)
RA2/AN2
01
A/D
Converter
RA1/AN1
00
RA0/AN0
VDD
00 or
10 or
11
VREF
(Reference
voltage)
01
PCFG1:PCFG0
1997 Microchip Technology Inc.
DS30272A-page 39
PIC16C71X
7.1
A/D Acquisition Requirements
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-5. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 7-5. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for analog sources is 10 kΩ. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, Equation 71 may be used. This equation calculates the acquisition
time to within 1/2 LSb error is used (512 steps for the
A/D). The 1/2 LSb error is the maximum error allowed
for the A/D to meet its specified accuracy.
EQUATION 7-1:
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specification.
Note 4: After a conversion has completed, a
2.0TAD delay must complete before acquisition can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
EXAMPLE 7-1:
CALCULATING THE
MINIMUM REQUIRED
AQUISITION TIME
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
A/D MINIMUM CHARGING
TIME
Temperature Coefficient
VHOLD = (VREF - (VREF/512)) • (1 - e(-TCAP/CHOLD(RIC + RSS + RS)))
TACQ = 5 µs + TCAP + [(Temp - 25°C)(0.05 µs/°C)]
Given: VHOLD = (VREF/512), for 1/2 LSb resolution
TCAP = -CHOLD (RIC + RSS + RS) ln(1/511)
The above equation reduces to:
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
TCAP = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
-51.2 pF (18 kΩ) ln(0.0020)
Example 7-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
-0.921 µs (-6.2364)
5.747 µs
TACQ = 5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]
CHOLD = 51.2 pF
10.747 µs + 1.25 µs
Rs = 10 kΩ
11.997 µs
1/2 LSb error
VDD = 5V → Rss = 7 kΩ
Temp (application system max.) = 50°C
VHOLD = 0 @ t = 0
FIGURE 7-5:
ANALOG INPUT MODEL
VDD
Rs
ANx
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS RSS
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
DS30272A-page 40
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
1997 Microchip Technology Inc.
PIC16C71X
7.2
Selecting the A/D Conversion Clock
7.3
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•
•
•
•
The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
2TOSC
8TOSC
32TOSC
Internal RC oscillator
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of:
2.0 µs for the PIC16C71
1.6 µs for all other PIC16C71X devices
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to consume current that is out of the devices
specification.
Table 7-1 and Table 7-2 and show the resultant TAD
times derived from the device operating frequencies
and the A/D clock source selected.
TABLE 7-1:
TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C71
AD Clock Source (TAD)
Operation
Configuring Analog Port Pins
Device Frequency
ADCS1:ADCS0
20 MHz
16 MHz
4 MHz
1 MHz
333.33 kHz
00
100 ns(2)
125 ns(2)
6 µs
8TOSC
01
400
ns(2)
500 ns(2)
2.0 µs
2.0 µs
ns(2)
8.0 µs
24 µs(3)
32TOSC
10
1.6 µs(2)
8.0 µs
32.0 µs(3)
96 µs(3)
2TOSC
RC(5)
5:
2-6
2-6
2-6
2 - 6 µs(1)
2 - 6 µs
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 4 µs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep operation only.
For extended voltage devices (LC), please refer to Electrical Specifications section.
TABLE 7-2:
µs(1,4)
(1,4)
11
Legend:
Note 1:
2:
3:
4:
500
2.0 µs
ADCS1:ADCS0
Device Frequency
20 MHz
2TOSC
00
100
8TOSC
01
400 ns(2)
1.6 µs
32TOSC
µs(1)
TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C710/711, PIC16C715
AD Clock Source (TAD)
Operation
µs(1,4)
10
ns(2)
5 MHz
1.25 MHz
333.33 kHz
400
1.6 µs
1.6 µs
6 µs
6.4 µs
24 µs(3)
6.4 µs
25.6 µs
96 µs(3)
ns(2)
(3)
2 - 6 µs(1,4)
2 - 6 µs(1,4)
2 - 6 µs(1)
2 - 6 µs(1,4)
Shaded cells are outside of recommended range.
The RC source has a typical TAD time of 4 µs.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep operation only.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
RC(5)
Legend:
Note 1:
2:
3:
4:
11
1997 Microchip Technology Inc.
DS30272A-page 41
PIC16C71X
7.4
A/D Conversions
Example 7-2 shows how to perform an A/D conversion.
The RA pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC.
The conversion is performed on the RA0 pin (channel
0).
EXAMPLE 7-2:
BSF
CLRF
BCF
MOVLW
MOVWF
BSF
BSF
;
;
;
;
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed
conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started
on the selected channel.
A/D CONVERSION
STATUS,
ADCON1
STATUS,
0xC1
ADCON0
INTCON,
INTCON,
RP0
RP0
ADIE
GIE
;
;
;
;
;
;
;
Select Bank 1
Configure A/D inputs
Select Bank 0
RC Clock, A/D is on, Channel 0 is selected
Enable A/D Interrupt
Enable all interrupts
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
:
ADCON0, GO
DS30272A-page 42
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
; is cleared upon completion of the A/D Conversion.
1997 Microchip Technology Inc.
PIC16C71X
7.4.1
FASTER CONVERSION - LOWER
RESOLUTION TRADE-OFF
Not all applications require a result with 8-bits of resolution, but may instead require a faster conversion time.
The A/D module allows users to make the trade-off of
conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same. To
speed up the conversion, the clock source of the A/D
module may be switched so that the TAD time violates
the minimum specified time (see the applicable electrical specification). Once the TAD time violates the minimum specified time, all the following A/D result bits are
not valid (see A/D Conversion Timing in the Electrical
Specifications section.) The clock sources may only be
switched between the three oscillator versions (cannot
be switched from/to RC). The equation to determine
the time before the oscillator can be switched is as
follows:
Since the TAD is based from the device oscillator, the
user must use some method (a timer, software loop,
etc.) to determine when the A/D oscillator may be
changed. Example 7-3 shows a comparison of time
required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. The example is for
devices operating at 20 MHz and 16 MHz (The A/D
clock is programmed for 32TOSC), and assumes that
immediately after 6TAD, the A/D clock is programmed
for 2TOSC.
The 2TOSC violates the minimum TAD time since the
last 4-bits will not be converted to correct values.
Conversion time = 2TAD + N • TAD + (8 - N)(2TOSC)
Where: N = number of bits of resolution required.
EXAMPLE 7-3:
4-BIT vs. 8-BIT CONVERSION TIMES
Freq. (MHz)(1)
TAD
TOSC
2TAD + N • TAD + (8 - N)(2TOSC)
20
16
20
16
20
16
Resolution
4-bit
8-bit
1.6 µs
2.0 µs
50 ns
62.5 ns
10 µs
12.5 µs
1.6 µs
2.0 µs
50 ns
62.5 ns
16 µs
20 µs
Note 1: The PIC16C71 has a minimum TAD time of 2.0 µs.
All other PIC16C71X devices have a minimum TAD time of 1.6 µs.
1997 Microchip Technology Inc.
DS30272A-page 43
PIC16C71X
7.5
A/D Operation During Sleep
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
7.6
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruction that sets the GO/DONE bit.
A/D Accuracy/Error
The absolute accuracy specified for the A/D converter
includes the sum of all contributions for quantization
error, integral error, differential error, full scale error, offset error, and monotonicity. It is defined as the maximum deviation from an actual transition versus an ideal
transition for any code. The absolute error of the A/D
converter is specified at < ±1 LSb for VDD = VREF (over
the device’s specified operating range). However, the
accuracy of the A/D converter will degrade as VDD
diverges from VREF.
For a given range of analog inputs, the output digital
code will be the same. This is due to the quantization of
the analog input to a digital code. Quantization error is
typically ± 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to increase the resolution of the A/D
converter.
Offset error measures the first actual transition of a
code versus the first ideal transition of a code. Offset
error shifts the entire transfer function. Offset error can
be calibrated out of a system or introduced into a system through the interaction of the total leakage current
and source impedance at the analog input.
full scale error is that full scale does not take offset error
into account. Gain error can be calibrated out in software.
Linearity error refers to the uniformity of the code
changes. Linearity errors cannot be calibrated out of
the system. Integral non-linearity error measures the
actual code transition versus the ideal code transition
adjusted by the gain error for each code.
Differential non-linearity measures the maximum
actual code width versus the ideal code width. This
measure is unadjusted.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be
≤ 8 µs for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock transitions. This reduces, to a large extent,
the effects of digital switching noise. This is not possible
with the RC derived clock. The loss of accuracy due to
digital switching noise can be significant if many I/O
pins are active.
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
7.7
Effects of a RESET
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted.
The value that is in the ADRES register is not modified
for a Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
7.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conversion is out of specification.
Note:
Care must be taken when using the RA0
pin in A/D conversions due to its proximity
to the OSC1 pin.
An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
Gain error measures the maximum deviation of the last
actual transition and the last ideal transition adjusted
for offset error. This error appears as a change in slope
of the transfer function. The difference in gain error to
DS30272A-page 44
1997 Microchip Technology Inc.
PIC16C71X
7.9
Transfer Function
FIGURE 7-6:
A/D TRANSFER FUNCTION
The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input
voltage (VAIN) is Analog VREF/256 (Figure 7-6).
References
Digital code output
7.10
A very good reference for understanding A/D converters is the "Analog-Digital Conversion Handbook" third
edition, published by Prentice Hall (ISBN 0-13-032848-0).
FFh
FEh
04h
03h
02h
01h
256 LSb
(full scale)
255 LSb
4 LSb
3 LSb
2 LSb
0.5 LSb
1 LSb
00h
Analog input voltage
FIGURE 7-7:
FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
A/D Clock
= RC?
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
GO = 0
ADIF = 1
No
No
Device in
SLEEP?
SLEEP Yes
Instruction?
Yes
Abort Conversion
GO = 0
ADIF = 0
Finish Conversion
GO = 0
ADIF = 1
Wait 2 TAD
No
No
Finish Conversion
GO = 0
ADIF = 1
Wake-up Yes
From Sleep?
SLEEP
Power-down A/D
Wait 2 TAD
Stay in Sleep
Power-down A/D
Wait 2 TAD
1997 Microchip Technology Inc.
DS30272A-page 45
PIC16C71X
TABLE 7-3:
Address
REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C710/71/711
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
ADIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
xxxx xxxx
uuuu uuuu
0Bh,8Bh
INTCON
89h
ADRES
A/D Result Register
08h
ADCON0
ADCS1 ADCS0
—
CHS1
CHS0
GO/DONE
ADIF
ADON
00-0 0000
00-0 0000
88h
ADCON1
—
—
—
—
—
—
PCFG1
PCFG0
---- --00
---- --00
05h
PORTA
—
—
—
RA4
RA3
RA2
RA1
RA0
---x 0000
---u 0000
---1 1111
---1 1111
85h
TRISA
—
—
— PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
TABLE 7-4:
REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C715
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
0Bh/8Bh INTCON
PIR1
0Ch
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
—
ADIF
—
—
—
—
—
—
-0-- ----
-0-- ----
—
ADIE
—
—
—
—
—
—
-0-- ----
-0-- ----
xxxx xxxx
uuuu uuuu
0000 00-0
0000 00-0
PCFG0 ---- --00
---- --00
8Ch
PIE1
1Eh
ADRES
A/D Result Register
1Fh
ADCON
0
ADCON
1
ADCS
1
—
ADCS
0
—
CHS2
CHS1
CHS0
—
—
PORTA
—
—
—
RA4
—
—
9Fh
05h
85h
TRISA
TRISA4
—
PCFG1
RA3
RA2
RA1
ADON
---x 0000
---u 0000
TRISA1 TRISA0 ---1 1111
---1 1111
RA0
TRISA
TRISA2
3
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
DS30272A-page 46
—
—
GO/
DONE
—
1997 Microchip Technology Inc.
PIC16C71X
8.0
SPECIAL FEATURES OF THE
CPU
Applicable Devices
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
710 71 711 715
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection. These are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
(PIC16C710/711/715)
- Parity Error Reset (PER) (PIC16C715)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
8.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
The PIC16CXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
FIGURE 8-1:
—
—
CONFIGURATION WORD FOR PIC16C71
—
—
—
—
—
—
—
CP0
bit13
PWRTE WDTE FOSC1 FOSC0
bit0
Register:
Address
CONFIG
2007h
bit 13-5: Unimplemented: Read as '1'
bit 4:
CP0: Code protection bit
1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
bit 3:
PWRTE: Power-up Timer Enable bit
1 = Power-up Timer enabled
0 = Power-up Timer disabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
1997 Microchip Technology Inc.
DS30272A-page 47
PIC16C71X
FIGURE 8-2:
CP0
CP0
CONFIGURATION WORD, PIC16C710/711
CP0
CP0
CP0
CP0
CP0
BODEN
CP0
CP0
bit13
PWRTE WDTE FOSC1 FOSC0
bit0
Register:
Address
CONFIG
2007h
bit 13-7 CP0: Code protection bits (2)
5-4: 1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.
FIGURE 8-3:
CP1
CP0
CONFIGURATION WORD, PIC16C715
CP1
CP0
CP1
CP0 MPEEN BODEN
CP1
CP0
bit13
PWRTE WDTE FOSC1 FOSC0
bit0
bit 13-8
5-4:
CP1:CP0: Code Protection bits (2)
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7:
MPEEN: Memory Parity Error Enable
1 = Memory Parity Checking is enabled
0 = Memory Parity Checking is disabled
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Register:
Address
CONFIG
2007h
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
DS30272A-page 48
1997 Microchip Technology Inc.
PIC16C71X
8.2
Oscillator Configurations
8.2.1
OSCILLATOR TYPES
TABLE 8-1:
The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
8.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
Ranges Tested:
Mode
XT
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
C2
(2)
47 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
10 - 47 pF
To internal
logic
See Table 8-1 and Table 8-1 for recommended values of
C1 and C2.
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
TABLE 8-2:
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR,
PIC16C71
Mode
Freq
OSC1
OSC2
LP
32 kHz
200 kHz
100 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
20 MHz
33 - 68 pF
15 - 47 pF
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
15 - 47 pF
15 - 47 pF
33 - 68 pF
15 - 47 pF
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
15 - 47 pF
15 - 47 pF
SLEEP
PIC16CXXX
OSC2
47 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
10 - 47 pF
All resonators used did not have built-in capacitors.
C1
RS
Note1
OSC2
Resonators Used:
XT
OSC1
RF
OSC1
These values are for design guidance only. See
notes at bottom of page.
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 8-4). The
PIC16CXX Oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 8-5).
XTAL
Freq
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
HS
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
FIGURE 8-4:
CERAMIC RESONATORS,
PIC16C71
HS
These values are for design guidance only. See
notes at bottom of page.
Note 1: A series resistor may be required for AT strip
cut crystals.
2: The buffer is on the OSC2 pin.
FIGURE 8-5:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
Clock from
ext. system
PIC16CXXX
Open
OSC2
1997 Microchip Technology Inc.
DS30272A-page 49
PIC16C71X
TABLE 8-3:
CERAMIC RESONATORS,
PIC16C710/711/715
TABLE 8-4:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR,
PIC16C710/711/715
Ranges Tested:
Mode
XT
Freq
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
HS
OSC1
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
OSC2
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
Osc Type
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
LP
32 kHz
33 pF
33 pF
XT
HS
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
All resonators used did not have built-in capacitors.
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
These values are for design guidance only. See
notes at bottom of page.
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
Note 1: Recommended values of C1 and C2 are identical to the ranges tested table.
2: Higher capacitance increases the stability of oscillator but also increases the start-up time.
3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification.
DS30272A-page 50
1997 Microchip Technology Inc.
PIC16C71X
8.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types of
crystal oscillator circuits can be used; one with series
resonance, or one with parallel resonance.
Figure 8-6 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This could
be used for external oscillator designs.
FIGURE 8-6:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CXXX
CLKIN
74AS04
10k
10k
20 pF
Figure 8-7 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 8-7:
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
Cext values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 8-8 shows how the R/C combination is connected to the PIC16CXX. For Rext values
below 2.2 kΩ, the oscillator operation may become
unstable, or stop completely. For very high Rext values
(e.g. 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or package lead frame capacitance.
See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
XTAL
20 pF
8.2.4
See characterization data for desired device for variation of oscillator frequency due to VDD for given Rext/
Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-2 for
waveform).
FIGURE 8-8:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
RC OSCILLATOR MODE
V DD
Rext
330 kΩ
330 kΩ
74AS04
74AS04
0.1 µF
74AS04
Internal
clock
OSC1
To Other
Devices
PIC16CXXX
CLKIN
Cext
PIC16CXXX
VSS
Fosc/4
OSC2/CLKOUT
XTAL
1997 Microchip Technology Inc.
DS30272A-page 51
PIC16C71X
8.3
Reset
Applicable Devices
710 71 711 715
The PIC16CXX differentiates between various kinds of
reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (normal operation)
Brown-out Reset (BOR) (PIC16C710/711/715)
Parity Error Reset (PIC16C715)
A simplified block diagram of the on-chip reset circuit is
shown in Figure 8-9.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
FIGURE 8-9:
WDT Reset, on MCLR reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 87, Table 8-8 and Table 8-9. These bits are used in software to determine the nature of the reset. See Table 810 and Table 8-11 for a full description of reset states
of all registers.
The PIC16C710/711/715 have a MCLR noise filter in
the MCLR reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP Pin
MPEEN
Program
Memory
Parity(3)
WDT SLEEP
Module
WDT Time-out
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset(2)
S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 8-6 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: Brown-out Reset is implemented on the PIC16C710/711/715.
3: Parity Error Reset is implemented on the PIC16C715.
DS30272A-page 52
1997 Microchip Technology Inc.
PIC16C71X
8.4
8.4.1
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST), and Brown-out Reset
(BOR)
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
POWER-ON RESET (POR)
Applicable Devices
Applicable Devices
710 71 711 715
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met. Brown-out Reset may be used to meet the startup
conditions.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
8.4.2
POWER-UP TIMER (PWRT)
Applicable Devices
710 71 711 715
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
8.4.3
OSCILLATOR START-UP TIMER (OST)
710 71 711 715
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
8.4.4
BROWN-OUT RESET (BOR)
Applicable Devices
710 71 711 715
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for
greater than parameter #35, the brown-out situation will
reset the chip. A reset may not occur if VDD falls below
4.0V for less than parameter #35. The chip will remain
in Brown-out Reset until VDD rises above BVDD. The
Power-up Timer will now be invoked and will keep the
chip in RESET an additional 72 ms. If VDD drops below
BVDD while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up
Timer will be initialized. Once VDD rises above BVDD,
the Power-up Timer will execute a 72 ms time delay.
The Power-up Timer should always be enabled when
Brown-out Reset is enabled. Figure 8-10 shows typical
brown-out situations.
FIGURE 8-10: BROWN-OUT SITUATIONS
VDD
BVDD
Internal
Reset
72 ms
VDD
BVDD
Internal
Reset
VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA ........................................................................................................................200 mA
Maximum current sourced by PORTA ...................................................................................................................200 mA
Maximum current sunk by PORTB........................................................................................................................200 mA
Maximum current sourced by PORTB...................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 11-1:
OSC
RC
XT
HS
LP
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C710-04
PIC16C711-04
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq:4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at
5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ. at
32 kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
PIC16C710-10
PIC16C711-10
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 30 mA max. at
5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 10 MHz max.
PIC16C710-20
PIC16C711-20
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 30 mA max. at
5.5V
IPD: 1.5 µA typ. at 4.5V
Freq:20 MHz max.
Not recommended for
use in LP mode
Not recommended for
use in LP mode
1997 Microchip Technology Inc.
PIC16LC710-04
PIC16LC711-04
VDD: 2.5V to 6.0V
IDD: 3.8 mA typ. at 3.0V
IPD: 5.0 µA typ. at 3V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA typ. at 3.0V
IPD: 5.0 µA typ. at 3V
Freq: 4 MHz max.
PIC16C710/JW
PIC16C711/JW
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq:4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 30 mA max. at
Not recommended for
5.5V
use in HS mode
IPD: 1.5 µA typ. at 4.5V
Freq: 10 MHz max.
VDD: 2.5V to 6.0V
VDD: 2.5V to 6.0V
IDD: 48 µA max. at
IDD: 48 µA max. at
32 kHz, 3.0V
32 kHz, 3.0V
IPD: 5.0 µA max. at 3.0V IPD: 5.0 µA max. at
Freq: 200 kHz max.
3.0V
Freq: 200 kHz max.
DS30272A-page 89
PIC16C71X
Applicable Devices
11.1
710 71 711 715
DC Characteristics:
PIC16C710-04 (Commercial, Industrial, Extended)
PIC16C711-04 (Commercial, Industrial, Extended)
PIC16C710-10 (Commercial, Industrial, Extended)
PIC16C711-10 (Commercial, Industrial, Extended)
PIC16C710-20 (Commercial, Industrial, Extended)
PIC16C711-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
-40˚C ≤ TA ≤ +125˚C (extended)
DC CHARACTERISTICS
Param.
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
D001
D001A
Supply Voltage
VDD
4.0
4.5
-
6.0
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Poweron Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage
BVDD
3.7
4.0
4.3
3.7
4.0
4.4
V
D010
Supply Current (Note 2)
IDD
-
2.7
5
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
13.5
30
mA
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D013
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
V
BODEN configuration bit is enabled
Extended Range Only
D015
Brown-out Reset Current ∆IBOR
(Note 5)
-
300* 500
µA
BOR enabled VDD = 5.0V
D020
D021
D021A
D021B
Power-down Current
(Note 3)
-
10.5
1.5
1.5
1.5
42
21
24
30
µA
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +125°C
D023
Brown-out Reset Current ∆IBOR
(Note 5)
-
300* 500
µA
BOR enabled VDD = 5.0V
*
†
Note 1:
2:
3:
4:
5:
IPD
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30272A-page 90
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
11.2
DC Characteristics:
PIC16LC710-04 (Commercial, Industrial, Extended)
PIC16LC711-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
-40˚C ≤ TA ≤ +125˚C (extended)
DC CHARACTERISTICS
Param
No.
D001
710 71 711 715
Characteristic
Sym
Min
Typ† Max Units
Supply Voltage
Commercial/Industrial
Extended
VDD
VDD
2.5
3.0
-
6.0
6.0
V
V
Conditions
LP, XT, RC osc configuration (DC - 4 MHz)
LP, XT, RC osc configuration (DC - 4 MHz)
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Poweron Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on
Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset
Voltage
BVDD
3.7
4.0
4.3
V
BODEN configuration bit is enabled
D010
Supply Current
(Note 2)
IDD
-
2.0
3.8
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
48
µA
∆IBOR
-
300*
500
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
BOR enabled VDD = 5.0V
IPD
-
7.5
0.9
0.9
0.9
300*
30
5
5
10
500
µA
µA
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, -40°C to +125°C
BOR enabled VDD = 5.0V
D010A
D015
Brown-out Reset
Current (Note 5)
D020
D021
D021A
D021B
D023
Power-down Current
(Note 3)
*
†
Note 1:
2:
3:
4:
5:
Brown-out Reset
Current (Note 5)
∆IBOR
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1997 Microchip Technology Inc.
DS30272A-page 91
PIC16C71X
Applicable Devices
11.3
710 71 711 715
DC Characteristics:
PIC16C710-04 (Commercial, Industrial, Extended)
PIC16C711-04 (Commercial, Industrial, Extended)
PIC16C710-10 (Commercial, Industrial, Extended)
PIC16C711-10 (Commercial, Industrial, Extended)
PIC16C710-20 (Commercial, Industrial, Extended)
PIC16C711-20 (Commercial, Industrial, Extended)
PIC16LC710-04 (Commercial, Industrial, Extended)
PIC16LC711-04 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Param
No.
D030
D030A
D031
D032
D033
D040
D040A
D041
D042
D042A
D043
D070
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1
(in RC mode)
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
with TTL buffer
D060
with Schmitt Trigger buffer
MCLR, RB0/INT
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
D061
D063
MCLR, RA4/T0CKI
OSC1
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
-40˚C ≤ TA ≤ +125˚C (extended)
Operating voltage VDD range as described in DC spec Section 11.1 and
Section 11.2.
Sym
Min Typ Max Units
Conditions
†
VIL
VSS
VSS
VSS
VSS
- 0.15VDD
0.8V
- 0.2VDD
- 0.2VDD
V
V
V
V
For entire VDD range
4.5 ≤ VDD ≤ 5.5V
VSS
-
0.3VDD
V
Note1
VDD
VDD
V
V
4.5 ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
400
V For entire VDD range
V
V Note1
V
µA VDD = 5V, VPIN = VSS
VIH
2.0
0.25VDD + 0.8V
0.8VDD 0.8VDD 0.7VDD 0.9VDD IPURB
50
250
IIL
-
-
±1
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30272A-page 92
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
DC CHARACTERISTICS
Param
No.
Characteristic
Output Low Voltage
I/O ports
D080
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
-40˚C ≤ TA ≤ +125˚C (extended)
Operating voltage VDD range as described in DC spec Section 11.1 and
Section 11.2.
Sym
Min Typ Max Units
Conditions
†
VOL
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
VOH VDD - 0.7 -
-
V
VDD - 0.7 -
-
V
VDD - 0.7 -
-
V
VDD - 0.7 -
-
V
D080A
D083
OSC2/CLKOUT (RC osc config)
D083A
Output High Voltage
I/O ports (Note 3)
D090
D090A
D092
OSC2/CLKOUT (RC osc config)
D092A
D130*
D100
Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
OSC2 pin
710 71 711 715
VOD
-
-
14
V
COSC2
-
-
15
pF
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
All I/O pins and OSC2 (in RC mode) CIO
50
pF
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
*
†
1997 Microchip Technology Inc.
DS30272A-page 93
PIC16C71X
Applicable Devices
11.4
710 71 711 715
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
FIGURE 11-1: LOAD CONDITIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464Ω
CL = 50 pF
15 pF
DS30272A-page 94
for all pins except OSC2
for OSC2 output
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
11.5
710 71 711 715
Timing Diagrams and Specifications
FIGURE 11-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 11-2:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
10
MHz HS osc mode (-10)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
100
—
—
ns
HS osc mode (-10)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
100
—
250
ns
HS osc mode (-10)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
—
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1) 200
3
TosL, External Clock in (OSC1) High
50
—
—
ns
XT oscillator
TosH or Low Time
2.5
—
—
µs
LP oscillator
10
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise
—
—
25
ns
XT oscillator
TosF or Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected
(has no loading) for the PIC16C710/711.
1997 Microchip Technology Inc.
DS30272A-page 95
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 11-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 11-1 for load conditions.
TABLE 11-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
15
30
ns
Note 1
11*
TosH2ckH
OSC1↑ to CLKOUT↑
—
15
30
ns
Note 1
12*
TckR
CLKOUT rise time
—
5
15
ns
Note 1
13*
TckF
CLKOUT fall time
—
5
15
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
16*
TckH2ioI
17*
TosH2ioV
18*
TosH2ioI
19*
20*
21*
—
—
0.5TCY + 20
ns
Note 1
0.25TCY + 25
—
—
ns
Note 1
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
OSC1↑ (Q1 cycle) to
Port out valid
—
—
80 - 100
ns
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in hold time)
TBD
—
—
ns
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
ns
TioR
Port output rise time
PIC16C710/711
—
10
25
ns
PIC16LC710/711
—
—
60
ns
PIC16C710/711
—
10
25
ns
PIC16LC710/711
—
—
60
ns
TioF
Port output fall time
22††*
Tinp
INT pin high or low time
20
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
20
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30272A-page 96
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 11-1 for load conditions.
FIGURE 11-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 11-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Characteristic
30
TmcL
MCLR Pulse Width (low)
1
—
—
µs
VDD = 5V, -40˚C to +125˚C
31
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7*
18
33*
ms
VDD = 5V, -40˚C to +125˚C
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
Power up Timer Period
28*
72
132*
ms
VDD = 5V, -40˚C to +125˚C
—
—
1.1
µs
100
—
—
µs
32
Tost
33
Tpwrt
34
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
*
†
Min
Typ†
Max
Units
Conditions
3.8V ≤ VDD ≤ 4.2V
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1997 Microchip Technology Inc.
DS30272A-page 97
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 11-6: TIMER0 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
TMR0
Note: Refer to Figure 11-1 for load conditions.
TABLE 11-5:
TIMER0 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40
Tt0H
T0CKI High Pulse Width
41
Tt0L
T0CKI Low Pulse Width
Min
No Prescaler
With Prescaler
No Prescaler
With Prescaler
42
Tt0P
48
T0CKI Period
Tcke2tmrI Delay from external clock edge to timer increment
*
†
0.5TCY + 20*
Typ† Max Units Conditions
—
—
ns
10*
—
—
ns
0.5TCY + 20*
—
—
ns
10*
—
—
ns
Greater of:
20 ns or TCY + 40*
N
—
—
ns
2Tosc
—
7Tosc
—
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30272A-page 98
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
TABLE 11-6:
A/D CONVERTER CHARACTERISTICS:
PIC16C710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C710/711-10 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C710/711-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
Param Sym Characteristic
No.
A01
NR
A02
710 71 711 715
Resolution
EABS Absolute error
Min
Typ†
Max
Units
bit
Conditions
VREF = VDD, VSS ≤ AIN ≤ VREF
—
—
8-bits
—
—
VDD) .............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA ..........................................................................................................................80 mA
Maximum current sourced by PORTA .....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB...................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 15-1:
OSC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C71-04
PIC16C71-20
PIC16LC71-04
JW Devices
RC
VDD: 4.0V to 6.0V
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq:4 MHz max.
VDD: 4.5V to 5.5V
IDD: 1.8 mA typ. at 5.5V
IPD: 1.0 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 6.0V
IDD: 1.4 mA typ. at 3.0V
IPD: 0.6 µA typ. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq:4 MHz max.
XT
VDD: 4.0V to 6.0V
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 1.8 mA typ. at 5.5V
IPD: 1.0 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 6.0V
IDD: 1.4 mA typ. at 3.0V
IPD: 0.6 µA typ. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V
IDD: 30 mA max. at 5.5V
IPD: 1.0 µA typ. at 4.5V
IPD: 1.0 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 20 MHz max.
HS
LP
VDD: 4.0V to 6.0V
IDD: 15 µA typ. at 32 kHz,
4.0V
IPD: 0.6 µA typ. at 4.0V
Freq: 200 kHz max.
Not recommended for use
in LP mode
VDD: 4.5V to 5.5V
Not recommended for use in
HS mode
IDD: 30 mA max. at 5.5V
IPD: 1.0 µA typ. at 4.5V
Freq: 20 MHz max.
VDD: 3.0V to 6.0V
IDD: 32 µA max. at 32 kHz,
3.0V
IPD: 9 µA max. at 3.0V
Freq: 200 kHz max.
VDD: 3.0V to 6.0V
IDD: 32 µA max. at 32 kHz,
3.0V
IPD: 9 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
1997 Microchip Technology Inc.
DS30272A-page 135
PIC16C71X
Applicable Devices
15.1
710 71 711 715
DC Characteristics:
PIC16C71-04 (Commercial, Industrial)
PIC16C71-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Sym
Min
D001 Supply Voltage
D001A
VDD
4.0
4.5
-
6.0
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D010
Supply Current (Note 2)
IDD
-
1.8
3.3
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
13.5
30
mA
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
-
7
1.0
1.0
28
14
16
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
D013
D020 Power-down Current
D021 (Note 3)
D021A
*
†
Note 1:
2:
3:
4:
IPD
Typ† Max Units
Conditions
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
DS30272A-page 136
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
15.2
DC Characteristics:
PIC16LC71-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
OOperating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
710 71 711 715
Sym
Min
Typ† Max Units
Conditions
D001
Supply Voltage
VDD
3.0
-
6.0
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D010
Supply Current (Note 2)
IDD
-
1.4
2.5
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
15
32
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
-
5
0.6
0.6
20
9
12
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D010A
D020
D021
D021A
*
†
Note 1:
2:
3:
4:
Power-down Current
(Note 3)
IPD
XT, RC, and LP osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
1997 Microchip Technology Inc.
DS30272A-page 137
PIC16C71X
Applicable Devices
15.3
710 71 711 715
DC Characteristics:
PIC16C71-04 (Commercial, Industrial)
PIC16C71-20 (Commercial, Industrial)
PIC16LC71-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D030
D031
D032
D033
D040
D040A
D041
D042
D042A
D043
D070
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports (Note 4)
with TTL buffer
D060
with Schmitt Trigger buffer
MCLR, RB0/INT
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D083
OSC2/CLKOUT (RC osc config)
D090
Output High Voltage
I/O ports (Note 3)
D092
D130*
†
Note 1:
2:
3:
4:
Standard Operating Conditions (unless otherwise stated)
OOperating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
Operating voltage VDD range as described in DC spec Section 15.1
and Section 15.2.
Sym
Min Typ Max Units
Conditions
†
VIL
VSS
VSS
VSS
VSS
-
0.15V
0.8V
0.2VDD
0.3VDD
V
V
V
V
For entire VDD range
4.5 ≤ VDD ≤ 5.5V
Note1
VIH
2.0
VDD
0.25VDD VDD
+ 0.8V
VDD
0.85VDD 0.85VDD VDD
0.7VDD VDD
0.9VDD VDD
IPURB
50
250 †400
IIL
VOL
V
For entire VDD range
V
V Note1
V
µA VDD = 5V, VPIN = VSS
-
-
±1
-
-
±5
±5
-
-
0.6
V
-
-
0.6
V
-
V
VOH VDD - 0.7 -
4.5 ≤ VDD ≤ 5.5V
For entire VDD range
µA Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
IOL = 8.5mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6mA, VDD = 4.5V,
-40°C to +85°C
IOH = -3.0mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
VDD - 0.7 V IOH = -1.3mA, VDD = 4.5V,
-40°C to +85°C
Open-Drain High Voltage
VOD
14
V RA4 pin
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the
PIC16C71 be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as current sourced by the pin.
PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input
buffer.
DS30272A-page 138
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
DC CHARACTERISTICS
Param
No.
Characteristic
Capacitive Loading Specs on
Output Pins
OSC2 pin
D100
D101
†
Note 1:
2:
3:
4:
710 71 711 715
Standard Operating Conditions (unless otherwise stated)
OOperating temperature 0˚C
≤ TA ≤ +70˚C (commercial)
-40˚C ≤ TA ≤ +85˚C (industrial)
Operating voltage VDD range as described in DC spec Section 15.1
and Section 15.2.
Sym
Min Typ Max Units
Conditions
†
COSC2
15
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1.
All I/O pins and OSC2 (in RC mode) CIO
50
pF
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the
PIC16C71 be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as current sourced by the pin.
PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input
buffer.
1997 Microchip Technology Inc.
DS30272A-page 139
PIC16C71X
Applicable Devices
15.4
710 71 711 715
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
FIGURE 15-1: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
DS30272A-page 140
for all pins except OSC2/CLKOUT
for OSC2 output
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
15.5
710 71 711 715
Timing Diagrams and Specifications
FIGURE 15-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 15-2:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
1
—
4
MHz HS osc mode
1
—
20
MHz HS osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
1,000
ns
HS osc mode (-04)
50
—
1,000
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
1.0
TCY
DC
µs
TCY = 4/Fosc
2
TCY Instruction Cycle Time (Note 1)
3
TosL, External Clock in (OSC1) High or
50
—
—
ns
XT oscillator
TosH Low Time
2.5
—
—
µs
LP oscillator
10
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise or
25
—
—
ns
XT oscillator
TosF Fall Time
50
—
—
ns
LP oscillator
15
—
—
ns
HS oscillator
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected
(has no loading) for the PIC16C71.
1997 Microchip Technology Inc.
DS30272A-page 141
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 15-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
15
30
ns
Note 1
11*
TosH2ckH
OSC1↑ to CLKOUT↑
—
15
30
ns
Note 1
12*
TckR
CLKOUT rise time
—
5
15
ns
Note 1
13*
TckF
CLKOUT fall time
—
5
15
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
16*
TckH2ioI
17*
TosH2ioV
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
—
—
0.5TCY + 20
ns
Note 1
0.25TCY + 25
—
—
ns
Note 1
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
OSC1↑ (Q1 cycle) to
Port out valid
—
—
80 - 100
ns
PIC16C71
100
—
—
ns
PIC16LC71
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
PIC16C71
—
10
25
ns
PIC16LC71
—
—
60
ns
PIC16C71
—
10
25
ns
PIC16LC71
—
—
60
ns
21*
TioF
Port output fall time
22††*
Tinp
INT pin high or low time
20
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
20
—
—
ns
* These parameters are characterized but not tested.
†Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30272A-page 142
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
200
—
—
ns
VDD = 5V, -40˚C to +85˚C
7*
18
33*
ms
VDD = 5V, -40˚C to +85˚C
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
Power-up Timer Period
28*
72
132*
ms
VDD = 5V, -40˚C to +85˚C
I/O High Impedance from MCLR
Low
—
—
100
ns
30
TmcL
MCLR Pulse Width (low)
31
Twdt
Watchdog Timer Time-out Period
32
Tost
33
Tpwrt
34
TIOZ
Typ†
Max
Units
Conditions
(No Prescaler)
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1997 Microchip Technology Inc.
DS30272A-page 143
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 15-5: TIMER0 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
TMR0
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-5:
Param
No.
40*
TIMER0 EXTERNAL CLOCK REQUIREMENTS
Sym Characteristic
Tt0H T0CKI High Pulse Width
Min
No Prescaler
With Prescaler
41*
Tt0L T0CKI Low Pulse Width
No Prescaler
With Prescaler
42*
Tt0P T0CKI Period
No Prescaler
With Prescaler
*
†
Typ† Max Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
TCY + 40
—
—
ns
Greater of:
20 ns or TCY + 40
N
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30272A-page 144
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
TABLE 15-6:
Param
No.
A01
A02
A/D CONVERTER CHARACTERISTICS
Sym Characteristic
NR
Resolution
EABS Absolute error
PIC16C71
PIC16LC71
A03
EIL
Integral linearity error
A04
EDL
Differential linearity error
A05
EFS
Full scale error
A06
EOFF Offset error
PIC16C71
PIC16LC71
PIC16C71
PIC16LC71
PIC16C71
PIC16LC71
PIC16C71
PIC16LC71
A10
—
710 71 711 715
Monotonicity
Min
Typ†
Max
Units
Conditions
—
—
8 bits
bits
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
< ±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
< ±2
LSb
VREF = VDD = 3.0V (Note 3)
—
—
< ±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
< ±2
LSb
VREF = VDD = 3.0V (Note 3)
—
—
< ±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
< ±2
LSb
VREF = VDD = 3.0V (Note 3)
—
—
< ±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
< ±2
LSb
VREF = VDD = 3.0V (Note 3)
—
—
< ±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
< ±2
LSb
VREF = VDD = 3.0V (Note 3)
—
guaranteed
—
—
3.0V
—
VDD + 0.3
V
VSS - 0.3
—
VREF
V
VSS ≤ VAIN ≤ VREF
A20
VREF Reference voltage
A25
VAIN Analog input voltage
A30
ZAIN Recommended impedance of analog
voltage source
—
—
10.0
kΩ
A40
IAD
—
180
—
µA
Average current consumption when A/D is on. (Note 1)
A50
IREF VREF input current (Note 2)
10
—
1000
µA
—
—
40
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN.
To charge CHOLD see
Section 7.1.
During A/D Conversion cycle
—
—
1
mA
—
—
10
µA
A/D conversion current (VDD)
PIC16C71
PIC16LC71
During VAIN acquisition.
Based on differential of
VHOLD to VAIN.
To charge CHOLD see
Section 7.1.
During A/D Conversion cycle
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VAIN must be between VSS and VREF.
1997 Microchip Technology Inc.
DS30272A-page 145
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 15-6: A/D CONVERSION TIMING
BSF ADCON0, GO
1 Tcy
(TOSC/2) (1)
131
Q4
130
132
A/D CLK
7
A/D DATA
6
5
4
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 15-7:
A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
130
TAD
A/D clock period
Min
Typ†
Max
Units
PIC16C71
2.0
—
—
µs
TOSC based, VREF ≥ 3.0V
PIC16LC71
2.0
—
—
µs
TOSC based, VREF full range
PIC16C71
2.0
4.0
6.0
µs
A/D RC Mode
PIC16LC71
3.0
6.0
9.0
µs
A/D RC Mode
—
9.5
—
TAD
Note 2
20
—
µs
5*
—
—
µs
The minimum time is the amplifier settling time. This may be
used if the "new" input voltage
has not changed by more than
1 LSb (i.e., 19.5 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
—
Tosc/2§
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
1.5§
—
—
TAD
131
TCNV
Conversion time
(not including S/H time) (Note 1)
132
TACQ
Acquisition time
134
TGO
135
TSWC
Conditions
Q4 to A/D clock start
Switching from convert → sample time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§ These specifications ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for min conditions.
DS30272A-page 146
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
16.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES FOR PIC16C71
FIGURE 16-2: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
5.0
R = 4.7k
The graphs and tables provided in this section are for
design guidance and are not tested or guaranteed. In
some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and
devices are guaranteed to operate properly only
within the specified range.
The data presented in this section is a statistical summary of data collected on units
from different lots over a period of time and
matrix samples. 'Typical' represents the
mean of the distribution while 'max' or 'min'
represents (mean + 3σ) and (mean - 3σ)
respectively where σ is standard deviation.
4.5
4.0
3.5
3.0
R = 10k
2.5
Fosc (MHz)
Note:
2.0
1.5
Cext = 20 pF, T = 25°C
FIGURE 16-1: TYPICAL RC OSCILLATOR
FREQUENCY VS.
TEMPERATURE
1.0
R = 100k
0.5
Fosc
Fosc (25°C)
Frequency Normalized to 25°C
0.0
3.0
1.050
1.025
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
Rext = 10k
Cext = 100 pF
FIGURE 16-3: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
1.000
VDD = 5.5V
0.975
710 71 711 715
2.0
0.950
R = 3.3k
1.8
VDD = 3.5V
0.925
0.900
1.6
0.875
1.4
R = 4.7k
0.850
0
10
20
30
40
50
60
70
1.2
T(°C)
Fosc (MHz)
1.0
0.8
R = 10k
0.6
Cext = 100 pF, T = 25°C
0.4
0.2
0.0
3.0
R = 100k
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1997 Microchip Technology Inc.
DS30272A-page 147
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 16-4: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
TABLE 16-1:
RC OSCILLATOR
FREQUENCIES
.8
Average
R = 3.3k
Cext
Rext
FOSC @ 5V, 25°C
.7
20 pF
4.7k
10k
100k
3.3k
4.7k
10k
100k
3.3k
4.7k
10k
100k
R = 4.7k
.6
Fosc (MHz)
100 pF
.5
300 pF
.4
R = 10k
.3
Cext = 300 pF, T = 25°C
R = 100k
0
3.0
3.5
4.0
±17.35%
±10.10%
±11.90%
±9.43%
±9.83%
±10.92%
±16.03%
±10.97%
±10.14%
±10.43%
±11.24%
The percentage variation indicated here is part to part
variation due to normal process distribution. The variation indicated is ±3 standard deviation from average
value for VDD = 5V.
.1
4.5
5.0
5.5
6.0
FIGURE 16-6: TYPICAL IPD VS. VDD
WATCHDOG TIMER ENABLED
25°C
VDD (Volts)
14
FIGURE 16-5: TYPICAL IPD VS. VDD
WATCHDOG TIMER
DISABLED 25°C
12
0.6
10
IPD (µA)
0.5
0.4
8
6
IPD (µA)
Data based on matrix samples. See first page of this section for details.
.2
4.52 MHz
2.47 MHz
290.86 kHz
1.92 MHz
1.49 MHz
788.77 kHz
88.11 kHz
726.89 kHz
573.95 kHz
307.31 kHz
33.82 kHz
0.3
4
0.2
2
0
0.1
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
0.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30272A-page 148
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
FIGURE 16-7: MAXIMUM IPD VS. VDD
WATCHDOG DISABLED
710 71 711 715
FIGURE 16-8: MAXIMUM IPD VS. VDD
WATCHDOG ENABLED
45
25
-55°C
-40°C
40
125°C
35
20
30
125°C
25
20
0°C
70°C
85°C
15
10
85°C
70°C
10
5
5
0
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
5.5
0°C
-40°C
-55°C
6.0
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
IPD, with Watchdog Timer enabled, has two components:
The leakage current which increases with higher temperature and the operating current of the Watchdog Timer logic
which increases with lower temperature. At -40°C, the latter
dominates explaining the apparently anomalous behavior.
FIGURE 16-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD
2.00
1.80
Max (-40˚C to 85˚C)
VTH (Volts)
1.60
25˚C, TYP
1.40
1.20
Min (-40˚C to 85˚C)
1.00
0.80
0.60
2.5
1997 Microchip Technology Inc.
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
DS30272A-page 149
Data based on matrix samples. See first page of this section for details.
IPD (µA)
IPD (µA)
15
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 16-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD
4.50
VIH, Max (-40°C to 85°C)
VIH, Typ (25°C)
4.00
VIH, Min (-40°C to 85°C)
VIH, VIL (Volts)
3.50
3.00
2.50
2.00
1.50
VIL, Max (-40°C to 85°C)
1.00
VIL, Typ (25°C)
VIL, Min (-40°C to 85°C)
0.50
0.00
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Note: These input pins have a Schmitt Trigger input buffer.
FIGURE 16-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
VS. VDD
Min (-40°C to 85°C)
3.60
3.40
TYP (25°C)
Max (-40°C to 85°C)
3.20
3.00
2.80
2.60
VTH (Volts)
Data based on matrix samples. See first page of this section for details.
VDD (Volts)
Min (-40°C to 85°C)
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS30272A-page 150
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 16-12: TYPICAL IDD VS. FREQ (EXT CLOCK, 25°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
100
10
1
10,000
100,000
1,000,000
100,000,000
10,000,000
Frequency (Hz)
FIGURE 16-13: MAXIMUM, IDD VS. FREQ (EXT CLOCK, -40° TO +85°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
IDD (µA)
1,000
100
10
10,000
100,000
1,000,000
10,000,000
100,000,000
Frequency (Hz)
1997 Microchip Technology Inc.
DS30272A-page 151
Data based on matrix samples. See first page of this section for details.
IDD (µA)
1,000
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 16-14: MAXIMUM IDD VS. FREQ WITH A/D OFF (EXT CLOCK, -55° TO +125°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
IDD (µA)
1,000
10
10,000
100,000
1,000,000
100,000,000
10,000,000
Frequency (Hz)
FIGURE 16-15: WDT TIMER TIME-OUT
PERIOD VS. VDD
FIGURE 16-16: TRANSCONDUCTANCE (gm)
OF HS OSCILLATOR VS. VDD
9000
50
8000
45
7000
40
Max, -40°C
35
gm (µA/V)
6000
WDT Period (ms)
Data based on matrix samples. See first page of this section for details.
100
Max, 85°C
Max, 70°C
30
25
5000
4000
Typ, 25°C
3000
20
Min, 85°C
2000
Typ, 25°C
Min, 0°C
1000
15
0
10
2
Min, -40°C
3
4
5
6
7
VDD (Volts)
5
2
3
4
5
6
7
VDD (Volts)
DS30272A-page 152
1997 Microchip Technology Inc.
PIC16C71X
Applicable Devices
FIGURE 16-17: TRANSCONDUCTANCE (gm)
OF LP OSCILLATOR VS. VDD
710 71 711 715
FIGURE 16-19: IOH VS. VOH, VDD = 3V
0
225
200
-5
Max, -40°C
Min, 85°C
175
-10
Typ, 25°C
IOH (mA)
gm (µA/V)
150
125
100
Min, 85°C
Typ, 25°C
-15
Max, -40°C
50
-20
25
0
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 16-18: TRANSCONDUCTANCE (gm)
OF XT OSCILLATOR VS. VDD
-25
0.0
0.5
1.0
1.5
2.0
VOH (Volts)
2.5
3.0
FIGURE 16-20: IOH VS. VOH, VDD = 5V
0
2500
-5
Max, -40°C
-10
2000
IOH (mA)
-15
gm (µA/V)
Typ, 25°C
1500
-20
Min @ 85°C
-25
Typ @ 25°C
-30
1000
-35
-40
Max @ -40°C
Min, 85°C
500
-45
-50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
2
3
4
5
VDD (Volts)
1997 Microchip Technology Inc.
6
7
VOH (Volts)
DS30272A-page 153
Data based on matrix samples. See first page of this section for details.
75
PIC16C71X
Applicable Devices
710 71 711 715
FIGURE 16-22: IOL VS. VOL, VDD = 5V
FIGURE 16-21: IOL VS. VOL, VDD = 3V
35
90
Max @ -40°C
30
80
Max @ -40°C
70
25
60
Typ @ 25°C
Typ @ 25°C
15
Min @ +85°C
IOL (mA)
IOL (mA)
20
50
Min @ +85°C
40
30
10
20
Data based on matrix samples. See first page of this section for details.
5
10
0
0.0
0.5
1.0
1.5
VOL (Volts)
2.0
2.5
3.0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL (Volts)
DS30272A-page 154
1997 Microchip Technology Inc.
PIC16C71X
17.0
PACKAGING INFORMATION
17.1
18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW)
N
α
C
E1 E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A3 A
e1
B
A2
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
10°
0°
10°
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
—
0.381
3.810
3.810
0.355
1.270
0.203
22.352
20.320
7.620
5.588
2.540
7.366
7.620
3.175
18
0.508
0.381
5.080
1.7780
4.699
4.445
0.585
1.651
0.381
23.622
20.320
8.382
7.874
2.540
8.128
10.160
3.810
18
1.397
1.270
—
0.015
0.150
0.150
0.014
0.050
0.008
0.880
0.800
0.300
0.220
0.100
0.290
0.300
0.125
18
0.020
0.015
0.200
0.070
0.185
0.175
0.023
0.065
0.015
0.930
0.800
0.330
0.310
0.100
0.320
0.400
0.150
18
0.055
0.050
1997 Microchip Technology Inc.
Typical
Typical
Reference
Reference
Typical
Notes
Typical
Typical
Reference
Reference
Typical
DS30272A-page 155
PIC16C71X
17.2
18-Lead Plastic Dual In-line (300 mil) (P)
N
α
C
E1 E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A2 A
e1
B
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
–
0.381
3.048
0.355
1.524
0.203
22.479
20.320
7.620
6.096
2.489
7.620
7.874
3.048
18
0.889
0.127
DS30272A-page 156
Inches
Notes
Min
Max
10°
0°
10°
4.064
–
3.810
0.559
1.524
0.381
23.495
20.320
8.255
7.112
2.591
7.620
9.906
3.556
18
–
–
–
0.015
0.120
0.014
0.060
0.008
0.885
0.800
0.300
0.240
0.098
0.300
0.310
0.120
18
0.035
0.005
0.160
–
0.150
0.022
0.060
0.015
0.925
0.800
0.325
0.280
0.102
0.300
0.390
0.140
18
–
–
Reference
Typical
Reference
Typical
Reference
Notes
Reference
Typical
Reference
Typical
Reference
1997 Microchip Technology Inc.
PIC16C71X
17.3
18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)(SO)
e
B
h x 45°
N
Index
Area
E
H
α
C
Chamfer
h x 45°
L
1
2
3
D
Seating
Plane
Base
Plane
CP
A1
A
Package Group: Plastic SOIC (SO)
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
8°
0°
8°
A
A1
B
C
D
E
e
H
h
L
N
CP
2.362
0.101
0.355
0.241
11.353
7.416
1.270
10.007
0.381
0.406
18
–
2.642
0.300
0.483
0.318
11.735
7.595
1.270
10.643
0.762
1.143
18
0.102
0.093
0.004
0.014
0.009
0.447
0.292
0.050
0.394
0.015
0.016
18
–
0.104
0.012
0.019
0.013
0.462
0.299
0.050
0.419
0.030
0.045
18
0.004
1997 Microchip Technology Inc.
Reference
Notes
Reference
DS30272A-page 157
PIC16C71X
17.4
20-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS)
N
Index
area
E
H
α
C
L
1 2 3
B
e
A
Base plane
CP
Seating plane
D
A1
Package Group: Plastic SSOP
Millimeters
Symbol
Min
Max
α
0°
A
A1
B
C
D
E
e
H
L
N
CP
1.730
0.050
0.250
0.130
7.070
5.200
0.650
7.650
0.550
20
-
Inches
Notes
Min
Max
8°
0°
8°
1.990
0.210
0.380
0.220
7.330
5.380
0.650
7.900
0.950
20
0.102
0.068
0.002
0.010
0.005
0.278
0.205
0.026
0.301
0.022
20
-
0.078
0.008
0.015
0.009
0.289
0.212
0.026
0.311
0.037
20
0.004
Reference
Notes
Reference
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per
side. D1 and E1 dimensions including mold mismatch.
2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m
(0.003”)max.
3: This outline conforms to JEDEC MS-026.
DS30272A-page 158
1997 Microchip Technology Inc.
PIC16C71X
17.5
Package Marking Information
18-Lead PDIP
Example
MMMMMMMMMMMMM
XXXXXXXXXXXXXXXX
AABBCDE
18-Lead SOIC
PIC16C711-04/P
9452CBA
Example
MMMMMMMMMM
XXXXXXXXXXXX
XXXXXXXXXXXX
AABBCDE
PIC16C715
-20/50
9447CBA
18-Lead CERDIP Windowed
Example
MMMMMM
XXXXXXXX
AABBCDE
20-Lead SSOP
Example
XXXXXXXX
XXXXXXXX
PIC16C710
20I/SS025
AABBCAE
Legend:
9517SBP
MM...M
XX...X
AA
BB
C
D1
E
Note:
PIC16C71
/JW
945/CBT
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
1997 Microchip Technology Inc.
DS30272A-page 159
PIC16C71X
NOTES:
DS30272A-page 160
1997 Microchip Technology Inc.
PIC16C71X
APPENDIX A:
APPENDIX B: COMPATIBILITY
The following are the list of modifications over the
PIC16C5X microcontroller family:
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (1K now as opposed to 512 before) and
register file (68 bytes now versus 32 bytes
before).
A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
Data memory paging is redefined slightly.
STATUS register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compatibility with PIC16C5X.
OPTION and TRIS registers are made addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
Reset vector is changed to 0000h.
Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Registers are reset differently.
Wake up from SLEEP through interrupt is
added.
Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt on
change feature.
T0CKI pin is also a port pin (RA4) now.
FSR is made a full eight bit register.
“In-circuit serial programming” is made possible.
The user can program PIC16CXX devices using
only five pins: VDD, VSS, MCLR/VPP, RB6 (clock)
and RB7 (data in/out).
PCON status register is added with a Power-on
Reset status bit (POR).
Code protection scheme is enhanced such that
portions of the program memory can be protected, while the remainder is unprotected.
Brown-out protection circuitry has been added.
Controlled by configuration word bit BODEN.
Brown-out reset ensures the device is placed in
a reset condition if VDD dips below a fixed setpoint.
1997 Microchip Technology Inc.
2.
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to 0000h.
DS30272A-page 161
PIC16C71X
APPENDIX C: WHAT’S NEW
APPENDIX D: WHAT’S CHANGED
1.
1.
Consolidated all pin compatible 18-pin A/D
based devices into one data sheet.
2.
3.
DS30272A-page 162
Minor changes, spelling and grammatical
changes.
Low voltage operation on the PIC16LC710/711/
715 has been reduced from 3.0V to 2.5V.
Part numbers of the PIC16C70 and PIC16C71A
have changed to PIC16C710 and PIC16C711,
respectively.
1997 Microchip Technology Inc.
PIC16C71X
INDEX
A
A/D
Accuracy/Error ........................................................... 44
ADIF bit ...................................................................... 39
Analog Input Model Block Diagram ............................ 40
Analog-to-Digital Converter ........................................ 37
Configuring Analog Port Pins ..................................... 41
Configuring the Interrupt ............................................ 39
Configuring the Module .............................................. 39
Connection Considerations ........................................ 44
Conversion Clock ....................................................... 41
Conversion Time ........................................................ 43
Conversions ............................................................... 42
Converter Characteristics .......................... 99, 122, 145
Delays ........................................................................ 40
Effects of a Reset ....................................................... 44
Equations ................................................................... 40
Faster Conversion - Lower Resolution Trade-off ....... 43
Flowchart of A/D Operation ........................................ 45
GO/DONE bit ............................................................. 39
Internal Sampling Switch (Rss) Impedence ............... 40
Minimum Charging Time ............................................ 40
Operation During Sleep ............................................. 44
Sampling Requirements ............................................. 40
Source Impedence ..................................................... 40
Time Delays ............................................................... 40
Transfer Function ....................................................... 45
Absolute Maximum Ratings ............................... 89, 111, 135
AC Characteristics
PIC16C710 .............................................................. 101
PIC16C711 .............................................................. 101
PIC16C715 .............................................................. 125
ADCON0 Register .............................................................. 37
ADCON1 ............................................................................ 37
ADCON1 Register ........................................................ 14, 37
ADCS0 bit .......................................................................... 37
ADCS1 bit .......................................................................... 37
ADIE bit ........................................................................ 19, 20
ADIF bit ........................................................................ 21, 37
ADON bit ............................................................................ 37
ADRES Register .................................................... 15, 37, 39
ALU ...................................................................................... 7
Application Notes
AN546 ........................................................................ 37
AN552 ........................................................................ 27
AN556 ........................................................................ 23
AN607, Power-up Trouble Shooting .......................... 53
Architecture
Harvard ........................................................................ 7
Overview ...................................................................... 7
von Neumann ............................................................... 7
Assembler
MPASM Assembler .................................................... 86
B
Block Diagrams
Analog Input Model .................................................... 40
On-Chip Reset Circuit ................................................ 52
PIC16C71X .................................................................. 8
RA3/RA0 Port Pins .................................................... 25
RA4/T0CKI Pin ........................................................... 25
RB3:RB0 Port Pins .................................................... 27
RB7:RB4 Pins ............................................................ 28
1997 Microchip Technology Inc.
RB7:RB4 Port Pins .....................................................28
Timer0 ........................................................................31
Timer0/WDT Prescaler ...............................................34
Watchdog Timer .........................................................65
BODEN bit ..........................................................................48
BOR bit ........................................................................ 22, 54
Brown-out Reset (BOR) ......................................................53
C
C bit ....................................................................................17
C16C71 ..............................................................................47
Carry bit ................................................................................7
CHS0 bit .............................................................................37
CHS1 bit .............................................................................37
Clocking Scheme ................................................................10
Code Examples
Call of a Subroutine in Page 1 from Page 0 ...............24
Changing Prescaler (Timer0 to WDT) ........................35
Changing Prescaler (WDT to Timer0) ........................35
Doing an A/D Conversion ...........................................42
I/O Programming ........................................................30
Indirect Addressing .....................................................24
Initializing PORTA ......................................................25
Initializing PORTB ......................................................27
Saving STATUS and W Registers in RAM .................64
Code Protection ........................................................... 47, 67
Computed GOTO ...............................................................23
Configuration Bits ...............................................................47
CP0 bit ......................................................................... 47, 48
CP1 bit ................................................................................48
D
DC bit ..................................................................................17
DC Characteristics ........................................................... 147
PIC16C71 ................................................................ 136
PIC16C710 ........................................................ 90, 101
PIC16C711 ........................................................ 90, 101
PIC16C715 ...................................................... 113, 125
Development Support .................................................... 3, 85
Development Tools .............................................................85
Diagrams - See Block Diagrams
Digit Carry bit ........................................................................7
Direct Addressing ...............................................................24
E
Electrical Characteristics
PIC16C71 ................................................................ 135
PIC16C710 .................................................................89
PIC16C711 .................................................................89
PIC16C715 .............................................................. 111
External Brown-out Protection Circuit .................................60
External Power-on Reset Circuit ........................................60
F
Family of Devices
PIC16C71X ...................................................................4
FOSC0 bit .................................................................... 47, 48
FOSC1 bit .................................................................... 47, 48
FSR Register ......................................................... 15, 16, 24
Fuzzy Logic Dev. System (fuzzyTECH-MP) .....................87
G
General Description ..............................................................3
GIE bit .......................................................................... 19, 61
GO/DONE bit ......................................................................37
DS30390D-page 163
PIC16C71X
I
I/O Ports
PORTA ....................................................................... 25
PORTB ....................................................................... 27
Section ....................................................................... 25
I/O Programming Considerations ....................................... 30
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 85
In-Circuit Serial Programming ...................................... 47, 67
INDF Register ........................................................ 14, 16, 24
Indirect Addressing ............................................................ 24
Instruction Cycle ................................................................. 10
Instruction Flow/Pipelining ................................................. 10
Instruction Format .............................................................. 69
Instruction Set
ADDLW ...................................................................... 71
ADDWF ...................................................................... 71
ANDLW ...................................................................... 71
ANDWF ...................................................................... 71
BCF ............................................................................ 72
BSF ............................................................................ 72
BTFSC ....................................................................... 72
BTFSS ....................................................................... 73
CALL .......................................................................... 73
CLRF .......................................................................... 74
CLRW ........................................................................ 74
CLRWDT .................................................................... 74
COMF ........................................................................ 75
DECF ......................................................................... 75
DECFSZ ..................................................................... 75
GOTO ........................................................................ 76
INCF ........................................................................... 76
INCFSZ ...................................................................... 77
IORLW ....................................................................... 77
IORWF ....................................................................... 78
MOVF ......................................................................... 78
MOVLW ..................................................................... 78
MOVWF ..................................................................... 78
NOP ........................................................................... 79
OPTION ..................................................................... 79
RETFIE ...................................................................... 79
RETLW ...................................................................... 80
RETURN .................................................................... 80
RLF ............................................................................ 81
RRF ............................................................................ 81
SLEEP ....................................................................... 82
SUBLW ...................................................................... 82
SUBWF ...................................................................... 83
SWAPF ...................................................................... 83
TRIS ........................................................................... 83
XORLW ...................................................................... 84
XORWF ...................................................................... 84
Section ....................................................................... 69
Summary Table .......................................................... 70
INT Interrupt ....................................................................... 63
INTCON Register ............................................................... 19
INTE bit .............................................................................. 19
INTEDG bit ................................................................... 18, 63
Internal Sampling Switch (Rss) Impedence ....................... 40
Interrupts ............................................................................ 47
A/D ............................................................................. 61
External ...................................................................... 61
PORTB Change ......................................................... 61
PortB Change ............................................................ 63
RB7:RB4 Port Change ............................................... 27
Section ....................................................................... 61
TMR0 ......................................................................... 63
DS30390D-page 164
TMR0 Overflow .......................................................... 61
INTF bit .............................................................................. 19
IRP bit ................................................................................ 17
K
KeeLoq Evaluation and Programming Tools ................... 87
L
Loading of PC .................................................................... 23
LP ...................................................................................... 54
M
MCLR ........................................................................... 52, 56
Memory
Data Memory ............................................................. 12
Program Memory ....................................................... 11
Register File Maps
PIC16C71 .......................................................... 12
PIC16C710 ........................................................ 12
PIC16C711 ........................................................ 13
PIC16C715 ........................................................ 13
MP-DriveWay - Application Code Generator .................. 87
MPEEN bit ................................................................... 22, 48
MPLAB C ........................................................................ 87
MPLAB Integrated Development Environment
Software ............................................................................. 86
O
OPCODE ........................................................................... 69
OPTION Register ............................................................... 18
Orthogonal ........................................................................... 7
OSC selection .................................................................... 47
Oscillator
HS ........................................................................ 49, 54
LP ........................................................................ 49, 54
RC ............................................................................. 49
XT ........................................................................ 49, 54
Oscillator Configurations .................................................... 49
Oscillator Start-up Timer (OST) ......................................... 53
P
Packaging
18-Lead CERDIP w/Window ................................... 155
18-Lead PDIP .......................................................... 156
18-Lead SOIC .......................................................... 157
20-Lead SSOP ........................................................ 158
Paging, Program Memory .................................................. 23
PCL Register ................................................... 14, 15, 16, 23
PCLATH ....................................................................... 57, 58
PCLATH Register ............................................ 14, 15, 16, 23
PCON Register ............................................................ 22, 54
PD bit ..................................................................... 17, 52, 55
PER bit ............................................................................... 22
PIC16C71 ........................................................................ 147
AC Characteristics ................................................... 147
PICDEM-1 Low-Cost PIC16/17 Demo Board .................... 86
PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 86
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............... 86
PICMASTER In-Circuit Emulator ..................................... 85
PICSTART Plus Entry Level Development System ......... 85
PIE1 Register ..................................................................... 20
Pin Functions
MCLR/VPP ................................................................... 9
OSC1/CLKIN ............................................................... 9
OSC2/CLKOUT ........................................................... 9
RA0/AN0 ...................................................................... 9
RA1/AN1 ...................................................................... 9
1997 Microchip Technology Inc.
PIC16C71X
RA2/AN2 ...................................................................... 9
RA3/AN3/VREF ............................................................. 9
RA4/T0CKI ................................................................... 9
RB0/INT ....................................................................... 9
RB1 .............................................................................. 9
RB2 .............................................................................. 9
RB3 .............................................................................. 9
RB4 .............................................................................. 9
RB5 .............................................................................. 9
RB6 .............................................................................. 9
RB7 .............................................................................. 9
VDD .............................................................................. 9
VSS ............................................................................... 9
Pinout Descriptions
PIC16C71 .................................................................... 9
PIC16C710 .................................................................. 9
PIC16C711 .................................................................. 9
PIC16C715 .................................................................. 9
PIR1 Register ..................................................................... 21
POP ................................................................................... 23
POR ............................................................................. 53, 54
Oscillator Start-up Timer (OST) ........................... 47, 53
Power Control Register (PCON) ................................ 54
Power-on Reset (POR) ............................ 47, 53, 57, 58
Power-up Timer (PWRT) ..................................... 47, 53
Time-out Sequence .................................................... 54
Time-out Sequence on Power-up .............................. 59
TO ........................................................................ 52, 55
POR bit ........................................................................ 22, 54
Port RB Interrupt ................................................................ 63
PORTA ......................................................................... 57, 58
PORTA Register .................................................... 14, 15, 25
PORTB ......................................................................... 57, 58
PORTB Register .................................................... 14, 15, 27
Power-down Mode (SLEEP) .............................................. 66
Prescaler, Switching Between Timer0 and WDT ............... 35
PRO MATE II Universal Programmer .............................. 85
Program Branches ............................................................... 7
Program Memory
Paging ........................................................................ 23
Program Memory Maps
PIC16C71 .................................................................. 11
PIC16C710 ................................................................ 11
PIC16C711 ................................................................ 11
PIC16C715 ................................................................ 11
Program Verification .......................................................... 67
PS0 bit ............................................................................... 18
PS1 bit ............................................................................... 18
PS2 bit ............................................................................... 18
PSA bit ............................................................................... 18
PUSH ................................................................................. 23
PWRT
Power-up Timer (PWRT) ........................................... 53
PWRTE bit ................................................................... 47, 48
R
RBIE bit .............................................................................. 19
RBIF bit .................................................................. 19, 27, 63
RBPU bit ............................................................................ 18
RC ...................................................................................... 54
RC Oscillator ................................................................ 51, 54
Read-Modify-Write ............................................................. 30
Register File ....................................................................... 12
Registers
Maps
PIC16C71 .......................................................... 12
PIC16C710 ........................................................ 12
1997 Microchip Technology Inc.
PIC16C711 .........................................................13
PIC16C715 .........................................................13
Reset Conditions ........................................................56
Summary ............................................................. 14–??
Reset ........................................................................... 47, 52
Reset Conditions for Special Registers ..............................56
RP0 bit ......................................................................... 12, 17
RP1 bit ................................................................................17
S
SEEVAL Evaluation and Programming System ...............87
Services
One-Time-Programmable (OTP) Devices ....................5
Quick-Turnaround-Production (QTP) Devices ..............5
Serialized Quick-Turnaround Production (SQTP)
Devices .........................................................................5
SLEEP ......................................................................... 47, 52
Software Simulator (MPLAB SIM) ...................................87
Special Features of the CPU ..............................................47
Special Function Registers
PIC16C71 ...................................................................14
PIC16C710 .................................................................14
PIC16C711 .................................................................14
Special Function Registers, Section ...................................14
Stack ...................................................................................23
Overflows ....................................................................23
Underflow ...................................................................23
STATUS Register ...............................................................17
T
T0CS bit ..............................................................................18
T0IE bit ...............................................................................19
T0IF bit ...............................................................................19
TAD .....................................................................................41
Timer0
RTCC ................................................................... 57, 58
Timers
Timer0
Block Diagram ....................................................31
External Clock ....................................................33
External Clock Timing ........................................33
Increment Delay .................................................33
Interrupt ..............................................................31
Interrupt Timing ..................................................32
Prescaler ............................................................34
Prescaler Block Diagram ....................................34
Section ...............................................................31
Switching Prescaler Assignment ........................35
Synchronization ..................................................33
T0CKI .................................................................33
T0IF ....................................................................63
Timing .................................................................31
TMR0 Interrupt ...................................................63
Timing Diagrams
A/D Conversion ....................................... 100, 124, 146
Brown-out Reset .................................................. 53, 97
CLKOUT and I/O ....................................... 96, 119, 142
External Clock Timing ................................ 95, 118, 141
Power-up Timer ................................................. 97, 143
Reset ................................................................. 97, 143
Start-up Timer .................................................... 97, 143
Time-out Sequence ....................................................59
Timer0 ................................................. 31, 98, 121, 144
Timer0 Interrupt Timing ..............................................32
Timer0 with External Clock .........................................33
Wake-up from SLEEP through Interrupt .....................67
Watchdog Timer ................................................ 97, 143
DS30390D-page 165
PIC16C71X
TO bit ................................................................................. 17
TOSE bit ............................................................................. 18
TRISA Register ...................................................... 14, 16, 25
TRISB Register ...................................................... 14, 16, 27
Two’s Complement .............................................................. 7
LIST OF EXAMPLES
U
Example 4-2:
Example 5-1:
Example 5-2:
Example 5-3:
Upward Compatibility ........................................................... 3
UV Erasable Devices ........................................................... 5
W
W Register
ALU .............................................................................. 7
Wake-up from SLEEP ........................................................ 66
Watchdog Timer (WDT) ................................... 47, 52, 56, 65
WDT ................................................................................... 56
Block Diagram ............................................................ 65
Programming Considerations .................................... 65
Timeout ................................................................ 57, 58
WDT Period ........................................................................ 65
WDTE bit ...................................................................... 47, 48
Z
Z bit .................................................................................... 17
Zero bit ................................................................................. 7
Example 3-1:
Example 4-1:
Example 6-1:
Example 6-2:
Equation 7-1:
Example 7-1:
Example 7-2:
Example 7-3:
Example 8-1:
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
Figure 4-10:
Figure 4-11:
Figure 4-12:
Figure 4-13:
Figure 4-14:
Figure 4-15:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 6-1:
Figure 6-2:
Figure 6-3:
Figure 6-4:
Figure 6-5:
Figure 6-6:
Figure 7-1:
Figure 7-2:
DS30390D-page 166
Instruction Pipeline Flow ........................... 10
Call of a Subroutine in Page 1 from
Page 0 ...................................................... 24
Indirect Addressing ................................... 24
Initializing PORTA..................................... 25
Initializing PORTB..................................... 27
Read-Modify-Write Instructions
on an I/O Port ........................................... 30
Changing Prescaler (Timer0→WDT) ........ 35
Changing Prescaler (WDT→Timer0) ........ 35
A/D Minimum Charging Time.................... 40
Calculating the Minimum Required
Aquisition Time ......................................... 40
A/D Conversion......................................... 42
4-bit vs. 8-bit Conversion Times ............... 43
Saving STATUS and W Registers
in RAM ...................................................... 64
PIC16C71X Block Diagram ........................ 8
Clock/Instruction Cycle ............................. 10
PIC16C710 Program Memory Map
and Stack .................................................. 11
PIC16C71/711 Program Memory Map
and Stack .................................................. 11
PIC16C715 Program Memory Map
and Stack .................................................. 11
PIC16C710/71 Register File Map ............. 12
PIC16C711 Register File Map .................. 13
PIC16C715 Register File Map .................. 13
Status Register (Address 03h, 83h).......... 17
OPTION Register (Address 81h, 181h) .... 18
INTCON Register (Address 0Bh, 8Bh) ..... 19
PIE1 Register (Address 8Ch) ................... 20
PIR1 Register (Address 0Ch) ................... 21
PCON Register (Address 8Eh),
PIC16C710/711 ........................................ 22
PCON Register (Address 8Eh),
PIC16C715 ............................................... 22
Loading of PC In Different Situations........ 23
Direct/Indirect Addressing......................... 24
Block Diagram of RA3:RA0 Pins .............. 25
Block Diagram of RA4/T0CKI Pin ............. 25
Block Diagram of RB3:RB0 Pins .............. 27
Block Diagram of RB7:RB4 Pins
(PIC16C71) ............................................... 28
Block Diagram of RB7:RB4 Pins
(PIC16C710/711/715) ............................... 28
Successive I/O Operation ......................... 30
Timer0 Block Diagram .............................. 31
Timer0 Timing: Internal Clock/
No Prescale .............................................. 31
Timer0 Timing: Internal Clock/
Prescale 1:2 .............................................. 32
Timer0 Interrupt Timing ............................ 32
Timer0 Timing with External Clock ........... 33
Block Diagram of the Timer0/
WDT Prescaler ......................................... 34
ADCON0 Register (Address 08h),
PIC16C710/71/711 ................................... 37
ADCON0 Register (Address 1Fh),
PIC16C715 ............................................... 38
1997 Microchip Technology Inc.
PIC16C71X
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Figure 8-1:
Figure 8-2:
Figure 8-3:
Figure 8-4:
Figure 8-5:
Figure 8-6:
Figure 8-7:
Figure 8-8:
Figure 8-9:
Figure 8-10:
Figure 8-11:
Figure 8-12:
Figure 8-13:
Figure 8-14:
Figure 8-15:
Figure 8-16:
Figure 8-17:
Figure 8-18:
Figure 8-19:
Figure 8-20:
Figure 8-21:
Figure 8-22:
Figure 8-23:
Figure 9-1:
Figure 11-1:
Figure 11-2:
Figure 11-3:
Figure 11-4:
Figure 11-5:
Figure 11-6:
Figure 11-7:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 12-6:
Figure 12-7:
Figure 12-8:
ADCON1 Register, PIC16C710/71/711
(Address 88h),
PIC16C715 (Address 9Fh)........................ 38
A/D Block Diagram.................................... 39
Analog Input Model ................................... 40
A/D Transfer Function ............................... 45
Flowchart of A/D Operation....................... 45
Configuration Word for PIC16C71 ............ 47
Configuration Word, PIC16C710/711........ 48
Configuration Word, PIC16C715............... 48
Crystal/Ceramic Resonator Operation
(HS, XT or LP OSC Configuration) ........... 49
External Clock Input Operation
(HS, XT or LP OSC Configuration) ........... 49
External Parallel Resonant Crystal
Oscillator Circuit ........................................ 51
External Series Resonant Crystal
Oscillator Circuit ........................................ 51
RC Oscillator Mode ................................... 51
Simplified Block Diagram of On-chip
Reset Circuit.............................................. 52
Brown-out Situations ................................. 53
Time-out Sequence on Power-up
(MCLR not Tied to VDD): Case 1............... 59
Time-out Sequence on Power-up
(MCLR Not Tied To VDD): Case 2............. 59
Time-out Sequence on Power-up
(MCLR Tied to VDD) .................................. 59
External Power-on Reset Circuit
(for Slow VDD Power-up)........................... 60
External Brown-out Protection Circuit 1 .... 60
External Brown-out Protection Circuit 2 .... 60
Interrupt Logic, PIC16C710, 71, 711......... 62
Interrupt Logic, PIC16C715....................... 62
INT Pin Interrupt Timing ............................ 63
Watchdog Timer Block Diagram ............... 65
Summary of Watchdog Timer Registers ... 65
Wake-up from Sleep Through Interrupt..... 67
Typical In-Circuit Serial Programming
Connection ................................................ 67
General Format for Instructions ................ 69
Load Conditions ........................................ 94
External Clock Timing ............................... 95
CLKOUT and I/O Timing ........................... 96
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing ....................................................... 97
Brown-out Reset Timing............................ 97
Timer0 External Clock Timings ................. 98
A/D Conversion Timing ........................... 100
Typical IPD vs. VDD
(WDT Disabled, RC Mode) ..................... 101
Maximum IPD vs. VDD
(WDT Disabled, RC Mode) ..................... 101
Typical IPD vs. VDD @ 25°C
(WDT Enabled, RC Mode) ...................... 102
Maximum IPD vs. VDD
(WDT Enabled, RC Mode) ...................... 102
Typical RC Oscillator Frequency
vs. VDD .................................................... 102
Typical RC Oscillator Frequency
vs. VDD .................................................... 102
Typical RC Oscillator Frequency
vs. VDD .................................................... 102
Typical IPD vs. VDD Brown-out Detect
Enabled (RC Mode) ................................ 103
1997 Microchip Technology Inc.
Figure 12-9:
Figure 12-10:
Figure 12-11:
Figure 12-12:
Figure 12-13:
Figure 12-14:
Figure 12-15:
Figure 12-16:
Figure 12-17:
Figure 12-18:
Figure 12-19:
Figure 12-20:
Figure 12-21:
Figure 12-22:
Figure 12-23:
Figure 12-24:
Figure 12-25:
Figure 12-26:
Figure 12-27:
Figure 12-28:
Figure 12-29:
Figure 12-30:
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
Figure 13-5:
Figure 13-6:
Figure 13-7:
Figure 14-1:
Figure 14-2:
Figure 14-3:
Figure 14-4:
Figure 14-5:
Maximum IPD vs. VDD Brown-out Detect
Enabled (85°C to -40°C, RC Mode)........ 103
Typical IPD vs. Timer1 Enabled
(32 kHz, RC0/RC1 = 33 pF/33 pF,
RC Mode) ............................................... 103
Maximum IPD vs. Timer1 Enabled
(32 kHz, RC0/RC1 = 33 pF/33 pF,
85°C to -40°C, RC Mode) ....................... 103
Typical IDD vs. Frequency
(RC Mode @ 22 pF, 25°C) ..................... 104
Maximum IDD vs. Frequency
(RC Mode @ 22 pF, -40°C to 85°C) ....... 104
Typical IDD vs. Frequency
(RC Mode @ 100 pF, 25°C) ................... 105
Maximum IDD vs. Frequency
(RC Mode @ 100 pF, -40°C to 85°C) ..... 105
Typical IDD vs. Frequency
(RC Mode @ 300 pF, 25°C) ................... 106
Maximum IDD vs. Frequency
(RC Mode @ 300 pF, -40°C to 85°C) ..... 106
Typical IDD vs. Capacitance
@ 500 kHz (RC Mode) ........................... 107
Transconductance(gm) of
HS Oscillator vs. VDD .............................. 107
Transconductance(gm) of
LP Oscillator vs. VDD .............................. 107
Transconductance(gm) of
XT Oscillator vs. VDD .............................. 107
Typical XTAL Startup Time vs.
VDD (LP Mode, 25°C) ............................. 108
Typical XTAL Startup Time vs.
VDD (HS Mode, 25°C)............................. 108
Typical XTAL Startup Time vs.
VDD (XT Mode, 25°C) ............................. 108
Typical IDD vs. Frequency
(LP Mode, 25°C) ..................................... 109
Maximum IDD vs. Frequency
(LP Mode, 85°C to -40°C)....................... 109
Typical IDD vs. Frequency
(XT Mode, 25°C)..................................... 109
Maximum IDD vs. Frequency
(XT Mode, -40°C to 85°C) ...................... 109
Typical IDD vs. Frequency
(HS Mode, 25°C) .................................... 110
Maximum IDD vs. Frequency
(HS Mode, -40°C to 85°C) ...................... 110
Load Conditions...................................... 117
External Clock Timing............................. 118
CLKOUT and I/O Timing......................... 119
Reset, Watchdog Timer, Oscillator
Start-Up Timer, and Power-Up Timer
Timing ..................................................... 120
Brown-out Reset Timing ......................... 120
Timer0 Clock Timings ............................. 121
A/D Conversion Timing........................... 124
Typical IPD vs. VDD
(WDT Disabled, RC Mode) ..................... 125
Maximum IPD vs. VDD
(WDT Disabled, RC Mode) ..................... 125
Typical IPD vs. VDD @ 25°C
(WDT Enabled, RC Mode)...................... 126
Maximum IPD vs. VDD
(WDT Enabled, RC Mode)...................... 126
Typical RC Oscillator Frequency vs.
VDD ......................................................... 126
DS30390D-page 167
PIC16C71X
Figure 14-6:
Figure 14-7:
Figure 14-8:
Figure 14-9:
Figure 14-10:
Figure 14-11:
Figure 14-12:
Figure 14-13:
Figure 14-14:
Figure 14-15:
Figure 14-16:
Figure 14-17:
Figure 14-18:
Figure 14-19:
Figure 14-20:
Figure 14-21:
Figure 14-22:
Figure 14-23:
Figure 14-24:
Figure 14-25:
Figure 14-26:
Figure 14-27:
Figure 14-28:
Figure 14-29:
Figure 14-30:
Figure 15-1:
Figure 15-2:
Figure 15-3:
Figure 15-4:
Figure 15-5:
Figure 15-6:
Figure 16-1:
Figure 16-2:
Figure 16-3:
Typical RC Oscillator Frequency vs.
VDD .......................................................... 126
Typical RC Oscillator Frequency vs.
VDD .......................................................... 126
Typical IPD vs. VDD Brown-out Detect
Enabled (RC Mode) ................................ 127
Maximum IPD vs. VDD Brown-out Detect
Enabled
(85°C to -40°C, RC Mode) ...................... 127
Typical IPD vs. Timer1 Enabled (32 kHz,
RC0/RC1 = 33 pF/33 pF, RC Mode) ....... 127
Maximum IPD vs. Timer1 Enabled
(32 kHz, RC0/RC1 = 33 pF/33 pF,
85°C to -40°C, RC Mode)........................ 127
Typical IDD vs. Frequency
(RC Mode @ 22 pF, 25°C)...................... 128
Maximum IDD vs. Frequency
(RC Mode @ 22 pF, -40°C to 85°C)........ 128
Typical IDD vs. Frequency
(RC Mode @ 100 pF, 25°C).................... 129
Maximum IDD vs. Frequency
(RC Mode @ 100 pF, -40°C to 85°C)...... 129
Typical IDD vs. Frequency
(RC Mode @ 300 pF, 25°C).................... 130
Maximum IDD vs. Frequency
(RC Mode @ 300 pF, -40°C to 85°C)...... 130
Typical IDD vs. Capacitance @ 500 kHz
(RC Mode)............................................... 131
Transconductance(gm) of
HS Oscillator vs. VDD .............................. 131
Transconductance(gm) of
LP Oscillator vs. VDD ............................... 131
Transconductance(gm) of
XT Oscillator vs. VDD .............................. 131
Typical XTAL Startup Time vs.
VDD (LP Mode, 25°C).............................. 132
Typical XTAL Startup Time vs.
VDD (HS Mode, 25°C) ............................. 132
Typical XTAL Startup Time vs.
VDD (XT Mode, 25°C).............................. 132
Typical IDD vs. Frequency
(LP Mode, 25°C) ..................................... 133
Maximum IDD vs. Frequency
(LP Mode, 85°C to -40°C) ....................... 133
Typical IDD vs. Frequency
(XT Mode, 25°C) ..................................... 133
Maximum IDD vs. Frequency
(XT Mode, -40°C to 85°C) ....................... 133
Typical IDD vs. Frequency
(HS Mode, 25°C)..................................... 134
Maximum IDD vs. Frequency
(HS Mode, -40°C to 85°C)....................... 134
Load Conditions ...................................... 140
External Clock Timing ............................. 141
CLKOUT and I/O Timing ......................... 142
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing ..................................................... 143
Timer0 External Clock Timings ............... 144
A/D Conversion Timing ........................... 146
Typical RC Oscillator Frequency vs.
Temperature............................................ 147
Typical RC Oscillator Frequency vs.
VDD .......................................................... 147
Typical RC Oscillator Frequency vs.
VDD .......................................................... 147
DS30390D-page 168
Figure 16-4:
Figure 16-5:
Figure 16-6:
Figure 16-7:
Figure 16-8:
Figure 16-9:
Figure 16-10:
Figure 16-11:
Figure 16-12:
Figure 16-13:
Figure 16-14:
Figure 16-15:
Figure 16-16:
Figure 16-17:
Figure 16-18:
Figure 16-19:
Figure 16-20:
Figure 16-21:
Figure 16-22:
Typical RC Oscillator Frequency vs.
VDD ......................................................... 148
Typical Ipd vs. VDD Watchdog Timer
Disabled 25°C......................................... 148
Typical Ipd vs. VDD Watchdog Timer
Enabled 25°C.......................................... 148
Maximum Ipd vs. VDD Watchdog
Disabled .................................................. 149
Maximum Ipd vs. VDD Watchdog
Enabled................................................... 149
Vth (Input Threshold Voltage) of
I/O Pins vs. VDD ...................................... 149
VIH, VIL of MCLR, T0CKI and OSC1
(in RC Mode) vs. VDD ............................. 150
VTH (Input Threshold Voltage)
of OSC1 Input (in XT, HS, and
LP Modes) vs. VDD ................................. 150
Typical IDD vs. Freq (Ext Clock, 25°C).... 151
Maximum, IDD vs. Freq (Ext Clock,
-40° to +85°C) ......................................... 151
Maximum IDD vs. Freq with A/D Off
(Ext Clock, -55° to +125°C) .................... 152
WDT Timer Time-out Period vs. VDD ...... 152
Transconductance (gm) of
HS Oscillator vs. VDD .............................. 152
Transconductance (gm) of
LP Oscillator vs. VDD .............................. 153
Transconductance (gm) of
XT Oscillator vs. VDD .............................. 153
IOH vs. VOH, VDD = 3V .......................... 153
IOH vs. VOH, VDD = 5V .......................... 153
IOL vs. VOL, VDD = 3V ........................... 154
IOL vs. VOL, VDD = 5V ........................... 154
1997 Microchip Technology Inc.
PIC16C71X
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 4-1:
Table 4-2:
Table 5-1:
Table 5-2:
Table 5-3:
Table 5-4:
Table 6-1:
Table 7-1:
Table 7-2:
Table 7-3:
Table 7-4:
Table 8-1:
Table 8-2:
Table 8-3:
Table 8-4:
Table 8-5:
Table 8-6:
Table 8-7:
Table 8-8:
Table 8-9:
Table 8-10:
Table 8-11:
Table 8-12:
Table 8-13:
Table 9-1:
Table 9-2:
Table 10-1:
Table 11-1:
Table 11-2:
Table 11-3:
Table 11-4:
Table 11-5:
PIC16C71X Family of Devices.................... 4
PIC16C710/71/711/715 Pinout
Description .................................................. 9
PIC16C710/71/711 Special Function
Register Summary .................................... 14
PIC16C715 Special Function Register
Summary................................................... 15
PORTA Functions ..................................... 26
Summary of Registers Associated with
PORTA...................................................... 26
PORTB Functions ..................................... 28
Summary of Registers Associated with
PORTB...................................................... 29
Registers Associated with Timer0............. 35
TAD vs. Device Operating Frequencies,
PIC16C71.................................................. 41
TAD vs. Device Operating Frequencies,
PIC16C710/711, PIC16C715 .................... 41
Registers/Bits Associated with A/D,
PIC16C710/71/711.................................... 46
Registers/Bits Associated with A/D,
PIC16C715................................................ 46
Ceramic Resonators, PIC16C71............... 49
Capacitor Selection For Crystal
Oscillator, PIC16C71................................. 49
Ceramic Resonators,
PIC16C710/711/715.................................. 50
Capacitor Selection for Crystal
Oscillator, PIC16C710/711/715................. 50
Time-out in Various Situations,
PIC16C71.................................................. 54
Time-out in Various Situations,
PIC16C710/711/715.................................. 54
Status Bits and Their Significance,
PIC16C71.................................................. 55
Status Bits and Their Significance,
PIC16C710/711......................................... 55
Status Bits and Their Significance,
PIC16C715................................................ 55
Reset Condition for Special Registers,
PIC16C710/71/711.................................... 56
Reset Condition for Special Registers,
PIC16C715................................................ 56
Initialization Conditions For All Registers,
PIC16C710/71/711.................................... 57
Initialization Conditions for All Registers,
PIC16C715................................................ 58
Opcode Field Descriptions ........................ 69
PIC16CXX Instruction Set......................... 70
Development Tools From Microchip ......... 88
Cross Reference of Device Specs for
Oscillator Configurations and
Frequencies of Operation
(Commercial Devices)............................... 89
External Clock Timing Requirements........ 95
CLKOUT and I/O Timing Requirements.... 96
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer,
and Brown-out Reset Requirements ......... 97
Timer0 External Clock Requirements ....... 98
1997 Microchip Technology Inc.
Table 11-6:
Table 11-7:
Table 12-1:
Table 12-2:
Table 13-1:
Table 13-2:
Table 13-3:
Table 13-4:
Table 13-5:
Table 13-6:
Table 13-7:
Table 13-8:
Table 14-1:
Table 14-2:
Table 15-1:
Table 15-2:
Table 15-3:
Table 15-4:
Table 15-5:
Table 15-6:
Table 15-7:
Table 16-1:
A/D Converter Characteristics:
PIC16C710/711-04
(Commercial, Industrial, Extended)
PIC16C710/711-10
(Commercial, Industrial, Extended)
PIC16C710/711-20
(Commercial, Industrial, Extended)
PIC16LC710/711-04
(Commercial, Industrial, Extended) ...........99
A/D Conversion Requirements ............... 100
RC Oscillator Frequencies...................... 107
Capacitor Selection for Crystal
Oscillators ............................................... 108
Cross Reference of Device Specs for
Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) ............................ 112
Clock Timing Requirements.................... 118
CLKOUT and I/O Timing Requirements . 119
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer,
and Brown-out Reset Requirements....... 120
Timer0 Clock Requirements ................... 121
A/D Converter Characteristics:
PIC16C715-04
(Commercial, Industrial, Extended)
PIC16C715-10
(Commercial, Industrial, Extended)
PIC16C715-20
(Commercial, Industrial, Extended) ........ 122
A/D Converter Characteristics:
PIC16LC715-04 (Commercial,
Industrial) ................................................ 123
A/D Conversion Requirements ............... 124
RC Oscillator Frequencies...................... 131
Capacitor Selection for Crystal
Oscillators ............................................... 132
Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) ............................ 135
External Clock Timing Requirements ..... 141
CLKOUT and I/O Timing Requirements . 142
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Requirements ......................................... 143
Timer0 External Clock Requirements ..... 144
A/D Converter Characteristics ................ 145
A/D Conversion Requirements ............... 146
RC Oscillator Frequencies...................... 148
DS30390D-page 169
PIC16C71X
NOTES:
DS30390D-page 170
1997 Microchip Technology Inc.
PIC16C71X
ON-LINE SUPPORT
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1997 Microchip Technology Inc.
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DS30272A-page 171
PIC16C71X
READER RESPONSE
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Literature Number: DS30272A
Questions:
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DS30272A-page 172
1997 Microchip Technology Inc.
PIC16C71X
PIC16C71X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office.
Examples
PART NO. -XX X /XX XXX
Pattern:
Package:
Temperature
Range:
Frequency
Range:
Device
QTP, SQTP, Code or Special Requirements
a)
JW
= Windowed CERDIP
SO
= SOIC
SP
= Skinny plastic dip
P
= PDIP
SS
= SSOP
b)
= 0°C to +70°C
I
= -40°C to +85°C
E
= -40°C to +125°C
04
= 200 kHz (PIC16C7X-04)
04
= 4 MHz
10
= 10 MHz
20
= 20 MHz
PIC16C7X
:VDD range 4.0V to 6.0V
PIC16C7XT :VDD range 4.0V to 6.0V (Tape/Reel)
PIC16LC7X :VDD range 2.5V to 6.0V
PIC16LC7XT :VDD range 2.5V to 6.0V (Tape/Reel)
PIC16C71 - 04/P 301
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits, QTP
pattern #301
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1997 Microchip Technology Inc.
DS30272A-page 173
PIC16C71X
NOTES:
DS30272A-page 174
1997 Microchip Technology Inc.
PIC16C71X
NOTES:
1997 Microchip Technology Inc.
DS30272A-page 175
Note the following details of the code protection feature on PICmicro® MCUs.
•
•
•
•
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
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2002 Microchip Technology Inc.
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