PIC16C745/765
8-Bit CMOS Microcontrollers with USB
Devices included in this data sheet:
• PIC16C765
28-Pin DIP, SOIC
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions
Memory
Program
x14
Data
x8
Pins
A/D
Resolution
A/D
Channels
PIC16C745
8K
256
28
8
5
PIC16C765
8K
256
40
8
8
Device
• All single cycle instructions except for program
branches which are two cycle
• Interrupt capability (up to 12 internal/external
interrupt sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
- EC - External clock (24 MHz)
- E4 - External clock with PLL (6 MHz)
- HS - Crystal/Resonator (24 MHz)
- H4 - Crystal/Resonator with PLL (6 MHz)
• Processor clock of 24 MHz derived from 6 MHz
crystal or resonator
• Fully static low-power, high-speed CMOS
• In-Circuit Serial Programming(ICSP)
• Operating voltage range
- 4.35 to 5.25V
• High Sink/Source Current 25/25 mA
• Wide temperature range
- Industrial (-40C - 85C)
• Low-power consumption:
- ~ 16 mA @ 5V, 24 MHz
- 100 A typical standby current
1999-2013 Microchip Technology Inc.
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4
Vss
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VUSB
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16C745
• PIC16C745
Pin Diagrams
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
Vss
RC7/RX/DT
RC6/TX/CK
D+
D-
Peripheral Features:
• Universal Serial Bus (USB 1.1)
- Soft attach/detach
• 64 bytes of USB dual port RAM
• 22 (PIC16C745) or 33 (PIC16C765) I/O pins
- Individual direction control
- 1 high voltage open drain (RA4)
- 8 PORTB pins with:
- Interrupt-on-change control (RB only)
- Weak pull-up control
- 3 pins dedicated to USB
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• 2 Capture, Compare and PWM modules
- Capture is 16-bit, max. resolution is 10.4 ns
- Compare is 16-bit, max. resolution is 167 ns
- PWM maximum resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (PIC16C765 only)
Preliminary
DS41124D-page 1
RC6/TX/CK
D+
DRD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
VUSB
RC2/CCP1
RC1/T1OSI/CCP2
NC
44-Pin TQFP
PIC16C765
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
PIC16C765
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4
RA4/T0CKI
NC
NC
RB4
RB5
RB6
RB7
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RC1/T1OSI/CCP2
RC2/CCP1
VUSB
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
DD+
RC6/TX/CK
NC
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
12
13
14
15
16
17
18
19
20
21
22
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
44
43
42
41
40
39
38
37
36
35
34
6
5
4
3
2
1
44
43
42
41
40
44-Pin PLCC
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
PIC16C745/765
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VUSB
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16C765
40-Pin DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
D+
DRD3/PSP3
RD2/PSP2
Key Features
PICmicroTM Mid-Range Reference Manual
(DS33023)
PIC16C745
PIC16C765
Operating Frequency
6 MHz or 24 MHz
6 MHz or 24 MHz
Resets (and Delays)
POR, BOR (PWRT, OST)
POR, BOR (PWRT, OST)
Program Memory (14-bit words)
8K
8K
Data Memory (bytes)
256
256
Dual Port Ram
64
64
Interrupt Sources
11
12
I/O Ports
22 (Ports A, B, C)
33 (Ports A, B, C, D, E)
Timers
3
3
Capture/Compare/PWM modules
2
2
Analog-to-Digital Converter Module
5 channel x 8 bit
8 channel x 8 bit
Parallel Slave Port
—
Yes
Serial Communication
USB, USART/SCI
USB, USART/SCI
Brown-out Detect Reset
Yes
Yes
DS41124D-page 2
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
Table of Contents
1.0 General Description .............................................................................................................................................. 5
2.0 PIC16C745/765 Device Varieties ......................................................................................................................... 7
3.0 Architectural Overview .......................................................................................................................................... 9
4.0 Memory Organization.......................................................................................................................................... 15
5.0 I/O Ports.............................................................................................................................................................. 31
6.0 Timer0 Module .................................................................................................................................................... 43
7.0 Timer1 Module .................................................................................................................................................... 45
8.0 Timer2 Module .................................................................................................................................................... 49
9.0 Capture/Compare/PWM Modules ....................................................................................................................... 51
10.0 Universal Serial Bus............................................................................................................................................ 57
11.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................. 77
12.0 Analog-to-Digital Converter (A/D) Module .......................................................................................................... 91
13.0 Special Features of the CPU .............................................................................................................................. 99
14.0 Instruction Set Summary................................................................................................................................... 113
15.0 Development Support ....................................................................................................................................... 121
16.0 Electrical Characteristics................................................................................................................................... 127
17.0 DC and AC Characteristics Graphs and Tables ............................................................................................... 145
18.0 Packaging Information ...................................................................................................................................... 147
Index .......................................................................................................................................................................... 157
On-Line Support.......................................................................................................................................................... 161
Reader Response ....................................................................................................................................................... 162
Product Identification System ..................................................................................................................................... 163
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
• E-mail us at webmaster@microchip.com.
We appreciate your assistance in making this a better document.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 3
PIC16C745/765
NOTES:
DS41124D-page 4
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
1.0
GENERAL DESCRIPTION
The PIC16C745/765 devices are low cost, high-performance, CMOS, fully-static, 8-bit microcontrollers in the
PIC16CXX mid-range family.
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC16C745/765 microcontroller family has enhanced core features, eight-level deep stack
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches, which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
The PIC16C745 device has 22 I/O pins. The
PIC16C765 device has 33 I/O pins. Each device has
256 bytes of RAM. In addition, several peripheral features are available including: three timer/counters, two
Capture/Compare/PWM modules and two serial ports.
The Universal Serial Bus (USB 1.1) low speed peripheral provides bus communications. The Universal
Synchronous Asynchronous Receiver Transmitter
(USART) is also known as the Serial Communications
Interface or SCI. Also, a 5-channel high-speed 8-bit
A/D is provided on the PIC16C745, while the
PIC16C765 offers 8 channels. The 8-bit resolution is
ideally suited for applications requiring a low cost analog interface (e.g., thermostat control, pressure sensing, etc.).
The PIC16C745/765 devices have special features to
reduce external components, thus reducing cost,
enhancing system reliability and reducing power consumption. There are 4 oscillator options, of which EC is
for the external regulated clock source, E4 is for the
external regulated clock source with the PLL enabled,
HS is for the high speed crystals/resonators and H4 is
for high speed crystals/resonators with the PLL
enabled. The SLEEP (power-down) feature provides a
power-saving mode. The user can wake-up the chip
from SLEEP through several external and internal
interrupts and RESETS.
1999-2013 Microchip Technology Inc.
A highly reliable Watchdog Timer (WDT), with a dedicated on-chip RC oscillator, provides protection against
software lock-up, and also provides one way of waking
the device from SLEEP.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost-effective One-TimeProgrammable (OTP) version is suitable for production
in any volume.
The PIC16C745/765 devices fit nicely in many applications ranging from security and remote sensors to appliance controls and automotives. The EPROM
technology makes customization of application programs (data loggers, industrial controls, UPS)
extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all
applications with space limitations. Low-cost, lowpower, high-performance, ease of use and I/O flexibility
make the PIC16C745/765 devices very versatile, even
in areas where no microcontroller use has been considered before (e.g., timer functions, serial communication,
capture and compare, PWM functions and coprocessor
applications).
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the
PIC16C5X architecture. Code written for the
PIC16C5X can be easily ported to the PIC16C745/765
family of devices.
1.2
Development Support
PIC® devices are supported by the complete line of
Microchip Development tools.
Please refer to Section 15.0 for more details about
Microchip’s development tools.
Preliminary
DS41124D-page 5
PIC16C745/765
NOTES:
DS41124D-page 6
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
2.0
PIC16C745/765 DEVICE
VARIETIES
2.3
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C745/765 Product
Identification System section at the end of this data
sheet. When placing orders, please use that page of
the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in windowed CERDIP
packages, is optimal for prototype development and
pilot programs. This version can be erased and
reprogrammed to any of the supported oscillator
modes.
Plus and PRO MATE II
Microchip's PICSTART
programmers both support programming of the
PIC16C745/765.
2.2
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 7
PIC16C745/765
NOTES:
DS41124D-page 8
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C745/765 family
can be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C745/765 uses a Harvard architecture,
in which program and data are accessed from separate
memories using separate buses. This improves bandwidth over traditional von Neumann architecture in
which program and data are fetched from the same
memory using the same bus. Separating program and
data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes
are 14-bits wide making it possible to have all single
word instructions. A 14-bit wide program memory
access bus fetches a 14-bit instruction in a single cycle.
A two-stage pipeline overlaps fetch and execution of
instructions (Example 3-1). Consequently, most
instructions execute in a single cycle (166.6667 ns @
24 MHz) except for program branches.
Memory
Device
A/D
A/D
Resolution Channels
Program
x14
Data
x8
Pins
PIC16C745
8K
256
28
8
5
PIC16C765
8K
256
40
8
8
PIC16C745/765 devices contain an 8-bit ALU and
working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions
between the data in the working register and any register file.
The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
The PIC16C745/765 can directly or indirectly address
its register files or data memory. All special function
registers, including the program counter, are mapped in
the data memory. The PIC16C745/765 has an orthogonal (symmetrical) instruction set that makes it possible
to carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C745/765 simple yet efficient. In addition, the
learning curve is reduced significantly.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 9
PIC16C745/765
FIGURE 3-1:
PIC16C745/765 BLOCK DIAGRAM
13
Program
Memory
Program
Bus
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4
RAM
File
Registers
256 x 8
8 Level Stack
(13 bit)
8K x 14
PORTA
8
Data Bus
Program Counter
EPROM
14
RAM Addr(1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
RB0/INT
Indirect
Addr
RB
FSR reg
STATUS reg
8
PORTC
3
Power-up
Timer
Instruction
Decode &
Control
OSC1/
CLKIN
OSC2/
CLKOUT
Timing
Generation
x4 PLL
Oscillator
Start-up Timer
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC6/TX/CK
RC7/RX/DT
MUX
ALU
Power-on
Reset
8
Watchdog
Timer
Brown-out
Reset
PORTD
W reg
RD3:0/PSP3:0(2)
RD4/PSP4(2)
RD5/PSP5(2)
RD6/PSP6(2)
RD7/PSP7(2)
Parallel Slave Port(2)
MCLR
Timer0
Timer1
CCP2
CCP1
VDD, VSS
Timer2
PORTE
RE0/AN5/RD(2)
RE1/AN6/WR(2)
RE2/AN7/CS(2)
8-bit A/D
Dual Port
RAM
64 x 8
USART
USB
XCVR
VUSB
DD+
Note 1: Higher order bits are from the STATUS register.
2: Not available on PIC16C745.
DS41124D-page 10
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
TABLE 3-1:
PIC16C745/765 PINOUT DESCRIPTION
Name
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Function
Input
Type
Output
Type
MCLR
ST
—
Master Clear
VPP
Power
—
Programming Voltage
OSC1
Xtal
—
Crystal/Resonator
CLKIN
ST
—
External Clock Input
OSC2
—
Xtal
CLKOUT
—
CMOS
Internal Clock (FINT/4) Output
RA0
ST
CMOS
Bi-directional I/O
AN0
AN
—
RA1
ST
CMOS
AN1
AN
—
RA2
ST
CMOS
AN2
AN
—
RA3
ST
CMOS
AN3
AN
—
VREF
AN
—
A/D Positive Reference
RA4
ST
OD
Bi-directional I/O
T0CKI
ST
—
Timer 0 Clock Input
A/D Input
Bi-directional I/O
A/D Input
Bi-directional I/O
A/D Input
ST
AN
—
RB0
TTL
CMOS
INT
ST
—
RB1
RB1
TTL
CMOS
Bi-directional I/O(1)
RB2
RB2
TTL
CMOS
Bi-directional I/O(1)
RB3
RB3
TTL
CMOS
Bi-directional I/O(1)
RB4
RB4
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change(1)
RB5
RB5
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change(1)
RB6
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change(1)
RB6/ICSPC
RB7/ICSPD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
Bi-directional I/O
RC2/CCP1
A/D Input
Bi-directional I/O(1)
Interrupt
ICSPC
ST
RB7
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change(1)
In-Circuit Serial Programming Clock Input
ICSPD
ST
CMOS
In-Circuit Serial Programming Data I/O
RC0
ST
CMOS
Bi-directional I/O
T1OSO
—
Xtal
T1CKI
ST
—
RC1
ST
CMOS
T1OSI
Xtal
—
CCP2
2:
A/D Input
Bi-directional I/O
AN4
RB0/INT
Note 1:
Crystal/Resonator
RA5
RA5/AN4
Legend:
Description
RC2
VUSB
D-
D-
T1 Clock Input
Bi-directional I/O
T1 Oscillator Input
Capture In/Compare Out/PWM Out 2
ST
CMOS
CCP1
VUSB
T1 Oscillator Output
Bi-directional I/O
Capture In/Compare Out/PWM Out 1
Power
Regulator Output Voltage
USB
USB
USB Differential Bus
D+
D+
USB
OD = open drain, ST = Schmitt Trigger
USB
USB Differential Bus
Weak pull-ups. PORT B pull-ups are byte wide programmable.
PIC16C765 only.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 11
PIC16C745/765
TABLE 3-1:
PIC16C745/765 PINOUT DESCRIPTION (CONTINUED)
Name
RC6/TX/CK
RC6
ST
CMOS
Bi-directional I/O
TX
—
CMOS
USART Async Transmit
Description
ST
CMOS
USART Master Out/Slave In Clock
ST
CMOS
Bi-directional I/O
RX
ST
—
DT
ST
CMOS
USART Data I/O
RD0
TTL
CMOS
Bi-directional I/O(2)
PSP0
TTL
—
RD1
TTL
CMOS
PSP1
TTL
—
RD2
TTL
CMOS
PSP2
TTL
—
RD3
TTL
CMOS
PSP3
TTL
—
RD4
TTL
CMOS
PSP4
TTL
—
RD5
TTL
CMOS
PSP5
TTL
—
RD6
TTL
CMOS
PSP6
TTL
—
RD7
TTL
CMOS
PSP7
TTL
—
RE0
ST
CMOS
RD
TTL
—
Parallel Slave Port Control Input(2)
AN5
AN
—
A/D Input(2)
RE1
ST
CMOS
WR
TTL
—
Parallel Slave Port Control Input(2)
AN6
AN
—
A/D Input(2)
RE2
ST
CMOS
CS
TTL
—
Parallel Slave Port Data Input(2)
AN7
AN
—
A/D Input(2)
VDD
Power
—
Power
VSS
VSS
Power
OD = open drain, ST = Schmitt Trigger
—
Ground
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
2:
Output
Type
CK
RD0/PSP0
Note 1:
Input
Type
RC7
RC7/RX/DT
Legend:
Function
USART Async Receive
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Parallel Slave Port Data Input(2)
Bi-directional I/O(2)
Bi-directional I/O(2)
Bi-directional I/O(2)
Weak pull-ups. PORT B pull-ups are byte wide programmable.
PIC16C765 only.
DS41124D-page 12
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input feeds either an on-chip PLL, or directly
drives (FINT). The clock output from either the PLL or
direct drive (FINT) is internally divided by four to generate four non-overlapping quadrature clocks namely,
Q1, Q2, Q3 and Q4. Internally, the program counter
(PC) is incremented every Q1, the instruction is fetched
from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks
and instruction execution flow is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
FINT
Q1
Internal
phase
clock
Q2
Q3
Q4
PC
OSC2/CLKOUT
(EC mode)
EXAMPLE 3-1:
1. MOVLW 55h
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3 (Forced NOP)
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
Note:
PC+2
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 13
PIC16C745/765
NOTES:
DS41124D-page 14
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
4.0
MEMORY ORGANIZATION
4.2
4.1
Program Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
The PIC16C745/765 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. All devices covered by this data sheet have 8K
x 14 bits of program memory. The address range is
0000h - 1FFFh for all devices.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1:
PIC16C745/765 PROGRAM
MEMORY MAP AND STACK
PC
CALL, RETURN
RETFIE, RETLW
Data Memory Organization
RP (STATUS)
= 00 Bank0
= 01 Bank1
= 10 Bank2
= 11 Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All implemented banks contain SFRs. Some “high use”
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
13
Stack Level 1
4.2.1
GENERAL PURPOSE REGISTER FILE
Stack Level 2
The register file can be accessed either directly or indirectly through the File Select Register (FSR)
(Section 4.5).
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
On-chip
Program
Memory
Page 1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
1FFFh
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 15
PIC16C745/765
FIGURE 4-2:
Bank 0
DATA MEMORY MAP FOR PIC16C745/765
File
Address
Bank 1
File
Address
Bank 2
File
Address
Bank 3
File
Address
Indirect addr.(*)
00h
Indirect addr.(*)
80h
Indirect addr.(*)
100h
Indirect addr.(*)
180h
TMR0
01h
OPTION_REG
81h
TMR0
101h
OPTION_REG
181h
182h
PCL
02h
PCL
82h
PCL
102h
PCL
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
105h
185h
PORTA
05h
TRISA
85h
PORTB
06h
TRISB
86h
PORTC
07h
TRISC
87h
107h
187h
PORTD(2)
08h
TRISD(2)
88h
108h
188h
PORTB
106h
TRISB
186h
PORTE(2)
09h
TRISE(2)
89h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
10Ch
18Ch
PIR2
0Dh
PIE2
8Dh
10Dh
18Dh
TMR1L
0Eh
PCON
8Eh
10Eh
18Eh
TMR1H
0Fh
8Fh
10Fh
T1CON
10h
90h
110h
TMR2
11h
T2CON
12h
109h
189h
18Fh
UIR
190h
191h
91h
111h
UIE
92h
112h
UEIR
192h
13h
93h
113h
UEIE
193h
PR2
14h
94h
114h
USTAT
194h
CCPR1L
15h
95h
115h
UCTRL
195h
CCPR1H
16h
96h
116h
UADDR
CCP1CON
17h
97h
117h
USWSTAT
197h
RCSTA
18h
TXSTA
98h
118h
UEP0
198h
TXREG
19h
SPBRG
99h
119h
UEP1
199h
RCREG
1Ah
9Ah
11Ah
UEP2
CCPR2L
1Bh
9Bh
11Bh
19Bh(1)
CCPR2H
1Ch
9Ch
11Ch
19Ch(1)
CCP2CON
1Dh
9Dh
11Dh
19Dh(1)
ADRES
1Eh
9Eh
11Eh
19Eh(1)
ADCON0
1Fh
ADCON1
9Fh
11Fh
19Fh(1)
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
80 Bytes
A0h
General
Purpose
Register
80 Bytes
120h
196h
(1)
USB Dual Port
Memory
64 Bytes
19Ah
1A0h
1DFh
1E0h
EFh
7Fh
accesses
70h-7Fh
F0h
FFh
16Fh
accesses
70h-7Fh
170h
17Fh
1EFh
accesses
70h-7Fh
1F0h
1FFh
Unimplemented data memory locations, read as ‘0’.
*Not a physical register.
Note 1: Reserved registers may contain USB state information.
2: Parallel slave ports (PORTD and PORTE) not implemented on PIC16C745; always maintain these bits clear.
DS41124D-page 16
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
Address
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 0
00h
INDF(3)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
PCL(3)
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h
STATUS
04h
FSR(3)
05h
PORTA
06h
PORTB
(3)
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
Indirect data memory address pointer
—
—
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--0x 0000 --0u 0000
PORTB Data Latch when written: PORTB pins when read
RC7
RC6
07h
PORTC
08h
PORTD(4)
09h
PORTE(4)
—
—
—
0Ah
PCLATH(1,3)
—
—
—
0Bh
INTCON(3)
0Ch
PIR1
—
—
xxxx xxxx uuuu uuuu
RC2
—
RC1
RC0
PORTD Data Latch when written: PORTD pins when read
—
xx-- -xxx uu-- -uuu
xxxx xxxx uuuu uuuu
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
---- -xxx ---- -uuu
---0 0000 ---0 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
PSPIF(4)
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
—
—
—
–
—
—
—
CCP2IF
---- ---0 ---- ---0
0Dh
PIR2
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
11h
TMR2
12h
T2CON
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
Timer2 module’s register
—
TOUTPS3
--00 0000 --uu uuuu
0000 0000 0000 0000
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
18h
RCSTA
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
CCPR2L
Capture/Compare/PWM Register2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
1Eh
ADRES
1Fh
ADCON0
—
—
DC2B1
DC2B1
CCP2M3
CCP2M2
CCP2M1
CCP2M0
A/D Result Register
ADCS1
ADCS0
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 17
PIC16C745/765
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 1
80h
INDF(3)
Addressing this location uses contents of FSR to address data memory (not a physical register)
81h
OPTION
82h
PCL(3)
83h
STATUS
84h
FSR(3)
85h
TRISA
86h
TRISB
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
0000 0000 0000 0000
PS0
Program Counter's (PC) Least Significant Byte
(3)
IRP
RP1
RP0
0000 0000 0000 0000
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
TRISC8
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
PORTB Data Direction Register
TRISC7
1111 1111 1111 1111
1111 1111 1111 1111
TRISC2
TRISC1
TRISC0
87h
TRISC
88h
TRISD(4)
89h
TRISE(4)
IBF
OBF
IBOV
8Ah
PCLATH(1,3)
—
—
—
8Bh
INTCON(3)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE(4)
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0 ---- ---0
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
—
—
91h
92h
—
PR2
—
—
—
PORTD Data Direction Register
11-- -111 11-- -111
1111 1111 1111 1111
PSPMODE
—
PORTE Data Direction Bits
0000 -111 0000 -111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
Unimplemented
Timer2 Period Register
1111 1111 1111 1111
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
Unimplemented
—
—
97h
—
98h
TXSTA
99h
SPBRG
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
Baud Rate Generator Register
0000 -010 0000 -010
0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
---- -000
---- -000
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
DS41124D-page 18
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 2
100h
INDF(3)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
101h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
102h
(3)
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
103h
104h
PCL
STATUS
FSR
(3)
(3)
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
105h
—
106h
PORTB
Unimplemented
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
—
—
—
PCLATH
10Bh
INTCON(3)
—
—
—
—
GIE
PEIE
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
Unimplemented
—
xxxx xxxx uuuu uuuu
Unimplemented
(1,3)
10Ah
10Ch11Fh
—
PORTB Data Latch when written: PORTB pins when read
T0IF
INTF
---0 0000 ---0 0000
RBIF
0000 000x 0000 000u
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 19
PIC16C745/765
TABLE 4-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 3
180h
INDF(3)
181h
OPTION_REG
182h
PCL(3)
183h
184h
STATUS
FSR
185h
186h
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
0000 0000 0000 0000
PS0
Program Counter's (PC) Least Significant Byte
(3)
(3)
—
TRISB
IRP
RP1
RP0
TO
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
Unimplemented
—
PORTB Data Direction Register
—
1111 1111 1111 1111
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
18Ah
PCLATH(1,3)
18Bh
INTCON(3)
18Ch18Fh
—
—
—
—
GIE
PEIE
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
---0 0000 ---0 0000
RBIF
Unimplemented
0000 000x 0000 000u
—
190h
UIR
191h
UIE
192h
UEIR
BTS_ERR OWN_ERR WRT_ERR
193h
UEIE
BTS_ERR OWN_ERR WRT_ERR
194h
USTAT
—
195h
UCTRL
—
196h
UADDR
—
—
—
STALL
—
—
STALL
—
UIDLE
TOK_DNE
ACTIVITY
UERR
USB_RST --00 0000 --00 0000
UIDLE
TOK_DNE
ACTIVITY
UERR
USB_RST --00 0000 --00 0000
BTO_ERR
DFN8
CRC16
CRC5
PID_ERR 0000 0000 0000 0000
PID_ERR 0000 0000 0000 0000
BTO_ERR
DFN8
CRC16
CRC5
—
ENDP1
ENDP0
IN
—
—
SEO
PKT_DIS
DEV_ATT
RESUME
SUSPND
—
--x0 000- --xq qqq-
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
-000 0000 -000 0000
SWSTAT3
SWSTAT2
SWSTAT1
—
—
---x xx-- ---u uu--
197h
USWSTAT
SWSTAT7
SWSTAT6
SWSTAT5
SWSTAT4
198h
UEP0
—
—
—
—
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
199h
UEP1
—
—
—
—
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
19Ah
UEP2
—
—
—
—
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
19Bh19Fh
Reserved
Reserved, do not use.
SWSTAT0 0000 0000 0000 0000
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
DS41124D-page 20
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
TABLE 4-2:
Address
Name
USB DUAL PORT RAM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PID1
DTS
PID0
BSTALL
—
—
—
—
1A0h
BD0OST
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
1A1h
BD0OBC
—
—
—
—
1A2h
BD0OAL
1A3h
—
Buffer Address Low
—
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
1A5h
BD0IBC
—
—
—
—
1A6h
BD0IAL
PID3
—
PID2
—
1A9h
BD1OBC
—
—
—
—
1AAh
BD1OAL
PID3
—
PID2
—
1ADh
BD1IBC
—
—
—
—
1AEh
BD1IAL
—
—
—
—
Byte Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PID1
DTS
PID0
BSTALL
—
—
—
—
Byte Count
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
xxxx xxxx uuuu uuuu
Reserved
—
1B0h
BD2OST
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
1B1h
BD2OBC
—
—
—
—
1B2h
BD2OAL
PID1
DTS
PID0
BSTALL
—
—
—
—
Byte Count
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
xxxx xxxx uuuu uuuu
Reserved
—
1B4h
BD2IST
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
1B5h
BD2IBC
—
—
—
—
1B6h
BD2IAL
1B8h1DFh
PID0
BSTALL
—
DATA0/1
DATA0/1
—
PID1
DTS
—
xxxx xxxx uuuu uuuu
UOWN
UOWN
1B7h
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Reserved
BD1IST
—
Byte Count
Buffer Address Low
1ACh
1B3h
—
—
—
DATA0/1
DATA0/1
—
—
—
—
xxxx xxxx uuuu uuuu
UOWN
UOWN
1AFh
PID0
BSTALL
Buffer Address Low
BD1OST
—
PID1
DTS
Reserved
1A8h
1ABh
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
BD0IST
—
Value on all
other resets
(1)
xxxx xxxx uuuu uuuu
Reserved
1A4h
1A7h
Byte Count
Value on:
POR,
BOR
PID1
DTS
PID0
BSTALL
—
—
Byte Count
Buffer Address Low
—
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Reserved
—
40 byte USB Buffer
—
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 21
PIC16C745/765
4.2.2.1
STATUS REGISTER
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
It is recommended that only BCF, BSF, SWAPF and
MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, C or DC bits
in the STATUS register. For other instructions which do
not affect status bits, see the "Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as borrow and
digit borrow bits, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 4-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
R/W-0
IRP
bit7
bit 7:
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C(1)
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
DS41124D-page 22
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
4.2.2.2
OPTION REGISTER
Note:
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external INT Interrupt,
TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
R/W-1
RBPU
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION REGISTER (OPTION_REG: 81h, 181h)
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
bit7
R/W-1
PS0
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 2-0: PS: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1999-2013 Microchip Technology Inc.
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
DS41124D-page 23
PIC16C745/765
4.2.2.3
INTCON REGISTER
Note:
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-3: INTERRUPT CONTROL REGISTER (INTCON: 10Bh, 18Bh)
R/W-0
GIE
bit7
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB pins changed state (must be cleared in software)
0 = None of the RB pins have changed state
DS41124D-page 24
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
4.2.2.4
PIE1 REGISTER
Note:
This register contains the individual enable bits for the
peripheral interrupts.
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
REGISTER 4-4: PERIPHERAL INTERRUPT ENABLE1 REGISTER (PIE1: 8Ch)
R/W-0
(1)
PSPIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
RCIE
TXIE
USBIE
CCP1IE
R/W-0
R/W-0
TMR2IE TMR1IE
bit7
bit0
bit 7:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5:
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4:
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3:
USBIE: Universal Serial Bus Interrupt Enable bit
1 = Enables the USB interrupt
0 = Disables the USB interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
Note 1: Parallel slave ports not implemented on the PIC16C745; always maintain this bit clear.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 25
PIC16C745/765
4.2.2.5
PIR1 REGISTER
Note:
This register contains the individual flag bits for the
peripheral interrupts.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-5: PERIPHERAL INTERRUPT REGISTER1 (PIR1: 0Ch)
R/W-0
PSPIF
(1)
R/W-0
R-0
R-0
R/W-0
R/W-0
ADIF
RCIF
TXIF
USBIF
CCP1IF
R/W-0
R/W-0
TMR2IF TMR1IF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5:
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (clear by reading RCREG)
0 = The USART receive buffer is empty
bit 4:
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (clear by writing to TXREG)
0 = The USART transmit buffer is full
bit 3:
USBIF: Universal Serial Bus (USB) Interrupt Flag
1 = A USB interrupt condition has occurred. The specific cause can be found by examining the contents
of the UIR and UIE registers.
0 = No USB interrupt conditions that are enabled have occurred.
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: Parallel slave ports not implemented on the PIC16C745; always maintain this bit clear.
DS41124D-page 26
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
4.2.2.6
PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6: PERIPHERAL INTERRUPT ENABLE 2 REGISTER (PIE2: 8Dh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
4.2.2.7
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIR2 REGISTER
This register contains the CCP2 interrupt flag bit.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-7:
U-0
—
bit7
PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 27
PIC16C745/765
4.2.2.8
PCON REGISTER
Note:
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 4-8:
U-0
—
U-0
—
BOR is unknown on POR. It must be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred.
POWER CONTROL REGISTER REGISTER (PCON: 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
bit7
R/W-q
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS41124D-page 28
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
4.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 4-3 shows the two situations
for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL
(PCLATH PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH PCH).
FIGURE 4-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
5
8
PCLATH
Instruction with
PCL as
Destination
ALU
PCLATH
PCH
12
11 10
0
7
PC
GOTO,CALL
2
PCLATH
2: There are no instructions/mnemonics
called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address.
4.4
Program Memory Paging
PIC16CXX devices are capable of addressing a continuous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack.
Therefore, manipulation of the PCLATH bits is
not required for the return instructions (which POPs the
address from the stack).
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt service routine (if interrupts are used).
PCL
8
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
11
Opcode
EXAMPLE 4-1:
PCLATH
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BSF PCLATH,3
CALL SUB1_P1
:
:
ORG 0x900
SUB1_P1
:
:
:
RETURN
;Select page 1 (800h-FFFh)
;Call subroutine in
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call subroutine
;in page 0 (000h-7FFh)
STACK
The PIC16C745/765 family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event
of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 29
PIC16C745/765
4.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-2:
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
movlw
movwf
clrf
incf
btfss
goto
NEXT
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS), as shown in Figure 4-4.
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
RP
6
bank select
location select
0
IRP
7
bank select
00
01
10
FSR register
0
location select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory
Bank 0
Note:
Bank 1
Bank 2
Bank 3
For register file map detail see Figure 4-2.
DS41124D-page 30
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
5.0
I/O PORTS
FIGURE 5-1:
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
5.1
WR
Port
PORTA and TRISA Registers
PORTA is a 6-bit latch.
BLOCK DIAGRAM OF RA
AND RA5 PINS
D
Q
VDD
Q
CK
P
Data Latch
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers), which can configure these pins as output or input.
D
WR
TRIS
Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
VSS
Q
CK
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
On the PIC16C745/765, PORTA pins are multiplexed
with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control
Register1).
Analog
Input
Mode
TRIS Latch
Q
RD Port
To A/D Converter
FIGURE 5-2:
INITIALIZING PORTA
(PIC16C745/765)
STATUS, RP1
STATUS, RP0
PORTA
BSF
MOVLW
MOVWF
MOVLW
STATUS, RP0
0x06
ADCON1
0xCF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
D
EN
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
BCF
BCF
CLRF
Schmitt Trigger
Input Buffer
RD TRIS
On all RESETS, pins with analog and digital functions are configured as analog
inputs.
EXAMPLE 5-1:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
VDD
Data
Bus
WR
Port
D
Q
CK
Q
N
Data Latch
WR
TRIS
D
Q
CK
Q
Preliminary
I/O pin
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
Initialize PORTA by
clearing output
data latches
Select Bank 1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA as inputs
RA as outputs
TRISA are always
read as '0'.
1999-2013 Microchip Technology Inc.
I/O Pin
N
Q
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified, and then written to the port
data latch.
Note:
VDD
RD TRIS
Q
D
ENEN
RD Port
TMR0 Clock Input
DS41124D-page 31
PIC16C745/765
TABLE 5-1:
PORTA FUNCTIONS
Name
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4
Legend:
Output
Type
RA0
ST
CMOS
AN0
AN
—
RA1
ST
CMOS
AN1
AN
—
RA2
ST
CMOS
Description
Bi-directional I/O
A/D Input
Bi-directional I/O
A/D Input
Bi-directional I/O
AN2
AN
—
RA3
ST
CMOS
AN3
AN
—
VREF
AN
—
A/D Positive Reference
RA4
ST
OD
Bi-directional I/O
T0CKI
ST
—
RA5
ST
A/D Input
Bi-directional I/O
A/D Input
Timer 0 Clock Input
Bi-directional I/O
AN4
AN
OD = open drain, ST = Schmitt Trigger
TABLE 5-2:
Address
Input
Type
Function
—
A/D Input
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0u 0000
--11 1111
--11 1111
---- -000
---- -000
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1
—
—
PORTA Data Direction Register
—
—
—
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS41124D-page 32
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 5-3:
BLOCK DIAGRAM OF RB
PINS
VDD
RBPU(1)
Data
Bus
WR
Port
This interrupt-on-mismatch feature, together with software configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG).
RB0/INT is discussed in detail in Section 13.5.1.
VDD
weak
P pull-up
FIGURE 5-4:
BLOCK DIAGRAM OF
RB PINS
Data Latch
D
Q
I/O
pin
CK
TRIS Latch
D
Q
WR
TRIS
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
VDD
RBPU(1)
Data Bus
TTL
Input
Buffer
CK
WR Port
VDD
weak
P pull-up
Data Latch
D
Q
I/O
pin
CK
TRIS Latch
D
RD TRIS
WR TRIS
Q
RD Port
D
Q
TTL
Input
Buffer
CK
EN
RD TRIS
RB0/INT
Latch
Q
Schmitt Trigger
Buffer
RD Port
Set RBIF
ST
Buffer
D
EN
RD Port
Q1
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG).
From other
RB pins
Four of PORTB’s pins, RB, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB pin configured as an output is excluded from the interrupt-onchange comparison). The input pins (of RB) are
compared with the value latched on the last read of
PORTB. The “mismatch” outputs of RB are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON).
Q
D
RD Port
EN
Q3
RB in serial programming mode
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 33
PIC16C745/765
TABLE 5-3:
PORTB FUNCTIONS
Function
Input
Type
Output
Type
RB0
TTL
CMOS
INT
ST
—
RB1
RB1
TTL
CMOS
Bi-directional I/O
RB2
RB2
TTL
CMOS
Bi-directional I/O
RB3
RB3
TTL
CMOS
Bi-directional I/O
RB4
RB4
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change
RB5
RB5
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change
RB6
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change
Name
RB0/INT
RB6/ICSPC
RB7/ICSPD
Legend:
Bi-directional I/O
Interrupt
ICSPC
ST
RB7
TTL
CMOS
Bi-directional I/O with Interrupt-on-Change
ICSPD
ST
OD = open drain, ST = Schmitt Trigger
CMOS
In-Circuit Serial Programming Data I/O
TABLE 5-4:
Address
Description
In-Circuit Serial Programming Clock input
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
1111 1111
1111 1111
06h, 106h
PORTB
86h, 186h
TRISB
PORTB Data Direction Register
81h, 181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS41124D-page 34
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
5.3
PORTC and TRISC Registers
FIGURE 5-5:
PORTC is a 5-bit bi-directional port. Each pin is individually configureable as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
PORTC BLOCK DIAGRAM
Port/Peripheral Select(1)
Peripheral Data Out
Data Bus
WR
Port
VDD
0
D
Q
1
CK
Q
Data Latch
D
WR
TRIS
CK
VDD
P
I/O
pin
Q
Q
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(2)
RD
Port
Peripheral Input
Q
D
EN
Note 1: Port/Peripheral select signal selects between port
data and peripheral output.
2: Peripheral OE (output enable) is only activated if
peripheral select is active.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 35
PIC16C745/765
TABLE 5-5:
PORTC FUNCTIONS
Name
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
Function
Input
Type
Output
Type
RC0
ST
CMOS
T1OSO
—
Xtal
T1CKI
ST
—
T1 Clock Input
RC1
ST
CMOS
Xtal
—
T1 Oscillator Input
CCP2
—
—
Capture In/Compare Out/PWM Out 2
Bi-directional I/O
RC2
ST
CMOS
CCP1
—
—
RC6
ST
CMOS
Bi-directional I/O
TX
—
CMOS
USART Async Transmit
CK
ST
CMOS
USART Master Out/Slave In Clock
RC7
ST
CMOS
Bi-directional I/O
RX
ST
—
RC7/RX/DT
DT
ST
OD = open drain, ST = Schmitt Trigger
TABLE 5-6:
Bi-directional I/O
T1 Oscillator Output
T1OSI
RC6/TX/CK
Legend:
Description
CMOS
Bi-directional I/O
Capture In/Compare Out/PWM Out 1
USART Async Receive
USART Data I/O
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
07h
PORTC
RC7
RC6
—
—
—
RC2
RC1
RC0
xx-- -xxx
uu-- -uuu
87h
TRISC
TRISC7
TRISC6
—
—
—
TRISC2 TRISC1 TRISC0 11-- -111
11-- -111
Address
Legend: x = unknown, u = unchanged.
DS41124D-page 36
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
5.4
PORTD and TRISD Registers
FIGURE 5-6:
PORTD BLOCK DIAGRAM
VDD
Note:
The PIC16C745 does not provide PORTD.
The PORTD and TRISD registers are
reserved. Always maintain these bits clear.
Data
Bus
WR
Port
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or
output.
D
Q
I/O pin
CK
Data Latch
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE). In this mode, the input buffers
are TTL.
D
WR
TRIS
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRIS
Q
D
ENEN
RD Port
TABLE 5-7:
PORTD FUNCTIONS
Name
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Legend:
Note 1:
Function
Input
Type
Output
Type
RD0
TTL
CMOS
PSP0
TTL
—
RD1
TTL
CMOS
PSP1
TTL
—
RD2
TTL
CMOS
PSP2
TTL
—
RD3
TTL
CMOS
PSP3
TTL
—
RD4
TTL
CMOS
PSP4
TTL
—
RD5
TTL
CMOS
PSP5
TTL
—
RD6
TTL
CMOS
PSP6
TTL
—
RD7
TTL
CMOS
PSP7
TTL
OD = open drain, ST = Schmitt Trigger
—
Description
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
Bi-directional I/O(1)
Parallel Slave Port Data Input(1)
PIC16C765 only.
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h
PORTD(1)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
88h
TRISD(1)
1111 1111
1111 1111
Address
PORTD Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
Note 1:
PIC16C765 only.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 37
PIC16C745/765
5.5
PORTE and TRISE Registers
FIGURE 5-7:
PORTE BLOCK DIAGRAM
VDD
Note 1: The PIC16C745 does not provide
PORTE. The PORTE and TRISE registers
are reserved. Always maintain these bits
clear.
Data
Bus
WR
Port
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configured as
inputs or outputs. These pins have Schmitt Trigger
input buffers.
D
Q
I/O pin
CK
Data Latch
D
WR
TRIS
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE) is set. In
this mode, the user must make sure that the
TRISE bits are set (pins are configured as digital
inputs) and that register ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL.
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRIS
Register 5-1 shows the TRISE register, which also controls the parallel slave port operation.
Q
D
ENEN
PORTE pins may be multiplexed with analog inputs
(PIC16C765 only). The operation of these pins is
selected by control bits in the ADCON1 register. When
selected as an analog input, these pins will read as '0's.
RD Port
To A/D Converter
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
TRISE bits are used to control the parallel slave port.
Note:
On a Power-on Reset, these pins are configured as analog inputs.
TABLE 5-9:
PORTE(1) FUNCTIONS
Function
Input
Type
Output
Type
RE0
ST
CMOS
RD
TTL
—
Parallel Slave Port Control Input(1)
AN5
AN
—
A/D Input(1)
RE1
ST
CMOS
WR
TTL
—
Parallel Slave Port Control Input(1)
AN6
AN
—
A/D Input(1)
RE2
ST
CMOS
CS
TTL
—
Parallel Slave Port Data Input(1)
AN7
AN
OD = open drain, ST = Schmitt Trigger
—
A/D Input(1)
Name
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
Legend:
Note 1:
Description
Bi-directional I/O(1)
Bi-directional I/O(1)
Bi-directional I/O(1)
PIC16C765 only.
DS41124D-page 38
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
REGISTER 5-1: PORTE DATA DIRECTION CONTROL REGISTER(1) (TRISE: 89h)
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
—
TRISE2
TRISE1
TRISE0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7 :
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2:
TRISE2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1:
TRISE1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0:
TRISE0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Note 1:
PIC16C765 only.
TABLE 5-10:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
09h
PORTE(1)
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
89h
TRISE(1)
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
0000 -111
0000 -111
9Fh
ADCON1
—
—
—
—
—
PCFG2
---- -000
---- -000
Address
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1:
PIC16C765 only.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 39
PIC16C745/765
5.6
Note:
Parallel Slave Port (PSP)
The PIC16C745 does not provide a parallel slave port. The PORTD, PORTE, TRISD
and TRISE registers are reserved. Always
maintain these bits clear.
PORTD operates as an 8-bit wide Parallel Slave Port
(PSP), or microprocessor port when control bit PSPMODE (TRISE) is set. In slave mode, it is asynchronously readable and writable by the external world
through RD control input pin RE0/RD/AN5 and WR
control input pin RE1/WR/AN6.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input, RE1/
WR/AN6 to be the WR input and RE2/CS/AN7 to be
the CS (chip select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE) must be configured as inputs (set) and
the A/D port configuration bits PCFG
(ADCON1) must be set, which will configure pins
RE as digital I/O.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1).
FIGURE 5-8:
PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
VDD
Data Bus
D
WR
Port
Q
RDx
pin
CK
TTL
Q
RD
Port
D
ENEN
One bit of PORTD
There are actually two 8-bit latches; one for data-out
(from the PIC® microcontroller) and one for data input.
The user writes 8-bit data to PORTD data latch and
reads data from the port pin latch (note that they have
the same address). In this mode, the TRISD register is
ignored, since the microprocessor is controlling the
direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full (IBF) status flag bit (TRISE) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete (Figure 5-9). The interrupt flag bit
PSPIF (PIR1) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The Input Buffer Overflow (IBOV) status
flag bit (TRISE) is set if a second write to the PSP
is attempted when the previous byte has not been read
out of the buffer.
Set interrupt flag
PSPIF (PIR1)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE) is cleared immediately (Figure 5-10) indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
DS41124D-page 40
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
FIGURE 5-9:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 5-11:
Address
08h
09h
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD(2) Port data latch when written: Port pins when read
PORTE
(2)
(2)
—
—
—
—
—
RE2
RE1
RE0
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
---- -xxx
---- -uuu
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
0000 -111
0000 -111
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
---- -000
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745. Always maintain these bits clear.
2: PIC16C765 only.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 41
PIC16C745/765
NOTES:
DS41124D-page 42
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
6.0
TIMER0 MODULE
Counter mode is selected by setting bit T0CS
(OPTION_REG). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
The Timer0 module timer/counter has the following features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt-on-overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The prescaler is not readable or writable. Section 6.3 details the
operation of the prescaler.
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
Additional information on the Timer0 module is available in the PIC Mid-Range MCU Family Reference
Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON). The interrupt can be masked by
clearing bit T0IE (INTCON). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 6-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FINT
Data Bus
0
RA4/T0CKI
Pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
TOCS
Set flag bit T0IF
on Overflow
PSA
PRESCALER
0
Watchdog
Timer
1
M
U
X
8-bit Prescaler
8
8 - to - 1MUX
PS
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS are (OPTION_REG).
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 43
PIC16C745/765
6.2
Using Timer0 with an External Clock
The PSA and PS bits (OPTION_REG) determine the prescaler assignment and prescale ratio.
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.3
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the watchdog timer. The prescaler is not
readable or writable.
Note:
Prescaler
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
module means that there is no prescaler for the watchdog timer, and vice-versa. This prescaler is not readable
or writable (see Figure 6-1).
EXAMPLE 6-1:
Address
To avoid an unintended device RESET, the following
instruction sequence (shown in Example 6-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
CHANGING PRESCALER (TIMER0WDT)
Lines 2 and 3 do
NOT have to be
included if the final
desired prescale
value is other than
1:1. If 1:1 is the final
desired value, then a
temporary prescale
value is set in lines 2
and 3 and the final
prescale value will
be set in lines 10
and 11.
TABLE 6-1:
Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
1)
BSF
STATUS, RP0
;Bank1
2)
MOVLW
b'xx0x0xxx'
;Select clock source and prescale value of
3)
MOVWF
OPTION_REG
;other than 1:1
4)
BCF
STATUS, RP0
;Bank0
5)
CLRF
TMR0
;Clear TMR0 and prescaler
6)
BSF
STATUS, RP1
;Bank1
7)
MOVLW
b'xxxx1xxx'
;Select WDT, do not change prescale value
8)
MOVWF
OPTION_REG
;
9)
CLRWDT
;Clears WDT and prescaler
10) MOVLW
b'xxxx1xxx'
;Select new prescale value and WDT
11) MOVWF
OPTION_REG
;
12) BCF
STATUS, RP0
;Bank0
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
01h,101h
TMR0
0Bh,8Bh,
10Bh,18Bh
INTCON
81h,181h
OPTION_REG RBPU INTEDG
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
GIE
PEIE
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS41124D-page 44
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
7.0
TIMER1 MODULE
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 9.0). Register 7-1 shows the Timer1
control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC value is
ignored.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual
(DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON).
REGISTER 7-1: TIMER1 CONTROL REGISTER (T1CON: 10h)
U-0
—
bit7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
bit 2:
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (1) or RC1/T1OSI/CCP2
0 = Internal clock (FINT)
bit 0:
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: On the rising edge after the first falling edge.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 45
PIC16C745/765
7.1
Timer1 Operation in Timer Mode
7.2
Timer mode is selected by clearing the TMR1CS
(T1CON) bit. In this mode, the input clock to the
timer is FINT. The synchronize control bit T1SYNC
(T1CON) has no effect since the internal clock is
always in sync.
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The prescaler however will continue to increment.
FIGURE 7-1:
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
0
TMR1
TMR1H
Synchronized
clock input
TMR1L
1
TMR1ON
on/off
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
T1SYNC
1
T1OSCEN FINT
Enable
Internal
Oscillator(1) Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS
TMR1CS
SLEEP input
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS41124D-page 46
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
7.3
Timer1 Operation in Asynchronous
Counter Mode
If control bit T1SYNC (T1CON) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.1).
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
7.3.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. Examples
12-2 and 12-3 in the PIC Mid-Range MCU Family Reference Manual (DS33023) show how to read and write
Timer1 when it is running in asynchronous mode.
7.4
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A 20 PPM
100 kHz
Epson C-2 100.00 KC-P
20 PPM
200 kHz
STD XTL 200.000 kHz
20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
7.5
Resetting Timer1 using a CCP Trigger
Output
If the CCP1 or CCP2 module is configured in compare
mode to generate a “special event trigger”
(CCP1M = 1011), this signal will reset Timer1.
Note:
The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
RESET operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for
Timer1.
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other RESET except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 47
PIC16C745/765
TABLE 7-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
0Bh,8Bh, INTCON
10Bh,
18Bh
Value on:
POR,
BOR
Value on
all other
resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
8Ch
PIE1
(1)
PSPIE
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
0Ch
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124D-page 48
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
8.0
TIMER2 MODULE
8.1
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any
device RESET.
The input clock (FINT/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS
(T2CON).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
FIGURE 8-1:
Sets flag
bit TMR2IF
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1)).
TIMER2 BLOCK DIAGRAM
TMR2
output
RESET
Postscaler
1:1 to 1:16
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON) to minimize power consumption.
EQ
TMR2 reg
Comparator
Prescaler
1:1, 1:4, 1:16
FINT
2
T2CKPS
4
Register 8-1 shows the Timer2 control register.
PR2 reg
T2OUTPS
Additional information on timer modules is available in
the PIC Mid-Range MCU Family Reference Manual
(DS33023).
REGISTER 8-1: TIMER2 CONTROL REGISTER (T2CON: 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
R/W-0
R/W-0
T2CKPS1 T2CKPS0
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6-3:
TOUTPS: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0:
T2CKPS: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
1999-2013 Microchip Technology Inc.
Preliminary
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS41124D-page 49
PIC16C745/765
TABLE 8-1:
Address
Name
0Bh,8Bh,
INTCON
10Bh,18Bh
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
TMR1IE
0000 0000 0000 0000
PSPIF(1)
8Ch
PIE1
(1)
11h
TMR2
12h
T2CON
92h
PR2
Legend:
Note 1:
Value on
all other
resets
Bit 6
PIR1
0Ch
Value on:
POR,
BOR
Bit 7
PSPIE
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
0000 0000 0000 0000
Timer2 module’s register
—
0000 000x 0000 000u
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124D-page 50
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
9.0
CAPTURE/COMPARE/PWM
MODULES
CCP2 Module:
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit capture register
• 16-bit compare register
• PWM master/slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 9-1 and Table 9-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
Capture/Compare/PWM Register1 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Additional information on CCP modules is available in
the PIC Mid-Range MCU Family Reference Manual
(DS33023) and in “Using the CCP Modules” (AN594).
TABLE 9-1:
CCP1 Module:
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
TABLE 9-2:
CCPx Mode
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
INTERACTION OF TWO CCP MODULES
CCPy Mode
Interaction
Capture
Capture
Same TMR1 time-base.
Capture
Compare
The compare should be configured for the special event trigger, which clears TMR1.
Compare
Compare
The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
None.
PWM
Compare
None.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 51
PIC16C745/765
REGISTER 9-1: CAPTURE/COMPARE/PWM CONTROL REGISTER
(CCP1CON: 17H, CCP2CON: 1Dh)
U
—
bit7
U
—
R/W-0
DCnB1
R/W-0
R/W-0
DCnB0 CCPnM3
R/W-0
CCPnM2
R/W-0
R/W-0
CCPnM1 CCPnM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: DCnB: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRnL.
bit 3-0: CCPnM: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPn module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPnIF bit is set)
1001 = Compare mode, clear output on match (CCPnIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPnIF bit is set, CCPn pin is unaffected)
1011 = Compare mode, trigger special event (CCPnIF bit is set; CCPn resets TMR1or TMR3)
11xx = PWM mode
DS41124D-page 52
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
9.1
9.1.2
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC bit.
Note:
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a capture condition.
FIGURE 9-1:
CAPTURE MODE OPERATION
BLOCK DIAGRAM
Prescaler
1, 4, 16
Set flag bit CCP1IF
(PIR1)
RC2/CCP1
Pin
CCPR1H
and
edge detect
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
9.1.3
An event is selected by control bits CCP1M
(CCP1CON). When a capture is made, the interrupt request flag bit CCP1IF (PIR1) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
SOFTWARE INTERRUPT
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
9.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M. Whenever the CCP module is turned
off, or the CCP module is not in capture mode, the prescaler counter is cleared. Any RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 9-1:
CCPR1L
Capture
Enable
TMR1H
TIMER1 MODE SELECTION
TMR1L
CLRF
MOVLW
MOVWF
CCP1CON
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new precscaler
; move value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
Q’s
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 53
PIC16C745/765
9.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Note:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M (CCP1CON). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
The special event trigger output of CCP2 starts an A/D
conversion (if the A/D module is on) and resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
COMPARE MODE OPERATION
BLOCK DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1),
and set bit GO/DONE (ADCON0).
9.3
The special event trigger from the
CCP1and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1).
PWM Mode (PWM)
In pulse width modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC bit must be cleared to make the CCP1 pin
an output.
Note:
Special Event Trigger
Set flag bit CCP1IF
(PIR1)
CCPR1H CCPR1L
Q
S
Output
Logic
match
RC2/CCP1
R
Pin
TRISC
Output Enable CCP1CON
Mode Select
9.2.1
Figure 9-3 shows a simplified block diagram of the CCP
module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
Comparator
TMR1H
TMR1L
FIGURE 9-3:
9.2.2
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
CCPR1H (Slave)
R
Comparator
TIMER1 MODE SELECTION
Q
RC2/CCP1
TMR2
(Note 1)
S
TRISC
Comparator
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
9.2.4
CCP1CON
CCPR1L
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC bit.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PR2
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time base.
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
A PWM output (Figure 9-4) has a time base (period) and
a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
The special event trigger output of CCP1 resets the TMR1
register pair. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
DS41124D-page 54
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
FIGURE 9-4:
When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
PWM OUTPUT
Period
Maximum PWM resolution (bits) for a given PWM
frequency:
CCP1(2)
Duty Cycle
(1)
Resolution
(1)
Note:
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
9.3.3
9.3.1
PWM PERIOD
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
(
log(2)
)
bits
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
PWM frequency is defined as 1 / [PWM period].
=
FINT
log FPWM
4.
5.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
9.3.2
The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different frequency than the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 55
PIC16C745/765
TABLE 9-3:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
Value on:
POR,
BOR
Value on
all other
resets
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
1Bh
CCPR2L
Capture/Compare/PWM register2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
—
—
—
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
DCnB1
DCnB1
DCnB0
DCnB0
CCP1M3
CCP2M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16C745; always maintain these bits clear.
TABLE 9-4:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PSPIF(1)
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
0Ch
PIR1
Value on:
POR,
BOR
Value on
all other
resets
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 module’s register
0000 0000 0000 0000
92h
PR2
Timer2 module’s period register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
—
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
1Bh
CCPR2L
Capture/Compare/PWM register2 (LSB)
1Ch
CCPR2H
Capture/Compare/PWM register2 (MSB)
1Dh
CCP2CON
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
—
—
DCnB1
DCnB1
DCnB0
DCnB0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124D-page 56
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
10.0
UNIVERSAL SERIAL BUS
10.1.2
10.1
Overview
Information communicated on the bus is grouped in a
format called Frames. Each Frame is 1 ms in duration
and is composed of multiple transfers. Each transfer
type can be repeated more than once within a frame.
This section introduces a minimum amount of information on USB. If you already have basic knowledge of
USB, you can safely skip this section. If terms like
Enumeration, Endpoint, IN/OUT Transactions, Transfers and Low Speed/Full Speed are foreign to you,
read on.
USB was developed to address the increased connectivity needs of PC’s in the PC 2000 specification.
There was a base requirement to increase the bandwidth and number of devices, which could be
attached. Also desired were the ability for hot swapping, user friendly operation, robust communications
and low cost. The primary promoters of USB are Intel,
Compaq, Microsoft and NEC.
USB is implemented as a Tiered Star topology, with
the host at the top, hubs in the middle, spreading out
to the individual devices at the end. USB is limited to
127 devices on the bus, and the tree cannot be more
than 6 levels deep.
USB is a host centric architecture. The host is always
the master. Devices are not allowed to “speak” unless
“spoken to” by the host.
Transfers take place at one of two speeds. Full Speed
is 12 Mb/s and Low Speed is 1.5 Mb/s. Full Speed
covers the middle ground of data intensive audio and
compressed video applications, while low speed supports less data intensive applications.
10.1.1
TRANSFER PROTOCOLS
Full speed supports four transfer types: Isochronous,
Bulk, Interrupt and Control. Low speed supports two
transfer types: Interrupt and Control. The four transfer
types are described below.
- Isochronous Transfers, meaning equal
time, guarantee a fixed amount of data at a
fixed rate. This mode trades off guaranteed
data accuracy for guaranteed timeliness.
Data validity is not checked because there
isn’t time to re-send bad packets anyway and
the consequences of bad data are not
catastrophic.
- Bulk Transfers are the converse of Isochronous. Data accuracy is guaranteed, but
timeliness is not.
- Interrupt Transfers are designed to communicate with devices which have a moderate
data rate requirement. Human Interface
Devices like keyboards are but one example.
For Interrupt Transfers, the key is the desire
to transfer data at regular intervals. USB periodically polls these devices at a fixed rate to
see if there is data to transfer.
- Control Transfers are used for configuration
purposes.
1999-2013 Microchip Technology Inc.
10.1.3
FRAMES
POWER
Power has always been a concern with any device.
With USB, 5 volt power is now available directly from
the bus. Devices may be self-powered or buspowered. Self-powered devices will draw power from
a wall adapter or power brick. On the other hand, buspowered devices will draw power directly from the
USB bus itself. There are limits to how much power
can be drawn from the USB bus. Power is expressed
in terms of “unit loads” (100 mA). All devices, including Hubs, are guaranteed at least 1 unit load (low
power), but must negotiate with the host for up to 5
unit loads (high power). If the host determines that the
bus as currently configured cannot support a device’s
request for more unit loads, the device will be denied
the extra unit loads and must remain in a low power
configuration.
10.1.4
END POINTS
At the lowest level, each device controls one or more
endpoints. An endpoint can be thought of as a virtual
port. Endpoints are used to communicate with a
device’s functions. Each endpoint is a source or sink of
data. Endpoints have both an In and Out direction
associated with it. Each device must implement endpoint 0 to support Control Transfers for configuration.
There are a maximum of 15 endpoints available for
use by each full speed device and 6 endpoints for
each slow speed device. Remember that the bus is
host centric, so In/Out is with respect to the host and
not the device.
10.1.5
ENUMERATION
Prior to communicating on the bus, the host must see
that a new device has been connected and then go
through an “enumeration process”. This process
allows the host to ask the device to introduce itself,
and negotiate performance parameters, such as
power consumption, transfer protocol and polling rate.
The enumeration process is initiated by the host when
it detects that a new device has attached itself to the
bus. This takes place completely in the background
from the application process.
10.1.6
DESCRIPTORS
The USB specification requires a number of different
descriptors to provide information necessary to identify
a device, specify its endpoints, and each endpoint’s
function. The five general categories of descriptors are
Device, Configuration, Interface, End Point and String.
Preliminary
DS41124D-page 57
PIC16C745/765
The Device descriptor provides general information
such as manufacturer, product number, serial number,
USB device class the product falls under, and the
number of different configurations supported. There
can only be one Device descriptor for any given application.
10.2
The Configuration descriptor provides information on
the power requirements of the device and how many
different interfaces are supported when in this configuration. There may be more than one configuration for
each device, (i.e., a high power device may also support a low power configuration).
The following terms are used in the description of the
USB module:
The Interface descriptor details the number of endpoints used in this interface, as well as the class driver
to use should the device support functions in more
than just one device class. There can only be one
Interface descriptor for each configuration.
The Endpoint descriptor details the actual registers for
a given function. Information is stored about the transfer types supported, direction (In/Out), bandwidth
requirements and polling interval. There may be more
than one endpoint in a device, and endpoints may be
shared between different interfaces.
Many of the four descriptors listed above will reference
or index different String descriptors. String descriptors
are used to provide vendor specific or application specific information. They may be optional and are
encoded in “Unicode” format.
10.1.7
DEVICE CLASSES/CLASS DRIVERS
Operating systems provide drivers which group functions together by common device types called classes.
Examples of device classes include, but are not limited
to, storage, audio, communications and HID (Human
Interface). Class drivers for a given application are referenced in both the Device descriptor and Interface
descriptor. Most applications can find a Class Driver
which supports the majority of their function/command
needs. Vendors who have a requirement for specific
commands which are not supported by any of the
standard class drivers may provide a vendor specific
“.inf” file or driver for extra support.
10.1.8
SUMMARY
While a complete USB overview is beyond the scope
of this document, a few key concepts must be noted.
Low speed communication is designed for devices,
which in the past, used an interrupt to communicate
with the host. In the USB scheme, devices do not
directly interrupt the processor when they have data.
Instead the host periodically polls each device to see if
they have any data. This polling rate is negotiated
between the device and host, giving the system a
guaranteed latency.
Introduction
The PIC16C745/765 USB peripheral module supports
Low Speed control and interrupt (IN and OUT) transfers only. The implementation supports 3 endpoint
numbers (0, 1, 2) for a total of 6 endpoints.
• MCU - The core processor and corresponding
firmware
• SIE - Serial Interface Engine: That part of the
USB that performs functions such as CRC generation and clocking of the D+ and D- signals.
• USB - The USB module including SIE and
registers
• Bit Stuffing - forces insertion of a transition on D+
and D- to maintain clock synchronization
• BD - Buffer Descriptor
• BDT - Buffer Descriptor Table
• EP - Endpoint (combination of endpoint number
and direction)
• IN - Packet transfer into the host
• OUT - Packet transfer out of the host
10.3
USB Transaction
When the USB transmits or receives data the SIE will
first check that the corresponding endpoint and direction Buffer Description UOWN bit equals 1. The USB
will move the data to or from the corresponding buffer.
When the TOKEN is complete, the USB will update the
BD status and change the UOWN bit to 0. The USTAT
register is updated and the TOK_DNE interrupt is set.
When the MCU processes the TOK_DNE interrupt it
reads the USTAT register, which gives the MCU the
information it needs to process the endpoint. At this
point the MCU will process the data and set the corresponding UOWN bit. Figure 10-1 shows a time line of
how a typical USB token would be processed.
10.4
Firmware Support
Microchip provides a comprehensive support library of
standard chapter 9 USB commands. These libraries
provide a software layer to insulate the application
software from having to handle the complexities of the
USB protocol. A simple Put/Get interface is implemented to allow most of the USB processing to take
place in the background within the USB interrupt service routine. Applications are encouraged to use the
provided libraries during both enumeration and configured operation.
For more details on USB, see the USB V1.1 spec,
available from the USB website at www.usb.org.
DS41124D-page 58
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
FIGURE 10-1: USB TOKENS
USB RESET
USB_RST
Interrupt Generated
SETUP TOKEN
DATA
ACK
TOK_DNE
Interrupt Generated
IN TOKEN
DATA
ACK
TOK_DNE
Interrupt Generated
OUT TOKEN
DATA
ACK
TOK_DNE
Interrupt Generated
= Host
= Device
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 59
PIC16C745/765
10.5
USB Register Map
10.5.1.1
The USB Control Registers, Buffer Descriptors and
Buffers are located in Bank 3.
10.5.1
CONTROL AND STATUS REGISTERS
The USB module is controlled by 7 registers, plus
those that control each endpoint and endpoint/
direction buffer.
USB Interrupt Register (UIR)
The USB Interrupt Status Register (UIR) contains flag
bits for each of the interrupt sources within the USB.
Each of these bits are qualified with their respective
interrupt enable bits (see the Interrupt Enable Register
UIE). All bits of the register are logically OR'ed
together to form a single interrupt source for the microprocessor interrupt found in PIR1 (USBIF). Once an
interrupt bit has been set, it must be cleared by writing
a zero.
REGISTER 10-1: USB INTERRUPT FLAGS REGISTER (UIR: 190h)
U-0
—
bit7
U-0
—
R/C-0
STALL
R/C-0
R/C-0
R/C-0
UIDLE TOK_DNE ACTIVITY
R/C-0
UERR
R/C-0
USB_RST
bit0
R = Readable bit
C = Clearable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
STALL: A STALL handshake was sent by the SIE
bit 4:
UIDLE: This bit is set if the USB has detected a constant idle on the USB bus signals for 3 ms. The idle
timer is reset by activity on the USB bus. Once a IDLE condition has been detected, the user may wish
to place the USB module in SUSPEND by setting the SUSPEND bit in the UCTRL register.
bit 3:
TOK_DNE: This bit is set when the current token being processed is complete. The microprocessor
should immediately read the USTAT register to determine the Endpoint number and direction used for
this token. Clearing this bit causes the USTAT register to be cleared or the USTAT holding register to be
loaded into the STAT register if another token has been processed.
bit 2:
ACTIVITY: Activity on the D+/D- lines will cause the SIE to set this bit. Typically this bit is unmasked
following detection of SLEEP. Users must enable the activity interrupt in the USB Interrupt Register
(UIE: 191h) prior to entering suspend.
bit 1:
UERR: This bit is set when any of the error conditions within the ERR_STAT register has occurred. The
MCU must then read the ERR_STAT register to determine the source of the error.
bit 0:
USB_RST: This bit is set when the USB has decoded a valid USB Reset. This will inform the MCU to
write 00h into the address register and enable endpoint 0. USB_RST is set once a USB Reset has been
detected for 2.5 microseconds. It will not be asserted again until the USB Reset condition has been
removed, and then reasserted.
Note 1: Bits can only be modified when UCTRL.SUSPND = 0.
DS41124D-page 60
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
10.5.1.2
USB Interrupt Enable Register (UIE)
The USB Interrupt Enable Register (UIE) contains
enable bits for each of the interrupt sources within the
USB. Setting any of these bits will enable the respective interrupt source in the UIR register. The values in
the UIE register only affect the propagation of an interrupt condition to the PIE1 register. Interrupt conditions
can still be polled and serviced.
REGISTER 10-2: USB INTERRUPT ENABLE REGISTER (UIE: 191h)
U-0
—
bit7
U-0
—
R/W-0
STALL
R/W-0
UIDLE
R/W-0
R/W-0
TOK_DNE ACTIVITY
R/W-0
UERR
R/W-0
USB_RST
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
STALL: Set to enable STALL interrupts
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4:
UIDLE: Set to enable IDLE interrupts
1 = IDLE interrupt enabled
0 = IDLE interrupt disabled
bit 3:
TOK_DNE: Set to enable TOK_DNE interrupts
1 = TOK_DNE interrupt enabled
0 = TOK_DNE interrupt disabled
bit 2(1): ACTIVITY: Set to enable ACTIVITY interrupts
1 = ACTIVITY interrupt enabled
0 = ACTIVITY interrupt disabled
bit 1:
UERR: Set to enable ERROR interrupts
1 = ERROR interrupt enabled
0 = ERROR interrupt disabled
bit 0:
USB_RST: Set to enable USB_RST interrupts
1 = USB_RST interrupt enabled
0 = USB_RST interrupt disabled
Note 1: This interrupt is the only interrupt active during UCTRL.SUSPEND = 1.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 61
PIC16C745/765
10.5.1.3
USB Error Interrupt Status Register (UEIR)
The USB Error Interrupt Status Register (UEIR) contains bits for each of the error sources within the USB.
Each of these bits are enabled by their respective
error enable bits (UEIE). The result is OR'ed together
and sent to the ERROR bit of the UIR register. Once
an interrupt bit has been set it must be cleared by writing a zero to the respective interrupt bit. Each bit is set
as soon as the error condition is detected. Thus, the
interrupt will typically not correspond with the end of a
token being processed.
REGISTER 10-3: USB ERROR INTERRUPT FLAGS STATUS REGISTER (UEIR: 192h)
R/C-0
R/C-0
R/C-0
R/C-0
BTS_ERR OWN_ERR WRT_ERR BTO_ERR
bit7
R/C-0
DFN8
R/C-0
CRC16
R/C-0
CRC5
R/C-0
PID_ERR
bit0
R = Readable bit
C = Clearable bit
U = Unimplemented
bit, read as ‘0’
-n = Value at POR
reset
bit 7:
BTS_ERR: A bit stuff error has been detected
bit 6:
OWN_ERR: This bit is set if the USB is processing a token and the OWN bit within the BDT is equal to 0
(signifying that the microprocessor owns the BDT and the SIE does not have access to the BDT). If processing an IN TOKEN this would cause a transmit data underflow condition. Processing an OUT or SETUP
TOKEN would cause a receive data overflow condition.
bit 5:
WRT_ERR: Write Error
A write by the MCU to the USB Buffer Descriptor Table or Buffer area was unsuccessful. This error occurs
when the MCU attempts to write to the same location that is currently being written to by the SIE.
bit 4:
BTO_ERR: This bit is set if a bus turnaround time-out error has occurred. This USB uses a bus turnaround
timer to keep track of the amount of time elapsed between the token and data phases of a SETUP or OUT
TOKEN or the data and handshake phases of a IN TOKEN. If more than 17-bit times are counted from the
previous EOP before a transition from IDLE, a bus turnaround time-out error will occur.
bit 3:
DFN8: The data field received was not 8 bits. The USB Specification 1.1 specifies that data field must be an
integral number of bytes. If the data field was not an integral number of bytes this bit will be set.
bit 2:
CRC16: The CRC16 failed
bit 1:
CRC5: This interrupt will detect CRC5 error in the token packets generated by the host. If set the token
packet was rejected due to a CRC5 error.
bit 0:
PID_ERR: The PID check field failed
Note 1: Bits can only be modified when UCTRL.SUSPND = 0.
DS41124D-page 62
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
10.5.1.4
Error Interrupt Enable Register (UEIE)
The USB Error Interrupt Enable Register (UEIE) contains enable bits for each of the error interrupt sources
within the USB. Setting any of these bits will enable
the respective error interrupt source in the UEIR register.
REGISTER 10-4: USB ERROR INTERRUPT ENABLE REGISTER (UEIE: 193h)
R/W-0
R/W-0
R/W-0
R/W-0
BTS_ERR OWN_ERR WRT_ERR BTO_ERR
R/W-0
R/W-0
R/W-0
R/W-0
DFN8
CRC16
CRC5
PID_ERR
bit7
bit0
bit 7:
BTS_ERR: Set this bit to enable BTS_ERR interrupts
1 = BTS_ERR interrupt enabled
0 = BTS_ERR interrupt disabled
bit 6:
OWN_ERR: Set this bit to enable OWN_ERR interrupts
1 = OWN_ERR interrupt enabled
0 = OWN_ERR interrupt disabled
bit 5:
WRT_ERR: Set this bit to enable WRT_ERR interrupts
1 = WRT_ERR interrupt enabled
0 = WRT_ERR interrupt disabled
bit 4:
BTO_ERR: Set this bit to enable BTO_ERR interrupts
1 = BTO_ERR interrupt enabled
0 = BTO_ERR interrupt disabled
bit 3:
DFN8: Set this bit to enable DFN8 interrupts
1 = DFN8 interrupt enabled
0 = DFN8 interrupt disabled
bit 2:
CRC16: Set this bit to enable CRC16 interrupts
1 = CRC16 interrupt enabled
0 = CRC16 interrupt disabled
bit 1:
CRC5: Set this bit to enable CRC5 interrupts
1 = CRC5 interrupt enabled
0 = CRC5 interrupt disabled
bit 0:
PID_ERR: Set this bit to enable PID_ERR interrupts
1 = PID_ERR interrupt enabled
0 = PID_ERR interrupt disabled
1999-2013 Microchip Technology Inc.
Preliminary
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
DS41124D-page 63
PIC16C745/765
10.5.1.5
Status Register (USTAT)
The USB Status Register reports the transaction status within the USB. When the MCU recognizes a
TOK_DNE interrupt, this register should be read to
determine the status of the previous endpoint communication. The data in the status register is valid when
the TOK_DNE interrupt bit is asserted.
The USTAT register is actually a read window into a
status FIFO maintained by the USB. When the USB
uses a BD, it updates the status register. If another
USB transaction is performed before the TOK_DNE
interrupt is serviced the USB will store the status of the
next transaction in the STAT FIFO. Thus, the STAT
register is actually a four byte FIFO which allows the
MCU to process one transaction while the SIE is processing the next. Clearing the TOK_DNE bit in the
INT_STAT register causes the SIE to update the STAT
register with the contents of the next STAT value. If the
data in the STAT holding register is valid, the SIE will
immediately reassert the TOK_DNE interrupt.
REGISTER 10-5: USB STATUS REGISTER (USTAT: 194h)
U-0
—
bit7
U-0
—
U-0
—
R-X
R-X
R-X
ENDP1
ENDP0
IN
U-0
—
U-0
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-5: Unimplemented: Read as ’0’
bit 4-3: ENDP: These bits encode the endpoint address that received or transmitted the previous token.
This allows the microprocessor to determine which BDT entry was updated by the last USB transaction.
bit 2:
IN: This bit indicates the direction of the last BD that was updated
1 = The last transaction was an IN TOKEN
0 = The last transaction was an OUT or SETUP TOKEN
bit 1-0: Unimplemented: Read as ’0’
DS41124D-page 64
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
10.5.1.6
USB Control Register (UCTRL)
The control register provides various control and configuration information for the USB.
REGISTER 10-6: USB CONTROL REGISTER (UCTRL: 195h)
U-0
—
bit7
U-0
—
R-X
R/C-0
SE0
PKT_DIS
R/W-0
R/W-0
R/W-0
DEV_ATT RESUME SUSPND
U-0
—
bit0
R = Readable bit
W = Writable bit
C = Clearable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-6: Unimplemented: Read as ’0’
bit 5:
SE0: Live Single Ended Zero
This status bit indicates that the D+ and D- lines are both pulled to low.
1 = Single ended zero being received
0 = Single ended zero not being received
bit 4
PKT_DIS: The PKT_DIS bit informs the MCU that the SIE has disabled packet transmission and reception. Clearing this bit allows the SIE to continue token processing. This bit is set by the SIE when a Setup
Token is received allowing software to dequeue any pending packet transactions in the BDT before resuming token processing. The PKT_DIS bit is set under certain conditions such as back to back SETUP
tokens. This bit is not set on every SETUP token and can be modified only when UCTRL.SUSPND = 0.
bit 3:
DEV_ATT: Device Attach
Enables the 3.3V output.
1 = When DEV_ATT is set, the VUSB pin will be driven with 3.3V (nominal)
0 = The VUSB pins (D+ and D-) will be in a high impedance state
bit 2:
RESUME: Setting this bit will allow the USB to execute resume signaling. This will allow the USB to
perform remote wake-up. Software must set RESUME to 1 for 10 mS then clear it to 0 to enable remote
wake-up. For more information on RESUME signaling, see Section 7.1.7.5, 11.9 and 11.4.4 in the USB 1.1
specification.
1 = Perform RESUME signaling
0 = Normal operation
bit 1:
SUSPND: Suspends USB operation and clocks and places the module in low power mode. This bit will
generally be set in response to a UIDLE interrupt. It will generally be reset after an ACTIVITY interrupt.
VUSB regulation will be different between suspend and non-suspend modes. The VUSB pin will still be
driven, however the transceiver outputs are disabled.
1 = USB module in power conserve mode
0 = USB module normal operation
bit 0:
Unimplemented: Read as ’0’
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 65
PIC16C745/765
10.5.1.7
USB Address Register (UADDR)
The Address Register (UADDR) contains the unique
USB address that the USB will decode. The register is
reset to 00h after the RESET input has gone active or
the USB has decoded a USB Reset signaling. That will
initialize the address register to decode address 00h
as required by the USB specification. The USB
address must be written by the MCU during the USB
SETUP phase.
REGISTER 10-7: USB ADDRESS REGISTER (UADDR: 196h)
U-0
—
bit7
bit 7:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
Unimplemented: Read as ’0’
bit 6-0: ADDR: This 7-bit value defines the USB address that the USB will decode
10.5.1.8
USB Software Status Register (USWSTAT)
This register is used by the USB firmware libraries for
USB status.
Warning: Writing to this register may cause the
SIE to drop off the Bus.
REGISTER 10-8: RESERVED SOFTWARE LIBRARY REGISTER (USWSTAT: 197H):.
R/W-0
7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
6
5
4
3
2
1
0
Reserved for CH9 Firmware
Enumeration Status
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-2(1):Reserved: Read as “X’
bit 1-0: W Enumeration Status : Status of USB peripheral during enumeration
00 = Powered
01 = Default
10 = Addressed
11 = Configured
Note 1: Application should not modify these bits.
DS41124D-page 66
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
10.5.1.9
Endpoint Registers
10.5.1.10 USB Endpoint Control Register (EPCn)
Each endpoint is controlled by an Endpoint Control
Register. The PIC16C745/765 supports Buffer
Descriptors (BD) for the following endpoints:
-
The Endpoint Control Register contains the endpoint
control bits for each of the 6 endpoints available on
USB for a decoded address. These four bits define the
control necessary for any one endpoint. Endpoint 0
(ENDP0) is associated with control pipe 0 which is
required by USB for all functions (IN, OUT, and
SETUP). Therefore, after a USB_RST interrupt has
been received, the microprocessor should set UEP0 to
contain 06h.
EP0 Out
EP0 In
EP1 Out
EP1 In
EP2 Out
EP2 In
Note:
The user will be required to disable unused Endpoints
and directions using the Endpoint Control Registers.
These registers are initialized in response
to a RESET from the host. The user
must modify function USBReset in
USB_CH9.ASM to configure the endpoints
as needed for the application.
REGISTER 10-9: USB ENDPOINT CONTROL REGISTER (UEPn: 198H-19Ah)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-4: Unimplemented: Read as ’0’
bit 3-1: EP_CTL_DIS, EP_OUT_EN, EP_IN_EN: These three bits define if an endpoint is enabled and the direction of the endpoint. The endpoint enable/direction control is defined as follows:
EP_CTL_DIS EP_OUT_EN
bit 0:
EP_IN_EN
Endpoint Enable/Direction Control
X
0
0
Disable Endpoint
X
0
1
Enable Endpoint for IN tokens only
X
1
0
Enable Endpoint for OUT tokens only
1
1
1
Enable Endpoint for IN and OUT tokens
0
1
1
Enable Endpoint for IN, OUT, and SETUP tokens
EP_STALL: When this bit is set it indicates that the endpoint is stalled. This bit has priority over all other
control bits in the Endpoint Enable register, but is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access
to this endpoint will cause the USB to return a STALL handshake. The EP_STALL bit can be set or cleared
by the SIE. Refer to the USB 1.1 Specification, Sections 4.4.4 and 8.5.2 for more details on the STALL
protocol.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 67
PIC16C745/765
10.6
Buffer Descriptor Table (BDT)
To efficiently manage USB endpoint communications
the USB implements a Buffer Descriptor Table (BDT)
in register space. Every endpoint requires a 4 byte
Buffer Descriptor (BD) entry. Because the buffers are
shared between the MCU and the USB, a simple
semaphore mechanism is used to distinguish which is
allowed to update the BD and buffers in system memory. The UOWN bit is cleared when the BD entry is
“owned” by the MCU. When the UOWN bit is set to 1,
the BD entry and the buffer in system memory is
owned by the USB. The MCU should not modify the
BD or its corresponding data buffer.
Each endpoint has a 4 byte Buffer Descriptor and
points to a data buffer in the USB dual port register
space. Control of the BD and buffer would typically be
handled in the following fashion:
•
The MCU verifies UOWN = 0, sets the BDndAL to
point to the start of a buffer, if necessary fills the
buffer, then sets the BDndST byte to the desired
value with UOWN = 1.
When the host commands an in or out transaction, the Serial Interface Engine (SIE) performs
the following:
- Get the buffer address
- Read or write the buffer
- Update the USTAT register
- Update the buffer descriptors with the packet
ID (PID) value
- Set the data 0/1 bit
- Update the byte count
- Clear the UOWN bit
The MCU is interrupted and reads the USTAT,
translates that value to a BD, where the UOWN,
PID, Data 0/1, and byte count values are
checked.
•
The Buffer Descriptors provide endpoint buffer control
information for the USB and MCU. The Buffer Descriptors have different meaning based on the value of the
UOWN bit.
The USB Controller uses the data stored in the BDs
when UOWN = 1 to determine:
•
•
•
•
Data0 or Data1 PID
Data toggle synchronization enable
Number of bytes to be transmitted or received
Starting location of the buffer
•
The MCU uses the data stored in the BDs when
UOWN = 0 to determine:
•
•
•
Data0 or Data1 PID
The received TOKEN PID
Number of bytes transmitted or received
DS41124D-page 68
Warning: The bit entries should be written as a
whole word instead of using BSF, BCF to
affect individual bits. This is because of
the dual meaning of the bits. Bit sets and
clears may leave other bits set incorrectly and present incorrect data to the
SIE.
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
REGISTER 10-10: BUFFER DESCRIPTOR STATUS REGISTER. BITS WRITTEN BY THE MCU
(BDndST: 1A0h, 1A4h, 1A8h, 1ACh, 1B0h, 1B4h)
W-X
UOWN
bit7
W-X
DATA0/1
U-X
—
U-X
—
W-X
DTS
W-X
BSTALL
U-X
—
U-X
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7:
UOWN: USB Own
This UOWN bit determines who currently owns the buffer. The SIE writes a 0 to this bit when it has completed a token. This byte of the BD should always be the last byte the MCU updates when it initializes a
BD. Once the BD has been assigned to the USB, the MCU should not change it in any way.
1 = USB has exclusive access to the BD. The MCU should not modify the BD or buffer.
0 = The MCU has exclusive access to the BD. The USB ignores all other fields in the BD.
bit 6:
DATA0/1: This bit defines the type of data toggle packet that was transmitted or received
1 = Data 1 packet
0 = Data 0 packet
bit 5-4: Reserved: Read as ’X’
bit 3:
DTS: Setting this bit will enable the USB to perform Data Toggle Synchronization. If a packet arrives with
an incorrect DTS, it will be ignored and the buffer will remain unchanged.
1 = Data Toggle Synchronization is performed
0 = No Data Toggle Synchronization is performed
bit 2:
BSTALL: Buffer Stall
Setting this bit will cause the USB to issue a STALL handshake if a token is received by the SIE that would
use the BD in this location. The BD is not consumed by the SIE (the own bit remains and the rest of the
BD are unchanged) when a BSTALL bit is set.
bit 1-0: Reserved: Read as ’X’
Note:
Recommend that users not use BSF, BCF due to the dual functionality of this register.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 69
PIC16C745/765
REGISTER 10-11: BUFFER DESCRIPTOR STATUS. BITS READ BY THE MCU
(BDndST: 1A0h, 1A4h, 1A8h, 1ACh, 1B0h, 1B4h)
R/W-0
UOWN
bit7
R/W-X
DATA0/1
R/W-X
PID3
R/W-X
PID2
R/W-X
PID1
R/W-X
PID0
U-X
—
U-X
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7:
UOWN: USB Own
This UOWN bit determines who currently owns the buffer. The SIE writes a 0 to this bit when it has completed a token. This byte of the BD should always be the last byte the MCU updates when it initializes a
BD. Once the BD has been assigned to the USB, the MCU should not change it in any way.
1 = USB has exclusive access to the BD. The MCU should not modify the BD or buffer.
0 = The MCU has exclusive access to the BD. The USB ignores all other fields in the BD.
bit 6:
DATA0/1: This bit defines the type of data toggle packet that was transmitted or received
1 = Data 1 packet
0 = Data 0 packet
bit 5-2: PID: Packet Identifier
The received token PID value.
bit 1-0: Reserved: Read as 'X'
Note:
Recommend that users not use BSF, BCF due to the dual functionality of this register.
REGISTER 10-12: BUFFER DESCRIPTOR BYTE COUNT
(BDndBC: 1A1h, 1A5h, 1A9h, 1ADh, 1B1h, 1B5h)
U-X
—
bit7
U-X
—
U-X
—
U-X
—
R/W-X
BC3
R/W-X
BC2
R/W-X
BC1
R/W-X
BC0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-4: Reserved: Read as ’X’
bit 3-0: BC: The Byte Count bits represent the number of bytes that will be transmitted for an IN TOKEN or
received during an OUT TOKEN. Valid byte counts are 0 - 8. The SIE will change this field upon the completion of an OUT or SETUP token with the actual byte count of the data received.
DS41124D-page 70
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
REGISTER 10-13: BUFFER DESCRIPTOR ADDRESS LOW
(BDndAL: 1A2h, 1A6h, 1AAh, 1AEh, 1B2h, 1B6h)
R/W-X
BA7
bit7
R/W-X
BA6
R/W-X
BA5
R/W-X
BA4
R/W-X
BA3
R/W-X
BA2
R/W-X
BA1
R/W-X
BA0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-0: BA: Buffer Address
The base address of the buffer controlled by this endpoint. The upper order bit address (BA8) of the
9-bit address is assumed to be 1h. This value must point to a location within the dual port memory
space, Bank 3 (1B8h - 1DFh).
Note 1: This register should always contain a value between B8h-DFh.
10.6.1
ENDPOINT BUFFERS
FIGURE 10-2: EXTERNAL CIRCUITRY
Endpoint buffers are located in the Dual Port RAM
area. The starting location of an endpoint buffer is
determined by the Buffer Descriptor.
10.7
APPLICATION
Transceiver
VUSB
200 nF
An on-chip integrated transceiver is included to drive
the D+/D- physical layer of the USB.
10.7.1
Host
Controller/HUB
PIC16C745/765
1.5K
D-
REGULATOR
D+
A 3.3V regulator provides the D+/D- drives with power,
as well as an external pin. This pin is intended to be
used to power a 1.5k +5% pull-up resistor on the Dline to signal a low speed device, as specified by the
USB 1.1 Specification. A +20% 200nF capacitor is
required on VUSB for regulator stability.
Note: The PIC16C745/765 requires an external resistor and
capacitor to communicate with a host over USB.
10.7.1.1
VUSB Output
The VUSB provides a 3.3V nominal output. This drive
current is sufficient for a pull-up only.
10.8
USB Software Libraries
Microchip Technology provides a comprehensive set
of Chapter 9 Standard requests functions to aid developers in implementing their designs. See Microchip
Technology’s website for the latest version of the software libraries.
TABLE 10-1:
USB PORT FUNCTIONS
Input
Type
Output
Type
VUSB
—
Power
D-
USB
USB
USB Differential Bus
D+
USB
OD = open drain, ST = Schmitt Trigger
USB
USB Differential Bus
Name
VUSB
Function
DD+
Legend:
1999-2013 Microchip Technology Inc.
Description
Regulator Output Voltage
Preliminary
DS41124D-page 71
PIC16C745/765
10.9
USB Firmware Users Guide
10.9.3
10.9.1
INTRODUCING THE USB SOFTWARE
INTERFACE
10.9.3.1
Microchip provides a layer of software that handles the
lowest level interface so your application won’t have
to. This provides a simple Put/Get interface for communication. Most of the USB processing takes place in
the background through the Interrupt Service Routine.
From the application viewpoint, the enumeration process and data communication takes place without further interaction. However, substantial setup is required
in the form of generating appropriate descriptors.
FIGURE 10-3: USB SOFTWARE INTERFACE
Main Application
Get
USB
If you write your own Interrupt Service Routine: W,
Status, FSR and PCLATH may be corrupted by servicing the USB interrupt and must be saved.
USB_MAIN.ASM provides a skeleton ISR which does
this for you, and includes tests for each of the possible
interrupt bits. This provides a good starting point if you
haven't already written your own.
USB
INTEGRATING USB INTO YOUR
APPLICATION
The latest version of the USB interface software
is
available
on
Microchip's
website
(see
http://www.microchip.com/).
The interface to the application is packaged in 3 functions: InitUSB, PutUSB and GetUSB. InitUSB initializes the USB peripheral, allowing the host to
enumerate the device. Then, for normal data communications, function PutUSB sends data to the host and
GetUSB receives data from the host.
However, there's a fair amount of setup work that must
be completed. USB depends heavily on the descriptors. These are the software parameters that are communicated to the host to let it know what the device is,
and how to communicate with it. See USB V1.1 spec
section 9.5 for more details.
Also, code must be added to give meaning to the
SetConfiguration command. The Chapter 9 commands call SetConfiguration when it receives the
command. Both the descriptors and SetConfiguration are in DESCRIPT.ASM.
InitUSB enables the USB interrupt so enumeration
can begin. The actual enumeration process occurs in
the background, driven by the host and the Interrupt
Service Routine. Macro ConfiguredUSB waits until
the device is in the CONFIGURED state. The time
required to enumerate is completely dependent on the
host and bus loading.
DS41124D-page 72
Stack Levels
The hardware stack on the PIC® MCU is only 8 levels
deep. So the worst case call between the application
and ISR can only be 8 levels. The enumeration process
requires 4 levels, so it's best if the main application holds
off on any processing until enumeration is complete.
ConfiguredUSB is a macro that waits until the enumeration process is complete for exactly this purpose, by
testing the lower two bits of USWSTAT (0x197).
Init
USB
USB Peripheral
10.9.2
Processor Resources
Most of the USB processing occurs via the interrupt and
thus is invisible to application. However, it still consumes processor resources. These include ROM, RAM,
Common RAM and Stack Levels. This section attempts
to quantify the impact on each of these resources, and
shows ways to avoid conflicts.
10.9.3.2
Put
USB
INTERRUPT STRUCTURE CONCERNS
10.9.3.3
ROM
The code required to support the USB interrupt,
including the chapter 9 interface calls, but not including the descriptor tables, is about 1kW. The descriptor
and string descriptor tables can each take up to an
additional 256W. The location of these parts is not
restricted.
10.9.3.4
RAM
With the exception of Common RAM discussed below,
servicing the USB interrupt requires ~40 bytes of
RAM in Bank 2. That leaves all the General Purpose
RAM in banks zero and one, plus half of bank two,
available for your application to use.
10.9.3.5
Common RAM Usage
The PIC16C745/765 has 16 bytes of common RAM.
These are the last 16 addresses in each bank and all
refer to the same 16 bytes of memory, without regard
to which register bank is currently addressed by the
RP0, RP1 and IRP bits.
These are particularly useful when responding to interrupts. When an interrupt occurs, the ISR doesn't immediately know which bank is addressed. With devices
that don't support common RAM, the W register must
be provided for in each bank. The 16C745/765 can
save the appropriate registers in Common RAM and not
have to waste a byte in each bank for W register.
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
10.9.3.6
Buffer Allocation
The PIC16C745/765 has 64 bytes of Dual Port RAM.
24 are used for the Buffer Descriptor Table (BDT),
leaving 40 bytes for buffers.
Endpoints 0 IN and OUT need dedicated buffers since
a setup transaction can never be NAKed. That leaves
three buffers for four possible Endpoints, but the USB
spec requires that low speed devices are only allowed
2 endpoints (USB 1.1 paragraph 5.3.1.2), where an
endpoint is a simplex connection that is defined by the
combination of Endpoint number and direction.
10.9.3.7
Vendor Specific Commands
Vendor specific commands are defined by the vendor.
These are parsed out, but are not processed. Instead,
control is passed to function CheckVendor where
they can be processed.
10.9.4
FILE PACKAGING
The software interface is packaged into four files,
designed to simplify the integration with your application.
File USB_CH9.ASM contains the interface and core
functions
needed
to
enumerate
the
bus.
DESCRIPT.ASM contains the device, config, interface, endpoint and string descriptors. Both of these
files must be linked in with your application.
HIDCLASS.ASM provides some HID Class specific
functions. Currently only GetReportDescriptor is supported. Other class specific functions can be implemented in a similar fashion. When a token done
interrupt determines that it's a class specific command
on the basis that ReportType bit 6 is set, control is
passed to function ClassSpecific. If you're working
with a different class, this is your interface between the
core functions and the class specific functions.
USB_MAIN.ASM is useful as a starting point on a new
application and as an example of how an existing
application needs to service the USB interrupt and
communicate with the core functions.
10.9.5
FUNCTION CALL REFERENCE
Interface between the Application and Protocol layer
takes place in three main functions: InitUSB, PutUSB
and GetUSB.
InitUSB should be called by the main program immediately upon power-up. It enables the USB peripheral and
USB Reset interrupt, and transitions the part to the
powered state to prepare the device for enumeration.
See Section 10.9.6 “Behind the Scenes” for details on
the enumeration process.
DeInitUSB disables the USB peripheral, removing the
device from the bus. An application might call
DeInitUSB if it was finished communicating to the host
and didn't want to be polled any more.
1999-2013 Microchip Technology Inc.
PutUSB (Buffer pointer, Buffer size, Endpoint) sends
data up to the host. The pointer to the block of data to
transmit is in the FSR/IRP, and the block size and endpoint is passed in W register. If the IN buffer is available
for that endpoint, PutUSB copies the buffer, flips the
Data 0/1 bit and sets the OWNS bit. A buffer not available would occur when it has been previously loaded
and the host has not requested that the USB peripheral
transmit it. In this case, a failure code would be returned
so the application can try again later.
GetUSB (Buffer Pointer, Endpoint) returns data sent
from the host. If the out buffer pointed to by the endpoint
number is ready, as indicated by the OWNS bit, the
buffer is copied from dual port RAM to the locations
pointed to by the buffer pointer, and resets the endpoint
for the next out transaction from the host. If no data is
available, it returns a failure code. Thus the functions of
polling for buffer ready and copying the data are combined into the one function.
ServiceUSBInt handles all interrupts generated by the
USB peripheral. First, it copies the active buffer to common RAM, which provides a quick turn around on the
buffer in dual port RAM and also avoids having to
switch banks during processing of the buffer. File
USB_MAIN.ASM gives an example of how
ServiceUSBInt would be invoked.
StallUSBEP/UnstallUSBEP sets or clears the stall bit
in the endpoint control register. The stall bit indicates to
the host that user intervention is required and until such
intervention is made, further attempts to communicate
with the endpoint will not be successful. Once the user
intervention has been made, UnstallUSBEP clears the
bit allowing communication to take place. These calls
are useful to signal to the host that user intervention is
required. An example of this might be a printer out of
paper.
SoftDetachUSB clears the DEV_ATT bit, electrically
disconnecting the device from the bus, then reconnecting, so it can be re-enumerated by the host. This process takes approximately 50 mS, to ensure that the host
has seen the device disconnect and reattach to the bus.
CheckSleep tests the UCTRL.UIDLE bit if set, indicating that there has been no activity on the bus for 3 mS.
If set, the device can be put to SLEEP, which puts the
part into a low power standby mode, until wakened by
bus activity. This has to be handled outside the ISR
because we need the interrupt to wake us from SLEEP,
and also because the application may not be ready to
SLEEP when the interrupt occurs. Instead, the application should periodically call this function to poll the bit,
when the device is in a good place to SLEEP.
Prior to putting the device to SLEEP, it enables the
activity interrupt so the device will be awakened by the
first transition on the bus. The PIC device will immediately jump to the ISR, recognize the activity interrupt,
which then disables the interrupt and resumes processing with the instruction following the CheckSleep call.
Preliminary
DS41124D-page 73
PIC16C745/765
ConfiguredUSB (Macro) continuously polls the enumeration status bits and waits until the device has been
configured by the host. This should be used after the
call to InitUSB and prior to the first time your application
attempts to communicate on the bus.
SetConfiguration is a callback function that allows
your application to associate some meaning to a Set
Configuration command from the host. The CH9 software stores the value in USB_Curr_Config so it can be
reported back on a Get Configuration call. This function is also called, passing the new configuration in W.
This function is called from within the ISR, so it should
be kept as short as possible.
10.9.6
BEHIND THE SCENES
InitUSB clears the error counters and enables the
3.3V regulator and the USB Reset interrupt. This
implements the requirement to prevent the PIC device
from responding to commands until the device has
been RESET.
The host sees the device and resets the device, to
begin the enumeration process. The RESET then initializes the Buffer Descriptor Table (BDT), EndPoint
Control Registers and enables the remaining USB
interrupt sources.
The Interrupt transfers control to the interrupt vector
(address 0x0004). Any Interrupt Service Routine
must preserve the processor state by saving the FSRs
that might change during interrupt processing. We recommend saving W, STATUS, PCLATH and FSR. W
can be stored in unbanked RAM to avoid banking
issues. Then it starts polling the Interrupt flags to see
what triggered the interrupt. The USB interrupts are
serviced by calling ServiceUSBInt which further tests
the USB interrupt sources to determine how to process the interrupt.
Then, the host sends an IN transaction to receive the
data from the setup transaction. The SIE sends the
data from the EP0 IN buffer and then sets the Token
Done interrupt to notify us that the data has been sent.
If there is additional data, the next buffer is setup in
EP0 IN buffer.
This token processing sequence holds true for the
entire enumeration sequence, which walks through the
flow chart starting chapter 9 of the USB spec. The
device starts off in the powered state, transitions to
default via the Reset interrupt, transitions to
ADDRESSED via the SetAddress command, and
transitions to CONFIGURED via a SetConfiguration
command.
The USB peripheral detects several different errors
and handles most internally. The USB_ERR interrupt
notifies the PIC device that an error has occurred. No
action is required by the device when an error occurs.
Instead, the errors are simply acknowledged and
counted. There is no mechanism to pull the device off
the bus if there are too many errors. If this behavior is
desired, it must be implemented in the application.
The Activity interrupt is left disabled until the USB
peripheral detects no bus activity for 3 mS. Then it
suspends the USB peripheral and enables the activity
interrupt. The activity interrupt then reactivates the
USB peripheral when bus activity resumes, so processing may continue.
CheckSleep is a separate call that takes the bus idle
one step further and puts the PIC device to SLEEP, if
the USB peripheral has detected no activity on the
bus. This powers down most of the device to minimal
current draw. This call should be made at a point in the
main loop where all other processing is complete.
Then, the host sends a setup token requesting the
device descriptor. The USB Peripheral receives the
Setup transaction, places the data portion in the EP0
OUT buffer, loads the USTAT register to indicate which
endpoint received the data and triggers the Token
Done (TOK_DNE) interrupt. The Chapter 9 commands
then interpret the Setup token and sets up the data to
respond to the request in the EP0 IN buffer, then sets
the UOWN bit to tell the SIE there is data available.
DS41124D-page 74
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
10.9.7
EXAMPLE
This example shows how the USB functions are used.
This example first initializes the USB peripheral, which
allows the host to enumerate the device. The enumeration process occurs in the background, via an Interrupt Service Routine. This function waits until
enumeration is complete, and then polls EP1 OUT to
see if there is any data available. When a buffer is
available, it is copied to the IN buffer. Presumably
your application would do something more interesting
with the data than this example.
; ******************************************************************
; Demo program that initializes the USB peripheral, allows the Host
;
to Enumerate, then copies buffers from EP1OUT to EP1IN.
; ******************************************************************
main
call
InitUSB
; Set up everything so we can enumerate
ConfiguredUSB
; wait here until we have enumerated.
CheckEP1
; Check Endpoint 1 for an OUT transaction
bankisel buffer
; point to lower banks
movlw
buffer
movwf
FSR
; point FSR to our buffer
movlw
1
; check end point 1
call
GetUSB
; If data is ready, it will be copied.
btfss
STATUS,C
; was there any data for us?
goto
PutBuffer
; Nope, check again.
; Code host to process out buffer from host
PutBuffer
bankisel buffer
movlw
movwf
movlw
call
btfss
goto
goto
buffer
FSR
0x81
PutUSB
STATUS,C
PutBuffer
idleloop
; point to lower banks
; save buffer length
; point FSR to our buffer
; put 8 bytes to Endpoint 1
; was it successful?
; No: try again until successful
; Yes: restart loop
end
10.9.8
ASSEMBLING THE CODE
10.9.8.1
The code is designed to be used with the linker. There
is no provision for includable files. The code comes
packaged as several different files:
• USB_CH9.ASM - handles all the Chapter 9 command processing.
• USB_DEFS.INC - #Defines used throughout the
code.
• USB_MAIN.ASM - Sample interrupt service
routine.
• HIDCLASS.ASM - Handles the HID class specific
commands.
1999-2013 Microchip Technology Inc.
Assembly Options
There are two #defines at the top of the code that control assembly options.
10.9.8.2
#define ERRORCOUNTERS
This define includes code to count the number of
errors that occur, by type of error. This requires extra
code and RAM locations to implement the counters.
10.9.8.3
#define FUNCTIONIDS
This is useful for debug. It encodes the upper 6 bits of
USWSTAT (0x197) to indicate which function is executing. See the defines in USB_DEFS.INC for the
codes that will be encoded.
Preliminary
DS41124D-page 75
PIC16C745/765
NOTES:
DS41124D-page 76
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
11.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, Serial EEPROMs, etc.
The USART can be configured in the following modes:
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bits SPEN (RCSTA) and TRISC have to be
set in order to configure pins RC6/TX/CK and RC7/RX/
DT as the Universal Synchronous Asynchronous
Receiver transmitter.
REGISTER 11-1: TRANSMIT STATUS AND CONTROL REGISTER (TXSTA: 98h)
R/W-0
CSRC
bit7
bit 7:
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
TRMT
R/W-0
TX9D
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3:
Unimplemented: Read as '0'
bit 2:
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1:
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data. (Can be used for parity.)
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 77
PIC16C745/765
REGISTER 11-2: RECEIVE STATUS AND CONTROL REGISTER (RCSTA: 18h)
R/W-0
SPEN
bit7
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
—
R-0
FERR
R-0
OERR
R-x
RX9D
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3:
Unimplemented: Read as '0'
bit 2:
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1:
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0:
RX9D: 9th bit of received data. (Can be used for parity.)
DS41124D-page 78
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
11.1
USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 11-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Given the desired baud rate and FINT, the nearest integer value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
TABLE 11-1:
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FINT/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting the new baud rate.
11.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
near the center of each bit time by a majority detect circuit to determine if a high or a low level is present at the
RX pin.
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FINT/(64(SPBRG+1))
(Synchronous) Baud Rate = FINT/(4(SPBRG+1))
Baud Rate = FINT/(16(SPBRG+1))
NA
TABLE 11-2:
BAUD RATES FOR
SYNCHRONOUS MODE
TABLE 11-3:
24 MHz
Desired
Baud
BAUD RATES FOR
ASYNCHRONOUS MODE
(BRGH = 0)
24 MHz
Actual
Baud
% of Error
Desired
Baud
SPBRG
Actual
Baud
% of Error
SPBRG
300
1200
300
2400
1200
4800
2400
2403.85
0.16
155
9600
4800
4807.69
0.16
77
19200
9600
9615.38
0.16
38
19736.84
2.80
18
38400
38461.54
0.16
155
19200
57600
57692.31
0.16
103
38400
41666.67
8.51
8
62500.00
8.51
5
115200
115384.62
0.16
51
57600
230400
230769.23
0.16
25
115200
125000.00
8.51
2
460800
461538.46
0.16
12
230400
921600
1000000.00
8.51
5
460800
921600
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 79
PIC16C745/765
TABLE 11-4:
BAUD RATES FOR
ASYNCHRONOUS MODE
(BRGH = 1)
24 MHz
Desired
Baud
Actual
Baud
% of Error
SPBRG
300
1200
2400
4800
9600
9615.38
0.16
155
19200
19230.77
0.16
77
38400
38461.54
0.16
38
57600
57692.31
0.16
25
115200
115384.62
0.16
12
230400
250000.00
8.51
5
460800
500000.00
8.51
2
921600
TABLE 11-5:
Address
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
18h
RCSTA
SPEN
RX9
SREN CREN
—
FERR
OERR RX9D
0000 -00x
0000 -00x
99h
SPBRG
Baud Rate Generator Register
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
DS41124D-page 80
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
11.2
( PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT
(TXSTA) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-tozero (NRZ) format (one start bit, eight or nine data bits,
and one stop bit). The most common data format is 8
bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 11-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA).
The USART Asynchronous module consists of the following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
11.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
In order to select 9-bit transmission, transmit bit TX9
(TXSTA) should be set and the ninth bit should be
written to TX9D (TXSTA). The ninth bit must be
written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
LSb
(8)
Pin Buffer
and Control
0
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 81
PIC16C745/765
Steps to follow when setting up an Asynchronous
Transmission:
4.
1.
5.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1)
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
2.
3.
If 9-bit transmission is desired, then set transmit
bit TX9.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts transmission).
6.
7.
FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
Bit 7/8
Stop Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
RC6/TX/CK (pin)
Start Bit
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 2
Word 1
BRG output
(shift clock)
Bit 0
Bit 1
WORD 1
Bit 7/8
WORD 1
Transmit Shift Reg.
Stop Bit
Start Bit
WORD 2
Bit 0
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 11-6:
Address
Name
0Ch
PIR1
18h
RCSTA
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
PSPIF(1)
ADIF
RCIF
TXIF
SPEN
RX9
SREN
CREN
Bit 5
19h
TXREG USART Transmit Register
8Ch
PIE1
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
Bit 4
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
Bit 3
Bit 2
USBIF CCP1IF
—
FERR
USBIE CCP1IE
—
BRGH
Bit 1
TMR2IF
OERR
TMR2IE
TRMT
Bit 0
Value on:
POR,
BOR
TMR1IF 0000 0000
RX9D
0000 0000
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR1IE 0000 0000
TX9D
Value on
all other
Resets
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124D-page 82
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
11.2.2
possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin
shifting to the RSR register. On the detection of the
STOP bit of the third byte, if the RCREG register is still
full, then overrun error bit OERR (RCSTA) will be
set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
so it is essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA) is set if a stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG, will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 11-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter operates at the bit rate or at FINT.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA).
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register, i.e., it is a two deep FIFO. It is
FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM
FERR
OERR
CREN
SPBRG
RSR Register
MSb
Baud Rate Generator
Stop (8)
7
1
LSb
0 Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
Interrupt
Data Bus
RCIE
FIGURE 11-5: ASYNCHRONOUS RECEPTION
RX (pin)
Start
bit
bit0
bit1
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
bit7/8 Stop
bit
Start
bit
bit0
WORD 1
RCREG
bit7/8
Stop
bit
Start
bit
bit7/8
Stop
bit
WORD 2
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 83
PIC16C745/765
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1).
Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
TABLE 11-7:
Address
Name
0Ch
PIR1
18h
RCSTA
7.
8.
9.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
PSPIF(1)
ADIF
RCIF
TXIF
SPEN
RX9
SREN
CREN
1Ah
RCREG USART Receive Register
8Ch
PIE1
98h
TXSTA
99h
SPBRG
Bit 4
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
Bit 3
Bit 2
USBIF CCP1IF
—
FERR
USBIE CCP1IE
—
BRGH
Baud Rate Generator Register
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
TMR2IF
TMR1IF
0000 0000
0000 0000
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR2IE
TMR1IE
0000 0000
0000 0000
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124D-page 84
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
11.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e., transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA). In
addition, enable bit SPEN (RCSTA) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA).
11.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and interrupt bit TXIF (PIR1) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hiimpedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-impedance receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock
(Figure 11-6). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 11-7). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally, when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
1999-2013 Microchip Technology Inc.
Preliminary
Initialize the SPBRG register for the appropriate
baud rate (Section 11.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
DS41124D-page 85
PIC16C745/765
TABLE 11-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
PSPIF(1)
ADIF
SPEN
RX9
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR2IE
TMR1IE
0000 0000
0000 0000
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Bit 5
0Ch
PIR1
18h
RCSTA
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
98h
TXSTA
99h
SPBRG
USBIE CCP1IE
—
BRGH
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
FIGURE 11-6: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin
bit 0
bit 1
WORD 1
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit 2
bit 7
bit 0
bit 1
WORD 2
bit 7
RC6/TX/CK pin
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT bit
TXEN bit
'1'
'1'
Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 11-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS41124D-page 86
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
11.3.2
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA) or enable bit CREN (RCSTA). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit RCIF
(PIR1) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read only bit, which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e., it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
TABLE 11-9:
Address
Name
0Ch
PIR1
18h
RCSTA
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 11.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
Bit 6
PSPIF(1)
ADIF
SPEN
RX9
Bit 5
Value on:
POR,
BOR
Value on all
other Resets
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
1Ah
RCREG
USART Receive Register
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
99h
SPBRG
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 87
PIC16C745/765
FIGURE 11-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit '0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRG = '0'.
DS41124D-page 88
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
11.4
11.4.2
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA).
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Also, bit SREN is a don't care in Slave mode.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a)
1.
11.4.1
b)
c)
d)
e)
USART SYNCHRONOUS SLAVE
TRANSMIT
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the interrupt vector (0004h).
2.
3.
4.
5.
6.
Steps to follow when setting up a Synchronous Slave
Transmission:
7.
1.
8.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
1999-2013 Microchip Technology Inc.
Preliminary
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
DS41124D-page 89
PIC16C745/765
TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
PSPIF(1)
SPEN
ADIF
RCIF
TXIF
RX9
SREN CREN
0Ch
PIR1
18h
RCSTA
19h
TXREG USART Transmit Register
8Ch
PIE1
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
Bit 3
Bit 2
USBIF CCP1IF
—
FERR
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
TMR2IF
TMR1IF
0000 0000
0000 0000
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR1IE
0000 0000
0000 0000
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
USBIE CCP1IE TMR2IE
—
BRGH
TRMT
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
0Ch
Name
PIR1
18h
RCSTA
1Ah
RCREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
PSPIF(1)
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
USART Receive Register
(1)
PSPIE
CSRC
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124D-page 90
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
12.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has three registers. These registers
are:
The 8-bit Analog-To-Digital (A/D) converter module has
five inputs for the PIC16C745 and eight for the
PIC16C765.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital value. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD) or the
voltage level on the RA3/AN3/VREF pin.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived
from the A/D’s dedicated internal RC oscillator.
1999-2013 Microchip Technology Inc.
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 12-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 12-2, configures the functions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference)
or as digital I/O.
Additional information on using the A/D module can be
found in the PIC Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note, AN546.
Note:
Preliminary
In order to maintain 8-bit A/D accuracy,
ADCS must be set to either FINT/32 or
FRC. Choosing FINT/8 or FINT/2 will cause
loss of accuracy, due to the USB module’s
requirement of running at 24 MHz.
DS41124D-page 91
PIC16C745/765
REGISTER 12-1: A/D CONTROL REGISTER (ADCON0: 1Fh)
R/W-0 R/W-0
ADCS1 ADCS0
bit7
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
GO/DONE
U-0
—
R/W-0
ADON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR Reset
bit 7-6: ADCS: A/D Conversion Clock Select bits
00 = FINT/2
01 = FINT/8
10 = FINT/32(2)
11 = FRC (clock derived from dedicated internal oscillator)(2)
bit 5-3: CHS: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
101 = channel 5, (RE0/AN5)(1)
110 = channel 6, (RE1/AN6)(1)
111 = channel 7, (RE2/AN7)(1)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1:
Unimplemented: Read as '0'
bit 0:
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C765 only.
2: Choose FINT/32 or FRC to maintain 8-bit A/D accuracy at 24 MHz.
DS41124D-page 92
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
REGISTER 12-2: A/D CONTROL REGISTER 1 (ADCON1: 9Fh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR
Reset
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG: A/D Port Configuration Control bits
PCFG AN7(1)
000
001
010
011
100
101
11x
A
A
D
D
D
A
D
AN6
A
A
D
D
D
A
D
AN5
A
A
D
D
D
A
D
AN4
A
A
A
A
D
A
D
AN3
A
VREF
A
VREF
A
VREF
D
AN2
A
A
A
A
D
A
D
AN1
A
A
A
A
A
A
D
AN0
A
A
A
A
A
A
D
VREF
VDD
RA3
VDD
AN3
VDD
AN3
VDD
A = Analog input
D = Digital I/O
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C765 only.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 93
PIC16C745/765
The following steps should be followed for doing an A/D
conversion:
4.
1.
5.
2.
3.
Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
6.
7.
• Waiting for the A/D interrupt
Read A/D result register (ADRES), clear bit
ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 12-1: A/D BLOCK DIAGRAM
CHS
111
RE2/AN7(1)
110
RE1/AN6(1)
101
RE0/AN5(1)
100
RA5/AN4
VIN
011
(Input voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
VDD
000 or
010 or
100 or
11x
VREF
(Reference
voltage)
000
RA0/AN0
001 or
011 or
101
PCFG
Note 1: Not available on PIC16C745.
DS41124D-page 94
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
12.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 12-2. The source impedance affects the
offset voltage at the analog input (due to pin leakage
current).
The maximum recommended impedance for analog sources is 10 k. After the analog input channel is
selected (changed), the acquisition must pass before
the conversion can be started.
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC Mid-Range MCU Family Reference Manual
(DS33023). In general, however, given a max of 10k
and a worst case temperature of 100°C, TACQ will be no
more than 16 sec.
FIGURE 12-2: ANALOG INPUT MODEL
VDD
Rs
VA
ANx
CPIN
5 pF
VT = 0.6V
VT = 0.6V
RIC 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend
CPIN
VT
I leakage
RIC
SS
CHOLD
EQUATION 12-1:
TACQ
= input capacitance
= threshold voltage
= leakage current at the pin due to
various junctions
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
ACQUISITION TIME
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
TAMP = 5S
TC = - (51.2pF)(1k + RSS + RS) In(1/511)
TCOFF = (Temp -25C)(0.05S/C)
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 95
PIC16C745/765
12.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•
•
•
•
2TOSC
8TOSC
32TOSC
Dedicated Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
TABLE 12-1:
TAD vs. DEVICE OPERATING
FREQUENCIES
AD Clock Source (TAD)
Operation
ADCS1:ADCS0
Device
Frequency
24 MHz
2TOSC
00
83.3 ns
8TOSC
01
333.3 ns
32TOSC
10
1.333
RC
11
2 - 6 s(1,2)
Note 1: The RC source has a typical TAD time of 4 s.
2: For device frequencies above 1 MHz, the
device must be in SLEEP for the entire conversion, or the A/D accuracy may be out of
specification.
12.3
Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be
converted.
12.4
Note:
2: Analog levels on any pin that is defined as
a digital input, but not as an analog input,
may cause the input buffer to consume
current that is out of specification.
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed
conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started on
the selected channel.
12.5
A/D Operation During Sleep
The A/D module can operate during SLEEP mode.
This requires that the A/D clock source be set to RC
(ADCS = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be
cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will
wake-up from SLEEP. If the A/D interrupt is not
enabled, the A/D module will then be turned off,
although the ADON bit will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
The A/D operation is independent of the state of the
CHS bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
A/D Conversions
12.6
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruction that sets the GO/DONE bit.
Effects of a RESET
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All pins with analog functions
are configured as available inputs.
The ADRES register will contain unknown data after a
Power-on Reset.
3: The TRISE register is not provided on the
PIC16C745.
DS41124D-page 96
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
12.7
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M bits (CCP2CON) be programmed as
1011 and that the A/D module is enabled (ADON bit is
set). When the trigger occurs, the GO/DONE bit will be
set, starting the A/D conversion, and the Timer1 counter
will be reset to zero. Timer1 is reset to automatically
repeat the A/D acquisition period with minimal software
TABLE 12-2:
Address
overhead (moving the ADRES to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
SUMMARY OF A/D REGISTERS
Name
Value on:
POR,
BOR
Value on all
other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
USBIE
CCP1IE
TMR2IE TMR1IE 0000 0000 0000 0000
1Eh
ADRES
A/D Result Register
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/
DONE
—
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
05h
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
85h
TRISA
—
—
INTCON
0Bh,8Bh,
10Bh,18Bh
0Ch
09h
89h
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
ADON
PCFG0 ---- -000 ---- -000
RA0
—
—
—
—
—
TRISE
IBF(1)
OBF(1)
IBOV(1)
PSP-MODE(1)
—
--0x 0000 --0u 0000
--11 1111 --11 1111
PORTA Data Direction Register
PORTE
0000 00-0 0000 00-0
RE2
(1)
PORTE(1)
RE1
(1)
(1)
RE0
---- -xxx ---- -uuu
Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved on the PIC6C745; always maintain these bits clear.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 97
PIC16C745/765
NOTES:
DS41124D-page 98
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
13.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16C745/765 family has a
host of such features intended to maximize system reliability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-Circuit Serial Programming™ (ICSP)
One is the Oscillator Start-up Timer (OST), intended to
keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only and is designed to keep the part in RESET, while
the power supply stabilizes. With these two timers onchip, most applications need no external RESET
circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, WDT wake-up or through an
interrupt. Several oscillator options are also made
available to allow the part to fit the application. The EC
oscillator allows the user to directly drive the microcontroller, while the HS oscillator allows the use of a high
speed crystal/resonator. A set of configuration bits are
used to select various options.
13.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The PIC16C745/765 has a Watchdog Timer, which can
be shut off only through configuration bits. It runs off its
own dedicated RC oscillator for added reliability. There
are two timers that offer necessary delays on power-up.
The user will note that address 2007h is beyond the user
program memory space. In fact, it belongs to the special
test/configuration memory space (2000h - 3FFFh),
which can be accessed only during programming.
REGISTER 13-1: CONFIGURATION WORD
CP1
CP0
CP1
CP0
CP1
CP0
—
—
CP1
CP0
PWRTE WDTE FOSC1 FOSC0
bit13
bit0
Register:
Address
CONFIG
2007h
bit 13-12: CP: Code Protection bits(1)
11-10: 00 = All memory is code protected
9-8: 01 = Upper 3/4th of program memory code protected
5-4: 10 = Upper half of program memory code protected
11 = Code protection off
bit 7-6:
Unimplemented: Read as '1'
bit 3:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled • No delay after Power-up Reset or Brown-out Reset
0 = PWRT enabled • A delay of 4x WDT (72 ms) is present after Power-up and Brown-out
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC: Oscillator Selection
00 = HS - HS osc
01 = EC - External clock. CLKOUT on OSC2 pin
10 = H4 - HS osc with 4x PLL enabled
11 = E4 - External clock with 4x PLL enabled. CLKOUT on OSC2 pin
Note 1:
All of the CP pairs have to be given the same value to enable the code protection scheme listed.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 99
PIC16C745/765
13.2
TABLE 13-1:
Oscillator Configurations
13.2.1
OSCILLATOR TYPES
The PIC16C745/765 can be operated in four different
oscillator modes. The user can program a configuration
bit (FOSC0) to select one of these four modes:
•
•
•
•
EC
E4
HS
H4
External Clock
External Clock with internal PLL enabled
High Speed Crystal/Resonator
High Speed Crystal/Resonator with
internal PLL enabled
Mode
Freq
OSC1
OSC2
HS
6.0 MHz
10 - 68 pF
10 - 68 pF
These values are for design guidance only. See notes at
bottom of page.
TABLE 13-2:
Osc Type
HS
13.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
FIGURE 13-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OSC CONFIGURATION)
To internal
logic
C1
XTAL
OSC2
C2
Note 1:
Rf
SLEEP
PIC16C745/765
Rs
Note1
A series resistor may be required for AT strip cut
crystals.
DS41124D-page 100
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Crystal
Freq
6.0 MHz
Cap. Range
C1
Cap. Range
C2
15 - 33 pF
15 - 33 pF
These values are for design guidance only. See notes at
bottom of page.
In HS mode, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to
establish oscillation (Figure 13-1). The PIC16C745/
765 oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may give a frequency
out of the crystal manufacturers specifications. When in
HS mode, the device can have an external clock
source to drive the OSC1/CLKIN pin (Figure 13-2). In
this mode, the oscillator start-up timer is active for a
period of 1024*TOSC. See the PIC Mid-Range MCU
Reference Manual (DS33023) for details on building an
external oscillator.
OSC1
CERAMIC RESONATORS
Ranges Tested:
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the startup time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
3: Rs may be required in HS mode to avoid
overdriving crystals with low drive level
specification.
4: When migrating from other PIC devices,
oscillator performance should be verified.
5: Users should consult the USB Specification
1.1 to ensure their resonator/crystal oscillator meets the required jitter limits for USB
operation.
13.2.3
H4 MODE
In H4 mode, a PLL module is switched on in-line with
the clock provided across OSC1 and OCS2. The output
of the PLL drives FINT.
13.2.4
PLL
An on-board 4x PLL provides a cheap means of generating a stable 24 MHz FINT, using an external 6 MHz
resonator. After power-up, a PLL settling time of less
than TPLLRT is required.
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
13.2.5
EXTERNAL CLOCK IN
13.2.6
In EC mode, users may directly drive the PIC16C745/
765 provided that this external clock source meets the
AC/DC timing requirements listed in Section 17.4.
Figure 13-2 below shows how an external clock circuit
should be configured.
E4 MODE
In E4 mode, a PLL module is switched on in-line with
the clock provided to OSC1. The output of the PLL
drives FINT.
Note: CLKOUT is the same frequency as OSC1 if
in E4 mode, otherwise CLKOUT = OSC1/4.
FIGURE 13-2: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
ext. system
OSC1
PIC16C745/765
OSC2/CLKOUT
CLKOUT
FIGURE 13-3: OSCILLATOR/PLL CLOCK CONTROL
OSC2
OSC1
13.3
6 MHz
EC
E4
HS
H4
4x PLL
24 MHz
FINT
Q Clock
Generator
To Circuits
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 13-4.
RESET
The PIC16CXX differentiates between various kinds of
RESET:
•
•
•
•
•
EC
E4
HS
H4
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
Brown-out Reset (BOR)
The PIC® devices have a MCLR noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on POR, on the MCLR and WDT Reset,
on MCLR Reset during SLEEP, and on BOR. The TO
and PD bits are set or cleared differently in different
RESET situations as indicated in Table 13-4. These
bits are used in software to determine the nature of the
RESET. See Table 13-7 for a full description of RESET
states of all registers.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 101
PIC16C745/765
FIGURE 13-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT Time-out
Module Reset
VDD rise Power-on Reset
detect
VDD
Brown-out
Reset
S
OST/PWRT
OST
Chip Reset
R
10-bit Ripple counter
Q
OSC1
PWRT
Dedicated
On-chip
RC OSC
10-bit Ripple counter
Enable PWRT
Enable OST
DS41124D-page 102
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
13.4
RESETS
13.4.4
13.4.1
POWER-ON RESET (POR)
If VDD falls below VBOR (parameter D005) for longer
than TBOR (parameter #35), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create
a POR. A maximum rise time for VDD is specified. See
Electrical Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
startup conditions.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
13.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up from the POR. The PWRT operates on an internal RC oscillator. The device is kept in
RESET as long as the PWRT is active. The PWRT’s
time delay allows VDD to rise to an acceptable level. A
configuration bit is provided to enable/disable the
PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
13.4.3
OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer provides a delay of 1024
oscillator cycles (from OSC1 input) after the PWRT
delay. This ensures that the crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for HS mode and
only on Power-on Reset or wake-up from SLEEP.
BROWN-OUT RESET (BOR)
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33). If VDD should fall below VBOR
during TPWRT, the Brown-out Reset process will
restart when VDD rises above VBOR, with the Powerup Timer Reset. Since the device is intended to operate at 5V nominal only, the Brown-out Detect is always
enabled and the device will RESET when Vdd falls
below the brown-out threshold. This device is unique
in that the 4WDT timer will not activate after a brownout if PWRTE = 1 (inactive).
13.4.5
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled), when a Power-on
Reset occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (HS). When the OST ends,
the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16CXX device operating in
parallel.
Table 13-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 13-7 shows
the RESET conditions for all the registers.
13.4.6
POWER CONTROL/STATUS REGISTER
(PCON)
The Brown-out Reset Status bit, BOR, is unknown on a
POR. It must be set by the user and checked on subsequent RESETS to see if bit BOR was cleared, indicating a BOR occurred. The BOR bit is not predictable
if the Brown-out Reset circuitry is disabled.
The Power-on Reset Status bit, POR, is cleared on a
POR and unaffected otherwise. The user must set this
bit following a POR and check it on subsequent
RESETS to see if it has been cleared.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 103
PIC16C745/765
13.5
Time-out in Various Situations
TABLE 13-3:
RESET TIME-OUTS
POR
BOR
Oscillator
Configuration
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up
from SLEEP
HS
TPWRT + 1024TOSC
1024TOSC
TPWRT + 1024TOSC
1024TOSC
1024TOSC
H4
TPWRT + TPLLRT +
1024TOSC
TPLLRT +
1024TOSC
TPWRT + TPLLRT +
1024TOSC
TPLLRT +
1024TOSC
TPLLRT +
1024TOSC
EC
TPWRT
0
TPWRT
0
0
E4
TPWRT + TPLLRT
TPLLRT
TPWRT + TPLLRT
TPLLRT
TPLLRT
TABLE 13-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP or Interrupt Wake-up from SLEEP
TABLE 13-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
000x xuuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 13-6:
Address
REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other Resets
03h, 83h,
103h, 183h
Status
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq
---- --uu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
DS41124D-page 104
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
TABLE 13-7:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
N/A
N/A
N/A
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
0000h
0000h
PC + 1(2)
STATUS
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
--0x 0000
--0u 0000
--uu uuuu
PORTB
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
xx-- -xxx
uu-- -uuu
uu-- -uuu
PORTD(4)
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE(4)
---- -xxx
---- -uuu
---- -uuu
PCLATH
---0 0000
---0 0000
---u uuuu
INTCON
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
0000 0000
0000 0000
uuuu uuuu(1)
PIR2
---- ---0
---- ---0
---- ---u(1)
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
--00 0000
--uu uuuu
--uu uuuu
TMR2
0000 0000
0000 0000
uuuu uuuu
T2CON
-000 0000
-000 0000
-uuu uuuu
CCPR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
--00 0000
--00 0000
--uu uuuu
RCSTA
0000 -00x
0000 -00x
uuuu -uuu
TXREG
0000 0000
0000 0000
uuuu uuuu
RCREG
0000 0000
0000 0000
uuuu uuuu
CCPR2L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
0000 0000
0000 0000
uuuu uuuu
ADRES
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
1111 1111
1111 1111
uuuu uuuu
TRISA
--11 1111
--11 1111
--uu uuuu
TRISB
1111 1111
1111 1111
uuuu uuuu
TRISC
11-- -111
11-- -111
uu-- -uuu
Register
W
PCL
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 13-5 for RESET value for specific condition.
4: PIC16C765 only.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 105
PIC16C745/765
TABLE 13-7:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
TRISD(4)
1111 1111
1111 1111
uuuu uuuu
TRISE(4)
0000 -111
0000 -111
uuuu -uuu
PIE1
0000 0000
0000 0000
uuuu uuuu
PIE2
---- ---0
---- ---0
---- ---u
---- --uu
---- --uu
Register
PCON
(3)
---- --0q
PR2
1111 1111
1111 1111
1111 1111
TXSTA
0000 -010
0000 -010
uuuu -uuu
SPBRG
0000 0000
0000 0000
uuuu uuuu
ADCON1
---- -000
---- -000
---- -uuu
UIR
--00 0000
--00 0000
--00 0000
UIE
--00 0000
--00 0000
--00 0000
UEIR
0000 0000
0000 0000
0000 0000
UEIE
0000 0000
0000 0000
0000 0000
USTAT
---x xx--
---u uu--
---u uu--
UCTRL
--x0 000-
--xq qqq-
--xq qqq-
UADDR
-000 0000
-000 0000
-000 0000
USWSTAT
0000 0000
0000 0000
0000 0000
UEP0
---- 0000
---- 0000
---- 0000
UEP1
---- 0000
---- 0000
---- 0000
UEP2
---- 0000
---- 0000
---- 0000
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 13-5 for RESET value for specific condition.
4: PIC16C765 only.
DS41124D-page 106
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
13.6
Interrupts
Note:
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note:
Individual interrupt flag bits are set, regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON)
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be reenabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1.
An instruction clears the GIE bit while
an interrupt is acknowledged.
2.
The program branches to the interrupt vector and executes the Interrupt
Service Routine.
3.
The Interrupt Service Routine completes the execution of the RETFIE
instruction. This causes the GIE bit to
be set (enables interrupts), and the
program returns to the instruction
after the one which was meant to disable interrupts.
Perform the following to ensure that interrupts are globally disabled:
LOOP BCF
The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function register INTCON.
INTCON, GIE
BTFSC INTCON, GIE
GOTO
:
LOOP
; Disable global
;
interrupt bit
; Global interrupt
;
disabled?
; NO, try again
;
Yes, continue
;
with program
;
flow
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack, and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 107
PIC16C745/765
FIGURE 13-5: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON)
Interrupt Latency(2)
GIE bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC+2
Note 1:
2:
3:
4:
PC + 2
PC+2
Instruction
fetched
Instruction
executed
Inst(PC + 2)
Inst(PC + 1)
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
HS oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). This delay is not present in EC osc mode.
GIE = '1' assumed. After wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
FIGURE 13-6: INTERRUPT LOGIC
PSPIF(1)
PSPIE(1)
ADIF
ADIE
Wake-up (If in SLEEP mode)
T0IF
T0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
Interrupt to CPU
RBIF
RBIE
USBIF
USBIE
PEIE
CCP1IF
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows the interrupts for each device.
Device
T0IF
INTF
RBIF
PSPIF
ADIF
RCIF
TXIF
USBIF
CCP1IF
TMR2IF
TMR1IF
CCP2IF
PIC16C745
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C765
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note 1:
PIC16C765 only.
DS41124D-page 108
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
13.6.1
INT INTERRUPT
13.7
The external interrupt on RB0/INT pin is edge triggered: either rising, if bit INTEDG (OPTION_REG)
is set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 13.9 for details on SLEEP mode.
13.6.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit T0IF (INTCON). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON). (Section 6.0)
13.6.3
PORTB INTERRUPT ON CHANGE
An input change on PORTB sets flag bit RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON)
(Section 5.2).
Note:
Context Saving During Interrupts
During an interrupt, only the PC is saved on the stack.
At the very least, W and STATUS should be saved to
preserve the context for the interrupted program. All
registers that may be corrupted by the ISR, such as
PCLATH or FSR, should be saved.
Example 13-1 stores and restores the STATUS, W and
PCLATH registers. The register, W_TEMP, is defined in
Common RAM, the last 16 bytes of each bank that may
be accessed from any bank. The STATUS_TEMP and
PCLATH_TEMP are defined in bank 0.
The example:
a)
b)
c)
d)
e)
f)
g)
Stores the W register.
Stores the STATUS register in bank 0.
Stores the PCLATH register in bank 0.
Executes the ISR code.
Restores the PCLATH register.
Restores the STATUS register
Restores W.
Note
that
W_TEMP,
STATUS_TEMP
and
PCLATH_TEMP are defined in the common RAM area
(70h - 7Fh) to avoid register bank switching during context save and restore.
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
#define
W_TEMP
0x70
#define
STATUS_TEMP
0x71
#define
PCLATH_TEMP
0x72
org
0x04
; start at Interrupt Vector
MOVWF
W_TEMP
; Save W register
MOVF
STATUS,W
MOVWF
STATUS_TEMP
; save STATUS
MOVF
PCLATH,W
MOVWF
PCLATH_TEMP
; save PCLATH
:
(Interrupt Service Routine)
:
MOVF
PCLATH_TEMP,W
MOVWF
PCLATH
MOVF
STATUS_TEMP,W
MOVWF
STATUS
SWAPF
W_TEMP,F
;
SWAPF
W_TEMP,W
; swapf loads W without affecting STATUS flags
RETFIE
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 109
PIC16C745/765
13.8
Watchdog Timer (WDT)
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
The Watchdog Timer is a free running on-chip dedicated oscillator, which does not require any external
components. The WDT will run, even if the clock on the
OSC1/CLKIN and OSC2/CLKOUT pins of the device
has been stopped, for example, by execution of a
SLEEP instruction.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEP instruction prevents the WDT from generating a RESET, but will allow the WDT to wake the device
from SLEEP mode.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
13.8.2
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.8.1
WDT PROGRAMMING CONSIDERATIONS
WDT PERIOD
Note:
The WDT has a nominal time-out period of 18 ms
(parameter #31, TWDT). The time-out periods vary with
temperature, VDD and process variations. If longer
time-out periods are desired, a prescaler with a division
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 13-7: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
1
WDT Timer
Postscaler
M
U
X
8
8 - to - 1 MUX
PS
PSA
WDT
Enable Bit
To TMR0 MUX
(Figure 6-1)
0
1
MUX
WDT
Time-out
Note: PSA and PS are bits in the OPTION register.
TABLE 13-8:
PSA
SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits
81h,181h
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
PLL
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Value on
POR, BOR
Value on
All Other
Resets
1111 1111 1111 1111
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
DS41124D-page 110
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
13.9
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip Q clocks are present.
Power-Down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the WDT will be cleared but keeps running,
the PD bit (STATUS) is cleared, the TO (STATUS) bit is set, and the oscillator driver is turned off.
The I/O ports maintain the status they had, before the
SLEEP instruction was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
13.9.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was enabled).
Interrupt from INT pin, RB port change or some
Peripheral Interrupts.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
13.9.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
The following peripheral interrupts can wake the device
from SLEEP:
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
1.
2.
3.
4.
5.
6.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
USB interrupt.
CCP capture mode interrupt.
Parallel slave port read or write (PIC16C765
only).
A/D conversion (when A/D clock source is dedicated internal oscillator).
USART TX or RX (Synchronous Slave mode).
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 111
PIC16C745/765
FIGURE 13-8: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON)
Interrupt Latency(2)
GIE bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Note 1:
2:
3:
4:
13.10
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
13.11
Program Verification/Code Protection
Microchip does not recommend code protecting windowed devices. Devices that are
code protected may be erased, but not programmed again.
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the four least significant bits of the ID
location are used.
13.12
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
HS oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). This delay is not present in EC osc mode.
GIE = '1' assumed. After wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
PC + 2
PC+2
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After RESET, to place the device into programming/
verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending if
the command was a load or a read. For complete
details of serial programming, please refer to the
PIC16C6X/7X Programming Specifications (Literature
#DS30228).
FIGURE 13-9: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
In-Circuit Serial Programming
PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom firmware to be programmed.
External
Connector
Signals
To Normal
Connections
PIC16CXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
DS41124D-page 112
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
14.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 14-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 14-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 14-1:
OPCODE FIELD
DESCRIPTIONS
Field
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 s.
Table 14-2 lists the instructions recognized by the
MPASM assembler.
Figure 14-1 shows the general formats that the instructions can have.
Note:
0xhh
Description
where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
FIGURE 14-1: GENERAL FORMAT FOR
INSTRUCTIONS
PC
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
Top of Stack
Program Counter
PCLATH Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
dest
[ ]
Options
Contents
Assigned to
Register bit field
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
Destination either the W register or the specified
register file location
( )
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Destination select; d = 0: store result in W,
d = 1: store result in file register f. Default is d = 1
label Label name
TOS
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
f
d
The instruction set is highly orthogonal and is grouped
into three basic categories:
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
In the set of
k = 11-bit immediate value
italics User defined term (font is courier)
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 113
PIC16C745/765
TABLE 14-2:
PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PIC Mid-Range MCU Family Reference Manual (DS33023).
DS41124D-page 114
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
14.1
Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
AND W with f
Syntax:
[label] ADDLW
Syntax:
[label] ANDWF
Operands:
0 k 255
Operands:
0 f 127
d
k
f,d
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Operation:
(W) .AND. (f) (destination)
Description:
The contents of the W register
are added to the eight bit literal 'k'
and the result is placed in the W
register.
Status Affected:
Z
Description:
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[label] ADDWF
Syntax:
[label] BCF
Operands:
0 f 127
d
Operands:
0 f 127
0b7
Operation:
(W) + (f) (destination)
Operation:
0 (f)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0, the result
is stored in the W register. If 'd' is
1, the result is stored back in register 'f'.
Description:
Bit 'b' in register 'f' is cleared.
ANDLW
AND Literal with W
BSF
Bit Set f
Syntax:
[label] ANDLW
Syntax:
[label] BSF
Operands:
0 k 255
Operands:
Operation:
(W) .AND. (k) (W)
0 f 127
0b7
Status Affected:
Z
Operation:
1 (f)
Description:
The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
Status Affected:
None
Description:
Bit 'b' in register 'f' is set.
1999-2013 Microchip Technology Inc.
f,d
k
Preliminary
f,b
f,b
DS41124D-page 115
PIC16C745/765
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
Operands:
0 f 127
0b VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byPORTA, PORTB, and PORTE (Note 2) (combined) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 2) (combined) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 2) (combined) ..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 2) (combined).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
2: PORTD and PORTE not available on the PIC16C745.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 127
PIC16C745/765
FIGURE 16-1: VALID OPERATING REGIONS, FREQUENCY ON FINT,
-40°C TA +85°C
5.5 V
Voltage
5.25 V
4.35 V
4.0 V
24 MHz
Frequency
DS41124D-page 128
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
16.1
DC Characteristics:
PIC16C745/765 (Industrial)
DC CHARACTERISTICS
Param
No.
Sym
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Characteristic
Min
Typ†
Max
Units
4.35
—
5.25
V
Conditions
D001
VDD
Supply Voltage
D002*
VDR
RAM Data Retention
Voltage (Note 1)
—
1.5
—
V
D003
VPOR
VDD Start Voltage to ensure
internal Power-on Reset signal
—
VSS
—
V
D004*
SVDD
D004A*
VDD Rise Rate to ensure
internal Power-on Reset signal
0.05
TBD
—
—
—
—
D005
VBOR
Brown-out Reset
voltage trip point
3.65
—
4.35
V
D010
D013
IDD
Supply Current
(Note 2, 4)
—
—
14
18
16
20
mA
mA
FINT = 24 MHz, VDD = 4.35V
FINT = 24 MHz, VDD = 5.25V
D020
D021
D021B
IPD
Power-down Current
(Note 3, 4)
—
—
90
100
120
140
A
A
VDD = 4.35V w/ USB suspended
VDD = 5.25V w/ USB suspended
Module Differential
Current (Note 5, 6)
Watchdog Timer
Not suspend mode
Phase Lock Loop
—
—
—
6.0
40
1.5
20
180
3.0
A
A
mA
WDTE bit set, VDD = 4.35V
WDTE bit set, VDD = 4.35V
WDTE bit set, VDD = 4.35V
HS oscillator operating freq.
H4 oscillator operating freg.
EC oscillator operating freq.
E4 oscillator operating freq.
24
6
24
6
—
—
—
—
24
6
24
6
MHz
MHz
MHz
MHz
All temperatures
All temperatures
All temperatures
All temperatures
D022*
IWDT
D022A* IUSB
PLL
1A
FOSC
See Figure 16-1
See section on Power-on Reset for details
V/mS PWRT enabled (PWRTE bit clear)
V/mS PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
Brown-out Reset is always active
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current
consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is
for design guidance only. This is not tested.
5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
6: Module differential currents measured at FINT = 24 MHz.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 129
PIC16C745/765
16.2
DC Characteristics:
PIC16C745/765 (Industrial)
DC CHARACTERISTICS
Param
No.
Sym
VIL
D030
D030A
D031
D032
D033
VIH
D040
D041
D042
D042A
D043
D060
IIL
D061
D063
D070
D080
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (in EC, E4
mode)
OSC1 (in HS, H4 mode)
Input High Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR
OSC1 (HS, H4 mode)
OSC1 (in EC, E4 mode)
Input Leakage Current
(Notes 2, 3)
I/O ports
MCLR, RA4/T0CKI
OSC1
IPURB PORTB weak pull-up current
AVIH
D+ In
D- In
AVOH D+ Out
D- Out
AVIL
D+ In
D- In
AVOL D+ Out
D- Out
Output Low Voltage
VOL
I/O ports
D083
OSC2/CLKOUT (EC, E4 osc
mode)
Output High Voltage
I/O ports (Note 3)
D090
VOH
D092
OSC2/CLKOUT (EC osc
mode)
VOD
Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
COSC2 OSC2 pin
D150*
D100
Standard Operating Conditions (unless otherwise stated)
+85°C for industrial
Operating temperature
-40°C TA
Operating voltage VDD range as described in DC spec Section 16.1 and Section 16.2
Min
Typ†
Max
Units
Conditions
VSS
—
0.8
V
VSS
VSS
—
—
0.2 VDD
0.2 VDD
V
V
For entire VDD range
VSS
—
0.3 VDD
V
Note 1
2.0
0.8 VDD
0.8 VDD
0.7 VDD
0.9 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
—
—
1
A
—
—
—
—
5
5
A
A
50
2.4
2.4
2.8
2.8
—
—
—
—
250
—
—
—
—
—
—
—
—
400
—
—
3.6
3.6
.8
.8
.3
.3
A
V
V
V
V
V
V
V
V
—
—
0.6
V
—
—
0.6
V
VDD-0.7
V
VDD-0.7
V
10.5
V
15
pF
For entire VDD range
Note 1
VSS VPIN VDD,
Pin at hi-impedance
VSS VPIN VDD
VSS VPIN VDD,
HS osc mode
VDD = 5V, VPIN = VSS
VDD = 4.35V w/ USB suspended (Note 4)
VDD = 4.35V w/ USB suspended
VDD = 4.35V w/ USB suspended (Note 4)
VDD = 4.35V w/ USB suspended
VDD = 4.35V w/ USB suspended (Note 4)
VDD = 4.35V w/ USB suspended
VDD = 4.35V w/ USB suspended (Note 4)
VDD = 4.35V w/ USB suspended
IOL = 8.5 mA, VDD = 4.35V,
-40C to +85C
IOL = 1.6 mA, VDD = 4.35V,
-40C to +85C
IOH = -3.0 mA, VDD = 4.35V,
-40C to +85C
IOH = -1.3 mA, VDD = 4.35V,
-40C to +85C
RA4 pin
In HS mode when external clock is used
to drive OSC1.
All I/O pins and OSC2 (in EC
50
pF
mode)
CVUSB VUSB regulation capacitor
200
nF
+ 20% (See Section 10.7.1)
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameters are per USB Specification 1.1. No Microchip specific parameter numbers exist (per the PIC Mid-Range Reference Manual, DS33023.
D101
CIO
DS41124D-page 130
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
16.3
AC (Timing) Characteristics
16.3.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
osc
OSC1
ck
CLKOUT
rd
RD
cs
CS
rw
RD or WR
di
SDI
sc
SCK
do
SDO
ss
SS
dt
Data in
t0
T0CKI
io
I/O port
t1
T1CKI
mc
MCLR
wr
WR
Uppercase letters and their meanings:
S
F
Fall
P
Period
H
High
R
Rise
I
Invalid (Hi-impedance)
V
Valid
L
Low
Z
Hi-impedance
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 131
PIC16C745/765
16.3.2
TIMING CONDITIONS
The temperature and voltages specified in Table 16-1
apply to all timing specifications unless otherwise
noted. Figure 16-2 specifies the load conditions for the
timing specifications.
TABLE 16-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Operating voltage VDD range as described in DC spec Section 16.1 and
Section 16.2.
FIGURE 16-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464
CL = 50 pF
for all pins except OSC2/CLKOUT,
but including D and E(1)
outputs as ports
CL = 15 pF
for OSC2 output
Note 1: PIC16C765 only.
DS41124D-page 132
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
16.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 16-3: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
FIGURE 16-4: CLOCK MULTIPLIER (PLL) PHASE RELATIONSHIP
OSC1/
CLKIN
FINT
Note 1: FINT represents the internal clock signal. FINT equals FOSC or CLKIN if the PLL is disabled. FINT
equals 4x FOSC or 4x CLKIN if the PLL is enabled. TCY is always 4/FINT. FINT is OSC1 pin in EC
mode, PLL disabled.
2: FINT = OSC1 in EC mode with PLL disabled.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 133
PIC16C745/765
TABLE 16-2:
EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
1A
FOSC
1
TOSC
Min
Typ†
External CLKIN Frequency
(Note 1)
24
—
24
MHz
EC osc mode
6
—
6
MHz
E4 osc mode
Oscillator Frequency
(Note 1)
24
—
24
MHz
HS osc mode
6
—
6
MHz
H4 osc mode
External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
Max
Units
Conditions
41
—
41
ns
EC osc modes
167
—
167
ns
E4 osc mode
41
—
41
ns
HS osc modes
167
—
167
ns
H4 osc mode
2
TCY
Instruction Cycle Time (Note 1)
167
—
DC
ns
TCY = 4/FINT
3*
TOSL,
TOSH
External Clock in (OSC1) High or Low
Time
10
—
—
ns
EC oscillator
4*
TOSR,
TOSF
External Clock in (OSC1) Rise or Fall
Time
—
—
15
ns
EC oscillator
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period when the PLL is enabled, or the input
oscillator time-base period divided by 4 when the PLL is disabled. All specified values are based on characterization data
for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these
specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices
are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input
is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
DS41124D-page 134
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
FIGURE 16-5: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
FINT
11
10
CLKOUT
13
12
19
14
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
10*
TOSH2CKL
OSC1 to CLKOUT
—
75
200
ns
Note 1
11*
TOSH2CKH
OSC1 to CLKOUT
—
75
200
ns
Note 1
12*
TCKR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TCKF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TCKL2IOV
CLKOUT to Port out valid
—
—
0.5 TCY + 20
ns
Note 1
15*
TIOV2CKH
Port in valid before CLKOUT
TOSC + 200
—
—
ns
Note 1
16*
TCKH2IOI
Port in hold after CLKOUT
0
—
—
ns
Note 1
17*
TOSH2IOV
OSC1 (Q1 cycle) to Port out valid
—
50
150
ns
18*
TOSH2IOI
OSC1 (Q2 cycle) to Port input invalid (I/O in hold
time)
100
—
—
ns
19*
TIOV2OSH
Port input valid to OSC1(I/O in setup time)
0
—
—
ns
20*
TIOR
Port output rise time
—
10
40
ns
21*
TIOF
Port output fall time
—
10
40
ns
22††*
TINP
INT pin high or low time
TCY
—
—
ns
23††*
TRBP
RB change INT high or low time
TCY
—
—
ns
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
2: FINT = OSC1 when PLL is disabled.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 135
PIC16C745/765
FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 16-2 for load conditions.
FIGURE 16-7: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 16-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
—
—
s
VDD = 5V, -40°C to +85°C
31*
TWDT
Watchdog Timer Time-out
Period (No Prescaler)
7
18
33
ms
VDD = 5V, -40°C to +85°C
32
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
TPWRT
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +85°C
34
TIOZ
I/O Hi-impedance from MCLR
Low or WDT Reset
—
—
2.1
s
35
TBOR
Brown-out Reset Pulse Width
100
—
—
s
VDD BVDD (D005)
36
TPLLRT
PLL Settling Time Period
—
1.4
—
ms
TOSC = OSC1 period
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41124D-page 136
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
FIGURE 16-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-5:
Param
No.
40*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Sym
TT0H
Characteristic
T0CKI High Pulse Width No Prescaler
With Prescaler
41*
TT0L
T0CKI Low Pulse Width No Prescaler
42*
TT0P
T0CKI Period
With Prescaler
46*
TT1H
TT1L
T1CKI High Time
T1CKI Low Time
—
—
ns
10
—
—
ns
0.5 TCY + 20
—
—
ns
—
—
ns
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
0.5 TCY + 20
—
—
ns
Synchronous,
Prescaler = 2,4,8
15
—
—
ns
Asynchronous
30
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
Synchronous, Prescaler = 1
Synchronous, Prescaler = 1
Asynchronous
30
—
—
ns
Synchronous
Greater of:
30 or TCY + 40
N
—
—
ns
TT1P
T1CKI input period
FT1
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
Asynchronous
48
0.5 TCY + 20
10
Synchronous,
Prescaler = 2,4,8
47*
Typ† Max Units
TCY + 40
No Prescaler
With Prescaler
45*
Min
TCKEZTMR1 Delay from external clock edge to timer increment
60
—
—
ns
DC
—
200
kHz
2Tosc
—
7Tosc
—
Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 137
PIC16C745/765
FIGURE 16-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
CCPx
(Compare or PWM Mode)
53
54
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-6:
Param
No.
Sym
50*
TCCL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Characteristic
CCP1 and CCP2
input low time
No Prescaler
With Prescaler
51*
TCCH
CCP1 and CCP2
input high time
No Prescaler
With Prescaler
Min
Typ†
Max
Units
0.5 TCY + 20
—
—
ns
10
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
3 TCY + 40
N
—
—
ns
52*
TCCP
CCP1 and CCP2 input period
53*
TCCR
CCP1 and CCP2 output rise time
—
10
25
ns
54*
TCCF
CCP1 and CCP2 output fall time
—
10
25
ns
Conditions
N = prescale
value (1,4, or 16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41124D-page 138
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
FIGURE 16-10: PARALLEL SLAVE PORT TIMING (PIC16C765)
RE2/CS
RE0/RD
RE1/WR
65
RD
62
64
63
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-7:
Param No.
PARALLEL SLAVE PORT REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
62*
TDTV2WRH Data in valid before WR or CS (setup time)
20
—
—
ns
63*
TWRH2DTI
WR or CS to data–in invalid (hold time)
20
—
—
ns
64
TRDL2DTV
RD and CS to data–out valid
—
—
80
ns
65*
TRDH2DTI
RD or CS to data–out invalid
10
—
30
ns
Conditions
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: PIC16C765 only.
1999-2013 Microchip Technology Inc.
Preliminary
DS41124D-page 139
PIC16C745/765
FIGURE 16-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-8:
Param
No.
USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
120*
TCKH2DTV
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
—
—
80
ns
121*
TCKRF
Clock out rise time and fall time (Master mode)
—
—
45
ns
122*
TDTRF
Data out rise time and fall time
—
—
45
ns
Conditions
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 16-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK pin
125
RC7/RX/DT pin
126
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-9:
Param
No.
USART SYNCHRONOUS RECEIVE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
125*
TDTV2CKL
SYNC RCV (MASTER & SLAVE)
Data setup before CK (DT setup time)
15
—
—
ns
126*
TCKL2DTL
Data hold after CK (DT hold time)
15
—
—
ns
Conditions
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41124D-page 140
Preliminary
1999-2013 Microchip Technology Inc.
PIC16C745/765
TABLE 16-10: A/D CONVERTER CHARACTERISTICS: PIC16C745/765 (INDUSTRIAL)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
8 bits
bit
A02
EABS
Total Absolute error
—
—
工商网监
湘ICP备2023018690号
