PIC16C925/926
64/68-Pin CMOS Microcontrollers with LCD Driver
High Performance RISC CPU:
Analog Features:
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14-bit words of EPROM program memory,
336 bytes general purpose registers (SRAM),
60 special function registers
• Pinout compatible with PIC16C923/924
• 10-bit 5-channel Analog-to-Digital Converter (A/D)
• Brown-out Reset (BOR)
Peripheral Features:
• 25 I/O pins with individual direction control and
25-27 input only pins
• Timer0 module: 8-bit timer/counter with programmable 8-bit prescaler
• Timer1 module: 16-bit timer/counter, can be incremented during SLEEP via external crystal/clock
• Timer2 module: 8-bit timer/counter with 8-bit
period register, prescaler, and postscaler
• One Capture, Compare, PWM module
• Synchronous Serial Port (SSP) module with
two modes of operation:
- 3-wire SPI (supports all 4 SPI modes)
- I2C™ Slave mode
• Programmable LCD timing module:
- Multiple LCD timing sources available
- Can drive LCD panel while in SLEEP mode
- Static, 1/2, 1/3, 1/4 multiplex
- Static drive and 1/3 bias capability
- 16 bytes of dedicated LCD RAM
- Up to 32 segments, up to 4 commons
Common
Segment
Pixels
1
2
3
4
32
31
30
29
32
62
90
116
2001-2013 Microchip Technology Inc.
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Selectable oscillator options
• In-Circuit Serial Programming™ (ICSP™) via
two pins
• Processor read access to program memory
CMOS Technology:
• Low power, high speed CMOS/EPROM
technology
• Fully static design
• Wide operating voltage range: 2.5V to 5.5V
• Commercial and Industrial temperature ranges
• Low power consumption
Preliminary
DS39544B-page 1
PIC16C925/926
Pin Diagrams
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
RA3/AN3/VREF+
RA2/AN2/VREFVSS
RA1/AN1
RA0/AN0
RB2
RB3
MCLR/VPP
N/C
RB4
RB5
RB7
RB6
VDD
COM0
RD7/SEG31/COM1
RD6/SEG30/COM2
PLCC, CLCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIC16C92X
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
RD5/SEG29/COM3
RG6/SEG26
RG5/SEG25
RG4/SEG24
RG3/SEG23
RG2/SEG22
RG1/SEG21
RG0/SEG20
RG7/SEG28
RF7/SEG19
RF6/SEG18
RF5/SEG17
RF4/SEG16
RF3/SEG15
RF2/SEG14
RF1/SEG13
RF0/SEG12
RC1/T1OSI
RC2/CCP1
VLCD1
VLCDADJ
RD0/SEG00
RD1/SEG01
RD2/SEG02
RD3/SEG03
RD4/SEG04
RE7/SEG27
RE0/SEG05
RE1/SEG06
RE2/SEG07
RE3/SEG08
RE4/SEG09
RE5/SEG10
RE6/SEG11
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
RA4/T0CKI
RA5/AN4/SS
RB1
RB0/INT
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
C1
C2
VLCD2
VLCD3
AVDD
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
LEGEND:
Input Pin
Output Pin
Input/Output Pin
Digital Input/LCD Output Pin
LCD Output Pin
DS39544B-page 2
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RA3/AN3/VREF+
RA2/AN2/VREFVSS
RA1/AN1
RA0/AN0
RB2
RB3
MCLR/VPP
RB4
RB5
RB7
RB6
VDD
COM0
RD7/SEG31/COM1
RD6/SEG30/COM2
TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC16C92X
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RD5/SEG29/COM3
RG6/SEG26
RG5/SEG25
RG4/SEG24
RG3/SEG23
RG2/SEG22
RG1/SEG21
RG0/SEG20
RF7/SEG19
RF6/SEG18
RF5/SEG17
RF4/SEG16
RF3/SEG15
RF2/SEG14
RF1/SEG13
RF0/SEG12
RC1/T1OSI
RC2/CCP1
VLCD1
VLCDADJ
RD0/SEG00
RD1/SEG01
RD2/SEG02
RD3/SEG03
RD4/SEG04
RE0/SEG05
RE1/SEG06
RE2/SEG07
RE3/SEG08
RE4/SEG09
RE5/SEG10
RE6/SEG11
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RA4/T0CKI
RA5/AN4/SS
RB1
RB0/INT
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
C1
C2
VLCD2
VLCD3
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
LEGEND:
Input Pin
Output Pin
Input/Output Pin
Digital Input/LCD Output Pin
LCD Output Pin
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 3
PIC16C925/926
Table of Contents
1.0 Device Overview ................................................................................................................................................... 5
2.0 Memory Organization .......................................................................................................................................... 11
3.0 Reading Program Memory .................................................................................................................................. 27
4.0 I/O Ports .............................................................................................................................................................. 29
5.0 Timer0 Module .................................................................................................................................................... 41
6.0 Timer1 Module .................................................................................................................................................... 47
7.0 Timer2 Module .................................................................................................................................................... 51
8.0 Capture/Compare/PWM (CCP) Module .............................................................................................................. 53
9.0 Synchronous Serial Port (SSP) Module .............................................................................................................. 59
10.0 Analog-to-Digital Converter (A/D) Module ........................................................................................................... 75
11.0 LCD Module ........................................................................................................................................................ 83
12.0 Special Features of the CPU............................................................................................................................... 97
13.0 Instruction Set Summary ................................................................................................................................... 113
14.0 Development Support ....................................................................................................................................... 133
15.0 Electrical Characteristics ................................................................................................................................... 139
16.0 DC and AC Characteristics Graphs and Tables ................................................................................................ 159
17.0 Packaging Information ...................................................................................................................................... 161
Appendix A: Revision History.................................................................................................................................... 167
Appendix B: Device Differences ............................................................................................................................... 167
Appendix C: Conversion Considerations .................................................................................................................. 168
Index .......................................................................................................................................................................... 169
On-Line Support ......................................................................................................................................................... 175
Reader Response ...................................................................................................................................................... 176
PIC16C925/926 Product Identification System .......................................................................................................... 177
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS39544B-page 4
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
1.0
DEVICE OVERVIEW
These devices come in 64-pin and 68-pin packages, as
well as die form. Both configurations offer identical
peripheral devices and other features. The only difference between the DSTEMP and DSTEMP is the additional EPROM and data memory offered in the latter.
An overview of features is presented in Table 1-1.
This document contains device-specific information for
the following devices:
1.
2.
PIC16C925
PIC16C926
The PIC16C925/926 series is a family of low cost, high
performance, CMOS, fully static, 8-bit microcontrollers
with an integrated LCD Driver module, in the
PIC16CXXX mid-range family.
A UV-erasable, CERQUAD packaged version (compatible with PLCC) is also available for both the
PIC16C925 and PIC16C926. This version is ideal for
cost effective code development.
For the PIC16C925/926 family, there are two device
“types” as indicated in the device number:
A block diagram for the PIC16C925/926 family architecture is presented in Figure 1-1.
1.
2.
C, as in PIC16C926. These devices operate
over the standard voltage range.
LC, as in PIC16LC926. These devices operate
over an extended voltage range.
TABLE 1-1:
PIC16C925/926 DEVICE FEATURES
Features
PIC16C925
PIC16C926
Operating Frequency
DC-20 MHz
DC-20 MHz
EPROM Program Memory (words)
4K
8K
Data Memory (bytes)
176
336
Timer Module(s)
TMR0,TMR1,TMR2
TMR0,TMR1,TMR2
Capture/Compare/PWM Module(s)
1
1
Serial Port(s)
(SPI/I2C, USART)
SPI/I2C
SPI/I2C
Parallel Slave Port
—
—
A/D Converter (10-bit) Channels
5
5
LCD Module
4 Com, 32 Seg
4 Com, 32 Seg
Interrupt Sources
9
9
I/O Pins
25
25
Input Pins
27
27
Voltage Range (V)
2.5-5.5
2.5-5.5
In-Circuit Serial Programming
Yes
Yes
Brown-out Reset
Yes
Yes
Packages
64-pin TQFP
68-pin PLCC
68-pin CLCC (CERQUAD)
Die
64-pin TQFP
68-pin PLCC
68-pin CLCC (CERQUAD)
Die
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 5
PIC16C925/926
FIGURE 1-1:
PIC16C925/926 BLOCK DIAGRAM
13
8
Data Bus
Program Counter
PORTA
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
EPROM
Program
Memory
Program
Bus
RAM
8 Level Stack
(13-bit)
14
File
Registers
RAM Addr
PORTB
9
Addr MUX
Instruction reg
RB0/INT
7
Direct Addr
8
Indirect
Addr
RB1-RB7
FSR reg
STATUS reg
8
3
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
Power-on
Reset
Timing
Generation
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
MUX
ALU
PORTD
8
Watchdog
Timer
W reg
RD0-RD4/SEGnn
OSC1/CLKIN
OSC2/CLKOUT
RD5-RD7/SEGnn/COMn
MCLR
VDD, VSS
PORTE
RE0-RE7/SEGnn
PORTF
RF0-RF7/SEGnn
PORTG
RG0-RG7/SEGnn
Timer0
A/D
Timer1, Timer2,
CCP1
Synchronous
Serial Port
LCD
DS39544B-page 6
Preliminary
COM0
VLCD1
VLCD2
VLCD3
C1
C2
VLCDADJ
2001-2013 Microchip Technology Inc.
PIC16C925/926
TABLE 1-2:
PIC16C925/926 PINOUT DESCRIPTION
PLCC,
CLCC
Pin#
TQFP
Pin#
Pin
Type
Buffer
Type
OSC1/CLKIN
24
14
I
ST/CMOS
OSC2/CLKOUT
25
15
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT, which has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
MCLR/VPP
2
57
I/P
ST
Master Clear (Reset) input or programming voltage input. This
pin is an active low RESET to the device.
RA0/AN0
5
60
I/O
TTL
RA0 can also be Analog input0.
RA1/AN1
6
61
I/O
TTL
RA1 can also be Analog input1.
RA2/AN2
8
63
I/O
TTL
RA2 can also be Analog input2.
RA3/AN3/VREF
9
64
I/O
TTL
RA3 can also be Analog input3 or A/D Voltage
Reference.
RA4/T0CKI
10
1
I/O
ST
RA4 can also be the clock input to the Timer0
timer/counter. Output is open drain type.
RA5/AN4/SS
11
2
I/O
TTL
RA5 can be the slave select for the synchronous serial port
or Analog input4.
Pin Name
Description
Oscillator crystal input or external clock source input. This
buffer is a Schmitt Trigger input when configured in RC
oscillator mode and a CMOS input otherwise.
PORTA is a bi-directional I/O port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT
13
4
I/O
TTL/ST
RB0 can also be the external interrupt pin. This buffer is a
Schmitt Trigger input when configured as an
external interrupt.
RB1
12
3
I/O
TTL
RB2
4
59
I/O
TTL
RB3
3
58
I/O
TTL
RB4
68
56
I/O
TTL
Interrupt-on-change pin.
RB5
67
55
I/O
TTL
Interrupt-on-change pin.
RB6
65
53
I/O
TTL/ST
Interrupt-on-change pin. Serial programming clock. This
buffer is a Schmitt Trigger input when used in Serial
Programming mode.
RB7
66
54
I/O
TTL/ST
Interrupt-on-change pin. Serial programming data. This
buffer is a Schmitt Trigger input when used in Serial
Programming mode.
RC0/T1OSO/T1CKI
26
16
I/O
ST
PORTC is a bi-directional I/O port.
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI
27
17
I/O
ST
RC1 can also be the Timer1 oscillator input.
RC2/CCP1
28
18
I/O
ST
RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL
14
5
I/O
ST
RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA
15
6
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
16
7
I/O
ST
C1
17
8
P
C2
18
9
P
LCD Voltage Generation.
COM0
63
51
L
Common Driver0.
Legend: I = input
— = Not used
O = output
TTL = TTL input
2001-2013 Microchip Technology Inc.
RC5 can also be the SPI Data Out (SPI mode).
LCD Voltage Generation.
P = power
L = LCD Driver
ST = Schmitt Trigger input
Preliminary
DS39544B-page 7
PIC16C925/926
TABLE 1-2:
PIC16C925/926 PINOUT DESCRIPTION (CONTINUED)
Pin Name
PLCC,
CLCC
Pin#
TQFP
Pin#
Pin
Type
Buffer
Type
Description
PORTD is a digital input/output port. These pins are also used
as LCD Segment and/or Common Drivers.
RD0/SEG00
31
21
I/O/L
ST
Segment Driver 00/Digital input/output.
RD1/SEG01
32
22
I/O/L
ST
Segment Driver 01/Digital input/output.
RD2/SEG02
33
23
I/O/L
ST
Segment Driver 02/Digital input/output.
RD3/SEG03
34
24
I/O/L
ST
Segment Driver 03/Digital input/output.
RD4/SEG04
35
25
I/O/L
ST
Segment Driver04/Digital input/output.
RD5/SEG29/COM3
60
48
I/L
ST
Segment Driver29/Common Driver 3/Digital input.
RD6/SEG30/COM2
61
49
I/L
ST
Segment Driver30/Common Driver 2/Digital input.
RD7/SEG31/COM1
62
50
I/L
ST
Segment Driver31/Common Driver 1/Digital input.
PORTE is a Digital input or LCD Segment Driver port.
RE0/SEG05
37
26
I/L
ST
Segment Driver 05.
RE1/SEG06
38
27
I/L
ST
Segment Driver 06.
RE2/SEG07
39
28
I/L
ST
Segment Driver 07.
RE3/SEG08
40
29
I/L
ST
Segment Driver 08.
RE4/SEG09
41
30
I/L
ST
Segment Driver 09.
RE5/SEG10
42
31
I/L
ST
Segment Driver 10.
RE6/SEG11
43
32
I/L
ST
Segment Driver 11.
RE7/SEG27
36
-
I/L
ST
Segment Driver 27 (not available on 64-pin devices).
RF0/SEG12
44
33
I/L
ST
Segment Driver 12.
RF1/SEG13
45
34
I/L
ST
Segment Driver 13.
RF2/SEG14
46
35
I/L
ST
Segment Driver 14.
RF3/SEG15
47
36
I/L
ST
Segment Driver 15.
RF4/SEG16
48
37
I/L
ST
Segment Driver 16.
RF5/SEG17
49
38
I/L
ST
Segment Driver 17.
RF6/SEG18
50
39
I/L
ST
Segment Driver 18.
RF7/SEG19
51
40
I/L
ST
PORTF is a Digital input or LCD Segment Driver port.
Segment Driver 19.
PORTG is a Digital input or LCD Segment Driver port.
RG0/SEG20
53
41
I/L
ST
Segment Driver 20.
RG1/SEG21
54
42
I/L
ST
Segment Driver 21.
RG2/SEG22
55
43
I/L
ST
Segment Driver 22.
RG3/SEG23
56
44
I/L
ST
Segment Driver 23.
RG4/SEG24
57
45
I/L
ST
Segment Driver 24.
RG5/SEG25
58
46
I/L
ST
Segment Driver 25.
RG6/SEG26
59
47
I/L
ST
Segment Driver 26.
RG7/SEG28
52
—
I/L
ST
Segment Driver 28 (not available on 64-pin devices).
VLCDADJ
30
20
P
—
LCD Voltage Generation.
AVDD
21
—
P
—
Analog Power (PLCC and CLCC packages only).
LCD Voltage.
VLCD1
29
19
P
—
VLCD2
19
10
P
—
LCD Voltage.
VLCD3
20
11
P
—
LCD Voltage.
VDD
22, 64
12, 52
P
—
Digital power.
VSS
7, 23
13, 62
P
—
Ground reference.
NC
1
—
—
—
These pins are not internally connected. These pins should be
left unconnected.
Legend: I = input
— = Not used
DS39544B-page 8
O = output
TTL = TTL input
P = power
L = LCD Driver
ST = Schmitt Trigger input
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
1.1
Clocking Scheme/Instruction
Cycle
1.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 1-1).
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 1-2.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3,
and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 1-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 1-1:
1. MOVLW 55h
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3 (Forced NOP)
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 9
PIC16C925/926
NOTES:
DS39544B-page 10
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
2.0
MEMORY ORGANIZATION
2.1
Program Memory Organization
The PIC16C925/926 family has a 13-bit program counter capable of addressing an 8K x 14 program memory
space.
For the PIC16C925, only the first 4K x 14 (0000h0FFFh) are physically implemented. Accessing a location above the physically implemented addresses will
cause a wraparound. The RESET vector is at 0000h
and the interrupt vector is at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR DSTEMP
FIGURE 2-2:
PC
PC
CALL, RETURN
RETFIE, RETLW
On-chip
Program
Memory
PROGRAM MEMORY MAP
AND STACK FOR DSTEMP
CALL, RETURN
RETFIE, RETLW
13
13
Stack Level 1
Stack Level 1
Stack Level 2
Stack Level 2
Stack Level 8
Stack Level 8
RESET Vector
0000h
Interrupt Vector
0004h
0005h
RESET Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
Page 0
07FFh
0800h
Page 1
0FFFh
1000h
07FFh
0800h
On-chip
Program
Memory
Reads
0000h-0FFFh
Page 1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
ID Locations
1FFFh
2000h
2003h
Reserved
2004h
Configuration Word
2007h
ID Locations
Reserved
Configuration Word
Reserved
Reserved
1FFFh
2000h
2003h
2004h
2007h
3FFFh
3FFFh
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 11
PIC16C925/926
2.2
2.2.1
Data Memory Organization
The data memory is partitioned into four banks which
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 and RP0 are the bank
select bits.
RP1:RP0
(STATUS)
Bank
11
3 (180h-1FFh)
10
2 (100h-17Fh)
01
1 (80h-FFh)
00
0 (00h-7Fh)
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or indirectly through the File Select Register FSR
(Section 2.6).
The following General Purpose Registers are not physically implemented:
• F0h-FFh of Bank 1
• 170h-17Fh of Bank 2
• 1F0h-1FFh of Bank 3
These locations are used for common access across
banks.
The lower locations of each Bank are reserved for the
Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. All four banks contain special
function registers. Some “high use” special function
registers are mirrored in other banks for code reduction
and quicker access.
DS39544B-page 12
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 2-3:
REGISTER FILE MAP — DSTEMP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
Indirect addr.(*) 80h
OPTION
81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
TRISD
88h
TRISE
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
8Dh
PCON
8Eh
8Fh
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
ADCON1
9Fh
A0h
File
Address
File
Address
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
PORTF
108h
PORTG
109h
10Ah
PCLATH
10Bh
INTCON
PMCON1
10Ch
10Dh
LCDSE
10Eh
LCDPS
10Fh
LCDCON
110h
LCDD00
111h
LCDD01
112h
LCDD02
113h
LCDD03
114h
LCDD04
115h
LCDD05
116h
LCDD06
117h
LCDD07
118h
LCDD08
119h
LCDD09
11Ah
LCDD10
11Bh
LCDD11
11Ch
LCDD12
11Dh
LCDD13
11Eh
LCDD14
11Fh
LCDD15
120h
Indirect addr.(*)
OPTION
PCL
STATUS
FSR
TRISB
TRISF
TRISG
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
General
Purpose
Register
EFh
accesses
70h - 7Fh
7Fh
Bank 0
F0h
accesses
70h - 7Fh
1EFh
accesses
70h - 7Fh
17Fh
FFh
Bank 2
Bank 1
16Fh
170h
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as '0'.
* Not a physical register.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 13
PIC16C925/926
FIGURE 2-4:
REGISTER FILE MAP— DSTEMP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
Indirect addr.(*) 80h
OPTION
81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
TRISD
88h
TRISE
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
8Dh
PCON
8Eh
8Fh
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
ADCON1
9Fh
A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
96 Bytes
accesses
70h - 7Fh
7Fh
Bank 0
BFh
C0h
EFh
F0h
File
Address
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
PORTF
108h
PORTG
109h
10Ah
PCLATH
10Bh
INTCON
PMCON1
10Ch
10Dh
LCDSE
10Eh
LCDPS
10Fh
LCDCON
110h
LCDD00
111h
LCDD01
112h
LCDD02
113h
LCDD03
114h
LCDD04
115h
LCDD05
116h
LCDD06
117h
LCDD07
118h
LCDD08
119h
LCDD09
11Ah
LCDD10
11Bh
LCDD11
11Ch
LCDD12
11Dh
LCDD13
11Eh
LCDD14
11Fh
LCDD15
120h
General
Purpose
Register
80 Bytes
accesses
70h - 7Fh
Indirect addr.(*)
OPTION
PCL
STATUS
FSR
TRISB
TRISF
TRISG
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
Bank 2
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
80 Bytes
16Fh
170h
accesses
70h - 7Fh
17Fh
FFh
Bank 1
File
Address
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as '0'.
* Not a physical register.
DS39544B-page 14
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
2.3
Special Function Registers
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.
TABLE 2-1:
Address
Name
The special function registers can be classified into two
sets, core and peripheral. Those registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Details on
page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
26
01h
TMR0
Timer0 Module Register
xxxx xxxx
41
02h
PCL
Program Counter (PC) Least Significant Byte
03h
STATUS
04h
FSR
05h
PORTA
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
0000 0000
25
0001 1xxx
19
xxxx xxxx
26
--0x 0000
29
xxxx xxxx
31
--xx xxxx
33
06h
PORTB
07h
PORTC
08h
PORTD
PORTD Data Latch when written: PORTD pins when read
0000 0000
34
09h
PORTE
PORTE pins when read
0000 0000
36
—
—
PORTC Data Latch when written: PORTC pins when read
0Ah
PCLATH
—
—
—
---0 0000
25
0Bh
INTCON
GIE
PEIE
TMR0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
00-- 0000
23
0Dh
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
10h
T1CON
11h
TMR2
12h
T2CON
Unimplemented
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Timer2 Module Register
—
TOUTPS3
TOUTPS2
TOUTPS1 TOUTPS0
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
SSPOV
SSPEN
CKP
SSPM3
—
xxxx xxxx
47
xxxx xxxx
47
--00 0000
47
0000 0000
51
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
52
xxxx xxxx
64, 72
SSPM2
SSPM1
SSPM0
0000 0000
60
xxxx xxxx
58
xxxx xxxx
58
--00 0000
53
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
—
16h
CCPR1H
17h
CCP1CON
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
xxxx xxxx
80, 81
0000 0000
75
1Eh
ADRESH
1Fh
ADCON0
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
A/D Result Register High
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 15
PIC16C925/926
TABLE 2-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Details on
page
Bank 1
80h
INDF
81h
OPTION
82h
PCL
83h
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
0000 0000
26
PSA
PS2
PS1
PS0
1111 1111
20
0000 0000
25
PD
Z
DC
C
0001 1xxx
19
xxxx xxxx
26
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
84h
FSR
85h
TRISA
86h
TRISB
87h
TRISC
88h
TRISD
PORTD Data Direction Register
PORTE Data Direction Register
TO
Indirect Data Memory Address Pointer
—
—
PORTA Data Direction Register
PORTB Data Direction Register
—
—
PORTC Data Direction Register
89h
TRISE
8Ah
PCLATH
—
—
—
8Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
8Dh
—
8Eh
PCON
8Fh
—
90h
—
91h
—
Write Buffer for the upper 5 bits of the PC
--11 1111
29
1111 1111
31
--11 1111
33
1111 1111
34
1111 1111
36
---0 0000
25
RBIF
0000 000x
21
TMR1IE
00-- 0000
24
Unimplemented
—
—
---- --0-
24
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
1111 1111
51
—
—
—
—
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
94h
SSPSTAT
SMP
CKE
D/A
P
—
S
—
R/W
POR
UA
BOR
BF
0000 0000
69, 72
0000 0000
59
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
xxxx xxxx
79
---- -000
76
9Eh
ADRESL
9Fh
ADCON1
A/D Result Register Low
—
—
—
—
—
PCFG2
PCFG1
PCFG0
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
DS39544B-page 16
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
TABLE 2-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Details on
page
Bank 2
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
26
101h
TMR0
Timer0 Module Register
xxxx xxxx
41
Program Counter (PC) Least Significant Byte
102h
PCL
103h
STATUS
104h
FSR
105h
106h
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
PORTB
Unimplemented
PORTB Data Latch when written: PORTB pins when read
0000 0000
25
0001 1xxx
19
xxxx xxxx
26
—
—
xxxx xxxx
31
107h
PORTF
PORTF pins when read
0000 0000
37
108h
PORTG
PORTG pins when read
0000 0000
38
109h
—
Unimplemented
—
—
25
—
—
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21
PMCON1
reserved
—
—
—
—
—
—
RD
1--- ---0
27
PCLATH
10Bh
10Ch
Write Buffer for the upper 5 bits of the PC
---0 0000
—
10Ah
10Dh
LCDSE
SE29
SE27
SE20
SE16
SE12
SE9
SE5
SE0
1111 1111
94
10Eh
LCDPS
—
—
—
—
LP3
LP2
LP1
LP0
---- 0000
84
10Fh
LCDCON
LCDEN
SLPEN
—
VGEN
CS1
CS0
LMUX1
LMUX0
00-0 0000
83
110h
LCDD00
SEG07
COM0
SEG06
COM0
SEG05
COM0
SEG04
COM0
SEG03
COM0
SEG02
COM0
SEG01
COM0
SEG00
COM0
xxxx xxxx
92
111h
LCDD01
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG09
COM0
SEG08
COM0
xxxx xxxx
92
112h
LCDD02
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
xxxx xxxx
92
113h
LCDD03
SEG31
COM0
SEG30
COM0
SEG29
COM0
SEG28
COM0
SEG27
COM0
SEG26
COM0
SEG25
COM0
SEG24
COM0
xxxx xxxx
92
114h
LCDD04
SEG07
COM1
SEG06
COM1
SEG05
COM1
SEG04
COM1
SEG03
COM1
SEG02
COM1
SEG01
COM1
SEG00
COM1
xxxx xxxx
92
115h
LCDD05
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG09
COM1
SEG08
COM1
xxxx xxxx
92
116h
LCDD06
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
xxxx xxxx
92
117h
LCDD07
SEG31
COM1(1)
SEG30
COM1
SEG29
COM1
SEG28
COM1
SEG27
COM1
SEG26
COM1
SEG25
COM1
SEG24
COM1
xxxx xxxx
92
118h
LCDD08
SEG07
COM2
SEG06
COM2
SEG05
COM2
SEG04
COM2
SEG03
COM2
SEG02
COM2
SEG01
COM2
SEG00
COM2
xxxx xxxx
92
119h
LCDD09
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG09
COM2
SEG08
COM2
xxxx xxxx
92
11Ah
LCDD10
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
xxxx xxxx
92
11Bh
LCDD11
SEG31
COM2(1)
SEG30
COM2(1)
SEG29
COM2
SEG28
COM2
SEG27
COM2
SEG26
COM2
SEG25
COM2
SEG24
COM2
xxxx xxxx
92
11Ch
LCDD12
SEG07
COM3
SEG06
COM3
SEG05
COM3
SEG04
COM3
SEG03
COM3
SEG02
COM3
SEG01
COM3
SEG00
COM3
xxxx xxxx
92
11Dh
LCDD13
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG09
COM3
SEG08
COM3
xxxx xxxx
92
11Eh
LCDD14
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
xxxx xxxx
92
11Fh
LCDD15
SEG31
COM3(1)
SEG30
COM3(1)
SEG29
COM3(1)
SEG28
COM3
SEG27
COM3
SEG26
COM3
SEG25
COM3
SEG24
COM3
xxxx xxxx
92
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 17
PIC16C925/926
TABLE 2-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Details on
page
Bank 3
180h
INDF
181h
OPTION
182h
PCL
183h
STATUS
184h
FSR
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
0000 0000
26
PSA
PS2
PS1
PS0
1111 1111
20
0000 0000
25
PD
Z
DC
C
0001 1xxx
19
xxxx xxxx
26
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
185h
—
186h
TRISB
PORTB Data Direction Register
187h
TRISF
PORTF Data Direction Register
1111 1111
37
188h
TRISG
PORTG Data Direction Register
1111 1111
38
189h
18Ah
—
PCLATH
Unimplemented
Unimplemented
—
—
—
GIE
PEIE
TMR0IE
18Bh
INTCON
18Ch
PMDATA
Data Register Low Byte
Address Register Low Byte
18Dh
PMADR
18Eh
PMDATH
18Fh
PMADRH
—
—
—
—
Write Buffer for the upper 5 bits of the PC
INTE
RBIE
TMR0IF
INTF
Data Register High Byte
—
RBIF
—
—
1111 1111
31
—
—
---0 0000
25
0000 000x
21
xxxx xxxx
27
xxxx xxxx
27
xxxx xxxx
27
xxxx xxxx
27
190h
—
Unimplemented
—
—
191h
—
Unimplemented
—
—
192h
—
Unimplemented
—
—
193h
—
Unimplemented
—
—
194h
—
Unimplemented
—
—
195h
—
Unimplemented
—
—
196h
—
Unimplemented
—
—
197h
—
Unimplemented
—
—
198h
—
Unimplemented
—
—
199h
—
Unimplemented
—
—
19Ah
—
Unimplemented
—
—
19Bh
—
Unimplemented
—
—
19Ch
—
Unimplemented
—
—
19Dh
—
Unimplemented
—
—
19Eh
—
Unimplemented
—
—
19Fh
—
Unimplemented
—
—
Address Register High Byte
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These pixels do not display, but can be used as general purpose RAM.
DS39544B-page 18
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
2.3.1
STATUS REGISTER
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1:
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
“Instruction Set Summary.”
Note:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow the polarity is reversed)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 19
PIC16C925/926
2.3.2
OPTION REGISTER
Note:
The OPTION register is a readable and writable register, which contains various control bits to configure the
TMR0/WDT prescaler, the external RB0/INT pin interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate WDT Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS39544B-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16C925/926
2.3.3
INTCON REGISTER
Note:
The INTCON Register is a readable and writable register which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE/GEIL: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4
INTE: RB0/INT0 External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT0 External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 21
PIC16C925/926
2.3.4
PIE1 REGISTER
Note:
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4:
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
LCDIE
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
LCDIE: LCD Interrupt Enable bit
1 = Enables the LCD interrupt
0 = Disables the LCD interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-4
Unimplemented: Read as ‘0’
bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
DS39544B-page 22
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16C925/926
2.3.5
PIR1 REGISTER
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
LCDIF
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
LCDIF: LCD Interrupt Flag bit
1 = LCD interrupt has occurred (must be cleared in software)
0 = LCD interrupt did not occur
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4
Unimplemented: Read as ‘0’
bit 3
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 23
PIC16C925/926
2.3.6
PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
For various RESET conditions, see Table 12-4 and
Table 12-5.
REGISTER 2-6:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-1
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
bit 7-2
Unimplemented: Read as '0'
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
DS39544B-page 24
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16C925/926
2.4
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL
(PCLATH PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH PCH).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an
interrupt address.
2.5
PIC16C925/926 devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11-bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2-bits of the address are provided by
PCLATH. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALL instruction
(or interrupt) is executed, the entire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PCLATH bits is not required for the RETURN
instructions (which POPs the address from the stack).
Note:
11
Opcode
PCLATH
2.4.1
The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the PCLATH for any subsequent
CALL or GOTO instructions.
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read” (AN556).
2.4.2
Program Memory Paging
STACK
The PIC16CXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
EXAMPLE 2-1:
ORG 0x500
BCF
PCLATH,4
BSF
PCLATH,3
CALL
SUB1_P1
:
:
:
ORG 0x900
SUB1_P1:
:
:
RETURN
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh)
;Call subroutine in
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call subroutine
;in page 0 (000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 25
PIC16C925/926
2.6
Indirect Addressing, INDF and
FSR Registers
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-2:
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register (FSR). Reading the INDF register itself, indirectly
(FSR = '0'), will produce 00h. Writing to the INDF register indirectly results in a no operation (although status
bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and
the IRP bit (STATUS), as shown in Figure 2-6.
FIGURE 2-6:
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
NEXT
Bank Select
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
;yes continue
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
6
From Opcode
Indirect Addressing
0
IRP
7
Bank Select
Location Select
00
01
10
FSR Register
0
Location Select
11
00h
00h
Data
Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note: For memory map detail, see Figure 2-3.
DS39544B-page 26
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
3.0
READING PROGRAM MEMORY
The Program Memory is readable during normal operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a
NOP.
There are five SFRs used to read the program and
memory. These registers are:
•
•
•
•
•
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two-byte word,
which holds the 14-bit data for reads. The
PMADRH:PMADR registers form a two-byte word,
which holds the 13-bit address of the location being
accessed. These devices can have from 4K words to
8K words of program memory, with an address range
from 0h to 3FFFh.
The unused upper bits in both the PMDATH and
PMADRH registers are not implemented and read as
“0’s”.
3.1
PMCON1
PMDATA
PMDATH
PMADR
PMADRH
PMADR
The address registers can address up to a maximum of
8K words of program memory.
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADR register. The upper
MSbits of PMADRH must always be clear.
3.2
PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
REGISTER 3-1: PMCON1 REGISTER (ADDRESS 10Ch)
R-1
U-0
U-0
U-0
U-x
U-0
U-0
R/S-0
r
—
—
—
—
—
—
RD
bit 7
bit 0
bit 7
Reserved: Read as ‘1’
bit 6-1
Unimplemented: Read as ‘0’
bit 0
RD: Read Control bit
1 = Initiates a read, RD is cleared in hardware. The RD bit can only be set (not cleared)
in software.
0 = Does not initiate a read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 27
PIC16C925/926
3.3
Reading the Program Memory
data is available in the PMDATA and PMDATH registers after the NOP instruction. Therefore, it can be read
as two bytes in the following instructions. The PMDATA
and PMDATH registers will hold this value until another
read operation.
A program memory location may be read by writing two
bytes of the address to the PMADR and PMADRH registers, and then setting control bit RD (PMCON1).
Once the read control bit is set, the microcontroller will
use the next two instruction cycles to read the data. The
EXAMPLE 3-1:
PROGRAM READ
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
STATUS, RP1
STATUS, RP0
MS_PROG_PM_ADDR
PMADRH
LS_PROG_PM_ADDR
PMADR
STATUS, RP0
PMCON1, RD
;
;
;
;
;
;
;
;
BSF
STATUS, RP0
; First instruction after BSF PMCON1,RD executes normally
; Bank 3
Bank 3
MS Byte of Program Address to read
LS Byte of Program Address to read
Bank 2
PM Read
;
;
NOP
; Any instructions here are ignored as program
; memory is read in second cycle after BSF PMCON1,RD
;
MOVF
MOVF
3.4
PMDATA, W
PMDATH, W
; W = LS Byte of Program PMDATA
; W = MS Byte of Program PMDATA
Operation During Code Protect
If only part of the program memory is code protected,
the program memory control can read the unprotected
segment and cannot read the protected segment. The
protected area cannot be read, because it may be
possible to write a downloading routine into the
unprotected segment.
If the program memory is not code protected, the program memory control can read anywhere within the
program memory.
If the entire program memory is code protected, the
program memory control can read anywhere within the
program memory.
TABLE 3-1:
Address
REGISTERS ASSOCIATED WITH PROGRAM MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
(1)
—
—
—
—
—
—
RD
10Ch
PMCON1
1--- ---0
1--- ---0
18Ch
PMDATA
Data Register Low Byte
xxxx xxxx
uuuu uuuu
18Dh
PMADR
Address Register Low Byte
xxxx xxxx
uuuu uuuu
18Eh
PMDATH
—
—
18Fh
PMADRH
—
—
Data Register High Byte
—
Address Register High Byte
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.
Shaded cells are not used during FLASH access.
Note 1: This bit always reads as a ‘1’.
DS39544B-page 28
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
4.0
I/O PORTS
FIGURE 4-1:
Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device.
In general, when a peripheral is enabled, that pin may
not be used as a general purpose I/O pin.
4.1
Data
Bus
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All RA pins
have data direction bits (TRISA register), which can
configure these pins as output or input.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The other PORTA
pins are multiplexed with analog inputs and the analog
VREF input. The operation of each pin is selected by
clearing/setting the control bits in the ADCON1 register
(A/D Control Register1).
EXAMPLE 4-1:
MOVWF
VDD
Q
CK
P
Q
N
Q
VSS
D
WR
TRIS
CK
I/O pin(1)
Analog
Input Mode
TRIS Latch
RD
TRIS
TTL
Input
Buffer
Q
D
EN
RD Port
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
On a Power-on Reset, these pins are configured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
BCF
BCF
CLRF
BSF
MOVLW
Q
Data Latch
Setting a bit in the TRISA register puts the corresponding output driver in a Hi-Impedance mode. Clearing a
bit in the TRISA register puts the contents of the output
latch on the selected pin.
Note:
D
WR
Port
PORTA and TRISA Register
BLOCK DIAGRAM OF
PINS RA3:RA0 AND RA5
STATUS, RP0
STATUS, RP1
PORTA
STATUS, RP0
0xCF
TRISA
FIGURE 4-2:
Data
Bus
WR
Port
INITIALIZING PORTA
; Select Bank0
;
;
;
;
;
;
;
;
BLOCK DIAGRAM OF
RA4/T0CKI PIN
D
Q
CK
Q
N
Data Latch
Initialize PORTA
Select Bank1
Value used to
initialize data
direction
Set RA as inputs
RA as outputs
RA are always
WR
TRIS
D
Q
CK
Q
I/O pin(1)
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
RD
TRIS
; read as '0'.
Q
D
EN
EN
RD Port
TMR0 Clock Input
Note 1: I/O pin has protection diodes to VSS only.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 29
PIC16C925/926
TABLE 4-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit0
TTL
Input/output or analog input.
RA1/AN1
bit1
TTL
Input/output or analog input.
RA2/AN2
bit2
TTL
Input/output or analog input.
RA3/AN3/VREF
bit3
TTL
Input/output or analog input or VREF.
RA4/T0CKI
bit4
ST
Input/output or external clock input for Timer0. Output is open drain type.
RA5/AN4/SS
bit5
TTL
Input/output or analog input or slave select input for synchronous serial port.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
RESETS
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0x 0000
--11 1111
--11 1111
---- -000
---- -000
PORTA Data Direction Control Register
—
—
—
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS39544B-page 30
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
4.2
PORTB and TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a Hi-Impedance Input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
EXAMPLE 4-2:
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
INITIALIZING PORTB
STATUS, RP0
STATUS, RP1
PORTB
STATUS, RP0
0xCF
TRISB
; Select Bank0
;
;
;
;
;
;
;
;
Initialize PORTB
Select Bank1
Value used to
initialize data
direction
Set RB as inputs
RB as outputs
RB as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are also disabled
on a Power-on Reset.
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’ed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt-on-mismatch feature, together with software configurable pull-ups on these four pins, allow easy
interface to a keypad and make it possible for wake-up on
key depression. Refer to the Embedded Control Handbook, “Implementing Wake-Up on Key Stroke” (AN552).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
VDD
RBPU(2)
Weak
P Pull-up
FIGURE 4-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
Data Bus
D
WR Port
Q
VDD
I/O
pin(1)
CK
TRIS Latch
D
WR TRIS
RBPU(2)
Data Bus
Q
TTL
Input
Buffer
CK
WR Port
Weak
P Pull-up
Data Latch
D
Q
I/O
pin(1)
CK
TRIS Latch
D
Q
RD TRIS
WR TRIS
Q
TTL
Input
Buffer
CK
D
ST
Buffer
RD Port
EN
RD TRIS
Latch
RB0/INT
Schmitt Trigger
Buffer
Q
D
RD Port
EN
RD Port
Q1
Set RBIF
Note 1:
2:
I/O pins have diode protection to VDD and VSS.
Q
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION).
D
RD Port
From other
RB7:RB4 pins
EN
Q3
RB7:RB6 in Serial Programming Mode
Note 1:
2:
2001-2013 Microchip Technology Inc.
Preliminary
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION).
DS39544B-page 31
PIC16C925/926
TABLE 4-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
RB0/INT
bit0
TTL/ST
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Legend:
Function
Input/output pin or external interrupt input. Internal software
programmable weak pull-up. This buffer is a Schmitt Trigger input when
configured as the external interrupt.
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
bit4
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
bit5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
bit6
TTL/ST
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock. This buffer is a Schmitt Trigger
input when used in Serial Programming mode.
bit7
TTL/ST
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data. This buffer is a Schmitt Trigger
input when used in Serial Programming mode.
TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address
Name
06h, 106h
PORTB
86h, 186h
TRISB
81h, 181h
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
1111 1111
1111 1111
PORTB Data Direction Control Register
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39544B-page 32
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
4.3
FIGURE 4-5:
PORTC and TRISC Register
PORTC is a 6-bit, bi-directional port. Each pin is individually configurable as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 4-5). PORTC pins have
Schmitt Trigger input buffers.
VDD
RBPU(2)
INITIALIZING PORTC
BCF
BCF
CLRF
BSF
MOVLW
STATUS,RP0
STATUS,RP1
PORTC
STATUS,RP0
0xCF
; Select Bank0
MOVWF
TRISC
TABLE 4-5:
;
;
;
;
;
;
;
;
Weak
P Pull-up
Data Latch
Data Bus
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, readmodify-write instructions (BSF, BCF, XORWF) with
TRISC as destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
EXAMPLE 4-3:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
D
WR Port
Q
I/O
pin(1)
CK
TRIS Latch
D
WR TRIS
Q
TTL
Input
Buffer
CK
RD TRIS
Q
RD Port
Initialize PORTC
Select Bank1
Value used to
initialize data
direction
Set RC as inputs
RC as outputs
RC always read 0
D
EN
RB0/INT
Schmitt Trigger
Buffer
Note 1:
2:
RD Port
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION).
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output or Timer1 clock input.
RC1/T1OSI
bit1
ST
Input/output port pin or Timer1 oscillator input.
RC2/CCP1
bit2
ST
Input/output port pin or Capture input/Compare output/PWM output.
RC3/SCK/SCL
bit3
ST
Input/output port pin or the synchronous serial clock for both SPI and
I2C modes.
RC4/SDI/SDA
bit4
ST
Input/output port pin or the SPI Data In (SPI mode) or data I/O
(I2C mode).
RC5/SDO
bit5
ST
Input/output port pin or Synchronous Serial Port data out.
Legend: ST = Schmitt Trigger input
TABLE 4-6:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
07h
PORTC
—
—
87h
TRISC
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
--uu uuuu
--11 1111
--11 1111
PORTC Data Direction Control Register
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTC.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 33
PIC16C925/926
4.4
PORTD and TRISD Registers
FIGURE 4-7:
PORTD is an 8-bit port with Schmitt Trigger input buffers. The first five pins are configurable as general purpose I/O pins or LCD segment drivers. Pins RD5, RD6
and RD7 can be digital inputs, or LCD segment, or
common drivers.
TRISD controls the direction of pins RD0 through RD4
when PORTD is configured as a digital port.
Note 1: On a Power-on Reset, these pins are
configured as LCD segment drivers.
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
EXAMPLE 4-4:
BCF
BSF
BCF
BCF
BSF
BCF
MOVLW
MOVWF
PORTD BLOCK
DIAGRAM
LCD
Segment Data
LCD Segment
Output Enable
LCD
Common Data
Digital Input/
LCD Output pin
LCD Common
Output Enable
LCDSE
Schmitt
Trigger
Input
Buffer
INITIALIZING PORTD
STATUS,RP0
STATUS,RP1
LCDSE, SE29
LCDSE, SE0
STATUS,RP0
STATUS,RP1
0xE0
TRISD
FIGURE 4-6:
;Select Bank2
;
;Make RD
;Make RD
;Select Bank1
;
;Make RD
;Make RD
Data Bus
Q
digital
digital
D
EN
EN
RD Port
outputs
inputs
PORTD BLOCK
DIAGRAM
VDD
RD TRIS
LCD
Segment Data
LCD Segment
Output Enable
Data
Bus
D
WR
Port
Q
I/O pin
CK
Data Latch
D
WR
TRIS
Q
CK
TRIS Latch
Schmitt
Trigger
Input
Buffer
RD
TRIS
LCD SE
Q
D
EN
EN
RD
Port
DS39544B-page 34
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
TABLE 4-7:
PORTD FUNCTIONS
Name
Bit#
RD0/SEG00
bit0
RD1/SEG01
bit1
RD2/SEG02
bit2
RD3/SEG03
bit3
RD4/SEG04
bit4
RD5/SEG29/COM3
bit5
RD6/SEG30/COM2
bit6
RD7/SEG31/COM1
bit7
Legend: ST = Schmitt Trigger input
TABLE 4-8:
Buffer
Type
ST
ST
ST
ST
ST
ST
ST
ST
Function
Input/output port pin or Segment Driver00.
Input/output port pin or Segment Driver01.
Input/output port pin or Segment Driver02.
Input/output port pin or Segment Driver03.
Input/output port pin or Segment Driver04.
Digital input pin or Segment Driver29 or Common Driver3.
Digital input pin or Segment Driver30 or Common Driver2.
Digital input pin or Segment Driver31 or Common Driver1.
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
08h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
0000 0000
0000 0000
88h
TRISD
1111 1111
1111 1111
10Dh
LCDSE
SE12
SE9
SE5
SE0
1111 1111
1111 1111
Address
PORTD Data Direction Control Register
SE29
SE27
SE20
SE16
Legend: Shaded cells are not used by PORTD.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 35
PIC16C925/926
4.5
FIGURE 17-1: PORTE BLOCK DIAGRAM
PORTE and TRISE Register
PORTE is a digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have
Schmitt Trigger input buffers.
LCD
Segment Data
LCD Segment
Output Enable
Note 1: On a Power-on Reset, these pins are
configured as LCD segment drivers.
LCD
Common Data
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
EXAMPLE 4-5:
BCF
BSF
BCF
BCF
BCF
STATUS,
STATUS,
LCDSE,
LCDSE,
LCDSE,
Digital Input/
LCD Output pin
LCD Common
Output Enable
LCDSE
INITIALIZING PORTE
RP0
RP1
SE27
SE5
SE9
Schmitt
Trigger
Input
Buffer
;Select Bank2
;
;Make all PORTE
;and PORTG
;digital inputs
Data Bus
Q
D
EN
EN
RD Port
VDD
RD TRIS
TABLE 4-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
RE0/SEG05
bit0
ST
RE1/SEG06
bit1
ST
RE2/SEG07
bit2
ST
RE3/SEG08
bit3
ST
RE4/SEG09
bit4
ST
RE5/SEG10
bit5
ST
RE6/SEG11
bit6
ST
RE7/SEG27
bit7
ST
Legend: ST = Schmitt Trigger input
TABLE 4-10:
Function
Digital input or Segment Driver05.
Digital input or Segment Driver06.
Digital input or Segment Driver07.
Digital input or Segment Driver08.
Digital input or Segment Driver09.
Digital input or Segment Driver10.
Digital input or Segment Driver11.
Digital input or Segment Driver27 (not available on 64-pin devices).
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
09h
PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
0000 0000
0000 0000
89h
TRISE
1111 1111
1111 1111
10Dh
LCDSE
1111 1111
1111 1111
Address
PORTE Data Direction Control Register
SE29
SE27
SE20
SE16
SE12
SE9
SE5
SE0
Legend: Shaded cells are not used by PORTE.
DS39544B-page 36
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
4.6
FIGURE 4-8:
PORTF and TRISF Register
PORTF is a digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have
Schmitt Trigger input buffers.
LCD
Segment Data
LCD Segment
Output Enable
Note 1: On a Power-on Reset, these pins are
configured as LCD segment drivers.
LCD
Common Data
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
EXAMPLE 4-6:
BCF
BSF
BCF
BCF
STATUS,
STATUS,
LCDSE,
LCDSE,
Digital Input/
LCD Output pin
LCD Common
Output Enable
LCDSE
INITIALIZING PORTF
RP0
RP1
SE16
SE12
PORTF BLOCK DIAGRAM
;Select Bank2
;
;Make all PORTF
;digital inputs
Schmitt
Trigger
Input
Buffer
Data Bus
Q
D
EN
EN
RD Port
VDD
RD TRIS
TABLE 4-11:
Name
PORTF FUNCTIONS
Bit#
Buffer Type
RF0/SEG12
bit0
ST
RF1/SEG13
bit1
ST
RF2/SEG14
bit2
ST
RF3/SEG15
bit3
ST
RF4/SEG16
bit4
ST
RF5/SEG17
bit5
ST
RF6/SEG18
bit6
ST
RF7/SEG19
bit7
ST
Legend: ST = Schmitt Trigger input
TABLE 4-12:
Address
Name
107h
PORTF
187h
TRISF
10Dh
LCDSE
Function
Digital input or Segment Driver12.
Digital input or Segment Driver13.
Digital input or Segment Driver14.
Digital input or Segment Driver15.
Digital input or Segment Driver16.
Digital input or Segment Driver17.
Digital input or Segment Driver18.
Digital input or Segment Driver19.
SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
0000 0000
0000 0000
PORTF Data Direction Control Register
SE29
SE27
SE20
SE16
SE12
SE9
SE5
SE0
1111 1111
1111 1111
1111 1111
1111 1111
Legend: Shaded cells are not used by PORTF.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 37
PIC16C925/926
4.7
FIGURE 4-9:
PORTG and TRISG Register
PORTG is a digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have
Schmitt Trigger input buffers.
PORTG BLOCK DIAGRAM
LCD
Segment Data
LCD Segment
Output Enable
Note 1: On a Power-on Reset, these pins are
configured as LCD segment drivers.
2: To configure the pins as a digital port, the
corresponding bits in the LCDSE register
must be cleared. Any bit set in the LCDSE
register overrides any bit settings in the
corresponding TRIS register.
LCD
Common Data
LCD Common
Output Enable
Digital Input/
LCD Output pin
LCDSE
EXAMPLE 4-7:
BCF
BSF
BCF
BCF
INITIALIZING PORTG
STATUS,
STATUS,
LCDSE,
LCDSE,
RP0
RP1
SE27
SE20
Schmitt
Trigger
Input
Buffer
;Select Bank2
;
;Make all PORTG
;and PORTE
;digital inputs
Data Bus
Q
D
EN
EN
RD Port
VDD
RD TRIS
TABLE 4-13:
Name
PORTG FUNCTIONS
Bit#
Buffer Type
RG0/SEG20
bit0
ST
RG1/SEG21
bit1
ST
RG2/SEG22
bit2
ST
RG3/SEG23
bit3
ST
RG4/SEG24
bit4
ST
RG5/SEG25
bit5
ST
RG6/SEG26
bit6
ST
RG7/SEG28
bit7
ST
Legend: ST = Schmitt Trigger input
TABLE 4-14:
Function
Digital input or Segment Driver20.
Digital input or Segment Driver21.
Digital input or Segment Driver22.
Digital input or Segment Driver23.
Digital input or Segment Driver24.
Digital input or Segment Driver25.
Digital input or Segment Driver26.
Digital input or Segment Driver28 (not available on 64-pin devices).
SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
108h
PORTG
RG7
RG6
RG5
RG4
RG3
RG2
RG1
RG0
0000 0000
0000 0000
188h
TRISG
1111 1111
1111 1111
10Dh
LCDSE
SE12
SE9
SE5
SE0
1111 1111
1111 1111
Address
PORTG Data Direction Control Register
SE29
SE27
SE20
SE16
Legend: Shaded cells are not used by PORTG.
DS39544B-page 38
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
4.8
4.8.1
I/O Programming Considerations
EXAMPLE 4-8:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the contents of the data latch may now be unknown.
Reading the port register reads the values of the port
pins. Writing to the port register, writes the value to the
port latch. When using read-modify-write instructions
(e.g. BCF, BSF) on a port, the value of the port pins is
read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 4-8 shows the effect of two sequential
read-modify-write instructions on an I/O port. A pin
actively outputting a Low or High should not be driven
from external devices at the same time, in order to
change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 4-10:
Instruction
Fetched
4.8.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 4-10). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file
to be read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU,
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP, or another
instruction not accessing this I/O port.
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4
PC
;Initial PORT settings: PORTB Inputs
;
PORTB Outputs
;PORTB have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch
PORT pins
;
-----------------BCF PORTB, 7
; 01pp pppp
11pp pppp
BCF PORTB, 6
; 10pp pppp
11pp pppp
BCF STATUS, RP1 ; Select Bank1
BSF STATUS, RP0 ;
BCF TRISB, 7
; 10pp pppp
11pp pppp
BCF TRISB, 6
; 10pp pppp
10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
MOVWF PORTB
write to
PORTB
PC + 1
Q1 Q2 Q3 Q4
PC + 2
NOP
MOVF PORTB,W
Note:
PC + 3
This example shows a write to PORTB
followed by a read from PORTB.
NOP
Note that:
data setup time = (0.25TCY - TPD)
where TCY =
TPD =
RB7:RB0
instruction cycle
propagation delay
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
Port pin
sampled here
TPD
Instruction
Executed
MOVWF PORTB
write to
PORTB
2001-2013 Microchip Technology Inc.
MOVF PORTB,W
Preliminary
NOP
DS39544B-page 39
PIC16C925/926
NOTES:
DS39544B-page 40
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
5.0
TIMER0 MODULE
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 5.2.
The Timer0 module has the following features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt-on-overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler assignment is controlled in software by control bit PSA (OPTION). Clearing bit PSA will assign
the prescaler to the Timer0 module. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing bit T0CS
(OPTION). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 5-2 and
Figure 5-3). The user can work around this by writing
an adjusted value to the TMR0 register.
5.1
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON). The interrupt can be masked
by clearing bit T0IE (INTCON). Bit TMR0IF must be
cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP.
Figure 5-4 displays the Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS
(OPTION). In Counter mode, Timer0 will increment
either on every rising, or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Source Edge Select bit T0SE (OPTION). Clearing
FIGURE 5-1:
Timer0 Interrupt
TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
PSout
1
1
Programmable
Prescaler
RA4/T0CKI
pin
0
8
Sync with
Internal
Clocks
TMR0
PSout
(2 cycle delay)
T0SE
3
PS2, PS1, PS0
PSA
T0CS
Set Interrupt
Flag bit TMR0IF
on Overflow
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION).
2: The prescaler is shared with the Watchdog Timer (refer to Figure 5-6 for detailed block diagram).
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 41
PIC16C925/926
FIGURE 5-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC-1
PC
T0
TMR0
PC+1
T0+1
Instruction
Executed
FIGURE 5-3:
PC+2
PC+3
PC+4
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+5
NT0
PC+6
NT0+1
NT0+2
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
PC-1
PC
T0
TMR0
T0
PC+1
PC+2
PC+3
T0+1
Instruction
Executed
PC+5
PC+6
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
NT0+1
NT0
Write TMR0
executed
FIGURE 5-4:
PC+4
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
TMR0IF bit
(INTCON)
FFh
00h
01h
02h
1
1
GIE bit
(INTCON)
INSTRUCTION
FLOW
PC
PC
Instruction
Fetched
Inst (PC)
Instruction
Executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: Interrupt flag bit TMR0IF is sampled here (every Q1).
2: Interrupt latency = 4TCY where TCY = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS39544B-page 42
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
5.2
Using Timer0 with an External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
5.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 5-5).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 20 ns) and low for
at least 2TOSC (and a small RC delay of 20 ns). Refer
to the electrical specification of the desired device.
FIGURE 5-5:
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter type prescaler, so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the
desired device.
5.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 module is actually incremented. Figure 5-5 shows the delay
from the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler Output(2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC.) Therefore, the error
in measuring the interval between two edges on Timer0 input = 4TOSC max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 43
PIC16C925/926
5.3
Prescaler
The PSA and PS2:PS0 bits (OPTION) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (Figure 5-6). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that the prescaler may be used by either the
Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that
there is no prescaler for the Watchdog Timer, and viceversa.
FIGURE 5-6:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler count. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler count along with the Watchdog Timer. The
prescaler is not readable or writable.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT (= FOSC/4)
Data Bus
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set Flag bit TMR0IF
on Overflow
PSA
8-bit Prescaler
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION).
DS39544B-page 44
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
5.3.1
SWITCHING PRESCALER
ASSIGNMENT
Note:
The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program
execution.
EXAMPLE 5-1:
To avoid an unintended device RESET,
the following instruction sequence (shown
in Example 5-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This precaution must
be followed even if the WDT is disabled.
CHANGING PRESCALER (TIMER0WDT)
Lines 2 and 3 do NOT have to
be included if the final desired
prescale value is other than 1:1.
If 1:1 is final desired value, then
a temporary prescale value is
set in lines 2 and 3 and the final
prescale value will be set in lines
10 and 11.
1)
BSF
STATUS, RP0
;Select Bank1
2)
MOVLW
b'xx0x0xxx'
;Select clock source and prescale value of
3)
MOVWF
OPTION_REG
;other than 1:1
4)
BCF
STATUS, RP0
;Select Bank0
5)
CLRF
TMR0
;Clear TMR0 and prescaler
6)
BSF
STATUS, RP1
;Select Bank1
7)
MOVLW
b'xxxx1xxx'
;Select WDT, do not change prescale value
8)
MOVWF
OPTION_REG
;
9)
CLRWDT
;Clears WDT and prescaler
10) MOVLW
b'xxxx1xxx'
;Select new prescale value and WDT
11) MOVWF
OPTION_REG
;
12) BCF
STATUS, RP0
;Select Bank0
To change prescaler from the WDT to the Timer0 module use the precaution shown in Example 5-2.
EXAMPLE 5-2:
CHANGING PRESCALER (WDTTIMER0)
CLRWDT
;Clear WDT and precaler
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
MOVWF
BCF
OPTION_REG
STATUS, RP0
TABLE 5-1:
Address
01h, 101h
;Select Bank1
;Select TMR0,
;new prescale value and
;clock source
;Select Bank0
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
0Bh, 8Bh,
INTCON
10Bh, 18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 Module Register
GIE
PEIE
81h, 181h
OPTION RBPU INTEDG
85h
TRISA
—
—
Value on
Power-on
Reset
Value on
all other
RESETS
xxxx xxxx uuuu uuuu
TMR0IE
INTE
RBIE TMR0IF
INTF
RBIF
T0CS
T0SE
PSA
PS1
PS0
PS2
PORTA Data Direction Control Register
0000 000x 0000 000u
1111 1111 1111 1111
--11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by Timer0.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 45
PIC16C925/926
NOTES:
DS39544B-page 46
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
6.0
TIMER1 MODULE
Timer1 is a 16-bit timer/counter consisting of two 8-bit
registers (TMR1H and TMR1L), which are readable
and
writable.
The
TMR1
Register
pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit, TMR1IF (PIR1). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1).
Timer1 can operate in one of two modes:
• As a timer
• As a counter
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be turned on and off using the control bit
TMR1ON (T1CON).
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 8.0). Register 6-1 shows the Timer1 control
register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs, regardless of the TRISC. RC1
and RC0 will be read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON).
REGISTER 6-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
—
—
T1CKPS1
T1CKPS0
R/W-0
R/W-0
R/W-0
R/W-0
T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 47
PIC16C925/926
6.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON) has no effect since the internal clock is
always in sync.
6.2
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI when bit T1OSCEN is
set, or pin RC0/T1OSO/T1CKI when bit T1OSCEN is
cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The prescaler however will continue to increment.
FIGURE 6-1:
6.2.1
EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
When an external clock input is used for Timer1 in Synchronized Counter mode, it must meet certain requirements. The external clock requirement is due to
internal phase clock (TOSC) synchronization. Also,
there is a delay in the actual incrementing of TMR1
after synchronization.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2TOSC (and
a small RC delay of 20 ns), and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the appropriate electrical specifications, parameters 45, 46, and 47.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple
counter type prescaler, so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple counter must be taken
into account. Therefore, it is necessary for T1CKI to
have a period of at least 4TOSC (and a small RC delay
of 40 ns), divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of
10 ns). Refer to the appropriate electrical specifications, parameters 40, 42, 45, 46, and 47.
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
0
TMR1
TMR1H
Synchronized
Clock Input
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS1:T1CKPS0
TMR1CS
SLEEP Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39544B-page 48
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
6.3
6.3.2
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow which will wake-up
the processor. However, special precautions in software are needed to read from, or write to the Timer1
register pair (TMR1H:TMR1L) (Section 6.3.2).
In Asynchronous Counter mode, Timer1 cannot be
used as a time-base for capture or compare operations.
6.3.1
EXTERNAL CLOCK INPUT TIMING
WITH UNSYNCHRONIZED CLOCK
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high time and low time requirements,
as specified in timing parameters 45, 46, and 47.
EXAMPLE 6-1:
READING AND WRITING TMR1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers while the
register is incrementing. This may produce an unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Example 6-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
READING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
;
MOVF
TMR1H, W
;Read high byte
MOVWF TMPH
;
MOVF
TMR1L, W
;Read low byte
MOVWF TMPL
;
MOVF
TMR1H, W
;Read high byte
SUBWF TMPH, W
;Sub 1st read with 2nd read
BTFSC STATUS,Z
;Is result = 0
GOTO
CONTINUE
;Good 16-bit read
;
; TMR1L may have rolled over between the read of the high and low bytes.
; Reading the high and low bytes now will read a good value.
;
MOVF
TMR1H, W
;Read high byte
MOVWF TMPH
;
MOVF
TMR1L, W
;Read low byte
MOVWF TMPL
;
; Re-enable the Interrupt (if required)
;
CONTINUE
;Continue with your code
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 49
PIC16C925/926
6.4
Timer1 Oscillator
6.5
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
Note:
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Timer1 must be configured for either Timer or Synchronized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively become the period register for
Timer1.
LP
32 kHz
33 pF
33 pF
100 kHz
15 pF
15 pF
200 kHz
15 pF
15 pF
These values are for design guidance only.
6.6
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A 20 PPM
100 kHz
Epson C-2 100.00 KC-P 20 PPM
200 kHz
STD XTL 200.000 kHz
20 PPM
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
TABLE 6-2:
Resetting Timer1 Using the CCP
Trigger Output
Resetting of Timer1 Register Pair
(TMR1H:TMR1L)
TMR1H and TMR1L registers are not reset on a POR
or any other RESET, except by the CCP1 special event
trigger.
T1CON register is reset to 00h on a Power-on Reset.
In any other RESET, the register is unaffected.
6.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
Value on
Power-on
Reset
Value on
all other
RESETS
0000 000x 0000 000u
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
00-- 0000 00-- 0000
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
00-- 0000 00-- 0000
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
Legend:
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by theTimer1 module.
DS39544B-page 50
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
7.0
TIMER2 MODULE
7.1
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module. It can also be used
as a time-base for the Master mode SPI clock. The
TMR2 register is readable and writable, and is cleared
on any device RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4,
or
1:16
(selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON)).
The Timer2 module has an 8-bit period register, PR2.
TMR2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
set during RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1)).
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON) to minimize power consumption.
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, or Watchdog Timer Reset)
TMR2 will not clear when T2CON is written.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate the shift clock.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
TMR2
Output(1)
FOSC/4
Figure 7-1 shows the Timer2 control register.
Prescaler
1:1, 1:4, 1:16
2
TMR2 reg
RESET
Comparator
EQ
PR2 reg
Sets Flag
bit TMR2IF
Postscaler
1:16 to 1:1
4
Note 1: TMR2 register output can be software selected by the
SSP Module as the source clock.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 51
PIC16C925/926
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
TABLE 7-1:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
Power-on
Reset
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
00-- 0000 00-- 0000
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
11h
TMR2
12h
T2CON
92h
PR2
Legend:
Timer2 Module’s Register
—
00-- 0000 00-- 0000
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
DS39544B-page 52
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
8.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
Register 8-1 shows the CCP1CON register.
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/slave duty cycle register. Table 8-1 shows the
timer resources used by the CCP module.
For use of the CCP module, refer to the Embedded
Control Handbook, “Using the CCP Modules” (AN594).
TABLE 8-1:
The Capture/Compare/PWM Register1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All three are readable and
writable.
REGISTER 8-1:
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1CON REGISTER (ADDRESS 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: CCP1 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (bit CCP1IF is set)
1001 = Compare mode, clear output on match (bit CCP1IF is set)
1010 = Compare mode, generate software interrupt-on-match (bit CCP1IF is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1)
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 53
PIC16C925/926
8.1
8.1.3
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1 (Figure 8-1). An event can be
selected to be one of the following:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC bit.
Note:
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a capture condition.
FIGURE 8-1:
RC2/CCP1
pin
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
CLRF
MOVLW
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
CCP
Prescaler
1, 4, 16
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep
enable bit CCP1IE (PIE1) clear to avoid false interrupts and should clear flag bit CCP1IF following any
such change in operating mode.
8.1.4
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON). When a capture is made, the interrupt request flag bit CCP1IF (PIR1) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten with the new captured value.
SOFTWARE INTERRUPT
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
; Turn CCP module off
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; mode value and CCP ON
CCP1CON
; Load CCP1CON with
; this value
Set CCP1IF
PIR1
CCPR1H
and
edge detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
CCP1CON
Q’s
8.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
DS39544B-page 54
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
8.2
8.2.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON). At the
same time, a compare interrupt is also generated.
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Trigger
Q
S
R
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion. This
allows the CCPR1H:CCPR1L register pair to effectively
be a 16-bit programmable period register for Timer1.
Set CCP1IF
PIR1
Output
Logic
Note:
CCPR1H CCPR1L
Match
TRISC
Output Enable
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1).
RC2/CCP1
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).
8.2.4
FIGURE 8-2:
TIMER1 MODE SELECTION
The “special event trigger” from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Comparator
TMR1H
TMR1L
CCP1CON
Mode Select
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 55
PIC16C925/926
8.3
8.3.1
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = [ (PR2) + 1 ] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON
Duty Cycle Registers
CCPR1L
8.3.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
TMR2
(Note 1)
S
Clear Timer,
CCP1 pin and
latch D.C.
PR2
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
PWM OUTPUT
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available; the CCPR1L contains
the eight MSbs and CCP1CON contains the two
LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
Period
Duty Cycle
PWM DUTY CYCLE
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
FIGURE 8-4:
The Timer2 postscaler (Section 7.0) is not
used in the determination of the PWM frequency. The postscaler could be used to
have a servo update rate at a different frequency than the PWM output.
PWM duty cycle = (CCPR1L:CCP1CON) •
TOSC • (TMR2 prescale value)
TRISC
Comparator
PWM PERIOD
F OSC
log ---------------
F PWM
PWM Resolution (max) = -----------------------------bits
log 2
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note:
DS39544B-page 56
Preliminary
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
2001-2013 Microchip Technology Inc.
PIC16C925/926
EQUATION 8-1:
1.
EXAMPLES OF PWM PERIOD AND DUTY CYCLE CALCULATION
Find the value of the PR2 register, given:
• Desired PWM frequency = 31.25 kHz
• FOSC = 8 MHz
• TMR2 prescale = 1
From the equation for PWM period in Section 8.3.1,
1 / 31.25 kHz
= [ (PR2) + 1 ] • 4 • 1/8 MHz • 1
32 s
= [ (PR2) + 1 ] • 4 • 125 ns • 1 = [ (PR2) + 1 ] • 0.5 s
PR2
= (32 s / 0.5 s) - 1
PR2
= 63
or
2.
Find the maximum resolution of the duty cycle that can be used with a 31.25 kHz frequency and
8 MHz oscillator.
From the equation from maximum PWM resolution in Section 8.3.2,
1 / 31.25 kHz
= 2PWM RESOLUTION • 1 / 8 MHz • 1
32 s
= 2PWM RESOLUTION • 125 ns • 1
256
= 2PWM RESOLUTION
log(256)
= (PWM Resolution) • log(2)
8.0
= PWM Resolution
or
At most, an 8-bit resolution duty cycle can be obtained
from a 31.25 kHz frequency and a 8 MHz oscillator, i.e.,
0 CCPR1L:CCP1CON 255. Any value greater
than 255 will result in a 100% duty cycle.
8.3.3
In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher
PWM frequency, the resolution must be decreased.
1.
Table 8-2 lists example PWM frequencies and resolutions for FOSC = 8 MHz. TMR2 prescaler and PR2 values are also shown.
The following steps should be taken when configuring
the CCP module for PWM operation:
2.
3.
4.
5.
TABLE 8-2:
SET-UP FOR PWM OPERATION
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP module for PWM operation.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 8 MHz
PWM Frequency
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
2001-2013 Microchip Technology Inc.
488 Hz
1.95 kHz
7.81 kHz
31.25 kHz
62.5 kHz
250 kHz
16
0xFF
10
4
0xFF
10
1
0xFF
10
1
0x3F
8
1
0x1F
7
1
0x07
5
Preliminary
DS39544B-page 57
PIC16C925/926
TABLE 8-3:
Address
REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
Value on
Power-on
Reset
Value on
all other
RESETS
0000 000x 0000 000u
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF 00-- 0000 00-- 0000
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE 00-- 0000 00-- 0000
87h
TRISC
—
—
PORTC Data Direction Control Register
--11 1111 --11 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
17h
CCP1CON
Legend:
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1Y
CCP1M3
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in these modes.
TABLE 8-4:
Address
—
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Power-on
Reset
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
00-- 0000 00-- 0000
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE 00-- 0000 00-- 0000
—
—
PORTC Data Direction Control Register
87h
TRISC
11h
TMR2
Timer2 Module Register
0000 0000 0000 0000
92h
PR2
Timer2 Module Period Register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
17h
CCP1CON
Legend:
—
—
--11 1111 --11 1111
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
—
CCP1X
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in this mode.
DS39544B-page 58
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
9.0
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
REGISTER 9-1:
• Serial Peripheral Interface (SPITM)
• Inter-Integrated Circuit (I 2CTM)
Refer to Application Note AN578, "Use of the SSP
Module in the I 2C Multi-Master Environment.”
SSPSTAT: SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
bit 6
CKE: SPI Clock Edge Select bit (see Figure 9-3, Figure 9-4, and Figure 9-5)
CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: STOP bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the START
bit was detected last.)
1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET)
0 = STOP bit was not detected last
bit 3
S: START bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the STOP
bit was detected last.)
1 = Indicates that a START bit has been detected last (this bit is '0' on RESET)
0 = START bit was not detected last
bit 2
R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit, or ACK bit.
1 = Read
0 = Write
bit 1
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 59
PIC16C925/926
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while SSPBUF is holding previous data. Data in SSPSR is lost on overflow.
Overflow only occurs in Slave mode. The user must read the SSPBUF, even if only transmitting data,
to avoid setting overflows. In Master mode, the overflow bit is not set since each operation is initiated
by writing to the SSPBUF register. (Must be cleared in software.)
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a “don’t care” in transmit
mode. (Must be cleared in software.)
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin (SS pin control enabled)
0101 = SPI Slave mode, clock = SCK pin (SS pin control disabled, SS can be used as I/O pin)
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1011 = I2C firmware controlled Master mode (slave idle)
1110 = I2C firmware controlled Master mode, 7-bit address with START and STOP bit interrupts enabled
1111 = I2C firmware controlled Master mode, 10-bit address with START and STOP bit interrupts enabled
1000, 1001, 1010, 1100, 1101 = reserved
Legend:
DS39544B-page 60
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16C925/926
9.1
EXAMPLE 9-1:
SPI Mode
The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
LOOP
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI
• Serial Clock (SCK) RC3/SCK
MOVF
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON)
and SSPSTAT. These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
TXDATA, W
;Select Bank1
;
;Has data been
;received
;(transmit
;complete)?
;No
;Select Bank0
;W reg = contents
;of SSPBUF
;Save in user RAM
;W reg = contents
; of TXDATA
;New data to xmit
MOVWF SSPBUF
The block diagram of the SSP module, when in SPI
mode (Figure 9-1), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 9-1:
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the buffer full detect bit, BF
(SSPSTAT), and interrupt flag bit, SSPIF
(PIR1), are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON), will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPBUF register completed successfully. When the
application software is expecting to receive valid data,
the SSPBUF should be read before the next byte of
data to transfer is written to the SSPBUF. Buffer full bit,
BF (SSPSTAT), indicates when SSPBUF has been
loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared.
This data may be irrelevant if the SPI is only a transmitter. Generally, the SSP interrupt is used to determine
when the transmission/reception has completed. The
SSPBUF must be read and/or written. If the interrupt
method is not going to be used, then software polling
can be done to ensure that a write collision does not
occur. Example 9-1 shows the loading of the SSPBUF
(SSPSR) for data transmission. The MOVWF RXDATA
instruction (shaded) is only required if the received data
is meaningful.
LOOP
STATUS, RP0
SSPBUF, W
MOVWF RXDATA
• Slave Select (SS) RA5/AN4/SS
2001-2013 Microchip Technology Inc.
BCF
STATUS, RP1
BSF
STATUS, RP0
BTFSS SSPSTAT, BF
GOTO
BCF
MOVF
Additionally, a fourth pin may be used when in a Slave
mode of operation:
LOADING THE SSPBUF
(SSPSR) REGISTER
SSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
SSPSR reg
RC4/SDI/SDA
Shift
Clock
bit0
RC5/SDO
SS Control
Enable
RA5/AN4/SS
Preliminary
Edge
Select
2
Clock Select
SSPM3:SSPM0
4
Edge
Select
RC3/SCK/
SCL
TMR2 Output
2
Prescaler TCY
4, 16, 64
TRISC
DS39544B-page 61
PIC16C925/926
To enable the serial port, SSP enable bit, SSPEN
(SSPCON) must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
register, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISC register)
appropriately programmed. That is:
• SDI must have TRISC set
• SDO must have TRISC cleared
• SCK (Master mode) must have TRISC
cleared
• SCK (Slave mode) must have TRISC set
• SS must have TRISA set and ADCON must
be configured such that RA5 is a digital I/O
Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example
would be in Master mode, where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite
edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time.
Whether the data is meaningful (or dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data—Slave sends dummy data
• Master sends data—Slave sends data
FIGURE 9-2:
• Master sends dummy data—Slave sends data
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the firmware protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1)
is set.
The clock polarity is selected by appropriately programming bit CKP (SSPCON). This then, would give
waveforms for SPI communication as shown in
Figure 9-3, Figure 9-4, and Figure 9-5, where the MSB
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the
following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum bit clock frequency (at 8 MHz)
of 2 MHz. When in Slave mode, the external clock must
meet the minimum high and low times.
In SLEEP mode, the slave can transmit and receive
data and wake the device from SLEEP.
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
SDO
LSb
Shift Register
(SSPSR)
MSb
LSb
Serial Clock
SCK
PROCESSOR 1
DS39544B-page 62
SCK
PROCESSOR 2
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode (SSPCON = 04h)
and the TRISA bit must be set for the Synchronous Slave mode to be enabled. When the SS pin
is low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
FIGURE 9-3:
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control must be
enabled.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit7
SDO
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
bit7
bit0
SSPIF
FIGURE 9-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 63
PIC16C925/926
FIGURE 9-5:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
(not optional)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit6
bit7
bit5
bit3
bit4
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF TMR2IF TMR1IF 00-- 0000
00-- 0000
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE
CCP1IE TMR2IE TMR1IE 00-- 0000
00-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
WCOL SSPOV
85h
TRISA
—
—
87h
TRISC
—
—
94h
SSPSTAT
SMP
CKE
SSPEN
CKP
SSPM3
SSPM2
xxxx xxxx
SSPM1
SSPM0
uuuu uuuu
0000 0000
0000 0000
PORTA Data Direction Control Register
--11 1111
--11 1111
PORTC Data Direction Control Register
--11 1111
--11 1111
0000 0000
0000 0000
D/A
P
S
R/W
UA
BF
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.
DS39544B-page 64
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
I 2C Overview
9.2
This section provides an overview of the InterIntegrated Circuit (I 2C) bus, with Section 9.3 discussing the operation of the SSP module in I 2C mode.
The I 2C bus is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. An enhanced specification, or fast mode is not
supported. This device will communicate with fast
mode devices if attached to the same bus.
The output stages of the clock (SCL) and data (SDA)
lines must have an open drain or open collector, in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The number of devices that may be attached to the I 2C bus is
limited only by the maximum bus loading specification
of 400 pF.
9.2.1
INITIATING AND TERMINATING
DATA TRANSFER
The I 2C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hardware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXXX software. Table 9-2 defines some of the
I 2C bus terminology. For additional information on the
I 2C interface specification, refer to the Philips document #939839340011, “The I 2C bus and how to use it”,
which can be obtained from the Philips Corporation.
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a
high to low transition of the SDA when the SCL is high.
The STOP condition is defined as a low to high transition of the SDA when the SCL is high. Figure 9-6 shows
the START and STOP conditions. The master generates these conditions for starting and terminating data
transfer. Due to the definition of the START and STOP
conditions, when data is being transmitted, the SDA
line can only change state when the SCL line is low.
In the I 2C interface protocol, each device has an
address. When a master wishes to initiate a data transfer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read from/write to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data transfer. That is, they can be thought of as operating in either
of these two relations:
FIGURE 9-6:
START AND STOP
CONDITIONS
SDA
SCL
S
START
Condition
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
P
Change
of Data
Allowed
Change
of Data
Allowed
STOP
Condition
In both cases, the master generates the clock signal.
TABLE 9-2:
I2C BUS TERMINOLOGY
Term
Description
Transmitter
The device that sends the data to the bus.
Receiver
The device that receives the data from the bus.
Master
The device which initiates the transfer, generates the clock and terminates the transfer.
Slave
The device addressed by a master.
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensures that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 65
PIC16C925/926
ADDRESSING I 2C DEVICES
9.2.2
9.2.3
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 9-7). The
more complex is the 10-bit address with a R/W bit
(Figure 9-8). For 10-bit address format, two bytes must
be transmitted with the first five bits specifying this to be
a 10-bit address.
FIGURE 9-7:
FIGURE 9-9:
LSb
SLAVE-RECEIVER
ACKNOWLEDGE
R/W ACK
S
Slave Address
S
R/W
ACK
All data must be transmitted per byte, with no limit to
the number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an Acknowledge bit (ACK) (see Figure 9-9). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 9-6).
7-BIT ADDRESS FORMAT
MSb
TRANSFER ACKNOWLEDGE
Data
Output by
Transmitter
Sent by
Slave
Data
Output by
Receiver
START Condition
Read/Write pulse
Acknowledge
Acknowledge
SCL from
Master
8
2
1
S
START
Condition
I2
FIGURE 9-8:
Not Acknowledge
C 10-BIT ADDRESS
FORMAT
9
Clock Pulse for
Acknowledgment
If the master is receiving the data (master-receiver), it
generates an Acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an Acknowledge (Not Acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the Acknowledge
pulse for valid termination of data transfer.
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
Sent by Slave
= 0 for Write
- START Condition
S
R/W - Read/Write Pulse
ACK - Acknowledge
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data, or fetch the data it needs to transfer
before allowing the clock to start. This wait state technique can also be implemented at the bit level,
Figure 9-10. The slave will inherently stretch the clock
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the SSPCON bit to
enable clock stretching when it is a receiver.
FIGURE 9-10:
DATA TRANSFER WAIT STATE
SDA
MSB
Acknowledgment
Signal from Receiver
Acknowledgment
Byte Complete
Signal from Receiver
Interrupt with Receiver
Clock Line Held Low while
Interrupts are Serviced
SCL
S
START
Condition
DS39544B-page 66
1
2
Address
7
8
9
R/W
ACK
1
Wait
State
Preliminary
2
Data
38
9
ACK
P
STOP
Condition
2001-2013 Microchip Technology Inc.
PIC16C925/926
Figure 9-11 and Figure 9-12 show master-transmitter
and Master-receiver data transfer sequences.
while SCL is high), but occurs after a data transfer
Acknowledge pulse (not the bus-free state). This allows
a master to send “commands” to the slave and then
receive the requested information, or to address a different slave device. This sequence is shown in
Figure 9-13.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a Repeated START
condition (Sr) must be generated. This condition is
identical to the START condition (SDA goes high-to-low
FIGURE 9-11:
MASTER-TRANSMITTER SEQUENCE
For 7-bit address:
For 10-bit address:
S Slave Address R/W A1 Slave Address A2
Second byte
First 7 bits
S Slave Address R/W A Data A Data A/A P
'0' (write)
data transferred
(n bytes - Acknowledge)
A master-transmitter addresses a slave-receiver with a
7-bit address. The transfer direction is not changed.
From master to slave
From slave to master
FIGURE 9-12:
(write)
Data A
Data A/A P
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
S = START Condition
A master-transmitter addresses a slave-receiver
P = STOP Condition
with a 10-bit address.
MASTER-RECEIVER SEQUENCE
For 10-bit address:
S Slave Address R/W A1 Slave Address A2
First 7 bits
Second byte
For 7-bit address:
S Slave Address R/W A Data A Data A P
'1' (read)
data transferred
(n bytes - Acknowledge)
A master reads a slave immediately after the first byte.
From master to slave
From slave to master
FIGURE 9-13:
(write)
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
S = START Condition
P = STOP Condition
Sr Slave Address R/W A3 Data A
First 7 bits
Data A P
(read)
A master-transmitter addresses a slave-receiver
with a 10-bit address.
COMBINED FORMAT
(read or write)
(n bytes + Acknowledge)
S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P
(read)
(write)
Sr = repeated
START Condition
Direction of transfer
may change at this point
Transfer direction of data and Acknowledgment bits depends on R/W bits.
Combined format:
Sr Slave Address R/W A Slave Address A Data A
First 7 bits
Second byte
Data A/A Sr Slave Address R/W A Data A
First 7 bits
Data A P
(read)
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
From master to slave
From slave to master
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
S = START Condition
P = STOP Condition
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 67
PIC16C925/926
9.2.4
MULTI-MASTER
9.2.4.2
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time,
arbitration and synchronization occur.
9.2.4.1
Arbitration
Arbitration takes place on the SDA line, while the SCL
line is high. The master, which transmits a high when
the other master transmits a low, loses arbitration
(Figure 9-14) and turns off its data output stage. A master, which lost arbitration can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
FIGURE 9-14:
MULTI-MASTER
ARBITRATION
(TWO MASTERS)
Clock Synchronization
Clock synchronization occurs after the devices have
started arbitration. This is performed using a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high transition of this clock may not change the state of the SCL
line, if another device clock is still within its low period.
The SCL line is held low by the device with the longest
low period. Devices with shorter low periods enter a
high wait state, until the SCL line comes high. When the
SCL line comes high, all devices start counting off their
high periods. The first device to complete its high
period will pull the SCL line low. The SCL line high time
is determined by the device with the shortest high
period, Figure 9-15.
FIGURE 9-15:
Transmitter 1 Loses Arbitration
DATA 1 SDA
CLOCK
SYNCHRONIZATION
Wait
State
DATA 1
Start Counting
HIGH Period
DATA 2
CLK
1
SDA
CLK
2
SCL
Counter
Reset
SCL
Masters that also incorporate the slave function and
have lost arbitration, must immediately switch over to
Slave-Receiver mode. This is because the winning
master-transmitter may be addressing it.
Arbitration is not allowed between:
• A Repeated START condition
• A STOP condition and a data bit
• A Repeated START condition and a STOP
condition
Care needs to be taken to ensure that these conditions
do not occur.
DS39544B-page 68
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
9.3
SSP I 2C Operation
The SSP module in I 2C mode fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementations of the master functions. The SSP module implements the standard mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC bits. The SSP module functions are
enabled by setting SSP enable bit, SSPEN
(SSPCON).
FIGURE 9-16:
SSP BLOCK DIAGRAM
(I2C MODE)
Write
SSPBUF reg
RC3/SCK/SCL
Shift
Clock
SSPSR reg
RC4/
SDI/
SDA
MSb
LSb
Match Detect
Addr Match
SSPADD reg
START and
STOP bit Detect
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
• I 2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I 2C Firmware controlled Master mode, slave is
idle
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address, if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer. The SSPSTAT register is read only.
Internal
Data Bus
Read
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow
one of the following I 2C modes to be selected:
Set, Reset
S, P bits
(SSPSTAT reg)
The SSP module has five registers for I2C operation.
These are the:
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
•
•
•
•
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 69
PIC16C925/926
9.3.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a)
b)
The buffer full bit BF (SSPSTAT) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1) is set.
Table 9-3 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification as well as the requirement of
the SSP module is shown in timing parameter #100
and parameter #101.
9.3.1.1
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 9-8). The five Most Significant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT) must
specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for a 10-bit address is as follows, with steps 7- 9 for
slave-transmitter:
1.
2.
3.
4.
5.
Addressing
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR is
compared to the value of the SSPADD register. The
TABLE 9-3:
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
6.
7.
8.
9.
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address, if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
BF
SSPOV
0
1
1
0
0
0
1
1
DS39544B-page 70
SSPSR SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Yes
No
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
9.3.1.2
Reception
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT) is
set, or bit SSPOV (SSPCON) is set.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 9-17:
Receiving Address R/W=0
Receiving Data
Receiving Data
ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
1
S
2
3
4
5
6
7
9
8
1
2
SSPIF (PIR1)
3
4
5
6
7
8
9
1
2
3
4
5
6
8
7
9
Cleared in software
BF (SSPSTAT)
P
Bus Master
terminates
transfer
SSPBUF register is read
SSPOV (SSPCON)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
9.3.1.3
Transmission
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR register. Then, pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 9-18).
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 9-18:
Receiving Address
SDA
SCL
A7
S
As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of the ninth
SCL input pulse. If the SDA line was high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, pin
RC3/SCK/SCL should be enabled by setting bit CKP.
A6
1
2
Data in
sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
Cleared in software
SSPIF (PIR1)
BF (SSPSTAT)
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP (SSPCON)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 71
PIC16C925/926
9.3.2
MASTER MODE
9.3.3
Master mode of operation is supported, in firmware,
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET, or when the
SSP module is disabled. The STOP and START bits
will toggle based on the START and STOP conditions.
Control of the I 2C bus may be taken when the P bit is
set, or the bus is idle with both the S and P bits clear.
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP and
START bits will toggle based on the START and STOP
conditions. Control of the I 2C bus may be taken when
bit P (SSPSTAT) is set, or the bus is idle, with both
the S and P bits clear. When the bus is busy, enabling
the SSP interrupt will generate the interrupt when the
STOP condition occurs.
In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC bit(s).
The output level is always low, irrespective of the
value(s) in PORTC. So when transmitting data, a
'1' data bit must have the TRISC bit set (input) and
a '0' data bit must have the TRISC bit cleared (output). The same scenario is true for the SCL line with the
TRISC bit.
In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC). There are two stages
where this arbitration can be lost, they are:
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
• Data transfer byte transmitted/received
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
Master mode of operation can be done with either the
Slave mode idle (SSPM3:SSPM0 = 1011), or with the
slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
REGISTERS ASSOCIATED WITH I2C OPERATION
TABLE 9-4:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other
RESETS
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF TMR2IF TMR1IF
00-- 0000
00-- 0000
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE CCP1IE TMR2IE TMR1IE
00-- 0000
00-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
0000 0000
14h
SSPCON
WCOL
94h
SSPSTAT
SMP
CKE
—
—
87h
Legend:
TRISC
SSPOV SSPEN
D/A
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
PORTC Data Direction Control Register
UA
BF
0000 0000
0000 0000
0000 0000
0000 0000
--11 1111
--11 1111
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by SSP in I2C mode.
DS39544B-page 72
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 9-19:
IDLE_MODE (7-bit):
if (Addr_match)
OPERATION OF THE I 2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE
{
Set interrupt;
if (R/W = 1)
{
Send ACK = 0;
set XMIT_MODE;
}
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((SSPBUF = Full) OR (SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
else
{
transfer SSPSR SSPBUF;
send ACK = 0;
}
Receive 8-bits in SSPSR;
Set interrupt;
XMIT_MODE:
While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if ( ACK Received = 1)
{
End of transmission;
Go back to IDLE_MODE;
}
else if ( ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{
PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((SSPBUF = Full) OR ((SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
else
{
Set UA = 1;
Send ACK = 0;
While (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{
PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1))
{
if (PRIOR_ADDR_MATCH)
{
send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 73
PIC16C925/926
NOTES:
DS39544B-page 74
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
10.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has four registers. These registers
are:
•
•
•
•
The Analog-to-Digital (A/D) Converter module has five
inputs.
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input
into the converter. The converter then generates a digital result of this analog level via successive approximation. The A/D conversion of the analog input signal
results in a corresponding 10-bit digital number. The
A/D module has high and low voltage reference input,
that is software selectable to some combination of VDD,
VSS, RA2 or RA3.
The ADCON0 register, shown in Register 10-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 10-2, configures the functions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage reference), or as digital I/O.
Additional information on using the A/D module can be
found in the PIC® Mid-Range MCU Family Reference
Manual (DS33023).
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To
operate in SLEEP, the A/D clock must be derived from
the A/D’s internal RC oscillator.
REGISTER 10-1:
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register0 (ADCON0)
A/D Control Register1 (ADCON1)
ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 0
bit 7-6
ADCS: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3
CHS: Analog Channel Select bits
000 = channel 0 (RA0/AN0)
001 = channel 1 (RA1/AN1)
010 = channel 2 (RA2/AN2)
011 = channel 3 (RA3/AN3)
100 = channel 4 (RA5/AN4)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
Unimplemented: Read as '0'
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 75
PIC16C925/926
REGISTER 10-2:
ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4
Unimplemented: Read as '0'
bit 3-0
PCFG: A/D Port Configuration Control bits:
PCFG
AN4
RA5
0000
0001
0010
0011
0100
0101
011x
D
1000
A
VREF-
CHAN/
Refs(1)
VDD
VSS
5/0
RA3
VSS
4/1
VDD
VSS
5/0
RA3
VSS
4/1
VDD
VSS
3/0
RA3
VSS
2/1
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
A
A
A
A
A
A
VREF+
A
A
A
A
A
A
A
A
A
VREF+
A
A
A
D
A
D
A
A
D
VREF+
D
A
A
D
D
D
D
VDD
VSS
0/0
VREF+
VREF-
A
A
RA3
RA2
3/2
VREF+
1001
A
A
A
A
A
VDD
VSS
5/0
1010
A
VREF+
A
A
A
RA3
VSS
4/1
1011
A
VREF+
VREF-
A
A
RA3
RA2
3/2
1100
A
VREF+
VREF-
A
A
RA3
RA2
3/2
1101
D
VREF+
VREF-
A
A
RA3
RA2
2/2
1110
D
D
D
D
A
VDD
VSS
1/0
1111
D
VREF+
VREF-
D
A
RA3
RA2
1/2
A = Analog input
D = Digital I/O
Note 1: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0) is cleared
and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 10-1.
DS39544B-page 76
x = Bit is unknown
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
The following steps should be followed for doing an A/D
conversion:
1.
2.
3.
4.
Configure the A/D module:
• Configure analog pins/voltage reference/
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
FIGURE 10-1:
5.
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
(interrupts disabled)
OR
6.
7.
• Waiting for the A/D interrupt
Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
A/D BLOCK DIAGRAM
CHS
100
RA5/AN4
VAIN
011
(Input Voltage)
RA3/AN3/VREF+
010
RA2/AN2/VREF001
RA1/AN1
VDD
A/D
Converter
000
RA0/AN0
VREF+
(Reference
Voltage)
PCFG
VREF(Reference
Voltage)
VSS
PCFG
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 77
PIC16C925/926
10.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 10-2. The maximum recommended impedance for analog sources is 10 k. As
EQUATION 10-1:
TACQ =
=
=
TC =
=
=
TACQ =
=
the impedance is decreased, the acquisition time may
be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time,
Equation 10-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC® Mid-Range Reference Manual (DS33023).
ACQUISITION TIME EXAMPLE
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
2S + TC + [(Temperature -25°C)(0.05S/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1k + 7k + 10k) In(0.0004885)
16.47S
2S + 16.47S + [(50°C -25C)(0.05S/C)
19.72S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 10-2:
ANALOG INPUT MODEL
VDD
RS
VA
ANx
CPIN
5 pF
VT = 0.6V
VT = 0.6V
RIC 1k
Sampling
Switch
SS RSS
CHOLD
= DAC Capacitance
= 120 pF
I LEAKAGE
± 500 nA
VSS
Legend CPIN
= input capacitance
= threshold voltage
VT
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
10.2
Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
DS39544B-page 78
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
A/D conversion requires a minimum 12TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
•
•
•
•
Table 10-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2TOSC
8TOSC
32TOSC
Internal A/D module RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
TABLE 10-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS
Max.
2TOSC
00
1.25 MHz
8TOSC
01
5 MHz
32TOSC
10
20 MHz
RC(1, 2, 3)
11
(Note 1)
Note 1: The RC source has a typical TAD time of 4 s, but can vary between 2-6 s.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 79
PIC16C925/926
10.3
Configuring Analog Port Pins
10.4
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2TAD wait is required before the next
acquisition is started. After this 2TAD wait, acquisition
on the selected channel is automatically started. After
this, the GO/DONE bit can be set to start the
conversion.
The A/D operation is independent of the state of the
CHS bits and the TRIS bits.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
In Figure 10-3, after the GO bit is set, the first time segment has a minimum of TCY and a maximum of TAD.
Note:
2: Analog levels on any pin that is defined as
a digital input (including the AN
pins), may cause the input buffer to consume current that is out of the device
specifications.
FIGURE 10-3:
A/D Conversions
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b9
b8
b7
b6
b5
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
10.4.1
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
A 2TAD wait is necessary before the next
acquisition is started.
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justification. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.
DS39544B-page 80
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 10-4:
A/D RESULT JUSTIFICATION
10-Bit Result
ADFM = 0
ADFM = 1
7
0
2107
7
0765
0000 00
0000 00
ADRESH
ADRESL
ADRESH
10-bit Result
Left Justified
A/D Operation During SLEEP
Turning off the A/D places the A/D module in its lowest
current consumption state.
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
Note:
10.6
Address
0Bh
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS = 11). To allow the conversion to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. All A/D input pins are configured as analog inputs.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
TABLE 10-2:
ADRESL
10-bit Result
Right Justified
10.5
0
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
REGISTERS/BITS ASSOCIATED WITH A/D
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
POR,
BOR
MCLR,
WDT
0000 000x 0000 000u
0Ch
PIR1
LCDIF
ADIF
(1)
(1)
SSPIF
CCP1IF
TMR2IF TMR1IF
8Ch
PIE1
LCDIE
ADIE
(1)
(1)
SSPIE
CCP1IE
TMR2IE TMR1IE r0rr 0000 r0rr 0000
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx uuuu uuuu
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
r0rr 0000 r0rr 0000
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
9Fh
ADCON1
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
--0- 0000
85h
TRISA
—
—
PORTA Data Direction Register
--11 1111 --11 1111
05h
PORTA
—
—
PORTA Data Latch when written: PORTA pins when read
--0x 0000 --0u 0000
--0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved; always maintain these bits clear.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 81
PIC16C925/926
NOTES:
DS39544B-page 82
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
11.0
LCD MODULE
The LCD module generates the timing control to drive
a static or multiplexed LCD panel, with support for up to
32 segments multiplexed with up to four commons. It
also provides control of the LCD pixel data.
The interface to the module consists of 3 control registers (LCDCON, LCDSE, and LCDPS), used to define
the timing requirements of the LCD panel and up to 16
LCD data registers (LCD00-LCD15) that represent the
array of the pixel data. In normal operation, the control
registers are configured to match the LCD panel being
used. Primarily, the initialization information consists of
REGISTER 11-1:
selecting the number of commons required by the LCD
panel, and then specifying the LCD frame clock rate to
be used by the panel.
Once the module is initialized for the LCD panel, the
individual bits of the LCD data registers are cleared/set
to represent a clear/dark pixel, respectively.
Once the module is configured, the LCDEN
(LCDCON) bit is used to enable or disable the LCD
module. The LCD panel can also operate during
SLEEP by clearing the SLPEN (LCDCON) bit.
Figure 11-2 through Figure 11-5 provides waveforms
for static, half-duty cycle, one-third-duty cycle, and
quarter-duty cycle drives.
LCDCON REGISTER (ADDRESS 10Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LCDEN
SLPEN
WERR
BIAS
CS1
CS0
LMUX1
LMUX0
bit 7
bit 0
bit 7
LCDEN: Module Drive Enable bit
1 = LCD drive enabled
0 = LCD drive disabled
bit 6
SLPEN: LCD Display Enabled to SLEEP bit
1 = LCD module will stop driving in SLEEP
0 = LCD module will continue driving in SLEEP
bit 5
WERR: Write Failed Error bit
1 = System tried to write LCDD register during disallowed time. (Must be reset in software.)
0 = No error
bit 4
BIAS: Bias Generator Enable bit
0 = Internal bias generator powered down, bias is expected to be provided externally
1 = Internal bias generator enabled, powered up
bit 3-2
CS: Clock Source bits
00 = FOSC/256
01 = T1CKI (Timer1)
1x = Internal RC oscillator
bit 1-0
LMUX: Common Selection bits
Specifies the number of commons
00 = Static(COM0)
01 = 1/2 (COM0, 1)
10 = 1/3 (COM0, 1, 2)
11 = 1/4 (COM0, 1, 2, 3)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39544B-page 83
PIC16C925/926
FIGURE 11-1:
LCD MODULE BLOCK DIAGRAM
128
LCD
RAM
32 x 4
Data Bus
to
SEG
To I/O Pads
32
MUX
Timing Control
LCDCON
COM3:COM0
To I/O Pads
LCDPS
LCDSE
Internal RC osc
Clock
Source
Select
and
Divide
T1CKI
FOSC/4
REGISTER 11-2:
LCDPS REGISTER (ADDRESS 10Eh)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
LP3
LP2
LP1
LP0
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3-0
LP: Frame Clock Prescale Selection bits (see Section 11.1.2)
LMUX1:LMUX0
Multiplex
Frame Frequency
00
Static
Clock source/(128 * (LP3:LP0 + 1))
01
1/2
Clock source/(128 * (LP3:LP0 + 1))
10
1/3
Clock source/(96 * (LP3:LP0 + 1))
11
1/4
Clock source/(128 * (LP3:LP0 + 1))
Legend:
DS39544B-page 84
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 11-2:
WAVEFORMS IN STATIC DRIVE
Liquid Crystal Display
and Terminal Connection
1/1 V
PIN
COM0
0/1 V
COM0
1/1 V
PIN
SEG0
0/1 V
SEG7
1/1 V
SEG6
PIN
SEG1
SEG5
0/1 V
SEG4
SEG3
SEG2
SEG0
SEG1
1/1 V
COM0 - SEG0
Selected Waveform
0/1 V
-1/1 V
1 frame
tf
COM0 - SEG1
Non-selected Waveform
2001-2013 Microchip Technology Inc.
Preliminary
0/1 V
DS39544B-page 85
PIC16C925/926
FIGURE 11-3:
WAVEFORMS IN HALF-DUTY CYCLE DRIVE (B TYPE)
Liquid Crystal Display
and Terminal Connection
2/2 V
PIN
COM0
1/2 V
0/2 V
2/2 V
COM1
PIN
COM1
1/2 V
0/2 V
COM0
2/2 V
PIN
SEG0
0/2 V
2/2 V
PIN
SEG1
SEG3
SEG2
SEG1
SEG0
0/2 V
2/2 V
1/2 V
COM0 - SEG0
Selected Waveform
0/2 V
-1/2 V
-2/2 V
2/2 V
0/2 V
COM0 - SEG1
Non-selected Waveform
-2/2 V
1 frame
tf
DS39544B-page 86
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 11-4:
WAVEFORMS IN ONE-THIRD DUTY CYCLE DRIVE (B TYPE)
3/3 V
Liquid Crystal Display
and Terminal Connection
PIN
COM0
2/3 V
1/3 V
0/3 V
COM2
COM1
3/3 V
2/3 V
PIN
COM1
1/3 V
0/3 V
COM0
3/3 V
2/3 V
PIN
COM2
1/3 V
0/3 V
3/3 V
2/3 V
PIN
SEG0
1/3 V
0/3 V
3/3 V
SEG0
SEG1
SEG2
2/3 V
PIN
SEG1
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
0/3 V
COM0 - SEG1
Selected Waveform
-1/3 V
-2/3 V
-3/3 V
1/3 V
0/3 V
COM0 - SEG0
Non-selected Waveform
-1/3 V
1 frame
tf
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 87
PIC16C925/926
FIGURE 11-5:
WAVEFORMS IN QUARTER-DUTY CYCLE DRIVE (B TYPE)
3/3 V
Liquid Crystal Display
and Terminal Connection
COM3
2/3 V
PIN
COM0
1/3 V
0/3 V
COM2
COM1
3/3 V
2/3 V
PIN
COM1
1/3 V
0/3 V
COM0
3/3 V
PIN
COM2
2/3 V
1/3 V
0/3 V
3/3 V
PIN
COM3
2/3 V
1/3 V
0/3 V
3/3 V
SEG0
SEG1
2/3 V
PIN
SEG0
1/3 V
0/3 V
3/3 V
2/3 V
PIN
SEG1
1/3 V
0/3 V
3/3 V
2/3 V
1/3 V
COM3 - SEG0
Selected Waveform
0/3 V
-1/3 V
-2/3 V
-3/3 V
1/3 V
COM0 - SEG0
Non-selected Waveform
0/3 V
-1/3 V
1 frame
tf
DS39544B-page 88
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
LCD Timing
The second source is the Timer1 external oscillator.
This oscillator provides a lower speed clock which may
be used to continue running the LCD while the processor is in SLEEP. It is assumed that the frequency provided on this oscillator will be 32 kHz. To use the
Timer1 oscillator as a LCD module clock source, it is
only necessary to set the T1OSCEN (T1CON) bit.
The LCD module has 3 possible clock source inputs
and supports static, 1/2, 1/3, and 1/4 multiplexing.
TIMING CLOCK SOURCE
SELECTION
The clock sources for the LCD timing generation are:
The third source is the system clock divided by 256.
This divider ratio is chosen to provide about 32 kHz
output when the external oscillator is 8 MHz. The
divider is not programmable. Instead the LCDPS register is used to set the LCD frame clock rate.
• Internal RC oscillator
• Timer1 oscillator
• System clock divided by 256
The first timing source is an internal RC oscillator which
runs at a nominal frequency of 14 kHz. This oscillator
provides a lower speed clock which may be used to
continue running the LCD while the processor is in
SLEEP. The RC oscillator will power-down when it is
not selected or when the LCD module is disabled.
256
CPCLK
TMR1 32 kHz
Crystal Oscillator
4
Static
2
1/2
4-bit Programmable
Prescaler
32
LCDCLK
FOSC
LCD CLOCK GENERATION
LCDPH
FIGURE 11-6:
All of the clock sources are selected with bits CS1:CS0
(LCDCON). Refer to Register 11-1 for details of
the register programming.
COMnLCK
11.1.1
COMn
11.1
1,2,3,4
Ring Counter
1/3
1/4
LCDPS
Internal RC Oscillator
Nominal FRC = 14 kHz
CS1:CS0
LMUX1:LMUX0
LMUX1:LMUX0
internal
Data Bus
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 89
PIC16C925/926
11.1.2
MULTIPLEX TIMING GENERATION
TABLE 11-2:
The timing generation circuitry will generate one to four
common clocks based on the display mode selected.
The mode is specified by bits LMUX1:LMUX0
(LCDCON). Table 11-1 shows the formulas for
calculating the frame frequency.
APPROXIMATE FRAME
FREQUENCY (IN Hz)
USING TIMER1 @ 32.768 kHz
OR FOSC @ 8 MHz
LP3:LP0
Static
1/2
1/3
1/4
2
85
85
114
85
FRAME FREQUENCY
FORMULAS
3
64
64
85
64
4
51
51
68
51
Multiplex
Frame Frequency =
5
43
43
57
43
Static
Clock source/(128 * (LP3:LP0 + 1))
6
37
37
49
37
1/2
Clock source/(128 * (LP3:LP0 + 1))
7
32
32
43
32
1/3
Clock source/(96 * (LP3:LP0 + 1))
1/4
Clock source/(128 * (LP3:LP0 + 1))
TABLE 11-1:
DS39544B-page 90
TABLE 11-3:
Preliminary
APPROXIMATE FRAME
FREQUENCY (IN Hz)
USING INTERNAL RC OSC
@ 14 kHz
LP3:LP0
Static
1/2
1/3
1/4
0
109
109
146
109
1
55
55
73
55
2
36
36
49
36
3
27
27
36
27
2001-2013 Microchip Technology Inc.
PIC16C925/926
11.2
LCD Interrupts
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver, such as a Microchip AY0438,
can be synchronized for segment data update to the
LCD frame.
FIGURE 11-7:
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(TFINT), as shown in Figure 11-7. The LCD controller
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (TFWR). New data
must be written within TFWR, as this is when the LCD
controller will begin to access the data for the next
frame.
EXAMPLE WAVEFORMS AND INTERRUPT TIMING
IN QUARTER-DUTY CYCLE DRIVE
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
3/3 V
2/3 V
1/3 V
0/3 V
COM0
3/3 V
2/3 V
1/3 V
0/3 V
COM1
3/3 V
2/3 V
1/3 V
0/3 V
COM2
3/3 V
2/3 V
1/3 V
0/3 V
COM3
1 Frame
TFINT
Frame
Boundary
TFWR
Frame
Boundary
TFWR = TFRAME/(LMUX1:LMUX0 + 1) + TCY/2
TFINT = (TFWR /2 - (2TCY + 40 ns)) minimum = 1.5(TFRAME/4) - (2TCY + 40ns)
(TFWR /2 - (1TCY + 40 ns)) maximum = 1.5(TFRAME/4) - (1TCY + 40 ns)
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 91
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11.3
11.3.1
Pixel Control
Table 11-4 shows the correlation of each bit in the
LCDD registers to the respective common and segment signals.
LCDD (PIXEL DATA) REGISTERS
The pixel registers contain bits which define the state of
each pixel. Each bit defines one unique pixel.
REGISTER 11-3:
Any LCD pixel location not being used for display can
be used as general purpose RAM.
GENERIC LCDD REGISTER LAYOUT
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
SEGs
COMc
bit 7
bit 7-0
bit 0
SEGsCOMc: Pixel Data bit for Segment S and Common C
1 = Pixel on (dark)
0 = Pixel off (clear)
Legend:
DS39544B-page 92
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16C925/926
11.4
Operation During SLEEP
The LCD module can operate during SLEEP. The
selection is controlled by bit SLPEN (LCDCON).
Setting the SLPEN bit allows the LCD module to go to
SLEEP. Clearing the SLPEN bit allows the module to
continue to operate during SLEEP.
If a SLEEP instruction is executed and SLPEN = '1', the
LCD module will cease all functions and go into a very
low current consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines. Figure
11-8 shows this operation. To ensure that the LCD completes the frame, the SLEEP instruction should be executed immediately after a LCD frame boundary. The
LCD interrupt can be used to determine the frame
boundary. See Section 11.2 for the formulas to calculate the delay.
FIGURE 11-8:
If a SLEEP instruction is executed and SLPEN = '0', the
module will continue to display the current contents of
the LCDD registers. To allow the module to continue
operation while in SLEEP, the clock source must be
either the internal RC oscillator or Timer1 external
oscillator. While in SLEEP, the LCD data cannot be
changed. The LCD module current consumption will
not decrease in this mode, however, the overall consumption of the device will be lower due to shut-down
of the core and other peripheral functions.
Note:
The internal RC oscillator or external
Timer1 oscillator must be used to operate
the LCD module during SLEEP.
SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS1:CS0 = 00
3/3V
Pin
COM0
2/3V
1/3V
0/3V
3/3V
Pin
COM1
2/3V
1/3V
0/3V
3/3V
2/3V
Pin
COM3
1/3V
0/3V
3/3V
2/3V
Pin
SEG0
1/3V
0/3V
Interrupted
Frame
Wake-up
SLEEP Instruction Execution
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 93
PIC16C925/926
11.4.1
SEGMENT ENABLES
EXAMPLE 11-1:
The LCDSE register is used to select the pin function
for groups of pins. The selection allows each group of
pins to operate as either LCD drivers or digital only
pins. To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared.
If the pin is a digital I/O the corresponding TRIS bit controls the data direction. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS
register.
BCF
BSF
BCF
BCF
MOVLW
MOVWF
. . .
STATUS,RP0
STATUS,RP1
LCDCON,LMUX1
LCDCON,LMUX0
0xFF
LCDSE
EXAMPLE 11-2:
Note 1: On a Power-on Reset, these pins are
configured as LCD drivers.
BCF
BSF
BSF
BCF
MOVLW
MOVWF
. . .
2: The LMUX1:LMUX0 takes precedence
over the LCDSE bit settings for pins RD7,
RD6 and RD5.
REGISTER 11-4:
STATIC MUX WITH 32
SEGMENTS
;Select Bank 2
;
;Select Static MUX
;
;Make PortD,E,F,G
;LCD pins
;configure rest of LCD
ONE-THIRD DUTY CYCLE
WITH 13 SEGMENTS
STATUS,RP0
STATUS,RP1
LCDCON,LMUX1
LCDCON,LMUX0
0x87
LCDSE
;Select Bank 2
;
;Select 1/3 MUX
;
;Make PORTD &
;PORTE LCD pins
;configure rest of LCD
LCDSE REGISTER (ADDRESS 10Dh)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SE29
SE27
SE20
SE16
SE12
SE9
SE5
SE0
bit 7
bit 0
bit 7
SE29: Pin Function Select RD7/COM1/SEG31 - RD5/COM3/SEG29
1 = Pins have LCD drive function
0 = Pins have digital Input function
bit 6
SE27: Pin Function Select RG7/SEG28 and RE7/SEG27
1 = Pins have LCD drive function
0 = Pins have LCD drive function
bit 5
SE20: Pin Function Select RG6/SEG26 - RG0/SEG20
1 = Pins have LCD drive function
0 = Pins have digital Input function
bit 4
SE16: Pin Function Select RF7/SEG19 - RF4/SEG16
1 = Pins have LCD drive function
0 = Pins have digital Input function
bit 3
SE12: Pin Function Select RF3/SEG15 - RF0/SEG12
1 = Pins have LCD drive function
0 = Pins have digital Input function
bit 2
SE9: Pin Function Select RE6/SEG11 - RE4/SEG09
1 = Pins have LCD drive function
0 = Pins have digital Input function
bit 1
SE5: Pin Function Select RE3/SEG08 - RE0/SEG05
1 = Pins have LCD drive function
0 = Pins have digital Input function
bit 0
SE0: Pin Function Select RD4/SEG04 - RD0/SEG00
1 = Pins have LCD drive function
0 = Pins have digital Input function
Legend:
DS39544B-page 94
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16C925/926
11.5
Voltage Generation
pump. The charge pump boosts VLCD1 into VLCD2 =
2*VLCD1 and VLCD3 = 3 * VLCD1. When the charge
pump is not operating, Vlcd3 will be internally tied to
VDD. See the Electrical Specifications section for
charge pump capacitor and potentiometer values.
There are two methods for LCD voltage generation:
internal charge pump, or external resistor ladder.
11.5.1
CHARGE PUMP
11.5.2
The LCD charge pump is shown in Figure 11-9. The
1.0V - 2.3V regulator will establish a stable base voltage from the varying battery voltage. This regulator is
adjustable through the range by connecting a variable
external resistor from VLCDADJ to ground. The potentiometer provides contrast adjustment for the LCD. This
base voltage is connected to VLCD1 on the charge
FIGURE 11-9:
EXTERNAL R-LADDER
The LCD module can also use an external resistor ladder (R-Ladder) to generate the LCD voltages.
Figure 11-9 shows external connections for static and
1/3 bias. The VGEN (LCDCON) bit must be cleared
to use an external R-Ladder.
CHARGE PUMP AND RESISTOR LADDER
CPCLK
VGEN
Control
Logic
3
2
C
VDD
C
2
3
10 A
3
Regulator
C+ VGEN
2
VGEN
VLCD3
VLCD2
VLCD1
VLCD0
VLCDADJ
VLCD3
VLCD2
VLCD1
C1
100 k*
0.47 F*
0.47 F*
0.47 F*
130 k*
10 k*
10 k*
VLCD3
10 k*
VLCD3
10 k*
To
LCD
Drivers
C2
0.47 F*
Connections for
internal charge
pump, VGEN = 1
5 k*
Connections for
external R-ladder,
1/3 Bias,
VGEN = 0
5 k*
Connections for
external R-ladder,
Static Bias,
VGEN = 0
* These values are provided for design guidance only and should be optimized to the application by the designer.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 95
PIC16C925/926
11.6
Configuring the LCD Module
4.
The following is the sequence of steps to follow to configure the LCD module.
5.
1.
Select the frame clock prescale using bits
LP3:LP0 (LCDPS).
Configure the appropriate pins to function as
segment drivers using the LCDSE register.
Configure the LCD module for the following
using the LCDCON register:
- Multiplex mode and Bias, bits
LMUX1:LMUX0
- Timing source, bits CS1:CS0
- Voltage generation, bit VGEN
- SLEEP mode, bit SLPEN
2.
3.
TABLE 11-4:
6.
Write initial values to pixel data registers,
LCDD00 through LCDD15.
Clear LCD interrupt flag, LCDIF (PIR1), and
if desired, enable the interrupt by setting bit
LCDIE (PIE1).
Enable the LCD module, by setting bit LCDEN
(LCDCON).
SUMMARY OF REGISTERS ASSOCIATED WITH THE LCD MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0Ch
PIR1
LCDIF
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
00-- 0000
00-- 0000
8Ch
PIE1
LCDIE
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
00-- 0000
00-- 0000
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
LCDD00
SEG07
COM0
SEG06
COM0
SEG05
COM0
SEG04
COM0
SEG03
COM0
SEG02
COM0
SEG01
COM0
SEG00
COM0
xxxx xxxx
uuuu uuuu
LCDD01
SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG09
COM0
SEG08
COM0
xxxx xxxx
uuuu uuuu
112h
LCDD02
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
xxxx xxxx
uuuu uuuu
113h
LCDD03
SEG31
COM0
SEG30
COM0
SEG29
COM0
SEG28
COM0
SEG27
COM0
SEG26
COM0
SEG25
COM0
SEG24
COM0
xxxx xxxx
uuuu uuuu
114h
LCDD04
SEG07
COM1
SEG06
COM1
SEG05
COM1
SEG04
COM1
SEG03
COM1
SEG02
COM1
SEG01
COM1
SEG00
COM1
xxxx xxxx
uuuu uuuu
LCDD05
SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG09
COM1
SEG08
COM1
xxxx xxxx
uuuu uuuu
116h
LCDD06
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
xxxx xxxx
uuuu uuuu
117h
LCDD07
SEG31
COM1(1)
SEG30
COM1
SEG29
COM1
SEG28
COM1
SEG27
COM1
SEG26
COM1
SEG25
COM1
SEG24
COM1
xxxx xxxx
uuuu uuuu
118h
LCDD08
SEG07
COM2
SEG06
COM2
SEG05
COM2
SEG04
COM2
SEG03
COM2
SEG02
COM2
SEG01
COM2
SEG00
COM2
xxxx xxxx
uuuu uuuu
LCDD09
SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG09
COM2
SEG08
COM2
xxxx xxxx
uuuu uuuu
11Ah
LCDD10
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
xxxx xxxx
uuuu uuuu
11Bh
LCDD11
SEG31
COM2(1)
SEG30
COM2(1)
SEG29
COM2
SEG28
COM2
SEG27
COM2
SEG26
COM2
SEG25
COM2
SEG24
COM2
xxxx xxxx
uuuu uuuu
11Ch
LCDD12
SEG07
COM3
SEG06
COM3
SEG05
COM3
SEG04
COM3
SEG03
COM3
SEG02
COM3
SEG01
COM3
SEG00
COM3
xxxx xxxx
uuuu uuuu
LCDD13
SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG09
COM3
SEG08
COM3
xxxx xxxx
uuuu uuuu
11Eh
LCDD14
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
xxxx xxxx
uuuu uuuu
11Fh
LCDD15
SEG31
COM3(1)
SEG30
COM3(1)
SEG29
COM3(1)
SEG28
COM3
SEG27
COM3
SEG26
COM3
SEG25
COM3
SEG24
COM3
xxxx xxxx
uuuu uuuu
10Dh
LCDSE
SE29
SE27
SE20
SE16
SE12
SE9
SE5
SE0
1111 1111
1111 1111
10Eh
LCDPS
—
—
—
—
LP3
LP2
LP1
LP0
---- 0000
---- 0000
10Fh
LCDCON
LCDEN
SLPEN
—
VGEN
CS1
CS0
LMUX1
LMUX0
00-0 0000
00-0 0000
Address
110h
111h
115h
119h
11Dh
Value on all
other
RESETS
0000 000u
Legend:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the LCD module.
Note 1: These pixels do not display, but can be used as general purpose RAM.
DS39544B-page 96
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
12.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors are special circuits to deal with the needs of real
time applications. The PIC16CXXX family has a host of
such features, intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection. These are:
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up, or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost, while the LP crystal option
saves power. A set of configuration bits are used to
select various options.
12.1
Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in program memory location 2007h.
The user will note that address 2007h is beyond the user
program memory space and can be accessed only during programming.
The PIC16CXXX has a Watchdog Timer which can be
shut-off only through configuration bits. It runs off its
own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 97
PIC16C925/926
REGISTER 12-1:
—
—
—
CONFIGURATION WORD (ADDRESS 2007h)
—
—
—
—
BOREN
CP1
CP0
bit13
PWRTE
WDTE
F0SC1
F0SC0
bit0
bit 13-7
Unimplemented
bit 6
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5-4
CP1:CP0: Program Memory Code Protection bits
PIC16C926 (8K program memory):
11 = Code protection off
10 = 0000h to 0FFFh code protected (1/2 protected)
01 = 0000h to 1EFFh code protected (all but last 256 protected)
00 = 0000h to 1FFFh code protected (all protected)
PIC16C925 (4K program memory):
11 = Code protection off
10 = 0000h to 07FFh code protected (1/2 protected)
01 = 0000h to 0EFFh code protected (all but last 256 protected)
00 = 0000h to 0FFFh code protected (all protected)
1000h to 1FFFh wraps around to 0000h to 0FFFh
bit 3
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
DS39544B-page 98
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
12.2
Oscillator Configurations
12.2.1
TABLE 12-1:
Ranges Tested:
OSCILLATOR TYPES
The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
Mode
Freq.
FIGURE 12-1:
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
OSC1
XTAL
C2
RF
OSC2
RS
(Note 1)
Osc Type
LP
XT
HS
Crystal
Freq.
Cap. Range
C1
Cap.
Range
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
These values are for design guidance only.
See notes following this table.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
PIC16CXXX
See Table 12-1 and Table 12-2 for recommended values
of C1 and C2.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
4: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
Note 1: A series resistor may be required for AT strip
cut crystals.
FIGURE 12-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Note 1: Recommended ranges of C1 and C2 are
depicted in Table 12-1.
To Internal
Logic
SLEEP
C1
C2
455 kHz
68 - 100 pF 68 - 100 pF
2.0 MHz
15 - 68 pF
15 - 68 pF
4.0 MHz
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
10 - 68 pF
10 - 68 pF
These values are for design guidance only.
See notes following Table 12-2.
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP, or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications. When in XT, LP, or HS modes, the device can
have an external clock source to drive the
OSC1/CLKIN pin (Figure 12-2).
C1
XT
TABLE 12-2:
12.2.2
CERAMIC RESONATORS
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
PIC16CXXX
Open
OSC2
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 99
PIC16C925/926
12.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used, or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range
and better stability. A well designed crystal oscillator
will provide good performance with TTL gates. Two
types of crystal oscillator circuits can be used: one with
series resonance, or one with parallel resonance.
Figure 12-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides
the negative feedback for stability. The 10 k potentiometer biases the 74AS04 in the linear region. This
could be used for external oscillator designs.
FIGURE 12-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
74AS04
PIC16CXXX
10k
10k
20 pF
Figure 12-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 12-4:
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C components used. Figure 12-5 shows how the R/C combination is connected to the PIC16CXXX. For REXT values
below 2.2 k, the oscillator operation may become
unstable, or stop completely. For very high REXT values
(e.g. 1 M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
REXT between 3 k and 100 k.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance, or package lead frame capacitance.
See characterization data for desired device for RC frequency variation from part to part, due to normal process variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
CLKIN
XTAL
20 pF
12.2.4
See characterization data for desired device for variation of oscillator frequency, due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C, and VDD
values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 1-2 for
waveform).
FIGURE 12-5:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
RC OSCILLATOR MODE
VDD
REXT
330 k
330 k
74AS04
74AS04
To Other
Devices
OSC1
CEXT
74AS04
CLKIN
0.1 F
Internal
Clock
PIC16CXXX
VSS
FOSC/4
XTAL
OSC2/CLKOUT
PIC16CXXX
DS39544B-page 100
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
12.3
RESET
The PIC16C9XX differentiates between various kinds
of RESET:
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
Brown-out Reset (BOR)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-6.
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, and on MCLR Reset during
FIGURE 12-6:
SLEEP. They are not affected by a WDT Wake-up,
which is viewed as the resumption of normal operation.
The TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 12-4.
These bits are used in software to determine the nature
of the RESET. See Table 12-6 for a full description of
RESET states of all registers.
The devices all have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
Module
VDD Rise
Detect
VDD
WDT
Time-out
Reset
Power-on
Reset
Brown-out
Reset
S
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT(2)
Enable OST(2)
Note 1:
2:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
See Table 12-3 for various time-out situations.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 101
PIC16C925/926
12.4
12.4.1
12.4.4
Power-on Reset (POR),
Power-up Timer (PWRT),
Brown-out Reset (BOR) and
Oscillator Start-up Timer (OST)
The configuration bit, BOREN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100S), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer, if enabled, then keeps the device in
RESET for TPWRT (parameter #33, about 72mS). If
VDD should fall below VBOR during TPWRT, the
Brown-out Reset process will restart when VDD rises
above VBOR with the Power-up Timer Reset. The
Power-up Timer is enabled separately from Brown-out
Reset.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating conditions are met.
12.4.5
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT’s time delay allows VDD to rise to an
acceptable level. A configuration bit is provided to
enable/disable the PWRT.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 12-8). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device operating in parallel.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
12.4.3
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 12-7, Figure 12-8, and Figure 12-9 depict
time-out sequences on power-up.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
12.4.2
BROWN-OUT RESET (BOR)
Table 12-5 shows the RESET conditions for some special function registers, while Table 12-6 shows the
RESET conditions for all the registers.
OSCILLATOR START-UP TIMER
(OST)
12.4.6
The Oscillator Start-up Timer (OST), if enabled, provides 1024 oscillator cycle (from OSC1 input) delay
after the PWRT delay (if the PWRT is enabled). This
helps to ensure that the crystal oscillator or resonator
has started and stabilized.
POWER CONTROL/STATUS
REGISTER (PCON)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see if
bit BOR cleared, indicating a BOR occurred. When the
Brown-out Reset is disabled, the state of the BOR bit is
unpredictable and is, therefore, not valid at any time.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
Bit1 is Power-on Reset Status bit POR. It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 12-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
XT, HS, LP
RC
DS39544B-page 102
Wake-up from SLEEP
PWRTE = 1
PWRTE = 0
1024TOSC
—
72 ms + 1024TOSC
72 ms
Preliminary
1024 TOSC
—
2001-2013 Microchip Technology Inc.
PIC16C925/926
TABLE 12-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 12-5:
Condition
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --u0
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
PC + 1
(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 103
PIC16C925/926
TABLE 12-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Power-on Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or
Interrupt
W
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
N/A
N/A
N/A
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000h
0000h
quuu(3)
PC + 1(2)
uuuq quuu(3)
STATUS
0001 1xxx
000q
FSR
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
--0x 0000
--0u 0000
--uu uuuu
PORTB
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
--xx xxxx
--uu uuuu
--uu uuuu
PORTD
0000 0000
0000 0000
uuuu uuuu
PORTE
0000 0000
0000 0000
uuuu uuuu
PCLATH
---0 0000
---0 0000
---u uuuu
INTCON
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
00-- 0000
00-- 0000
uu-- uuuu(1)
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
--00 0000
--uu uuuu
--uu uuuu
TMR2
0000 0000
0000 0000
uuuu uuuu
T2CON
-000 0000
-000 0000
-uuu uuuu
SSPBUF
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
0000 0000
0000 0000
uuuu uuuu
CCPR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
--00 0000
--00 0000
--uu uuuu
ADRES
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
1111 1111
1111 1111
uuuu uuuu
TRISA
--11 1111
--11 1111
--uu uuuu
TRISB
1111 1111
1111 1111
uuuu uuuu
TRISC
--11 1111
--11 1111
--uu uuuu
TRISD
1111 1111
1111 1111
uuuu uuuu
TRISE
1111 1111
1111 1111
uuuu uuuu
PIE1
00-- 0000
00-- 0000
uu-- uuuu
PCON
---- --0-
---- --u-
---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
DS39544B-page 104
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
TABLE 12-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Power-on Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or
Interrupt
PR2
1111 1111
1111 1111
1111 1111
SSPADD
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
0000 0000
0000 0000
uuuu uuuu
ADCON1
---- -000
---- -000
---- -uuu
PORTF
0000 0000
0000 0000
uuuu uuuu
PORTG
0000 0000
0000 0000
uuuu uuuu
LCDSE
1111 1111
1111 1111
uuuu uuuu
LCDPS
---- 0000
---- 0000
---- uuuu
LCDCON
00-0 0000
00-0 0000
uu-u uuuu
LCDD00
to
LCDD15
xxxx xxxx
uuuu uuuu
uuuu uuuu
TRISF
1111 1111
1111 1111
uuuu uuuu
TRISG
1111 1111
1111 1111
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for RESET value for specific condition.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 105
PIC16C925/926
FIGURE 12-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS39544B-page 106
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
12.5
Interrupts
The PIC16C925/926 family has nine sources of
interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts
(pins RB7:RB4)
• A/D Interrupt
• TMR1 overflow interrupt
• TMR2 matches period interrupt
• CCP1 interrupt
• Synchronous serial port interrupt
• LCD module interrupt
Individual interrupt flag bits are set, regardless of the status of their corresponding
mask bit, or the GIE bit.
A global interrupt enable bit, GIE (INTCON),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
FIGURE 12-10:
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the special function register, PIR1. The corresponding interrupt enable bits are contained in special function
register, PIE1, and the peripheral interrupt enable bit is
contained in special function register, INTCON.
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note:
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the RB0/INT pin
or RB Port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs
(Figure 12-11). The latency is the same for one or two
cycle instructions. Individual interrupt flag bits are set,
regardless of the status of their corresponding mask
bit, PEIE bit, or the GIE bit.
INTERRUPT LOGIC
TMR1IF
TMR1IE
TMR0IF
TMR0IE
INTF
INTE
TMR2IF
TMR2IE
Wake-up (If in SLEEP mode)
Interrupt to CPU
RBIF
RBIE
LCDIF
LCDIE
PEIF
PEIE
GIE
CCP1IF
CCP1IE
SSPIF
SSPIE
ADIF
ADIE
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 107
PIC16C925/926
FIGURE 12-11:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
INTF Flag
(INTCON)
1
1
Interrupt Latency 2
5
GIE bit
(INTCON)
INSTRUCTION FLOW
PC
PC
PC+1
PC+1
Instruction
Fetched
Inst (PC)
Inst (PC+1)
Instruction
Executed
Inst (PC-1)
Inst (PC)
—
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single
cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF can be set any time during the Q4-Q1 cycles.
12.5.1
12.5.2
INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 12.8 for details on SLEEP mode.
DS39544B-page 108
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit, TMR0IF (INTCON). The interrupt can be
enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON) (Section 5.0).
12.5.3
PORTB INTCON CHANGE
An input change on PORTB sets flag bit RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON)
(Section 4.2).
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
12.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt, i.e., the W and STATUS registers. This will have to be implemented in software.
Example 12-1 stores and restores the STATUS, W, and
PCLATH registers. The register, W_TEMP, must be
defined in each bank and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
EXAMPLE 12-1:
e)
f)
g)
h)
i)
j)
Stores the W register.
Stores the STATUS register in bank 0.
Stores the PCLATH register.
Executes the ISR code.
Restores the STATUS register (and bank select
bit).
Restores the W and PCLATH registers.
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
W_TEMP
SWAPF
STATUS,W
CLRF
STATUS
MOVWF
STATUS_TEMP
MOVF
PCLATH, W
MOVWF
PCLATH_TEMP
CLRF
PCLATH
BCF
STATUS, IRP
MOVF
FSR, W
MOVWF
FSR_TEMP
:
:(ISR)
:
MOVF
PCLATH_TEMP, W
MOVWF
PCLATH
SWAPF
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
The code in the example:
STATUS
W_TEMP,F
W_TEMP,W
2001-2013 Microchip Technology Inc.
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
;Insert user code here
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
Preliminary
DS39544B-page 109
PIC16C925/926
12.7
Watchdog Timer (WDT)
assigned to the WDT under software control, by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 12.1).
12.7.1
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, prevent it
from timing out and generating a device RESET
condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
12.7.2
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
Max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
WDT PERIOD
Note:
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
FIGURE 12-12:
WDT PROGRAMMING
CONSIDERATIONS
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-6)
0
WDT Timer
Postscaler
M
U
X
1
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable bit
To TMR0 (Figure 5-6)
0
1
MUX
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
FIGURE 12-13:
PSA
SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
Config. bits
(1)
BOREN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
81h, 181h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
DS39544B-page 110
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
12.8
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS) is cleared, the
TO (STATUS) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins that
are hi-impedance inputs, high or low externally, to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (VIHMC).
12.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from RB0/INT pin, RB port change, or
peripheral interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up is cleared when SLEEP is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
12.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
SSP (START/STOP) bit detect interrupt.
SSP transmit or receive in Slave mode
(SPI/I2C).
CCP Capture mode interrupt.
A/D conversion (when A/D clock source is RC).
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
LCD module.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 111
PIC16C925/926
FIGURE 12-14:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF Flag
(INTCON)
Interrupt Latency
(Note 2)
GIE bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
12.9
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
PC+2
Inst(PC + 2)
SLEEP
Inst(PC + 1)
Program Verification/Code
Protection
Microchip does not recommend code protecting windowed devices.
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
After RESET, to place the device into Program/Verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then
supplied to or from the device, depending if the command was a load or a read. For complete details of
serial programming, please refer to the PIC16C6X/7X
Programming Specifications (Literature #DS30228).
FIGURE 12-15:
12.10 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the four Least Significant bits of the
ID location are used.
12.11
PC + 2
XT, HS or LP oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine.
If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
PC+2
Inst(PC + 1)
In-Circuit Serial Programming
PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
External
Connector
Signals
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
PIC16CXXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
DS39544B-page 112
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
13.0
INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXXX instruction set summary in Table 13-2 lists byte-oriented, bitoriented, and literal and control operations.
Table 13-1 shows the opcode field descriptions.
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the address of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
FIGURE 13-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
8
7
OPCODE
0
k (literal)
CALL and GOTO instructions only
11
OPCODE
Field
Description
Register file address (0x00 to 0x7F)
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
Don't care location (= 0 or 1).
The assembler will generate code with x = 0.
x
It is the recommended form of use for compatibility with all Microchip software tools.
Destination select; d = 0: store result in W,
d
d = 1: store result in file register f.
Default is d = 1.
label Label name
TOS
Top-of-Stack
PC
Program Counter
PCLATH Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
Destination either the W register or the
dest
specified register file location
Options
[ ]
f
W
( )
Contents
Assigned to
Register bit field
italics
In the set of
User defined term (font is courier)
All instructions are executed within one single instruction cycle, unless a conditional test is true, or the program counter is changed, as a result of an instruction.
In this case, the execution takes two instruction cycles,
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true, or the
program counter is changed, as a result of an instruction, the instruction execution time is 2 s.
10
Figure 13-1 shows the general formats that the instructions can have.
Note:
k = 8-bit immediate value
13
OPCODE FIELD
DESCRIPTIONS
Table 13-2 lists the instructions recognized by the
MPASMTM assembler.
Literal and control operations
General
13
TABLE 13-1:
0
To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instructions.
All examples use the format ‘0xnn’ to represent a
hexadecimal number.
k (literal)
k = 11-bit immediate value
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 113
PIC16C925/926
TABLE 13-2:
PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS39544B-page 114
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
13.1
Instruction Descriptions
ADDLW
Add Literal and W
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Encoding:
Description:
11
1
Cycles:
1
Q1
Decode
Example:
k
kkkk
kkkk
The contents of the W register are
added to the eight-bit literal 'k' and
the result is placed in the W
register.
Words:
Q Cycle Activity:
111x
ADDWF
ADDLW
Q2
Q3
Q4
Read Process Write to
literal 'k'
data
W
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d
Operation:
(W) + (f) (destination)
Status Affected:
C, DC, Z
Encoding:
00
f [,d]
0111
dfff
ffff
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0, the result is
stored in the W register. If 'd' is 1, the
result is stored back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
Read Process Write to
register 'f' data destination
0x15
Before Instruction:
W = 0x10
Example
FSR,
0
Before Instruction:
W
= 0x17
FSR
= 0xC2
After Instruction:
W = 0x25
2001-2013 Microchip Technology Inc.
ADDWF
After Instruction:
W
= 0xD9
FSR
= 0xC2
Preliminary
DS39544B-page 115
PIC16C925/926
ANDLW
AND Literal with W
ANDWF
AND W with f
Syntax:
[ label ] ANDLW
Syntax:
[ label ] ANDWF
Operands:
0 k 255
Operands:
Operation:
(W) .AND. (k) (W)
0 f 127
d
Status Affected:
Z
Operation:
(W).AND. (f) (destination)
Status Affected:
Z
Encoding:
Description:
11
1
Cycles:
1
Q1
Decode
Example
ANDLW
Before Instruction:
W = 0xA3
After Instruction:
W = 0x03
DS39544B-page 116
kkkk
kkkk
The contents of W register are
AND’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
Words:
Q Cycle Activity:
1001
k
Q2
Q3
Q4
Read Process Write to
literal ‘k’
data
W
00
Encoding:
Description:
0101
f [,d]
dfff
ffff
AND the W register with register 'f'.
If 'd' is 0, the result is stored in the
W register. If 'd' is 1, the result is
stored back in register 'f'.
Words:
1
Cycles:
1
Q1
Q Cycle Activity:
Q2
Q3
Q4
Read
Process Write to
Decode register
data destination
'f'
0x5F
Example
ANDWF
Before Instruction:
W
=
FSR
=
After Instruction
W
=
FSR
=
Preliminary
FSR, 1
0x17
0xC2
0x17
0x02
2001-2013 Microchip Technology Inc.
PIC16C925/926
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] BCF
Syntax:
[ label ] BTFSC f [,b]
Operands:
0 f 127
0b7
Operands:
0 f 127
0b7
Operation:
0 (f)
Operation:
skip if (f) = 0
Status Affected:
None
Status Affected:
None
01
Encoding:
f [,b]
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Q1
Q Cycle Activity:
Q2
Q3
BCF
ffff
Words:
1
Cycles:
1(2)
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
No
Operation
Q3
Q4
FLAG_REG, 7
Before Instruction:
FLAG_REG =
After Instruction:
FLAG_REG =
bfff
If bit 'b' in register 'f' is '1', then the
next instruction is executed.
If bit 'b' in register 'f' is '0', then the
next instruction is discarded, and a
NOP is executed instead, making this a
2TCY instruction.
Q Cycle Activity:
Example
10bb
Description:
Q4
Read
Process
Write
Decode register
data register 'f'
'f'
01
Encoding:
0xC7
If Skip:
0x47
(2nd Cycle)
Q1
Q2
No
No
No
No
Operation Operation Operation Operation
Example
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f)
Status Affected:
None
01
Encoding:
f [,b]
01bb
bfff
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Q1
Q2
Decode
Example
BSF
Before Instruction:
FLAG_REG =
After Instruction:
FLAG_REG =
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction:
PC
= address HERE
Description:
Q Cycle Activity:
HERE
FALSE
TRUE
Q3
ffff
After Instruction:
if FLAG
PC
if FLAG
PC
=
=
=
=
0,
address TRUE
1,
address FALSE
Q4
Read Process
Write
register
data register 'f'
'f'
FLAG_REG,
7
0x0A
0x8A
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 117
PIC16C925/926
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f [,b]
Syntax:
[ label ] CALL k
Operands:
0 f 127
0b VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin .........................................................................................................25 mA
Maximum output current sourced by any I/O pin ...................................................................................................25 mA
Maximum current sunk byall Ports combined .....................................................................................................200 mA
Maximum current sourced by all Ports combined ................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 139
PIC16C925/926
FIGURE 15-1:
PIC16C925/926 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
PIC16C925/926
Voltage
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
20 MHz
Frequency
FIGURE 15-2:
PIC16LC925/926 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
Voltage
5.0 V
4.5 V
PIC16LC925/926
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
10 MHz
Frequency
FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS39544B-page 140
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
15.1
DC Characteristics
PIC16LC925/926
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
PIC16C925/926
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
Param
No.
Sym
VDD
Characteristic
Min
Typ† Max Units
Conditions
Supply Voltage
D001
D001A
PIC16LC925/926
2.5
4.5
—
—
5.5
5.5
V
V
LP, XT and RC osc configuration
HS osc configuration
D001
D001A
PIC16C925/926
4.0
4.5
—
—
5.5
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002
VDR
RAM Data Retention
Voltage (Note 1)
—
1.5
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
VSS
—
V
See Power-on Reset section for details
D004
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
D005
VBOR
Brown-out Reset
voltage trip point
3.65
—
4.35
V
IDD
Supply Current (Note 2)
—
.6
2.0
mA
—
225
48
A
—
2.7
5
mA
D011
—
35
70
A
D012
—
7
10
mA
D010
PIC16LC925/926
D011
D010
PIC16C925/926
†
Note 1:
2:
3:
4:
5:
6:
7:
V/ms See Power-on Reset section for details
(Note 6)
BODEN bit set
XT and RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
XT and RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 4.0V
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on
the current consumption.The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail;
all I/O pins tri-stated, pulled to VDD
MCLR = VDD.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
PWRT must be enabled for slow ramps.
LCDT1 and LCDRC includes the current consumed by the LCD Module and the voltage generation
circuitry. This does not include current dissipated by the LCD panel.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 141
PIC16C925/926
15.1
DC Characteristics
(Continued)
PIC16LC925/926
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
PIC16C925/926
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
Param
No.
Sym
IPD
Characteristic
Min
Typ† Max Units
Conditions
Power-down Current (Note 3)
D020
PIC16LC925/926
—
0.9
5
A
VDD = 3.0V
D020
PIC16C925/926
—
1.5
21
A
VDD = 4.0V
Module Differential Current (Note 5)
IWDT
D021
D021
ILCDT1
D022
D022
D022A
IBOR
D024
ILCDT1
D024
†
Note 1:
2:
3:
4:
5:
6:
7:
Watchdog Timer
PIC16LC925/926
—
6.0
20
A
VDD = 3.0V
Watchdog Timer
PIC16C925/926
—
9.0
25
A
VDD = 4.0V
LCD Voltage
Generation with
internal RC osc enabled
PIC16LC925/926
—
36
50
A
VDD = 3.0V (Note 7)
LCD Voltage
Generation with
internal RC osc enabled
PIC16C925/926
—
40
55
A
VDD = 4.0V (Note 7)
Brown-out Reset
—
100
150
A
BODEN bit set, VDD = 5.0
LCD Voltage
Generation with
Timer1 @ 32.768 kHz
PIC16LC925/926
—
15
29
A
VDD = 3.0V (Note 7)
LCD Voltage
Generation with
Timer1 @ 32.768 kHz
PIC16C925/926
—
33
60
A
VDD = 4.0V (Note 7)
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on
the current consumption.The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail;
all I/O pins tri-stated, pulled to VDD
MCLR = VDD.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
PWRT must be enabled for slow ramps.
LCDT1 and LCDRC includes the current consumed by the LCD Module and the voltage generation
circuitry. This does not include current dissipated by the LCD panel.
DS39544B-page 142
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
15.1
DC Characteristics
(Continued)
PIC16LC925/926
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
PIC16C925/926
(Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
Param
No.
Sym
IT1OSC
D025
D025
IAD
D026
D026
†
Note 1:
2:
3:
4:
5:
6:
7:
Characteristic
Min
Typ† Max Units
Conditions
Timer1 Oscillator
PIC16LC925/926
—
—
50
A
VDD = 3.0V
Timer1 Oscillator
PIC16C925/926
—
—
50
A
VDD = 4.0V
A/D Converter
PIC16LC925/926
—
1.0
—
A
A/D on, not converting
A/D Converter
PIC16C925/926
—
1.0
—
A
A/D on, not converting
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on
the current consumption.The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail;
all I/O pins tri-stated, pulled to VDD
MCLR = VDD.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
PWRT must be enabled for slow ramps.
LCDT1 and LCDRC includes the current consumed by the LCD Module and the voltage generation
circuitry. This does not include current dissipated by the LCD panel.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 143
PIC16C925/926
15.2
DC Characteristics: PIC16C925/926 (Commercial, Industrial)
PIC16LC925/926 (Commercial, Industrial)
DC CHARACTERISTICS
Param
Sym
No.
Characteristic
D030
Input Low Voltage
I/O ports
with TTL buffer
D031
D032
D033
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
VIL
VIH
D040
D040A
D041
D042
D042A
D043
Input High Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
0°C TA +70°C for commercial
Operating voltage VDD range as described in DC spec
Min
VSS
Vss
VSS
VSS
VSS
2.0
0.25VDD
+ 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
Typ†
Max
Units
Conditions
— 0.15VDD
—
0.8V
— 0.2VDD
— 0.2VDD
— 0.3VDD
V
V
V
V
V
For entire VDD range
4.5V VDD 5.5V
—
—
—
VDD
VDD
V
V
4.5V VDD 5.5V
For entire VDD range
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
(Note 1)
(Note 1)
D070
IPURB PORTB Weak Pull-up Current
50
250
400
A VDD = 5V, VPIN = VSS
D060
D061
D063
Input Leakage Current
(Notes 2, 3)
I/O ports
MCLR, RA4/T0CKI
OSC1
—
—
—
—
—
—
1.0
5
5
A Vss VPIN VDD, Pin at hi-Z
A Vss VPIN VDD
A Vss VPIN VDD, XT, HS and LP
osc configuration
—
—
IIL
D080
D083
Output Low Voltage
VOL I/O ports
OSC2/CLKOUT (RC osc mode)
—
—
0.6
0.6
V
V
IOL = 4.0 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V
D090
D092
Output High Voltage
VDD - 0.7 —
VOH I/O ports (Note 3)
OSC2/CLKOUT (RC osc mode) VDD - 0.7 —
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V
IOH = -1.3 mA, VDD = 4.5V
In XT, HS and LP modes when
external clock is used to drive
OSC1.
D100
D101
D102
COSC2
Capacitive Loading Specs on
Output Pins
OSC2 pin
CIO All I/O pins and OSC2 (in RC)
CB SCL, SDA in I2C mode
—
—
15
pF
—
—
—
—
50
400
pF
pF
D150
VDD Open Drain High Voltage
—
—
8.5
V RA4 pin
† Data in “Typ” column is at 5 V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C925/926 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS39544B-page 144
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-3:
LCD VOLTAGE WAVEFORM
D223
D224
VLCD3
VLCD2
VLCD1
VSS
TABLE 15-1:
LCD MODULE ELECTRICAL SPECIFICATIONS
Parameter
No.
Symbol
D200
Characteristic
Min
Typ†
Max
Units
VLCD3
LCD Voltage on pin
VLCD3
VDD - 0.3
—
Vss + 7.0
V
D201
VLCD2
LCD Voltage on pin
VLCD2
Vss - 0.3
—
VLCD3
V
D202
VLCD1
LCD Voltage on pin
VLCD1
Vss - 0.3
—
VLCD3
V
D220
VOH
Output High
Voltage
Max VLCDN - 0.1
—
Max VLCDN
V
COM outputs IOH = 25 A
SEG outputs IOH = 3 A
D221
VOL
Output Low Voltage
Min VLCDN
—
Min VLCDN + 0.1
V
COM outputs IOL = 25 A
SEG outputs IOL = 3 A
D222
FLCDRC
LCDRC Oscillator
Frequency
5
14
22
kHz
VDD = 5V, -40°C to +85°C
D223
TrLCD
Output Rise Time
—
—
200
s
COM outputs Cload = 5,000 pF
SEG outputs Cload = 500 pF
VDD = 5.0V, T = 25C
D224
TfLCD
Output Fall Time(1)
TrLCD - 0.05
TrLCD
—
TrLCD + 0.05
TrLCD
s
COM outputs Cload = 5,000 pF
SEG outputs Cload = 500 pF
VDD = 5.0V, T = 25C
†
Conditions
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: 0 ohm source impedance at VLCD.
TABLE 15-2:
Parameter
No.
VLCD CHARGE PUMP ELECTRICAL SPECIFICATIONS
Symbol
Characteristic
VLCDADJ Regulated Current Output
Min
Typ
Max
Units
—
10
—
A
0.1
A/V
2.3
V
VDD - 0.7V
V
D250
IVADJ
D252
IVADJ/ VDD VLCDADJ Current VDD Rejection
—
—
D265
VVADJ
VLCDADJ Voltage
Limits
PIC16C925/926
1.0
—
PIC16LC925/926
1.0
Conditions
VDD < 3V
Note 1: For design guidance only.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 145
PIC16C925/926
15.3
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
3. TCC:ST (I2C specifications only)
4. Ts (I2C specifications only)
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
output access
BUF
Bus free
2
TCC:ST (I C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
FIGURE 15-4:
LOAD CONDITIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL
=
464
CL
=
50 pF for all pins except OSC2 unless otherwise noted.
15 pF for OSC2 output
DS39544B-page 146
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
15.4
Timing Diagrams and Specifications
FIGURE 15-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 15-3:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
20
MHz HS osc mode
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
TOSC External CLKIN Period
250
—
—
ns XT and RC osc mode
(Note 1)
125
—
—
ns HS osc mode
5
—
—
s LP osc mode
Oscillator Period
250
—
—
ns RC osc mode
(Note 1)
250
—
10,000
ns XT osc mode
125
—
250
ns HS osc mode
5
—
—
s LP osc mode
2
TCY
Instruction Cycle Time (Note 1)
500
—
DC
ns TCY = 4/FOSC
3
TosL, External Clock in (OSC1) High or 50
—
—
ns XT oscillator
TosH Low Time
2.5
—
—
s LP oscillator
10
—
—
ns HS oscillator
—
25
ns XT oscillator
4
TosR, External Clock in (OSC1) Rise or —
TosF
Fall Time
—
—
50
ns LP oscillator
—
—
15
ns HS oscillator
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
FOSC
External CLKIN Frequency
(Note 1)
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 147
PIC16C925/926
FIGURE 15-6:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note:
Refer to Figure 15-4 for load conditions.
TABLE 15-4:
Parameter
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
10
TosH2ckL
OSC1 to CLKOUT
—
75
200
ns
(Note 1)
11
TosH2ckH
OSC1 to CLKOUT
—
75
200
ns
(Note 1)
12
TckR
CLKOUT rise time
—
35
100
ns
(Note 1)
13
TckF
CLKOUT fall time
—
35
100
ns
(Note 1)
14
TckL2ioV
CLKOUT to Port out valid
—
—
0.5TCY + 20
ns
(Note 1)
15
TioV2ckH
Port in valid before CLKOUT
Tosc + 200
—
—
ns
(Note 1)
16
TckH2ioI
Port in hold after CLKOUT
0
—
—
ns
(Note 1)
17
TosH2ioV
OSC1 (Q1 cycle) to
Port out valid
—
50
150
ns
18
TosH2ioI
OSC1 (Q2 cycle) to
Port input invalid
(I/O in hold time)
PIC16C925/926
100
—
—
ns
PIC16LC925/926
200
—
—
ns
19
TioV2osH
Port input valid to OSC1(I/O in setup time)
0
—
—
ns
20
TioR
Port output rise time
PIC16C925/926
—
10
40
ns
PIC16LC925/926
—
—
80
ns
21
TioF
Port output fall time
PIC16C925/926
—
10
40
ns
—
—
80
ns
22††
Tinp
INT pin high or low time
TCY
—
—
ns
23††
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
PIC16LC925/926
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS39544B-page 148
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note:
Refer to Figure 15-4 for load conditions.
TABLE 15-5:
Parameter
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
s
31
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40°C to +85°C
32
TOST
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
33
TPWRT
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +85°C
34
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
s
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 149
PIC16C925/926
FIGURE 15-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 15-4 for load conditions.
TABLE 15-6:
Param
No.
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Symbol
Characteristic
40
Tt0H
T0CKI High Pulse Width
41
Tt0L
T0CKI Low Pulse Width
42
Tt0P
T0CKI Period
45
46
47
Tt1H
Tt1L
Tt1P
T1CKI High
Time
T1CKI Low
Time
T1CKI Input
Period
Min
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
Synchronous, Prescaler = 1
Synchronous, PIC16C925/926
Prescaler =
PIC16LC925/926
2,4,8
Asynchronous PIC16C925/926
PIC16LC925/926
Synchronous, Prescaler = 1
Synchronous, PIC16C925/926
Prescaler =
PIC16LC925/926
2,4,8
Asynchronous PIC16C925/926
PIC16LC925/926
Synchronous PIC16C925/926
PIC16LC925/926
0.5TCY + 20
10
0.5TCY + 20
10
TCY + 40
Greater of:
20 or TCY + 40
N
0.5TCY + 20
15
Typ† Max Units
Conditions
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Must also meet
parameter 42
—
—
—
—
—
—
ns
ns
ns
Must also meet
parameter 47
0.5TCY + 20
15
—
—
—
—
—
—
—
—
ns
ns
ns
ns
25
—
—
ns
30
50
Greater of:
30 or TCY + 40
N
Greater of:
50 or TCY + 40
N
60
100
—
—
—
—
ns
ns
—
—
ns
25
30
50
Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16C925/926
—
—
ns
PIC16LC925/926
—
—
ns
Ft1
Timer1 oscillator input frequency range
DC
—
200 kHz
(oscillator enabled by setting bit T1OSCEN)
48
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
— 7Tosc —
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS39544B-page 150
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-9:
CAPTURE/COMPARE/PWM TIMINGS
RC2/CCP1
(Capture Mode)
50
51
52
RC2/CCP1
(Compare or PWM Mode)
53
Note:
Refer to Figure 15-4 for load conditions.
TABLE 15-7:
CAPTURE/COMPARE/PWM REQUIREMENTS
Parameter
Symbol
No.
50
54
TccL
Characteristic
Input Low Time
Min
No Prescaler
With Prescaler PIC16C925/926
PIC16LC925/926
51
TccH
Input High Time
No Prescaler
With Prescaler PIC16C925/926
PIC16LC925/926
52
TccP
Input Period
53
TccR
Output Rise Time
54
TccF
Output Fall Time
Typ† Max Units
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
PIC16C925/926
—
10
25
ns
PIC16LC925/926
—
25
45
ns
PIC16C925/926
—
10
25
ns
PIC16LC925/926
—
25
45
ns
Conditions
N = prescale value
(1,4 or 16)
† Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 151
PIC16C925/926
FIGURE 15-10:
SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note:
Refer to Figure 15-4 for load conditions.
FIGURE 15-11:
SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note:
Refer to Figure 15-4 for load conditions.
DS39544B-page 152
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
FIGURE 15-12:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note:
Refer to Figure 15-4 for load conditions.
FIGURE 15-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
77
BIT6 - - - -1
LSb IN
74
Note:
Refer to Figure 15-4 for load conditions.
2001-2013 Microchip Technology Inc.
Preliminary
DS39544B-page 153
PIC16C925/926
TABLE 15-8:
Param
No.
SPI MODE REQUIREMENTS
Symbol
Characteristic
70
TssL2scH,
TssL2scL
SS to SCK or SCK input
71
TscH
SCK input high time (Slave
mode)
Min
Typ†
Max
Units
TCY
—
—
ns
Continuous
1.25TCY + 30
—
—
ns
Single Byte
40
—
—
ns
—
—
ns
Conditions
71A
72
TscL
SCK input low time (Slave
mode)
Continuous
1.25TCY + 30
Single Byte
40
72A
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
50
—
—
ns
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
50
—
—
ns
75
TdoR
SDO data output rise time
—
10
25
ns
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ
SS to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time (Master mode)
—
10
25
ns
79
TscF
SCK output fall time (Master mode)
—
10
25
ns
80
TscH2doV,
TscL2doV
SDO data output valid after SCK edge
—
—
50
ns
81
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
TCY
—
—
ns
82
TssL2doV
SDO data output valid after SS edge
—
—
50
ns
83
TscH2ssH,
TscL2ssH
SS after SCK edge
1.5TCY + 40
—
—
ns
Tb2b
Delay between consecutive bytes
1.5TCY + 40
—
—
ns
84
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS39544B-page 154
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
I2C BUS START/STOP BITS TIMING
FIGURE 15-14:
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note:
Refer to Figure 15-4 for load conditions.
TABLE 15-9:
Parameter
No.
I2C BUS START/STOP BITS REQUIREMENTS
Symbol
90
TSU:STA
91
THD:STA
92
TSU:STO
93
THD:STO
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
2001-2013 Microchip Technology Inc.
Min Typ Max Units
100 kHz mode
4700 —
—
ns
100 kHz mode
4000 —
—
ns
100 kHz mode
4700 —
—
ns
100 kHz mode
4000 —
—
ns
Preliminary
Conditions
Only relevant for Repeated
START condition
After this period the first clock
pulse is generated
DS39544B-page 155
PIC16C925/926
I2C BUS DATA TIMING
FIGURE 15-15:
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note:
Refer to Figure 15-4 for load conditions.
TABLE 15-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
101
TLOW
Clock low time
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
s
Device must operate at a
minimum of 1.5 MHz
SSP Module
SDA and SCL rise 100 kHz mode
time
SDA and SCL fall 100 kHz mode
time
START condition 100 kHz mode
setup time
START condition 100 kHz mode
hold time
Data input hold
100 kHz mode
time
Data input setup
100 kHz mode
time
STOP condition
100 kHz mode
setup time
Output valid from 100 kHz mode
clock
Bus free time
100 kHz mode
1.5TCY
—
—
1000
ns
—
300
ns
4.7
—
s
4.0
—
s
0
—
ns
250
—
ns
4.7
—
s
—
3500
ns
(Note 1)
4.7
—
s
Time the bus must be free
before a new transmission
can start
102
TR
103
TF
90
TSU:STA
91
THD:STA
106
THD:DAT
107
TSU:DAT
92
TSU:STO
109
TAA
110
TBUF
Only relevant for Repeated
START condition
After this period the first
clock pulse is generated
D102
CB
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
DS39544B-page 156
Preliminary
2001-2013 Microchip Technology Inc.
PIC16C925/926
TABLE 15-11: A/D CONVERTER CHARACTERISTICS:
PIC16C925/926 (COMMERCIAL, INDUSTRIAL)
PIC16LC925/926 (COMMERCIAL, INDUSTRIAL)
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
—
—
10-bits
bit
VREF = VDD = 5.12V,
VSS VAIN VREF
A01
NR
A02
EABS Total Absolute error
—
—
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