PIC16F15276-I/PT

PIC16F15256/74/75/76 PIC16F15256/74/75/76 28/40-Pin Microcontrollers Introduction The PIC16F152 microcontroller family is available in 8/14/16/20/28/40/44-pin packages for cost-sensitive sensor and real-time control applications. The PIC16F152 family’s simplified feature set includes a 10-bit Analog-to-Digital Converter (ADC), Peripheral Pin Select (PPS), digital communication peripherals, timers and waveform generators. This microcontroller family also provides memory features, such as the Memory Access Partition (MAP) to support users in data protection and bootloader applications, and a Device Information Area (DIA) that stores Fixed Voltage Reference (FVR) offset values to help improve ADC accuracy. PIC16F152 Family Types SMBus Compatible I/O Pads External Interrupt Pins 2/2 17/2 1 1 Y 1 25 Y PIC16F15274 7k 512 Y/Y 36/Y 1/2 2/2 28/2 1 1 Y 1 25 Y PIC16F15275 14k 1024 Y/Y 36/Y 1/2 2/2 28/2 1 1 Y 1 25 Y PIC16F15276 28k 2048 Y/Y 36/Y 1/2 2/2 28/2 1 1 Y 1 25 Y Device © 2021 Microchip Technology Inc. Preliminary Datasheet Watchdog Timer EUSART 1/2 Interrupt-on-Change Pins MSSP 25/Y 10-Bit ADC Channels (External/Internal) 10-Bit PWM/ CCP Y/Y I/O Pins(1)/ Peripheral Pin Select 2048 Memory Access Partition/ Device Information Area 28k Data SRAM (bytes) PIC16F15256 Program Flash Memory (bytes) 8-Bit Timers with HLT/ 16-Bit Timers(2) Table 1.  Devices Included in This Data Sheet DS40002305B-page 1 PIC16F15256/74/75/76 Notes:  1. Total I/O count includes one pin (MCLR) that is input-only. 2. Timer0 can be configured as either an 8 or 16-bit timer. Core Features • • • • • • • C Compiler Optimized RISC Architecture Operating Speed: – DC – 32 MHz clock input – 125 ns minimum instruction time 16-Level Deep Hardware Stack Low-Current Power-on Reset (POR) Configurable Power-up Timer (PWRT) Brown-out Reset (BOR) Watchdog Timer (WDT) Memory • • • • • • • Up to 28 KB of Program Flash Memory Up to 2 KB of Data SRAM Memory Memory Access Partition (MAP): The Program Flash Memory Can Be Partitioned into: – Application Block – Boot Block – Storage Area Flash (SAF) Block Programmable Code Protection and Write Protection Device Information Area (DIA) Stores: – Fixed Voltage Reference (FVR) measurement data – Microchip unique identifier Device Characteristics Area (DCI) Stores: – Program/erase row sizes – Pin count details Direct, Indirect and Relative Addressing Modes Operating Characteristics • • Operating Voltage Range: – 1.8V to 5.5V Temperature Range: – Industrial: -40°C to 85°C – Extended: -40°C to 125°C Power-Saving Functionality • • Sleep: – Reduce device power consumption – Reduce system electrical noise while performing ADC conversions Low-Power Mode Features: – Sleep: • < 900 nA typical @ 3V/25°C (WDT enabled) © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 2 PIC16F15256/74/75/76 • < 600 nA typical @ 3V/25°C (WDT disabled) – Operating Current: • 48 µA typical @ 32 kHz, 3V/25°C • < 1 mA typical @ 4 MHz, 5V/25°C Digital Peripherals • • • • • • • • • Two Capture/Compare/PWM (CCP) Modules: – 16-bit resolution for Capture/Compare modes – 10-bit resolution for PWM mode Two Pulse-Width Modulators (PWM): – 10-bit resolution – Independent pulse outputs One Configurable 8/16-Bit Timer (TMR0) One 16-Bit Timer (TMR1) with Gate Control One 8-Bit Timer (TMR2) with Hardware Limit Timer (HLT) One Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART): – RS-232, RS-485, LIN compatible – Auto-wake-up on Start One Host Synchronous Serial Port (MSSP): – Serial Peripheral Interface (SPI) mode • Client Select Synchronization – Inter-Integrated Circuit (I2C) mode • 7/10-bit Addressing modes Peripheral Pin Select (PPS): – Enables pin mapping of digital I/O Device I/O Port Features: – Up to 35 I/O pins – 1 input-only pin – Individual I/O direction, open-drain, input threshold, slew rate and weak pull-up control – Interrupt-on-change (IOC) on all pins – One external interrupt pin Analog Peripherals • • Analog-to-Digital Converter (ADC): – 10-bit resolution – Up to 28 external input channels – Two internal input channels – Internal ADC oscillator (ADCRC) – Operates in Sleep – Selectable auto-conversion trigger sources Fixed Voltage Reference (FVR): – Selectable 1.024V, 2.048V and 4.096V output levels – Internally connected to ADC Clocking Structure • High-Precision Internal Oscillator Block (HFINTOSC): © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 3 PIC16F15256/74/75/76 • • – Selectable frequencies up to 32 MHz – ±2% at calibration Internal 31 kHz Oscillator (LFINTOSC) External High-Frequency Clock Input: – Two External Clock (EC) power modes Programming/Debug Features • In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) with One Breakpoint via Two Pins •Filename: Debug Integrated On-Chip 59B0S BLOCK DIAGRAM.vsdx Title: Last Edit: First Used: Notes: 12/1/2020 Block Diagram Figure 1. PIC16F15256/74/75/76 Block Diagram Ports PORTA PORTB PORTC PORTD(1) PORTE PPS Module Peripherals Memory Data Bus MSSP1 Timers Program Flash Memory CCP Instruction Bus EUSART Interconnect Bus Data Memory (RAM) ADC PWM FVR MCLR Single-Supply Programming In-Circuit Debugger Power-up Timer Brown-out Reset Power-on Reset WDT CPU Interrupt Controller Program, Debug and Supervisory Modules Oscillator and Clock Precision Band Gap Reference OSC1 ECIN EXTOSC HFINTOSC with Active Clock Tuning LFINTOSC Note:  40-pin devices only. © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 4 PIC16F15256/74/75/76 Table of Contents Introduction.....................................................................................................................................................1 PIC16F152 Family Types............................................................................................................................... 1 Core Features................................................................................................................................................ 2 1. Packages................................................................................................................................................ 7 2. Pin Diagrams...........................................................................................................................................8 3. Pin Allocation Tables............................................................................................................................. 11 4. Guidelines for Getting Started with PIC16F152 Microcontrollers..........................................................14 5. Register and Bit Naming Conventions.................................................................................................. 17 6. Register Legend....................................................................................................................................19 7. Enhanced Mid-Range CPU...................................................................................................................20 8. Device Configuration.............................................................................................................................22 9. Memory Organization............................................................................................................................32 10. Resets................................................................................................................................................... 65 11. OSC - Oscillator Module....................................................................................................................... 77 12. Interrupts............................................................................................................................................... 87 13. Sleep Mode......................................................................................................................................... 100 14. WDT - Watchdog Timer.......................................................................................................................102 15. NVM - Nonvolatile Memory Control ....................................................................................................106 16. I/O Ports.............................................................................................................................................. 127 17. IOC - Interrupt-on-Change.................................................................................................................. 143 18. PPS - Peripheral Pin Select Module................................................................................................... 149 19. TMR0 - Timer0 Module....................................................................................................................... 158 20. TMR1 - Timer1 Module with Gate Control...........................................................................................166 21. TMR2 - Timer2 Module....................................................................................................................... 181 22. CCP - Capture/Compare/PWM Module.............................................................................................. 204 23. PWM - Pulse-Width Modulation.......................................................................................................... 217 24. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter.......................... 225 25. MSSP - Host Synchronous Serial Port Module...................................................................................255 26. FVR - Fixed Voltage Reference.......................................................................................................... 315 © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 5 PIC16F15256/74/75/76 27. ADC - Analog-to-Digital Converter...................................................................................................... 318 28. Charge Pump...................................................................................................................................... 334 29. Instruction Set Summary.....................................................................................................................337 30. ICSP™ - In-Circuit Serial Programming™........................................................................................... 357 31. Register Summary.............................................................................................................................. 360 32. Electrical Specifications...................................................................................................................... 365 33. DC and AC Characteristics Graphs and Tables.................................................................................. 388 34. Packaging Information........................................................................................................................ 389 35. Appendix A: Revision History..............................................................................................................409 The Microchip Website...............................................................................................................................410 Product Change Notification Service..........................................................................................................410 Customer Support...................................................................................................................................... 410 Product Identification System..................................................................................................................... 411 Microchip Devices Code Protection Feature.............................................................................................. 411 Legal Notice............................................................................................................................................... 412 Trademarks................................................................................................................................................ 412 Quality Management System..................................................................................................................... 413 Worldwide Sales and Service.....................................................................................................................414 © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 6 1. Device 14-Pin TSSOP 14Pin SOIC 16-Pin VQFN 3x3x0.9 20Pin PDIP 20-Pin SSOP 20Pin SOIC 20-Pin VQFN 3x3x0.9 Preliminary Datasheet 28Pin SOIC 28-Pin SSOP 28-Pin VQFN 4x4x1 40Pin PDIP 40-Pin VQFN 5x5x0.9 44-Pin TQFP 10x10x1 PIC16F15223 • • • PIC16F15224 • • • PIC16F15225 • • • PIC16F15243 • • • • PIC16F15244 • • • • PIC16F15245 • • • • PIC16F15254 • • • PIC16F15255 • • • PIC16F15256 • • • PIC16F15274 • • • PIC16F15275 • • • PIC16F15276 • • • rotatethispage90 8-Pin 8-Pin SOIC DFN PIC16F15213 • • PIC16F15214 • • Packages © 2021 Microchip Technology Inc. Table 1-1. Packages PIC16F15256/74/75/76 Packages DS40002305B-page 7 PIC16F15256/74/75/76 Pin Diagrams Pin Diagrams Figure 2-1.  28-Pin SPDIP 28-Pin SSOP 28-Pin SOIC MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 Figure 2-2.  28-Pin VQFN 28 27 26 25 24 23 22 RA2 RA3 RA4 RA5 VSS RA7 RA6 1 21 RB3 2 20 RB2 3 19 RB1 4 18 RB0 5 17 VDD 6 16 VSS 7 15 RC7 8 9 10 11 12 13 14 RC0 RC1 RC2 RC3 RC4 RC5 RC6 2. Note:  It is recommended that the exposed bottom pad be connected to VSS; however, it must not be the only VSS connection to the device. Figure 2-3.  40-Pin PDIP © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 8 PIC16F15256/74/75/76 Pin Diagrams MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS RA7 RA6 RC0 RC1 RC2 RC3 RD0 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 Figure 2-4.  40-Pin VQFN 40 39 38 37 36 35 34 33 32 31 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 1 30 RC0 2 29 RA6 3 28 4 27 5 26 6 25 7 24 8 23 9 22 10 21 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 11 12 13 14 15 16 17 18 19 20 Note:  It is recommended that the exposed bottom pad be connected to VSS; however, it must not be the only VSS connection to the device. Figure 2-5.  44-Pin TQFP © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 9 PIC16F15256/74/75/76 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC Pin Diagrams 44 43 42 41 40 39 38 37 36 35 34 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 NC NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 12 13 14 15 16 17 18 19 20 21 22 © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 10 PIC16F15256/74/75/76 Pin Allocation Tables 3. Pin Allocation Tables Table 3-1. 28-Pin Allocation Table I/O 28-PinSPDIP SSOP SOIC 28-Pin VQFN ADC Reference Timers CCP 10-Bit PWM MSSP EUSART IOC Interrupt Basic RA0 2 27 ANA0 — — — — — — IOCA0 — — RA1 3 28 ANA1 — — — — — — IOCA1 — — RA2 4 1 ANA2 — — — — — — IOCA2 — — RA3 5 2 ANA3 VREF+ (ADC) — — — — — IOCA3 — — — T0CKI(1) — — — — IOCA4 — — — — SS1(1) — IOCA5 — — RA4 6 RA5 7 3 4 — ANA5 — — RA6 10 7 — — — — — — — IOCA6 — CLKOUT RA7 9 6 — — — — — — — IOCA7 — CLKIN RB0 21 18 ANB0 — — — — — — IOCB0 INT(1) — RB1 22 19 ANB1 — — — — — — IOCB1 — — RB2 23 20 ANB2 — — — — — — IOCB2 — — RB3 24 21 ANB3 — — — — — — IOCB3 — — RB4 25 22 ANB4 ADACT(1) — — — — — — IOCB4 — — RB5 26 23 ANB5 — T1G(1) — — — — IOCB5 — — RB6 27 24 — — — — — — — IOCB6 — ICSPCLK ICDCLK RB7 28 25 — — — — — — — IOCB7 — ICSPDAT ICDDAT RC0 11 8 — — T1CKI(1) — — — — IOCC0 — — RC1 12 9 — — — CCP2(1) — — — IOCC1 — — RC2 13 10 ANC2 — — CCP1(1) — — — IOCC2 — — RC3 14 11 ANC3 — T2IN(1) — — SCL1(1,3,4) SCK1(1,3,4) — IOCC3 — — RC4 15 12 ANC4 — — — — SDA1(1,3,4) SDI1(1,3,4) — IOCC4 — — RC5 16 13 ANC5 — — — — — — IOCC5 — — RC6 17 14 ANC6 — — — — — CK1(1,3) IOCC6 — — RC7 18 15 ANC7 — — — — — RX1(1) DT1(1,3) IOCC7 — — RE3 1 26 — — — — — — — IOCE3 — MCLR VPP VDD 20 17 — — — — — — — — — VDD VSS 8 19 5 16 — — — — — — — — — VSS OUT(2) — — — — TMR0 CCP1 CCP2 PWM3 PWM4 SCL1 SCK1 SDA1 SDO1 TX1 DT1 CK1 — — — © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 11 PIC16F15256/74/75/76 Pin Allocation Tables Notes:  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal. 2. All output signals shown in this row are PPS remappable. 3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. 4. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register. Table 3-2. 40/44-Pin Allocation Table I/O 40-Pin PDIP 40-Pin VQFN 44-Pin TQFP ADC Reference Timers CCP 10-Bit PWM MSSP EUSART IOC Interrupt Basic RA0 2 17 19 ANA0 — — — — — — IOCA0 — — RA1 3 18 20 ANA1 — — — — — — IOCA1 — — RA2 4 19 21 ANA2 — — — — — — IOCA2 — — RA3 5 20 22 ANA3 VREF+ (ADC) — — — — — IOCA3 — — RA4 6 21 23 — — T0CKI(1) — — — — IOCA4 — — RA5 7 22 24 ANA5 — — — — SS1(1) — IOCA5 — — RA6 14 29 31 — — — — — — — IOCA6 — CLKOUT RA7 13 28 30 — — — — — — — IOCA7 — CLKIN — RB0 33 8 8 ANB0 — — — — — — IOCB0 INT(1) RB1 34 9 9 ANB1 — — — — — — IOCB1 — — RB2 35 10 10 ANB2 — — — — — — IOCB2 — — RB3 36 11 11 ANB3 — — — — — — IOCB3 — — RB4 37 12 14 ANB4 ADACT(1) — — — — — — IOCB4 — — RB5 38 13 15 ANB5 — T1G(1) — — — — IOCB5 — — RB6 39 14 16 — — — — — — — IOCB6 — ICSPCLK ICDCLK RB7 40 15 17 — — — — — — — IOCB7 — ICSPDAT ICDDAT RC0 15 30 32 — — T1CKI(1) — — — — IOCC0 — — — CCP2(1) — — — IOCC1 — — — — CCP1(1) — — — IOCC2 — — — — SCL1(1,3,4) SCK1(1,3,4) — IOCC3 — — RC1 RC2 16 17 31 32 35 36 — ANC2 — RC3 18 33 37 ANC3 — T2IN(1) RC4 23 38 42 ANC4 — — — — SDA1(1,3,4) SDI1(1,3,4) — IOCC4 — — RC5 24 39 43 ANC5 — — — — — — IOCC5 — — — CK1(1,3) IOCC6 — — IOCC7 — — RC6 25 40 44 ANC6 — — — — RC7 26 1 1 ANC7 — — — — — RX1(1) DT1(1,3) RD0 19 34 38 AND0 — — — — — — — — — RD1 20 35 39 AND1 — — — — — — — — — RD2 21 36 40 AND2 — — — — — — — — — RD3 22 37 41 AND3 — — — — — — — — — RD4 27 2 2 AND4 — — — — — — — — — © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 12 PIC16F15256/74/75/76 Pin Allocation Tables ...........continued I/O 40-Pin PDIP 40-Pin VQFN 44-Pin TQFP ADC Reference Timers CCP 10-Bit PWM MSSP EUSART IOC Interrupt Basic RD5 28 3 3 AND5 — — — — — — — — — RD6 29 4 4 AND6 — — — — — — — — — RD7 30 5 5 AND7 — — — — — — — — — RE0 8 23 25 ANE0 — — — — — — — — — RE1 9 24 26 ANE1 — — — — — — — — — RE2 10 25 27 ANE2 — — — — — — — — — RE3 1 16 18 — — — — — — — IOCE3 — MCLR VPP VDD 11 32 7 26 7 28 — — — — — — — — — VDD VSS 12 31 6 27 6 29 — — — — — — — — — VSS OUT(2) — — — — TMR0 CCP1 CCP2 PWM3 PWM4 SCL1 SCK1 SDA1 SDO1 TX1 DT1 CK1 — — — Notes:  1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal. 2. All output signals shown in this row are PPS remappable. 3. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I2C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register. 4. © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 13 PIC16F15256/74/75/76 Guidelines for Getting Started with PIC16F152 Micr... 4. Guidelines for Getting Started with PIC16F152 Microcontrollers 4.1 Basic Connection Requirements Getting started with the PIC16F152 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. Filename: Recommended Minimum Connections.vsdx Last Edit: 1/2/2020 The following pins must Title: always be connected: • • All VDD and VSS pins (see 4.2 Power Supply Pins) First Used: MCLR pin (seeNotes: 4.3 Master Clear (MCLR) Pin) These pins must also be connected if they are being used in the end application: • • PGC/PGD pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see 4.4 In-Circuit Serial Programming (ICSP) Pins) CLKIN pin when an external clock source is used. Additionally, the following may be required: • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented The minimum recommended connections are shown in the figure below. Figure 4-1. Minimum Recommended Connections VDD V DD R1 R2 Vss C2 MCLR C1 PIC MCU Vss Key (all values are recommendations): C1: 10 nF, 16V ceramic C2: 0.1 F, 16V ceramic R1: 10 kΩ R2: 100Ω to 470Ω 4.2 Power Supply Pins 4.2.1 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required. Consider the following criteria when using decoupling capacitors: • • Value and type of capacitor: A 0.1 μF (100 nF), 10-25V capacitor is recommended. The capacitor may be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. Placement on the printed circuit board: The decoupling capacitors may be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 14 PIC16F15256/74/75/76 Guidelines for Getting Started with PIC16F152 Micr... • • 4.2.2 Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 μF in parallel with 0.001 μF). Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. Tank Capacitors With on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor may be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor that meets the acceptable voltage sag at the device. Typical values range from 4.7 μF to 47 μF. 4.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 4-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 4-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin may be placed within 0.25 inch (6 mm) of the pin. Figure 4-2. Example of MCLR Pin Connections VDD Rev. 30-000058A 4/5/2017 R1 R2 JP MCLR PIC MCU C1 Notes:  1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL   specifications are met.  2. R2 ≤ 470Ω will limit any current flowing into MCLR from the extended capacitor, C1, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin   VIH and VIL specifications are met. 4.4 In-Circuit Serial Programming™ (ICSP™) Pins The ICSPCLK and ICSPDAT pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω. © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 15 PIC16F15256/74/75/76 Guidelines for Getting Started with PIC16F152 Micr... Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they can interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they may be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the Communication Channel Select (i.e., ICSPCLK/ICSPDAT pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. 4.5 Unused I/Os Unused I/O pins may be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins to drive the output to logic low. © 2021 Microchip Technology Inc. Preliminary Datasheet DS40002305B-page 16 PIC16F15256/74/75/76 Register and Bit Naming Conventions 5. 5.1 Register and Bit Naming Conventions Register Names When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The Control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 5.2 Bit Names There are two variants for bit names: • • 5.2.1 Short name: Bit function abbreviation Long name: Peripheral abbreviation + short name Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, ON, in the ADCON0 register can be set in C programs with the instruction ADCON0bits.ON = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 5.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the ADC enable bit is the ADC prefix, AD, appended with the enable bit short name, ON, resulting in the unique bit name ADON. Long bit names are useful in both C and assembly programs. For example, in C the ADCON0 enable bit can be set with the ADON = 1 instruction. In assembly, this bit can be set with the BSF ADCON0,ADON instruction. 5.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the ADCON2 register contain the ADC Operating Mode Selection bit. The short name for this field is MD and the long name is ADMD. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the ADC to operate in Accumulate mode: ADCON2bits.MD = 0b001; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant MODE bit has the short bit name MD2 and the long bit name is ADMD2. The following two examples demonstrate assembly program sequences for setting the ADC to operate in Accumulate mode: MOVLW ANDWF ~(1