PIC16F15325T-I/SL

PIC16(L)F15325/45 Full-Featured 14/16/20-Pin Microcontrollers Description PIC16(L)F15325/45 microcontrollers feature analog, Core Independent Peripherals and communication peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications. The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture • Operating Speed: - DC – 32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Timers: - 8-bit Timer2 with Hardware Limit Timer (HLT) - 16-bit Timer0/1 • Low-Current Power-on Reset (POR) • Configurable Power-up Timer (PWRTE) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software • Programmable Code Protection • Doze Mode: Ability to Run the CPU Core Slower Than the System Clock • Idle Mode: Ability to Halt CPU Core while Internal Peripherals Continue Operating • Sleep Mode: Lowest Power Consumption • Peripheral Module Disable (PMD): - Ability to disable hardware module to minimize active power consumption of unused peripherals Memory • • • • Up to 14 KB Flash Program Memory Up to 1024 Bytes Data SRAM Direct, Indirect and Relative Addressing Modes Memory Access Partition (MAP): - Write-protect - Customizable Partition • Device Information Area (DIA) • Device Configuration Information (DCI) • High-Endurance Flash (HEF) - Last 128 words of Program Flash Memory Operating Characteristics • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF15325/45) - 2.3V to 5.5V (PIC16F15325/45) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C  2016-2022 Microchip Technology Inc. and its subsidiaries eXtreme Low-Power (XLP) Features • • • • Sleep Mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 A @ 32 kHz, 1.8V, typical - 32 A/MHz @ 1.8V, typical Digital Peripherals • Four Configurable Logic Cells (CLC): - Integrated combinational and sequential logic • Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources • Two Capture/Compare/PWM (CCP) Module: - 16-bit resolution for Capture/Compare modes - 10-bit resolution for PWM mode • Four 10-Bit PWMs • Numerically Controlled Oscillator (NCO): - Generates true linear frequency control and increased frequency resolution - Input Clock: 0 Hz < FNCO < 32 MHz - Resolution: FNCO/220 • Two EUSART, RS-232, RS-485, LIN Compatible • One SPI • One I2C, SMBus, PMBus™ Compatible DS40001865E-page 1 PIC16(L)F15325/45 Digital Peripherals (Cont.) Flexible Oscillator Structure • I/O Pins: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select - Input level selection control (ST or TTL) - Digital open-drain enable • Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O • High-Precision Internal Oscillator: - Software selectable frequency range up to 32 MHz, ±1% typical • x2/x4 PLL with Internal and External Sources • Low-Power Internal 31 kHz Oscillator (LFINTOSC) • External 32 kHz Crystal Oscillator (SOSC) • External Oscillator Block with: - Three crystal/resonator modes up to 20 MHz - Three external clock modes up to 32 MHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if primary clock stops • Oscillator Start-up Timer (OST): - Ensures stability of crystal oscillator resources Analog Peripherals • Analog-to-Digital Converter (ADC): - 10-bit with up to 43 external channels - Operates in Sleep • Two Comparators: - FVR, DAC and external input pin available on inverting and noninverting input - Software selectable hysteresis - Outputs available internally to other modules, or externally through PPS • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive Reference Selection - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels • Zero-Cross Detect Module: - AC high voltage zero-crossing detection for simplifying TRIAC control - Synchronized switching control and timing  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001865E-page 2 PIC16(L)F15325/45 5-bit DAC Comparator 8-bit/ (with HLT) Timer 16-bit Timer Window Watchdog Timer CCP/10-bit PWM CWG NCO CLC Memory Access Partition Device Information Area Peripheral Pin Select Peripheral Module Disable Debug (1) 5 1 1 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I PIC16(L)F15323 (C) 2 3.5 224 256 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I 224 512 EUSART/ I2C-SPI 10-bit ADC 6 Zero-Cross Detect Temperature Indicator I/OPins 3.5 224 256 Data SRAM (bytes) 2 Storage Area Flash (B) PIC16(L)F15313 (C) Device Program Flash Memory (KB) Program Flash Memory (KW) PIC16(L)F153XX FAMILY TYPES Data Sheet Index TABLE 1: PIC16(L)F15324 (D) 4 7 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15325 (B) 8 14 224 1024 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15344 (D) 4 7 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15345 (B) 8 14 224 1024 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15354 (A) 4 7 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15355 (A) 8 14 224 1024 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15356 (E) 16 28 224 2048 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15375 (E) 8 14 224 1024 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15376 (E) 16 28 224 2048 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15385 (E) 8 14 224 1024 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15386 (E) 16 28 224 2048 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I Note 1: 224 512 224 512 I - Debugging integrated on chip. Data Sheet Index: A: DS40001853 PIC16(L)F15354/5 Data Sheet, 28-Pin B: DS40001865 PIC16(L)F15325/45 Data Sheet, 14/20-Pin C: DS40001897 PIC16(L)F15313/23 Data Sheet, 8/14-Pin D: DS40001889 PIC16(L)F15324/44 Data Sheet, 14/20-Pin E: DS40001866 PIC16(L)F15356/75/76/85/86 Data Sheet, 28/40/48-Pin Note: For other small form-factor package availability and marking information, visit www.microchip.com/ packaging or contact your local sales office.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001865E-page 3 PIC16(L)F15325/45 TABLE 2: PACKAGES Device PIC16(L)F15325 PIC16(L)F15345 PDIP SOIC      2016-2022 Microchip Technology Inc. and its subsidiaries SSOP  TSSOP UQFN (4x4) QFN/VQFN (4x4)      DS40001865E-page 4 PIC16(L)F15325/45 PIN DIAGRAMS 1 2 3 4 5 6 7 20-PIN PDIP, SOIC, SSOP VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 VDD 1 20 VSS RA5 2 RA4 3 19 RA0/ICSPDAT 18 RA1/ICSPCLK 17 RA2 16 RC0 15 RC1 MCLR/VPP/RA3 4 RC5 5 RC4 6 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 RC3 7 Note: 14 13 12 11 10 9 8 See Table 3 for location of all peripheral functions. PIC16(L)F15345 Note: VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 PIC16(L)F15325 14-PIN PDIP, SOIC, TSSOP See Table 4 for location of all peripheral functions. VDD NC NC Vss 16-PIN UQFN/VQFN (4X4) 16 15 14 13 RA5 RA4 MCLR/VPP/RA3 RC5 1 2 3 4 PIC16(L)F15325 12 11 10 9 RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC4 RC3 RC2 RC1 5 6 7 8 Note 1: 2: See Table 3 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001865E-page 5 RA4 RA5 VDD Vss RA0/ICSPDAT PIC16(L)F15325/45 20-PIN UQFN/VQFN/QFN (4x4) 1 2 3 4 5 PI C RA3/MCLR/VPP RC5 RC4 RC3 RC6 16 (L )F 15 34 5 20 19 18 17 16 15 14 13 12 11 RA1/ICSPCLK RA2 RC0 RC1 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 Note 1: 2: See Table 4 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001865E-page 6 CCP PWM CWG MSSP ZCD EUSART CLC CLKR Interrupt Pull-up ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― ― ― ― IOCA0 Y ICSPDAT ANA1 VREF+ C1IN0C2IN0- ― DAC1REF+ T0CKI(1) ― ― ― ― ― ― ― ― IOCA1 Y ICSPCLK RA2 11 10 ANA2 ― ― ― ― ― ― ― CWG1IN(1) ― ZCD1 ― ― ― INT(1) IOCA2 Y ― RA3 4 3 ― ― ― ― ― ― ― ― ― ― ― ― ― ― IOCA3 Y MCLR VPP RA4 3 2 ANA4 ― ― ― ― T1G(1) ― ― ― ― ― ― ― ― IOCA4 Y CLKOUT OSC2 RA5 2 1 ANA5 ― ― ― ― T1CKI(1) T2IN ― ― ― ― ― CLCIN3(1) ― IOCA5 Y CLKIN OSC1 EIN RC0 10 9 ANC0 ― C2IN0+ ― ― ― ― ― ― SCK1(1) SCL1(1,4) ― TX2(1) CK2(1) ― ― IOCC0 Y ― RC1 9 8 ANC1 ― C1IN1C2IN1- ― ― ― ― ― ― SDA1(1,4) SDI1(1) ― RX2(1) DT2(1) CLCIN2(1) ― IOCC1 Y ― RC2 8 7 ANC2 ― C1IN2C2IN2- ― ― ― ― ― ― ― ― ― ― ― IOCC2 Y ― RC3 7 6 ANC3 ― C1IN3C2IN3- ― ― ― CCP2(1) ― ― SS1(1) ― ― CLCIN0(1) ― IOCC3 Y ― RC4 6 5 ANC4 ― ― ― ― ― ― ― ― ― ― TX1(1) CK1(1) CLCIN1(1) ― IOCC4 Y ― RC5 5 4 ANC5 ― ― ― ― ― CCP1(1) ― ― ― ― RX1(1) DT1(1) ― ― IOCC5 Y ― VDD 1 16 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD VSS 14 13 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS Note 1: 2: 3: 4: Basic Timers ANA0 11 DAC Comparator 12 12 NCO Reference 13 RA1 ADC RA0 This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865E-page 7 16-Pin QFN/UQFN/VQFN 14/16-PIN ALLOCATION TABLE (PIC16(L)F15325) 14-Pin PDIP/SOIC/TSSOP TABLE 3: I/O(2)  2016-2022 Microchip Technology Inc. and its subsidiaries PIN ALLOCATION TABLES Reference Comparator NCO DAC Timers CCP PWM CWG MSSP ZCD EUSART CLC CLKR ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3OUT CWG1A SDO1 ― DT1(3) CLC1OUT CLKR ― ― ― ― ― ― ― C2OUT ― ― ― CCP2 PWM4OUT CWG1B SCK1 ― CK1 CLC2OUT ― ― ― ― ― ― ― ― ― ― ― ― ― PWM5OUT CWG1C SCL1(3,4) ― TX1 CLC3OUT ― ― ― ― ― ― ― ― ― ― ― ― ― PWM6OUT CWG1D SDA1(3,4) ― DT2(3) CLC4OUT ― ― ― ― Basic ADC ― Pull-up 16-Pin QFN/UQFN/VQFN OUT(2) Interrupt 14-Pin PDIP/SOIC/TSSOP 14/16-PIN ALLOCATION TABLE (PIC16(L)F15325) (CONTINUED) I/O(2)  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 3: CK2 TX2 Note 1: 2: 3: 4: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865E-page 8 Reference Comparator NCO Timers CCP PWM CWG MSSP ZCD EUSART CLC CLKR Interrupt Pull-up 16 ANA0 ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― ― ― ― IOCA0 Y ICSPDAT 18 15 ANA1 VREF+ C1IN0C2IN0- ― DAC1REF+ T0CKI(1) ― ― ― ― ― ― ― ― IOCA1 Y ICSPCLK RA2 17 14 ANA2 ― ― ― ― ― ― ― CWG1IN(1) ― ZCD1 ― CLCIN0(1) ― INT(1) IOCA2 Y ― RA3 4 1 ― ― ― ― ― ― ― ― ― ― ― ― ― ― IOCA3 Y MCLR VPP RA4 3 20 ANA4 ― ― ― ― T1G(1) ― ― ― ― ― ― ― ― IOCA4 Y CLKOUT OSC2 RA5 2 19 ANA5 ― ― ― ― T1CKI(1) T2IN ― ― ― ― ― ― ― IOCA5 Y CLKIN OSC1 EIN RB4 13 10 ANB4 ADACT(1) ― ― ― ― ― ― ― ― SCK1(1) SCL1(1,4) ― ― CLCIN2(1) ― IOCB4 ― ― RB5 12 9 ANB5 ― ― ― ― ― ― ― ― ― ― RX1(1) DT1(1) CLCIN3(1) ― IOCB5 ― ― RB6 11 8 ANB6 ― ― ― ― ― ― ― ― SDA1(1,4) SDI1(1) ― ― ― ― IOCB6 Y ― RB7 10 7 ANB7 ― ― ― ― ― ― ― ― ― ― TX1(1) CK1(1) ― ― IOCB7 Y ― RC0 16 13 ANC0 ― C2IN0+ ― ― ― ― ― ― SCK1(1) SCL1(1,4) ― TX2(1) CK2(1) ― ― IOCC0 Y ― RC1 15 12 ANC1 ― C1IN1C2IN1- ― ― ― ― ― ― SDA1(1,4) SDI1(1) ― RX2(1) DT2(1) ― ― IOCC1 Y ― RC2 14 11 ANC2 ― C1IN2C2IN2- ― ― ― ― ― ― ― ― ― ― ― IOCC2 Y ― RC3 7 4 ANC3 ― C1IN3C2IN3- ― ― ― CCP2(1) ― ― ― ― ― CLCIN1(1) ― IOCC3 Y ― RC4 6 3 ANC4 ― ― ― ― ― ― ― ― ― ― ― ― ― IOCC4 Y ― RC5 5 2 ANC5 ― ― ― ― ― CCP1(1) ― ― ― ― ― ― ― IOCC5 Y ― RC6 8 5 ANC6 ― ― ― ― ― ― ― ― SS1(1) ― ― ― ― IOCC6 Y ― Note 1: 2: 3: 4: Basic ADC 19 RA1 DAC 20-Pin QFN/UQFN/VQFN RA0 This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865E-page 9 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F15345) I/O(2)  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4: ― ― ― ― IOCC7 Y ― ― ― ― ― ― ― ― VDD VSS 20 17 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS OUT(2) ― ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3OUT CWG1A SDO1 ― DT1(3) DT2(3) CLC1OUT CLKR ― ― ― ― ― ― ― C2OUT ― ― ― CCP2 PWM4OUT CWG1B SCK1 ― CK1 CK2 CLC2OUT ― ― ― ― ― ― ― ― ― ― ― ― ― PWM5OUT CWG1C SCL1(3,4) ― TX1 TX2 CLC3OUT ― ― ― ― ― ― ― ― ― ― ― ― ― PWM6OUT CWG1D SDA1(3,4) ― ― CLC4OUT ― ― ― ― Note 1: 2: 3: 4: Basic Interrupt ― ― Pull-up CLKR ― ― CLC ― ― EUSART ― ― ZCD ― ― MSSP ― ― CWG ― ― PWM ― ― CCP ― ― Timers ANC7 18 DAC 6 1 NCO ADC 9 VDD Comparator 20-Pin QFN/UQFN/VQFN RC7 Reference 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F15345) (CONTINUED) I/O(2)  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware may map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865E-page 10 PIC16(L)F15325/45 Table of Contents Pin Diagrams ......................................................................................................................................................................................... 5 Pin Allocation Tables ............................................................................................................................................................................. 7 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with PIC16(L)F15325/45 Microcontrollers.................................................................................. 26 3.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 29 4.0 Memory Organization ................................................................................................................................................................. 31 5.0 Device Configuration .................................................................................................................................................................. 79 6.0 Device Information Area............................................................................................................................................................. 90 7.0 Device Configuration Information ............................................................................................................................................... 92 8.0 Resets ........................................................................................................................................................................................ 93 9.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 104 10.0 Interrupts .................................................................................................................................................................................. 121 11.0 Power-Saving Operation Modes .............................................................................................................................................. 143 12.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 150 13.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 158 14.0 I/O Ports ................................................................................................................................................................................... 176 15.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 194 16.0 Peripheral Module Disable ....................................................................................................................................................... 203 17.0 Interrupt-On-Change ................................................................................................................................................................ 211 18.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 220 19.0 Temperature Indicator Module ................................................................................................................................................. 223 20.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 225 21.0 5-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 239 22.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 244 23.0 Comparator Module.................................................................................................................................................................. 254 24.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 264 25.0 Timer0 Module ......................................................................................................................................................................... 270 26.0 Timer1 Module with Gate Control............................................................................................................................................. 276 27.0 Timer2 Module With Hardware Limit Timer (HLT).................................................................................................................... 290 28.0 Capture/Compare/PWM Modules ............................................................................................................................................ 310 29.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 321 30.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 328 31.0 Configurable Logic Cell (CLC).................................................................................................................................................. 353 32.0 Host Synchronous Serial Port (MSSP1) Module...................................................................................................................... 370 33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 421 34.0 Reference Clock Output Module .............................................................................................................................................. 449 35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 453 36.0 Instruction Set Summary .......................................................................................................................................................... 455 37.0 Electrical Specifications............................................................................................................................................................ 468 38.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 497 39.0 Development Support .............................................................................................................................................................. 518 40.0 Packaging Information.............................................................................................................................................................. 519 The Microchip Website ...................................................................................................................................................................... 552 Customer Change Notification Service .............................................................................................................................................. 552 Customer Support .............................................................................................................................................................................. 552 Product Identification System ............................................................................................................................................................ 553  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001865E-page 11 PIC16(L)F15325/45 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001865E-page 12 PIC16(L)F15325/45 DEVICE OVERVIEW The PIC16(L)F15325/45 are described within this data sheet. The PIC16(L)F15325/45 devices are available in 14/20-pin PDIP, SSOP, SOIC, TSSOP, UQFN and VQFN packages. Figure 1-1 and Figure 1-2 show the block diagrams of the PIC16(L)F15325/45 devices. Table 1-2 and Table 1-3 show the pinout descriptions. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral PIC16(L)F15325/45 1.0 Analog-to-Digital Converter ● Digital-to-Analog Converter (DAC1) ● Fixed Voltage Reference (FVR) ● Numerically Controlled Oscillator (NCO1) ● Temperature Indicator Module (TIM) ● Zero-Cross Detect (ZCD1) ● Reference Table 1-1 for peripherals available per device. Capture/Compare/PWM Modules (CCP) CCP1 ● CCP2 ● C1 ● C2 ● CLC1 ● CLC2 ● CLC3 ● CLC4 ● CWG1 ● EUSART1 ● EUSART2 ● MSSP1 ● PWM3 ● PWM4 ● PWM5 ● PWM6 ● Timer0 ● Timer1 ● Timer2 ● Comparator Module (Cx) Configurable Logic Cell (CLC) Complementary Waveform Generator (CWG) Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) Host Synchronous Serial Ports (MSSP) Pulse-Width Modulator (PWM) Timers  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001865E-page 13 PIC16(L)F15325/45 1.1 1.1.1 Register and Bit Naming Conventions REGISTER NAMES When there are multiple instances of the same peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.1.2 BIT NAMES There are two variants for bit names: • Short name: Bit function abbreviation • Long name: Peripheral abbreviation + short name 1.1.2.1 Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction COG1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.1.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction.  2016-2022 Microchip Technology Inc. and its subsidiaries 1.1.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1