PIC16F15345-E/SO

PIC16(L)F15325/45 Full-Featured 14/20-Pin Microcontrollers Description PIC16(L)F15325/45 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications. The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture • Only 48 Instructions • Operating Speed: - DC – 32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Timers: - 8-bit Timer2 with Hardware Limit Timer (HLT) - 16-bit Timer0/1 • Low-Current Power-on Reset (POR) • Configurable Power-up Timer (PWRTE) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software • Programmable Code Protection • DOZE mode: Ability to Run the CPU Core Slower than the System Clock • IDLE mode: Ability to halt CPU Core while Internal Peripherals Continue Operating • SLEEP mode: Lowest Power Consumption • Peripheral Module Disable (PMD): - Ability to disable hardware module to minimize active power consumption of unused peripherals Memory • • • • Up to 14 KB Flash Program Memory Up to 1 KB Data SRAM Direct, Indirect and Relative Addressing modes Memory Access Partition (MAP): - Write protect - Customizable Partition • Device Information Area (DIA) • Device Configuration Information (DCI) Operating Characteristics • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF15325/45) - 2.3V to 5.5V (PIC16F15325/45) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C  2016 Microchip Technology Inc. eXtreme Low-Power (XLP) Features • • • • Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 A @ 32 kHz, 1.8V, typical - 32 A/MHz @ 1.8V, typical Digital Peripherals • Four Configurable Logic Cells (CLC): - Integrated combinational and sequential logic • Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources • Two Capture/Compare/PWM (CCP) module: - 16-bit resolution for Capture/Compare modes - 10-bit resolution for PWM mode • Four 10-Bit PWMs • Numerically Controlled Oscillator (NCO): - Generates true linear frequency control and increased frequency resolution - Input Clock: 0 Hz < FNCO < 32 MHz - Resolution: FNCO/220 • Two EUSART, RS-232, RS-485, LIN compatible • One SPI • One I2C, SMBus, PMBus™ compatible Preliminary DS40001865B PIC16(L)F15325/45 Digital Peripherals (Cont.) Flexible Oscillator Structure • I/O Pins: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select - Input level selection control (ST or TTL) - Digital open-drain enable • Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O • High-Precision Internal Oscillator: - Software selectable frequency range up to 32 MHz, ±1% typical • x2/x4 PLL with Internal and External Sources • Low-Power Internal 32 kHz Oscillator (LFINTOSC) • External 32 kHz Crystal Oscillator (SOSC) • External Oscillator Block with: - Three crystal/resonator modes up to 20 MHz - Three external clock modes up to 32 MHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if primary clock stops • Oscillator Start-up Timer (OST): - Ensures stability of crystal oscillator resources Analog Peripherals • Analog-to-Digital Converter (ADC): - 10-bit with up to 43 external channels - Operates in Sleep • Two Comparators: - FVR, DAC and external input pin available on inverting and noninverting input - Software selectable hysteresis - Outputs available internally to other modules, or externally through PPS • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive Reference Selection - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels • Zero-Cross Detect module: - AC high voltage zero-crossing detection for simplifying TRIAC control - Synchronized switching control and timing  2016 Microchip Technology Inc. Preliminary DS40001865B-page 2 PIC16(L)F15325/45 5-bit DAC Comparator 8-bit/ (with HLT) Timer 16-bit Timer Window Watchdog Timer CCP/10-bit PWM CWG NCO CLC Memory Access Partition Device Information Area Peripheral Pin Select Peripheral Module Disable Debug (1) 6 5 1 1 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I PIC16(L)F15323 (C) 2 3.5 224 256 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I 224 512 EUSART/ I2C-SPI 10-bit ADC 3.5 224 256 Zero-Cross Detect Temperature Indicator I/OPins 2 Data SRAM (bytes) Program Flash Memory (KB) PIC16(L)F15313 (C) Device Storage Area Flash (B) Program Flash Memory (KW) PIC16(L)F153XX FAMILY TYPES Data Sheet Index TABLE 1: PIC16(L)F15324 (D) 4 7 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15325 (B) 8 14 224 1024 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15344 (D) 4 7 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15345 (B) 8 14 224 1024 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I PIC16(L)F15354 (A) 4 7 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15355 (A) 8 14 224 1024 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15356 (E) 16 28 224 2048 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15375 (E) 8 14 224 1024 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15376 (E) 16 28 224 2048 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15385 (E) 8 14 224 1024 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I PIC16(L)F15386 (E) 16 28 224 2048 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I Note 1: 224 512 224 512 I - Debugging integrated on chip. Data Sheet Index: A: DS40001853 PIC16(L)F15354/5 Data Sheet, 28-Pin B: DS40001865 PIC16(L)F15325/45 Data Sheet, 14/20-Pin C: Future Release PIC16(L)F15313/23 Data Sheet, 8/14-Pin D: Future Release PIC16(L)F15324/44 Data Sheet, 14/20-Pin E: PIC16(L)F15356/75/76/85/86 Data Sheet, 28/40/48-Pin Note: DS40001866 For other small form-factor package availability and marking information, visit www.microchip.com/packaging or contact your local sales office.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 3 PIC16(L)F15325/45 TABLE 2: PACKAGES Device PDIP SOIC SSOP PIC16(L)F15325      PIC16(L)F15345  2016 Microchip Technology Inc. Preliminary TSSOP UQFN (4x4)    DS40001865B-page 4 PIC16(L)F15325/45 PIN DIAGRAMS 1 2 3 4 5 6 7 20-PIN PDIP, SOIC, SSOP VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 VDD 1 20 VSS RA5 2 RA4 3 19 RA0/ICSPDAT 18 RA1/ICSPCLK 17 RA2 16 RC0 15 RC1 MCLR/VPP/RA3 4 RC5 5 RC4 6 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 RC3 7 Note: 14 13 12 11 10 9 8 See Table 3 for location of all peripheral functions. PIC16(L)F15345 Note: VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 PIC16(L)F15325 14-PIN PDIP, SOIC, TSSOP See Table 4 for location of all peripheral functions. VDD NC NC Vss 16-PIN UQFN (4X4) 16 15 14 13 RA5 RA4 MCLR/VPP/RA3 RC5 1 2 3 4 PIC16(L)F15325 12 11 10 9 RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC4 RC3 RC2 RC1 5 6 7 8 Note 1: 2: See Table 3 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 5 RA4 RA5 VDD Vss RA0/ICSPDAT PIC16(L)F15325/45 20-PIN UQFN (4x4) 53 )F 1 (L 16 C 1 2 3 4 5 PI RA3/MCLR/VPP RC5 RC4 RC3 RC6 45 20 19 18 17 16 15 14 13 12 11 RA1/ICSPCLK RA2 RC0 RC1 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 Note 1: 2: See Table 4 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 6 PWM CWG MSSP ZCD EUSART CLC CLKR C1IN0+ ― DAC1OUT ― ― ― ― ― ― ― ― ― IOCA0 Y ICSPDAT VREF+ C1IN0C2IN0- ― DAC1REF+ T0CKI(1) ― ― ― ― ― ― ― ― IOCA1 Y ICSPCLK RA2 11 10 ANA2 ― ― ― ― ― ― ― CWG1IN(1) ― ZCD1 ― ― ― INT(1) IOCA2 Y ― RA3 4 3 ― ― ― ― ― ― ― ― ― ― ― ― ― ― IOCA3 Y MCLR VPP RA4 3 2 ANA4 ― C1IN1- ― ― T1G(1) SOSCO ― ― ― ― ― ― ― ― IOCA4 Y CLKOUT OSC2 RA5 2 1 ANA5 ― ― ― ― T1CKI(1) T2IN SOSCIN ― ― ― ― ― CLCIN3(1) ― IOCA5 Y CLKIN OSC1 EIN RC0 10 9 ANC0 ― C2IN0+ ― ― ― ― ― ― SCK1(1) SCL1(1,4) ― ― ― ― IOCC0 Y ― RC1 9 8 ANC1 ― C1IN1C2IN1- ― ― ― ― ― ― SDA1(1,4) SDI1(1) ― ― CLCIN2(1) ― IOCC1 Y ― RC2 8 7 ANC2 ― C1IN2C2IN2- ― ― ― ― ― ― ― ― ― ― ― IOCC2 Y ― RC3 7 6 ANC3 ― C1IN3C2IN3- ― ― ― CCP2(1) ― ― SS1(1) ― ― CLCIN0(1) ― IOCC3 Y ― RC4 6 5 ANC4 ― ― ― ― ― ― ― ― ― ― TX1(1) CK1(1) CLCIN1(1) ― IOCC4 Y ― RC5 5 4 ANC5 ― ― ― ― ― CCP1(1) ― ― ― ― RX1(1) DT1(1) ― ― IOCC5 Y ― VDD 1 16 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD VSS 14 13 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS Note 1: 2: 3: 4: Basic CCP ― ANA1 Pull-up Timers ANA0 11 Interrupt NCO 12 12 DAC Comparator 13 RA1 ADC RA0 This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865B-page 7 Reference Preliminary 16-Pin QFN/UQFN 14/16-PIN ALLOCATION TABLE (PIC16(L)F15325) 14-Pin PDIP/SOIC/TSSOP TABLE 3: I/O(2)  2016 Microchip Technology Inc. PIN ALLOCATION TABLES 16-Pin QFN/UQFN ADC Reference Comparator NCO DAC Timers CCP PWM CWG MSSP ZCD CLC CLKR Interrupt Pull-up Basic OUT(2) ― ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3OUT CWG1A SDO1 ― DT1(3) DT2(3) CLC1OUT CLKR ― ― ― ― ― ― ― C2OUT ― ― ― CCP2 PWM4OUT CWG1B SCK1 ― CK1 CK2 CLC2OUT ― ― ― ― ― ― ― ― ― ― ― ― ― PWM5OUT CWG1C SCL1(3,4) ― TX1 TX2 CLC3OUT ― ― ― ― ― ― ― ― ― ― ― ― PWM6OUT CWG1D SDA1(3,4) ― ― CLC4OUT ― ― ― ― ― Note Preliminary 1: 2: 3: 4: EUSART 14-Pin PDIP/SOIC/TSSOP 14/16-PIN ALLOCATION TABLE (PIC16(L)F15325) (CONTINUED) I/O(2)  2016 Microchip Technology Inc. TABLE 3: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865B-page 8 CLC CLKR ― ― ― ― ― ― ― ― IOCA0 Y ICSPDAT T0CKI(1) ― ― ― ― ― ― ― ― IOCA1 Y ICSPCLK RA2 17 14 ANA2 ― ― ― ― ― ― ― CWG1IN(1) ― ZCD1 ― CLCIN0(1) ― INT(1) IOCA2 Y ― RA3 4 1 ― ― ― ― ― ― ― ― ― ― ― ― ― ― IOCA3 Y MCLR VPP RA4 3 20 ANA4 ― C1IN1- ― ― T1G(1) SOSCO ― ― ― ― ― ― ― ― IOCA4 Y CLKOUT OSC2 RA5 2 19 ANA5 ― ― ― ― T1CKI(1) T2IN SOSCIN ― ― ― ― ― ― ― IOCA5 Y CLKIN OSC1 EIN RB4 13 10 ANB4 ADACT(1) ― ― ― ― ― ― ― ― SCK1(1) SCL1(1,4) ― ― CLCIN2(1) ― IOCB4 ― ― RB5 12 9 ANB5 ― ― ― ― ― ― ― ― ― ― RX2(1) DT2(1) CLCIN3(1) ― IOCB5 ― ― RB6 11 8 ANB6 ― ― ― ― ― ― ― ― SDA1(1,4) SDI1(1) ― ― ― ― IOCB6 Y ― RB7 10 7 ANB7 ― ― ― ― ― ― ― ― ― ― TX2(1) CK2(1) ― ― IOCB7 Y ― RC0 16 13 ANC0 ― C2IN0+ ― ― ― ― ― ― ― ― ― ― ― IOCC0 Y ― RC1 15 12 ANC1 ― C1IN1C2IN1- ― ― ― ― ― ― ― ― ― ― ― IOCC1 Y ― RC2 14 11 ANC2 ― C1IN2C2IN2- ― ― ― ― ― ― ― ― ― ― ― IOCC2 Y ― RC3 7 4 ANC3 ― C1IN3C2IN3- ― ― ― CCP2(1) ― ― ― ― ― CLCIN1(1) ― IOCC3 Y ― RC4 6 3 ANC4 ― ― ― ― ― ― ― ― ― ― ― ― ― IOCC4 Y ― RC5 5 2 ANC5 ― ― ― ― ― CCP1(1) ― ― ― ― ― ― ― IOCC5 Y ― RC6 8 5 ANC6 ― ― ― ― ― ― ― ― SS1(1) ― ― ― ― IOCC6 Y ― 6 ANC7 ― ― ― ― ― ― ― ― ― ― ― ― ― IOCC7 Y ― RC7 Note 9 1: 2: 3: 4: Basic EUSART ― DAC1REF+ Pull-up CWG DAC1OUT ― Interrupt PWM ― C1IN0C2IN0- ZCD CCP C1IN0+ VREF+ MSSP Timers ― ANA1 DAC ANA0 15 NCO Comparator 16 18 ADC 19 RA1 20-Pin UQFN RA0 This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865B-page 9 Reference Preliminary 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F15345) I/O(2)  2016 Microchip Technology Inc. TABLE 4: ADC Reference Comparator NCO DAC Timers CCP PWM CWG MSSP ZCD CLC CLKR Interrupt Pull-up Basic 1 18 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD VSS 20 17 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS OUT(2) ― ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3OUT CWG1A SDO1 ― DT1(3) DT2(3) CLC1OUT CLKR ― ― ― ― ― ― ― C2OUT ― ― ― CCP2 PWM4OUT CWG1B SCK1 ― CK1 CK2 CLC2OUT ― ― ― ― ― ― ― ― ― ― ― ― ― PWM5OUT CWG1C SCL1(3,4) ― TX1 TX2 CLC3OUT ― ― ― ― ― ― ― ― ― ― ― ― PWM6OUT CWG1D SDA1(3,4) ― ― CLC4OUT ― ― ― ― ― Note Preliminary 1: 2: 3: 4: EUSART 20-Pin UQFN 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F15345) (CONTINUED) VDD I/O(2)  2016 Microchip Technology Inc. TABLE 4: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. PIC16(L)F15325/45 DS40001865B-page 10 PIC16(L)F15325/45 Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 31.0 32.0 33.0 34.0 35.0 36.0 37.0 38.0 39.0 40.0 Device Overview ........................................................................................................................................................................ 13 Guidelines for Getting Started with PIC16(L)F15325/45 Microcontrollers.................................................................................. 26 Enhanced Mid-Range CPU ........................................................................................................................................................ 29 Memory Organization ................................................................................................................................................................. 31 Device Configuration .................................................................................................................................................................. 79 Device Information Area............................................................................................................................................................. 89 Device Configuration Information ............................................................................................................................................... 91 Resets ........................................................................................................................................................................................ 92 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 103 Interrupts .................................................................................................................................................................................. 120 Power-Saving Operation Modes .............................................................................................................................................. 142 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 149 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 157 I/O Ports ................................................................................................................................................................................... 175 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 193 Peripheral Module Disable ....................................................................................................................................................... 203 Interrupt-On-Change ................................................................................................................................................................ 211 Fixed Voltage Reference (FVR) .............................................................................................................................................. 219 Temperature Indicator Module ................................................................................................................................................. 222 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 225 5-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 239 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 244 Comparator Module.................................................................................................................................................................. 254 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 264 Timer0 Module ......................................................................................................................................................................... 270 Timer1 Module with Gate Control............................................................................................................................................. 276 Timer2 Module With Hardware Limit Timer (HLT).................................................................................................................... 289 Capture/Compare/PWM Modules ............................................................................................................................................ 314 Pulse-Width Modulation (PWM) ............................................................................................................................................... 326 Complementary Waveform Generator (CWG) Module ............................................................................................................ 333 Configurable Logic Cell (CLC).................................................................................................................................................. 358 Master Synchronous Serial Port (MSSP1) Module .................................................................................................................. 375 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 426 Reference Clock Output Module .............................................................................................................................................. 454 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 458 Instruction Set Summary .......................................................................................................................................................... 460 Electrical Specifications............................................................................................................................................................ 473 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 502 Development Support............................................................................................................................................................... 503 Packaging Information.............................................................................................................................................................. 507  2016 Microchip Technology Inc. Preliminary DS40001865B-page 11 PIC16(L)F15325/45 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 12 PIC16(L)F15325/45 DEVICE OVERVIEW The PIC16(L)F15325/45 are described within this data sheet. The PIC16(L)F15325/45 devices are available in 14/20-pin PDIP, SSOP, SOIC, TSSOP, and UQFN packages. Figure 1-1 and Figure 1-2 shows the block diagrams of the PIC16(L)F15325/45 devices. Table 1-2 and Table 1-3 shows the pinout descriptions. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral PIC16(L)F15325/45 1.0 Analog-to-Digital Converter ● Digital-to-Analog Converter (DAC1) ● Fixed Voltage Reference (FVR) ● Enhanced Universal Synchronous/Asynchronous Receiver/ Transmitter (EUSART1 and EUSART2) ● Numerically Controlled Oscillator (NCO1) ● Temperature Indicator Module (TIM) ● Zero-Cross Detect (ZCD1) ● Reference Table 1-1 for peripherals available per device. Capture/Compare/PWM Modules (CCP) CCP1 ● CCP2 ● C1 ● C2 ● CLC1 ● CLC2 ● CLC3 ● CLC4 ● CWG1 ● MSSP1 ● PWM3 ● PWM4 ● PWM5 ● PWM6 ● Timer0 ● Timer1 ● Timer2 ● Comparator Module (Cx) Configurable Logic Cell (CLC) Complementary Waveform Generator (CWG) Master Synchronous Serial Ports (MSSP) Pulse-Width Modulator (PWM) Timers  2016 Microchip Technology Inc. Preliminary DS40001865B-page 13 PIC16(L)F15325/45 1.1 1.1.1 1.1.2.3 Register and Bit Naming Conventions REGISTER NAMES When there are multiple instances of the same peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.1.2 BIT NAMES There are two variants for bit names: • Short name: Bit function abbreviation • Long name: Peripheral abbreviation + short name 1.1.2.1 Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction COG1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.1.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction.  2016 Microchip Technology Inc. Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(11) when the T1CKI signal is currently logic low. DS40001865B-page 277 PIC16(L)F15325/45 26.3 26.5.1 Timer Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 26.4 Secondary Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is designed to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. The oscillator will continue to run during Sleep. Note: 26.5 The oscillator requires a start-up and stabilization time before use. Thus, SOSCEN should be set and a suitable delay observed prior to using Timer1 with the SOSC source. A suitable delay similar to the OST delay can be implemented in software by clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to FC00h. The TMR1IF flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. Timer Operation in Asynchronous Counter Mode If the control bit SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 26.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 26.6 Timer Gate Timer1 can be configured to count freely or the count can be enabled and disabled using the time gate circuitry. This is also referred to as Timer Gate Enable. The timer gate can also be driven by multiple selectable sources. 26.6.1 TIMER GATE ENABLE The Timer Gate Enable mode is enabled by setting the GE bit of the T1GCON register. The polarity of the Timer Gate Enable mode is configured using the GPOL bit of the T1GCON register. When Timer Gate Enable signal is enabled, the timer will increment on the rising edge of the Timer1 clock source. When Timer Gate Enable signal is disabled, the timer always increments, regardless of the GE bit. See Figure 26-3 for timing details. TABLE 26-2: TIMER GATE ENABLE SELECTIONS T1CLK T1GPOL T1G Timer Operation  1 1 Counts  1 0 Holds Count  0 1 Holds Count  0 0 Counts When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 278 PIC16(L)F15325/45 26.6.2 TIMER GATE SOURCE SELECTION One of the several different external or internal signal sources may be chosen to gate the timer and allow the timer to increment. The gate input signal source can be selected based on the T1GATE register setting. See the T1GATE register (Register 26-4) description for a complete list of the available gate sources. The polarity for each available source is also selectable. Polarity selection is controlled by the GPOL bit of the T1GCON register. 26.6.2.1 T1G Pin Gate Operation The T1G pin is one source for the timer gate control. It can be used to supply an external source to the time gate circuitry. 26.6.2.2 Timer0 Overflow Gate Operation 26.6.4 TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the GSPM bit in the T1GCON register. Next, the GGO/DONE bit in the T1GCON register must be set. The timer will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment the timer until the GGO/DONE bit is once again set in software. See Figure 26-5 for timing details. If the Single-Pulse Gate mode is disabled by clearing the GSPM bit in the T1GCON register, the GGO/DONE bit should also be cleared. When Timer0 overflows, or a period register match condition occurs (in 8-bit mode), a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the timer gate source to be measured. See Figure 26-6 for timing details. 26.6.2.3 26.6.5 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for the timer gate control. The Comparator 1 output can be synchronized to the timer clock or left asynchronous. For more information see Section 23.4.1 “Comparator Output Synchronization”. 26.6.2.4 The output resulting from a Comparator 2 operation can be selected as a source for the timer gate control. The Comparator 2 output can be synchronized to the timer clock or left asynchronous. For more information see Section 23.4.1 “Comparator Output Synchronization”. 26.6.3 When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the GVAL bit in the T1GCON register. The GVAL bit is valid even when the timer gate is not enabled (GE bit is cleared). 26.6.6 Comparator C2 Gate Operation TIMER1 GATE TOGGLE MODE TIMER1 GATE VALUE STATUS TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of GVAL occurs, the TMR1GIF flag bit in the PIR5 register will be set. If the TMR1GIE bit in the PIE5 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the timer gate is not enabled (TMR1GE bit is cleared). When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a timer gate signal, as opposed to the duration of a single level pulse. The timer gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 26-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the GTM bit of the T1GCON register. When the GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 279 PIC16(L)F15325/45 26.7 Timer1 Interrupts 26.9 The timer register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When the timer rolls over, the respective timer interrupt flag bit of the PIR5 register is set. To enable the interrupt on rollover, you must set these bits: • • • • ON bit of the T1CON register TMR1IE bit of the PIE4 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 26.8 To avoid immediate interrupt vectoring, the TMR1H:TMR1L register pair should be preloaded with a value that is not imminently about to rollover, and the TMR1IF flag should be cleared prior to enabling the timer interrupts. The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. In Compare mode, an event is triggered when the value CCPRxH:CCPRxL register pair matches the value in the TMR1H:TMR1L register pair. This event can be an Auto-conversion Trigger. For more information, see “Capture/Compare/PWM Modules”. Section 28.0 26.10 CCP Auto-Conversion Trigger When any of the CCP’s are configured to trigger an auto-conversion, the trigger will clear the TMR1H:TMR1L register pair. This auto-conversion does not cause a timer interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1. Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • • CCP Capture/Compare Time Base ON bit of the T1CON register must be set TMR1IE bit of the PIE4 register must be set PEIE bit of the INTCON register must be set SYNC bit of the T1CON register must be set CS bits of the T1CLK register must be configured The timer clock source must be enabled and continue operation during sleep. When the SOSC is used for this purpose, the SOSCEN bit of the OSCEN register must be set. The timer should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Auto-conversion Trigger. Asynchronous operation of the timer can cause an Auto-conversion Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with an Auto-conversion Trigger from the CCP, the write will take precedence. For more information, see Section 28.2.4 “Compare During Sleep”. The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. Secondary oscillator will continue to operate in Sleep regardless of the SYNC bit setting.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 280 PIC16(L)F15325/45 FIGURE 26-2: TIMER1 INCREMENTING EDGE TxCKI = 1 when the timer is enabled TxCKI = 0 when the timer is enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 26-3: TIMER1 GATE ENABLE MODE TMRxGE TxGPOL Selected gate input TxCKI TxGVAL TMRxH:TMRxL Count  2016 Microchip Technology Inc. N N+1 Preliminary N+2 N+3 N+4 DS40001865B-page 281 PIC16(L)F15325/45 FIGURE 26-4: TIMER1 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM Selected gate input TxCKI TxGVAL TMRxH:TMRxL Count FIGURE 26-5: N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ DONE Cleared by hardware on falling edge of TxGVAL Set by software Counting enabled on rising edge of selected source Selected gate source TxCKI TxGVAL TMRxH:TMRxL Count TMRxGIF N N+1 Set by hardware on falling edge of TxGVAL Cleared by software  2016 Microchip Technology Inc. N+2 Preliminary Cleared by software DS40001865B-page 282 PIC16(L)F15325/45 FIGURE 26-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ DONE Cleared by hardware on falling edge of TxGVAL Set by software Counting enabled on rising edge of selected source Selected gate source TxCKI TxGVAL TMRxH:TMRxL Count TMRxGIF N Cleared by software  2016 Microchip Technology Inc. N+1 N+2 N+3 N+4 Set by hardware on falling edge of TxGVAL Preliminary Cleared by software DS40001865B-page 283 PIC16(L)F15325/45 26.11 Register Definitions: Timer1 Control REGISTER 26-1: T1CON: TIMER1 CONTROL REGISTER U-0 U-0 — — R/W-0/u R/W-0/u CKPS U-0 R/W-0/u R/W-0/u R/W-0/u — SYNC RD16 ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CKPS: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 Unimplemented: Read as ‘0’ bit 2 SYNC: Timer1 Synchronization Control bit When TMR1CLK = FOSC or FOSC/4 This bit is ignored. The timer uses the internal clock and no additional synchronization is performed. ELSE 0 = Synchronize external clock input with system clock 1 = Do not synchronize external clock input bit 1 RD16: 16-bit Read/Write Mode Enable bit 0 = Enables register read/write of Timer1 in two 8-bit operation 1 = Enables register read/write of Timer1 in one 16-bit operation bit 0 ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop  2016 Microchip Technology Inc. Preliminary DS40001865B-page 284 PIC16(L)F15325/45 REGISTER 26-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x U-0 U-0 GE GPOL GTM GSPM GGO/DONE GVAL — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 GE: Timer1 Gate Enable bit If ON = 0: This bit is ignored If ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 is always counting bit 6 GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when GSPM is cleared bit 2 GVAL: Timer1 Gate Value Status bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L Unaffected by Timer1 Gate Enable (GE) bit 1-0 Unimplemented: Read as ‘0’  2016 Microchip Technology Inc. Preliminary DS40001865B-page 285 PIC16(L)F15325/45 REGISTER 26-3: T1CLK TIMER1 CLOCK SELECT REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/u R/W-0/u R/W-0/u R/W-0/u CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CS: Timer1 Clock Select bits 1111 = Reserved 1110 = Reserved 1101 = LC4_out 1100 = LC3_out 1011 = LC2_out 1010 = LC1_out 1001 = Timer0 overflow output 1000 = CLKR output 0111 = SOSC 0110 = MFINTOSC (32 kHz) 0101 = MFINTOSC (500 kHz) 0100 = LFINTOSC 0011 = HFINTOSC 0010 = FOSC 0001 = FOSC/4 0000 = T1CKIPPS  2016 Microchip Technology Inc. Preliminary DS40001865B-page 286 PIC16(L)F15325/45 REGISTER 26-4: T1GATE TIMER1 GATE SELECT REGISTER U-0 U-0 U-0 — — — R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u GSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 GSS: Timer1 Gate Select bits 11111-10001 = Reserved 10000 = LC4_out 01111 = LC3_out 01110 = LC2_out 01101 = LC1_out 00100 = ZCD1_output 01011 = C2OUT_sync 01010 = C1OUT_sync 01001 = NCO1_out 01000 = PWM6_out 00111 = PWM5_out 00110 = PWM4_out 00101 = PWM3_out 00100 = CCP2_out 00011 = CCP1_out 00010 = TMR2_postscaled 00001 = Timer0 overflow output 00000 = T1GPPS  2016 Microchip Technology Inc. Preliminary DS40001865B-page 287 PIC16(L)F15325/45 TABLE 26-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE ― ― ― ― ― INTEDG 124 PIE4 — — — — — — TMR2IE TMR1IE 129 PIR4 — — — — — — TMR2IF TMR1IF 137 — SYNC RD16 ON 284 GGO/DONE GVAL — — 285 T1CON — — T1GCON GE GPOL GTM T1GATE — — — — — — T1CLK CKPS GSPM GSS — CS 287 286 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 276* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 276* T1CKIPPS ― ― T1CKIPPS 199 T1GPPS ― ― T1GPPS 199 CCPxCON CCPxEN CCPxOE CLCxSELy ― ― ― ADACT ― ― ― Legend: * CCPxOUT CCPxFMT CCPxMODE LCxDyS ― ADACT 321 367 235 — = Unimplemented location, read as ‘0’. Shaded cells are not used with the Timer1 modules. Page with register information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 288 PIC16(L)F15325/45 27.0 • • • • • • • TIMER2 MODULE WITH HARDWARE LIMIT TIMER (HLT) The Timer2 modules are 8-bit timers that can operate as free-running period counters or in conjunction with external signals that control start, run, freeze, and reset operation in One-Shot and Monostable modes of operation. Sophisticated waveform control such as pulse density modulation are possible by combining the operation of these timers with other internal peripherals such as the comparators and CCP modules. Features of the timer include: See Figure 27-1 for a block diagram of Timer2. See Figure 27-2 for the clock source block diagram. • 8-bit timer register • 8-bit period register FIGURE 27-1: TIMER2 BLOCK DIAGRAM RSEL INPPS TxIN PPS External Reset (2) Sources Selectable external hardware timer Resets Programmable prescaler (1:1 to 1:128) Programmable postscaler (1:1 to 1:16) Selectable synchronous/asynchronous operation Alternate clock sources Interrupt-on-period Three modes of operation: - Free Running Period - One-shot - Monostable Rev. 10-000168C 9/10/2015 MODE TMRx_ers Edge Detector Level Detector Mode Control (2 clock Sync) MODE reset CCP_pset(1) MODE=01 enable D MODE=1011 Q Clear ON CPOL 0 Prescaler TMRx_clk T[7MR 3 CKPS Sync 1 Fosc/4 PSYNC R Comparator Set flag bit TMRxIF Postscaler TMRx_postscaled 4 Sync (2 Clocks) ON 1 7[PR OUTPS 0 CSYNC Note 1: 2: Signal to the CCP to trigger the PWM pulse. See Register 27-4 for external Reset sources.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 289 PIC16(L)F15325/45 FIGURE 27-2: TIMER2 CLOCK SOURCE BLOCK DIAGRAM TxCLKCON Rev. 10-000 169B 5/29/201 4 TXINPPS TXIN 27.1.2 PPS Timer Clock Sources (See Table 27-2) the output postscaler counter. When the postscaler count equals the value in the OUTPS bits of the TMRxCON1 register, a one TMR2_clk period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared. The One-Shot mode is identical to the Free Running Period mode except that the ON bit is cleared and the timer is stopped when TMR2 matches T2PR and will not restart until the T2ON bit is cycled off and on. Postscaler OUTPS values other than 0 are meaningless in this mode because the timer is stopped at the first period event and the postscaler is reset when the timer is restarted. TMR2_clk 27.1.3 27.1 ONE-SHOT MODE MONOSTABLE MODE Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can be restarted by an external Reset event. Timer2 Operation Timer2 operates in three major modes: 27.2 • Free Running Period • One-shot • Monostable The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period when the postscaler counter matches the value in the OUTPS bits of the TMR2CON register. The T2PR postscaler is incremented each time the TMR2 value matches the T2PR value. This signal can be selected as an input to several other input modules: Within each mode there are several options for starting, stopping, and reset. Table 27-1 lists the options. In all modes, the TMR2 count register is incremented on the rising edge of the clock signal from the programmable prescaler. When TMR2 equals T2PR, a high level is output to the postscaler counter. TMR2 is cleared on the next clock input. An external signal from hardware can also be configured to gate the timer operation or force a TMR2 count Reset. In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes the TMR2 count is reset on either the level or edge from the external source. The TMR2 and T2PR registers are both directly readable and writable. The TMR2 register is cleared and the T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters are cleared on the following events: • • • • a write to the TMR2 register a write to the T2CON register any device Reset External Reset Source event that resets the timer. Note: 27.1.1 TMR2 is not cleared when T2CON is written. FREE RUNNING PERIOD MODE The value of TMR2 is compared to that of the Period register, T2PR, on each TMR2_clk cycle. When the two values match, the comparator resets the value of TMR2 to 00h on the next rising TMR2_clk edge and increments  2016 Microchip Technology Inc. Timer2 Output • The ADC module, as an Auto-conversion Trigger • COG, as an auto-shutdown source In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. Both the actual TMR2 value as well as other internal signals are sent to the CCP module to properly clock both the period and pulse width of the PWM signal. See Section 28.0 “Capture/Compare/PWM Modules” for more details on setting up Timer2 for use with the CCP, as well as the timing diagrams in Section 27.5 “Operation Examples” for examples of how the varying Timer2 modes affect CCP PWM output. 27.3 External Reset Sources In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset source is selected for Timer2 with the T2RST register. This source can control starting and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. The mode of the timer is controlled by the MODE bits of the TMRxHLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug Freeze mode. Preliminary DS40001865B-page 290 PIC16(L)F15325/45 TABLE 27-1: TIMER2 OPERATING MODES MODE Mode Output Operation 000 001 Period Pulse 010 Free Running Period Start Reset Stop Software gate (Figure 27-4) ON = 1 — ON = 0 Hardware gate, active-high (Figure 27-5) ON = 1 and TMRx_ers = 1 — ON = 0 or TMRx_ers = 0 Hardware gate, active-low ON = 1 and TMRx_ers = 0 — ON = 0 or TMRx_ers = 1 011 Rising or falling edge Reset TMRx_ers ↕ 100 Rising edge Reset (Figure 27-6) TMRx_ers ↑ 00 101 110 Period Pulse with Hardware Reset 111 000 001 010 One-shot Edge triggered start (Note 1) 011 One-shot Timer Control Operation 01 100 101 110 111 Edge triggered start and hardware Reset (Note 1) Falling edge Reset Mono-stable 010 High level Reset (Figure 27-7) 10 Reserved 111 Reserved Note 1: 2: 3: 11 TMRx_ers = 1 ON = 0 or TMRx_ers = 1 ON = 1 — Rising edge start (Figure 27-9) ON = 1 and TMRx_ers ↑ — Falling edge start ON = 1 and TMRx_ers ↓ — Any edge start ON = 1 and TMRx_ers ↕ — Rising edge start and Rising edge Reset (Figure 27-10) ON = 1 and TMRx_ers ↑ TMRx_ers ↑ Falling edge start and Falling edge Reset ON = 1 and TMRx_ers ↓ TMRx_ers ↓ Rising edge start and Low level Reset (Figure 27-11) ON = 1 and TMRx_ers ↑ TMRx_ers = 0 Falling edge start and High level Reset ON = 1 and TMRx_ers ↓ TMRx_ers = 1 Edge triggered start (Note 1) Rising edge start (Figure 27-12) ON = 1 and TMRx_ers ↑ — Falling edge start ON = 1 and TMRx_ers ↓ — Any edge start ON = 1 and TMRx_ers ↕ — ON = 0 or Next clock after TMRx = PRx (Note 2) ON = 0 or Next clock after TMRx = PRx (Note 3) Reserved Reserved 101 One-shot ON = 0 or TMRx_ers = 0 Software start (Figure 27-8) 100 110 TMRx_ers = 0 Reserved 011 Reserved TMRx_ers ↓ ON = 1 Low level Reset 000 001 ON = 0 Level triggered start and hardware Reset High level start and Low level Reset (Figure 27-13) ON = 1 and TMRx_ers = 1 TMRx_ers = 0 Low level start & High level Reset ON = 1 and TMRx_ers = 0 TMRx_ers = 1 ON = 0 or Held in Reset (Note 2) Reserved xxx If ON = 0 then an edge is required to restart the timer after ON = 1. When TMRx = PRx then the next clock clears ON and stops TMRx at 00h. When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 291 PIC16(L)F15325/45 27.4 Timer2 Interrupt Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches one of 16 postscale options (from 1:1 through 1:16), which are selected with the postscaler control bits, OUTPS of the T2CON register. The interrupt is enabled by setting the TMR2IE interrupt enable bit of the PIE4 register. Interrupt timing is illustrated in Figure 27-3. FIGURE 27-3: TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM Rev. 10-000205A 4/7/2016 0b010 CKPS PRx 1 OUTPS 0b0001 TMRx_clk TMRx 0 0 1 1 0 1 0 TMRx_postscaled TMRxIF (1) (2) (1) Note 1: Setting the interrupt flag is synchronized with the instruction clock. Synchronization may take as many as 2 instruction cycles 2: Cleared by software.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 292 PIC16(L)F15325/45 27.5 27.5.1 Operation Examples Unless otherwise specified, the following notes apply to the following timing diagrams: - Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the TxCON register are cleared). - The diagrams illustrate any clock except Fosc/4 and show clock-sync delays of at least two full cycles for both ON and Timer2_ers. When using Fosc/4, the clock-sync delay is at least one instruction period for Timer2_ers; ON applies in the next instruction period. - The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in Section 28.0 “Capture/Compare/PWM Modules”. The signals are not a part of the Timer2 module.  2016 Microchip Technology Inc. SOFTWARE GATE MODE This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 27-4. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock. Preliminary DS40001865B-page 293 PIC16(L)F15325/45 FIGURE 27-4: SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000) Rev. 10-000195B 5/30/2014 0b00000 MODE TMRx_clk Instruction(1) BSF BCF BSF ON PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 294 PIC16(L)F15325/45 27.5.2 HARDWARE GATE MODE When MODE = 00001 then the timer is stopped when the external signal is high. When MODE = 00010 then the timer is stopped when the external signal is low. The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal gates the timer. When used with the CCP the gating extends the PWM period. If the timer is stopped when the PWM output is high then the duty cycle is also extended. FIGURE 27-5: Figure 27-5 illustrates the Hardware Gating mode for MODE = 00001 in which a high input level starts the counter. HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001) Rev. 10-000 196B 5/30/201 4 0b00001 MODE TMRx_clk TMRx_ers PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output  2016 Microchip Technology Inc. Preliminary DS40001865B-page 295 PIC16(L)F15325/45 27.5.3 EDGE-TRIGGERED HARDWARE LIMIT MODE When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 27-6. In Hardware Limit mode the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: • Reset on rising or falling edge (MODE= 00011) • Reset on rising edge (MODE = 00100) • Reset on falling edge (MODE = 00101) FIGURE 27-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM (MODE = 00100) Rev. 10-000 197B 5/30/201 4 0b00100 MODE TMRx_clk PRx 5 Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 296 PIC16(L)F15325/45 27.5.4 LEVEL-TRIGGERED HARDWARE LIMIT MODE When the CCP uses the timer as the PWM time base then the PWM output will be set high when the timer starts counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the timer count matches the PRx value or two clock periods after the external Reset signal goes true and stays true. In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 27-7. Selecting MODE = 00110 will cause the timer to reset on a low level external signal. Selecting MODE = 00111 will cause the timer to reset on a high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0 the external signal is ignored. FIGURE 27-7: The timer starts counting, and the PWM output is set high, on either the clock following the PRx match or two clocks after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to match the CCPRx pulse width value. If the external Reset signal goes true while the PWM output is high then the PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx value. LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM (MODE = 00111) Rev. 10-000198B 5/30/2014 0b00111 MODE TMRx_clk 5 PRx Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 297 PIC16(L)F15325/45 27.5.5 SOFTWARE START ONE-SHOT MODE In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the PRx period value. The ON bit must be set by software to start another timer cycle. Setting MODE = 01000 selects One-Shot mode which is illustrated in Figure 27-8. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. FIGURE 27-8: When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match. SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000) Rev. 10-000199B 4/7/2016 0b01000 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 298 PIC16(L)F15325/45 27.5.6 EDGE-TRIGGERED ONE-SHOT MODE The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer: • Rising edge (MODE = 01001) • Falling edge (MODE = 01010) • Rising or Falling edge (MODE = 01011) FIGURE 27-9: If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 27-9 illustrates operation in the rising edge One-Shot mode. When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay deactivated when the timer halts at the PRx period count match. EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001) Rev. 10-000200B 5/19/2016 0b01001 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 CCP_pset TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 299 PIC16(L)F15325/45 27.5.7 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: • Rising edge start and Reset (MODE = 01100) • Falling edge start and Reset (MODE = 01101) The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 27-10 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 300  2016 Microchip Technology Inc. FIGURE 27-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100) Rev. 10-000201B 4/7/2016 MODE 0b01100 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0 Preliminary TMRx_postscaled PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001865B-page 301 PIC16(L)F15325/45 Note PIC16(L)F15325/45 27.5.8 LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODES In Level -Triggered One-Shot mode the timer count is reset on the external signal level and starts counting on the rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are selected as follows: • Low Reset level (MODE = 01110) • High Reset level (MODE = 01111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control a new external signal edge is required after the ON bit is set to start the counter. When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx period count match.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 302  2016 Microchip Technology Inc. FIGURE 27-11: LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110) Rev. 10-000202B 4/7/2016 MODE 0b01110 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 0 1 2 3 4 5 0 TMRx_postscaled Preliminary PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001865B-page 303 PIC16(L)F15325/45 Note PIC16(L)F15325/45 27.5.9 EDGE-TRIGGERED MONOSTABLE MODES The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON bit is set, and stop incrementing the timer when the timer matches the PRx period value. The following edges will start the timer: • Rising edge (MODE = 10001) • Falling edge (MODE = 10010) • Rising or Falling edge (MODE = 10011) When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the PRx value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP PWM.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 304  2016 Microchip Technology Inc. FIGURE 27-12: RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001) Rev. 10-000203A 4/7/2016 0b10001 MODE TMRx_clk PRx Instruction(1) 5 BSF BCF BSF BCF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled Preliminary PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001865B-page 305 PIC16(L)F15325/45 Note PIC16(L)F15325/45 27.5.10 LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODES The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level and start counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external signal is not in Reset or the ON bit is set then the other signal being set/made active will start the timer. Reset levels are selected as follows: • Low Reset level (MODE = 10110) • High Reset level (MODE = 10111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control the timer will stay in Reset until both the ON bit is set and the external signal is not at the Reset level. When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation the PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts the timer.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 306  2016 Microchip Technology Inc. FIGURE 27-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110) Rev. 10-000204A 4/7/2016 0b10110 MODE TMR2_clk PRx 5 Instruction(1) BSF BSF BCF BSF ON TMR2_ers TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0 Preliminary TMR2_postscaled PWM Duty Cycle ‘D3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001865B-page 307 PIC16(L)F15325/45 Note PIC16(L)F15325/45 27.6 Timer2 Operation During Sleep When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and T2PR registers will remain unchanged while processor is in Sleep mode. When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. Selecting the LFINTOSC, MFINTOSC, or HFINTOSC oscillator as the timer clock source will keep the selected oscillator running during Sleep.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 308 PIC16(L)F15325/45 27.7 Register Definitions: Timer2 Control REGISTER 27-1: T2CLKCON: TIMER2 CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CS: Timer2 Clock Select bits 1111 = Reserved 1110 = LC4_out 1101 = LC3_out 1100 = LC2_out 1011 = LC1_out 1010 = ZCD1_output 1001 = NCO1_out 1000 = CLKR 0111 = SOSC 0110 = MFINTOSC (31.25 kHz) 0101 = MFINTOSC (500 kHz) 0100 = LFINTOSC 0011 = HFINTOSC (32 MHz) 0010 = FOSC 0001 = FOSC/4 0000 = T2CKIPPS  2016 Microchip Technology Inc. Preliminary DS40001865B-page 309 PIC16(L)F15325/45 REGISTER 27-2: R/W/HC-0/0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 (1) ON R/W-0/0 R/W-0/0 R/W-0/0 CKPS R/W-0/0 R/W-0/0 R/W-0/0 OUTPS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 ON: Timerx On bit 1 = Timerx is on 0 = Timerx is off: all counters and state machines are reset bit 6-4 CKPS: Timer2-type Clock Prescale Select bits 111 = 1:128 Prescaler 110 = 1:64 Prescaler 101 = 1:32 Prescaler 100 = 1:16 Prescaler 011 = 1:8 Prescaler 010 = 1:4 Prescaler 001 = 1:2 Prescaler 000 = 1:1 Prescaler bit 3-0 OUTPS: Timerx Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 27.5 “Operation Examples”.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 310 PIC16(L)F15325/45 REGISTER 27-3: T2HLT: TIMERx HARDWARE LIMIT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 PSYNC(1, 2) CKPOL(3) CKSYNC(4, 5) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE(6, 7) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2) 1 = TMRx Prescaler Output is synchronized to Fosc/4 0 = TMRx Prescaler Output is not synchronized to Fosc/4 bit 6 CKPOL: Timerx Clock Polarity Selection bit(3) 1 = Falling edge of input clock clocks timer/prescaler 0 = Rising edge of input clock clocks timer/prescaler bit 5 CKSYNC: Timerx Clock Synchronization Enable bit(4, 5) 1 = ON register bit is synchronized to TMR2_clk input 0 = ON register bit is not synchronized to TMR2_clk input bit 4-0 MODE: Timerx Control Mode Selection bits(6, 7) See Table 27-1. Note 1: Setting this bit ensures that reading TMRx will return a valid value. 2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode. 3: CKPOL should not be changed while ON = 1. 4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled. 5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set. 6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TMRx). 7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 311 PIC16(L)F15325/45 REGISTER 27-4: T2RST: TIMER2 EXTERNAL RESET SIGNAL SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RSEL: Timer2 External Reset Signal Source Selection bits 1111 = Reserved 1101 = LC4_out 1100 = LC3_out 1011 = LC2_out 1010 = LC1_out 1001 = ZCD1_output 1000 = C2OUT_sync 0111 = C1OUT_sync 0110 = PWM6_out 0101 = PWM5_out 0100 = PWM4_out 0011 = PWM3_out 0010 = CCP2_out 0001 = CCP1_out 0000 = T2INPPS  2016 Microchip Technology Inc. Preliminary DS40001865B-page 312 PIC16(L)F15325/45 TABLE 27-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 5 Bit 4 CCP1CON EN — OUT FMT MODE CCP2CON EN — OUT FMT MODE INTCON GIE PEIE — — — OSFIE CSWIE — — — OSFIF CSWIF — — — PIE1 PIR1 PR2 Timer2 Module Period Register TMR2 Holding Register for the 8-bit TMR2 Register T2CON ON T2CLKCON — — — T2RST — — — T2HLT PSYNC CKPOL CKSYNC Legend: * Bit 3 CKPS Bit 2 Bit 1 Bit 0 Register on Page 321 321 — — INTEDG 124 — ― ADIE 126 — — ADIF 134 OUTPS 310 — CS 309 — RSEL 312 MODE 311 — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. Page provides register information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 313 PIC16(L)F15325/45 28.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. The Capture/Compare/PWM modules available are shown in Table 28-1. TABLE 28-1: AVAILABLE CCP MODULES Device PIC16(L)F15325/45 CCP1 CCP2 ● ● The Capture and Compare functions are identical for all CCP modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 314 PIC16(L)F15325/45 28.1 Figure 28-1 shows a simplified diagram of the capture operation. Capture Mode Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the capture source, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCPxMODE bits of the CCPxCON register: • • • • 28.1.1 In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Note: Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge If the CCPx pin is configured as an output, a write to the port can cause a capture condition. The capture source is selected by configuring the CCPxCTS bits of the CCPxCAP register. The following sources can be selected: • • • • • • • • When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIR6 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. FIGURE 28-1: CAPTURE SOURCES CCPxPPS input C1OUT_sync C2OUT_sync IOC_interrupt LC1_out LC2_out LC3_out LC4_out CAPTURE MODE OPERATION BLOCK DIAGRAM Rev. 10-000158F 9/1/2015 RxyPPS CCPx CTS TRIS Control CCPx LC4_out 111 LC3_out 110 LC2_out 101 LC1_out 100 IOC_interrupt 011 C2OUT_sync 010 C1OUT_sync 001 PPS 000 CCPRxH CCPRxL 16 Prescaler 1,4,16 set CCPxIF and Edge Detect 16 MODE TMR1H TMR1L CCPxPPS  2016 Microchip Technology Inc. Preliminary DS40001865B-page 315 PIC16(L)F15325/45 28.1.2 28.1.5 TIMER1 MODE RESOURCE CAPTURE DURING SLEEP Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. See Section 26.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. 28.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIE6 register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIR6 register following any change in Operating mode. Note: 28.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4). CCP PRESCALER Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 28.2 Compare Mode Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate an Auto-conversion Trigger Generate a Software Interrupt There are four prescaler settings specified by the CCPxMODE bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. The action on the pin is based on the value of the CCPxMODE control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set, and an ADC conversion can be triggered, if selected. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 28-1 demonstrates the code to perform this function. All Compare modes can generate an interrupt and trigger and ADC conversion. Figure 28-2 shows a simplified diagram of the compare operation. FIGURE 28-2: EXAMPLE 28-1: COMPARE MODE OPERATION BLOCK DIAGRAM CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW MOVWF ;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value CCPxMODE Mode Select BANKSEL CCPxCON Set CCPxIF Interrupt Flag (PIR6) 4 CCPRxH CCPRxL CCPx Pin Q S R Output Logic Match Comparator TMR1H TRIS Output Enable TMR1L Auto-conversion Trigger  2016 Microchip Technology Inc. Preliminary DS40001865B-page 316 PIC16(L)F15325/45 28.2.1 CCPX PIN CONFIGURATION 28.3 The software must configure the CCPx pin as an output by clearing the associated TRIS bit and defining the appropriate output pin through the RxyPPS registers. See Section 15.0 “Peripheral Pin Select (PPS) Module” for more details. The CCP output can also be used as an input for other peripherals. Note: 28.2.2 Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. TIMER1 MODE RESOURCE In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 26.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. Note: 28.2.3 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. AUTO-CONVERSION TRIGGER All CCPx modes set the CCP interrupt flag (CCPxIF). When this flag is set and a match occurs, an Auto-conversion Trigger can take place if the CCP module is selected as the conversion trigger source. Refer to Section 20.2.5 “Auto-Conversion Trigger” for more information. Note: 28.2.4 Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 28-3 shows a typical waveform of the PWM signal. 28.3.1 STANDARD PWM OPERATION The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • PR2 registers T2CON registers CCPRxL registers CCPxCON registers Figure 28-4 shows a simplified block diagram of PWM operation. Note: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. FIGURE 28-3: COMPARE DURING SLEEP Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the timer is running. The device will wake on interrupt (if enabled). CCP PWM OUTPUT SIGNAL Period Pulse Width TMR2 = PR2 TMR2 = CCPRxH:CCPRxL TMR2 = 0  2016 Microchip Technology Inc. Preliminary DS40001865B-page 317 PIC16(L)F15325/45 FIGURE 28-4: SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000 157C 9/5/201 4 Duty cycle registers CCPRxH CCPRxL CCPx_out set CCPIF 10-bit Latch(2) (Not accessible by user) Comparator R PPS Q RxyPPS S TMR2 Module R TMR2 To Peripherals CCPx TRIS Control (1) ERS logic Comparator CCPx_pset PR2 28.3.2 SETUP FOR PWM OPERATION 6. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR4 register is set. See Note below. • Enable the CCPx pin output driver by clearing the associated TRIS bit. The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register, and the CCPRxH register with the PWM duty cycle value and configure the CCPxFMT bit of the CCPxCON register to set the proper register alignment. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR4 register. See Note below. • Configure the CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the Timer2 ON bit of the T2CON register.  2016 Microchip Technology Inc. Note: 28.3.3 In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. CCP/PWM CLOCK SELECTION The PIC16(L)F15325/45 allows each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. Preliminary DS40001865B-page 318 PIC16(L)F15325/45 28.3.4 TIMER2 TIMER RESOURCE FIGURE 28-5: This device has a newer version of the Timer2 module that has many new modes, which allow for greater customization and control of the PWM signals than on older parts. Refer to Section 27.5 “Operation Examples” for examples of PWM signal generation using the different modes of Timer2. The CCP operation requires that the timer used as the PWM time base has the FOSC/4 clock source selected 28.3.5 PWM 10-BIT ALIGNMENT Rev. 10-000 160A 12/9/201 3 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 PWM PERIOD 10-bit Duty Cycle The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 28-1. EQUATION 28-1: 9 8 7 6 5 4 3 2 1 0 EQUATION 28-2: PWM PERIOD T OSC  (TMR2 Prescale Value) (TMR2 Prescale Value) TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is transferred from the CCPRxL/H register pair into a 10-bit buffer. Note: 28.3.6 PULSE WIDTH Pulse Width =  CCPRxH:CCPRxL register pair   PWM Period =   PR2  + 1   4  T OSC  Note 1: FMT = 0 EQUATION 28-3: DUTY CYCLE RATIO  CCPRxH:CCPRxL register pair  Duty Cycle Ratio = ---------------------------------------------------------------------------------4  PR2 + 1  CCPRxH:CCPRxL register pair are used to double buffer the PWM duty cycle. This double buffering provides for glitchless PWM operation. The Timer postscaler (see Section 27.4 “Timer2 Interrupt”) is not used in the determination of the PWM frequency. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. PWM DUTY CYCLE When the 10-bit time base matches the CCPRxH:CCPRxL register pair, then the CCPx pin is cleared (see Figure 28-4). The PWM duty cycle is specified by writing a 10-bit value to the CCPRxH:CCPRxL register pair. The alignment of the 10-bit value is determined by the CCPRxFMT bit of the CCPxCON register (see Figure 28-5). The CCPRxH:CCPRxL register pair can be written to at any time; however the duty cycle value is not latched into the 10-bit buffer until after a match between PR2 and TMR2. Equation 28-2 is used to calculate the PWM pulse width. Equation 28-3 is used to calculate the PWM duty cycle ratio. 28.3.7 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 28-4. EQUATION 28-4: PWM RESOLUTION log  4  PR2 + 1   Resolution = ------------------------------------------ bits log  2  Note:  2016 Microchip Technology Inc. Preliminary If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. DS40001865B-page 319 PIC16(L)F15325/45 TABLE 28-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz Timer Prescale PR2 Value 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale PR2 Value Maximum Resolution (bits) 28.3.8 19.53 kHz 0xFF Maximum Resolution (bits) TABLE 28-3: 4.88 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 28.3.9 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 9.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 28.3.10 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 320 PIC16(L)F15325/45 28.4 Register Definitions: CCP Control Long bit name prefixes for the CCP peripherals are shown in Section 1.1 “Register and Bit Naming Conventions”. TABLE 28-4: LONG BIT NAMES PREFIXES FOR CCP PERIPHERALS Peripheral Bit Name Prefix CCP1 CCP1 CCP2 CCP2 REGISTER 28-1: CCPxCON: CCPx CONTROL REGISTER R/W-0/0 U-0 R-x R/W-0/0 EN — OUT FMT R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EN: CCPx Module Enable bit 1 = CCPx is enabled 0 = CCPx is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 OUT: CCPx Output Data bit (read-only) bit 4 FMT: CCPW (Pulse Width) Alignment bit MODE = Capture mode Unused MODE = Compare mode Unused MODE = PWM mode 1 = Left-aligned format 0 = Right-aligned format  2016 Microchip Technology Inc. Preliminary DS40001865B-page 321 PIC16(L)F15325/45 REGISTER 28-1: bit 3-0 Note 1: CCPxCON: CCPx CONTROL REGISTER (CONTINUED) MODE: CCPx Mode Select bits(1) 1111 - 1100 = PWM mode (Timer2 as the timer source) 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = 1010 = 1001 = 1000 = Compare mode: output will pulse 0-1-0; Clears TMR1 Compare mode: output will pulse 0-1-0 Compare mode: clear output on compare match Compare mode: set output on compare match 0111 = 0110 = 0101 = 0100 = Capture mode: every 16th rising edge of CCPx input Capture mode: every 4th rising edge of CCPx input Capture mode: every rising edge of CCPx input Capture mode: every falling edge of CCPx input 0011 = 0010 = 0001 = 0000 = Capture mode: every edge of CCPx input Compare mode: toggle output on match Compare mode: toggle output on match; clear TMR1 Capture/Compare/PWM off (resets CCPx module) All modes will set the CCPxIF bit, and will trigger an ADC conversion if CCPx is selected as the ADC trigger source.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 322 PIC16(L)F15325/45 REGISTER 28-2: CCPxCAP: CAPTURE INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/x R/W-0/x R/W-0/x CTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CTS: Capture Trigger Input Selection bits CTS CCP1.capture 111 LC4_out 110 LC3_out 101 LC2_out 100 LC1_out 011 IOC_interrupt 010 C2OUT 001 C1OUT CCP1PPS 000 REGISTER 28-3: R/W-x/x CCP2.capture CCP2PPS CCPRxL REGISTER: CCPx REGISTER LOW BYTE R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x CCPRx bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 CCPxMODE = Capture mode CCPRxL: Capture value of TMR1L CCPxMODE = Compare mode CCPRxL: LS Byte compared to TMR1L CCPxMODE = PWM modes when CCPxFMT = 0: CCPRxL: Pulse-width Least Significant eight bits CCPxMODE = PWM modes when CCPxFMT = 1: CCPRxL: Pulse-width Least Significant two bits CCPRxL: Not used.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 323 PIC16(L)F15325/45 REGISTER 28-4: R/W-x/x CCPRxH REGISTER: CCPx REGISTER HIGH BYTE R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x CCPRx bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 CCPxMODE = Capture mode CCPRxH: Captured value of TMR1H CCPxMODE = Compare mode CCPRxH: MS Byte compared to TMR1H CCPxMODE = PWM modes when CCPxFMT = 0: CCPRxH: Not used CCPRxH: Pulse-width Most Significant two bits CCPxMODE = PWM modes when CCPxFMT = 1: CCPRxH: Pulse-width Most Significant eight bits  2016 Microchip Technology Inc. Preliminary DS40001865B-page 324 PIC16(L)F15325/45 TABLE 28-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH CCPx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 GIE PEIE — — — — — — — — PIE4 — — — — — CCP1CON EN — OUT FMT CCP1CAP — — — — INTCON PIR4 CCPR1L Capture/Compare/PWM Register 1 (LSB) CCPR1H Capture/Compare/PWM Register 1 (MSB) — OUT FMT CCP2CAP — — — — CCPR2H Capture/Compare/PWM Register 1 (MSB) — — INTEDG 124 — TMR2IF TMR1IF 137 — TMR2IE TMR1IE 129 MODE — CTS 321 323 324 EN Capture/Compare/PWM Register 1 (LSB) Bit 0 323 CCP2CON CCPR2L Register on Page Bit 1 MODE — CTS 321 323 323 323 CCP1PPS — — CCP1PPS 199 CCP2PPS — — CCP2PPS 199 RxyPPS — — — ADACT — — — CLCxSELy — — — — — — CWG1ISM Legend: RxyPPS — ADACT LCxDyS — IS 200 235 367 356 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCP module.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 325 PIC16(L)F15325/45 29.0 PULSE-WIDTH MODULATION (PWM) The PWMx modules generate Pulse-Width Modulated (PWM) signals of varying frequency and duty cycle. In addition to the CCP modules, the PIC16(L)F15325/45 devices contain four 10-bit PWM modules (PWM3, PWM4, PWM5 and PWM6). The PWM modules reproduce the PWM capability of the CCP modules. FIGURE 29-1: Q1 PWM OUTPUT Q2 Q3 Q4 Rev. 10-000023C 8/26/2015 FOSC PWM Pulse Width TMRx = 0 TMRx = PWMxDC Note: The PWM3/4/5/6 modules are four instances of the same PWM module design. Throughout this section, the lower case ‘x’ in register and bit names is a generic reference to the PWM module number (which should be substituted with 3, or 4, or, 5 or 6 during code development). For example, the control register is generically described in this chapter as PWMxCON, but the actual device registers are PWM3CON, PWM4CON, PWM5CON and PWM6CON. Similarly, the PWMxEN bit represents the PWM3EN, PWM4EN, PWM5EN and PWM6EN bits. TMRx = PRx (1) (1) (1) Note 1: Timer dependent on PWMTMRS register settings. Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the ‘on’ state (pulse width), and the low portion of the signal is considered the ‘off’ state. The term duty cycle describes the proportion of the ‘on’ time to the ‘off’ time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and, in turn, the power that is applied to the load. Figure 29-1 shows a typical waveform of the PWM signal.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 326 PIC16(L)F15325/45 29.1 Standard PWM Mode The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the PWMx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • • TMR2 register PR2 register PWMxCON registers PWMxDCH registers PWMxDCL registers Figure 29-2 shows a simplified block diagram of PWM operation. If PWMPOL = 0, the default state of the output is ‘0‘. If PWMPOL = 1, the default state is ‘1’. If PWMEN = 0, the output will be the default state. Note: The corresponding TRIS bit must be cleared to enable the PWM output on the PWMx pin FIGURE 29-2: SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000022B 9/24/2014 PWMxDCL Duty cycle registers PWMxDCH PWMx_out 10-bit Latch (Not visible to user) R Comparator Q 0 1 S To Peripherals PPS PWMx Q TMR2 Module TMR2 Comparator R PWMxPOL (1) RxyPPS TRIS Control T2_match PR2 Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 327 PIC16(L)F15325/45 29.1.1 PWM CLOCK SELECTION 29.1.4 The PIC16(L)F15325/45 allows each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. 29.1.2 USING THE TMR2 WITH THE PWM MODULE This device has a newer version of the TMR2 module that has many new modes, which allow for greater customization and control of the PWM signals than on older parts. Refer to Section 27.5 “Operation Examples” for examples of PWM signal generation using the different modes of Timer2. Note: 29.1.3 PWM operation requires that the timer used as the PWM time base has the FOSC/4 clock source selected. PWM PERIOD The PWM duty cycle is specified by writing a 10-bit value to the PWMxDC register. The PWMxDCH contains the eight MSbs and the PWMxDCL bits contain the two LSbs. The PWMDC register is double-buffered and can be updated at any time. This double buffering is essential for glitch-free PWM operation. New values take effect when TMR2 = PR2. Note that PWMDC is left-justified. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. Equation 29-2 is used to calculate the PWM pulse width. Equation 29-3 is used to calculate the PWM duty cycle ratio. EQUATION 29-2: Referring to Figure 29-1, the PWM output has a period and a pulse width. The frequency of the PWM is the inverse of the period (1/period). The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: EQUATION 29-1: PWM DUTY CYCLE Pulse Widthൌሺܹܲ‫ܥܦݔܯ‬ሻ  ή ܱܶܵ‫ ܥ‬ή ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ EQUATION 29-3: 29.1.5 Note 1: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The PWMx pin is set (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM pulse width is latched from PWMxDC. ሺܹܲ‫ܥܦݔܯ‬ሻ  Ͷሺܴܲʹ ൅ ͳሻ PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 29-4. EQUATION 29-4: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.  2016 Microchip Technology Inc. DUTY CYCLE RATIO ‫ ݋݅ݐܴ݈ܽ݁ܿݕܥݕݐݑܦ‬ൌ  PWM PERIOD ܹܲ‫ ݀݋݅ݎ݁ܲܯ‬ൌ  ሾሺܴܲʹሻ  ൅ ͳሿ  ή Ͷ ή ܱܶܵ‫ܥ‬ ή  ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ Note: PULSE WIDTH Preliminary PWM RESOLUTION log  4  PR2 + 1   Resolution = ------------------------------------------ bits log  2  DS40001865B-page 328 PIC16(L)F15325/45 29.1.6 OPERATION IN SLEEP MODE 29.1.8 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 29.1.7 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWMx registers to their Reset states. CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 9.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. TABLE 29-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency Timer Prescale PR2 Value Maximum Resolution (bits) TABLE 29-2: 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency Timer Prescale PR2 Value Maximum Resolution (bits) 29.1.9 1.22 kHz 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 SETUP FOR PWM OPERATION The following steps should be taken when configuring the module for using the PWMx outputs: 1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). 2. Configure the PWM output polarity by configuring the PWMxPOL bit of the PWMxCON register. 3. Load the PR2 register with the PWM period value, as determined by Equation 29-1. 4. Load the PWMxDCH register and bits of the PWMxDCL register with the PWM duty cycle value, as determined by Equation 29-2. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR4 register. • Select the Timer2 prescale value by configuring the CKPS bits of the T2CON register. • Enable Timer2 by setting the Timer2 ON bit of the T2CON register.  2016 Microchip Technology Inc. 6. Wait until the TMR2IF is set. 7. When the TMR2IF flag bit is set: • Clear the associated TRIS bit(s) to enable the output driver. • Route the signal to the desired pin by configuring the RxyPPS register. • Enable the PWMx module by setting the PWMxEN bit of the PWMxCON register. In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then the PWM module can be enabled during Step 2 by setting the PWMxEN bit of the PWMxCON register. Preliminary DS40001865B-page 329 PIC16(L)F15325/45 29.2 Register Definitions: PWM Control REGISTER 29-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 U-0 R-0 R/W-0/0 U-0 U-0 U-0 U-0 PWMxEN — PWMxOUT PWMxPOL — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PWMxEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 PWMxOUT: PWM Module Output Level when Bit is Read bit 4 PWMxPOL: PWMx Output Polarity Select bit 1 = PWM output is active-low 0 = PWM output is active-high bit 3-0 Unimplemented: Read as ‘0’  2016 Microchip Technology Inc. Preliminary DS40001865B-page 330 PIC16(L)F15325/45 REGISTER 29-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDC: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register. REGISTER 29-3: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u PWMxDC U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PWMxDC: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register. bit 5-0 Unimplemented: Read as ‘0’  2016 Microchip Technology Inc. Preliminary DS40001865B-page 331 PIC16(L)F15325/45 TABLE 29-3: Name T2CON SUMMARY OF REGISTERS ASSOCIATED WITH PWMx Bit 7 Bit 6 Bit 5 ON Bit 4 T2PR TMR2 Period Register ― ― — — CWG1ISM — — — — TRISA — Register on Page 310 290* RxyPPS — 200 IS 356 LCxDyS — (1) Bit 0 290* RxyPPS CLCxSELy Bit 1 OUTPS Holding Register for the 8-bit TMR2 Register TRISC7 Bit 2 CKPS T2TMR TRISC Bit 3 (1) TRISC6 367 TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 178 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 189 Legend: - = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWMx module. * Page with Register information. Note 1: Present on PIC16(L)F15345 only.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 332 PIC16(L)F15325/45 30.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms. It is backwards compatible with previous ECCP functions. The CWG has the following features: • Six operating modes: - Synchronous Steering mode - Asynchronous Steering mode - Full-Bridge mode, Forward - Full-Bridge mode, Reverse - Half-Bridge mode - Push-Pull mode • Output polarity control • Output steering - Synchronized to rising event - Immediate effect • Independent 6-bit rising and falling event deadband timers - Clocked dead band - Independent rising and falling dead-band enables • Auto-shutdown control with: - Selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control 30.1 Fundamental Operation The CWG module can operate in six different modes, as specified by MODE of the CWG1CON0 register: • Half-Bridge mode (Figure 30-9) • Push-Pull mode (Figure 30-2) - Full-Bridge mode, Forward (Figure 30-3) - Full-Bridge mode, Reverse (Figure 30-3) • Steering mode (Figure 30-10) • Synchronous Steering mode (Figure 30-11) It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. Thus, all output modes support auto-shutdown, which is covered in 30.10 “Auto-Shutdown”. 30.1.1 HALF-BRIDGE MODE In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 30-9. A non-overlap (dead-band) time is inserted between the two outputs as described in Section 30.5 “Dead-Band Control”. The unused outputs CWG1C and CWG1D drive similar signals, with polarity independently controlled by the POLC and POLD bits of the CWG1CON1 register, respectively. The CWG modules available are shown in Table 30-1. TABLE 30-1: AVAILABLE CWG MODULES Device PIC16(L)F15325/45  2016 Microchip Technology Inc. CWG1 ● Preliminary DS40001865B-page 333  2016 Microchip Technology Inc. FIGURE 30-1: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE) Rev. 10-000166B 8/29/2014 CWG_data Rising Deadband Block See CWGxISM Register CWG_dataA clock signal_out CWG_dataC signal_in Preliminary D Q CWGxISM E R Q Falling Deadband Block CWG_dataB clock signal_out signal_in SHUTDOWN HFINTOSC 1 FOSC 0 CWGxCLK DS40001865B-page 334 PIC16(L)F15325/45 EN CWG_dataD PIC16(L)F15325/45 30.1.2 PUSH-PULL MODE In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 30-2. This alternation creates the push-pull effect required for driving some transformer-based power supply designs. The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWG1A. The unused outputs CWG1C and CWG1D drive copies of CWG1A and CWG1B, respectively, but with polarity controlled by the POLC and POLD bits of the CWG1CON1 register, respectively. 30.1.3 FULL-BRIDGE MODES In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the input data signal. In Forward Full-Bridge mode, CWG1A is driven to its active state, CWG1B and CWG1C are driven to their inactive state, and CWG1D is modulated by the input signal. In Reverse Full-Bridge mode, CWG1C is driven to its active state, CWG1A and CWG1D are driven to their inactive states, and CWG1B is modulated by the input signal. In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice-versa. This dead-band control is described in Section 30.5 “Dead-Band Control”, with additional details in Section 30.6 “Rising Edge and Reverse Dead Band” and Section 30.7 “Falling Edge and Forward Dead Band”. The mode selection may be toggled between forward and reverse toggling the MODE bit of the CWG1CON0 while keeping MODE static, without disabling the CWG module.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 335  2016 Microchip Technology Inc. FIGURE 30-2: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE) Rev. 10-000167B 8/29/2014 CWG_data See CWGxISM Register D Q CWG_dataA Q CWG_dataC R CWG_dataB Preliminary D Q E Q CWG_dataD CWGxISM R EN DS40001865B-page 336 PIC16(L)F15325/45 SHUTDOWN  2016 Microchip Technology Inc. FIGURE 30-3: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES) Rev. 10-000165B 8/29/2014 Reverse Deadband Block MODE0 clock signal_out See CWGxISM Register signal_in CWG_dataA D D Q Q CWG_dataB Q CWG_dataC CWGxISM Preliminary E R CWG_dataD Q clock signal_out signal_in Forward Deadband Block EN CWG_data SHUTDOWN FOSC CWGxCLK 1 0 DS40001865B-page 337 PIC16(L)F15325/45 HFINTOSC PIC16(L)F15325/45 30.1.4 STEERING MODES In Steering modes, the data input can be steered to any or all of the four CWG output pins. In Synchronous Steering mode, changes to steering selection registers take effect on the next rising input. In Non-Synchronous mode, steering takes effect on the next instruction cycle. Additional details are provided in Section 30.9 “CWG Steering Mode”. FIGURE 30-4: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES) Rev. 10-000164B 8/26/2015 See CWGxISM Register CWG_dataA CWG_data CWG_dataB CWG_dataC CWG_dataD D Q CWGxISM E R Q EN SHUTDOWN 30.2 Clock Source The CWG module allows the following clock sources to be selected: • Fosc (system clock) • HFINTOSC (16 MHz only) The clock sources are selected using the CS bit of the CWG1CLKCON register.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 338 PIC16(L)F15325/45 30.3 Selectable Input Sources 30.4 The CWG generates the output waveforms from the input sources in Table 30-2. TABLE 30-2: SELECTABLE INPUT SOURCES Source Peripheral Signal Name CWG input PPS pin CWG1IN PPS CCP1 CCP1_out CCP2 CCP2_out PWM3 PWM3_out PWM4 PWM4_out PWM5 PWM5_out PWM6 PWM6_out NCO NCO1_out Comparator C1 C1OUT_sync Comparator C2 C2OUT_sync CLC1 LC1_out CLC2 LC2_out CLC3 LC3_out CLC4 LC4_out 30.4.1 Output Control POLARITY CONTROL The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the POLx bits of the CWG1CON1. Auto-shutdown and steering options are unaffected by polarity. The input sources are selected using the CWG1ISM register.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 339 PIC16(L)F15325/45 FIGURE 30-5: CWG OUTPUT BLOCK DIAGRAM Rev. 10-000171B 9/24/2014 LSAC CWG_dataA 1 POLA OVRA ‘1’ 11 ‘0’ 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 PPS CWGxA STRA(1) LSBD CWG_dataB 1 POLB OVRB ‘1’ 11 ‘0’ 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 CWGxB PPS STRB(1) LSAC CWG_dataC 1 POLC OVRC ‘1’ 11 ‘0’ 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 CWGxC PPS STRC(1) LSBD CWG_dataD 1 POLD OVRD ‘1’ 11 ‘0’ 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 PPS CWGxD STRD(1) CWG_shutdown Note 1:  2016 Microchip Technology Inc. STRx is held to 1 in all modes other than Output Steering Mode. Preliminary DS40001865B-page 340 PIC16(L)F15325/45 30.5 Dead-Band Control 30.6 The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM switches. Dead-band operation is employed for HalfBridge and Full-Bridge modes. The CWG contains two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge mode or for reverse dead-band Full-Bridge mode. The other is used for the falling edge of the input source control in Half-Bridge mode or for forward dead band in FullBridge mode. Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. See CWG1DBR and CWG1DBF registers, respectively. 30.5.1 DEAD-BAND FUNCTIONALITY IN HALF-BRIDGE MODE In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the rising edge of the inverted output. This can be seen in Figure 30-9. 30.5.2 DEAD-BAND FUNCTIONALITY IN FULL-BRIDGE MODE In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE bit of the CWG1CON0 register can be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWG1A and CWG1C signals will change upon the first rising input edge following a direction change, but the modulated signals (CWG1B or CWG1D, depending on the direction of the change) will experience a delay dictated by the deadband counters. This is demonstrated in Figure 30-3.  2016 Microchip Technology Inc. Rising Edge and Reverse Dead Band CWG1DBR controls the rising edge dead-band time at the leading edge of CWG1A (Half-Bridge mode) or the leading edge of CWG1B (Full-Bridge mode). The CWG1DBR value is double-buffered. When EN = 0, the CWG1DBR register is loaded immediately when CWG1DBR is written. When EN = 1, then software must set the LD bit of the CWG1CON0 register, and the buffer will be loaded at the next falling edge of the CWG input signal. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. 30.7 Falling Edge and Forward Dead Band CWG1DBF controls the dead-band time at the leading edge of CWG1B (Half-Bridge mode) or the leading edge of CWG1D (Full-Bridge mode). The CWG1DBF value is double-buffered. When EN = 0, the CWG1DBF register is loaded immediately when CWG1DBF is written. When EN = 1 then software must set the LD bit of the CWG1CON0 register, and the buffer will be loaded at the next falling edge of the CWG input signal. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. Refer to Figure 30-6 and Figure 30-7 for examples. Preliminary DS40001865B-page 341  2016 Microchip Technology Inc. FIGURE 30-6: DEAD-BAND OPERATION CWG1DBR = 0X01, CWG1DBF = 0X02 cwg_clock Input Source CWG1A CWG1B Preliminary FIGURE 30-7: DEAD-BAND OPERATION, CWG1DBR = 0X03, CWG1DBF = 0X04, SOURCE SHORTER THAN DEAD BAND Input Source CWG1A CWG1B source shorter than dead band DS40001865B-page 342 PIC16(L)F15325/45 cwg_clock PIC16(L)F15325/45 30.8 EQUATION 30-1: Dead-Band Uncertainty When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates uncertainty in the dead-band time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 30-1 for more details. DEAD-BAND UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock Example: FCWG_CLOCK = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock 1 = -----------------16MHz = 62.5ns FIGURE 30-8: EXAMPLE OF PWM DIRECTION CHANGE MODE0 CWG1A CWG1B CWG1C CWG1D No delay CWG1DBR No delay CWG1DBF CWG1_data Note 1: 2: 3: WGPOL{ABCD} = 0 The direction bit MODE (Register 30-1) can be written any time during the PWM cycle, and takes effect at the next rising CWG1_data. When changing directions, CWG1A and CWG1C switch at rising CWG1_data; modulated CWG1B and CWG1D are held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 343 PIC16(L)F15325/45 FIGURE 30-9: CWG HALF-BRIDGE MODE OPERATION CWG1_clock CWG1A CWG1C Falling Event Dead Band Rising Event Dead Band Rising Event D Falling Event Dead Band CWG1B CWG1D CWG1_data Note: CWG1_rising_src = CCP1_out, CWG1_falling_src = ~CCP1_out  2016 Microchip Technology Inc. Preliminary DS40001865B-page 344 PIC16(L)F15325/45 30.9 30.9.1 CWG Steering Mode In Steering mode (MODE = 00x), the CWG allows any combination of the CWG1x pins to be the modulated signal. The same signal can be simultaneously available on multiple pins, or a fixed-value output can be presented. When the respective STRx bit of CWG1OCON0 is ‘0’, the corresponding pin is held at the level defined. When the respective STRx bit of CWG1OCON0 is ‘1’, the pin is driven by the input data signal. The user can assign the input data signal to one, two, three, or all four output pins. The POLx bits of the CWG1CON1 register control the signal polarity only when STRx = 1. The CWG auto-shutdown operation also applies in Steering modes as described in Section 30.10 “AutoShutdown”. An auto-shutdown event will only affect pins that have STRx = 1. FIGURE 30-10: STEERING SYNCHRONIZATION Changing the MODE bits allows for two modes of steering, synchronous and asynchronous. When MODE = 000, the steering event is asynchronous and will happen at the end of the instruction that writes to STRx (that is, immediately). In this case, the output signal at the output pin may be an incomplete waveform. This can be useful for immediately removing a signal from the pin. When MODE = 001, the steering update is synchronous and occurs at the beginning of the next rising edge of the input data signal. In this case, steering the output on/off will always produce a complete waveform. Figure 30-10 and Figure 30-11 illustrate the timing of asynchronous and synchronous steering, respectively. EXAMPLE OF ASYNCHRONOUS STEERING EVENT (MODE = 000) Rising Event CWG1_data (Rising and Falling Source) STR CWG1 OVR Data OVR follows CWG1_data FIGURE 30-11: EXAMPLE OF STEERING EVENT (MODE = 001) CWG1_data (Rising and Falling Source) STR CWG1 OVR Data OVR Data follows CWG1_data  2016 Microchip Technology Inc. Preliminary DS40001865B-page 345 PIC16(L)F15325/45 30.10 Auto-Shutdown 30.11 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. The auto-shutdown circuit is illustrated in Figure 30-12. The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. 30.10.1 • CWG module is enabled • Input source is active • HFINTOSC is selected as the clock source, regardless of the system clock source selected. SHUTDOWN The shutdown state can be entered by either of the following two methods: • Software generated • External Input 30.10.1.1 Software Generated Shutdown Setting the SHUTDOWN bit of the CWG1AS0 register will force the CWG into the shutdown state. When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set. The HFINTOSC remains active during Sleep when all the following conditions are met: In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, then the CPU will go idle during Sleep, but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current. When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. 30.10.2 EXTERNAL INPUT SOURCE External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. Several input sources can be selected to cause a shutdown condition. All input sources are active-low. The sources are: • • • • Comparator C1OUT_sync Comparator C2OUT_sync Timer2 – TMR2_postscaled CWG1IN input pin Shutdown inputs are selected using the CWG1AS1 register (Register 30-6). Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling autoshutdown, as long as the shutdown input level persists.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 346  2016 Microchip Technology Inc. FIGURE 30-12: CWG SHUTDOWN BLOCK DIAGRAM Write ‘1’ to SHUTDOWN bit Rev. 10-000172B 1/21/2015 PPS INAS CWGINPPS C1OUT_sync C1AS C2OUT_sync C2AS TMR2_postscaled TMR2AS TMR4_postscaled TMR4AS TMR6_postscaled TMR6AS S Q SHUTDOWN S D FREEZE REN Write ‘0’ to SHUTDOWN bit Q CWG_shutdown R CWG_data CK Preliminary PIC16(L)F15325/45 DS40001865B-page 347 PIC16(L)F15325/45 30.12 Configuring the CWG 30.12.2 The following steps illustrate how to properly configure the CWG. After an auto-shutdown event has occurred, there are two ways to resume operation: 1. • Software controlled • Auto-restart 2. 3. 4. 5. Ensure that the TRIS control bits corresponding to the desired CWG pins for your application are set so that the pins are configured as inputs. Clear the EN bit, if not already cleared. Set desired mode of operation with the MODE bits. Set desired dead-band times, if applicable to mode, with the CWG1DBR and CWG1DBF registers. Setup the following controls in the CWG1AS0 and CWG1AS1 registers. a. Select the desired shutdown source. b. Select both output overrides to the desired levels (this is necessary even if not using autoshutdown because start-up will be from a shutdown state). c. Set which pins will be affected by auto-shutdown with the CWG1AS1 register. d. Set the SHUTDOWN bit and clear the REN bit. 6. 7. Select the desired input source using the CWG1ISM register. Configure the following controls. a. Select desired clock source CWG1CLKCON register. using the AUTO-SHUTDOWN RESTART The restart method is selected with the REN bit of the CWG1CON2 register. Waveforms of software controlled and automatic restarts are shown in Figure 30-13 and Figure 30-14. 30.12.2.1 Software Controlled Restart When the REN bit of the CWG1AS0 register is cleared, the CWG must be restarted after an auto-shutdown event by software. Clearing the shutdown state requires all selected shutdown inputs to be low, otherwise the SHUTDOWN bit will remain set. The overrides will remain in effect until the first rising edge event after the SHUTDOWN bit is cleared. The CWG will then resume operation. 30.12.2.2 Auto-Restart When the REN bit of the CWG1CON2 register is set, the CWG will restart from the auto-shutdown state automatically. The SHUTDOWN bit will clear automatically when all shutdown sources go low. The overrides will remain in effect until the first rising edge event after the SHUTDOWN bit is cleared. The CWG will then resume operation. b. Select the desired output polarities using the CWG1CON1 register. c. Set the output enables for the desired outputs. 8. 9. Set the EN bit. Clear TRIS control bits corresponding to the desired output pins to configure these pins as outputs. 10. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit to start the CWG. 30.12.1 PIN OVERRIDE LEVELS The levels driven to the output pins, while the shutdown input is true, are controlled by the LSBD and LSAC bits of the CWG1AS0 register. LSBD controls the CWG1B and D override levels and LSAC controls the CWG1A and C override levels. The control bit logic level corresponds to the output logic drive level while in the shutdown state. The polarity control does not affect the override level.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 348  2016 Microchip Technology Inc. FIGURE 30-13: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01) Shutdown Event Ceases REN Cleared by Software CWG Input Source Shutdown Source SHUTDOWN CWG1A CWG1C Tri-State (No Pulse) CWG1B CWG1D Tri-State (No Pulse) No Shutdown Preliminary Output Resumes Shutdown FIGURE 30-14: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01) Shutdown Event Ceases REN auto-cleared by hardware Shutdown Source SHUTDOWN DS40001865B-page 349 CWG1A CWG1C Tri-State (No Pulse) CWG1B CWG1D Tri-State (No Pulse) No Shutdown Shutdown Output Resumes PIC16(L)F15325/45 CWG Input Source PIC16(L)F15325/45 30.13 Register Definitions: CWG Control Long bit name prefixes for the CWG peripherals are shown in Section 1.1 “Register and Bit Naming Conventions”. REGISTER 30-1: CWG1CON0: CWG1 CONTROL REGISTER 0 R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 EN LD(1) — — — R/W-0/0 R/W-0/0 R/W-0/0 MODE bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 EN: CWG1 Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 LD: CWG1 Load Buffer bits(1) 1 = Buffers to be loaded on the next rising/falling event 0 = Buffers not loaded bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 MODE: CWG1 Mode bits 111 = Reserved 110 = Reserved 101 = CWG outputs operate in Push-Pull mode 100 = CWG outputs operate in Half-Bridge mode 011 = CWG outputs operate in Reverse Full-Bridge mode 010 = CWG outputs operate in Forward Full-Bridge mode 001 = CWG outputs operate in Synchronous Steering mode 000 = CWG outputs operate in Steering mode Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 350 PIC16(L)F15325/45 REGISTER 30-2: CWG1CON1: CWG1 CONTROL REGISTER 1 U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IN — POLD POLC POLB POLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5 IN: CWG Input Value bit bit 4 Unimplemented: Read as ‘0’ bit 3 POLD: CWG1D Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 2 POLC: CWG1C Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 1 POLB: CWG1B Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 0 POLA: CWG1A Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity  2016 Microchip Technology Inc. Preliminary DS40001865B-page 351 PIC16(L)F15325/45 REGISTER 30-3: CWG1DBR: CWG1 RISING DEAD-BAND COUNTER REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 DBR: Rising Event Dead-Band Value for Counter bits REGISTER 30-4: CWG1DBF: CWG1 FALLING DEAD-BAND COUNTER REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 DBF: Falling Event Dead-Band Value for Counter bits  2016 Microchip Technology Inc. Preliminary DS40001865B-page 352 PIC16(L)F15325/45 REGISTER 30-5: CWG1AS0: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 0 R/W/HS-0/0 R/W-0/0 (1, 2) REN SHUTDOWN R/W-0/0 R/W-1/1 R/W-0/0 LSBD R/W-1/1 LSAC U-0 U-0 — — bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1, 2) 1 = An Auto-Shutdown state is in effect 0 = No Auto-shutdown event has occurred bit 6 REN: Auto-Restart Enable bit 1 = Auto-restart enabled 0 = Auto-restart disabled bit 5-4 LSBD: CWG1B and CWG1D Auto-Shutdown State Control bits 11 =A logic ‘1’ is placed on CWG1B/D when an auto-shutdown event is present 10 =A logic ‘0’ is placed on CWG1B/D when an auto-shutdown event is present 01 =Pin is tri-stated on CWG1B/D when an auto-shutdown event is present 00 =The inactive state of the pin, including polarity, is placed on CWG1B/D after the required deadband interval bit 3-2 LSAC: CWG1A and CWG1C Auto-Shutdown State Control bits 11 =A logic ‘1’ is placed on CWG1A/C when an auto-shutdown event is present 10 =A logic ‘0’ is placed on CWG1A/C when an auto-shutdown event is present 01 =Pin is tri-stated on CWG1A/C when an auto-shutdown event is present 00 =The inactive state of the pin, including polarity, is placed on CWG1A/C after the required deadband interval bit 1-0 Unimplemented: Read as ‘0’ Note 1: This bit may be written while EN = 0 (CWG1CON0 register) to place the outputs into the shutdown configuration. 2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is cleared.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 353 PIC16(L)F15325/45 REGISTER 30-6: CWG1AS1: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 1 U-1 U-1 U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — AS4E AS3E AS2E AS1E AS0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 AS4E: CLC2 Output bit 1 = LC2_out shut-down is enabled 0 = LC2_out shut-down is disabled bit 3 AS3E: Comparator C2 Output bit 1 = C2 output shut-down is enabled 0 = C2 output shut-down is disabled bit 2 AS2E: Comparator C1 Output bit 1 = C1 output shut-down is enabled 0 = C1 output shut-down is disabled bit 2 AS1E: TMR2 Postscale Output bit 1 = TMR2 Postscale shut-down is enabled 0 = TMR2 Postscale shut-down is disabled bit 0 AS0E: CWG1 Input Pin bit 1 = Input pin selected by CWG1PPS shut-down is enabled 0 = Input pin selected by CWG1PPS shut-down is disabled  2016 Microchip Technology Inc. Preliminary DS40001865B-page 354 PIC16(L)F15325/45 CWG1STR: CWG1 STEERING CONTROL REGISTER(1) REGISTER 30-7: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 OVRD: Steering Data D bit bit 6 OVRC: Steering Data C bit bit 5 OVRB: Steering Data B bit bit 4 OVRA: Steering Data A bit bit 3 STRD: Steering Enable D bit(2) 1 = CWG1D output has the CWG1_data waveform with polarity control from POLD bit 0 = CWG1D output is assigned the value of OVRD bit bit 2 STRC: Steering Enable C bit(2) 1 = CWG1C output has the CWG1_data waveform with polarity control from POLC bit 0 = CWG1C output is assigned the value of OVRC bit bit 1 STRB: Steering Enable B bit(2) 1 = CWG1B output has the CWG1_data waveform with polarity control from POLB bit 0 = CWG1B output is assigned the value of OVRB bit bit 0 STRA: Steering Enable A bit(2) 1 = CWG1A output has the CWG1_data waveform with polarity control from POLA bit 0 = CWG1A output is assigned the value of OVRA bit Note 1: The bits in this register apply only when MODE = 00x. 2: This bit is effectively double-buffered when MODE = 001.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 355 PIC16(L)F15325/45 REGISTER 30-8: CWG1CLK: CWG1 CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as ‘0’ bit 0 CS: CWG1 Clock Selection bit 1 = HFINTOSC 16 MHz is selected 0 = FOSC is selected REGISTER 30-9: CWG1ISM: CWG1 INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 IS: CWG1 Input Selection bits 1111 = Reserved. No channel connected. 1110 = Reserved. No channel connected. 1101 = LC4_out 1100 = LC3_out 1011 = LC2_out 1010 = LC1_out 1001 = Comparator C2 out 1000 = Comparator C1 out 0111 = NCO1 output 0110 = PWM6_out 0101 = PWM5_out 0100 = PWM4_out 0011 = PWM3_out 0010 = CCP2_out 0001 = CCP1_out 0000 = CWG11CLK  2016 Microchip Technology Inc. Preliminary DS40001865B-page 356 PIC16(L)F15325/45 TABLE 30-3: SUMMARY OF REGISTERS ASSOCIATED WITH CWG Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CWG1CLKCON — — — — — — CWG1ISM — — — — CWG1DBR — — — — CWG1CON0 EN LD — IN — — CWG1AS0 SHUTDOWN REN CWG1AS1 — — CWG1STR OVRD OVRC Legend: Bit 0 Register on Page — CS 356 IS 356 DBR CWG1DBF CWG1CON1 Bit 1 352 DBF — — — POLD LSBD 352 MODE POLC LSAC 355 POLB POLA — — 351 353 — AS4E AS3E AS2E AS1E AS0E 354 OVRB OVRA STRD STRC STRB STRA 355 – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 357 PIC16(L)F15325/45 31.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) module provides programmable logic that operates outside the speed limitations of software execution. The logic cell selects from 40 input signals and, through the use of configurable gates, reduces the inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: • • • • I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. Refer to Figure 31-1 for a simplified diagram showing signal flow through the CLCx. Possible configurations include: • Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR • Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset The CLC modules available are shown in Table 31-1. TABLE 31-1: AVAILABLE CLC MODULES Device CLC1 CLC2 CLC3 CLC4 PIC16(L)F15325/45 Note: ● ● ● ● The CLC1, CLC2, CLC3 and CLC4 are four separate module instances of the same CLC module design. Throughout this section, the lower case ‘x’ in register and bit names is a generic reference to the CLC number (which should be substituted with 1, 2, 3, or 4 during code development). For example, the control register is generically described in this chapter as CLCxCON, but the actual device registers are CLC1CON, CLC2CON, CLC3CON and CLC4CON. Similarly, the LCxEN bit represents the LC1EN, LC2EN, LC3EN and LC4EN bits.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 358 PIC16(L)F15325/45 FIGURE 31-1: CLCx SIMPLIFIED BLOCK DIAGRAM Rev. 10-000025H 11/9/2016 D OUT CLCxOUT Q Q1 . . . LCx_in[n-2] LCx_in[n-1] LCx_in[n] CLCx_out Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] EN lcxg1 lcxg2 CLCxPPS Logic lcxq Function lcxg3 to Peripherals PPS CLCx (2) lcxg4 POL MODE TRIS Interrupt det INTP INTN set bit CLCxIF Interrupt det Note 1: 2: See Figure 31-2: Input Data Selection and Gating. See Figure 31-3: Programmable Logic Functions.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 359 PIC16(L)F15325/45 31.1 TABLE 31-2: CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: • • • • Data selection Data gating Logic function selection Output polarity CLCx DATA INPUT SELECTION LCxDyS Value CLCx Input Source 101000 to 111111 [40+] Reserved 100111 [39] CWG1B output 100110 [38] CWG1A output 100101 [37] Reserved 100100 [36] Reserved 100011 [35] MSSP1 SCK output Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 100010 [34] MSSP1 SDO output 011111 [31] EUSART1 (TX/CK) output 31.1.1 011110 [30] EUSART1 (DT) output 011101 [29] CLC4 output 011100 [28] CLC3 output 011011 [27] CLC2 output 011010 [26] CLC1 output DATA SELECTION There are 40 signals available as inputs to the configurable logic. Four 40-input multiplexers are used to select the inputs to pass on to the next stage. Data selection is through four multiplexers as indicated on the left side of Figure 31-2. Data inputs in the figure are identified by a generic numbered input name. Table 31-2 correlates the generic input name to the actual signal for each CLC module. The column labeled ‘LCxDyS Value’ indicates the MUX selection code for the selected data input. LCxDyS is an abbreviation to identify specific multiplexers: LCxD1S through LCxD4S. Data inputs are selected with CLCxSEL0 through CLCxSEL3 registers (Register 31-3 through Register 31-6).  2016 Microchip Technology Inc. 100001 [33] EUSART2 (TX/CK) output 100000 [32] EUSART2 (DT) output 011001 [25] IOCIF 011000 [24] ZCD output 010111 [23] C2OUT 010110 [22] C1OUT 010101 [21] NCO1 output 010100 [20] PWM6 output 010011 [19] PWM5 output 010010 [18] PWM4 output 010001 [17] PWM3 output 010000 [16] CCP2 output 001111 [15] CCP1 output 001110 [14] Timer2 overflow 001101 [13] Timer1 overflow 001100 [12] Timer0 overflow 001011 [11] CLKR 001010 [10] ADCRC 001001 [9] SOSC 001000 [8] MFINTOSC (32 kHz) 000111 [7] MFINTOSC (500 kHz) 000110 [6] LFINTOSC 000101 [5] HFINTOSC 000100 [4] FOSC 000011 [3] CLCIN3PPS 000010 [2] CLCIN2PPS 000001 [1] CLCIN1PPS 000000 [0] CLCIN0PPS Preliminary DS40001865B-page 360 PIC16(L)F15325/45 31.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: 31.1.3 Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND or all enabled inputs. Table 31-3 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. TABLE 31-3: CLCxGLSy 1 4-input AND 0x55 0 4-input NAND 0xAA 1 4-input NOR 0xAA 0 4-input OR 0x00 0 Logic 0 0x00 1 Logic 1 • • • • • • • • AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 31-2. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. OUTPUT POLARITY The last stage in the Configurable Logic Cell is the output polarity. Setting the LCxPOL bit of the CLCxPOL register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. Gate Logic 0x55 LOGIC FUNCTION There are eight available logic functions including: 31.1.4 DATA GATING LOGIC LCxGyPOL Data gating is indicated in the right side of Figure 31-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: • • • • Gate 1: CLCxGLS0 (Register 31-7) Gate 2: CLCxGLS1 (Register 31-8) Gate 3: CLCxGLS2 (Register 31-9) Gate 4: CLCxGLS3 (Register 31-10) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 361 PIC16(L)F15325/45 31.2 CLCx Interrupts 31.6 An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR5 register will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: • CLCxIE bit of the PIE5 register • LCxINTP bit of the CLCxCON register (for a rising edge detection) • LCxINTN bit of the CLCxCON register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The CLCxIF bit of the PIR5 register, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 31.3 Output Mirror Copies Mirror copies of all LCxCON output bits are contained in the CLCxDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the LCxOUT bits in the individual CLCxCON registers. 31.4 Effects of a Reset CLCx Setup Steps The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 through CLCxSEL3 registers (See Table 31-2). • Clear any associated ANSEL bits. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. • Select the gate output polarities with the LCxGyPOL bits of the CLCxPOL register. • Select the desired logic function with the LCxMODE bits of the CLCxCON register. • Select the desired polarity of the logic output with the LCxPOL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). • If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. • If interrupts are desired, configure the following bits: - Set the LCxINTP bit in the CLCxCON register for rising event. - Set the LCxINTN bit in the CLCxCON register for falling event. - Set the CLCxIE bit of the PIE5 register. - Set the GIE and PEIE bits of the INTCON register. • Enable the CLCx by setting the LCxEN bit of the CLCxCON register. The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 31.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 362 PIC16(L)F15325/45 FIGURE 31-2: INPUT DATA SELECTION AND GATING Data Selection LCx_in Data GATE 1 lcxd1T LCxD1G1T lcxd1N LCxD1G1N LCx_in LCxD2G1T LCxD1S LCxD2G1N lcxg1 LCx_in LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCxD4G1T LCx_in LCxD2S LCxD4G1N LCx_in Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N Data GATE 3 LCx_in lcxg3 LCxD3S (Same as Data GATE 1) Data GATE 4 LCx_in lcxg4 (Same as Data GATE 1) lcxd4T lcxd4N LCx_in LCxD4S  2016 Microchip Technology Inc. Preliminary DS40001865B-page 363 PIC16(L)F15325/45 FIGURE 31-3: PROGRAMMABLE LOGIC FUNCTIONS Rev. 10-000122A 5/18/2016 AND-OR OR-XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxq lcxg3 lcxg3 lcxg4 lcxg4 LCxMODE = 000 LCxMODE = 001 4-input AND S-R Latch lcxg1 lcxg1 S Q lcxq Q lcxq lcxg2 lcxg2 lcxq lcxg3 lcxg3 R lcxg4 lcxg4 LCxMODE = 010 LCxMODE = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 R lcxg3 R lcxg3 LCxMODE = 100 LCxMODE = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 J Q lcxq lcxg2 D lcxg3 LE S Q lcxq lcxg1 lcxg4 K R lcxg3 R lcxg1 LCxMODE = 110  2016 Microchip Technology Inc. LCxMODE = 111 Preliminary DS40001865B-page 364 PIC16(L)F15325/45 31.7 Register Definitions: CLC Control REGISTER 31-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 LCxEN — LCxOUT LCxINTP LCxINTN R/W-0/0 R/W-0/0 R/W-0/0 LCxMODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxEN: Configurable Logic Cell Enable bit 1 = Configurable logic cell is enabled and mixing input signals 0 = Configurable logic cell is disabled and has logic zero output bit 6 Unimplemented: Read as ‘0’ bit 5 LCxOUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on CLCxOUT 0 = CLCxIF will not be set bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on CLCxOUT 0 = CLCxIF will not be set bit 2-0 LCxMODE: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K flip-flop with R 101 = Cell is 2-input D flip-flop with R 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR  2016 Microchip Technology Inc. Preliminary DS40001865B-page 365 PIC16(L)F15325/45 REGISTER 31-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: CLCxOUT Output Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as ‘0’ bit 3 LCxG4POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 2 LCxG3POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 1 LCxG2POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted bit 0 LCxG1POL: Gate 0 Output Polarity Control bit 1 = The output of gate 0 is inverted when applied to the logic cell 0 = The output of gate 0 is not inverted  2016 Microchip Technology Inc. Preliminary DS40001865B-page 366 PIC16(L)F15325/45 REGISTER 31-3: CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD1S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD1S: CLCx Data1 Input Selection bits See Table 31-2. REGISTER 31-4: CLCxSEL1: GENERIC CLCx DATA 1 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD2S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD2S: CLCx Data 2 Input Selection bits See Table 31-2. REGISTER 31-5: CLCxSEL2: GENERIC CLCx DATA 2 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD3S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD3S: CLCx Data 3 Input Selection bits See Table 31-2. REGISTER 31-6: CLCxSEL3: GENERIC CLCx DATA 3 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD4S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD4S: CLCx Data 4 Input Selection bits See Table 31-2.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 367 PIC16(L)F15325/45 REGISTER 31-7: CLCxGLS0: GATE 0 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 0 0 = CLCIN3 (true) is not gated into CLCx Gate 0 bit 6 LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 0 0 = CLCIN3 (inverted) is not gated into CLCx Gate 0 bit 5 LCxG1D3T: Gate 0 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 0 0 = CLCIN2 (true) is not gated into CLCx Gate 0 bit 4 LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 0 0 = CLCIN2 (inverted) is not gated into CLCx Gate 0 bit 3 LCxG1D2T: Gate 0 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 0 0 = CLCIN1 (true) is not gated into l CLCx Gate 0 bit 2 LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 0 0 = CLCIN1 (inverted) is not gated into CLCx Gate 0 bit 1 LCxG1D1T: Gate 0 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 0 0 = CLCIN0 (true) is not gated into CLCx Gate 0 bit 0 LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 0 0 = CLCIN0 (inverted) is not gated into CLCx Gate 0  2016 Microchip Technology Inc. Preliminary DS40001865B-page 368 PIC16(L)F15325/45 REGISTER 31-8: CLCxGLS1: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 1 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 1 0 = CLCIN3 (true) is not gated into CLCx Gate 1 bit 6 LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 1 0 = CLCIN3 (inverted) is not gated into CLCx Gate 1 bit 5 LCxG2D3T: Gate 1 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 1 0 = CLCIN2 (true) is not gated into CLCx Gate 1 bit 4 LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 1 0 = CLCIN2 (inverted) is not gated into CLCx Gate 1 bit 3 LCxG2D2T: Gate 1 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 1 0 = CLCIN1 (true) is not gated into CLCx Gate 1 bit 2 LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 1 0 = CLCIN1 (inverted) is not gated into CLCx Gate 1 bit 1 LCxG2D1T: Gate 1 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 1 0 = CLCIN0 (true) is not gated into CLCx Gate1 bit 0 LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 1 0 = CLCIN0 (inverted) is not gated into CLCx Gate 1  2016 Microchip Technology Inc. Preliminary DS40001865B-page 369 PIC16(L)F15325/45 REGISTER 31-9: CLCxGLS2: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 2 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 2 0 = CLCIN3 (true) is not gated into CLCx Gate 2 bit 6 LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 2 0 = CLCIN3 (inverted) is not gated into CLCx Gate 2 bit 5 LCxG3D3T: Gate 2 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 2 0 = CLCIN2 (true) is not gated into CLCx Gate 2 bit 4 LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 2 0 = CLCIN2 (inverted) is not gated into CLCx Gate 2 bit 3 LCxG3D2T: Gate 2 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 2 0 = CLCIN1 (true) is not gated into CLCx Gate 2 bit 2 LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 2 0 = CLCIN1 (inverted) is not gated into CLCx Gate 2 bit 1 LCxG3D1T: Gate 2 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 2 0 = CLCIN0 (true) is not gated into CLCx Gate 2 bit 0 LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 2 0 = CLCIN0 (inverted) is not gated into CLCx Gate 2  2016 Microchip Technology Inc. Preliminary DS40001865B-page 370 PIC16(L)F15325/45 REGISTER 31-10: CLCxGLS3: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 3 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 3 0 = CLCIN3 (true) is not gated into CLCx Gate 3 bit 6 LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 3 0 = CLCIN3 (inverted) is not gated into CLCx Gate 3 bit 5 LCxG4D3T: Gate 3 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 3 0 = CLCIN2 (true) is not gated into CLCx Gate 3 bit 4 LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 3 0 = CLCIN2 (inverted) is not gated into CLCx Gate 3 bit 3 LCxG4D2T: Gate 3 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 3 0 = CLCIN1 (true) is not gated into CLCx Gate 3 bit 2 LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 3 0 = CLCIN1 (inverted) is not gated into CLCx Gate 3 bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 3 0 = CLCIN0 (true) is not gated into CLCx Gate 3 bit 0 LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 3 0 = CLCIN0 (inverted) is not gated into CLCx Gate 3  2016 Microchip Technology Inc. Preliminary DS40001865B-page 371 PIC16(L)F15325/45 REGISTER 31-11: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit  2016 Microchip Technology Inc. Preliminary DS40001865B-page 372 PIC16(L)F15325/45 TABLE 31-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE ― ― ― ― ― INTEDG 124 PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — — — TMR1GIF 138 PIE5 CLC4IE CLC4IE CLC2IE CLC1IE — — — TMR1GIE CLC1CON LC1EN ― LC1OUT LC1INTP LC1INTN CLC1POL LC1POL ― ― ― LC1G4POL CLC1SEL0 ― ― LC1D1S 367 CLC1SEL1 ― ― LC1D2S 367 CLC1SEL2 ― ― LC1D3S 367 CLC1SEL3 ― ― LC1D4S CLC1GLS0 ― ― LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 368 CLC1GLS1 ― ― LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 369 CLC1GLS2 ― ― LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 370 CLC1GLS3 ― ― LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 371 CLC2CON LC2EN ― LC2OUT LC2INTP LC2INTN CLC2POL LC2POL ― ― ― LC2G4POL CLC2SEL0 ― ― LC2D1S 367 CLC2SEL1 ― ― LC2D2S 367 CLC2SEL2 ― ― LC2D3S 367 CLC2SEL3 ― ― CLC2GLS0 ― ― LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 368 CLC2GLS1 ― ― LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 369 CLC2GLS2 ― ― LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 370 CLC2GLS3 ― ― LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 371 CLC3CON LC3EN ― LC3OUT LC3INTP LC3INTN CLC3POL LC3POL ― ― ― LC3G4POL CLC3SEL0 ― ― LC3D1S 367 CLC3SEL1 ― ― LC3D2S 367 CLC3SEL2 ― ― LC3D3S 367 CLC3SEL3 ― ― LC3D4S 367 Name INTCON LC1MODE LC1G3POL LC1G2POL LC1G1POL LC2G2POL 365 LC2G1POL LC2D4S 366 367 LC3MODE LC3G3POL 366 367 LC2MODE LC2G3POL 130 365 LC3G2POL 365 LC3G1POL 366 CLC3GLS0 ― ― LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 368 CLC3GLS1 ― ― LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 369 CLC3GLS2 ― ― LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 370 CLC3GLS3 ― ― LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 371 CLC4CON LC4EN ― LC4OUT LC4INTP LC4INTN CLC4POL LC4POL ― ― ― LC4G4POL CLC4SEL0 ― ― LC4D1S 367 CLC4SEL1 ― ― LC4D2S 367 CLC4SEL2 ― ― LC4D3S 367 CLC4SEL3 ― ― LC4D4S 367 ― ― CLC4GLS0 Legend: LC4G1D3T LC4G1D3N LC4G1D2T LC4MODE LC4G3POL LC4G1D2N LC4G2POL LC4G1D1T 365 LC4G1POL LC4G1D1N 366 368 — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 373 PIC16(L)F15325/45 TABLE 31-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLC4GLS1 ― ― LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 369 CLC4GLS2 ― ― LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 370 CLC4GLS3 ― ― LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N CLCIN0PPS ― ― CLCIN0PPS 199 CLCIN1PPS ― ― CLCIN1PPS 199 CLCIN2PPS ― ― CLCIN2PPS 199 ― ― CLCIN3PPS 199 CLCIN3PPS Legend: 371 — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 374 PIC16(L)F15325/45 32.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP1) MODULE 32.1 MSSP Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: • • • • • Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 32-1 is a block diagram of the SPI interface module. FIGURE 32-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSP1BUF Reg SSPDATPPS SDI PPS SSPSR Reg Shift Clock bit 0 SDO PPS RxyPPS SS SS Control Enable PPS Edge Select SSPSSPPS SSPCLKPPS(2) SCK SSPM 4 PPS Edge Select PPS TRIS bit Note 1: 2: 2 (CKP, CKE) Clock Select RxyPPS(1) ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSP1ADD) Output selection for master mode. Input selection for slave mode.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 375 PIC16(L)F15325/45 The I2C interface supports the following modes and features: • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Selectable SDA hold times FIGURE 32-2: Figure 32-2 is a block diagram of the I2C interface module in Master mode. Figure 32-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal data bus SSPDATPPS(1) Read [SSPM] Write SDA SDA in SSP1BUF Baud Rate Generator (SSP1ADD) SSPCLKPPS(2) SCL PPS Receive Enable (RCEN) MSb LSb Start bit, Stop bit, Acknowledge Generate (SSP1CON2) Clock Cntl SSPSR PPS (Hold off clock source) Shift Clock RxyPPS(1) Clock arbitrate/BCOL detect PPS PPS RxyPPS(2) SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Note 1: SDA pin selections must be the same for input and output. 2: SCL pin selections must be the same for input and output.  2016 Microchip Technology Inc. Preliminary Set/Reset: S, P, SSP1STAT, WCOL, SSPOV Reset SEN, PEN (SSP1CON2) Set SSP1IF, BCL1IF DS40001865B-page 376 PIC16(L)F15325/45 FIGURE 32-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPCLKPPS(2) SCL PPS PPS SSP1BUF Reg Shift Clock Clock Stretching SSPSR Reg MSb RxyPPS(2) LSb SSP1MSK Reg (1) SSPDATPPS SDA Match Detect Addr Match PPS SSP1ADD Reg PPS Start and Stop bit Detect RxyPPS(1) Note 1: SDA pin selections must be the same for input and output. 2: SCL pin selections must be the same for input and output.  2016 Microchip Technology Inc. Preliminary Set, Reset S, P bits (SSP1STAT Reg) DS40001865B-page 377 PIC16(L)F15325/45 32.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Figure 32-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 32-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. Data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Master sends useful data and slave sends dummy data. • Master sends useful data and slave sends useful data. • Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 32-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 378 PIC16(L)F15325/45 FIGURE 32-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 32.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: • • • • • • MSSP STATUS register (SSP1STAT) MSSP Control register 1 (SSP1CON1) MSSP Control register 3 (SSP1CON3) MSSP Data Buffer register (SSP1BUF) MSSP Address register (SSP1ADD) MSSP Shift register (SSP1SR) (Not directly accessible) SSP1CON1 and SSP1STAT are the control and status registers in SPI mode operation. The SSP1CON1 register is readable and writable. The lower six bits of the SSP1STAT are read-only. The upper two bits of the SSP1STAT are read/write. In one SPI master mode, SSP1ADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 32.7 “Baud Rate Generator”. SSP1SR is the shift register used for shifting data in and out. SSP1BUF provides indirect access to the SSP1SR register. SSP1BUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSP1SR and SSP1BUF together create a buffered receiver. When SSP1SR receives a complete byte, it is transferred to SSP1BUF and the SSP1IF interrupt is set. During transmission, the SSP1BUF is not buffered. A write to SSP1BUF will write to both SSP1BUF and SSP1SR.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 379 PIC16(L)F15325/45 32.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSP1CON1 and SSP1STAT). These control bits allow the following to be specified: • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSP1CON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSP1CONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRISx register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set The MSSP consists of a transmit/receive shift register (SSP1SR) and a buffer register (SSP1BUF). The SSP1SR shifts the data in and out of the device, MSb first. The SSP1BUF holds the data that was written to the SSP1SR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSP1BUF register. Then, the Buffer Full Detect bit, BF of the SSP1STAT register, and the interrupt flag bit, SSP1IF, are set. Any write to the SSP1BUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSP1CON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSP1BUF register to complete successfully. When the application software is expecting to receive valid data, the SSP1BUF should be read before the next byte of data to transfer is written to the SSP1BUF. The Buffer Full bit, BF of the SSP1STAT register, indicates when SSP1BUF has been loaded with the received data (transmission is complete). When the SSP1BUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSP1SR is not directly readable or writable and can only be accessed by addressing the SSP1BUF register. Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 32-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPM = 00xx = 1010 SPI Slave SSPM = 010x SDO SDI Serial Input Buffer (SSP1BUF) SDI Shift Register (SSP1SR) MSb Serial Input Buffer (SSP1BUF) LSb SCK General I/O Processor 1  2016 Microchip Technology Inc. SDO Serial Clock Slave Select (optional) Preliminary Shift Register (SSP1SR) MSb LSb SCK SS Processor 2 DS40001865B-page 380 PIC16(L)F15325/45 32.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSP1CON1 register and the CKE bit of the SSP1STAT register. This then, would give waveforms for SPI communication as shown in Figure 32-6, Figure 32-8, Figure 32-9 and Figure 32-10, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 32-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSP1BUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSP1SR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSP1BUF register as if a normal received byte (interrupts and Status bits appropriately set). • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSP1ADD + 1)) Figure 32-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSP1BUF is loaded with the received data is shown. FIGURE 32-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSP1BUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSP1IF SSP1SR to SSP1BUF  2016 Microchip Technology Inc. Preliminary DS40001865B-page 381 PIC16(L)F15325/45 32.2.4 32.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSP1IF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSP1CON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 32.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 32-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSP1CON3 register will enable writes to the SSP1BUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. SLAVE SELECT SYNCHRONIZATION The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSP1CON1 = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSP1CON1 = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSP1STAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 382 PIC16(L)F15325/45 FIGURE 32-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 32-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Shift register SSP1SR and bit count are reset SSP1BUF to SSP1SR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF  2016 Microchip Technology Inc. Preliminary DS40001865B-page 383 PIC16(L)F15325/45 FIGURE 32-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active FIGURE 32-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active  2016 Microchip Technology Inc. Preliminary DS40001865B-page 384 PIC16(L)F15325/45 32.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. 32.3 I2C This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. FIGURE 32-11: VDD SCL MODE OVERVIEW The Inter-Integrated Circuit bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. SCL VDD Master (I2C) The I2C bus specifies two signal connections: I2C MASTER/ SLAVE CONNECTION Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. • Serial Clock (SCL) • Serial Data (SDA) Figure 32-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 32-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: • Master Transmit mode (master is transmitting data to a slave) • Master Receive mode (master is receiving data from a slave) • Slave Transmit mode (slave is transmitting data to a master) • Slave Receive mode (slave is receiving data from the master) The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit. To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 385 PIC16(L)F15325/45 32.3.1 CLOCK STRETCHING 32.4 When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 32.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common.  2016 Microchip Technology Inc. I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 32.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 32.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 32.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note 1: Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPDATPPS registers. The SCL input is selected with the SSPCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user’s responsibility to make the selections so that both the input and the output for each function is on the same pin. Preliminary DS40001865B-page 386 PIC16(L)F15325/45 32.4.4 SDA HOLD TIME 32.4.5 The hold time of the SDA pin is selected by the SDAHT bit of the SSP1CON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. TABLE 32-1: TERM I2C BUS TERMS Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSP1ADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state.  2016 Microchip Technology Inc. The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an active state. Figure 32-12 shows wave forms for Start and Stop conditions. 32.4.6 Description START CONDITION STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. 32.4.7 RESTART CONDITION A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 32-13 shows the wave form for a Restart condition. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. 32.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSP1CON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. Preliminary DS40001865B-page 387 PIC16(L)F15325/45 FIGURE 32-12: I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 32-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition 32.4.9 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSP1CON2 register.  2016 Microchip Technology Inc. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSP1CON2 register is set/cleared to determine the response. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSP1STAT register or the SSPOV bit of the SSP1CON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSP1CON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. Preliminary DS40001865B-page 388 PIC16(L)F15325/45 32.5 I2C SLAVE MODE OPERATION 32.5.2 The MSSP Slave mode operates in one of four modes selected by the SSPM bits of SSP1CON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSP1IF additionally getting set upon detection of a Start, Restart, or Stop condition. 32.5.1 SLAVE MODE ADDRESSES The SSP1ADD register (Register 32-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSP1BUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 32-5) affects the address matching process. See Section 32.5.9 “SSP Mask Register” for more information. 32.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 32.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb’s of the 10-bit address and stored in bits 2 and 1 of the SSP1ADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSP1ADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSP1ADD. Even if there is not an address match; SSP1IF and UA are set, and SCL is held low until SSP1ADD is updated to receive a high byte again. When SSP1ADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match.  2016 Microchip Technology Inc. SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSP1STAT register is cleared. The received address is loaded into the SSP1BUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSP1STAT register is set, or bit SSPOV of the SSP1CON1 register is set. The BOEN bit of the SSP1CON3 register modifies this operation. For more information see Register 32-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSP1IF, must be cleared by software. When the SEN bit of the SSP1CON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSP1CON1 register. 32.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 32-14 and Figure 32-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Preliminary Start bit detected. S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears the SSP1IF bit. Software reads received address from SSP1BUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears SSP1IF. Software reads the received byte from SSP1BUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSP1STAT, and the bus goes idle. DS40001865B-page 389 PIC16(L)F15325/45 32.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allows time for the slave software to decide whether it wants to ACK the receive address or data byte. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 32-16 displays a module using both address and data holding. Figure 32-17 includes the operation with the SEN bit of the SSP1CON2 register set. 1. S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSP1IF is set and CKP cleared after the eighth falling edge of SCL. 3. Slave clears the SSP1IF. 4. Slave can look at the ACKTIM bit of the SSP1CON3 register to determine if the SSP1IF was after or before the ACK. 5. Slave reads the address value from SSP1BUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSP1IF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSP1IF. Note: SSP1IF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSP1IF not set 11. SSP1IF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSP1CON3 to determine the source of the interrupt. 13. Slave reads the received data from SSP1BUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSP1STAT register.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 390  2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 32-14: Bus Master sends Stop condition From Slave to Master Receiving Address SDA SCL S Receiving Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 ACK 8 9 Receiving Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 ACK = 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P Preliminary SSP1IF Cleared by software Cleared by software SSP1BUF is read First byte of data is available in SSP1BUF SSPOV SSPOV set because SSP1BUF is still full. ACK is not sent. DS40001865B-page 391 PIC16(L)F15325/45 BF SSP1IF set on 9th falling edge of SCL  2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-15: Bus Master sends Stop condition Receive Address SDA SCL S Receive Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 R/W=0 ACK 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to ‘1’ Preliminary SSP1IF Cleared by software BF SSP1IF set on 9th falling edge of SCL First byte of data is available in SSP1BUF SSPOV SSPOV set because SSP1BUF is still full. ACK is not sent. CKP DS40001865B-page 392 CKP is written to ‘1’ in software, releasing SCL CKP is written to ‘1’ in software, releasing SCL SCL is not held low because ACK= 1 PIC16(L)F15325/45 SSP1BUF is read Cleared by software  2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 32-16: Master sends Stop condition Master Releases SDA to slave for ACK sequence Receiving Address SDA Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 Received Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSP1IF If AHEN = 1: SSP1IF is set BF Preliminary ACKDT CKP SSP1IF is set on 9th falling edge of SCL, after ACK Address is read from SSP1BUF Data is read from SSP1BUF Slave software clears ACKDT to ACK the received byte Slave software sets ACKDT to not ACK When DHEN = 1: CKP is cleared by hardware on 8th falling edge of SCL CKP set by software, SCL is released ACKTIM ACKTIM set by hardware on 8th falling edge of SCL DS40001865B-page 393 S P ACKTIM cleared by hardware in 9th rising edge of SCL ACKTIM set by hardware on 8th falling edge of SCL PIC16(L)F15325/45 When AHEN = 1: CKP is cleared by hardware and SCL is stretched No interrupt after not ACK from Slave Cleared by software  2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 32-17: R/W = 0 Receiving Address SDA ACK A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 3 4 5 6 7 Master sends Stop condition Master releases SDA to slave for ACK sequence 8 9 Receive Data 1 2 3 4 5 6 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 7 8 ACK 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P SSP1IF No interrupt after if not ACK from Slave Cleared by software Preliminary BF Received address is loaded into SSP1BUF Received data is available on SSP1BUF ACKDT Slave sends not ACK CKP When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL DS40001865B-page 394 S P ACKTIM is cleared by hardware on 9th rising edge of SCL Set by software, release SCL CKP is not cleared if not ACK PIC16(L)F15325/45 Slave software clears ACKDT to ACK the received byte SSP1BUF can be read any time before next byte is loaded PIC16(L)F15325/45 32.5.3 SLAVE TRANSMISSION 32.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSP1STAT register is set. The received address is loaded into the SSP1BUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 32-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 32.5.6 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSP1BUF register which also loads the SSP1SR register. Then the SCL pin should be released by setting the CKP bit of the SSP1CON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSP1CON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSP1BUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSP1IF bit must be cleared by software and the SSP1STAT register is used to determine the status of the byte. The SSP1IF bit is set on the falling edge of the ninth clock pulse. 32.5.3.1 Slave Mode Bus Collision A slave receives a read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSP1CON3 register is set, the BCL1IF bit of the PIR3 register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCL1IF bit to handle a slave bus collision.  2016 Microchip Technology Inc. Master sends a Start condition on SDA and SCL. 2. S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSP1IF bit. 4. Slave hardware generates an ACK and sets SSP1IF. 5. SSP1IF bit is cleared by user. 6. Software reads the received address from SSP1BUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSP1BUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSP1IF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSP1IF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSP1IF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. Preliminary DS40001865B-page 395  2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) FIGURE 32-18: Master sends Stop condition Receiving Address SDA R/W = 1 A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 3 4 5 6 7 ACK 8 9 Automatic Transmitting Data Automatic ACK Transmitting Data D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 P SSP1IF Cleared by software BF Received address is read from SSP1BUF Data to transmit is loaded into SSP1BUF BF is automatically cleared after 8th falling edge of SCL Preliminary CKP When R/W is set SCL is always held low after 9th SCL falling edge Set by software CKP is not held for not ACK ACKSTAT R/W R/W is copied from the matching address byte D/A DS40001865B-page 396 Indicates an address has been received S P PIC16(L)F15325/45 Masters not ACK is copied to ACKSTAT PIC16(L)F15325/45 32.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSP1CON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure 32-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSP1IF interrupt is generated. 4. Slave software clears SSP1IF. 5. Slave software reads ACKTIM bit of SSP1CON3 register, and R/W and D/A of the SSP1STAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSP1BUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSP1CON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSP1IF after the ACK if the R/W bit is set. 11. Slave software clears SSP1IF. 12. Slave loads value to transmit to the master into SSP1BUF setting the BF bit. Note: SSP1BUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSP1CON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 397  2016 Microchip Technology Inc. FIGURE 32-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) Master sends Stop condition Master releases SDA to slave for ACK sequence Receiving Address SDA SCL ACK A7 A6 A5 A4 A3 A2 A1 S 1 2 3 4 5 6 Automatic R/W = 1 7 8 9 Transmitting Data Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 ACK 8 9 P SSP1IF Cleared by software BF Received address is read from SSP1BUF Data to transmit is loaded into SSP1BUF BF is automatically cleared after 8th falling edge of SCL Preliminary ACKDT Slave clears ACKDT to ACK address ACKSTAT CKP When AHEN = 1; CKP is cleared by hardware after receiving matching address. ACKTIM DS40001865B-page 398 R/W D/A ACKTIM is set on 8th falling edge of SCL CKP not cleared When R/W = 1; CKP is always cleared after ACK Set by software, releases SCL ACKTIM is cleared on 9th rising edge of SCL after not ACK PIC16(L)F15325/45 Master’s ACK response is copied to SSP1STAT PIC16(L)F15325/45 32.5.4 32.5.5 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 32-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSP1STAT register is set. Slave sends ACK and SSP1IF is set. Software clears the SSP1IF bit. Software reads received address from SSP1BUF clearing the BF flag. Slave loads low address into SSP1ADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSP1ADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 32-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 32-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSP1ADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSP1IF is set. Note: If the low address does not match, SSP1IF and UA are still set so that the slave software can set SSP1ADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSP1IF. 11. Slave reads the received matching address from SSP1BUF clearing BF. 12. Slave loads high address into SSP1ADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSP1IF is set. 14. If SEN bit of SSP1CON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSP1IF. 16. Slave reads the received byte from SSP1BUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 399  2016 Microchip Technology Inc. I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 32-20: Master sends Stop condition Receive Second Address Byte Receive First Address Byte SDA SCL S 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 Receive Data Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 P SCL is held low while CKP = 0 SSP1IF Preliminary Set by hardware on 9th falling edge Cleared by software BF Receive address is read from SSP1BUF Data is read from SSP1BUF UA When UA = 1; SCL is held low Software updates SSP1ADD and releases SCL CKP DS40001865B-page 400 Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte PIC16(L)F15325/45 If address matches SSP1ADD it is loaded into SSP1BUF  2016 Microchip Technology Inc. I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 32-21: Receive First Address Byte SDA SCL S Receive Second Address Byte R/W = 0 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 UA Receive Data A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 UA Receive Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 D6 D5 2 SSP1IF Set by hardware on 9th falling edge Cleared by software Cleared by software Preliminary BF SSP1BUF can be read anytime before the next received byte Received data is read from SSP1BUF ACKDT UA Update to SSP1ADD is not allowed until 9th falling edge of SCL CKP DS40001865B-page 401 If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL Update of SSP1ADD, clears UA and releases SCL Set CKP with software releases SCL PIC16(L)F15325/45 Slave software clears ACKDT to ACK the received byte  2016 Microchip Technology Inc. I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 32-22: Master sends Restart event Receiving Address R/W = 0 1 1 1 1 0 A9 A8 SDA SCL S 1 2 3 4 5 6 7 ACK 8 9 Receiving Second Address Byte 2 3 4 5 6 7 8 Transmitting Data Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 Master sends not ACK 1 1 1 1 0 A9 A8 1 9 2 3 4 5 6 7 8 ACK 9 Master sends Stop condition ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Sr SSP1IF Preliminary Set by hardware Cleared by software Set by hardware BF SSP1BUF loaded with received address Received address is read from SSP1BUF Data to transmit is loaded into SSP1BUF UA CKP After SSP1ADD is updated, UA is cleared and SCL is released High address is loaded back into SSP1ADD When R/W = 1; CKP is cleared on 9th falling edge of SCL ACKSTAT Set by software releases SCL Masters not ACK is copied R/W DS40001865B-page 402 R/W is copied from the matching address byte D/A Indicates an address has been received PIC16(L)F15325/45 UA indicates SSP1ADD must be updated PIC16(L)F15325/45 32.5.6 CLOCK STRETCHING 32.5.6.3 Byte NACKing Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. When AHEN bit of SSP1CON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When DHEN bit of SSP1CON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. The CKP bit of the SSP1CON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 32.5.7 32.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSP1STAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSP1BUF with data to transfer to the master. If the SEN bit of SSP1CON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. 32.5.6.2 Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 32-23). 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSP1ADD. FIGURE 32-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSP1CON1  2016 Microchip Technology Inc. Preliminary DS40001865B-page 403 PIC16(L)F15325/45 32.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit of the SSP1CON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSP1CON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSP1ADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSP1BUF and respond. Figure 32-24 shows a general call reception sequence. FIGURE 32-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSP1IF BF (SSP1STAT) Cleared by software SSP1BUF is read GCEN (SSP1CON2) ’1’ 32.5.9 SSP MASK REGISTER An SSP Mask (SSP1MSK) register (Register 32-5) is available in I2C Slave mode as a mask for the value held in the SSP1SR register during an address comparison operation. A zero (‘0’) bit in the SSP1MSK register has the effect of making the corresponding bit of the received address a “don’t care”.  2016 Microchip Technology Inc. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A. • 10-bit Address mode: address compare of A only. The SSP mask has no effect during the reception of the first (high) byte of the address. Preliminary DS40001865B-page 404 PIC16(L)F15325/45 32.6 I2C Master Mode 32.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSP1CON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSP1IF, to be set (SSP interrupt, if enabled): • • • • • Start condition generated Stop condition generated Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSP1BUF register to initiate transmission before the Start condition is complete. In this case, the SSP1BUF will not be written to and the WCOL bit will be set, indicating that a write to the SSP1BUF did not occur In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 32.7 “Baud Rate Generator” for more detail. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 405 PIC16(L)F15325/45 32.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 32-25). FIGURE 32-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 32.6.3 WCOL STATUS FLAG If the user writes the SSP1BUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSP1BUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSP1CON2 is disabled until the Start condition is complete.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 406 PIC16(L)F15325/45 32.6.4 I2C MASTER MODE START CONDITION TIMING Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. To initiate a Start condition (Figure 32-26), the user sets the Start Enable bit, SEN bit of the SSP1CON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSP1STAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSP1ADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSP1CON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. FIGURE 32-26: 2: The Philips I2C specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Set S bit (SSP1STAT) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit and sets SSP1IF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSP1BUF occurs here SDA 1st bit 2nd bit TBRG SCL S  2016 Microchip Technology Inc. Preliminary TBRG DS40001865B-page 407 PIC16(L)F15325/45 32.6.5 I2C MASTER MODE REPEATED cally cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSP1STAT register will be set. The SSP1IF bit will not be set until the Baud Rate Generator has timed out. START CONDITION TIMING A Repeated Start condition (Figure 32-27) occurs when the RSEN bit of the SSP1CON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSP1CON2 register will be automati- FIGURE 32-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSP1CON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSP1IF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSP1BUF occurs here TBRG SCL Sr TBRG Repeated Start  2016 Microchip Technology Inc. Preliminary DS40001865B-page 408 PIC16(L)F15325/45 32.6.6 I2C MASTER MODE TRANSMISSION 32.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSP1BUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSP1IF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSP1BUF, leaving SCL low and SDA unchanged (Figure 32-28). After the write to the SSP1BUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSP1CON2 register. Following the falling edge of the ninth clock transmission of the address, the SSP1IF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSP1BUF takes place, holding SCL low and allowing SDA to float. 32.6.6.1 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSP1CON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 32.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. BF Status Flag Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSP1BUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSP1BUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. The user loads the SSP1BUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSP1CON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSP1STAT register is set when the CPU writes to SSP1BUF and is cleared when all eight bits are shifted out. 32.6.6.2 WCOL Status Flag If the user writes the SSP1BUF when a transmit is already in progress (i.e., SSP1SR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 409  2016 Microchip Technology Inc. I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) FIGURE 32-28: Write SSP1CON2 SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSP1CON2 SEN = 0 Transmit Address to Slave SDA A7 A6 A5 A4 ACKSTAT in SSP1CON2 = 1 A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 ACK = 0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCL held low while CPU responds to SSP1IF 2 3 4 5 6 7 8 SSP1BUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 9 P Preliminary SSP1IF Cleared by software Cleared by software service routine from SSP interrupt SSP1BUF written SEN After Start condition, SEN cleared by hardware PEN DS40001865B-page 410 R/W SSP1BUF is written by software PIC16(L)F15325/45 BF (SSP1STAT) Cleared by software PIC16(L)F15325/45 32.6.7 I2C MASTER MODE RECEPTION 32.6.7.4 Master mode reception (Figure 32-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSP1SR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSP1SR are loaded into the SSP1BUF, the BF flag bit is set, the SSP1IF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSP1CON2 register. 32.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSP1BUF from SSP1SR. It is cleared when the SSP1BUF register is read. 32.6.7.2 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSP1SR and the BF flag bit is already set from a previous reception. 32.6.7.3 1. WCOL Status Flag If the user writes the SSP1BUF when a receive is already in progress (i.e., SSP1SR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2016 Microchip Technology Inc. 12. 13. 14. 15. Preliminary Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. User writes SSP1BUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSP1BUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. User sets the RCEN bit of the SSP1CON2 register and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSP1IF and BF are set. Master clears SSP1IF and reads the received byte from SSP1BUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSP1CON2 register and initiates the ACK by setting the ACKEN bit. Master’s ACK is clocked out to the slave and SSP1IF is set. User clears SSP1IF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. DS40001865B-page 411  2016 Microchip Technology Inc. I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) FIGURE 32-29: Write to SSP1CON2 to start Ackno1wledge sequence SDA = ACKDT (SSP1CON2) = 0 Write to SSP1CON2(SEN = 1), begin Start condition Transmit Address to Slave A7 SDA A6 A5 A4 A3 A2 RCEN = 1, start next receive ACK PEN bit = 1 written here RCEN cleared automatically Receiving Data from Slave Receiving Data from Slave A1 R/W Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 ACK from Master SDA = ACKDT = 0 Master configured as a receiver by programming SSP1CON2 (RCEN = 1) SEN = 0 Write to SSP1BUF occurs here, RCEN cleared ACK from Slave automatically start XMIT D7 D6 D5 D4 D3 D2 D1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Bus master terminates transfer ACK is not sent SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 Data shifted in on falling edge of CLK Preliminary Set SSP1IF interrupt at end of receive Cleared by software Cleared by software Cleared by software Cleared by software Cleared in software Last bit is shifted into SSP1SR and contents are unloaded into SSP1BUF SSPOV SSPOV is set because SSP1BUF is still full ACKEN DS40001865B-page 412 RCEN Master configured as a receiver by programming SSP1CON2 (RCEN = 1) RCEN cleared automatically ACK from Master SDA = ACKDT = 0 RCEN cleared automatically Set SSP1IF interrupt at end of Acknowledge sequence Set P bit (SSP1STAT) and SSP1IF PIC16(L)F15325/45 BF (SSP1STAT) P Set SSP1IF at end of receive Set SSP1IF interrupt at end of Acknowledge sequence SSP1IF SDA = 0, SCL = 1 while CPU responds to SSP1IF 9 8 PIC16(L)F15325/45 32.6.8 ACKNOWLEDGE SEQUENCE TIMING 32.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSP1CON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSP1STAT register is set. A TBRG later, the PEN bit is cleared and the SSP1IF bit is set (Figure 32-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSP1CON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into IDLE mode (Figure 32-30). 32.6.8.1 32.6.9.1 WCOL Status Flag If the user writes the SSP1BUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSP1BUF when an Acknowledge sequence is in progress, then WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 32-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSP1CON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSP1IF SSP1IF set at the end of receive Cleared in software Cleared in software SSP1IF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 32-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSP1STAT) is set. Write to SSP1CON2, set PEN PEN bit (SSP1CON2) is cleared by hardware and the SSP1IF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 413 PIC16(L)F15325/45 32.6.10 SLEEP OPERATION 32.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 32.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 32.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSP1STAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCL1IF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF and reset the I2C port to its Idle state (Figure 32-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSP1BUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSP1CON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSP1IF bit will be set. A write to the SSP1BUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSP1STAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 32-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF  2016 Microchip Technology Inc. Preliminary DS40001865B-page 414 PIC16(L)F15325/45 32.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 32-33). SCL is sampled low before SDA is asserted low (Figure 32-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 32-35). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCL1IF flag is set and • the MSSP module is reset to its Idle state (Figure 32-33). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 32-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSP1IF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCL1IF SDA sampled low before Start condition. Set BCL1IF. S bit and SSP1IF set because SDA = 0, SCL = 1. SSP1IF and BCL1IF are cleared by software S SSP1IF SSP1IF and BCL1IF are cleared by software  2016 Microchip Technology Inc. Preliminary DS40001865B-page 415 PIC16(L)F15325/45 FIGURE 32-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software ’0’ ’0’ SSP1IF ’0’ ’0’ S FIGURE 32-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSP1IF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN BCL1IF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSP1IF SDA = 0, SCL = 1, set SSP1IF  2016 Microchip Technology Inc. Preliminary Interrupts cleared by software DS40001865B-page 416 PIC16(L)F15325/45 32.6.13.2 Bus Collision During a Repeated Start Condition counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 32-37. A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’ (Case 2). If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSP1ADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 32-36). If SDA is sampled high, the BRG is reloaded and begins FIGURE 32-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL1IF Cleared by software S ’0’ SSP1IF ’0’ FIGURE 32-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCL1IF SCL goes low before SDA, set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSP1IF  2016 Microchip Technology Inc. Preliminary DS40001865B-page 417 PIC16(L)F15325/45 32.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSP1ADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 32-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 32-39). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 32-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCL1IF SDA asserted low SCL PEN BCL1IF P ’0’ SSP1IF ’0’ FIGURE 32-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, set BCL1IF Assert SDA SCL PEN BCL1IF P ’0’ SSP1IF ’0’  2016 Microchip Technology Inc. Preliminary DS40001865B-page 418 PIC16(L)F15325/45 32.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSP1ADD register (Register 32-6). When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 32-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSP1ADD. EQUATION 32-1: FOSC FCLOCK = -------------------------------------------------- SSP 1ADD + 1   4  An internal signal “Reload” in Figure 32-40 triggers the value from SSP1ADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 32-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM SSPM Reload SCL Control SSPCLK SSP1ADD Reload BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSP1ADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 32-2: Note: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical specifications in Table 37-4 to ensure the system is designed to support IOL requirements.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 419 PIC16(L)F15325/45 32.8 Register Definitions: MSSP1 Control REGISTER 32-1: SSP1STAT: SSP1 STATUS REGISTER R/W-0/0 R/W-0/0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 SMP CKE(1) D/A P(2) S(2) R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Hardware set/clear bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)(1) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(2) (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (2) (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSP1ADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSP1BUF is full 0 = Receive not complete, SSP1BUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty Note 1: 2: Polarity of clock state is set by the CKP bit of the SSP1CON register. This bit is cleared on Reset and when SSPEN is cleared.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 420 PIC16(L)F15325/45 REGISTER 32-2: SSP1CON1: SSP1 CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV(1) SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, the following pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1101 = Reserved 1100 = Reserved 1011 = I2C firmware controlled Master mode (slave idle) 1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5) 1001 = Reserved 1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = T2_match/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. When enabled, these pins must be properly configured as input or output. Use SSP1SSPPS, SSP1CLKPPS, SSP1DATPPS, and RxyPPS to select the pins. When enabled, the SDA and SCL pins must be configured as inputs. Use SSP1CLKPPS, SSP1DATPPS, and RxyPPS to select the pins. SSP1ADD values of 0, 1 or 2 are not supported for I2C mode. SSP1ADD value of ‘0’ is not supported. Use SSPM = 0000 instead.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 421 PIC16(L)F15325/45 REGISTER 32-3: SSP1CON2: SSP1 CONTROL REGISTER 2 (I2C MODE ONLY)(1) R/W-0/0 R/HS/HC-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).  2016 Microchip Technology Inc. Preliminary DS40001865B-page 422 PIC16(L)F15325/45 REGISTER 32-4: SSP1CON3: SSP1 CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSPOV bit of the SSP1CON1 register is set, and the buffer is not updated In I2 C Master mode and SPI Master mode: This bit is ignored. In I2 C Slave mode: 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSP1BUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR3 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSP1CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP1CON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 423 PIC16(L)F15325/45 REGISTER 32-5: R/W-1/1 SSP1MSK: SSP1 MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SSP1MSK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 SSP1MSK: Mask bits 1 = The received address bit n is compared to SSP1ADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 SSP1MSK: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM = 0111 or 1111): 1 = The received address bit 0 is compared to SSP1ADD to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address: MSK0 bit is ignored. REGISTER 32-6: R/W-0/0 SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSP1ADD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 SSP1ADD: Baud Rate Clock Divider bits SCL pin clock period = ((ADD + 1) *4)/FOSC 10-Bit Slave mode – Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 SSP1ADD: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode – Least Significant Address Byte: bit 7-0 SSP1ADD: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 SSP1ADD: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 424 PIC16(L)F15325/45 REGISTER 32-7: R/W-x SSP1BUF: MSSP1 BUFFER REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SSP1BUF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SSP1BUF: MSSP Buffer bits TABLE 32-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH MSSP1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE — — — — — INTEDG 124 — — — — ADIF 134 — — — ― ADIE 126 S R/W UA BF 420 PIR1 OSFIF CSWIF — PIE1 OSFIE CSWIE — SSP1STAT SMP CKE D/A P SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 422 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 420 SSPM 421 SSP1MSK SSPMSK 424 SSP1ADD SSPADD 424 SSP1BUF SSPBUF 425 SSP1CLKPPS — — SSP1CLKPPS 199 SSP1DATPPS — — SSP1DATPPS 199 SSP1SSPPS — — SSP1SSPPS RxyPPS — — Legend: Note 1: — RxyPPS 199 200 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 module When using designated I2C pins, the associated pin values in INLVLx will be ignored.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 425 PIC16(L)F15325/45 33.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) • • • • • • • • • • Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes • Sleep operation The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. Note: The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 33-1 and Figure 33-2. Two identical EUSART modules are implemented on this device, EUSART1 and EUSART2. All references to EUSART1 apply to EUSART2 as well. FIGURE 33-1: The EUSART transmit output (TX_out) is available to the TX/CK pin and internally to the following peripherals: • Configurable Logic Cell (CLC) EUSART TRANSMIT BLOCK DIAGRAM Data Bus SYNC CSRC 8 TXEN LSb (8) 0 0 • • • TRMT Multiplier TX_out ÷n TX9 n BRG16 SPxBRGH SPxBRGL RX/DT pin PPS SYNC FOSC +1 Pin Buffer and Control Transmit Shift Register (TSR) CKPPS Note 1: RxyPPS(1) MSb 1 Baud Rate Generator Interrupt TXxIF TXxREG Register CK pin PPS TXxIE x4 x16 x64 TX9D SYNC 1 X 0 0 0 0 BRGH X 1 1 0 0 1 BRG16 X 1 0 1 0 PPS RxyPPS In Synchronous mode the DT output and RX input PPS selections should enable the same pin.  2016 Microchip Technology Inc. TX/CK pin Preliminary SYNC CSRC DS40001865B-page 426 PIC16(L)F15325/45 FIGURE 33-2: EUSART RECEIVE BLOCK DIAGRAM SPEN RX/DT pin CREN OERR RXPPS(1) RSR Register MSb Pin Buffer and Control PPS Baud Rate Generator Data Recovery FOSC +1 SPxBRGH SPxBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop (8) ••• 7 1 LSb 0 Start RX9 ÷n BRG16 n FERR RX9D RCxREG Register 8 Note 1: RCIDL In Synchronous mode the DT output and RX input PPS selections should enable the same pin. FIFO Data Bus RXxIF RXxIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXxSTA) • Receive Status and Control (RCxSTA) • Baud Rate Control (BAUDxCON) These registers are detailed in Register 33-1, Register 33-2 and Register 33-3, respectively. The RX input pin is selected with the RXPPS. The CK input is selected with the TXPPS register. TX, CK, and DT output pins are selected with each pin’s RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 427 PIC16(L)F15325/45 33.1 33.1.1.2 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 33-3 for examples of baud rate configurations. Transmitting Data A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 33.1.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 33.4.1.2 “Clock Polarity”. 33.1.1 33.1.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 33-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. 33.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXxSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXxIF interrupt flag bit of the PIR3 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution. Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software. The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIE3 register. However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit. To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. The TXxIF Transmitter Interrupt flag is set when the TXEN enable bit is set.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 428 PIC16(L)F15325/45 33.1.1.5 TSR Status 33.1.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 33.1.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 33.1.2.7 “Address Detection” for more information on the Address mode. FIGURE 33-3: Write to TXxREG BRG Output (Shift Clock) 6. 7. 8. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.3 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set. If interrupts are desired, set the TXxIE interrupt enable bit of the PIE3 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXxREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) 4. 5. Asynchronous Transmission Set-up: 1 TCY Word 1 Transmit Shift Reg.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 429 PIC16(L)F15325/45 FIGURE 33-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG BRG Output (Shift Clock) Word 1 TX/CK pin TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Start bit bit 0 1 TCY bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. EUSART ASYNCHRONOUS RECEIVER 33.1.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 33-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 33.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCxSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note: bit 1 Word 1 This timing diagram shows two consecutive transmissions. Note: 33.1.2 Word 2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 33.1.2.4 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RXxIF interrupt flag bit of the PIR3 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 33.1.2.5 “Receive Overrun Error” for more information on overrun errors. If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 430 PIC16(L)F15325/45 33.1.2.3 Receive Interrupts 33.1.2.6 The RXxIF interrupt flag bit of the PIR3 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RXxIF interrupt flag bit is read-only, it cannot be set or cleared by software. RXxIF interrupts are enabled by setting all of the following bits: • RXxIE, Interrupt Enable bit of the PIE3 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register 33.1.2.4 The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 33.1.2.7 The RXxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. Receiving 9-Bit Characters Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RXxIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 33.1.2.5 If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 431 PIC16(L)F15325/45 33.1.2.8 Asynchronous Reception Setup: 33.1.2.9 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RXxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RXxIE interrupt enable bit was also set. 8. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 33-5: This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RXxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RXxIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Setup Rcv Shift Reg Rcv Buffer Reg. RCIDL bit 1 bit 7/8 Stop bit Start bit bit 0 Word 1 RCxREG bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCxREG Read Rcv Buffer Reg. RCxREG RXxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 432 PIC16(L)F15325/45 33.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 9.2.2.2 “Internal Oscillator Frequency Adjustment” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 33.3.1 “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 433 PIC16(L)F15325/45 33.3 EXAMPLE 33-1: EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: FOSC Desired Baud Rate = -----------------------------------------------------------------------64  [SPBRGH:SPBRGL] + 1  Solving for SPxBRGH:SPxBRGL: The SPxBRGH, SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Table 33-1 contains the formulas for determining the baud rate. Example 33-1 provides a sample calculation for determining the baud rate and baud rate error. CALCULATING BAUD RATE ERROR F OS C --------------------------------------------Desired Baud Rate X = --------------------------------------------- – 1 64 16000000 -----------------------9600 = ------------------------ – 1 64 =  25.042  = 25 16000000 Calculated Baud Rate = --------------------------64  25 + 1  Typical baud rates and error values for various Asynchronous modes have been computed for your convenience and are shown in Table 33-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Calc. Baud Rate – Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate  9615 – 9600  = ---------------------------------- = 0.16% 9600 Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 434 PIC16(L)F15325/45 33.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 33-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH, SPxBRGL register pair, the ABDEN bit is automatically cleared and the RXxIF interrupt flag is set. The value in the RCxREG needs to be read to clear the RXxIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 33-1. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at FIGURE 33-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 33.3.3 “Auto-Wake-up on Break”). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. TABLE 33-1: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 1 FOSC/4 FOSC/32 Note: During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter, independent of the BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. RX pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RXxIF bit (Interrupt) Read RCxREG SPxBRGL XXh 1Ch SPxBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 435 PIC16(L)F15325/45 33.3.2 AUTO-BAUD OVERFLOW 33.3.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. The overflow condition will set the RXxIF flag. The counter continues to count until the fifth rising edge is detected on the RX pin. The RCIDL bit will remain false (‘0’) until the fifth rising edge at which time the RCIDL bit will be set. If the RCxREG is read after the overflow occurs but before the fifth rising edge then the fifth rising edge will set the RXxIF again. Terminating the auto-baud process early to clear an overflow condition will prevent proper detection of the sync character fifth rising edge. If any falling edges of the sync character have not yet occurred when the ABDEN bit is cleared then those will be falsely detected as Start bits. The following steps are recommended to clear the overflow condition: 1. 2. 3. Read RCxREG to clear RXxIF. If RCIDL is ‘0’ then wait for RDCIF and repeat step 1. Clear the ABDOVF bit. 33.3.3 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The wake-up event causes a receive interrupt by setting the RXxIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The EUSART module generates an RXxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 33-7), and asynchronously if the device is in Sleep mode (Figure 33-8). The interrupt condition is cleared by reading the RCxREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in IDLE mode waiting to receive the next character.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 436 PIC16(L)F15325/45 FIGURE 33-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RXxIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set. FIGURE 33-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RXxIF Sleep Command Executed Note 1: 2: 33.3.4 Cleared due to User Read of RCxREG Sleep Ends If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. BREAK CHARACTER SEQUENCE 33.3.4.1 Break and Sync Transmit Sequence The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all ‘0’s will be transmitted. 1. 2. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). 4. The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 33-9 for the timing of the Break character sequence. When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG.  2016 Microchip Technology Inc. 3. 5. Preliminary Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. DS40001865B-page 437 PIC16(L)F15325/45 33.3.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when: • RXxIF bit is set • FERR bit is set • RCxREG = 00h The second method uses the Auto-Wake-up feature described in Section 33.3.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RXxIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. FIGURE 33-9: Write to TXxREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit)  2016 Microchip Technology Inc. SENDB Sampled Here Preliminary Auto Cleared DS40001865B-page 438 PIC16(L)F15325/45 33.4 33.4.1.2 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 33.4.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART for synchronous master operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.  2016 Microchip Technology Inc. A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 33.4.1.3 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXxSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 33.4.1.1 Clock Polarity Note: The TSR register is not mapped in data memory, so it is not available to the user. 33.4.1.4 Synchronous Master Transmission Set-up: 1. 2. 3. 4. 5. 6. 7. 8. Preliminary Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 33.3 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXxREG register. DS40001865B-page 439 PIC16(L)F15325/45 FIGURE 33-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXxREG Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words. FIGURE 33-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXxREG reg TXxIF bit TRMT bit TXEN bit 33.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence.  2016 Microchip Technology Inc. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RXxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RXxIF bit remains set as long as there are unread characters in the receive FIFO. Note: Preliminary If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. DS40001865B-page 440 PIC16(L)F15325/45 33.4.1.6 Slave Clock received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: 33.4.1.7 33.4.1.9 1. Initialize the SPxBRGH, SPxBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RXxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RXxIE was set. 9. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 33.4.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character FIGURE 33-12: RX/DT pin Synchronous Master Reception Set-up: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RXxIF bit (Interrupt) Read RCxREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 441 PIC16(L)F15325/45 33.4.2 SYNCHRONOUS SLAVE MODE 33.4.2.1 The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 The operation of the Synchronous Master and Slave modes are identical (see Section 33.4.1.3 “Synchronous Master Transmission”), except in the case of the Sleep mode. If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 1. 2. 3. 4. 5. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXxREG register. The TXxIF bit will not be set. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXxIF bit will now be set. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. 33.4.2.2 1. 2. 3. 4. 5. 6. 7. 8.  2016 Microchip Technology Inc. EUSART Synchronous Slave Transmit Preliminary Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXxREG register. DS40001865B-page 442 PIC16(L)F15325/45 33.4.2.3 EUSART Synchronous Slave Reception 33.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 33.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RXxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9.  2016 Microchip Technology Inc. Preliminary Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RXxIF bit will be set when reception is complete. An interrupt will be generated if the RXxIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. DS40001865B-page 443 PIC16(L)F15325/45 33.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 33.5.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: • RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see Section 33.4.2.4 “Synchronous Slave Reception Set-up:”). • If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. • The RXxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RXxIF interrupt flag bit of the PIR3 register will be set. Thereby, waking the processor from Sleep. 33.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see Section 33.4.2.2 “Synchronous Slave Transmission Set-up:”). • The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and transmit buffer. • If interrupts are desired, set the TXxIE bit of the PIE3 register and the PEIE bit of the INTCON register. • Interrupt enable bits TXxIE of the PIE3 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another character for transmission, which will clear the TXxIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 444 PIC16(L)F15325/45 33.6 Register Definitions: EUSART Control REGISTER 33-1: R/W-/0 TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 CSRC TX9 R/W-0/0 TXEN (1) R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Unused in this mode – value ignored Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send SYNCH BREAK on next transmission – Start bit, followed by 12 ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = SYNCH BREAK transmission disabled or completed Synchronous mode: Unused in this mode – value ignored bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode – value ignored bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 445 PIC16(L)F15325/45 REGISTER 33-2: R/W-0/0 (1) SPEN RCxSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit(1) 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Unused in this mode – value ignored Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Unused in this mode – value ignored bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in the receive buffer is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Unused in this mode – value ignored bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCxREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Note 1: The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the associated TRIS bits for TX/CK and RX/DT to 1.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 446 PIC16(L)F15325/45 REGISTER 33-3: BAUDxCON: BAUD RATE CONTROL REGISTER R/W-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Clock/Transmit Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is a low level 0 = Idle state for transmit (TX) is a high level Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = USART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge. 0 = RX pin not monitored nor rising edge detected Synchronous mode: Unused in this mode – value ignored bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character – requires reception of a SYNCH field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode – value ignored  2016 Microchip Technology Inc. Preliminary DS40001865B-page 447 PIC16(L)F15325/45 RCxREG(1): RECEIVE DATA REGISTER REGISTER 33-4: R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RCxREG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: RCxREG: Lower eight bits of the received data; read-only; see also RX9D (Register 33-2) RCxREG (including the 9th bit) is double buffered, and data is available while new data is being received. TXxREG(1): TRANSMIT DATA REGISTER REGISTER 33-5: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXxREG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: TXxREG: Lower eight bits of the received data; read-only; see also RX9D (Register 33-1) TXxREG (including the 9th bit) is double buffered, and can be written when previous data has started shifting. SPxBRGL(1): BAUD RATE GENERATOR REGISTER REGISTER 33-6: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPxBRG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: SPxBRG: Lower eight bits of the Baud Rate Generator Writing to SP1BRG resets the BRG counter.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 448 PIC16(L)F15325/45 SPxBRGH(1, 2): BAUD RATE GENERATOR HIGH REGISTER REGISTER 33-7: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPxBRG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Note 1: 2: SPxBRG: Upper eight bits of the Baud Rate Generator SPxBRGH value is ignored for all modes unless BAUDxCON is active. Writing to SPxBRGH resets the BRG counter.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 449 PIC16(L)F15325/45 TABLE 33-2: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH EUSART Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE ― ― ― ― ― INTEDG 124 PIR3 RC2IF TX2IF RC1IF TX1IF ― ― BCL1IF SSP1IF 136 PIE3 RC2IE TX2IE RC1IE TX1IE ― ― BCL1IE SSP1IE 128 RCxSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 446 TXxSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 445 ABDOVF RCIDL ― SCKP BRG16 ― WUE ABDEN 447 BAUDxCON RCxREG EUSART Receive Data Register 448* TXxREG EUSART Transmit Data Register 448* SPxBRGL SPxBRG SPxBRGH 448* SPxBRG 449* RXPPS ― ― RXPPS 199 CKPPS ― ― CXPPS 199 RxyPPS ― ― CLCxSELy ― ― Legend: * ― RxyPPS LCxDyS 200 367 — = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART module. Page with register information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 450 PIC16(L)F15325/45 TABLE 33-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[16 (n+1)] FOSC/[4 (n+1)] x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair. TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1221 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k — -3.55 — 3 — — — — — — — 57.60k — 0.00 7 — 57.60k — 0.00 2 — — 115.2k Actual Rate % Error SPBRG value (decimal) Actual Rate — 1.73 — 255 % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) — 1200 — 0.00 — 239 — 1200 — 0.00 — 143 71 — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — 1202 — 0.16 — 103 300 1202 0.16 0.16 207 51 300 1200 0.00 191 47 300 1202 0.16 0.16 51 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — —  2016 Microchip Technology Inc. Actual Rate % Error SPBRG value (decimal) Actual Rate % Error 0.00 Preliminary SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) DS40001865B-page 451 PIC16(L)F15325/45 TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 207 300 — — — — — — — — — 300 0.16 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.02 6666 3332 300.0 1200 -0.01 -0.03 4166 1041 300.0 1200 0.00 0.00 3839 959 300.0 1200 0.00 0.00 2303 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 71 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5  2016 Microchip Technology Inc. Preliminary DS40001865B-page 452 PIC16(L)F15325/45 TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 207 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2016 Microchip Technology Inc. Preliminary DS40001865B-page 453 PIC16(L)F15325/45 34.0 REFERENCE CLOCK OUTPUT MODULE The reference clock output module provides the ability to send a clock signal to the clock reference output pin (CLKR). The reference clock output module has the following features: • Selectable input clock • Programmable clock divider • Selectable duty cycle 34.1 CLOCK SOURCE CLOCK SYNCHRONIZATION Once the reference clock enable (CLKREN) is set, the module is ensured to be glitch-free at start-up. When the reference clock output is disabled, the output signal will be disabled immediately. SELECTABLE DUTY CYCLE The CLKRDC bits of the CLKRCON register can be used to modify the duty cycle of the output clock. A duty cycle of 25%, 50%, or 75% can be selected for all clock rates, with the exception of the undivided base FOSC value. The duty cycle can be changed while the module is enabled; however, in order to prevent glitches on the output, the CLKRDC bits should only be changed when the module is disabled (CLKREN = 0). Note: The reference clock output module has a selectable clock source. The CLKRCLK register (Register 34-2) controls which input is used. 34.1.1 34.3 34.4 The CLKRDC1 bit is reset to ‘1’. This makes the default duty cycle 50% and not 0%. OPERATION IN SLEEP MODE The reference clock output module clock is based on the system clock. When the device goes to Sleep, the module outputs will remain in their current state. This will have a direct effect on peripherals using the reference clock output as an input signal. Clock dividers and clock duty cycles can be changed while the module is enabled, but glitches may occur on the output. To avoid possible glitches, clock dividers and clock duty cycles should be changed only when the CLKREN is clear. 34.2 PROGRAMMABLE CLOCK DIVIDER The module takes the system clock input and divides it based on the value of the CLKRDIV bits of the CLKRCON register (Register 34-1). The following configurations can be made based on the CLKRDIV bits: • • • • • • • • Base clock value Base clock value divided by 2 Base clock value divided by 4 Base clock value divided by 8 Base clock value divided by 16 Base clock value divided by 32 Base clock value divided by 64 Base clock value divided by 128 The clock divider values can be changed while the module is enabled; however, in order to prevent glitches on the output, the CLKRDIV bits should only be changed when the module is disabled (CLKREN = 0).  2016 Microchip Technology Inc. Preliminary DS40001865B-page 454 PIC16(L)F15325/45 FIGURE 34-1: CLOCK REFERENCE BLOCK DIAGRAM Rev. 10-000261A 9/10/2015 CLKRDIV Counter Reset Reference Clock Divider CLKREN See CLKRCLK Register D CLKREN CLKRCLK FREEZE ENABLED(1) ICD FREEZE MODE(1) FIGURE 34-2: Q 128 111 64 110 32 101 16 100 8 011 4 010 2 001 CLKRDC CLKR Duty Cycle PPS To Peripherals 000 EN CLOCK REFERENCE TIMING P2 P1 FOSC CLKREN CLKR Output CLKRDIV[2:0] = 001 CLKRDC[1:0] = 10 CLKR Output Duty Cycle (50%) FOSC / 2 CLKRDIV[2:0] = 001 CLKRDC[1:0] = 01 Duty Cycle (25%)  2016 Microchip Technology Inc. Preliminary DS40001865B-page 455 PIC16(L)F15325/45 REGISTER 34-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 U-0 U-0 CLKREN — — R/W-0/0 R/W-0/0 CLKRDC R/W-0/0 R/W-0/0 R/W-0/0 CLKRDIV bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference clock module enabled 0 = Reference clock module is disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4-3 CLKRDC: Reference Clock Duty Cycle bits (1) 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 CLKRDIV: Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2 000 = Base clock value Note 1: Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 456 PIC16(L)F15325/45 REGISTER 34-2: CLKRCLK: CLOCK REFERENCE CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CLKRCLK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CLKRCLK: CLKR Input bits Clock Selection 1111 = Reserved • • • 1011 = Reserved 1010 = LC4_out 1001 = LC3_out 1000 = LC2_out 0111 = LC1_out 0110 = NCO1_out 0101 = SOSC 0100 = MFINTOSC (31.25 kHz) 0011 = MFINTOSC (500 kHz) 0010 = LFINTOSC 0001 = HFINTOSC 0000 = FOSC TABLE 34-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT Bit 7 Bit 6 Bit 5 CLKRCON CLKREN — — CLKRCLK — — — CLCxSELy — — RxyPPS — — Legend: Bit 4 Bit 3 Bit 2 CLKRDC — Bit 1 CLKRDIV CLKRCLK LCxDyS — Bit 0 RxyPPS Register on Page 456 457 367 200 — = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 457 PIC16(L)F15325/45 35.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) 35.3 ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 35-1. FIGURE 35-1: VDD In Program/Verify mode the program memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16(L)F153XX Memory Programming Specification” (DS40001838). 35.1 The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR High-Voltage Programming Entry Mode Low-Voltage Programming Entry Mode ICD RJ-11 STYLE CONNECTOR INTERFACE VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 35.2 Common Programming Interfaces 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 35-2. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 35-3 for more information. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 8.5“MCLR” for more information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 458 PIC16(L)F15325/45 FIGURE 35-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Rev. 10-000128A 7/30/2013 Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No connect FIGURE 35-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING Rev. 10-000129A 7/30/2013 External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2016 Microchip Technology Inc. Preliminary DS40001865B-page 459 PIC16(L)F15325/45 36.0 INSTRUCTION SET SUMMARY 36.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 36-1: Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 36-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine entry takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Prepost increment-decrement mode selection TABLE 36-2: ABBREVIATION DESCRIPTIONS Field PC Program Counter TO Time-Out bit C DC Z PD  2016 Microchip Technology Inc. Description Preliminary Carry bit Digit Carry bit Zero bit Power-Down bit DS40001865B-page 460 PIC16(L)F15325/45 36.2 General Format for Instructions TABLE 36-3: INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF f, b f, b Bit Clear f Bit Set f BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 1, 2 1, 2 BIT-ORIENTED SKIP OPERATIONS 1 (2) 1 (2) 01 01 10bb bfff ffff 11bb bfff ffff 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 000 0001 0000 1100 1010 LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 2: Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W  2016 Microchip Technology Inc. Preliminary kkkk kkkk kkkk 0k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z DS40001865B-page 461 PIC16(L)F15325/45 TABLE 36-3: INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP RESET SLEEP TRIS – – – – f Clear Watchdog Timer No Operation Software device Reset Go into Standby or IDLE mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 0000 0000 0000 0000 0000 0110 0000 0000 0110 0110 0100 TO, PD 0000 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] Note 1: 2: 3: 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z 2, 3 1 1 11 00 1111 0nkk kkkk Z 0000 0001 1nmm 2 2, 3 1 11 1111 1nkk kkkk 2 If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Table in the MOVIW and MOVWI instruction descriptions.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 462 PIC16(L)F15325/45 36.3 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32  k  31 n  [ 0, 1] Operands: 0  k  255 Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f k FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0  k  255 Operation: Status Affected: Syntax: [ label ] ANDWF Operands: 0  f  127 d 0,1 (W) + k  (W) Operation: (W) .AND. (f)  (destination) C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0  f  127 d 0,1 Operation: (W) + (f)  (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC k f,d Syntax: [ label ] ASRF Operands: 0  f  127 d [0,1] Operation: (f) dest (f)  dest, (f)  C, [ label ] ADDWFC Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f C f {,d} Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2016 Microchip Technology Inc. f {,d} Status Affected: ADD W and CARRY bit to f Syntax: f,d Preliminary DS40001865B-page 463 PIC16(L)F15325/45 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0  f  127 0b7 Operands: 0  f  127 0b7 Operands: Operation: 0  (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: 0  f  127 0b VDD) ................................................................................................... 20 mA Total power dissipation(2)................................................................................................................................ 800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 37-6 to calculate device specifications. Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 473 PIC16(L)F15325/45 37.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF15325/45 VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +3.6V PIC16F15325/45 VDDMIN (Fosc  16 MHz) ......................................................................................................... +2.3V VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................... +85°C Extended Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................. +125°C Note 1: See Parameter Supply Voltage, DS Characteristics: Supply Voltage.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 474 PIC16(L)F15325/45 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F15325/45 ONLY FIGURE 37-1: VDD (V) 5.5 2.5 2.3 0 10 4 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies. VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16LF15325/45 ONLY VDD (V) FIGURE 37-2: 3.6 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 475 PIC16(L)F15325/45 37.3 DC Characteristics TABLE 37-1: SUPPLY VOLTAGE PIC16LF15325/45 Standard Operating Conditions (unless otherwise stated) PIC16F15325/45 Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions Supply Voltage D002 VDD 1.8 2.5 — — 3.6 3.6 V V FOSC  16 MHz FOSC  16 MHz D002 VDD 2.3 2.5 — — 5.5 5.5 V V FOSC  16 MHz FOSC 16 MHz RAM Data Retention(1) D003 VDR 1.5 — — V Device in Sleep mode D003 VDR 1.7 — — V Device in Sleep mode Power-on Reset Release Voltage(2) D004 VPOR — 1.6 — V BOR or LPBOR disabled(3) D004 VPOR — 1.6 — V BOR or LPBOR disabled(3) Power-on Reset Rearm Voltage(2) D005 VPORR — 0.8 — V BOR or LPBOR disabled(3) D005 VPORR — 1.5 — V BOR or LPBOR disabled(3) VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3) D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3) † Note 1: 2: 3: 4: Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. See Figure 37-3, POR and POR REARM with Slow Rising VDD. See Table 37-11 for BOR and LPBOR trip point information. = F device  2016 Microchip Technology Inc. Preliminary DS40001865B-page 476 PIC16(L)F15325/45 FIGURE 37-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) Note 1: 2: 3: TPOR(2) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 477 PIC16(L)F15325/45 TABLE 37-2: SUPPLY CURRENT (IDD)(1,2,4) Standard Operating Conditions (unless otherwise stated) PIC16LF15325/45 PIC16F15325/45 Param. No. Conditions Symbol Device Characteristics Min. Typ.† Max. Units VDD D100 IDDXT4 XT = 4 MHz — 360 400 A 3.0V D100 IDDXT4 XT = 4 MHz — 380 450 A 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz — 1.4 1.8 mA 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz — 1.5 1.9 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.3 3.2 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.4 3.2 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.3 3.2 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.4 3.2 mA 3.0V D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.05 1.5 mA 3.0V D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.15 1.5 mA 3.0V D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.1 — mA 3.0V D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.2 — mA 3.0V † Note 1: 2: 3: 4: 5: Note Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 11-2). PMD bits are all in the default state, no modules are disabled. = F device  2016 Microchip Technology Inc. Preliminary DS40001865B-page 478 PIC16(L)F15325/45 TABLE 37-3: POWER-DOWN CURRENT (IPD)(1,2) PIC16LF15325/45 Standard Operating Conditions (unless otherwise stated) PIC16F15325/45 Standard Operating Conditions (unless otherwise stated) VREGPM = 1 Param. No. Symbol Device Characteristics Conditions Min. Typ.† Max. +85°C Max. +125°C Units 2 9 A 3.0V 3.0V VDD D200 IPD IPD Base — 0.06 D200 D200A IPD IPD Base — 0.4 4 12 — 18 22 27 D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — 0.8 4.0 11.5 A A A D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — 0.9 5.0 13 A 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.6 5 13 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.8 8.5 15 D203 IPD_FVR FVR — 33 47 47 D203 IPD_FVR FVR — 28 44 44 D204 IPD_BOR Brown-out Reset (BOR) — 10 17 19 D204 IPD_BOR Brown-out Reset (BOR) — 14 18 20 D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.5 4 10 D207 IPD_ADCA ADC - Active — 250 — — D207 IPD_ADCA ADC - Active — 280 — — D208 IPD_CMP Comparator — 30 42 44 D208 IPD_CMP Comparator — 33 44 45 A A A A A A A A A A A † Note 1: 2: 3: 4: 5: 3.0V Note VREGPM = 0 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V ADC is converting (4) 3.0V ADC is converting (4) 3.0V 3.0V Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. ADC clock source is FRC. = F device  2016 Microchip Technology Inc. Preliminary DS40001865B-page 479 PIC16(L)F15325/45 TABLE 37-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ† Max. Units — — Conditions — 0.8 V 4.5V  VDD  5.5V — 0.15 VDD V 1.8V  VDD  4.5V 2.0V  VDD  5.5V Input Low Voltage I/O PORT: D300 with TTL buffer D301 D302 with Schmitt Trigger buffer — — 0.2 VDD V D303 with I2C levels — — 0.3 VDD V with SMBus levels — — 0.8 V — — 0.2 VDD V D304 D305 MCLR VIH 2.7V  VDD  5.5V Input High Voltage I/O PORT: D320 with TTL buffer D321 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V 2.0V  VDD  5.5V D322 with Schmitt Trigger buffer 0.8 VDD — — V D323 with I2C levels 0.7 VDD — — V D324 with SMBus levels D325 MCLR IIL D340 D341 MCLR(2) IPUR Weak Pull-up Current VOL Output Low Voltage D350 D360 I/O ports VOH D370 CIO — V — — V — ±5 ± 125 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C — ±5 ± 1000 nA VSS  VPIN  VDD, Pin at high-impedance, 125°C — ± 50 ± 200 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C 25 120 200 A VDD = 3.0V, VPIN = VSS — — 0.6 V IOL = 10.0mA, VDD = 3.0V VDD - 0.7 — — V IOH = 6.0 mA, VDD = 3.0V — 5 50 pF Output High Voltage I/O ports D380 — Input Leakage Current(1) I/O Ports D342 2.7V  VDD  5.5V 2.1 0.7 VDD All I/O pins † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 480 PIC16(L)F15325/45 TABLE 37-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Voltage on MCLR/VPP pin to enter programming mode 8 — 9 V Current on MCLR/VPP pin during programming mode — 1 — mA Conditions High Voltage Entry Programming Mode Specifications MEM01 VIHH MEM02 IPPGM (Note 2, Note 3) (Note 2) Programming Mode Specifications MEM10 VBE VDD for Bulk Erase — 2.7 — V MEM11 IDDPGM Supply Current during Programming operation — — 10 mA Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance 10k — — E/W -40C  TA  +85C (Note 1) MEM32 TP_RET Characteristic Retention — 40 — Year Provided no other specifications are violated MEM33 VP_RD VDD for Read operation VDDMIN — VDDMAX V MEM34 VP_REW VDD for Row Erase or Write operation VDDMIN — VDDMAX V MEM35 TP_REW Self-Timed Row Erase or Self-Timed Write — 2.0 2.5 ms † Note 1: 2: 3: Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. Required only if CONFIG4, bit LVP is disabled. The MPLAB® ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between the ICD2 and target system when programming or debugging with the ICD2.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 481 PIC16(L)F15325/45 TABLE 37-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 70 C/W 95.3C C/W 14-pin SOIC package 100.0 C/W 14-pin TSSOP package 51.5 C/W 16-pin UQFN 4x4mm package 62.2 C/W 20-pin PDIP package 87.3 C/W 20-pin SSOP package 77.7 C/W 20-pin SOIC package 20-pin UQFN 4x4mm package 14-pin SPDIP package 43.0 C/W 32.75 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 24.4 C/W 14-pin TSSOP package 5.4 C/W 16-pin UQFN 4x4mm package 27.5 C/W 20-pin PDIP package 31.1 C/W 20-pin SSOP package 23.1 C/W 20-pin SOIC package 5.3 C/W 20-pin UQFN 4x4mm package 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature  2016 Microchip Technology Inc. Preliminary DS40001865B-page 482 PIC16(L)F15325/45 37.4 AC Characteristics FIGURE 37-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins  2016 Microchip Technology Inc. Preliminary DS40001865B-page 483 PIC16(L)F15325/45 FIGURE 37-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS2 OS1 OS2 OS20 CLKOUT (CLKOUT Mode) Note See Table 37-7. 1: TABLE 37-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency — — 500 kHz OS2 TECL_DC Clock Duty Cycle 40 — 60 % ECM Oscillator OS3 FECM Clock Frequency — — 4 MHz OS4 TECM_DC Clock Duty Cycle 40 — 60 % ECH Oscillator OS5 FECH Clock Frequency — — 32 MHz OS6 TECH_DC Clock Duty Cycle 40 — 60 % Clock Frequency — — 100 kHz Note 4 Clock Frequency — — 4 MHz Note 4 Clock Frequency — — 20 MHz Note 4 (Note 2, Note 3) LP Oscillator OS7 FLP XT Oscillator OS8 FXT HS Oscillator OS9 FHS System Oscillator OS20 FOSC System Clock Frequency — — 32 MHz OS21 FCY Instruction Frequency — FOSC/4 — MHz OS22 TCY Instruction Period 125 1/FCY — ns * † Note 1: 2: 3: 4: These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 9.0 “Oscillator Module (with Fail-Safe Clock Monitor)”. The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 “Standard Operating Conditions”. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 484 PIC16(L)F15325/45 INTERNAL OSCILLATOR PARAMETERS(1) TABLE 37-8: Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions OS50 FHFOSC Precision Calibrated HFINTOSC Frequency — 4 8 12 16 32 — MHz (Note 2) OS51 FHFOSCLP Low-Power Optimized HFINTOSC Frequency — — 1 2 — — MHz MHz OS52 FMFOSC Internal Calibrated MFINTOSC Frequency — 500 — kHz OS53* FLFOSC Internal LFINTOSC Frequency — 31 — kHz OS54* THFOSCST HFINTOSC Wake-up from Sleep Start-up Time — — 11 50 20 — s s OS56 TLFOSCST — 0.2 — ms LFINTOSC Wake-up from Sleep Start-up Time VREGPM = 0 VREGPM = 1 * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature. FIGURE 37-6: PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 0 ± 5% -40 1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2016 Microchip Technology Inc. Preliminary DS40001865B-page 485 PIC16(L)F15325/45 TABLE 37-9: PLL SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD 2.5V Param. No. Sym. Characteristic PLL Input Frequency Range PLL01 FPLLIN PLL02 FPLLOUT PLL Output Frequency Range PLL03 TPLLST PLL Lock Time from Start-up PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) Min. Typ† Max. Units Conditions 4 — 8 MHz 16 — 32 MHz Note 1 — 200 — s -0.25 — 0.25 % * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 486 PIC16(L)F15325/45 FIGURE 37-7: CLKOUT AND I/O TIMING Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 CLKOUT IO8, IO9 IO6, IO7 IO5 IO4 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO6, IO7, IO8, IO9 TABLE 37-10: I/O AND CLKOUT TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. IO1* Sym. Characteristic Min. Conditions IO7* CLKOUT rising edge delay (rising edge Fosc (Q1 cycle) to falling edge CLKOUT TCLKOUTL CLKOUT falling edge delay (rising edge Fosc (Q3 cycle) to rising edge CLKOUT Port output valid time (rising edge TIO_VALID Fosc (Q1 cycle) to port valid) Port input setup time (Setup time TIO_SETUP before rising edge Fosc – Q2 cycle) Port input hold time (Hold time after TIO_HOLD rising edge Fosc – Q2 cycle) TIOR_SLREN Port I/O rise time, slew rate enabled TIOR_SLRDIS Port I/O rise time, slew rate disabled IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD = 3.0V IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD = 3.0V IO10* TINT 25 — — ns IO11* TIOC 25 — — ns IO2* IO3* IO4* IO5* IO6* TCLKOUTH Typ† Max. Units INT pin high or low time to trigger an interrupt Interrupt-on-Change minimum high or low time to trigger interrupt *These parameters are characterized but not tested.  2016 Microchip Technology Inc. Preliminary — — 70 ns — — 72 ns — 50 70 ns 20 — — ns 50 — — ns — 25 — ns VDD = 3.0V — 5 — ns VDD = 3.0V DS40001865B-page 487 PIC16(L)F15325/45 FIGURE 37-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST03 RST02 RST02 I/O pins Note 1: Asserted low. FIGURE 37-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) (RST08)(1) Reset (RST04)(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 488 PIC16(L)F15325/45 TABLE 37-11: RESET, WDT, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units RST01* TMCLR MCLR Pulse Width Low to ensure Reset 2 — — s RST02* TIOZ I/O high-impedance from Reset detection — — 2 s RST03 TWDT Watchdog Timer Time-out Period — 16 — ms RST04* TPWRT Power-up Timer Period — 65 — ms RST05 TOST Oscillator Start-up Timer Period(1,2) RST06 VBOR Brown-out Reset Voltage(4) RST07 VBORHYS RST08 TBORDC RST09 VLPBOR — 1024 — TOSC 2.55 2.30 1.80 2.70 2.45 1.90 2.85 2.60 2.05 V V V Brown-out Reset Hysteresis — 40 — mV Brown-out Reset Response Time — 3 — s Low-Power Brown-out Reset Voltage 1.8 1.9 2.2 V Conditions 16 ms Nominal Reset Time BORV = 0 BORV = 1 (F devices) BORV = 1 (LF devices) LF Devices Only * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. TABLE 37-12: ANALOG-TO-DIGITAL CONVERTER (ADC) ACCURACY SPECIFICATIONS(1,2): Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. AD01 Sym. Characteristic Min. Typ† Max. Units bit NR Resolution — — 10 Conditions AD02 EIL Integral Error — ±0.1 ±1.0 AD03 EDL Differential Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V LSb ADCREF+ = 3.0V, ADCREF-= 0V AD04 EOFF Offset Error — 0.5 2.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V AD05 EGN Gain Error — ±0.2 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V AD06 VADREF ADC Reference Voltage (ADREF+ - ADREF-) 1.8 — VDD V AD07 VAIN Full-Scale Range ADREF- — ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source — 10 — k AD09 RVREF ADC Voltage Reference Ladder Impedance — 50 — k Note 3 * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors. 2: The ADC conversion result never decreases with an increase in the input and has no missing codes. 3: This is the impedance seen by the VREF pads when the external reference pads are selected.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 489 PIC16(L)F15325/45 TABLE 37-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. AD20 TAD Characteristic Min. Typ† Max. Units 1 — 9 s The requirement is to set ADCCS correctly to produce this period/frequency. 1 2 6 s Using FRC as the ADC clock source ADOSC = 1 Set of GO/DONE bit to Clear of GO/DONE bit ADC Clock Period AD21 AD22 TCNV Conversion Time — 11 — TAD AD23 TACQ Acquisition Time — 2 — s AD24 THCD Sample and Hold Capacitor Disconnect Time — — — s * † Conditions FOSC-based clock source FRC-based clock source These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) FIGURE 37-10: BSF ADCON0, GO AD24 1 TCY AD22 Q4 9 ADC Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD23 FIGURE 37-11: ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC) BSF ADCON0, GO AD24 1 TCY AD22 Q4 AD20 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 TCY ADIF GO Sample 3 DONE AD23  2016 Microchip Technology Inc. Sampling Stopped Preliminary DS40001865B-page 490 PIC16(L)F15325/45 TABLE 37-14: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. CM01 Sym. VIOFF Characteristics Input Offset Voltage Min. Typ. Max. Units — — ±50 mV CM02 VICM Input Common Mode Range GND — VDD V CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB Comments VICM = VDD/2 CM04 VHYST Comparator Hysteresis 15 25 35 mV CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns Response Time, Falling Edge — 220 500 ns CMOS6 TMCV2VO(2) Mode Change to Valid Output — — 10 µs * Note 1: 2: These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. A mode change includes changing any of the control register values, including module enable. TABLE 37-15: 5-BIT DAC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristics Min. Typ. Max. Units — (VDACREF+ -VDACREF-) /32 — V LSb DSB01 VLSB Step Size DSB01 VACC Absolute Accuracy — —  0.5 DSB03* RUNIT Unit Resistor Value — 5000 —  DSB04* TST Settling Time(1) — — 10 s * † Note 1: Comments These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Settling time measured while DACR transitions from ‘00000’ to ‘01111’. TABLE 37-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions FVR01 VFVR1 1x Gain (1.024V) -4 — +4 % VDD  2.5V, -40°C to 85°C FVR02 VFVR2 2x Gain (2.048V) -4 — +4 % VDD  2.5V, -40°C to 85°C FVR03 VFVR4 4x Gain (4.096V) -5 — +5 % VDD  4.75V, -40°C to 85°C FVR04 TFVRST FVR Start-up Time — 25 — us FVR05 FVRA1X/FVRC1X FVR output voltage for 1x setting stored in the DIA — 1024 — mV FVR06 FVRA2X/FVRC2X FVR output voltage for 2x setting stored in the DIA — 2048 — mV FVR07 FVRA4X/FVRC4X FVR output voltage for 4x setting stored in the DIA — 4096 — mV  2016 Microchip Technology Inc. Preliminary DS40001865B-page 491 PIC16(L)F15325/45 TABLE 37-17: ZERO CROSS DETECT (ZCD) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristics Min. Typ† Max. Units — 0.75 — V ZC01 VPINZC Voltage on Zero Cross Pin ZC02 IZCD_MAX Maximum source or sink current — — 600 A ZC03 TRESPH Response Time, Rising Edge — 1 — s TRESPL Response Time, Falling Edge — 1 — s † Comments Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 37-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1  2016 Microchip Technology Inc. Preliminary DS40001865B-page 492 PIC16(L)F15325/45 TABLE 37-18: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler Max. Units 0.5 TCY + 20 — — ns 10 — — ns With Prescaler 41* Typ† 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler 0.5 TCY + 20 — — ns 15 — — ns Asynchronous 30 — — ns Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Greater of: 30 or TCY + 40 N — — ns TT1L 46* T1CKI Low Time 47* TT1P T1CKI Input Synchronous Period 48 FT1 Secondary Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * † 60 — — ns 32.4 32.768 33.1 kHz 2 TOSC — 7 TOSC — Conditions N = prescale value N = prescale value Timers in Sync mode These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 493 PIC16(L)F15325/45 FIGURE 37-13: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 37-4 for load conditions. TABLE 37-19: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param. Sym. No. Characteristic CC01* TccL CCPx Input Low Time No Prescaler CC02* TccH CCPx Input High Time No Prescaler CC03* TccP CCPx Input Period With Prescaler With Prescaler * † Min. Typ† Max. Units 0.5TCY + 20 — — ns 20 — — ns 0.5TCY + 20 — — ns 20 — — ns 3TCY + 40 N — — ns Conditions N = prescale value These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 494 PIC16(L)F15325/45 FIGURE 37-14: CLC PROPAGATION TIMING Rev. 10-000031A 6/16/2016 CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC01 Note 1: CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC02 CLC03 See Figure 31-1 to identify specific CLC signals. TABLE 37-20: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions CLC01* TCLCIN CLC input time — 7 IO5 ns (Note 1) CLC02* TCLC CLC module input to output propagation time — — 24 12 — — ns ns VDD = 1.8V VDD > 3.6V — IO7 — — (Note 1) — IO8 — — (Note 1) — 32 FOSC MHz CLC03* TCLCOUT CLC output time Rise Time Fall Time CLC04* FCLCMAX CLC maximum switching frequency * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Table 37-10 for IO5, IO7 and IO8 rise and fall times.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 495 PIC16(L)F15325/45 FIGURE 37-15: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Refer to Figure 37-4 for load conditions. Note: TABLE 37-21: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. US120 Symbol TCKH2DTV Characteristic Min. Max. Units Conditions 3.0V  VDD  5.5V SYNC XMIT (Master and Slave) Clock high to data-out valid — 80 ns — 100 ns 1.8V  VDD  5.5V 45 ns 3.0V  VDD  5.5V US121 TCKRF Clock out rise time and fall time (Master mode) — — 50 ns 1.8V  VDD  5.5V US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V — 50 ns 1.8V  VDD  5.5V FIGURE 37-16: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 37-4 for load conditions. TABLE 37-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol US125 TDTV2CKL US126 TCKL2DTL Characteristic Min. Max. Units SYNC RCV (Master and Slave) Data-setup before CK  (DT hold time) 10 — ns Data-hold after CK  (DT hold time) 15 — ns  2016 Microchip Technology Inc. Preliminary Conditions DS40001865B-page 496 PIC16(L)F15325/45 FIGURE 37-17: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 37-4 for load conditions. FIGURE 37-18: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 MSb SDO SP78 bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 37-4 for load conditions.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 497 PIC16(L)F15325/45 FIGURE 37-19: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 37-4 for load conditions. FIGURE 37-20: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 37-4 for load conditions.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 498 PIC16(L)F15325/45 TABLE 37-23: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. SP70* Symbol Characteristic TSSL2SCH, TSSL2SCL SS to SCK or SCK input Min. Typ† Max. Units 2.25*TCY — — ns Conditions SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 — — ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 — — ns SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  VDD  5.5V — 25 50 ns 1.8V  VDD  5.5V SDO data output fall time — 10 25 ns SP76* TDOF SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) — 10 25 ns 3.0V  VDD  5.5V — 25 50 ns 1.8V  VDD  5.5V 25 ns SP79* TSCF SCK output fall time (Master mode) — 10 SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge — — 50 ns 3.0V  VDD  5.5V — — 145 ns 1.8V  VDD  5.5V SP81* TDOV2SCH, TDOV2SCL SDO data output setup to SCK edge 1 Tcy — — ns SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns SP83* TSCH2SSH, TSCL2SSH SS after SCK edge 1.5 TCY + 40 — — ns * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 499 PIC16(L)F15325/45 FIGURE 37-21: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 37-4 for load conditions. TABLE 37-24: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. SP90* Symbol TSU:STA THD:STA SP91* TSU:STO SP92* THD:STO SP93 * Characteristic Min. Typ Max. Units Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Start condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — Stop condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — ns ns These parameters are characterized but not tested. FIGURE 37-22: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 37-4 for load conditions.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 500 PIC16(L)F15325/45 TABLE 37-25: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. SP100* Symbol THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns — 250 ns 20 + 0.1CB 250 ns SSP module SP102* SP103* TR TF SDA and SCL rise time SDA and SCL fall time 100 kHz mode 400 kHz mode SP106* SP107* SP109* SP110* THD:DAT TSU:DAT TAA TBUF Data input hold time Data input setup time Output valid from clock Bus free time Bus capacitive loading Conditions 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 100 kHz mode 250 — ns 400 kHz mode 100 — ns 100 kHz mode — 3500 ns 400 kHz mode — — ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start SP111 CB * Note 1: These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 2:  2016 Microchip Technology Inc. Preliminary DS40001865B-page 501 PIC16(L)F15325/45 38.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range. Charts and graphs are not available at this time.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 502 PIC16(L)F15325/45 39.0 DEVELOPMENT SUPPORT 39.1 The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software - MPLAB® XPRESS IDE Software • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2016 Microchip Technology Inc. Preliminary DS40001865B-page 503 PIC16(L)F15325/45 39.2 MPLAB XC Compilers 39.4 The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 39.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 39.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2016 Microchip Technology Inc. Preliminary DS40001865B-page 504 PIC16(L)F15325/45 39.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 39.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables.  2016 Microchip Technology Inc. 39.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 39.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 39.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. Preliminary DS40001865B-page 505 PIC16(L)F15325/45 39.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 39.12 Third-Party Development Tools A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 506 PIC16(L)F15325/45 40.0 PACKAGING INFORMATION 40.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC16F15325 /SO e3 1525017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX YYWW NNN 16F15325 1525 e3 017 14-Lead SOIC (3.90 mm) Example PIC16F15325 /SO e3 1525017 Legend: XX...X Y YY WW NNN * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 507 PIC16(L)F15325/45 40.1 Package Marking Information (Continued) 16-Lead UQFN (4x4x0.5 mm) PIN 1 Example PIN 1 PIC16 F15325 /MV 525017 e3 Legend: XX...X Y YY WW NNN * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 508 PIC16(L)F15325/45 40.1 Package Marking Information (Continued) 20-Lead PDIP (300 mil) Example PIC16F15345 /P e3 1525017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP (5.30 mm) Example PIC16F15345 /SO e3 1525017 20-Lead SOIC (7.50 mm) Example PIC16F15325 /SO e3 1525017 Legend: XX...X Y YY WW NNN * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 509 PIC16(L)F15325/45 40.1 Package Marking Information (Continued) 20-Lead UQFN (4x4x0.5 mm) PIN 1 Example PIN 1 PIC16 F15345 /MV 525017 e3 Legend: XX...X Y YY WW NNN * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 510 PIC16(L)F15325/45 The following sections give the technical details of the packages.                ! J '*"' # '  K$ 5"+ ""'    K  & ' '$' '' HVV555*    *V  K N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB X'" *"\*'" Y#*/ &" Y7[; Y Y Y] ^  '    ''  _ _  $$ K K""  B 9 B G"''  B _ _ #$ '#$ `$' ;  9 9B $$ K`$' ;  B j ]! \'  9B B B  '' \ B 9 B \$ K"" j  B / B {  /  j  G _ _ X  \$`$' \5 \$`$' ]! 5  6 G7 9  !  !"#$%&'# *! +/#'*#"'/ '$5''' $   6& '7  ' "'  9 *""$;$' #$*$&"  ' #""$&"  ' #"""'% $?  "$  *"$'    ;@B G7HG" *" ' % '!#"55'#''  "       5 7BG  2016 Microchip Technology Inc. Preliminary DS40001865B-page 511 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 512 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 513 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 514 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 515 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 516 PIC16(L)F15325/45  ! J '*"' # '  K$ 5"+ ""'    K  & ' '$' '' HVV555*    *V  K  2016 Microchip Technology Inc. Preliminary DS40001865B-page 517 PIC16(L)F15325/45 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C SEATING PLANE A1 0.10 C C A 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N 16X b 0.10 L e C A B BOTTOM VIEW Microchip Technology Drawing C04-257A Sheet 1 of 2  2016 Microchip Technology Inc. Preliminary DS40001865B-page 518 PIC16(L)F15325/45 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.50 2.50 0.25 0.30 0.20 MILLIMETERS NOM 16 0.65 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.60 4.00 BSC 2.60 0.30 0.40 - MAX 0.55 0.05 2.70 2.70 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-257A Sheet 2 of 2  2016 Microchip Technology Inc. Preliminary DS40001865B-page 519 PIC16(L)F15325/45 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 16 1 2 C2 Y2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X16) X1 Contact Pad Length (X16) Y1 MIN MILLIMETERS NOM 0.65 BSC MAX 2.70 2.70 4.00 4.00 0.35 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2257A  2016 Microchip Technology Inc. Preliminary DS40001865B-page 520 PIC16(L)F15325/45 "               ! J '*"' # '  K$ 5"+ ""'    K  & ' '$' '' HVV555*    *V  K  N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e X'" *"\*'" Y#*/ &" Y7[; Y Y Y] ^  '    ''  _ _  $$ K K""  B 9 B G"''  B _ _ #$ '#$ `$' ; 9 9 9B $$ K`$' ;  B j ]! \'  j 9 {  '' \ B 9 B \$ K"" j  B / B {  /  j  G _ _ X  \$`$' \5 \$`$' ]! 5  6 G7 9  !  !"#$%&'# *! +/#'*#"'/ '$5''' $   6& '7  ' "'  9 *""$;$' #$*$&"  ' #""$&"  ' #"""'% $?  "$  *"$'    ;@B G7H G" *" ' % '!#"55'#''  "       5 7G  2016 Microchip Technology Inc. Preliminary DS40001865B-page 521 PIC16(L)F15325/45 "   #$%& # '  ##  *+   ##'   ! J '*"' # '  K$ 5"+ ""'    K  & ' '$' '' HVV555*    *V  K D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 X'" *"\*'" Y#*/ &" L \\;; Y Y Y] ^  '   ]! ['  _ {BG7 _  $$ K K""  {B B jB '$&&  B _ _ ]! `$' ;  j j $$ K`$' ; B B9 B{ ]! \'  {  B J'\' \ BB B B J' ' \ B;J \$ K""  _ J'    B j \$`$' /  _ 9j  !  !"#$%&'# *! +/#'*#"'/ '$5''' $   *""$;$' #$*$&"  ' #""$&"  ' #"""'% $**  "$ 9 *"$'    ;@B G7H G" *" ' % '!#"55'#''  " ;JH &  *"+#"#5'#''  +& & *' # ""       5 7G  2016 Microchip Technology Inc. Preliminary DS40001865B-page 522 PIC16(L)F15325/45 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.65 0.45 SILK SCREEN c Y1 G X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.65 BSC 7.20 MAX 0.45 1.75 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2072B  2016 Microchip Technology Inc. Preliminary DS40001865B-page 523 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 524 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 525 PIC16(L)F15325/45 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016 Microchip Technology Inc. Preliminary DS40001865B-page 526 PIC16(L)F15325/45 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C SEATING PLANE A1 0.10 C C A 20X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 L 0.10 C A B E2 2 K 1 NOTE 1 N 20X b 0.10 e C A B BOTTOM VIEW Microchip Technology Drawing C04-255A Sheet 1 of 2  2016 Microchip Technology Inc. Preliminary DS40001865B-page 527 PIC16(L)F15325/45 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width Overall Length D D2 Exposed Pad Length Terminal Width b Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.60 2.60 0.20 0.30 0.20 MILLIMETERS NOM 20 0.50 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.70 4.00 BSC 2.70 0.25 0.40 - MAX 0.55 0.05 2.80 2.80 0.30 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-255A Sheet 2 of 2  2016 Microchip Technology Inc. Preliminary DS40001865B-page 528 PIC16(L)F15325/45 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 20 1 2 C2 Y2 G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 MIN MILLIMETERS NOM 0.50 BSC MAX 2.80 2.80 4.00 4.00 0.30 0.80 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2255A  2016 Microchip Technology Inc. Preliminary DS40001865B-page 529 PIC16(L)F15325/45 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (11/2016) Initial release of the document. Revision B (12/2016) Updates to Section 2.2.1, Figure 2-1, Figure 3-1, Table 6-1, Section 9.0, Section 10.2, Section 17.0, Registers 9-6, 9-7, 10-13, 18-1, Tables 37-2, 37-11; Updated 37.0 Electrical Specifications.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 530 PIC16(L)F15325/45 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2016 Microchip Technology Inc. Preliminary DS40001865B-page 531 PIC16(L)F15325/45 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Device: PIC16F15325, PIC16LF15325 PIC16F15345, PIC16LF15345 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) JQ P SL SO SS ST GZ = = = = = = = Pattern: a) PIC16F15325- E/SP Extended temperature SPDIP package (Industrial) (Extended) 16-lead, 20-lead UQFN 4x4x0.5mm 14-lead, 20-lead PDIP 14-lead SOIC 20-lead SOIC 20-lead SSOP 14-lead TSSOP 20-lead UQFN QTP, SQTP, Code or Special Requirements (blank otherwise)  2016 Microchip Technology Inc. Examples: Preliminary Note 1: 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. DS40001865B-page 532 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-1220-5 == ISO/TS 16949 ==  2016 Microchip Technology Inc. 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