PIC16(L)F15356/75/76/85/86
Full-Featured 28/40/44/48-Pin Microcontrollers
Description
PIC16(L)F15356/75/76/85/86 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power
applications.
The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory
Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information
Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.
Core Features
Power-Saving Functionality
• C Compiler Optimized RISC Architecture
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Timers:
- 8-bit Timer2 with Hardware Limit Timer (HLT)
- 16-bit Timer0/1
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
• Programmable Code Protection
• DOZE mode: Ability to Run the CPU Core Slower
than the System Clock
• IDLE mode: Ability to halt CPU Core while Internal
Peripherals Continue Operating
• SLEEP mode: Lowest Power Consumption
• Peripheral Module Disable (PMD):
- Ability to disable hardware module to
minimize active power consumption of
unused peripherals
Memory
•
•
•
•
Up to 28 KB Flash Program Memory
Up to 2 Bytes Data SRAM
Direct, Indirect and Relative Addressing modes
Memory Access Partition (MAP):
- Write protect
- Customizable Partition
• Device Information Area (DIA)
• Device Configuration Information (DCI)
• High-Endurance Flash (HEF)
- Last 128 words of Program Flash Memory
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF15356/75/76/85/86)
- 2.3V to 5.5V (PIC16F15356/75/76/85/86)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
2016-2018 Microchip Technology Inc.
eXtreme Low-Power (XLP) Features
•
•
•
•
Sleep mode: 50 nA @ 1.8V, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
- 8 A @ 32 kHz, 1.8V, typical
- 32 A/MHz @ 1.8V, typical
Digital Peripherals
• Four Configurable Logic Cells (CLC):
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Two Capture/Compare/PWM (CCP) module:
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• Four 10-Bit PWMs
• Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control and
increased frequency resolution
- Input Clock: 0 Hz < FNCO < 32 MHz
- Resolution: FNCO/220
• Two EUSART, RS-232, RS-485, LIN compatible
• Two SPI
• Two I2C, SMBus, PMBus™ compatible
DS40001866B-page 1
PIC16(L)F15356/75/76/85/86
Digital Peripherals (Cont.)
Flexible Oscillator Structure
• I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• High-Precision Internal Oscillator:
- Software selectable frequency range up to 32
MHz, ±1% typical
• x2/x4 PLL with Internal and External Sources
• Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
• External Oscillator Block with:
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 32 MHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if primary clock
stops
• Oscillator Start-up Timer (OST):
- Ensures stability of crystal oscillator
resources
Analog Peripherals
• Analog-to-Digital Converter (ADC):
- 10-bit with up to 43 external channels
- Operates in Sleep
• Two Comparators:
- FVR, DAC and external input pin available on
inverting and noninverting input
- Software selectable hysteresis
- Outputs available internally to other modules,
or externally through PPS
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
• Zero-Cross Detect module:
- AC high voltage zero-crossing detection for
simplifying TRIAC control
- Synchronized switching control and timing
2016-2018 Microchip Technology Inc.
DS40001866B-page 2
PIC16(L)F15356/75/76/85/86
5-bit DAC
Comparator
8-bit/ (with HLT) Timer
16-bit Timer
Window Watchdog Timer
CCP/10-bit PWM
CWG
NCO
CLC
Memory Access Partition
Device Information Area
Peripheral Pin Select
Peripheral Module Disable
Debug (1)
5
1
1
1
2
Y
2/4
1
1
4 Y Y
Y
Y 1/1
Y
Y
I
PIC16(L)F15323 (C)
2
3.5 224 256
12
11
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 1/1
Y
Y
I
PIC16(L)F15324 (D)
4
7
12
11
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15325 (B)
8
14 224 1024 12
11
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15344 (D)
4
7
18
17
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15345 (B)
8
14 224 1024 18
17
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15354 (A)
4
7
25
24
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15355 (A)
8
14 224 1024 25
24
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15356 (E) 16
28 224 2048 25
24
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15375 (E)
14 224 1024 36
35
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15376 (E) 16
28 224 2048 36
35
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15385 (E)
8
14 224 1024 44
43
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15386 (E) 16
28 224 2048 44
43
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
Note 1:
8
224 512
224 512
224 512
EUSART/ I2C-SPI
10-bit ADC
6
Zero-Cross Detect
Temperature Indicator
I/OPins
3.5 224 256
Data SRAM
(bytes)
2
Storage Area Flash (B)
PIC16(L)F15313 (C)
Device
Program Flash Memory (KB)
Program Flash Memory (KW)
PIC16(L)F153XX FAMILY TYPES
Data Sheet Index
TABLE 1:
I - Debugging integrated on chip.
Data Sheet Index:
A: DS40001853
PIC16(L)F15354/5 Data Sheet, 28-Pin
B:
DS40001865
PIC16(L)F15325/45 Data Sheet, 14/20-Pin
C:
DS40001897
PIC16(L)F15313/23 Data Sheet, 8/14-Pin
D:
DS40001889
PIC16(L)F15324/44 Data Sheet, 14/20-Pin
E:
DS40001866
PIC16(L)F15356/75/76/85/86 Data Sheet, 28/40/48-Pin
Note:
For other small form-factor package availability and marking information, visit www.microchip.com/
packaging or contact your local sales office.
2016-2018 Microchip Technology Inc.
DS40001866B-page 3
PIC16(L)F15356/75/76/85/86
TABLE 2:
PACKAGES
Device
PIC16(L)F15356
PIC16(L)F15375
PIC16(L)F15376
(S)PDIP
SOIC
SSOP
PIC16(L)F15385
PIC16(L)F15386
2016-2018 Microchip Technology Inc.
TQFP
(7x7)
TQFP
(10x10)
QFN
(8x8)
QFN
(6x6)
UQFN
(4x4)
UQFN
(5x5)
UQFN
(6x6)
DS40001866B-page 4
PIC16(L)F15356/75/76/85/86
PIN DIAGRAMS
28-PIN PDIP, SOIC, SSOP
2:
40-PIN PDIP
Note:
28
RB7/ICSPDAT
2
27
RB6/ICSPCLK
RA1
3
26
RB5
RA2
4
25
RB4
RA3
5
RB3
RA4
6
24
23
RA5
VSS
7
22
21
RB1
RB0
RA7
9
20
VDD
19
VSS
8
PIC16(L)F15356
1
RA0
RB2
RA6
10
RC0
11
18
RC7
RC1
12
17
RC6
RC2
13
16
RC5
RC3
14
15
RC4
See Table 3 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level.
VPP/MCLR/RE3
1
40
RB7/ICSPDAT
RA0
2
39
RB6/ICSPCLK
RA1
3
38
RB5
RA2
4
37
RB4
RA3
5
36
RB3
RA4
6
35
RB2
RA5
RE0
7
34
8
33
RB1
RB0
RE1
9
32
VDD
RE2
10
31
VSS
VDD
11
30
RD7
29
RD6
28
RD5
PIC16(L)F15375
PIC16(L)F15376
Note 1:
VPP/MCLR/RE3
VSS
12
RA7
13
RA6
14
27
RD4
RC0
15
26
RC7
RC1
16
25
RC6
RC2
24
23
RC5
RC3
17
18
RD0
19
22
RC4
RD3
RD1
20
21
RD2
See Table 4 for location of all peripheral functions.
2016-2018 Microchip Technology Inc.
DS40001866B-page 5
PIC16(L)F15356/75/76/85/86
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28
27
26
25
24
23
22
RA1
RA0
RE3/MCLR/VPP
28-PIN UQFN (4x4), UQFN (6x6)
RA2
RA3
RA4
RA5
VSS
RA7
RA6
1
2
3
4
5
6
7
Note 1:
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC1
RC2
RC3
RC4
RC5
RC6
RC0
8
9
10
11
12
13
14
PIC16(L)F15356
21
20
19
18
17
16
15
See Table 3 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3:
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
2:
40
39
38
37
36
35
34
33
32
31
40-PIN UQFN (5x5)
1
2
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
3
4
5
6
7
8
9
10
PIC16(L)F15375
PIC16(L)F15376
30
29
28
27
26
25
24
23
22
21
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RB3
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
11
12
13
14
15
16
17
18
19
20
RC7
RD4
Note 1:
2:
See Table 4 for the pin allocation tables.
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
2016-2018 Microchip Technology Inc.
DS40001866B-page 6
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
PIC16(L)F15356/75/76/85/86
44
43
42
41
40
39
38
37
36
35
34
44-PIN TQFP (10x10)
12
13
14
15
16
17
18
19
20
21
22
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality.
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
44-PIN QFN (8x8x0.9)
1
2
3
4
5
6
7
8
9
10
11
PIC16(L)F15375
PIC16(L)F15376
33
32
31
30
29
28
27
26
25
24
23
RA6
RA7
NC
VSS
NC
VDD
RE2
RE1
RE0
RA5
RA4
RB3
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
RC7
RD4
RD5
RD6
RD7
VSS
VDD
NC
RB0
RB1
RB2
44
43
42
41
40
39
38
37
36
35
34
2:
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
See Table 4 for location of all peripheral functions.
12
13
14
15
16
17
18
19
20
21
22
Note 1:
33
32
31
30
29
28
27
26
25
24
23
PIC16(L)F15375
PIC16(L)F15376
NC
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
1
2
3
4
5
6
7
8
9
10
11
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
AN0/RA0
RA1
RA2
RA3
RC7
RD4
Note 1:
2:
3:
See Table 4 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to fl
may result in degraded electrical performance or non-functionality.
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
2016-2018 Microchip Technology Inc.
DS40001866B-page 7
PIC16(L)F15356/75/76/85/86
RF1
RF2
RF3
RC2
RC3
RD0
RD1
RD2
RD3
RC4
RC5
RC6
48-PIN UQFN (6x6)
48 47 46 45 44 43 42 41 40 39 38 37
RC7
1
36
RF0
RD4
2
35
RC1
RD5
3
34
RC0
RD6
4
33
RA6
32
RA7
RD7
5
VSS
6
31
VSS
VDD
7
30
VDD
RB0
8
29
RE2
RB1
9
28
RE1
RB2
10
27
RE0
RB3
11
26
RA5
RF4
12
25
RA4
PIC16(L)F15385
PIC16(L)F15386
RA3
RA2
RA1
RA0
VPP/MCLR/RE3
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
RF7
RF6
RF5
13 14 15 16 17 18 19 20 21 22 23 24
Note 1: See Table 5 for location of all peripheral functions.
RD3
RD2
RD1
RD0
RC3
RC2
RF3
RF2
RF1
45
44
43
42
41
40
39
38
37
PIC16(L)F15385
PIC16(L)F15386
36
35
34
33
32
31
30
29
28
27
26
25
RF0
RC1
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RF5
RF6
RF7
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
13
14
15
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
RF4
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
RC7
RD4
RC6
RC5
RC4
48-PIN TQFP (7x7)
48
47
46
2: The bottom pad of the QFN/UQFN package should be connected to Vss as the circuit board level.
Note:
See Table 5 for location of all peripheral functions.
2016-2018 Microchip Technology Inc.
DS40001866B-page 8
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0
2
27
ANA0
―
C1IN0C2IN0-
―
―
―
―
―
―
―
―
―
CLCIN0(1)
―
IOCA0
Y
―
RA1
3
28
ANA1
―
C1IN1C2IN1-
―
―
―
―
―
―
―
―
―
CLCIN1(1)
―
IOCA1
Y
―
RA2
4
1
ANA2
—
C1IN0+
C2IN0+
―
DAC1OUT1
―
―
―
―
―
―
―
―
―
IOCA2
Y
―
RA3
5
2
ANA3
VREF+
C1IN1+
―
DAC1REF+
―
―
―
―
―
―
―
―
―
IOCA3
Y
―
RA4
6
3
ANA4
―
―
―
―
T0CKI
―
―
―
―
―
―
―
―
IOCA4
Y
―
RA5
7
4
ANA5
―
―
―
―
—
―
―
―
SS1(1)
―
―
―
―
IOCA5
Y
―
RA6
10
7
ANA6
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA6
Y
CLKOUT
OSC2
RA7
9
6
ANA7
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA7
Y
CLKIN
OSC1
RB0
21
18
ANB0
―
C2IN1+
―
―
―
―
―
CWG1IN(1)
SS2(1)
ZCD1
―
―
―
INT(1)
IOCB0
Y
―
RB1
22
19
ANB1
―
C1IN3C2IN3-
―
―
―
―
―
―
SCK2,
SCL2(1,4)
―
―
―
―
IOCB1
Y
―
RB2
23
20
ANB2
―
―
―
―
―
―
―
―
SDA2,
SDI2(1,4)
―
―
―
―
IOCB2
Y
―
RB3
24
21
ANB3
―
C1IN2C2IN2-
―
―
―
―
―
―
―
―
―
―
―
IOCB3
Y
―
RB4
25
22
ANB4
ADACT(1)
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCB4
Y
―
―
―
―
―
―
―
―
―
IOCB5
Y
―
CLCIN2(1)
―
IOCB6
Y
ICSPCLK
CLCIN3(1)
―
IOCB7
Y
ICSPDAT
RB5
26
23
ANB5
―
―
―
―
(1)
T1G
DS40001866B-page 9
RB6
27
24
ANB6
―
―
―
―
―
―
―
―
―
―
TX2
CK2(1)
RB7
28
25
ANB7
―
―
―
DAC1OUT2
―
―
―
―
―
―
RX2
DT2(1)
Note
1:
2:
3:
4:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBus input buffer thresholds.
PIC16(L)F15356/75/76/85/86
28-Pin UQFN
28-PIN ALLOCATION TABLE (PIC16(L)F15356)
28-Pin PDIP/SOIC/SSOP
TABLE 3:
I/O(2)
2016-2018 Microchip Technology Inc.
PIN ALLOCATION TABLES
Basic
CCP1(1)
Pull-up
CCP2(1)
―
Interrupt
SOSCI
CLKR
―
CLC
―
―
EUSART
―
ZCD
―
―
MSSP
―
―
SOSCO
T1CKI
CWG
―
ANC2
―
PWM
ANC1
―
CCP
―
Timers
10
―
DAC
9
13
ANC0
NCO
12
Comparator
8
Reference
RC2
11
ADC
RC1
28-Pin UQFN
RC0
28-PIN ALLOCATION TABLE (PIC16(L)F15356) (CONTINUED)
28-Pin PDIP/SOIC/SSOP
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 3:
―
―
―
―
―
―
―
IOCC0
Y
―
―
―
―
―
―
―
―
IOCC1
Y
―
―
―
―
―
―
―
―
IOCC2
Y
―
―
―
―
―
IOCC3
Y
―
―
―
―
IOCC4
Y
―
14
11
ANC3
―
―
―
―
T2IN(1)
―
―
―
RC4
15
12
ANC4
―
―
―
―
―
―
―
―
SDA1,
SDI1(1,4)
―
RC5
16
13
ANC5
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCC5
Y
―
―
―
IOCC6
Y
―
RC6
17
14
ANC6
―
―
―
―
―
―
―
―
―
―
TX1
CK1(1)
RC7
18
15
ANC7
―
―
―
―
―
―
―
―
―
―
RX1
DT1(1)
―
―
IOCC7
Y
―
RE3
1
26
—
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCE3
Y
MCLR
VPP
VDD
20
17
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VDD
VSS
8
16
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
VSS
19
5
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
SDO1/2
―
DT(1,2)
CLC1OUT
CLKR
―
―
―
OUT(2)
Note
DS40001866B-page 10
1:
2:
3:
4:
―
―
―
―
C1OUT
NCO1OUT
―
TMR0
CCP1
PWM3OUT
CWG1A
CWG2A
―
―
―
―
C2OUT
―
―
―
CCP2
PWM4OUT
CWG1B
CWG2B
SCK1/2
―
CK(1,2)
CLC2OUT
―
―
―
―
―
―
―
―
―
―
―
―
―
PWM5OUT
CWG1C
CWG2C
SCL1(3,4)
SCL2(3,4)
―
TX(1,2)
CLC3OUT
―
―
―
―
―
―
―
―
―
―
―
―
―
PWM6OUT
CWG1D
CWG2D
SDA1(3,4)
SDA2(3,4)
―
―
CLC4OUT
―
―
―
―
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBus input buffer thresholds.
PIC16(L)F15356/75/76/85/86
RC3
SCL1,
SCK1(1,4)
40-Pin UQFN
44-Pin QFN
44-Pin TQFP
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
2
17
19
19
ANA0
―
C1IN0C2IN0-
―
―
―
―
―
―
―
―
―
CLCIN0(1)
―
IOCA0
Y
―
RA1
3
18
20
20
ANA1
―
C1IN1C2IN1-
―
―
―
―
―
―
―
―
―
CLCIN1(1)
―
IOCA1
Y
―
RA2
4
19
21
21
ANA2
―
C1IN0+
C2IN0+
―
DAC1OUT1
―
―
―
―
―
―
―
―
―
IOCA2
Y
―
RA3
5
20
22
22
ANA3
VREF+
C1IN1+
―
DACREF+
―
―
―
―
―
―
―
―
―
IOCA3
Y
―
RA4
6
21
23
23
ANA4
―
―
―
―
T0CKI(1)
―
―
―
―
―
―
―
―
IOCA4
Y
―
RA5
7
22
24
24
ANA5
―
―
―
―
T1G(1)
―
―
―
SS1(1)
―
―
―
―
IOCA5
Y
―
RA6
14
29
33
31
ANA6
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA6
Y
CLKOUT/
OSC1
RA7
13
28
32
30
ANA7
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA7
Y
CLKIN/
OSC2
RB0
33
8
9
8
ANB0
―
C2IN1+
―
―
―
―
―
CWG1(1)
SS2(1)
ZCD1
―
―
―
INT(1)
IOCB0
Y
―
RB1
34
9
10
9
ANB1
―
C1IN3C2IN3-
―
―
―
―
―
―
SCL1
SCK1(1,4)
―
―
―
―
IOCB1
Y
―
RB2
35
10
11
10
ANB2
―
―
―
―
―
―
―
―
SDA1
SDI1(1,4)
―
―
―
―
IOCB2
Y
―
RB3
36
11
12
11
ANB3
―
C1IN2C2IN2-
―
―
―
―
―
―
―
―
―
―
―
IOCB3
Y
―
RB4
37
12
14
14
ANB4
ADACT
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCB4
Y
―
(1)
DS40001866B-page 11
RB5
38
13
15
15
ANB5
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCB5
Y
―
RB6
39
14
16
16
ANB6
―
―
―
―
―
―
―
―
―
―
TX2
CK2(1)
CLCIN2(1)
―
IOCB6
Y
ICSPCLK
RB7
40
15
17
17
ANB7
―
―
―
DAC1OUT2
―
―
―
―
―
―
RX2
DT2(1)
CLCIN3(1)
―
IOCB7
Y
ICSPDAT
RC0
15
30
34
32
ANC0
―
―
―
―
SOSCO
T1CKI(1)
―
―
―
―
―
―
―
―
IOCC0
Y
―
RC1
16
31
35
35
ANC1
―
―
―
―
SOSCI
CCP2(1)
―
―
―
―
―
―
―
IOCC1
Y
―
RC2
17
32
36
36
ANC2
―
―
―
―
―
CCP1(1)
―
―
―
―
―
―
―
IOCC2
Y
―
Note
1:
2:
3:
4:
This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBUS input buffer thresholds.
PIC16(L)F15356/75/76/85/86
40-Pin PDIP
40/44-PIN ALLOCATION TABLE (PIC16(L)F15375, PIC16(L)F15376)
RA0
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 4:
40-Pin UQFN
44-Pin QFN
44-Pin TQFP
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RC3
18
33
37
37
ANC3
―
―
―
―
T2IN(1)
―
―
―
SCL1
SCK1(1,4)
―
―
―
―
IOCC3
Y
―
RC4
23
38
42
42
ANC4
―
―
―
―
―
―
―
―
SDA1
SDI1(1,4)
―
―
―
―
IOCC4
Y
―
RC5
24
39
43
43
ANC5
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCC5
Y
―
RC6
25
40
44
44
ANC6
―
―
―
―
―
―
―
―
―
―
TX1
CK1(1)
―
―
IOCC6
Y
―
RC7
26
1
1
1
ANC7
―
―
―
―
―
―
―
―
―
―
RX1
DT1(1)
―
―
IOCC7
Y
―
RD0
19
34
38
38
AND0
―
―
―
―
―
―
―
―
SCK2,
SCL2(1,4)
―
―
―
―
―
―
―
RD1
20
35
39
39
AND1
―
―
―
―
―
―
―
―
SDA2,
SDI2(1,4)
―
―
―
―
―
―
―
RD2
21
36
40
40
AND2
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RD3
22
37
41
41
AND3
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RD4
27
2
2
2
AND4
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RD5
28
3
3
3
AND5
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RD6
29
4
4
4
AND6
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RD7
30
5
5
5
AND7
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RE0
8
23
25
25
ANE0
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RE1
9
24
26
26
ANE1
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RE2
10
25
27
27
ANE2
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
RE3
1
16
18
18
―
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCE3
Y
MCLR
VPP
VDD
11
26
7
7
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VDD
VDD
32
7
28
28
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VDD
VSS
12
27
6
6
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
VSS
31
6
30
29
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
Note
DS40001866B-page 12
1:
2:
3:
4:
This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBUS input buffer thresholds.
PIC16(L)F15356/75/76/85/86
40-Pin PDIP
40/44-PIN ALLOCATION TABLE (PIC16(L)F15375, PIC16(L)F15376) (CONTINUED)
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 4:
40-Pin PDIP
40-Pin UQFN
44-Pin QFN
44-Pin TQFP
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
40/44-PIN ALLOCATION TABLE (PIC16(L)F15375, PIC16(L)F15376) (CONTINUED)
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 4:
OUT(2)
―
―
―
―
―
―
C1OUT
NCO1OUT
―
TMR0
CCP1
PWM3OUT
CWG1A
CWG2A
SDO1
SDO2
―
DT(3)
CLC1OUT
CLKR
―
―
―
―
―
―
―
―
―
C2OUT
―
―
―
CCP2
PWM4OUT
CWG1B
CWG2B
SCK1
SCK2
―
CK1
CK2
CLC2OUT
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
PWM5OUT
CWG1C
CWG2C
SCL1(3,4)
SCL2(3,4)
―
TX1
TX2
CLC3OUT
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
PWM6OUT
CWG1D
CWG2D
SDA1(3,4)
SDA2(3,4)
―
―
CLC4OUT
―
―
―
―
Note
1:
2:
3:
4:
DS40001866B-page 13
PIC16(L)F15356/75/76/85/86
This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBUS input buffer thresholds.
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
21
ANA0
―
C1IN0C2IN0-
―
―
―
―
―
―
―
―
―
CLCIN0(1)
―
IOCA0
Y
―
RA1
22
ANA1
―
C1IN1C2IN1-
―
―
―
―
―
―
―
―
―
CLCIN1(1)
―
IOCA1
Y
―
RA2
23
ANA2
―
C1IN0+
C2IN0+
―
DAC1OUT1
―
―
―
―
―
―
―
―
―
IOCA2
Y
―
RA3
24
ANA3
VREF+
C1IN1+
―
DACREF+
―
―
―
―
―
―
―
―
―
IOCA3
Y
―
RA4
25
ANA4
―
C1IN1-
―
―
T0CKI(1)
―
―
―
―
―
―
―
―
IOCA4
Y
―
RA5
26
ANA5
ADACT
―
―
―
―
T1G(1)
―
―
―
SS1(1)
―
―
―
―
IOCA5
Y
―
RA6
33
ANA6
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA6
Y
CLKOUT/
OSC1
RA7
32
ANA7
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA7
Y
CLKIN/
OSC2
RB0
8
ANB0
―
C2IN1+
―
―
―
―
―
CWG1(1)
SS2(1)
ZCD1
―
―
―
INT(1)
IOCB0
Y
―
RB1
9
ANB1
―
C1IN3C2IN3-
―
―
―
―
―
―
SCL1
SCK1(1,4)
―
―
―
―
IOCB1
Y
―
RB2
10
ANB2
―
―
―
―
―
―
―
―
SDA1
SDI1(1,4)
―
―
―
―
IOCB2
Y
―
RB3
11
ANB3
―
C1IN2C2IN2-
―
―
―
―
―
―
―
―
―
―
―
IOCB3
Y
―
RB4
16
ANB4
ADACT(1)
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCB4
Y
―
RB5
17
ANB5
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCB5
Y
―
RB6
18
ANB6
―
―
―
―
―
―
―
―
―
―
TX2
CK2(1)
CLCIN2(1)
―
IOCB6
Y
ICSPCLK
RB7
19
ANB7
―
―
―
DAC1OUT2
―
―
―
―
―
―
RX2
DT2(1)
CLCIN3(1)
―
IOCB7
Y
ICSPDAT
RC0
34
ANC0
―
―
―
―
SOSCO
T1CKI(1)
―
―
―
―
―
―
―
―
IOCC0
Y
―
RC1
35
ANC1
―
―
―
―
SOSCI
CCP2(1)
―
―
―
―
―
―
―
IOCC1
Y
―
Note
1:
2:
3:
4:
This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBUS input buffer thresholds.
PIC16(L)F15356/75/76/85/86
DS40001866B-page 14
48-Pin UQFN/TQFP
48-PIN ALLOCATION TABLE (PIC16(L)F15385, PIC16(L)F15386)
RA0
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 5:
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RC2
40
ANC2
―
―
―
―
―
CCP1(1)
―
―
―
―
―
―
―
IOCC2
Y
―
41
ANC3
―
―
―
―
T2IN(1)
―
―
―
SCL1
SCL2(1,4)
―
―
―
―
IOCC3
Y
―
RC4
46
ANC4
―
―
―
―
―
―
―
―
SDA1
SDI1(1,4)
―
―
―
―
IOCC4
Y
―
RC5
47
ANC5
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCC5
Y
―
RC6
48
ANC6
―
―
―
―
―
―
―
―
―
―
TX1
CK1(1)
―
―
IOCC6
Y
―
RC7
1
ANC7
―
―
―
―
―
―
―
―
―
―
RX1
DT1(1)
―
―
IOCC7
Y
―
RD0
42
AND0
―
―
―
―
―
―
―
―
SCK2
SCL2(1,4)
―
―
―
―
―
Y
―
RD1
43
AND1
―
―
―
―
―
―
―
―
SDA2
SDI2(1,4)
―
―
―
―
―
Y
―
RD2
44
AND2
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RD3
45
AND3
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RD4
2
AND4
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RD5
3
AND5
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RD6
4
AND6
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RD7
5
AND7
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RE0
27
ANE0
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RE1
28
ANE1
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RE2
29
ANE2
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RE3
20
―
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCE3
Y
MCLR
VPP
DS40001866B-page 15
RF0
36
ANF0
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RF1
37
ANF1
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RF2
38
ANF2
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RF3
39
ANF3
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
RF4
12
ANF4
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
Note
1:
2:
3:
4:
This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBUS input buffer thresholds.
PIC16(L)F15356/75/76/85/86
ADC
48-Pin UQFN/TQFP
48-PIN ALLOCATION TABLE (PIC16(L)F15385, PIC16(L)F15386) (CONTINUED)
RC3
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 5:
Pull-up
―
―
―
Y
―
―
―
―
―
Y
―
RF7
15
ANF7
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
―
VDD
30
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
Y
VDD
VDD
7
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VDD
VSS
6
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
VSS
31
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
OUT(2)
―
―
―
C1OUT
NCO1OUT
―
TMR0
CCP1
PWM3OUT
CWG1A
CWG2A
SDO1
SDO2
―
DT(3)
CLC1OUT
CLKR
―
―
―
―
―
―
C2OUT
―
―
―
CCP2
PWM4OUT
CWG1B
CWG2B
SCK1
SCK2
―
CK1
CK2
CLC2OUT
―
―
―
―
―
―
―
―
―
―
―
―
PWM5OUT
CWG1C
CWG2C
SCK1(3,4)
SCL2(3,4)
―
TX1
TX2
CLC3OUT
―
―
―
―
―
―
―
―
―
―
―
―
PWM6OUT
CWG1D
CWG2D
SDA1(3,4)
SDA2(3,4)
―
―
CLC4OUT
―
―
―
―
1:
2:
3:
4:
This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBUS input buffer thresholds.
DS40001866B-page 16
PIC16(L)F15356/75/76/85/86
Note
Basic
Interrupt
―
―
CLKR
―
―
CLC
―
―
EUSART
―
―
ZCD
―
―
MSSP
―
―
CWG
―
―
PWM
―
―
CCP
―
―
Timers
―
―
DAC
―
ANF6
NCO
ANF5
14
Comparator
ADC
13
RF6
Reference
48-Pin UQFN/TQFP
48-PIN ALLOCATION TABLE (PIC16(L)F15385, PIC16(L)F15386) (CONTINUED)
RF5
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 5:
PIC16(L)F15356/75/76/85/86
Table of Contents
1.0 Device Overview ........................................................................................................................................................................... 19
2.0 Guidelines for Getting Started with PIC16(L)F15354/55 Microcontrollers .................................................................................... 43
3.0 Enhanced Mid-Range CPU........................................................................................................................................................... 46
4.0 Memory Organization .................................................................................................................................................................... 48
5.0 Device Configuration ................................................................................................................................................................... 101
6.0 Device Information Area ............................................................................................................................................................. 112
7.0 Device Configuration Information ................................................................................................................................................ 114
8.0 Resets ......................................................................................................................................................................................... 115
9.0 Oscillator Module (with Fail-Safe Clock Monitor) ........................................................................................................................ 126
10.0 Interrupts ................................................................................................................................................................................... 143
11.0 Power-Saving Operation Modes ............................................................................................................................................... 165
12.0 Windowed Watchdog Timer (WWDT) ....................................................................................................................................... 172
13.0 Nonvolatile Memory (NVM) Control .......................................................................................................................................... 180
14.0 /O Ports ..................................................................................................................................................................................... 198
15.0 Peripheral Pin Select (PPS) Module ......................................................................................................................................... 233
16.0 Peripheral Module Disable ........................................................................................................................................................ 246
17.0 Interrupt-On-Change ................................................................................................................................................................. 254
18.0 Fixed Voltage Reference (FVR) ................................................................................................................................................ 264
19.0 Temperature Indicator Module .................................................................................................................................................. 267
20.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 269
21.0 5-Bit Digital-to-Analog Converter (DAC1) Module ..................................................................................................................... 285
22.0 Numerically Controlled Oscillator (NCO) Module ...................................................................................................................... 290
23.0 Comparator Module .................................................................................................................................................................. 300
24.0 Zero-Cross Detection (ZCD) Module ........................................................................................................................................ 310
25.0 Timer0 Module .......................................................................................................................................................................... 316
26.0 Timer1 Module with Gate Control ............................................................................................................................................. 322
27.0 Timer2 Module With Hardware Limit Timer (HLT) .................................................................................................................... 336
28.0 Capture/Compare/PWM Modules ............................................................................................................................................. 357
29.0 Pulse-Width Modulation (PWM) ................................................................................................................................................ 368
30.0 Complementary Waveform Generator (CWG) Module ............................................................................................................. 375
31.0 Configurable Logic Cell (CLC) .................................................................................................................................................. 400
32.0 Master Synchronous Serial Port (MSSPx) Modules ................................................................................................................. 417
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ................................................................ 468
34.0 Reference Clock Output Module ............................................................................................................................................... 496
35.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 500
36.0 Instruction Set Summary........................................................................................................................................................... 502
37.0 Electrical Specifications ............................................................................................................................................................ 515
38.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 544
39.0 Development Support ............................................................................................................................................................... 564
40.0 Packaging Information .............................................................................................................................................................. 568
2016-2018 Microchip Technology Inc.
DS40001866B-page 17
PIC16(L)F15356/75/76/85/86
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2016-2018 Microchip Technology Inc.
DS40001866B-page 18
PIC16(L)F15356/75/76/85/86
DEVICE OVERVIEW
The PIC16(L)F15356/75/76/85/86 are described within
this data sheet. The PIC16(L)F15356/75/76/85/86
devices are available in 28/40/44/48-pin SPDIP, SSOP,
SOIC, TQFP, QFN and UQFN packages. Figure 1-1,
Figure 1-2 and Figure 1-3 shows the block diagrams of
the PIC16(L)F15356/75/76/85/86 devices. Table 1-2
through Table 1-4 shows the pinout descriptions.
TABLE 1-1:
DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F15356/75/76/85/86
1.0
Analog-to-Digital Converter
●
Digital-to-Analog Converter (DAC1)
●
Fixed Voltage Reference (FVR)
●
Numerically Controlled Oscillator (NCO1)
●
Temperature Indicator Module (TIM)
●
Zero-Cross Detect (ZCD1)
●
Reference Table 1-1 for peripherals available per device.
Capture/Compare/PWM Modules (CCP)
CCP1
●
CCP2
●
C1
●
C2
●
CLC1
●
CLC2
●
CLC3
●
CLC4
●
CWG1
●
EUSART1
●
EUSART2
●
MSSP1
●
MSSP2
●
PWM3
●
PWM4
●
PWM5
●
PWM6
●
Timer0
●
Timer1
●
Timer2
●
Comparator Module (Cx)
Configurable Logic Cell (CLC)
Complementary Waveform Generator (CWG)
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
Master Synchronous Serial Ports (MSSP)
Pulse-Width Modulator (PWM)
Timers
2016-2018 Microchip Technology Inc.
DS40001866B-page 19
PIC16(L)F15356/75/76/85/86
1.1
1.1.1
Register and Bit Naming
Conventions
REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance, and control identifier.
The control registers section will show just one
instance of all the register names with an ‘x’ in the place
of the peripheral instance number. This naming
convention may also be applied to peripherals when
there is only one instance of that peripheral in the
device to maintain compatibility with other devices in
the family that contain more than one.
1.1.2
BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.1.2.1
Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.1.2.2
Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
2016-2018 Microchip Technology Inc.
1.1.2.3
Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW
ANDWF
MOVLW
IORWF
~(1 VIH
0 = Port pin is < VIL
Note 1:
Present on PIC16(L)F15375/76/85/86 only.
REGISTER 14-34: TRISE: PORTE TRI-STATE REGISTER
U-0
U-0
—
U-0
—
—
U-0
U-1
R/W-1/1
R/W-1/1
R/W-1/1
—
—(2)
TRISE2(1)
TRISE1(1)
TRISE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
Unimplemented: Read as ‘1’
bit 2-0
Unimplemented: Read as ‘0’
bit 2-0
TRISA: PORTA Tri-State Control bit(1)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1:
2:
Present on PIC16(L)F15375/76/85/86 only.
Unimplemented, read as ‘1’.
2016-2018 Microchip Technology Inc.
DS40001866B-page 223
PIC16(L)F15356/75/76/85/86
REGISTER 14-35: LATE: PORTE DATA LATCH REGISTER(1)
U-0
U-0
U-0
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
—
—
—
—
—
LATE2
LATE1
LATE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
LATE: PORTE Output Latch Value bits
Note 1:
2:
Present on PIC16(L)F15375/76/85/86 only.
Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is
return of actual I/O pin values.
REGISTER 14-36: ANSELE: PORTE ANALOG SELECT REGISTER(1)
U-0
U-0
U-0
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
—
—
—
—
—
ANSE2
ANSE1
ANSE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
ANSE: Analog Select between Analog or Digital Function on Pins RE, respectively(2)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(2). Digital input buffer disabled.
Note 1:
2:
Present on PIC16(L)F15375/76/85/86 only.
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2016-2018 Microchip Technology Inc.
DS40001866B-page 224
PIC16(L)F15356/75/76/85/86
REGISTER 14-37: WPUE: WEAK PULL-UP PORTE REGISTER
U-0
U-0
—
U-0
—
—
U-0
—
R/W-1/1
WPUE3
(2)
R/W-1/1
(1)
WPUE2
R/W-1/1
(1)
WPUE1
bit 7
R/W-1/1
WPUE0(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
WPUE: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1:
2:
3:
Present on PIC16(L)F15375/76/85/86 only.
If MCLRE = 1, the weak pull-up in RE3 is always enabled; bit WPUE3 is not affected.
The weak pull-up device is automatically disabled if the pin is configured as an output.
REGISTER 14-38: ODCONE: PORTE OPEN-DRAIN CONTROL REGISTER(1)
U-0
U-0
—
U-0
—
—
U-0
—
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
ODCE2
ODCE1
ODCE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
ODCE: PORTE Open-Drain Enable bits
For RE pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
Note 1:
Present on PIC16(L)F15375/76/85/86 only.
REGISTER 14-39: SLRCONE: PORTE SLEW RATE CONTROL REGISTER(1)
U-0
U-0
U-0
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
—
—
—
—
—
SLRE2
SLRE1
SLRE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
2016-2018 Microchip Technology Inc.
DS40001866B-page 225
PIC16(L)F15356/75/76/85/86
REGISTER 14-39: SLRCONE: PORTE SLEW RATE CONTROL REGISTER(1) (CONTINUED)
bit 2-0
Note 1:
SLRE: PORTE Slew Rate Enable bits
For RE pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
Present on PIC16(L)F15375/76/85/86 only.
REGISTER 14-40: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER
U-0
U-0
—
U-0
—
—
U-0
—
R/W-1/1
R/W-1/1
INLVLE3
INLVLE2(1)
R/W-1/1
(1)
INLVLE1
bit 7
R/W-1/1
INLVLE0(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
INLVLE: PORTE Input Level Select bits
For RE pins,
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change
Note 1:
Present on PIC16(L)F15375/76/85/86 only.
2016-2018 Microchip Technology Inc.
DS40001866B-page 226
PIC16(L)F15356/75/76/85/86
TABLE 14-6:
Name
PORTE
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
—
—
RE3
RE2(1)
RE1(1)
RE0(1)
223
TRISE2(1)
TRISE2(1)
TRISE2(1)
223
LATE2
LATE2
LATE2
224
TRISE
—
—
—
—
—(2)
LATE(1)
—
—
—
—
—
ANSELE
(1)
—
—
—
—
—
ANSE2
ANSE1
ANSE0
218
WPUE
—
—
—
—
WPUE3
WPUE2(1)
WPUE1(1)
WPUE0(1)
225
ODCONE(1)
—
—
—
—
—
ODCE2
ODCE1
ODCE0
225
SLRCONE
(1)
INLVLE
Legend:
Note 1:
2:
CONFIG2
Legend:
—
—
—
—
—
—
—
—
INLVLE3
SLRE2
SLRE1
(1)
SLRE0
(1)
225
INLVLE2(1) INLVLE1(1) INLVLE0(1)
226
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Present only in PIC16(L)F15375/76/85/86.
Unimplemented, read as ‘1’
TABLE 14-7:
Name
—
(1)
SUMMARY OF CONFIGURATION WORD WITH PORTE
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
—
—
DEBUG
STVREN
PPS1WAY
ZCDDIS
BORV
—
7:0
BOREN
LPBOREN
—
—
—
PWRTE
MCLRE
Register
on Page
103
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.
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PIC16(L)F15356/75/76/85/86
14.12 PORTF Registers
Note:
14.12.1
Present only on PIC16(L)F15385/86.
DATA REGISTER
PORTF is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISF
(Register 14-42). Setting a TRISF bit (= 1) will make the
corresponding PORTF pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISF bit (= 0) will make the corresponding
PORTF pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Figure 14-1 shows how to initialize an I/O port.
Reading the PORTF register (Register 14-41) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATF).
The PORT data latch LATF (Register 14-43) holds the
output port data, and contains the latest value of a LATF
or PORTF write.
14.12.2
DIRECTION CONTROL
The TRISF register (Register 14-42) controls the
PORTF pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISF register are maintained set when using them
as analog inputs. I/O pins configured as analog inputs
always read ‘0’.
14.12.3
INPUT THRESHOLD CONTROL
The INLVLF register (Register 14-48) controls the input
voltage threshold for each of the available PORTF
input pins. A selection between the Schmitt Trigger
CMOS or the TTL Compatible thresholds is available.
The input threshold is important in determining the
value of a read of the PORTF register and also the level
at which an interrupt-on-change occurs, if that feature
is enabled. See Table 37-4 for more information on
threshold levels.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
14.12.4
OPEN-DRAIN CONTROL
The ODCONF register (Register 14-46) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONF bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONF bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
Note:
14.12.5
It is not necessary to set open-drain
control when using the pin for I2C; the I2C
module controls the pin and makes the pin
open-drain.
SLEW RATE CONTROL
The SLRCONF register (Register 14-47) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONF bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONF bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
14.12.6
ANALOG CONTROL
The ANSELF register (Register 14-44) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELF bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELF bits has no effect on digital
output functions. A pin with TRIS clear and ANSELF set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
14.12.7
The ANSELF bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
WEAK PULL-UP CONTROL
The WPUF register (Register 14-45) controls the
individual weak pull-ups for each port pin.
14.12.8
PORTF FUNCTIONS AND OUTPUT
PRIORITIES
Each pin defaults to the PORT latch data after Reset.
Other output functions are selected with the peripheral
pin select logic. See Section 15.0 “Peripheral Pin
Select (PPS) Module” for more information.
Analog input functions, such as ADC and comparator
inputs, are not shown in the peripheral pin select lists.
Digital output functions may continue to control the pin
when it is in Analog mode.
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PIC16(L)F15356/75/76/85/86
14.13 Register Definitions: PORTF
REGISTER 14-41: PORTF: PORTF REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
RF: PORTF General Purpose I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
bit 7-0
Note 1:
Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return
of actual I/O pin values.
REGISTER 14-42: TRISF: PORTF TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
TRISF: PORTF Tri-State Control bits
1 = PORTF pin configured as an input (tri-stated)
0 = PORTF pin configured as an output
REGISTER 14-43: LATF: PORTF DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
LATF: PORTF Output Latch Value bits(1)
Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return
of actual I/O pin values.
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
REGISTER 14-44: ANSELF: PORTF ANALOG SELECT REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSF7
ANSF6
ANSF5
ANSF4
ANSF3
ANSF2
ANSF1
ANSF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
ANSF: Analog Select between Analog or Digital Function on Pins RF, respectively(1)
0 = Digital I/O. Pin is assigned to port or digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 7-0
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
REGISTER 14-45: WPUF: WEAK PULL-UP PORTF REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
WPUF7
WPUF6
WPUF5
WPUF4
WPUF3
WPUF2
WPUF1
WPUF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
WPUF: Weak Pull-up Register bits(1)
1 = Pull-up enabled
0 = Pull-up disabled
The weak pull-up device is automatically disabled if the pin is configured as an output.
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PIC16(L)F15356/75/76/85/86
REGISTER 14-46: ODCONF: PORTF OPEN-DRAIN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ODCF7
ODCF6
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ODCF: PORTF Open-Drain Enable bits
For RF pins, respectively
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
REGISTER 14-47: SLRCONF: PORTF SLEW RATE CONTROL REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
SLRF7
SLRF6
SLRF5
SLRF4
SLRF3
SLRF2
SLRF1
SLRF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
SLRF: PORTF Slew Rate Enable bits
For RF pins, respectively
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 14-48: INLVLF: PORTF INPUT LEVEL CONTROL REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
INLVLF7
INLVLF6
INLVLF5
INLVLF4
INLVLF3
INLVLF2
INLVLF1
INLVLF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
INLVLF: PORTF Input Level Select bits
For RF pins, respectively
1 = ST input used for PORT reads and interrupt-on-change
0 = TTL input used for PORT reads and interrupt-on-change
2016-2018 Microchip Technology Inc.
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TABLE 14-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
217
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
217
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
217
Name
ANSELF
ANSF7
ANSF6
ANSF5
ANSF4
ANSF3
ANSF2
ANSF1
ANSF0
218
WPUF
WPUF7
WPUF6
WPUF5
WPUF4
WPUF3
WPUF2
WPUF1
WPUF0
218
ODCONF
ODCF7
ODCF6
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
219
SLRCONF
SLRF7
SLRF6
SLRF5
SLRF4
SLRF3
SLRF2
SLRF1
SLRF0
219
INLVLF7
INLVLF6
INLVLF5
INLVLF4
INLVLF3
INLVLF2
INLVLF1
INLVLF0
219
INLVLF
Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF.
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
15.0
PERIPHERAL PIN SELECT
(PPS) MODULE
The Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O pins.
Only digital signals are included in the selections.
All analog inputs and outputs remain fixed to their
assigned pins. Input and output selections are
independent as shown in the simplified block diagram
Figure 15-1.
FIGURE 15-1:
SIMPLIFIED PPS BLOCK DIAGRAM
PPS Outputs
RA0PPS
PPS Inputs
abcPPS
RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RE3(1)
RE3PPS(1)
xyzPPS
RE3(1)
Note 1: RE3 is PPS input capable only (when MLCR is disabled).
15.1
PPS Inputs
Each peripheral has a PPS register with which the
inputs to the peripheral are selected. Inputs include the
device pins.
Although every peripheral has its own PPS input
selection register, the selections are identical for every
peripheral as shown in Register 15-1.
Note:
The notation “xxx” in the register name is
a place holder for the peripheral identifier.
For example, CLC1PPS.
15.2
PPS Outputs
Each I/O pin has a PPS register with which the pin
output source is selected. With few exceptions, the port
TRIS control associated with that pin retains control
over the pin output driver. Peripherals that control the
pin output driver as part of the peripheral operation will
override the TRIS control as needed. These
peripherals are (See Section 15.3 “Bidirectional
Pins”):
• EUSART (synchronous operation)
• MSSP (I2C)
Although every pin has its own PPS peripheral
selection register, the selections are identical for every
pin as shown in Register 15-2.
Note:
2016-2018 Microchip Technology Inc.
The notation “Rxy” is a place holder for the
pin port and bit identifiers. For example, x
and y for PORTA bit 0 would be A and 0,
respectively, resulting in the pin PPS
output selection register RA0PPS.
DS40001866B-page 233
PIC16(L)F15356/75/76/85/86
TABLE 15-1:
INPUT SIGNAL
NAME
PPS INPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15356)
Input Register
Name
Default
Location at
POR
Reset Value
(xxxPPS)
INT
INTPPS
RB0
01000
T0CKI
T0CKIPPS
RA4
00100
T1CKI
T1CKIPSS
RC0
10000
T1G
T1GPPS
RB5
01101
T2IN
T2INPPS
RC3
10011
CCP1
CCP1PPS
RC2
10010
CCP2
CCP2PPS
RC1
10001
CWG1IN
CWG1PPS
RB0
01000
CLCIN0
CLCIN0PPS
RA0
00000
CLCIN1
CLCIN1PPS
RA1
00001
CLCIN2
CLCIN2PPS
RB6
01110
CLCIN3
CLCIN3PPS
RB7
01111
ADACT
ADACTPPS
RB4
01100
SCK1/SCL1
SSP1CLKPPS
RC3
10011
SDI1/SDA1
SSP1DATPPS
RC4
10100
SS1
SSP1SS1PPS
RA5
00101
SCK2/SCL2
SSP2CLKPPS
RB1
01001
SDI2/SDA2
SSP2DATPPS
RB2
01010
SS2
SSP2SSPPS
RB0
01000
RX1/DT1
RX1DTPPS
RC7
10111
CK1
TX1CKPPS
RC6
10110
RX2/DT2
RX2DTPPS
RB7
01111
CK2
TX2CKPPS
RB6
01110
2016-2018 Microchip Technology Inc.
Remappable to Pins of PORTx
PIC16(L)F15356
PORTA
PORTB
PORTC
DS40001866B-page 234
PIC16(L)F15356/75/76/85/86
TABLE 15-2:
INPUT SIGNAL
NAME
PPS INPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15375/76)
Input Register
Name
Default
Location at
POR
Reset Value
(xxxPPS)
INT
INTPPS
RB0
01000
T0CKI
T0CKIPPS
RA4
00100
T1CKI
T1CKIPSS
RC0
10000
T1G
T1GPPS
RB5
01101
T2IN
T2INPPS
RC3
10011
CCP1
CCP1PPS
RC2
10010
CCP2
CCP2PPS
RC1
10001
CWG1IN
CWG1INPPS
RB0
01000
CLCIN0
CLCIN0PPS
RA0
00000
CLCIN1
CLCIN1PPS
RA1
00001
CLCIN2
CLCIN2PPS
RB6
01110
CLCIN3
CLCIN3PPS
RB7
01111
ADACT
ADACTPPS
RB4
01100
SCK1/SCL1
SSP1CLKPPS
RC3
10011
SDI1/SDA1
SSP1DATPPS
RC4
10100
SS1
SSP1SS1PPS
RA5
00101
SCK2/SCL2
SSP2CLKPPS
RB1
01001
SDI2/SDA2
SSP2DATPPS
RB2
01010
SS2
SSP2SSPPS
RB0
01000
RX1/DT1
RX1DTPPS
RC7
10111
CK1
TX1CKPPS
RC6
10110
RX2/DT2
RX2DTPPS
RB7
01111
CK2
TX2CKPPS
RB6
01110
2016-2018 Microchip Technology Inc.
Remappable to Pins of PORTx
PIC16(L)F15375/76
PORTA
PORTB
PORTC
PORTD
DS40001866B-page 235
PIC16(L)F15356/75/76/85/86
TABLE 15-3:
INPUT SIGNAL
NAME
PPS INPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15385/86)
Input Register
Name
Default
Location at
POR
Reset Value
(xxxPPS)
INT
INTPPS
RB0
01000
T0CKI
T0CKIPPS
RA4
00100
T1CKI
T1CKIPSS
RC0
10000
T1G
T1GPPS
RB5
01101
T2IN
T2INPPS
RC3
10011
CCP1
CCP1PPS
RC2
10010
CCP2
CCP2PPS
RC1
10001
CWG1IN
CWG1INPPS
RB0
01000
CLCIN0
CLCIN0PPS
RA0
00000
CLCIN1
CLCIN1PPS
RA1
00001
CLCIN2
CLCIN2PPS
RB6
01110
CLCIN3
CLCIN3PPS
RB7
01111
ADACT
ADACTPPS
RB4
01100
SCK1/SCL1
SSP1CLKPPS
RC3
10011
SDI1/SDA1
SSP1DATPPS
RC4
10100
SS1
SSP1SS1PPS
RA5
00101
SCK2/SCL2
SSP2CLKPPS
RB1
01001
SDI2/SDA2
SSP2DATPPS
RB2
01010
SS2
SSP2SSPPS
RB0
01000
RX1/DT1
RX1PPS
RC7
10111
CK1
TX1PPS
RC6
10110
RX2/DT2
RX2PPS
RB7
01111
CK2
TX2PPS
RB6
01110
2016-2018 Microchip Technology Inc.
Remappable to Pins of PORTx
PIC16(L)F15385/86
PORTA
PORTB
PORTC
PORTD
PORTF
DS40001866B-page 236
PIC16(L)F15356/75/76/85/86
TABLE 15-4:
TABLE 15-4:
PPS INPUT REGISTER
VALUES
PPS INPUT REGISTER
VALUES
Desired Input Pin
Value to Write to Register
Desired Input Pin
Value to Write to Register
RA0
0x00
RF1(3)
0x29
RA1
0x01
RF2(3)
0x2A
RA2
0x02
RF3(3)
0x2B
RA3
0x03
RF4(3)
0x2C
RA4
0x04
RF5(3)
0x2D
RA5
0x05
RF6(3)
0x2E
RA6
0x06
RF7(3)
0x2F
RA7
0x07
RB0
0x08
RB1
0x09
RB2
0x0A
RB3
0x0B
RB4
0x0C
RB5
0x0D
RB6
0x0E
RB7
0x0F
RC0
0x10
RC1
0x11
RC2
0x12
RC3
0x13
RC4
0x14
RC5
0x15
RC6
0x16
RC7
0x17
RD0(2)
0x18
RD1(2)
0x19
RD2(2)
0x1A
RD3(2)
0x1B
RD4(2)
0x1C
RD5(2)
0x1D
RD6(2)
0x1E
RD7(2)
0x1F
RE0(2)
0x20
RE1(2)
0x21
RE2(2)
0x22
Note 1:
2:
3:
(3)
RF0
Note 1:
2:
3:
0x28
Only a few of the values in this column are
valid for any given signal. For example,
since the INT signal can only be mapped
to PORTA or PORTB pins, only the register values 0x00-0x0F (corresponding to
RA and RB) are valid values
to write to the INTPPS register.
Present on PIC16(L)F15375/76/85/86 only.
Present on PIC16(L)F15385/86 only.
Only a few of the values in this column are
valid for any given signal. For example,
since the INT signal can only be mapped
to PORTA or PORTB pins, only the register values 0x00-0x0F (corresponding to
RA and RB) are valid values
to write to the INTPPS register.
Present on PIC16(L)F15375/76/85/86 only.
Present on PIC16(L)F15385/86 only.
2016-2018 Microchip Technology Inc.
DS40001866B-page 237
PIC16(L)F15356/75/76/85/86
15.3
Bidirectional Pins
PPS selections for peripherals with bidirectional
signals on a single pin must be made so that the PPS
input and PPS output select the same pin. Peripherals
that have bidirectional signals include:
• EUSART (synchronous operation)
• MSSP (I2C)
Note:
15.4
The I2C SCLx and SDAx functions can be
remapped through PPS. However, only
certain pins have the I2C and SMBusspecific input buffers implemented (I2C
mode disables INLVL and sets thresholds
that are specific for I2C). If the SCLx or
SDAx functions are mapped to some
other pin, the general purpose TTL or ST
input buffers (as configured based on
INLVL register setting) will be used
instead. In most applications, it is
therefore recommended only to map the
SCLx and SDAx pin functions to the
special I2C pins, specified in the pin
allocation tables.
15.5
PPS Permanent Lock
The PPS can be permanently locked by setting the
PPS1WAY Configuration bit. When this bit is set, the
PPSLOCKED bit can only be cleared and set one time
after a device Reset. This allows for clearing the
PPSLOCKED bit so that the input and output selections
can be made during initialization. When the
PPSLOCKED bit is set after all selections have been
made, it will remain set and cannot be cleared until after
the next device Reset event.
15.6
Operation During Sleep
PPS input and output selections are unaffected by Sleep.
15.7
Effects of a Reset
A device Power-on-Reset (POR) clears all PPS input
and output selections to their default values (Permanent
Lock Removed). All other Resets leave the selections
unchanged. Default input selections are shown in
Table 15-1 through Table 15-3.
PPS Lock
The PPS includes a mode in which all input and output
selections can be locked to prevent inadvertent
changes. PPS selections are locked by setting the
PPSLOCKED bit of the PPSLOCK register. Setting and
clearing this bit requires a special sequence as an extra
precaution against inadvertent changes. Examples of
setting and clearing the PPSLOCKED bit are shown in
Example 15-1.
EXAMPLE 15-1:
PPS LOCK/UNLOCK
SEQUENCE
; suspend interrupts
BCF
INTCON,GIE
;
BANKSEL PPSLOCK
; set bank
; required sequence, next 5 instructions
MOVLW
0x55
MOVWF
PPSLOCK
MOVLW
0xAA
MOVWF
PPSLOCK
; Set PPSLOCKED bit to disable writes or
; Clear PPSLOCKED bit to enable writes
BSF
PPSLOCK,PPSLOCKED
; restore interrupts
BSF
INTCON,GIE
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
TABLE 15-5:
Output
Signal
Name
PPS OUTPUT SIGNAL
ROUTING OPTIONS
(PIC16(L)F15356)
RxyPPS
Register
Value
Remappable to Pins of
PORTx
PIC16(L)F15356
PORTA
CLKR
0x1B
NCO1OUT
0x1A
PORTB
PORTC
TMR0
0x19
SDO2/SDA2
0x18
SCK2/SCL2
0x17
SDO1/SDA1
0x16
SCK1/SCL1
0x15
C2OUT
0x14
C1OUT
0x13
DT2
0x12
TX2/CK2
0x11
DT1
0x10
TX1/CK1
0x0F
PWM6OUT
0x0E
PWM5OUT
0x0D
PWM4OUT
0x0C
PWM3OUT
0x0B
CCP2
0x0A
CCP1
0x09
CWG1D
0x08
CWG1C
0x07
CWG1B
0x06
CWG1A
0x05
CLC4OUT
0x04
CLC3OUT
0x03
CLC2OUT
0x02
CLC1OUT
0x01
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PIC16(L)F15356/75/76/85/86
TABLE 15-6:
Output Signal
Name
PPS OUTPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15375/76)
Remappable to Pins of PORTx
RxyPPS
Register Value
PIC16(L)F15375/76
PORTA
PORTB
PORTC
CLKR
0x1B
NCO1OUT
0x1A
TMR0
0x19
SDO2/SDA2
0x18
SCK2/SCL2
0x17
SDO1/SDA1
0x16
SCK1/SCL1
0x15
C2OUT
0x14
C1OUT
0x13
DT2
0x12
TX2/CK2
0x11
DT1
0x10
PORTD
TX1/CK1
0x0F
PWM6OUT
0x0E
PWM5OUT
0x0D
PWM4OUT
0x0C
PWM3OUT
0x0B
CCP2
0x0A
CCP1
0x09
CWG1D
0x08
CWG1C
0x07
CWG1B
0x06
CWG1A
0x05
CLC4OUT
0x04
CLC3OUT
0x03
CLC2OUT
0x02
CLC1OUT
0x01
2016-2018 Microchip Technology Inc.
PORTE
DS40001866B-page 240
PIC16(L)F15356/75/76/85/86
TABLE 15-7:
Output Signal
Name
PPS OUTPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15385/86)
Remappable to Pins of PORTx
RxyPPS
Register Value
PIC16(L)F15385/86
PORTA
CLKR
0x1B
NCO1OUT
0x1A
TMR0
0x19
PORTB
PORTC
PORTD
PORTE
PORTF
SDO2/SDA2
0x18
SCK2/SCL2
0X17
SDO1/SDA1
0x16
SCK1/SCL1
0x15
C2OUT
0x14
C1OUT
0x13
DT2
0x12
TX2/CK2
0x11
DT1
0x10
TX1/CK1
0x0F
PWM6OUT
0x0E
PWM5OUT
0x0D
PWM4OUT
0x0C
PWM3OUT
0x0B
CCP2
0x0A
CCP1
0x09
CWG1D
0x08
CWG1C
0x07
CWG1B
0x06
CWG1A
0x05
CLC4OUT
0x04
CLC3OUT
0x03
CLC2OUT
0x02
CLC1OUT
0x01
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
15.8
Register Definitions: PPS Input Selection
REGISTER 15-1:
xxxPPS: PERIPHERAL xxx INPUT SELECTION(1)
U-0
U-0
—
—
R/W-q/u
R/W-q/u
R/W/q/u
R/W-q/u
R/W-q/u
R/W-q/u
xxxPPS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = value depends on peripheral
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
xxxPPS: Peripheral xxx Input Selection bits
See Table 15-1 through Table 15-3.
Note 1:
2:
The “xxx” in the register name “xxxPPS” represents the input signal function name, such as “INT”,
“T0CKI”, “RX”, etc. This register summary shown here is only a prototype of the array of actual registers,
as each input function has its own dedicated SFR (ex: INTPPS, T0CKIPPS, RXPPS, etc.).
Each specific input signal may only be mapped to a subset of these I/O pins, as shown in Table 15-1
through Table 15-3. Attempting to map an input signal to a non-supported I/O pin will result in undefined
behavior. For example, the “INT” signal map be mapped to any PORTA or PORTB pin. Therefore, the
INTPPS register may be written with values from 0x00-0x0F (corresponding to RA0-RB7). Attempting to
write 0x10 or higher to the INTPPS register is not supported and will result in undefined behavior.
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
REGISTER 15-2:
RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
RxyPPS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RxyPPS: Pin Rxy Output Source Selection bits
See Table 15-5 through Table 15-7.
REGISTER 15-3:
PPSLOCK: PPS LOCK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
—
—
PPSLOCKED
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
PPSLOCKED: PPS Locked bit
1= PPS is locked. PPS selections can not be changed.
0= PPS is not locked. PPS selections can be changed.
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
TABLE 15-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
—
—
—
—
—
PPSLOCKED
243
PPSLOCK
—
—
INTPPS
—
—
INTPPS
242
T0CKIPPS
—
—
T0CKIPPS
242
T1CKIPPS
—
—
T1CKIPPS
242
T1GPPS
—
—
T2INPPS
T1GPPS
242
T2INPPS
242
CCP1PPS
—
—
CCP1PPS
242
CCP2PPS
—
—
CCP2PPS
242
CWG1PPS
—
—
CWG1PPS
242
SSP1CLKPPS
—
—
SSP1CLKPPS
242
SSP1DATPPS
—
—
SSP1DATPPS
242
SSP1SSPPS
—
—
SSP1SSPPS
242
SSP2CLKPPS
—
—
SSP2CLKPPS
242
SSP2DATPPS
—
—
SSP2DATPPS
242
SSP2SSPPS
—
—
SSP2SSPPS
242
RX1DTPPS
—
—
RX1DTPPS
242
TX1CKPPS
—
—
TX1CKPPS
242
CLCIN0PPS
—
—
CLCIN0PPS
242
CLCIN1PPS
—
—
CLCIN1PPS
242
CLCIN2PPS
—
—
CLCIN2PPS
242
CLCIN3PPS
—
—
CLCIN3PPS
242
RX2DTPPS
—
—
RX2DTPPS
242
TX2CKPPS
—
—
TX2CKPPS
242
ADACTPPS
—
—
ADACTPPS
242
RA0PPS
—
—
—
RA0PPS
243
RA1PPS
—
—
—
RA1PPS
243
RA2PPS
—
—
—
RA2PPS
243
RA3PPS
—
—
—
RA3PPS
243
RA4PPS
—
—
—
RA4PPS
243
RA5PPS
—
—
—
RA5PPS
243
RA6PPS
—
—
—
RA6PPS
243
RA7PPS
—
—
—
RA7PPS
243
RB0PPS
—
—
—
RB0PPS
243
RB1PPS
—
—
—
RB1PPS
243
RB2PPS
—
—
—
RB2PPS
243
RB3PPS
—
—
—
RB3PPS
243
RB4PPS
—
—
—
RB4PPS
243
RB5PPS
—
—
—
RB5PPS
243
RB6PPS
—
—
—
RB6PPS
243
RB7PPS
—
—
—
RB7PPS
243
—
—
—
RC0PPS
243
RC0PPS
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Present only on PIC16(L)F15375/76/85/86.
Present only on PIC16(L)F15385/86.
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
TABLE 15-8:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)
Bit 6
Bit 5
RC1PPS
—
—
—
RC1PPS
243
RC2PPS
—
—
—
RC2PPS
243
RC3PPS
—
—
—
RC3PPS
243
RC4PPS
—
—
—
RC4PPS
243
RC5PPS
—
—
—
RC5PPS
243
RC6PPS
—
—
—
RC6PPS
243
RC7PPS
—
—
—
RC7PPS
243
RD0PPS(1)
—
—
—
RD0PPS
243
RD1PPS(1)
—
—
—
RD1PPS
243
RD2PPS(1)
—
—
—
RD2PPS
243
RD3PPS(1)
—
—
—
RD3PPS
243
(1)
—
—
—
RD4PPS
243
RD5PPS(1)
—
—
—
RD5PPS
243
RD6PPS(1)
—
—
—
RD6PPS
243
(1)
—
—
—
RD7PPS
243
RE0PPS(1)
—
—
—
RD5PPS
243
RE1PPS(1)
—
—
—
RD6PPS
243
RE2PPS(1)
—
—
—
RD7PPS
243
(2)
—
—
—
RF0PPS
243
RF1PPS(2)
—
—
—
RF1PPS
243
RF2PPS(2)
—
—
—
RF2PPS
243
RF3PPS(2)
—
—
—
RF3PPS
243
RF4PPS(2)
—
—
—
RF4PPS
243
RF5PPS(2)
—
—
—
RF5PPS
243
RF6PPS(2)
—
—
—
RF6PPS
243
RF7PPS(2)
—
—
—
RF7PPS
243
RD4PPS
RD7PPS
RF0PPS
Legend:
Note 1:
2:
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
Bit 7
— = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.
Present only on PIC16(L)F15375/76/85/86.
Present only on PIC16(L)F15385/86.
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PIC16(L)F15356/75/76/85/86
16.0
PERIPHERAL MODULE
DISABLE
The PIC16(L)F15356/75/76/85/86 provides the ability
to disable selected modules, placing them into the
lowest possible Power mode.
For legacy reasons, all modules are ON by default
following any Reset.
16.1
Disabling a Module
16.2
Enabling a module
When the register bit is cleared, the module is reenabled and will be in its Reset state; SFR data will
reflect the POR Reset values.
Depending on the module, it may take up to one full
instruction cycle for the module to become active.
There should be no interaction with the module
(e.g., writing to registers) for at least one instruction
after it has been re-enabled.
Disabling a module has the following effects:
16.3
• All clock and control inputs to the module are
suspended; there are no logic transitions, and the
module will not function.
• The module is held in Reset:
- Writing to SFRs is disabled
- Reads return 00h
When a module is disabled, all the associated PPS
selection registers (Registers xxxPPS Register 15-1,
15-2, and 15-3), are also disabled.
2016-2018 Microchip Technology Inc.
16.4
Disabling a Module
System Clock Disable
Setting SYSCMD (PMD0, Register 16-1) disables the
system clock (FOSC) distribution network to the
peripherals. Not all peripherals make use of SYSCLK,
so not all peripherals are affected. Refer to the specific
peripheral description to see if it will be affected by this
bit.
DS40001866B-page 246
PIC16(L)F15356/75/76/85/86
16.5
Register Definitions: Peripheral Module Disable Control
REGISTER 16-1:
PMD0: PMD CONTROL REGISTER 0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
SYSCMD
FVRMD
—
—
—
NVMMD
CLKRMD
IOCMD
7
0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SYSCMD: Disable Peripheral System Clock Network bit
See description in Section 16.4 “System Clock Disable”.
1 = System clock network disabled (a.k.a. FOSC)
0 = System clock network enabled
bit 6
FVRMD: Disable Fixed Voltage Reference (FVR) bit
1 = FVR module disabled
0 = FVR module enabled
bit 5-3
Unimplemented: Read as ‘0’
bit 2
NVMMD: NVM Module Disable bit(1)
1 = User memory reading and writing is disabled; NVMCON registers cannot be written; FSR access
to these locations returns zero.
0 = NVM module enabled
bit 1
CLKRMD: Disable Clock Reference CLKR bit
1 = CLKR module disabled
0 = CLKR module enabled
bit 0
IOCMD: Disable Interrupt-on-Change bit, All Ports
1 = IOC module(s) disabled
0 = IOC module(s) enabled
Note 1:
When enabling NVM, a delay of up to 1 µs may be required before accessing data.
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
REGISTER 16-2:
PMD1: PMD CONTROL REGISTER 1
R/W-0/0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1MD
—
—
—
—
TMR2MD
TMR1MD
TMR0MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
NCO1MD: Disable Numerically Control Oscillator bit
1 = NCO1 module disabled
0 = NCO1 module enabled
bit 6-3
Unimplemented: Read as ‘0’
bit 2
TMR2MD: Disable Timer TMR2 bit
1 = Timer2 module disabled
0 = Timer2 module enabled
bit 1
TMR1MD: Disable Timer TMR1 bit
1 = Timer1 module disabled
0 = Timer1 module enabled
bit 0
TMR0MD: Disable Timer TMR0 bit
1 = Timer0 module disabled
0 = Timer0 module enabled
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
REGISTER 16-3:
PMD2: PMD CONTROL REGISTER 2
U-0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
DAC1MD
ADCMD
—
—
CMP2MD
CMP1MD
ZCDMD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6
DAC1MD: Disable DAC1 bit
1 = DAC module disabled
0 = DAC module enabled
bit 5
ADCMD: Disable ADC bit
1 = ADC module disabled
0 = ADC module enabled
bit 4-3
Unimplemented: Read as ‘0’
bit 2
CMP2MD: Disable Comparator C2 bit
1 = C2 module disabled
0 = C2 module enabled
bit 1
CMP1MD: Disable Comparator C1 bit
1 = C1 module disabled
0 = C1 module enabled
bit 0
ZCDMD: Disable ZCD bit
1 = ZCD module disabled
0 = ZCD module enabled
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
REGISTER 16-4:
PMD3: PMD CONTROL REGISTER 3
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
PWM6MD
PWM5MD
PWM4MD
PWM3MD
CCP2MD
CCP1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5
PWM6MD: Disable Pulse-Width Modulator PWM6 bit
1 = PWM6 module disabled
0 = PWM6 module enabled
bit 4
PWM5MD: Disable Pulse-Width Modulator PWM5 bit
1 = PWM5 module disabled
0 = PWM5 module enabled
bit 3
PWM4MD: Disable Pulse-Width Modulator PWM4 bit
1 = PWM4 module disabled
0 = PWM4 module enabled
bit 2
PWM3MD: Disable Pulse-Width Modulator PWM3 bit
1 = PWM3 module disabled
0 = PWM3 module enabled
bit 1
CCP2MD: Disable CCP2 bit
1 = CCP2 module disabled
0 = CCP2 module enabled
bit 0
CCP1MD: Disable CCP1 bit
1 = CCP1 module disabled
0 = CCP1 module enabled
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
REGISTER 16-5:
PMD4: PMD CONTROL REGISTER 4
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
R/W-0/0
UART2MD
UART1MD
MSSP2MD
MSSP1MD
—
—
—
CWG1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
UART2MD: Disable EUSART2 bit
1 = EUSART2 module disabled
0 = EUSART2 module enabled
bit 6
UART1MD: Disable EUSART1 bit
1 = EUSART1 module disabled
0 = EUSART1 module enabled
bit 5
MSSP2MD: Disable MSSP2 bit
1 = MSSP2 module disabled
0 = MSSP2 module enabled
bit 4
MSSP1MD: Disable MSSP1 bit
1 = MSSP1 module disabled
0 = MSSP1 module enabled
bit 3-1
Unimplemented: Read as ‘0’
bit 0
CWG1MD: Disable CWG1 bit
1 = CWG1 module disabled
0 = CWG1 module enabled
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PIC16(L)F15356/75/76/85/86
REGISTER 16-6:
PMD5 – PMD CONTROL REGISTER 5
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
—
—
CLC4MD
CLC3MD
CLC2MD
CLC1MD
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-5
Unimplemented: Read as ‘0’
bit 4
CLC4MD: Disable CLC4 bit
1 = CLC4 module disabled
0 = CLC4 module enabled
bit 3
CLC3MD: Disable CLC3 bit
1 = CLC3 module disabled
0 = CLC3 module enabled
bit 2
CLC2MD: Disable CLC2 bit
1 = CLC2 module disabled
0 = CLC2 module enabled
bit 1
CLC1MD: Disable CLC1 bit
1 = CLC1 module disabled
0 = CLC1 module enabled
bit 0
Unimplemented: Read as ‘0’
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PIC16(L)F15356/75/76/85/86
TABLE 16-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE PMD MODULE
Bit 0
Register
on page
CLKRMD
IOCMD
247
TMR1MD
TMR0MD
248
ZCDMD
249
CCP2MD
CCP1MD
250
—
CWG1MD
251
CLC1MD
—
252
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PMD0
SYSCMD
FVRMD
—
—
—
NVMMD
PMD1
NCO1MD
—
—
—
—
TMR2MD
PMD2
—
DAC1MD
ADCMD
—
—
CMP2MD
CMP1MD
—
—
PWM6MD
PWM5MD
PWM4MD
PWM3MD
—
—
CLC3MD
CLC2MD
PMD3
PMD4
PMD5
Legend:
UART2MD UART1MD MSSP2MD MSSP1MD
—
—
—
CLC4MD
Bit 2
Bit 1
— = unimplemented, read as ‘0’. Shaded cells are unused by the PMD module.
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17.0
INTERRUPT-ON-CHANGE
17.3
Interrupt Flags
All pins on ports A, B and C and lower four bits of PORTE
can be configured to operate as Interrupt-on-Change
(IOC) pins. An interrupt can be generated by detecting a
signal that has either a rising edge or a falling edge. Any
individual pin, or combination of pins, can be configured
to generate an interrupt. The interrupt-on-change
module has the following features:
The bits located in the IOCxF registers are status flags
that correspond to the interrupt-on-change pins of each
port. If an expected edge is detected on an appropriately
enabled pin, then the status flag for that pin will be set,
and an interrupt will be generated if the IOCIE bit is set.
The IOCIF bit of the PIR0 register reflects the status of
all IOCxF bits.
•
•
•
•
17.3.1
Interrupt-on-Change enable (Master Switch)
Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
Figure 17-1 is a block diagram of the IOC module.
17.1
Enabling the Module
To allow individual pins to generate an interrupt, the
IOCIE bit of the PIE0 register must be set. If the IOCIE
bit is disabled, the edge detection on the pin will still
occur, but an interrupt will not be generated.
17.2
CLEARING INTERRUPT FLAGS
The individual status flags, (IOCxF register bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 17-1:
Individual Pin Configuration
For each pin, a rising edge detector and a falling edge
detector are present. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register is set. To
enable a pin to detect a falling edge, the associated bit
of the IOCxN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in
both of the IOCxP and IOCxN registers.
2016-2018 Microchip Technology Inc.
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
MOVLW0xff
XORWFIOCAF, W
ANDWFIOCAF, F
17.4
Operation in Sleep
The interrupt-on-change interrupt event will wake the
device from Sleep mode, if the IOCIE bit is set.
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PIC16(L)F15356/75/76/85/86
FIGURE 17-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTB EXAMPLE)
Rev. 10-000037C
9/14/2016
IOCBNx
D
Q
R
edge
detect
RBx
IOCBPx
D
Q
R
data bus =
0 or 1
D
S
to data bus
IOCBFx
Q
write IOCBFx
IOCIE
IOC interrupt
to CPU core
RESET
from all other
IOCnFx individual
pin detectors
Note 1: See Table 8-1 for BOR Active Conditions.
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17.5
Register Definitions: Interrupt-on-Change Control
REGISTER 17-1:
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAP7
IOCAP6
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCAP: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 17-2:
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAN7
IOCAN6
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCAN: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
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REGISTER 17-3:
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
R/W/HS-0/0
R/W/HS-0/0
IOCAF7
IOCAF6
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCAF5
IOCAF4
IOCAF3
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-0
IOCAF: Interrupt-on-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
0 = No change was detected, or the user cleared the detected change.
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REGISTER 17-4:
R/W-0/0
IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER
R/W-0/0
(1)
(1)
IOCBP7
IOCBP6
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
IOCBP: Interrupt-on-Change PORTB Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCBFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
If the debugger is enabled, these bits are not available for use.
REGISTER 17-5:
IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCBN7(1)
IOCBN6(1)
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
IOCBN: Interrupt-on-Change PORTB Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCBFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
If the debugger is enabled, these bits are not available for use.
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REGISTER 17-6:
R/W/HS-0/0
IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER
R/W/HS-0/0
(1)
IOCBF7
IOCBF6
(1)
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCBF5
IOCBF4
IOCBF3
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCBF2
IOCBF1
IOCBF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-0
Note 1:
IOCBF: Interrupt-on-Change PORTB Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling
edge was detected on RBx.
0 = No change was detected, or the user cleared the detected change.
If the debugger is enabled, these bits are not available for use.
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REGISTER 17-7:
IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCP7
IOCCP6
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCCP: Interrupt-on-Change PORTC Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
REGISTER 17-8:
IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCCN7
IOCCN6
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
IOCCN: Interrupt-on-Change PORTC Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
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REGISTER 17-9:
IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER
R/W/HS-0/0
R/W/HS-0/0
IOCCF7
IOCCF6
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCCF5
IOCCF4
IOCCF3
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCCF2
IOCCF1
IOCCF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-0
IOCCF: Interrupt-on-Change PORTC Flag bits
1 = An enabled change was detected on the associated pin
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling
edge was detected on RCx.
0 = No change was detected, or the user cleared the detected change
REGISTER 17-10: IOCEP: INTERRUPT-ON-CHANGE PORTE POSITIVE EDGE REGISTER
U-0
U-0
—
U-0
—
—
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
—
IOCEP3(2)
IOCEP2(1)
IOCEP1(1)
IOCEP0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
IOCEP: Interrupt-on-Change PORTE Positive Edge Enable bit
1 = Interrupt-on-Change enabled on the pin for a positive-going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
Note 1:
2:
Present only on PIC16(L)F15375/76/85/86.
If MCLRE=1 or LVP=1, port functionality is disabled and IOC on that pin is not available.
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REGISTER 17-11: IOCEN: INTERRUPT-ON-CHANGE PORTE NEGATIVE EDGE REGISTER
U-0
U-0
—
U-0
—
—
U-0
—
R/W/HS-0/0
(2)
IOCEN3
R/W/HS-0/0
(1)
IOCEN2
R/W/HS-0/0
(1)
IOCEN1
bit 7
R/W/HS-0/0
IOCEN0(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
IOCEN: Interrupt-on-Change PORTE Negative Edge Enable bit
1 = Interrupt-on-Change enabled on the pin for a negative-going edge. IOCCFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
Note 1:
2:
Present only on PIC16(L)F15375/76/85/86.
If MCLRE=1 or LVP=1, port functionality is disabled and IOC on that pin is not available.
REGISTER 17-12: IOCEF: INTERRUPT-ON-CHANGE PORTE FLAG REGISTER
U-0
U-0
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
—
—
—
—
IOCEF3(2)
IOCEF2(1)
IOCEF1(1)
IOCEF0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-4
Unimplemented: Read as ‘0’
bit 3
IOCEF: Interrupt-on-Change PORTE Flag bit
1 = An enabled change was detected on the associated pin
Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling
edge was detected on RCx.
0 = No change was detected, or the user cleared the detected change
Note 1:
2:
Present only on PIC16(L)F15375/76/85/86.
If MCLRE=1 or LVP=1, port functionality is disabled and IOC on that pin is not available.
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TABLE 17-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 4
Bit 0
Register
on Page
—
—
INTEDG
147
—
—
INTE
148
IOCAP2
IOCAP1
IOCAP0
256
IOCAN3
IOCAN2
IOCAN1
IOCAN0
256
IOCAF3
IOCAF2
IOCAF1
IOCAF0
257
Bit 7
Bit 6
INTCON
GIE
PEIE
—
—
—
—
—
TMR0IE
IOCIE
—
IOCAP
IOCAP7
IOCAP6
IOCAP5
IOCAP4
IOCAP3
IOCAN
IOCAN7
IOCAN6
IOCAN5
IOCAN4
IOCAF
IOCAF7
IOCAF6
IOCAF5
IOCAF4
PIE0
Bit 5
Bit 1
Name
Bit 3
Bit 2
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
IOCBP3
IOCBP2
IOCBP1
IOCBP0
258
IOCBN
IOCBN7
IOCBN6
IOCBN5
IOCBN4
IOCBN3
IOCBN2
IOCBN1
IOCBN0
258
IOCBF
IOCBF7
IOCBF6
IOCBF5
IOCBF4
IOCBF3
IOCBF2
IOCBF1
IOCBF0
259
IOCCP
IOCCP7
IOCCP6
IOCCP5
IOCCP4
IOCCP3
IOCCP2
IOCCP1
IOCCP0
260
IOCCN
IOCCN7
IOCCN6
IOCCN5
IOCCN4
IOCCN3
IOCCN2
IOCCN1
IOCCN0
260
IOCCF
IOCCF7
IOCCF6
IOCCF5
IOCCF4
IOCCF3
IOCCF2
IOCCF1
IOCCF0
261
IOCEP1(1)
IOCEP0(1)
261
262
IOCEP
—
—
—
—
IOCEP3
IOCEP2(1)
IOCEN
—
—
—
—
IOCEN3
IOCEN2(1) IOCEN1(1) IOCEN0(1)
IOCEF
Legend:
Note 1:
—
—
—
—
IOCEF3
IOCEF2
(1)
IOCEF1
(1)
IOCEF0
(1)
262
— = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Present only in PIC16(L)F15375/76/85/86.
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18.0
FIXED VOLTAGE REFERENCE
(FVR)
18.1
The output of the FVR, which is connected to the ADC,
comparators, and DAC, is routed through two
independent programmable gain amplifiers. Each
amplifier can be programmed for a gain of 1x, 2x or 4x,
to produce the three possible voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
•
•
•
•
The ADFVR bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module.
Reference
Section 20.0
“Analog-to-Digital
Converter (ADC) Module” for additional information.
ADC input channel
ADC positive reference
Comparator positive and negative input
Digital-to-Analog Converter (DAC)
The CDAFVR bits of the FVRCON register are used
to enable and configure the gain amplifier settings for the
reference supplied to the DAC and comparator module.
Reference Section 21.0 “5-Bit Digital-to-Analog
Converter (DAC1) Module” and Section 23.0
“Comparator Module” for additional information.
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
Note:
Independent Gain Amplifiers
Fixed Voltage Reference output cannot
exceed VDD.
18.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled,
it requires time for the reference and amplifier circuits
to stabilize.
FVRRDY is an indicator of the reference being ready.
In the case of an LF device, or a device on which the
BOR is enabled in the Configuration Word settings,
then the FVRRDY bit will be high prior to setting
FVREN as those module require the reference voltage.
FIGURE 18-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
Rev. 10-000053D
9/15/2016
ADFVR
CDAFVR
2
1x
2x
4x
ADC FVR Buffer
1x
2x
4x
Comparator and DAC
FVR Buffer
2
FVREN
Voltage
Reference
Note 1:
2:
FVRRDY (Note 1)
FVRRDY is always ‘1’.
Any peripheral requiring the Fixed Reference (See Table 18-1).
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18.3
Register Definitions: FVR Control
REGISTER 18-1:
R/W-0/0
FVREN
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R-q/q
FVRRDY
R/W-0/0
(1)
(3)
TSEN
R/W-0/0
R/W-0/0
(3)
TSRNG
R/W-0/0
R/W-0/0
CDAFVR
bit 7
R/W-0/0
ADFVR
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
FVREN: Fixed Voltage Reference Enable bit
1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5
TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4
TSRNG: Temperature Indicator Range Selection bit(3)
1 = Temperature in High Range VOUT = 3VT
0 = Temperature in Low Range VOUT = 2VT
bit 3-2
CDAFVR: Comparator FVR Buffer Gain Selection bits
11 =Comparator FVR Buffer Gain is 4x, (4.096V)(2)
10 =Comparator FVR Buffer Gain is 2x, (2.048V)(2)
01 =Comparator FVR Buffer Gain is 1x, (1.024V)
00 =Comparator FVR Buffer is off
bit 1-0
ADFVR: ADC FVR Buffer Gain Selection bit
11 =ADC FVR Buffer Gain is 4x, (4.096V)(2)
10 =ADC FVR Buffer Gain is 2x, (2.048V)(2)
01 =ADC FVR Buffer Gain is 1x, (1.024V)
00 =ADC FVR Buffer is off
Note 1:
2:
3:
FVRRDY is always ‘1’.
Fixed Voltage Reference output cannot exceed VDD.
See Section 19.0 “Temperature Indicator Module” for additional information.
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TABLE 18-1:
Name
FVRCON
SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
ADCON0
Bit 2
CDAFVR
CHS
ADCON1
ADFM
DAC1CON0
Legend:
Bit 3
DAC1EN
—
DAC1OE1
DAC1OE2
—
DAC1PSS
Bit 0
ADFVR
GO/DONE
—
ADCS
Bit 1
ADON
Register
on page
265
278
ADPREF
280
—
288
DAC1NSS
– = unimplemented locations read as ‘0’. Shaded cells are not used with the Fixed Voltage Reference.
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19.0
TEMPERATURE INDICATOR
MODULE
19.1.1
TEMPERATURE INDICATOR
RANGE
The circuit’s range of operating temperature falls
between -40°C and +125°C. A one-point calibration
allows the circuit to indicate a temperature closely
surrounding that point. A two-point calibration allows
the circuit to sense the entire range of temperature
more accurately.
The temperature indicator circuit operates in either high
or low range. The high range, selected by setting the
TSRNG bit of the FVRCON register, provides a wider
output voltage. This provides more resolution over the
temperature range. High range requires a higher-bias
voltage to operate and thus, a higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
sensor voltage and thus, a lower VDD voltage is needed
to operate the circuit.
19.1
The output voltage of the sensor is the highest value at
-40°C and the lowest value at +125°C.
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die.
Module Operation
The temperature indicator module consists of a
temperature-sensing circuit that provides a voltage to
the device ADC. The analog voltage output, VMEAS,
varies inversely to the device temperature. The output of
the temperature indicator is referred to as VMEAS.
Figure 19-1 shows a simplified block diagram of the
temperature indicator module.
FIGURE 19-1:
TEMPERATURE
INDICATOR MODULE
BLOCK DIAGRAM
5HY '
9''
7651*
76(1
7HPSHUDWXUH,QGLFDWRU
0RGXOH
• High Range: The High range is used in applications with the reference for the ADC,
VREF = 2.048V. This range may not be suitable for
battery-powered applications. The ADC reading
(in counts) at 90°C for the high range setting is
stored in the DIA Table (Table 6-1) as parameter
TSHR2.
• Low Range: This mode is useful in applications in
which the VDD is too low for high-range operation.
The VDD in this mode can be as low as 1.8V. VDD
must, however, be at least 0.5V higher than the
maximum sensor voltage depending on the
expected low operating temperature. The ADC
reading (in counts) at 90°C for the Low range setting is stored in the DIA Table (Table 6-1) as
parameter TSLR2.
19.1.2
90($6
7R$'&
*1'
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 20.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The ON/OFF bit for the module is located in the
FVRCON register. See Section 18.0 “Fixed Voltage
Reference (FVR)” for more information. The circuit is
enabled by setting the TSEN bit of the FVRCON
register. When the module is disabled, the circuit draws
no current.
MINIMUM OPERATING VDD
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications. When the temperature
circuit is operated in high range, the device operating
voltage, VDD, must be high enough to ensure that the
temperature circuit is correctly biased.
Table 19-1 shows the recommended minimum VDD vs.
Range setting.
TABLE 19-1:
RECOMMENDED VDD vs.
RANGE
Min.VDD, TSRNG = 1
(High Range)
Min. VDD, TSRNG = 0
(Low Range)
2.5
1.8
The circuit operates in either High or Low range. Refer
to Section 19.1.1 “Temperature Indicator Range” for
more details on the range settings.
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19.2
Temperature Calculation
This section describes the steps involved in calculating
the die temperature, TMEAS:
1.
2.
3.
4.
Obtain the ADC count value of the measured
analog voltage: The analog output voltage,
VMEAS is converted to a digital count value by
the Analog to Digital Converter (ADC) and is
referred to as ADCMEAS.
Obtain the ADC count value, ADCDIA at 90
degrees, in the DIA table (Table 6-1). This
parameter is TSLR2 for the low range setting or
TSHR2 for the high range setting of the
temperature indicator module.
Obtain the output analog voltage (in mV) value
of the Fixed Reference Voltage (FVR) for 2x
setting, from the DIA Table. This parameter is
FVRA2X in the DIA table (Table 5-3).
Obtain the value of the temperature indicator
voltage sensitivity, parameter Mv, from Table 3726 for the corresponding range setting.
Equation 19-1 provides an estimate for the die
temperature based on the above parameters.
EQUATION 19-1:
Note 1: It is recommended to take the average of
ten measurements of ADCmeas to
reduce noise and improve accuracy.
2: Refer to Section 37.0, Electrical Specifications for FVR reference voltage accuracy.
19.2.1
CALIBRATION
19.2.1.1
Higher-Order Calibration
If the application requires more precise temperature
measurement, additional calibrations steps will be
necessary. For these applications, two-point or threepoint calibration is recommended.
19.3
ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait a certain minimum acquisition time
(parameter TS01 in Table 37-26) for the ADC value to
settle, after the ADC input multiplexer is connected to
the temperature indicator output, before the conversion
is performed.
SENSOR TEMPERATURE
ADC MEAS – ADC DIA FVRA2X
T MEAS = 90 + -------------------------------------------------------------------------------------------N
2 – 1 Mv
Where:
ADCMEAS = ADC reading at temperature being
estimated
ADCDIA = ADC reading stored in the DIA
FVRA2X = FVR value stored in the DIA for 2x setting
N = Resolution of the ADC
Mv = Temperature Indicator voltage sensitivity (mV/°C)
TABLE 19-2:
Name
FVRCON
SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR(1)
Bit 7
Bit 6
Bit 5
Bit 4
EN
RDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR
Bit 1
Bit 0
ADFVR
Register
on page
265
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are unused by the temperature indicator module.
Note 1: It is recommended to take the average of ten measurements of ADCMEAS to reduce noise and improve
accuracy.
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20.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 20-1 shows the block diagram of the ADC.
FIGURE 20-1:
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
ADC BLOCK DIAGRAM
VDD
ADPREF
Rev. 10-000033A
7/30/2013
Positive
Reference
Select
VDD
VREF+ pin
External
Channel
Inputs
ANa
VRNEG VRPOS
.
.
.
ADC_clk
sampled
input
ANz
Internal
Channel
Inputs
ADCS
VSS
AN0
ADC
Clock
Select
FOSC/n Fosc
Divider
FRC
FOSC
FRC
Temp Indicator
DACx_output
ADC CLOCK SOURCE
FVR_buffer1
ADC
Sample Circuit
CHS
ADFM
set bit ADIF
Write to bit
GO/DONE
10-bit Result
GO/DONE
Q1
Q4
16
start
ADRESH
Q2
TRIGSEL
10
complete
ADRESL
Enable
Trigger Select
ADON
. . .
VSS
Trigger Sources
AUTO CONVERSION
TRIGGER
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20.1
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
20.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin will be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 14.0 “I/O Ports” for more information.
Note:
20.1.2
Note:
It is recommended that when switching
from an ADC channel of a higher voltage
to a channel of a lower voltage, that the
user selects the VSS channel before connecting to the channel with the lower voltage. If the ADC does not have a dedicated
VSS input channel, the VSS selection
(DAC1R = b’00000’) through the
DAC output channel can be used. If the
DAC is in use, a free input channel can be
connected to VSS, and can be used in
place of the DAC.
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
There are several channel selections available:
•
•
•
•
•
•
•
•
•
•
Seven Port A channels
Seven Port B channels
Seven Port C channels
Seven Port D channels(1)
Three Port E channels(1)
Seven Port F channels(2)
Temperature Indicator
DAC output
Fixed Voltage Reference (FVR)
AVSS (Ground)
Note 1: Present on PIC16(L)F15375/76/85/86 only.
2: Present on PIC16(L)F15385/86 only.
The CHS bits of the ADCON0 register
(Register 20-1) determine which channel is connected
to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 20.2
“ADC Operation” for more information.
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20.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register
provides control of the positive voltage reference. The
positive voltage reference can be:
•
•
•
•
VREF+ pin
VDD
FVR 2.048V
FVR 4.096V (Not available on LF devices)
The ADPREF bit of the ADCON1 register provides
control of the negative voltage reference. The negative
voltage reference can be:
• VREF- pin
• VSS
See Section 18.0 “Fixed Voltage Reference (FVR)”
for more details on the Fixed Voltage Reference.
20.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1
register. There are seven possible clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
ADCRC (dedicated RC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD
periods as shown in Figure 20-2.
For correct conversion, the appropriate TAD specification
must be met. Refer to Table 37-13 for more information.
Table 20-1 gives examples of appropriate ADC clock
selections.
Note:
Unless using the ADCRC, any changes in
the system clock frequency will change
the ADC clock frequency, which may
adversely affect the ADC result.
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TABLE 20-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS
32 MHz
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
000
62.5ns(2)
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
FOSC/4
100
(2)
125 ns
(2)
200 ns
250 ns
(2)
(2)
FOSC/8
001
0.5 s(2)
400 ns(2)
0.5 s(2)
FOSC/16
101
800 ns
800 ns
1.0 s
FOSC/32
010
1.0 s
FOSC/64
110
2.0 s
ADCRC
Legend:
Note 1:
2:
3:
4:
x11
1.6 s
2.0 s
3.2 s
(1,4)
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
2.0 s
4.0 s
16.0 s(3)
4.0 s
8.0 s
8.0 s(3)
4.0 s
(1,4)
1.0 s
500 ns
(1,4)
1.0-6.0 s
(3)
32.0 s(2)
16.0 s(2)
(1,4)
1.0-6.0 s
64.0 s(2)
(1,4)
1.0-6.0 s(1,4)
Shaded cells are outside of recommended range.
See TAD parameter for ADCRC source typical TAD value.
These values violate the required TAD time.
Outside the recommended TAD time.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived
from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be
performed with the device in Sleep mode.
FIGURE 20-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
Rev. 10-000035A
7/30/2013
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
TAD10
TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
THCD
Conversion Starts
TACQ
Holding capacitor disconnected
from analog input (THCD).
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ADON bit)
and
Select channel (ACS bits)
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20.1.5
INTERRUPTS
20.1.6
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
RESULT FORMATTING
The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFM bit
of the ADCON1 register controls the output format.
Figure 20-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the ADCRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine (ISR).
FIGURE 20-3:
10-BIT ADC CONVERSION RESULT FORMAT
Rev. 10-000 054A
12/21/201 6
ADRESH
ADRESL
(ADFM = 0) MSb
LSb
bit 0
bit 7
10-bit ADC Result
(ADFM = 1)
bit 0
bit 7
Unimplemented: Read as ‘0’
MSb
bit 7
Unimplemented: Read as ‘0’
2016-2018 Microchip Technology Inc.
LSb
bit 0
bit 7
bit 0
10-bit ADC Result
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20.2
20.2.1
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
20.2.2
The GO/DONE bit will not be set in the
same instruction that turns on the ADC.
Refer to Section 20.2.5 “ADC Conversion Procedure”.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH and ADRESL registers with
new conversion result
Note:
20.2.3
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the ADCRC
option. When the ADCRC oscillator source is selected,
the ADC waits one additional instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
Note:
The Auto-conversion feature is not available while the device is in Sleep mode.
TABLE 20-2:
ADACT
VALUE
ADC AUTO-CONVERSION
TABLE
SOURCE/
PERIPHERAL
DESCRIPTION
0x00
Disabled
External Trigger Disabled
0x01
ADACTPPS
Pin Selected by ADACTPPS
0x02
TMR0
Timer0 overflow condition
0x03
TMR1
Timer1 overflow condition
0x04
TMR2
Match between Timer2 postscaled
value and PR2
0x05
CCP1
CCP1 output
0x06
CCP2
CCP2 output
0x07
PWM3
PWM3 output
0x08
PWM4
PWM4 output
0x09
PWM5
PWM5 output
0x0A
PWM6
PWM6 output
0x0B
NCO1
NCO1 output
0x0C
C1OUT
Comparator C1 output
0x0D
C2OUT
Comparator C2 output
0x0E
IOCIF
Interrupt-on change flag trigger
0x0F
CLC1
CLC1 output
0x10
CLC2
CLC2 output
0x11
CLC3
CLC3 output
0x12
CLC4
CLC4 output
0x13-0xFF
Reserved
Reserved, do not use
When the ADC clock source is something other than
ADCRC, a SLEEP instruction causes the present
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
20.2.4
AUTO-CONVERSION TRIGGER
The Auto-conversion Trigger allows periodic ADC
measurements without software intervention. When a
rising edge of the selected source occurs, the GO/
DONE bit is set by hardware.
The Auto-conversion Trigger source is selected with
the ADACT bits of the ADACT register.
Using the Auto-conversion Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
See Table 20-2 for auto-conversion sources.
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20.2.5
ADC CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
• Select ADC conversion clock
• Select voltage reference
• Select ADC input channel
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 20-1:
ADC CONVERSION
;This code block configures the ADC
;for polling, Vdd and Vss references, ADCRC
;oscillator and AN0 input.
;
;Conversion start & polling for completion ;
are included.
;
BANKSELADCON1;
MOVLWB’11110000’;Right justify, ADCRC
;oscillator
MOVWFADCON1;Vdd and Vss Vref
BANKSELTRISA;
BSF TRISA,0;Set RA0 to input
BANKSELANSELA;
BSF ANSELA,0;Set RA0 to analog
BANKSELADCON0;
MOVLWB’00000001’;Select channel AN0
MOVWFADCON0;Turn ADC On
CALLSampleTime;Acquisiton delay
BSF ADCON0,ADGO;Start conversion
BTFSCADCON0,ADGO;Is conversion done?
GOTO$-1 ;No, test again
BANKSELADRESH;
MOVFADRESH,W;Read upper 2 bits
MOVWFRESULTHI;store in GPR space
BANKSELADRESL;
MOVFADRESL,W;Read lower 8 bits
MOVWFRESULTLO;Store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 20.3 “ADC Acquisition Requirements”.
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20.3
ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 20-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 20-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 20-1:
Assumptions:
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an ADC acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 20-1 may be
used. This equation assumes that 1/2 LSb error is used
(1024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + Temperature - 25°C 0.05µs/°C
The value for TC can be approximated with the following equations:
1
V APPLIED 1 – -------------------------- = V CHOLD
n+1
2
–1
;[1] VCHOLD charged to within 1/2 lsb
–T C
----------
RC
V APPLIED 1 – e = V CHOLD
;[2] VCHOLD charge response to VAPPLIED
– Tc
---------
RC
1
;combining [1] and [2]
V APPLIED 1 – e = V APPLIED 1 – -------------------------
n+1
2
–1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD R IC + R SS + R S ln(1/2047)
= – 10pF 1k + 7k + 10k ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2µs + 1.37 + 50°C- 25°C 0.05µs/°C
= 4.62µs
Note 1: The VAPPLIED has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
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FIGURE 20-4:
ANALOG INPUT MODEL
Rev. 10-000070A
8/23/2016
VDD
RS
Analog
Input pin
VT § 0.6V
RIC 1K
Sampling
switch
SS
RSS
ILEAKAGE(1)
VA
Legend: CHOLD
CPIN
ILEAKAGE
RIC
RSS
SS
VT
RS
CPIN
5pF
CHOLD = 10 pF
VT § 0.6V
Ref-
= Sample/Hold Capacitance
= Input Capacitance
= Leakage Current at the pin due to varies injunctions
= Interconnect Resistance
= Resistance of Sampling switch
= Sampling Switch
= Threshold Voltage
= Source Resistance
VDD
6V
5V
4V
3V
2V
RSS
5 6 7 8 9 10 11
Sampling Switch
(k )
Note 1: See Refer to Section 37.0 “Electrical Specifications”.
FIGURE 20-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB
Ref-
2016-2018 Microchip Technology Inc.
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
Ref+
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20.4
Register Definitions: ADC Control
REGISTER 20-1:
R/W-0/0
ADCON0: ADC CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
CHS: Analog Channel Select bits
111111 = FVR Buffer 2 reference voltage(2)
111110 = FVR 1Buffer 1 reference voltage(2)
111101 = DAC1 output voltage(1)
111100 = Temperature sensor output(3)
111011 = AVSS (Analog Ground)
111010-100000 = Reserved. No channel connected
101111 = RF7
101110 = RF6
101101 = RF5
101100 = RF4
101011 = RF3
101010 = RF2
101001 = RF1
101000 = RF0
100010 = RE2
100001 = RE1
100000 = RE0
011111 = RD7
011110 = RD6
011101 = RD5
011100 = RD4
011011 = RD3
011010 = RD2
011001 = RD1
011000 = RD0
010111 = RC7
010110 = RC6
010101 = RC5
010100 = RC4
010011 = RC3
010010 = RC2
010001 = RC1
010000 = RC0
001111 = RB7
001110 = RB6
001101 = RB5
001100 = RB4
001011 = RB3
001010 = RB2
001001 = RB1
001000 = RB0
000111 = RA7(4)
000110 = RA6(4)
000101 = RA5
000100 = RA4
000011 = RA3
000010 = RA2
000001 = RA1
000000 = RA0
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REGISTER 20-1:
ADCON0: ADC CONTROL REGISTER 0 (CONTINUED)
bit 1
GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note
1:
2:
3:
4:
See Section 21.0 “5-Bit Digital-to-Analog Converter (DAC1) Module” for more information.
See Section 18.0 “Fixed Voltage Reference (FVR)” for more information.
See Section 19.0 “Temperature Indicator Module” for more information.
The analog channel functionality on these pins is disabled when the system clock source is selected is external.
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REGISTER 20-2:
R/W-0/0
ADCON1: ADC CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS
U-0
U-0
—
—
R/W-0/0
bit 7
R/W-0/0
ADPREF
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: ADC Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS: ADC Conversion Clock Select bits
111 =ADCRC (dedicated RC oscillator)
110 =FOSC/64
101 =FOSC/16
100 =FOSC/4
011 =ADCRC (dedicated RC oscillator)
010 =FOSC/32
001 =FOSC/8
000 =FOSC/2
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADPREF: ADC Positive Voltage Reference Configuration bits
11 =VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1)
10 =VREF+ is connected to external VREF+ pin(1)
01 =Reserved
00 =VREF+ is connected to VDD
Note 1:
When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Table 37-14 for details.
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REGISTER 20-3:
ADACT: A/D AUTO-CONVERSION TRIGGER
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADACT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
ADACT: Auto-Conversion Trigger Selection bits(1) (see Table 20-2)
Note 1:
This is a rising edge sensitive input for all sources.
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REGISTER 20-4:
R/W-x/u
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES: ADC Result Register bits
Upper eight bits of 10-bit conversion result
REGISTER 20-5:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
ADRES
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
ADRES: ADC Result Register bits
Lower two bits of 10-bit conversion result
bit 5-0
Reserved: Do not use.
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REGISTER 20-6:
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
—
R/W-x/u
R/W-x/u
ADRES
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Reserved: Do not use.
bit 1-0
ADRES: ADC Result Register bits
Upper two bits of 10-bit conversion result
REGISTER 20-7:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES: ADC Result Register bits
Lower eight bits of 10-bit conversion result
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TABLE 20-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
—
—
—
—
—
INTEDG
147
PIE1
OSFIE
CSWIE
—
—
—
—
—
ADIE
149
PIR1
OSFIF
CSWIF
—
—
—
—
—
ADIF
157
TRISA4
—
TRISA2
TRISA1
TRISA0
201
TRISA3
TRISA2
TRISA1
TRISA0
201
TRISA
—
—
TRISA5
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
(1)
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
207
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
207
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
212
TRISD
TRISD7(1)
TRISD6(1)
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
217
TRISE
TRISE7(1)
TRISE6(1)
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
223
TRISF
TRISF7(1)
TRISF6(1)
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
229
—
—
ANSA5
ANSA4
—
ANSA2
ANSA1
ANSA0
202
ANSELA
(1)
ANSELB
—
—
—
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
208
ANSELA
ANSA7
ANSA6
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
202
ANSELB
ANSB7
ANSB6
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
208
ANSELC
ANSC7(1)
ANSC6(1)
ANSC5
ANSC4
ANSC3
ANSC2
ANSC1
ANSC0
213
ANSELD
ANSD7(1)
ANSD6(1)
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
218
ANSELE
ANSE7(1)
ANSE6(1)
ANSE5
ANSE4
ANSE3
ANSE2
ANSE1
ANSE0
224
ANSELF
ANSF7(1)
ANSF6(1)
ANSF5
ANSF4
ANSF3
ANSF2
ANSF1
ANSF0
230
GO/DONE
ADON
—
—
ADCON0
CHS
ADCON1
ADFM
—
ADACT
ADCS
—
—
ADACT
ADRESH
ADRESH
ADRESL
ADRESL
FVRCON
FVREN
FVRRDY
TSEN
DAC1CON1
—
—
—
OSCSTAT1
EXTOR
HFOR
MFOR
TSRNG
281
282
CDAFVR
ADFVR
DAC1R
LFOR
SOR
278
280
282
ADOR
Legend:
Note 1:
— = unimplemented read as ‘0’. Shaded cells are not used for the ADC module.
Present on only.
Legend:
— = unimplemented read as ‘0’. Shaded cells are not used for the ADC module.
2016-2018 Microchip Technology Inc.
ADPREF
265
288
—
PLLR
138
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21.0
5-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC1) MODULE
21.1
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 32 selectable output levels.
Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels
are set with the DAC1R bits of the DAC1CON1
register.
The DAC output voltage is determined by Equation 21-1:
The input of the DAC can be connected to:
• External VREF pins
• VDD supply voltage
• FVR (Fixed Voltage Reference)
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DAC1OUT pin
The Digital-to-Analog Converter (DAC) is enabled by
setting the DAC1EN bit of the DAC1CON0 register.
EQUATION 21-1:
DAC OUTPUT VOLTAGE
V
OUT
V
V
21.2
=
4:0
----------------------------------- + V
VSOURCE+ – VSOURCE- DAC1R
SOURCE5
2
SOURCE+
SOURCE-
= V
= V
DD
SS
or V
REF+
or FVR
or V REF-
Ratiometric Output Level
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 37-15.
21.3
DAC Voltage Reference Output
The DAC voltage can be output to the DAC1OUT1/2
pins by setting the DAC1OE1/2 bits of the DAC1CON0
register, respectively. Selecting the DAC reference
voltage for output on the DAC1OUT1/2 pins
automatically overrides the digital output buffer and
digital input threshold detector functions, disables the
weak pull-up, and disables the current-controlled drive
function of that pin. Reading the DAC1OUT1/2 pin
when it has been configured for DAC reference voltage
output will always return a ‘0’.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to the DAC1OUT1/2 pins.
Figure 21-2 shows an example buffering technique.
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FIGURE 21-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Rev. 10-000026G
12/15/2016
Reserved
11
FVR Buffer
10
VSOURCE+
R
01
VREF+
DACR
5
00
VDD
R
DACPSS
R
32-to-1 MUX
R
32
Steps
DACEN
DACx_output
To Peripherals
R
DACxOUT1(1)
R
DACOE1
R
DACxOUT2(1)
1
VREF-
DACOE2
VSOURCE-
0
VSS
DACNSS
Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).
FIGURE 21-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
Voltage
Reference
Output
Impedance
2016-2018 Microchip Technology Inc.
DAC1OUT
+
–
Buffered DAC Output
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21.4
Operation During Sleep
The DAC continues to function during Sleep. When the
device wakes up from Sleep through an interrupt or a
Watchdog Timer time-out, the contents of the
DAC1CON0 register are not affected.
21.5
Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DAC1OUT1/2 pins.
• The DAC1R range select bits are cleared.
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21.6
Register Definitions: DAC Control
REGISTER 21-1:
DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
DAC1EN
—
DAC1OE1
DAC1OE2
R/W-0/0
R/W-0/0
U-0
R/W-0/0
—
DAC1NSS
DAC1PSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
DAC1EN: DAC1 Enable bit
1 = DAC is enabled
0 = DAC is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
DAC1OE1: DAC1 Voltage Output 1 Enable bit
1 = DAC voltage level is an output on the DAC1OUT1 pin
0 = DAC voltage level is disconnected from the DAC1OUT1 pin
bit 4
DAC1OE2: DAC1 Voltage Output 2 Enable bit
1 = DAC voltage level is an output on the DAC1OUT2 pin
0 = DAC voltage level is disconnected from the DAC1OUT2 pin
bit 3-2
DAC1PSS: DAC1 Positive Source Select bits
11 =Reserved, do not use
10 =FVR output
01 =VREF+ pin
00 =VDD
bit 1
Unimplemented: Read as ‘0’
bit 0
DAC1NSS: Read as ‘0’
REGISTER 21-2:
DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DAC1R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
DAC1R: DAC1 Voltage Output Select bits
VOUT = (VSRC+ - VSRC-)*(DAC1R/32) + VSRC
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TABLE 21-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE
Bit 2
—
DAC1NSS
288
DAC1EN
—
DAC1CON1
—
—
—
CM1PSEL
—
—
—
—
—
PCH
308
—
—
—
—
—
PCH
308
DAC1OE1 DAC1OE2
Bit 3
Register
on page
DAC1CON0
Legend:
Bit 4
Bit 0
Bit 6
CM2PSEL
Bit 5
Bit 1
Bit 7
DAC1PSS
DAC1R
288
— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.
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22.0
NUMERICALLY CONTROLLED
OSCILLATOR (NCO) MODULE
The Numerically Controlled Oscillator (NCO) module is
a timer that uses overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple counter
driven timer is that the output frequency resolution
does not vary with the divider value. The NCO is most
useful for application that requires frequency accuracy
and fine resolution at a fixed duty cycle.
Features of the NCO include:
•
•
•
•
•
•
•
20-bit Increment Function
Fixed Duty Cycle mode (FDC) mode
Pulse Frequency (PF) mode
Output Pulse Width Control
Multiple Clock Input Sources
Output Polarity Control
Interrupt Capability
Figure 22-1 is a simplified block diagram of the NCO
module.
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FIGURE 22-1:
NUMERICALLY CONTROLLED OSCILLATOR MODULE SIMPLIFIED BLOCK DIAGRAM
NCOxINCU NCOxINCH NCOxINCL
20
Rev. 10-000028D
3/24/2017
(1)
INCBUFU
INCBUFH
20
INCBUFL
20
1111
NCO_overflow
Adder
20
NCOx Clock
Sources
NCOx_clk
See
NCOxCLK
Register
NCOxACCU NCOxACCH NCOxACCL
20
NCO_interrupt
4
D
Q
D
Q
0
_
1
Q
NxPFM
TRIS bit
NCOxOUT
NxPOL
NCOx_out
EN
S
Q
Ripple
Counter
R
Q
_
R
DS40001866B-page 291
3
NxPWS
Note 1:
To Peripherals
NxOUT
Pulse
Frequency
Mode Circuitry
The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.
PIC16(L)F15356/75/76/85/86
0000
NxCKS
set bit
NCOxIF
Fixed Duty
Cycle Mode
Circuitry
PIC16(L)F15356/75/76/85/86
22.1
NCO OPERATION
The NCO operates by repeatedly adding a fixed value to
an accumulator. Additions occur at the input clock rate.
The accumulator will overflow with a carry periodically,
which is the raw NCO output (NCO_overflow). This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 22-1.
The NCO output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCO
output is then distributed internally to other peripherals
and can be optionally output to a pin. The accumulator
overflow also generates an interrupt (NCO_overflow).
The NCO period changes in discrete steps to create an
average frequency.
EQUATION 22-1:
NCO OVERFLOW FREQUENCY
Clock Frequency Increment ValueF OVERFLOW = NCO
--------------------------------------------------------------------------------------------------------------20
2
22.1.1
NCO CLOCK SOURCES
Clock sources available to the NCO include:
•
•
•
•
•
•
•
•
•
•
HFINTOSC
FOSC
LC1_out
LC2_out
LC3_out
LC4_out
MFINTOSC (500 kHz)
MFINTOSC (32 kHz)
SOSC
CLKR
The NCO clock source is selected by configuring the
N1CKS bits in the NCO1CLK register.
22.1.2
ACCUMULATOR
The accumulator is a 20-bit register. Read and write
access to the accumulator is available through three
registers:
• NCO1ACCL
• NCO1ACCH
• NCO1ACCU
22.1.3
ADDER
22.1.4
INCREMENT REGISTERS
The increment value is stored in three registers making
up a 20-bit incrementer. In order of LSB to MSB they
are:
• NCO1INCL
• NCO1INCH
• NCO1INCU
When the NCO module is enabled, the NCO1INCU and
NCO1INCH registers should be written first, then the
NCO1INCL register. Writing to the NCO1INCL register
initiates the increment buffer registers to be loaded
simultaneously on the second rising edge of the
NCO_clk signal.
The registers are readable and writable. The increment
registers are double-buffered to allow value changes to
be made without first disabling the NCO module.
When the NCO module is disabled, the increment
buffers are loaded immediately after a write to the
increment registers.
Note: The increment buffer registers are not useraccessible.
The NCO Adder is a full adder, which operates
synchronously from the source clock. The addition of
the previous result and the increment value replaces
the accumulator value on the rising edge of each input
clock.
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22.2
FIXED DUTY CYCLE MODE
In Fixed Duty Cycle (FDC) mode, every time the
accumulator overflows (NCO_overflow), the output is
toggled at a frequency rate half of the FOVERFLOW. This
provides a 50% duty cycle, provided that the increment
value remains constant. For more information, see
Figure 22-2.
22.5
Interrupts
When the accumulator overflows (NCO_overflow), the
NCO Interrupt Flag bit, NCO1IF, of the PIR7 register is
set. To enable the interrupt event (NCO_interrupt), the
following bits must be set:
The FDC mode is selected by clearing the N1PFM bit
in the NCO1CON register.
•
•
•
•
22.3
The interrupt must be cleared by software by clearing
the NCO1IF bit in the Interrupt Service Routine.
PULSE FREQUENCY MODE
In Pulse Frequency (PF) mode, every time the
Accumulator overflows, the output becomes active for
one or more clock periods. Once the clock period
expires, the output returns to an inactive state. This
provides a pulsed output. The output becomes active
on the rising clock edge immediately following the
overflow event. For more information, see Figure 22-2.
The value of the active and inactive states depends on
the polarity bit, N1POL in the NCO1CON register.
The PF mode is selected by setting the N1PFM bit in
the NCO1CON register.
22.3.1
OUTPUT PULSE WIDTH CONTROL
When operating in PF mode, the active state of the output can vary in width by multiple clock periods. Various
pulse widths are selected with the N1PWS bits in
the NCO1CLK register.
When the selected pulse width is greater than the
Accumulator overflow time frame, then NCO1 output
does not toggle.
22.4
N1EN bit of the NCO1CON register
NCO1IE bit of the PIE7 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
22.6
Effects of a Reset
All of the NCO registers are cleared to zero as the
result of a Reset.
22.7
Operation in Sleep
The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
OUTPUT POLARITY CONTROL
The last stage in the NCO module is the output polarity.
The N1POL bit in the NCO1CON register selects the
output polarity. Changing the polarity while the
interrupts are enabled will cause an interrupt for the
resulting output transition.
The NCO output signal (NCO1_out) is available to the
following peripherals:
•
•
•
•
•
CLC
CWG
Timer1
Timer2
CLKR
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FIGURE 22-2:
FDC OUTPUT MODE OPERATION DIAGRAM
Rev. 10-000029A
11/7/2013
NCOx
Clock
Source
NCOx
Increment
Value
NCOx
Accumulator
Value
NCO_interrupt
NCOx Output
FDC Mode
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NCOx Output
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
001
00000h 04000h 08000h
4000h
FC000h 00000h 04000h 08000h
4000h
FC000h 00000h 04000h 08000h
PIC16(L)F15356/75/76/85/86
NCO_overflow
4000h
PIC16(L)F15356/75/76/85/86
22.8
NCO Control Registers
REGISTER 22-1:
NCO1CON: NCO CONTROL REGISTER
R/W-0/0
U-0
R-0/0
R/W-0/0
U-0
U-0
U-0
R/W-0/0
N1EN
—
N1OUT
N1POL
—
—
—
N1PFM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
N1EN: NCO1 Enable bit
1 = NCO1 module is enabled
0 = NCO1 module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
N1OUT: NCO1 Output bit
Displays the current output value of the NCO1 module.
bit 4
N1POL: NCO1 Polarity bit
1 = NCO1 output signal is inverted
0 = NCO1 output signal is not inverted
bit 3-1
Unimplemented: Read as ‘0’
bit 0
N1PFM: NCO1 Pulse Frequency Mode bit
1 = NCO1 operates in Pulse Frequency mode
0 = NCO1 operates in Fixed Duty Cycle mode, divide by 2
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REGISTER 22-2:
R/W-0/0
NCO1CLK: NCO1 INPUT CLOCK CONTROL REGISTER
R/W-0/0
R/W-0/0
N1PWS(1,2)
U-0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
N1CKS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
N1PWS: NCO1 Output Pulse Width Select bits(1)
111 = NCO1 output is active for 128 input clock periods
110 = NCO1 output is active for 64 input clock periods
101 = NCO1 output is active for 32 input clock periods
100 = NCO1 output is active for 16 input clock periods
011 = NCO1 output is active for 8 input clock periods
010 = NCO1 output is active for 4 input clock periods
001 = NCO1 output is active for 2 input clock periods
000 = NCO1 output is active for 1 input clock period
bit 4
Unimplemented: Read as ‘0’
bit 3-0
N1CKS: NCO1 Clock Source Select bits
1011-1111 = Reserved
1010 = LC4_out
1001 = LC3_out
1000 = LC2_out
0111 = LC1_out
0110 = CLKR
0101 = SOSC
0100 = MFINTOSC (32 kHz)
0011 = MFINTOSC (500 kHz)
0010 = LFINTOSC
0001 = HFINTOSC
0000 = FOSC
Note 1: N1PWS applies only when operating in Pulse Frequency mode.
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REGISTER 22-3:
R/W-0/0
NCO1ACCL: NCO1 ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1ACC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCO1ACC: NCO1 Accumulator, Low Byte
REGISTER 22-4:
R/W-0/0
NCO1ACCH: NCO1 ACCUMULATOR REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1ACC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NOC1ACC: NCO1 Accumulator, High Byte
NCO1ACCU: NCO1 ACCUMULATOR REGISTER – UPPER BYTE(1)
REGISTER 22-5:
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1ACC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
NCO1ACC: NCO1 Accumulator, Upper Byte
Note 1:
The accumulator spans registers NCO1ACCU:NCO1ACCH: NCO1ACCL. The 24 bits are reserved but
not all are used.This register updates in real-time, asynchronously to the CPU; there is no provision to
guarantee atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is
operating will produce undefined results.
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NCO1INCL: NCO1 INCREMENT REGISTER – LOW BYTE(1,2)
REGISTER 22-6:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
NCO1INC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
2:
NCO1INC: NCO1 Increment, Low Byte
The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
NCO1INC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after
writing to NCO1INCL; NCO1INCU and NCO1INCH should be written prior to writing NCO1INCL.
NCO1INCH: NCO1 INCREMENT REGISTER – HIGH BYTE(1)
REGISTER 22-7:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1INC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
NCO1INC: NCO1 Increment, High Byte
The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
NCO1INCU: NCO1 INCREMENT REGISTER – UPPER BYTE(1)
REGISTER 22-8:
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1INC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
NCO1INC: NCO1 Increment, Upper Byte
Note 1:
The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
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TABLE 22-1:
Name
INTCON
PIR7
PIE7
NCO1CON
SUMMARY OF REGISTERS ASSOCIATED WITH NCO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
―
―
―
―
―
INTEDG
147
—
—
NVMIF
NCO1IF
—
—
—
CWG1IF
163
—
—
NVMIE
NCO1IE
—
—
—
CWG1IE
155
N1EN
―
N1OUT
N1POL
―
―
―
N1PFM
295
NCO1CLK
N1PWS
―
N1CKS
296
NCO1ACCL
NCO1ACC
297
NCO1ACCH
NCO1ACC
297
NCO1ACCU
―
―
―
―
NCO1ACC
297
NCO1INCL
NCO1INC
298
NCO1INCH
NCO1INC
298
NCO1INCU
―
―
―
RxyPPS
―
―
―
Legend:
―
NCO1AINC
RxyPPS
298
243
— = unimplemented read as ‘0’. Shaded cells are not used for NCO module.
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23.0
COMPARATOR MODULE
FIGURE 23-1:
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
•
•
•
•
•
VIN+
+
VIN-
–
Output
VINVIN+
Programmable input selection
Selectable voltage reference
Programmable output polarity
Rising/falling output edge interrupts
CWG1 Auto-shutdown source
23.1
SINGLE COMPARATOR
Output
Comparator Overview
A single comparator is shown in Figure 23-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
The comparators available are shown in Table 23-1.
TABLE 23-1:
AVAILABLE COMPARATORS
Device
PIC16(L)F15356/75/76/85/86
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C1
C2
●
●
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FIGURE 23-2:
COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000027K
11/20/2015
CxNCH
3
CxON
CxIN0-
000
CxIN1-
001
CxIN2-
010
CxIN3-
011
Reserved
100
Reserved
101
FVR_buffer2
110
(1)
CxON(1)
CxVN
Interrupt
Rising
Edge
CxINTP
Interrupt
Falling
Edge
CxINTN
set bit
CxIF
-
D
CxOUT
Q
MCxOUT
Cx
CxVP
+
111
Q1
CxSP CxHYS
CxPOL
CxOUT_sync
CxIN0+
000
CxIN1+
001
CxSYNC
Reserved
011
Reserved
100
DAC_output
101
FVR_buffer2
110
TRIS bit
0
PPS
010
Reserved
to
peripherals
D
(From Timer1 Module) T1CLK
Q
CxOUT
1
RxyPPS
111
CxPCH
Note 1:
2
CxON(1)
When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.
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23.2
Comparator Control
Each comparator has two control registers: CMxCON0
and CMxCON1.
The CMxCON0 register (see Register 23-1) contains
Control and Status bits for the following:
•
•
•
•
•
Enable
Output
Output polarity
Hysteresis enable
Timer1 output synchronization
The CMxCON1 register (see Register 23-2) contains
Control bits for the following:
• Interrupt on positive/negative edge enables
23.2.1
COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
23.2.2
23.2.3
COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 23-2 shows the output state versus input
conditions, including polarity control.
TABLE 23-2:
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
CxPOL
CxOUT
CxVN > CxVP
0
0
CxVN < CxVP
0
1
CxVN > CxVP
1
1
CxVN < CxVP
1
0
COMPARATOR OUTPUT
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register.
The comparator output can also be routed to an
external pin through the RxyPPS register (Register 152). The corresponding TRIS bit must be clear to enable
the pin as an output.
Note 1: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external outputs are not latched.
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23.3
Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
Note:
See Comparator Specifications in Table 37-14 for more
information.
23.4
Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 26.6 “Timer Gate” for more information. This
feature is useful for timing the duration or interval of an
analog event.
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
23.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
23.6
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
Comparator Positive Input
Selection
Configuring the CxPCH bits of the CMxPCH
register directs an internal voltage reference or an
analog pin to the noninverting input of the comparator:
•
•
•
•
CxIN0+ analog pin
DAC output
FVR (Fixed Voltage Reference)
VSS (Ground)
The output from a comparator can be synchronized
with Timer1 by setting the CxSYNC bit of the
CMxCON0 register.
See Section 18.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 23-2) and the Timer1 Block
Diagram (Figure 26-1) for more information.
See Section 21.0 “5-Bit Digital-to-Analog Converter
(DAC1) Module” for more information on the DAC
input signal.
23.5
Comparator Interrupt
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
register
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
2016-2018 Microchip Technology Inc.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
23.7
Comparator Negative Input
Selection
The CxNCH bits of the CMxNCH register direct
an analog input pin and internal reference voltage or
analog ground to the inverting input of the comparator:
• CxINy - pin
• FVR (Fixed Voltage Reference)
• Analog Ground
Note:
To use CxINy+ and CxINy- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the corresponding TRIS bits must also be set to disable
the output drivers.
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23.8
Comparator Response Time
23.9
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Table 37-14 for more
details.
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 23-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
FIGURE 23-3:
ANALOG INPUT MODEL
VDD
Rs < 10K
Analog
Input
pin
VT 0.6V
RIC
To Comparator
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
= Interconnect Resistance
= Source Impedance
RS
VA
= Analog Voltage
VT
= Threshold Voltage
Note 1: See I/O Ports in Table 37-4.
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23.10 CWG1 Auto-shutdown Source
The output of the comparator module can be used as
an auto-shutdown source for the CWG1 module. When
the output of the comparator is active and the
corresponding ASxE is enabled, the CWG operation
will be suspended immediately (see Section 30.10
“Auto-Shutdown”).
23.11 Operation in Sleep Mode
The comparator module can operate during Sleep. The
comparator clock source is based on the Timer1 clock
source. If the Timer1 clock source is either the system
clock (FOSC) or the instruction clock (FOSC/4), Timer1
will not operate during Sleep, and synchronized
comparator outputs will not operate.
A comparator interrupt will wake the device from Sleep.
The CxIE bits of the PIE2 register must be set to enable
comparator interrupts.
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23.12 Register Definitions: Comparator Control
REGISTER 23-1:
CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0
R-0/0
U-0
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
ON
OUT
—
POL
—
—
HYS
SYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6
OUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (noninverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5
Unimplemented: Read as ‘0’
bit 4
POL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3-2
Unimplemented: Read as ‘0’
bit 1
HYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0
SYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous
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REGISTER 23-2:
CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
—
—
—
—
—
—
INTP
INTN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
INTP: Comparator Interrupt on Positive-Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive-going edge of the CxOUT bit
bit 0
INTN: Comparator Interrupt on Negative-Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative-going edge of the CxOUT bit
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REGISTER 23-3:
CMxNCH: COMPARATOR Cx NEGATIVE INPUT SELECT REGISTER
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
NCH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
NCH: Comparator Negative Input Channel Select bits
111 =CxVN connects to AVSS
110 =CxVN connects to FVR Buffer 2
101 =CxVN unconnected
100 =CxVN unconnected
011 =CxVN connects to CxIN3- pin
010 =CxVN connects to CxIN2- pin
001 =CxVN connects to CxIN1- pin
000 =CxVN connects to CxIN0- pin
REGISTER 23-4:
CMxPCH: COMPARATOR Cx POSITIVE INPUT SELECT REGISTER
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
PCH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
PCH: Comparator Positive Input Channel Select bits
111 =CxVP connects to AVSS
110 =CxVP connects to FVR Buffer 2
101 =CxVP connects to DAC output
100 =CxVP unconnected
011 =CxVP unconnected
010 =CxVP unconnected
001 =CxVP connects to CxIN1+ pin
000 =CxVP connects to CxIN0+ pin
2016-2018 Microchip Technology Inc.
DS40001866B-page 308
PIC16(L)F15356/75/76/85/86
REGISTER 23-5:
CMOUT: COMPARATOR OUTPUT REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R-0/0
R-0/0
—
—
—
—
—
—
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
MC2OUT: Mirror Copy of C2OUT bit
bit 0
MC1OUT: Mirror Copy of C1OUT bit
TABLE 23-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 1
Bit 0
Register
on Page
—
HYS
SYNC
306
—
INTP
INTN
307
—
MC2OUT
MC1OUT
309
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CMxCON0
ON
OUT
—
POL
—
CMxCON1
—
—
—
—
—
CMOUT
—
—
—
—
—
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR
DAC1EN
—
DAC1OE1
DAC1OE2
DAC1PSS
FVRCON
DAC1CON0
DAC1CON1
ADFVR
—
265
DAC1NSS
288
INTEDG
147
—
—
—
GIE
PEIE
—
PIE2
—
ZCDIE
—
—
—
PIR2
—
ZCDIF
—
—
—
RxyPPS
―
―
―
CLCINxPPS
—
—
CLCIN0PPS
242
―
―
T1GPPS
242
INTCON
T1GPPS
Legend:
DAC1R
288
—
C2IE
C1IE
150
—
C2IF
C1IF
158
RxyPPS
243
— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
2016-2018 Microchip Technology Inc.
DS40001866B-page 309
PIC16(L)F15356/75/76/85/86
24.0
ZERO-CROSS DETECTION
(ZCD) MODULE
The ZCD module detects when an A/C signal crosses
through the ground potential. The actual zero crossing
threshold is the zero crossing reference voltage,
VCPINV, which is typically 0.75V above ground.
The connection to the signal to be detected is through
a series current limiting resistor. The module applies a
current source or sink to the ZCD pin to maintain a
constant voltage on the pin, thereby preventing the pin
voltage from forward biasing the ESD protection
diodes. When the applied voltage is greater than the
reference voltage, the module sinks current. When the
applied voltage is less than the reference voltage, the
module sources current. The current source and sink
action keeps the pin voltage constant over the full
range of the applied voltage. The ZCD module is
shown in the simplified block diagram Figure 24-2.
The ZCD module is useful when monitoring an A/C
waveform for, but not limited to, the following purposes:
•
•
•
•
A/C period measurement
Accurate long term time measurement
Dimmer phase delayed drive
Low EMI cycle switching
2016-2018 Microchip Technology Inc.
24.1
External Resistor Selection
The ZCD module requires a current limiting resistor in
series with the external voltage source. The impedance
and rating of this resistor depends on the external
source peak voltage. Select a resistor value that will drop
all of the peak voltage when the current through the
resistor is nominally 300 A. Refer to Equation 24-1 and
Figure 24-1. Make sure that the ZCD I/O pin internal
weak pull-up is disabled so it does not interfere with the
current source and sink.
EQUATION 24-1:
EXTERNAL RESISTOR
V PEAKR SERIES = ---------------–4
3 10
FIGURE 24-1:
VPEAK
EXTERNAL VOLTAGE
VMAXPEAK
VMINPEAK
VCPINV
DS40001866B-page 310
PIC16(L)F15356/75/76/85/86
FIGURE 24-2:
SIMPLIFIED ZCD BLOCK DIAGRAM
VPULLUP
Rev. 10-000194D
6/10/2016
optional
VDD
-
Zcpinv
RPULLUP
ZCDxIN
RSERIES
RPULLDOWN
+
External
voltage
source
optional
ZCD Output for other modules
ZCDxPOL
ZCDxOUT pin
Interrupt
det
ZCDxINTP
ZCDxINTN
Set
ZCDxIF
flag
Interrupt
det
2016-2018 Microchip Technology Inc.
DS40001866B-page 311
PIC16(L)F15356/75/76/85/86
24.2
ZCD Logic Output
24.5
Correcting for VCPINV offset
The ZCD module includes a Status bit, which can be
read to determine whether the current source or sink is
active. The OUT bit of the ZCDxCON register is set
when the current sink is active, and cleared when the
current source is active. The OUT bit is affected by the
polarity even if the module is disabled.
The actual voltage at which the ZCD switches is the
reference voltage at the noninverting input of the ZCD
op amp. For external voltage source waveforms other
than square waves, this voltage offset from zero
causes the zero-cross event to occur either too early or
too late.
24.3
24.5.1
ZCD Logic Polarity
The POL bit of the ZCDxCON register inverts the
ZCDxOUT bit relative to the current source and sink
output. When the POL bit is set, a logic '1' on the OUT
bit indicates that the current source is active, and a
logic '0' on the OUT bit indicates that the current sink is
active. When the POL bit is clear, a logic '1' on the OUT
bit indicates that the current sink is active, and a logic
'0' on the OUT bit indicates that the current source is
active.
The POL bit affects the ZCD interrupts. See
Section 24.4 “ZCD Interrupts”.
24.4
ZCD Interrupts
An interrupt will be generated upon a change in the
ZCD logic output when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in the ZCD for this purpose.
The ZCDIF bit of the PIR2 register will be set when
either edge detector is triggered and its associated
enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts.
Both are located in the ZCDxCON register.
CORRECTION BY AC COUPLING
When the external voltage source is sinusoidal then the
effects of the VCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a
capacitor in addition to the voltage reducing resistor.
The capacitor will cause a phase shift resulting in the
ZCD output switch in advance of the actual zero crossing event. The phase shift will be the same for both rising and falling zero crossings, which can be
compensated for by either delaying the CPU response
to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift
is negligible.
To determine the series resistor and capacitor values
for this configuration, start by computing the impedance, Z, to obtain a peak current of 300 uA. Next, arbitrarily select a suitably large non-polar capacitor and
compute its reactance, Xc, at the external voltage
source frequency. Finally, compute the series resistor,
capacitor peak voltage, and phase shift by the formulas
shown in Equation 24-2.
EQUATION 24-2:
R-C CALCULATIONS
VPEAK = external voltage source peak voltage
To fully enable the interrupt, the following bits must be set:
f = external voltage source frequency
• ZCDIE bit of the PIE2 register
• INTP bit of the ZCDxCON register
(for a rising edge detection)
• INTN bit of the ZCDxCON register
(for a falling edge detection)
• PEIE and GIE bits of the INTCON register
C = series capacitor
Changing the POL bit can cause an interrupt,
regardless of the level of the EN bit.
The ZCDIF bit of the PIR2 register must be cleared in
software as part of the interrupt service. If another edge
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence.
R = series resistor
VC = Peak capacitor voltage
= Capacitor induced zero crossing phase advance
in radians
T = Time ZC event occurs before actual zero
crossing
Z = VPEAK/3x10-4
Xc = 1/(2fC)
R = (Z2 - Xc2)
VC = Xc(3x10-4)
= Tan-1(Xc/R)
T = /(2f)
2016-2018 Microchip Technology Inc.
DS40001866B-page 312
PIC16(L)F15356/75/76/85/86
EXAMPLE 24-1:
VRMS = 120
VPEAK =VRMS*
f = 60 Hz
C = 0.1 uF
Z = VPEAK/3x10-4 = 169.7/(3x10-4) = 565.7 kOhms
Xc = 1/(2fC) = 1/(2*60*1*10-7) = 26.53 kOhms
R = (Z2 - Xc2) = 565.1 kOhms (computed)
R = 560 kOhms (used)
This offset time can be compensated for by adding a
pull-up or pull-down biasing resistor to the ZCD pin. A
pull-up resistor is used when the external voltage
source is varying relative to VSS. A pull-down resistor is
used when the voltage is varying relative to VDD. The
resistor adds a bias to the ZCD pin so that the target
external voltage source must go to zero to pull the pin
voltage to the VCPINV switching voltage. The pull-up or
pull-down value can be determined with the equation
shown in Equation 24-4.
EQUATION 24-4:
ZCD PULL-UP/DOWN
ZR = (R2 + Xc2) = 560.6 kOhms (using actual resistor)
IPEAK = VPEAK/ ZR = 302.7*10-6
VC = Xc* IPEAK = 8.0 V
= Tan-1(Xc/R) = 0.047 radians
T = /(2f) = 125.6 us
When External Signal is relative to Vss:
R SERIES V PULLUP – V cpinv
R PULLUP = -----------------------------------------------------------------------V cpinv
When External Signal is relative to VDD:
24.5.2
·
SERIES Vcpinv
R PULLDOWN = R
-------------------------------------------------
V DD – Vcpinv
CORRECTION BY OFFSET
CURRENT
When the waveform is varying relative to VSS, then the
zero cross is detected too early as the waveform falls
and too late as the waveform rises. When the
waveform is varying relative to VDD, then the zero cross
is detected too late as the waveform rises and too early
as the waveform falls. The actual offset time can be
determined for sinusoidal waveforms with the
corresponding equations shown in Equation 24-3.
EQUATION 24-3:
ZCD EVENT OFFSET
When External Voltage Source is relative to Vss:
T OFFSET
Vcpinv
asin ------------------
V PEAK
= ---------------------------------2 Freq
When External Voltage Source is relative to VDD:
T OFFSET
V DD – Vcpinv
asin --------------------------------
V PEAK
= ------------------------------------------------2 Freq
2016-2018 Microchip Technology Inc.
24.6
Handling VPEAK variations
If the peak amplitude of the external voltage is
expected to vary, the series resistor must be selected
to keep the ZCD current source and sink below the
design maximum range of ± 600 A and above a
reasonable minimum range. A general rule of thumb is
that the maximum peak voltage can be no more than
six times the minimum peak voltage. To ensure that the
maximum current does not exceed ± 600 A and the
minimum is at least ± 100 A, compute the series
resistance as shown in Equation 24-5. The
compensating pull-up for this series resistance can be
determined with Equation 24-4 because the pull-up
value is not dependent from the peak voltage.
EQUATION 24-5:
SERIES R FOR V RANGE
V MAXPEAK + V MINPEAK
R SERIES = --------------------------------------------------------–4
7 10
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PIC16(L)F15356/75/76/85/86
24.7
Operation During Sleep
The ZCD current sources and interrupts are unaffected
by Sleep.
24.8
Effects of a Reset
The ZCD circuit can be configured to default to the active
or inactive state on Power-on-Reset (POR). When the
ZCDDIS Configuration bit is cleared, the ZCD circuit will
be active at POR. When the ZCD Configuration bit is set,
the EN bit of the ZCDxCON register must be set to
enable the ZCD module.
2016-2018 Microchip Technology Inc.
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24.9
Register Definitions: ZCD Control
REGISTER 24-1:
ZCDCON: ZERO-CROSS DETECTION CONTROL REGISTER
R/W-q/q
U-0
R-x/x
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
SEN
—
OUT
POL
—
—
INTP
INTN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = value depends on Configuration bits
bit 7
SEN: Zero-Cross Detection Enable bit
1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.
0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: Zero-Cross Detection Logic Level bit
POL bit = 1:
1 = ZCD pin is sourcing current
0 = ZCD pin is sinking current
POL bit = 0:
1 = ZCD pin is sinking current
0 = ZCD pin is sourcing current
bit 4
POL: Zero-Cross Detection Logic Output Polarity bit
1 = ZCD logic output is inverted
0 = ZCD logic output is not inverted
bit 3-2
Unimplemented: Read as ‘0’
bit 1
INTP: Zero-Cross Positive Edge Interrupt Enable bit
1 = ZCDIF bit is set on low-to-high ZCDx_output transition
0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition
bit 0
INTN: Zero-Cross Negative Edge Interrupt Enable bit
1 = ZCDIF bit is set on high-to-low ZCDx_output transition
0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition
TABLE 24-1:
SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
PIE2
—
ZCDIE
—
—
—
—
C2IE
C1IE
150
PIR2
—
ZCDIF
—
—
—
—
C2IF
C1IF
158
ZCDxCON
EN
—
OUT
POL
—
—
INTP
INTN
315
Name
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.
TABLE 24-2:
Name
CONFIG2
SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE
Bits Bit -/7
13:8
7:0
—
Bit -/6
Bit 13/5
Bit 12/4
Bit 10/2
Bit 9/1
Bit 8/0
—
DEBUG
STVREN PPS1WAY ZCDDIS
BORV
—
PWRTE
MCLRE
BOREN
LPBOREN
—
Bit 11/3
—
—
Register
on Page
103
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.
2016-2018 Microchip Technology Inc.
DS40001866B-page 315
PIC16(L)F15356/75/76/85/86
25.0
TIMER0 MODULE
The Timer0 module is an 8/16-bit timer/counter with the
following features:
•
•
•
•
•
•
•
•
•
16-bit timer/counter
8-bit timer/counter with programmable period
Synchronous or asynchronous operation
Selectable clock sources
Programmable prescaler (independent of
Watchdog Timer)
Programmable postscaler
Operation during Sleep mode
Interrupt on match or overflow
Output on I/O pin (via PPS) or to other peripherals
25.1
Timer0 Operation
Timer0 can operate as either an 8-bit timer/counter or
a 16-bit timer/counter. The mode is selected with the
T016BIT bit of the T0CON register.
25.1.1
16-BIT MODE
In normal operation, TMR0 increments on the rising
edge of the clock source. A 15-bit prescaler on the
clock input gives several prescale options (see
prescaler control bits, T0CKPS in the T0CON1
register).
25.1.1.1
Timer0 Reads and Writes in 16-Bit
Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0, which is neither directly readable nor
writable (see Figure 25-1). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte was valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
25.1.2
8-BIT MODE
In normal operation, TMR0 increments on the rising
edge of the clock source. A 15-bit prescaler on the
clock input gives several prescale options (see
prescaler control bits, T0CKPS in the T0CON1
register).
2016-2018 Microchip Technology Inc.
The value of TMR0L is compared to that of the Period
buffer, a copy of TMR0H, on each clock cycle. When
the two values match, the following events happen:
• TMR0_out goes high for one prescaled clock
period
• TMR0L is reset
• The contents of TMR0H are copied to the period
buffer
In 8-bit mode, the TMR0L and TMR0H registers are
both directly readable and writable. The TMR0L
register is cleared on any device Reset, while the
TMR0H register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• A write to the TMR0L register
• A write to either the T0CON0 or T0CON1
registers
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
• Brown-out Reset (BOR)
25.1.3
COUNTER MODE
In Counter mode, the prescaler is normally disabled by
setting the T0CKPS bits of the T0CON1 register to
‘0000’. Each rising edge of the clock input (or the
output of the prescaler if the prescaler is used)
increments the counter by ‘1’.
25.1.4
TIMER MODE
In Timer mode, the Timer0 module will increment every
instruction cycle as long as there is a valid clock signal
and the T0CKPS bits of the T0CON1 register
(Register 25-2) are set to ‘0000’. When a prescaler is
added, the timer will increment at the rate based on the
prescaler value.
25.1.5
ASYNCHRONOUS MODE
When the T0ASYNC bit of the T0CON1 register is set
(T0ASYNC = ‘1’), the counter increments with each
rising edge of the input source (or output of the
prescaler, if used). Asynchronous mode allows the
counter to continue operation during Sleep mode
provided that the clock also continues to operate during
Sleep.
25.1.6
SYNCHRONOUS MODE
When the T0ASYNC bit of the T0CON1 register is clear
(T0ASYNC = 0), the counter clock is synchronized to
the system oscillator (FOSC/4). When operating in
Synchronous mode, the counter clock frequency
cannot exceed FOSC/4.
DS40001866B-page 316
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25.2
Clock Source Selection
The T0CS bits of the T0CON1 register are used
to select the clock source for Timer0. Register 25-2
displays the clock source selections.
25.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected, Timer0
operates as a timer and will increment on multiples of
the clock source, as determined by the Timer0
prescaler.
25.2.2
EXTERNAL CLOCK SOURCE
When an external clock source is selected, Timer0 can
operate as either a timer or a counter. Timer0 will
increment on multiples of the rising edge of the external
clock source, as determined by the Timer0 prescaler.
25.3
Programmable Prescaler
A software programmable prescaler is available for
exclusive use with Timer0. There are 16 prescaler
options for Timer0 ranging in powers of two from 1:1 to
1:32768. The prescaler values are selected using the
T0CKPS bits of the T0CON1 register.
The prescaler is not directly readable or writable.
Clearing the prescaler register can be done by writing
to the TMR0L register or the T0CON1 register.
25.4
Programmable Postscaler
A software programmable postscaler (output divider) is
available for exclusive use with Timer0. There are 16
postscaler options for Timer0 ranging from 1:1 to 1:16.
The postscaler values are selected using the
T0OUTPS bits of the T0CON0 register.
The postscaler is not directly readable or writable.
Clearing the postscaler register can be done by writing
to the TMR0L register or the T0CON0 register.
In the 16-bit mode, if the postscaler option is selected
to a ratio other than 1:1, the reload of the TMR0H and
TMR0L registers is not possible inside the Interrupt
Service Routine. The timer period must be calculated
with the prescaler and postscaler factors selected.
2016-2018 Microchip Technology Inc.
25.5
Operation during Sleep
When operating synchronously, Timer0 will halt. When
operating asynchronously, Timer0 will continue to
increment and wake the device from Sleep (if Timer0
interrupts are enabled) provided that the input clock
source is active.
25.6
Timer0 Interrupts
The Timer0 interrupt flag bit (TMR0IF) is set when
either of the following conditions occur:
• 8-bit TMR0L matches the TMR0H value
• 16-bit TMR0 rolls over from ‘FFFFh’
When the postscaler bits (T0OUTPS) are set to
1:1 operation (no division), the T0IF flag bit will be set
with every TMR0 match or rollover. In general, the
TMR0IF flag bit will be set every T0OUTPS +1 matches
or rollovers.
If Timer0 interrupts are enabled (TMR0IE bit of the
PIE0 register = 1), the CPU will be interrupted and the
device may wake from sleep (see Section 25.2 “Clock
Source Selection” for more details).
25.7
Timer0 Output
The Timer0 output can be routed to any I/O pin via the
RxyPPS output selection register (see Section 15.0
“Peripheral Pin Select (PPS) Module” for additional
information). The Timer0 output can also be used by
other peripherals, such as the Auto-conversion Trigger
of the Analog-to-Digital Converter. Finally, the Timer0
output can be monitored through software via the
Timer0 output bit (T0OUT) of the T0CON0 register
(Register 25-1).
TMR0_out will be one postscaled clock period when a
match occurs between TMR0L and TMR0H in 8-bit
mode, or when TMR0 rolls over in 16-bit mode. The
Timer0 output is a 50% duty cycle that toggles on each
TMR0_out rising clock edge.
DS40001866B-page 317
PIC16(L)F15356/75/76/85/86
FIGURE 25-1:
BLOCK DIAGRAM OF TIMER0
Rev. 10-000017D
4/6/2017
CLC1
111
SOSC
110
MFINTOSC
101
T0CKPS
100
LFINTOSC
HFINTOSC
011
FOSC/4
010
PPS
001
Peripherals
TMR0
body
T0OUTPS
T0IF
1
Prescaler
SYNC
0
IN
OUT
TMR0
FOSC/4
T016BIT
T0ASYNC
000
T0_out
Postscaler
Q
D
T0CKIPPS
PPS
RxyPPS
CK Q
3
T0CS
16-bit TMR0 Body Diagram (T016BIT = 1)
8-bit TMR0 Body Diagram (T016BIT = 0)
IN
TMR0L
R
Clear
IN
TMR0L
TMR0 High
Byte
OUT
8
Read TMR0L
COMPARATOR
OUT
Write TMR0L
T0_match
8
8
TMR0H
TMR0 High
Byte
Latch
Enable
8
TMR0H
8
Internal Data Bus
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
25.8
Register Definitions: Timer0 Control
REGISTER 25-1:
T0CON0: TIMER0 CONTROL REGISTER 0
R/W-0/0
U-0
R-0
R/W-0/0
T0EN
—
T0OUT
T016BIT
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T0OUTPS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
T0EN: Timer0 Enable bit
1 = The module is enabled and operating
0 = The module is disabled and in the lowest power mode
bit 6
Unimplemented: Read as ‘0’
bit 5
T0OUT: Timer0 Output bit (read-only)
Timer0 output bit
bit 4
T016BIT: Timer0 Operating as 16-bit Timer Select bit
1 = Timer0 is a 16-bit timer
0 = Timer0 is an 8-bit timer
bit 3-0
T0OUTPS: Timer0 output postscaler (divider) select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler
2016-2018 Microchip Technology Inc.
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REGISTER 25-2:
R/W-0/0
T0CON1: TIMER0 CONTROL REGISTER 1
R/W-0/0
R/W-0/0
T0CS
R/W-0/0
R/W-0/0
T0ASYNC
R/W-0/0
R/W-0/0
R/W-0/0
T0CKPS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
T0CS: Timer0 Clock Source select bits
111 = LC1_out
110 = SOSC
101 = MFINTOSC (500 kHz)
100 = LFINTOSC
011 = HFINTOSC
010 = FOSC/4
001 = T0CKIPPS (Inverted)
000 = T0CKIPPS (True)
bit 4
T0ASYNC: TMR0 Input Asynchronization Enable bit
1 = The input to the TMR0 counter is not synchronized to system clocks
0 = The input to the TMR0 counter is synchronized to FOSC/4
bit 3-0
T0CKPS: Prescaler Rate Select bit
1111 = 1:32768
1110 = 1:16384
1101 = 1:8192
1100 = 1:4096
1011 = 1:2048
1010 = 1:1024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
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TABLE 25-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
TMR0L
Holding Register for the Least Significant Byte of the 16-bit TMR0 Register
316*
TMR0H
Holding Register for the Most Significant Byte of the 16-bit TMR0 Register
316*
T0CON0
T0EN
T0CON1
―
T0OUT
T0CS
T016BIT
T0ASYNC
T0OUTPS
319
T0CKPS
320
T0CKIPPS
―
―
T0CKIPPS
242
TMR0PPS
―
―
TMR0PPS
242
T1GCON
GE
GPOL
GTM
GSPM
GGO/DONE
GVAL
—
—
332
INTCON
GIE
PEIE
―
―
―
―
―
INTEDG
147
PIR0
―
―
TMR0IF
IOCIF
―
―
―
INTF
156
PIE0
―
―
TMR0IE
IOCIE
―
―
―
INTE
148
Legend:
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page with Register information.
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26.0
TIMER1 MODULE WITH GATE
CONTROL
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Auto-conversion Trigger (with CCP)
• Selectable Gate Source Polarity
• Gate Toggle mode
• Gate Single-Pulse mode
• Gate Value Status
• Gate Event Interrupt
The Timer1 module is 16-bit timer/counters with the
following features:
•
•
•
•
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
2-bit prescaler
Clock source for optional comparator
synchronization
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
FIGURE 26-1:
Figure 26-1 is a block diagram of the Timer1 module.
This device has one instance of Timer1 type modules.
TIMER1 BLOCK DIAGRAM
TMRxGATE
Rev. 10-000018J
8/15/2016
4
TxGPPS
TxGSPM
00000
PPS
1
0
NOTE (5)
Single Pulse
Acq. Control
1
11111
D
D
0
Q
TxGVAL
Q1
Q
TxGGO/DONE
TxGPOL
CK
Q
Interrupt
TMRxON
R
set bit
TMRxGIF
det
TxGTM
TMRxGE
set flag bit
TMRxIF
TMRxON
EN
To Comparators (6)
(2)
Tx_overflow
TMRx
TMRxH
TMRxL
Q
Synchronized Clock Input
0
D
1
TxCLK
TxSYNC
TMRxCLK
4
TxCKIPPS
(1)
0000
PPS
Note
Prescaler
1,2,4,8
(4)
1111
det
2
TxCKPS
Note 1:
Synchronize(3)
Fosc/2
Internal
Clock
Sleep
Input
ST Buffer is high speed type when using TxCKIPPS.
2:
TMRx register increments on rising edge.
3:
Synchronize does not operate while in Sleep.
4:
See Register 26-3 for Clock source selections.
5:
See Register 26-4 for GATE source selections.
6:
Synchronized comparator output should not be used in conjunction with synchronized input clock.
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26.1
Timer1 Operation
26.2
The Timer1 modules are 16-bit incrementing counters
which are accessed through the TMR1H:TMR1L
register pairs. Writes to TMR1H or TMR1L directly
update the counter.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and increments on every selected edge of the external source.
The timer is enabled by configuring the TMR1ON and
GE bits in the T1CON and T1GCON registers,
respectively. Table 26-1 displays the Timer1 enable
selections.
TABLE 26-1:
TIMER1 ENABLE
SELECTIONS
Timer1
Operation
TMR1ON
TMR1GE
1
1
Count Enabled
1
0
Always On
0
1
Off
0
0
Off
Clock Source Selection
The T1CLK register is used to select the clock source for
the timer. Register 26-3 shows the possible clock
sources that may be selected to make the timer
increment.
26.2.1
INTERNAL CLOCK SOURCE
When the internal clock source FOSC is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the respective Timer1
prescaler.
When the FOSC internal clock source is selected, the
timer register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the
TMR1H:TMR1L value. To utilize the full resolution of the
timer in this mode, an asynchronous input signal must
be used to gate the timer clock input.
Out of the total timer gate signal sources, the following
subset of sources can be asynchronous and may be
useful for this purpose:
•
•
•
•
•
•
•
•
CLC4 output
CLC3 output
CLC2 output
CLC1 output
Zero-Cross Detect output
Comparator2 output
Comparator1 output
TxG PPS remappable input pin
26.2.2
EXTERNAL CLOCK SOURCE
When the timer is enabled and the external clock input
source (ex: T1CKI PPS remappable input) is selected as
the clock source, the timer will increment on the rising
edge of the external clock input.
When using an external clock source, the timer can be
configured to run synchronously or asynchronously, as
described in Section 26.5 “Timer Operation in
Asynchronous Mode”.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used connected to
the SOSCI/SOSCO pins.
Note:
When using Timer1 to count events, a falling edge must be registered by the
counter prior to the first incrementing rising edge after any one or more of the following conditions:
•The timer is first enabled after POR
•Firmware writes to TMR1H or TMR1L
•The timer is disabled
•The timer is re-enabled (e.g.,
TMR1ON-->1) when the T1CKI
signal is currently logic low.
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26.3
Timer Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
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26.4
Secondary Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins SOSCI (input) and SOSCO
(amplifier output). This internal circuit is designed to be
used in conjunction with an external 32.768 kHz
crystal.
The oscillator circuit is enabled by setting the SOSCEN
bit of the OSCEN register. The oscillator will continue to
run during Sleep.
Note:
26.5
The oscillator requires a start-up and
stabilization time before use. Thus,
SOSCEN should be set and a suitable
delay observed prior to using Timer1 with
the SOSC source. A suitable delay similar
to the OST delay can be implemented in
software by clearing the TMR1IF bit then
presetting the TMR1H:TMR1L register
pair to FC00h. The TMR1IF flag will be set
when 1024 clock cycles have elapsed,
thereby indicating that the oscillator is
running and reasonably stable.
Timer Operation in Asynchronous
Mode
If the control bit SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 26.5.1 “Reading and Writing Timer1 in
Asynchronous Mode”).
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
2016-2018 Microchip Technology Inc.
26.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
26.6
Timer Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using the time gate
circuitry. This is also referred to as Timer Gate Enable.
The timer gate can also be driven by multiple selectable sources.
26.6.1
TIMER GATE ENABLE
The Timer Gate Enable mode is enabled by setting the
GE bit of the T1GCON register. The polarity of the
Timer Gate Enable mode is configured using the GPOL
bit of the T1GCON register.
When Timer Gate Enable signal is enabled, the timer
will increment on the rising edge of the Timer1 clock
source. When Timer Gate Enable signal is disabled,
the timer always increments, regardless of the GE bit.
See Figure 26-3 for timing details.
TABLE 26-2:
TIMER GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G
Timer Operation
1
1
Counts
1
0
Holds Count
0
1
Holds Count
0
0
Counts
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26.6.2
TIMER GATE SOURCE SELECTION
One of the several different external or internal signal
sources may be chosen to gate the timer and allow the
timer to increment. The gate input signal source can be
selected based on the T1GATE register setting. See the
T1GATE register (Register 26-4) description for a
complete list of the available gate sources. The polarity
for each available source is also selectable. Polarity
selection is controlled by the GPOL bit of the T1GCON
register.
26.6.2.1
T1G Pin Gate Operation
The T1G pin is one source for the timer gate control. It
can be used to supply an external source to the time
gate circuitry.
26.6.2.2
Timer0 Overflow Gate Operation
26.6.4
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
GSPM bit in the T1GCON register. Next, the GGO/
DONE bit in the T1GCON register must be set. The
timer will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the GGO/
DONE bit will automatically be cleared. No other gate
events will be allowed to increment the timer until the
GGO/DONE bit is once again set in software. See
Figure 26-5 for timing details.
If the Single-Pulse Gate mode is disabled by clearing the
GSPM bit in the T1GCON register, the GGO/DONE bit
should also be cleared.
When Timer0 overflows, or a period register match
condition occurs (in 8-bit mode), a low-to-high pulse will
automatically be generated and internally supplied to
the Timer1 gate circuitry.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the timer gate
source to be measured. See Figure 26-6 for timing
details.
26.6.2.3
26.6.5
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for the timer gate control. The
Comparator 1 output can be synchronized to the timer
clock or left asynchronous. For more information see
Section 23.4.1
“Comparator
Output
Synchronization”.
26.6.2.4
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for the timer gate control.
The Comparator 2 output can be synchronized to the
timer clock or left asynchronous. For more information
see
Section 23.4.1
“Comparator
Output
Synchronization”.
26.6.3
TIMER1 GATE TOGGLE MODE
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the GVAL bit in the T1GCON register. The GVAL bit is valid even when the timer gate is
not enabled (GE bit is cleared).
26.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of GVAL occurs,
the TMR1GIF flag bit in the PIR5 register will be set. If
the TMR1GIE bit in the PIE5 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the timer
gate is not enabled (TMR1GE bit is cleared).
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a timer gate signal, as opposed to the duration of a single level pulse.
The timer gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 26-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
GTM bit of the T1GCON register. When the GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
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26.7
Timer1 Interrupts
The timer register pair (TMR1H:TMR1L) increments to
FFFFh and rolls over to 0000h. When the timer rolls
over, the respective timer interrupt flag bit of the PIR5
register is set. To enable the interrupt on rollover, you
must set these bits:
•
•
•
•
ON bit of the T1CON register
TMR1IE bit of the PIE4 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
26.8
To avoid immediate interrupt vectoring,
the TMR1H:TMR1L register pair should
be preloaded with a value that is not imminently about to rollover, and the TMR1IF
flag should be cleared prior to enabling
the timer interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
•
•
•
•
•
•
ON bit of the T1CON register must be set
TMR1IE bit of the PIE4 register must be set
PEIE bit of the INTCON register must be set
SYNC bit of the T1CON register must be set
CS bits of the T1CLK register must be configured
The timer clock source must be enabled and
continue operation during sleep. When the SOSC
is used for this purpose, the SOSCEN bit of the
OSCEN register must be set.
26.9
CCP Capture/Compare Time Base
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPRxH:CCPRxL
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPRxH:CCPRxL register pair matches the value in
the TMR1H:TMR1L register pair. This event can be an
Auto-conversion Trigger.
For more information, see Section 28.0 “Capture/
Compare/PWM Modules”.
26.10 CCP Auto-Conversion Trigger
When any of the CCP’s are configured to trigger an
auto-conversion, the trigger will clear the
TMR1H:TMR1L register pair. This auto-conversion
does not cause a timer interrupt. The CCP module may
still be configured to generate a CCP interrupt.
In this mode of operation, the CCPRxH:CCPRxL
register pair becomes the period register for Timer1.
The timer should be synchronized and FOSC/4 should
be selected as the clock source in order to utilize the
Auto-conversion Trigger. Asynchronous operation of
the timer can cause an Auto-conversion Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with an Auto-conversion Trigger from the CCP, the
write will take precedence.
For more information, see Section 28.2.4 “Compare
During Sleep”.
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Secondary oscillator will continue to operate in Sleep
regardless of the SYNC bit setting.
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FIGURE 26-2:
TIMER1 INCREMENTING EDGE
TxCKI = 1
when the timer is
enabled
TxCKI = 0
when the timer is
enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
FIGURE 26-3:
TIMER1 GATE ENABLE MODE
TMRxGE
TxGPOL
Selected
gate input
TxCKI
TxGVAL
TMRxH:TMRxL
Count
N
2016-2018 Microchip Technology Inc.
N+1
N+2
N+3
N+4
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FIGURE 26-4:
TIMER1 GATE TOGGLE MODE
TMRxGE
TxGPOL
TxGTM
Selected
gate input
TxCKI
TxGVAL
TMRxH:TMRxL
Count
FIGURE 26-5:
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
TIMER1 GATE SINGLE-PULSE MODE
TMRxGE
TxGPOL
TxGSPM
TxGGO/
DONE
Cleared by hardware on
falling edge of TxGVAL
Set by software
Counting enabled on
rising edge of selected source
Selected gate
source
TxCKI
TxGVAL
TMRxH:TMRxL
Count
TMRxGIF
N
Cleared by software
2016-2018 Microchip Technology Inc.
N+1
N+2
Set by hardware on
falling edge of TxGVAL
Cleared by
software
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FIGURE 26-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMRxGE
TxGPOL
TxGSPM
TxGTM
TxGGO/
DONE
Cleared by hardware on
falling edge of TxGVAL
Set by software
Counting enabled on
rising edge of selected source
Selected gate
source
TxCKI
TxGVAL
TMRxH:TMRxL
Count
TMRxGIF
N
Cleared by software
2016-2018 Microchip Technology Inc.
N+1
N+2
N+3
N+4
Set by hardware on
falling edge of TxGVAL
Cleared by
software
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26.11 Register Definitions: Timer1 Control
REGISTER 26-1:
T1CON: TIMER1 CONTROL REGISTER
U-0
U-0
—
—
R/W-0/u
R/W-0/u
CKPS
U-0
R/W-0/u
R/W-0/u
R/W-0/u
—
SYNC
RD16
ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
CKPS: Timer1 Input Clock Prescale Select bits
11 =1:8 Prescale value
10 =1:4 Prescale value
01 =1:2 Prescale value
00 =1:1 Prescale value
bit 3
Unimplemented: Read as ‘0’
bit 2
SYNC: Timer1 Synchronization Control bit
When TMR1CLK = FOSC or FOSC/4
This bit is ignored. The timer uses the internal clock and no additional synchronization is performed.
ELSE
0 = Synchronize external clock input with system clock
1 = Do not synchronize external clock input
bit 1
RD16: 16-bit Read/Write Mode Enable bit
0 = Enables register read/write of Timer1 in two 8-bit operation
1 = Enables register read/write of Timer1 in one 16-bit operation
bit 0
ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
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REGISTER 26-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
U-0
U-0
GE
GPOL
GTM
GSPM
GGO/DONE
GVAL
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
GE: Timer1 Gate Enable bit
If ON = 0:
This bit is ignored
If ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 is always counting
bit 6
GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3
GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when GSPM is cleared
bit 2
GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L
Unaffected by Timer1 Gate Enable (GE)
bit 1-0
Unimplemented: Read as ‘0’
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REGISTER 26-3:
T1CLK TIMER1 CLOCK SELECT REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
CS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
CS: Timer1 Clock Select bits
1111 = Reserved
1110 = Reserved
1101 = LC4_out
1100 = LC3_out
1011 = LC2_out
1010 = LC1_out
1001 = Timer0 overflow output
1000 = CLKR output
0111 = SOSC
0110 = MFINTOSC (32 kHz)
0101 = MFINTOSC (500 kHz)
0100 = LFINTOSC
0011 = HFINTOSC
0010 = FOSC
0001 = FOSC/4
0000 = T1CKIPPS
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REGISTER 26-4:
T1GATE TIMER1 GATE SELECT REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
GSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
GSS: Timer1 Gate Select bits
11111-10001 = Reserved
10000 = LC4_out
01111 = LC3_out
01110 = LC2_out
01101 = LC1_out
00100 = ZCD1_output
01011 = C2OUT_sync
01010 = C1OUT_sync
01001 = NCO1_out
01000 = PWM6_out
00111 = PWM5_out
00110 = PWM4_out
00101 = PWM3_out
00100 = CCP2_out
00011 = CCP1_out
00010 = TMR2_postscaled
00001 = Timer0 overflow output
00000 = T1GPPS
2016-2018 Microchip Technology Inc.
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TABLE 26-3:
Name
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
―
―
―
―
―
INTEDG
147
PIE4
—
—
—
—
—
—
TMR2IE
TMR1IE
152
PIR4
—
—
—
—
—
—
TMR2IF
TMR1IF
160
—
SYNC
RD16
ON
331
GGO/DONE
GVAL
—
—
332
T1CON
—
—
T1GCON
GE
GPOL
GTM
T1GATE
—
—
—
—
—
—
T1CLK
CKPS
GSPM
GSS
—
CS
334
333
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
322*
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
322*
T1CKIPPS
―
―
T1CKIPPS
242
T1GPPS
―
―
T1GPPS
242
CCPxCON
CCPxEN
CCPxOE
CLCxSELy
―
―
―
LCxDyS
409
ADACT
―
―
―
ADACT
281
Legend:
*
CCPxOUT CCPxFMT
CCPxMODE
364
— = Unimplemented location, read as ‘0’. Shaded cells are not used with the Timer1 modules.
Page with register information.
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27.0
TIMER2 MODULE WITH
HARDWARE LIMIT TIMER (HLT)
•
•
•
•
•
•
•
The Timer2 module is an 8-bit timer that can operate as
free-running period counters or in conjunction with
external signals that control start, run, freeze, and reset
operation in One-Shot and Monostable modes of
operation. Sophisticated waveform control such as
pulse density modulation are possible by combining the
operation of this timer with other internal peripherals
such as the comparators and CCP modules. Features
of the timer include:
See Figure 27-1 for a block diagram of Timer2. See
Figure 27-2 for the clock source block diagram.
• 8-bit timer register
• 8-bit period register
FIGURE 27-1:
TIMER2 BLOCK DIAGRAM
RSEL
INPPS
TxIN
PPS
External
Reset
(2)
Sources
Selectable external hardware timer Resets
Programmable prescaler (1:1 to 1:128)
Programmable postscaler (1:1 to 1:16)
Selectable synchronous/asynchronous operation
Alternate clock sources
Interrupt-on-period
Three modes of operation:
- Free Running Period
- One-shot
- Monostable
Rev. 10-000168C
9/10/2015
MODE
TMRx_ers
Edge Detector
Level Detector
Mode Control
(2 clock Sync)
MODE
reset
CCP_pset(1)
MODE=01
enable
D
MODE=1011
Q
Clear ON
CPOL
0
Prescaler
TMRx_clk
T[7MR
3
CKPS
Sync
1
Fosc/4
PSYNC
R
Comparator
Set flag bit
TMRxIF
Postscaler
TMRx_postscaled
4
Sync
(2 Clocks)
ON
1
7[PR
OUTPS
0
CSYNC
Note 1:
2:
Signal to the CCP to trigger the PWM pulse.
See Register 27-4 for external Reset sources.
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FIGURE 27-2:
TIMER2 CLOCK SOURCE
BLOCK DIAGRAM
TxCLKCON
Rev. 10-000 169B
5/29/201 4
TXINPPS
TXIN
27.1.2
PPS
Timer Clock Sources
(See Table 27-2)
the output postscaler counter. When the postscaler
count equals the value in the OUTPS bits of the
TMR2CON1 register, a one TMR2_clk period wide pulse
occurs on the TMR2_postscaled output, and the
postscaler count is cleared.
TMR2_clk
The One-Shot mode is identical to the Free Running
Period mode except that the ON bit is cleared and the
timer is stopped when TMR2 matches PR2 and will not
restart until the T2ON bit is cycled off and on.
Postscaler OUTPS values other than 0 are
meaningless in this mode because the timer is stopped
at the first period event and the postscaler is reset
when the timer is restarted.
27.1.3
27.1
Timer2 Operation
ONE-SHOT MODE
MONOSTABLE MODE
Monostable modes are similar to One-Shot modes
except that the ON bit is not cleared and the timer can
be restarted by an external Reset event.
Timer2 operates in three major modes:
27.2
• Free Running Period
• One-shot
• Monostable
The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period when
the postscaler counter matches the value in the
OUTPS bits of the TMR2CON register. The PR2 postscaler is incremented each time the TMR2 value
matches the PR2 value. This signal can be selected as
an input to several other input modules:
Within each mode there are several options for starting,
stopping, and reset. Table 27-1 lists the options.
In all modes, the TMR2 count register is incremented
on the rising edge of the clock signal from the programmable prescaler. When TMR2 equals PR2, a high level
is output to the postscaler counter. TMR2 is cleared on
the next clock input.
An external signal from hardware can also be configured to gate the timer operation or force a TMR2 count
Reset. In Gate modes the counter stops when the gate
is disabled and resumes when the gate is enabled. In
Reset modes the TMR2 count is reset on either the
level or edge from the external source.
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared and the
PR2 register initializes to FFh on any device Reset.
Both the prescaler and postscaler counters are cleared
on the following events:
•
•
•
•
a write to the TMR2 register
a write to the T2CON register
any device Reset
External Reset Source event that resets the timer.
Note:
27.1.1
TMR2 is not cleared when T2CON is
written.
FREE RUNNING PERIOD MODE
The value of TMR2 is compared to that of the Period
register, PR2, on each TMR2_clk cycle. When the two
values match, the comparator resets the value of TMR2
to 00h on the next rising TMR2_clk edge and increments
2016-2018 Microchip Technology Inc.
Timer2 Output
• The ADC module, as an Auto-conversion Trigger
• COG, as an auto-shutdown source
In addition, the Timer2 is also used by the CCP module
for pulse generation in PWM mode. Both the actual
TMR2 value as well as other internal signals are sent to
the CCP module to properly clock both the period and
pulse width of the PWM signal. See Section 28.0
“Capture/Compare/PWM Modules” for more details
on setting up Timer2 for use with the CCP, as well as
the timing diagrams in Section 27.5 “Operation
Examples” for examples of how the varying Timer2
modes affect CCP PWM output.
27.3
External Reset Sources
In addition to the clock source, the Timer2 also takes in
an external Reset source. This external Reset source
is selected for Timer2 with the T2RST register. This
source can control starting and stopping of the timer, as
well as resetting the timer, depending on which mode
the timer is in. The mode of the timer is controlled by
the MODE bits of the TMR2HLT register. EdgeTriggered modes require six Timer clock periods
between external triggers. Level-Triggered modes
require the triggering level to be at least three Timer
clock periods long. External triggers are ignored while
in Debug Freeze mode.
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TABLE 27-1:
TIMER2 OPERATING MODES
MODE
Mode
Output
Operation
000
001
Period
Pulse
010
Free
Running
Period
00
Reset
Stop
ON = 1
—
ON = 0
Hardware gate, active-high
(Figure 27-5)
ON = 1 and
TMRx_ers = 1
—
ON = 0 or
TMRx_ers = 0
Hardware gate, active-low
ON = 1 and
TMRx_ers = 0
—
ON = 0 or
TMRx_ers = 1
Rising or falling edge Reset
TMRx_ers ↕
100
Rising edge Reset (Figure 27-6)
TMRx_ers ↑
110
Period
Pulse
with
Hardware
Reset
111
000
001
010
011
01
Start
Software gate (Figure 27-4)
011
101
One-shot
100
101
110
111
One-shot
Edge
triggered
start
(Note 1)
Edge
triggered
start
and
hardware
Reset
(Note 1)
Falling edge Reset
001
010
011
Reserved
10
Reserved
High level Reset (Figure 27-7)
111
Reserved
Note 1:
2:
3:
11
ON = 0 or
TMRx_ers = 0
TMRx_ers = 1
ON = 0 or
TMRx_ers = 1
ON = 1
—
Rising edge start (Figure 27-9)
ON = 1 and
TMRx_ers ↑
—
Falling edge start
ON = 1 and
TMRx_ers ↓
—
Any edge start
ON = 1 and
TMRx_ers ↕
—
Rising edge start and
Rising edge Reset (Figure 27-10)
ON = 1 and
TMRx_ers ↑
TMRx_ers ↑
Falling edge start and
Falling edge Reset
ON = 1 and
TMRx_ers ↓
TMRx_ers ↓
Rising edge start and
Low level Reset (Figure 27-11)
ON = 1 and
TMRx_ers ↑
TMRx_ers = 0
Falling edge start and
High level Reset
ON = 1 and
TMRx_ers ↓
TMRx_ers = 1
ON = 0
or
Next clock
after
TMRx = PRx
(Note 2)
Reserved
Edge
triggered
start
(Note 1)
Rising edge start
(Figure 27-12)
ON = 1 and
TMRx_ers ↑
—
Falling edge start
ON = 1 and
TMRx_ers ↓
—
Any edge start
ON = 1 and
TMRx_ers ↕
—
ON = 0
or
Next clock
after
TMRx = PRx
(Note 3)
Reserved
Reserved
101
One-shot
TMRx_ers = 0
Software start (Figure 27-8)
100
110
ON = 0
TMRx_ers ↓
ON = 1
Low level Reset
000
Mono-stable
Timer Control
Operation
Level
triggered
start
and
hardware
Reset
xxx
High level start and
Low level Reset (Figure 27-13)
ON = 1 and
TMRx_ers = 1
TMRx_ers = 0
Low level start &
High level Reset
ON = 1 and
TMRx_ers = 0
TMRx_ers = 1
ON = 0 or
Held in Reset
(Note 2)
Reserved
If ON = 0 then an edge is required to restart the timer after ON = 1.
When TMRx = PRx then the next clock clears ON and stops TMRx at 00h.
When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.
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27.4
Timer2 Interrupt
Timer2 can also generate a device interrupt. The
interrupt is generated when the postscaler counter
matches one of 16 postscale options (from 1:1 through
1:16), which are selected with the postscaler control
bits, OUTPS of the T2CON register. The interrupt
is enabled by setting the TMR2IE interrupt enable bit of
the PIE4 register. Interrupt timing is illustrated in
Figure 27-3.
FIGURE 27-3:
TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM
Rev. 10-000205A
4/7/2016
CKPS
0b010
PRx
1
OUTPS
0b0001
TMRx_clk
TMRx
0
1
0
1
0
1
0
TMRx_postscaled
TMRxIF
(1)
(2)
(1)
Note 1:
Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.
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27.5
Operation Examples
Unless otherwise specified, the following notes apply to
the following timing diagrams:
- Both the prescaler and postscaler are set to
1:1 (both the CKPS and OUTPS bits in the
T2CON register are cleared).
- The diagrams illustrate any clock except
Fosc/4 and show clock-sync delays of at
least two full cycles for both ON and
Timer2_ers. When using Fosc/4, the clocksync delay is at least one instruction period
for Timer2_ers; ON applies in the next
instruction period.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 28.0 “Capture/Compare/PWM Modules”. The signals are not a
part of the Timer2 module.
2016-2018 Microchip Technology Inc.
27.5.1
SOFTWARE GATE MODE
This mode corresponds to legacy Timer2 operation.
The timer increments with each clock input when
ON = 1 and does not increment when ON = 0. When
the TMR2 count equals the PR2 period count the timer
resets on the next clock and continues counting from 0.
Operation with the ON bit software controlled is illustrated in Figure 27-4. With PR2 = 5, the counter
advances until TMR2 = 5, and goes to zero with the
next clock.
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FIGURE 27-4:
SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000)
Rev. 10-000195B
5/30/2014
0b00000
MODE
TMRx_clk
Instruction(1)
BSF
BCF
BSF
ON
PRx
TMRx
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
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27.5.2
HARDWARE GATE MODE
When MODE = 00001 then the timer is stopped
when the external signal is high. When
MODE = 00010 then the timer is stopped when
the external signal is low.
The Hardware Gate modes operate the same as the
Software Gate mode except the TMR2_ers external
signal gates the timer. When used with the CCP the
gating extends the PWM period. If the timer is stopped
when the PWM output is high then the duty cycle is also
extended.
FIGURE 27-5:
Figure 27-5 illustrates the Hardware Gating mode for
MODE = 00001 in which a high input level starts
the counter.
HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001)
Rev. 10-000 196B
5/30/201 4
0b00001
MODE
TMRx_clk
TMRx_ers
PRx
TMRx
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
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27.5.3
EDGE-TRIGGERED HARDWARE
LIMIT MODE
When the timer is used in conjunction with the CCP in
PWM mode then an early Reset shortens the period
and restarts the PWM pulse after a two clock delay.
Refer to Figure 27-6.
In Hardware Limit mode the timer can be reset by the
TMR2_ers external signal before the timer reaches the
period count. Three types of Resets are possible:
• Reset on rising or falling edge
(MODE= 00011)
• Reset on rising edge (MODE = 00100)
• Reset on falling edge (MODE = 00101)
FIGURE 27-6:
EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM
(MODE = 00100)
Rev. 10-000 197B
5/30/201 4
MODE
0b00100
TMRx_clk
PRx
5
Instruction(1)
BSF
BCF
BSF
ON
TMRx_ers
TMRx
0
1
2
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
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27.5.4
LEVEL-TRIGGERED HARDWARE
LIMIT MODE
When the CCP uses the timer as the PWM time base
then the PWM output will be set high when the timer
starts counting and then set low only when the timer
count matches the CCPRx value. The timer is reset
when either the timer count matches the PR2 value or
two clock periods after the external Reset signal goes
true and stays true.
In the Level-Triggered Hardware Limit Timer modes the
counter is reset by high or low levels of the external
signal TMR2_ers, as shown in Figure 27-7. Selecting
MODE = 00110 will cause the timer to reset on a
low
level
external
signal.
Selecting
MODE = 00111 will cause the timer to reset on a
high level external signal. In the example, the counter
is reset while TMR2_ers = 1. ON is controlled by BSF
and BCF instructions. When ON = 0 the external signal
is ignored.
FIGURE 27-7:
The timer starts counting, and the PWM output is set
high, on either the clock following the PR2 match or two
clocks after the external Reset signal relinquishes the
Reset. The PWM output will remain high until the timer
counts up to match the CCPRx pulse width value. If the
external Reset signal goes true while the PWM output
is high then the PWM output will remain high until the
Reset signal is released allowing the timer to count up
to match the CCPRx value.
LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM
(MODE = 00111)
Rev. 10-000198B
5/30/2014
0b00111
MODE
TMRx_clk
5
PRx
Instruction(1)
BSF
BCF
BSF
ON
TMRx_ers
TMRx
0
1
2
0
1
2
3
4
5
0
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
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27.5.5
SOFTWARE START ONE-SHOT
MODE
In One-Shot mode the timer resets and the ON bit is
cleared when the timer value matches the PR2 period
value. The ON bit must be set by software to start
another timer cycle. Setting MODE = 01000
selects One-Shot mode which is illustrated in
Figure 27-8. In the example, ON is controlled by BSF
and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and
clears ON. In the second case, a BSF instruction starts
the cycle, BCF/BSF instructions turn the counter off
and on during the cycle, and then it runs to completion.
FIGURE 27-8:
When One-Shot mode is used in conjunction with the
CCP PWM operation the PWM pulse drive starts
concurrent with setting the ON bit. Clearing the ON bit
while the PWM drive is active will extend the PWM
drive. The PWM drive will terminate when the timer
value matches the CCPRx pulse width value. The
PWM drive will remain off until software sets the ON bit
to start another cycle. If software clears the ON bit after
the CCPRx match but before the PR2 match then the
PWM drive will be extended by the length of time the
ON bit remains cleared. Another timing cycle can only
be initiated by setting the ON bit after it has been
cleared by a PR2 period count match.
SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000)
Rev. 10-000199B
4/7/2016
0b01000
MODE
TMRx_clk
5
PRx
Instruction(1)
BSF
BSF
BCF
BSF
ON
TMRx
0
1
2
3
4
5
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions
executed by the CPU to set or clear the ON bit of TxCON. CPU
execution is asynchronous to the timer clock input.
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27.5.6
EDGE-TRIGGERED ONE-SHOT
MODE
The Edge-Triggered One-Shot modes start the timer
on an edge from the external signal input, after the ON
bit is set, and clear the ON bit when the timer matches
the PR2 period value. The following edges will start
the timer:
• Rising edge (MODE = 01001)
• Falling edge (MODE = 01010)
• Rising or Falling edge (MODE = 01011)
FIGURE 27-9:
If the timer is halted by clearing the ON bit then another
TMR2_ers edge is required after the ON bit is set to
resume counting. Figure 27-9 illustrates operation in
the rising edge One-Shot mode.
When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate
the PWM drive and the PWM drive will deactivate when
the timer matches the CCPRx pulse width value and
stay deactivated when the timer halts at the PR2 period
count match.
EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001)
Rev. 10-000200B
5/19/2016
0b01001
MODE
TMRx_clk
5
PRx
Instruction(1)
BSF
BSF
BCF
ON
TMRx_ers
TMRx
0
1
2
3
4
5
0
1
2
CCP_pset
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
2016-2018 Microchip Technology Inc.
DS40001866B-page 346
2016-2018 Microchip Technology Inc.
27.5.7
EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT
MODE
The timer resets and clears the ON bit when the timer value matches the PR2
period value. External signal edges will have no effect until after software sets
the ON bit. Figure 27-10 illustrates the rising edge hardware limit one-shot
operation.
In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first
external signal edge after the ON bit is set and resets on all subsequent edges.
Only the first edge after the ON bit is set is needed to start the timer. The
counter will resume counting automatically two clocks after all subsequent
external Reset edges. Edge triggers are as follows:
• Rising edge start and Reset (MODE = 01100)
• Falling edge start and Reset (MODE = 01101)
FIGURE 27-10:
When this mode is used in conjunction with the CCP then the first starting edge
trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM
drive will deactivate when the timer matches the CCPRx pulse-width value and
stay deactivated until the timer halts at the PR2 period match unless an external
signal edge resets the timer before the match occurs.
EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100)
Rev. 10-000201B
4/7/2016
MODE
0b01100
5
PRx
Instruction(1)
BSF
BSF
ON
TMRx_ers
0
TMRx
1
2
3
4
5
0
1
2
0
1
2
3
4
TMRx_postscaled
PWM Duty
Cycle
3
DS40001866B-page 347
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
5
0
PIC16(L)F15356/75/76/85/86
TMRx_clk
2016-2018 Microchip Technology Inc.
27.5.8
LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT
ONE-SHOT MODES
When the timer count matches the PR2 period count, the timer is reset and the
ON bit is cleared. When the ON bit is cleared by either a PR2 match or by software control a new external signal edge is required after the ON bit is set to start
the counter.
In Level -Triggered One-Shot mode the timer count is reset on the external
signal level and starts counting on the rising/falling edge of the transition from
Reset level to the active level while the ON bit is set. Reset levels are selected
as follows:
• Low Reset level (MODE = 01110)
• High Reset level (MODE = 01111)
FIGURE 27-11:
When Level-Triggered Reset One-Shot mode is used in conjunction with the
CCP PWM operation the PWM drive goes active with the external signal edge
that starts the timer. The PWM drive goes inactive when the timer count equals
the CCPRx pulse width count. The PWM drive does not go active when the
timer count clears at the PR2 period count match.
LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110)
Rev. 10-000202B
4/7/2016
MODE
0b01110
TMRx_clk
Instruction(1)
BSF
BSF
ON
TMRx_ers
0
TMRx
1
2
3
4
5
0
1
0
1
2
3
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
DS40001866B-page 348
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
4
5
0
PIC16(L)F15356/75/76/85/86
5
PRx
2016-2018 Microchip Technology Inc.
27.5.9
EDGE-TRIGGERED MONOSTABLE MODES
When an Edge-Triggered Monostable mode is used in conjunction with the
CCP PWM operation the PWM drive goes active with the external Reset signal
edge that starts the timer, but will not go active when the timer matches the PR2
value. While the timer is incrementing, additional edges on the external Reset
signal will not affect the CCP PWM.
The Edge-Triggered Monostable modes start the timer on an edge from the
external Reset signal input, after the ON bit is set, and stop incrementing the
timer when the timer matches the PR2 period value. The following edges will
start the timer:
• Rising edge (MODE = 10001)
• Falling edge (MODE = 10010)
• Rising or Falling edge (MODE = 10011)
FIGURE 27-12:
RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001)
Rev. 10-000203A
4/7/2016
0b10001
MODE
PRx
Instruction(1)
5
BSF
BCF
BSF
BCF
BSF
ON
TMRx_ers
TMRx
0
1
2
3
4
5
0
1
2
3
4
5
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
DS40001866B-page 349
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
0
1
2
3
4
5
0
PIC16(L)F15356/75/76/85/86
TMRx_clk
2016-2018 Microchip Technology Inc.
27.5.10
LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT
MODES
When the timer count matches the PR2 period count, the timer is reset and the
ON bit is cleared. When the ON bit is cleared by either a PR2 match or by software control the timer will stay in Reset until both the ON bit is set and the external signal is not at the Reset level.
The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset
on an external Reset level and start counting when both the ON bit is set and
the external signal is not at the Reset level. If one of either the external signal
is not in Reset or the ON bit is set then the other signal being set/made active
will start the timer. Reset levels are selected as follows:
When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation the PWM drive goes active with either the
external signal edge or the setting of the ON bit, whichever of the two starts the
timer.
• Low Reset level (MODE = 10110)
• High Reset level (MODE = 10111)
FIGURE 27-13:
LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110)
Rev. 10-000204A
4/7/2016
0b10110
MODE
PRx
5
Instruction(1)
BSF
BSF
BCF
BSF
ON
TMR2_ers
TMRx
0
1
2
3
4
5
0
1
2
3
TMR2_postscaled
PWM Duty
Cycle
‘D3
DS40001866B-page 350
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
0
1
2
3
4
5
0
PIC16(L)F15356/75/76/85/86
TMR2_clk
PIC16(L)F15356/75/76/85/86
27.6
Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while
the processor is in Sleep mode. The contents of the
TMR2 and PR2 registers will remain unchanged while
processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long
as the clock source selected is also still running.
Selecting the LFINTOSC, MFINTOSC, or HFINTOSC
oscillator as the timer clock source will keep the
selected oscillator running during Sleep.
2016-2018 Microchip Technology Inc.
DS40001866B-page 351
PIC16(L)F15356/75/76/85/86
27.7
Register Definitions: Timer2 Control
REGISTER 27-1:
T2CLKCON: TIMER2 CLOCK SELECTION REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
CS: Timer2 Clock Select bits
1111 = Reserved
1110 = LC4_out
1101 = LC3_out
1100 = LC2_out
1011 = LC1_out
1010 = ZCD1_output
1001 = NCO1_out
1000 = CLKR
0111 = SOSC
0110 = MFINTOSC (31.25 kHz)
0101 = MFINTOSC (500 kHz)
0100 = LFINTOSC
0011 = HFINTOSC (32 MHz)
0010 = FOSC
0001 = FOSC/4
0000 = T2CKIPPS
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
REGISTER 27-2:
R/W/HC-0/0
T2CON: TIMER2 CONTROL REGISTER
R/W-0/0
ON(1)
R/W-0/0
R/W-0/0
R/W-0/0
CKPS
R/W-0/0
R/W-0/0
R/W-0/0
OUTPS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off: all counters and state machines are reset
bit 6-4
CKPS: Timer2-type Clock Prescale Select bits
111 =1:128 Prescaler
110 =1:64 Prescaler
101 =1:32 Prescaler
100 =1:16 Prescaler
011 =1:8 Prescaler
010 =1:4 Prescaler
001 =1:2 Prescaler
000 =1:1 Prescaler
bit 3-0
OUTPS: Timer2 Output Postscaler Select bits
1111 =1:16 Postscaler
1110 =1:15 Postscaler
1101 =1:14 Postscaler
1100 =1:13 Postscaler
1011 =1:12 Postscaler
1010 =1:11 Postscaler
1001 =1:10 Postscaler
1000 =1:9 Postscaler
0111 =1:8 Postscaler
0110 =1:7 Postscaler
0101 =1:6 Postscaler
0100 =1:5 Postscaler
0011 =1:4 Postscaler
0010 =1:3 Postscaler
0001 =1:2 Postscaler
0000 =1:1 Postscaler
Note 1:
In certain modes, the ON bit will be auto-cleared by hardware. See Section 27.5 “Operation Examples”.
2016-2018 Microchip Technology Inc.
DS40001866B-page 353
PIC16(L)F15356/75/76/85/86
REGISTER 27-3:
T2HLT: TIMER2 HARDWARE LIMIT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
PSYNC(1, 2)
CKPOL(3)
CKSYNC(4, 5)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
MODE(6, 7)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSYNC: Timer2 Prescaler Synchronization Enable bit(1, 2)
1 = TMR2 Prescaler Output is synchronized to Fosc/4
0 = TMR2 Prescaler Output is not synchronized to Fosc/4
bit 6
CKPOL: Timer2 Clock Polarity Selection bit(3)
1 = Falling edge of input clock clocks timer/prescaler
0 = Rising edge of input clock clocks timer/prescaler
bit 5
CKSYNC: Timer2 Clock Synchronization Enable bit(4, 5)
1 = ON register bit is synchronized to TMR2_clk input
0 = ON register bit is not synchronized to TMR2_clk input
bit 4-0
MODE: Timer2 Control Mode Selection bits(6, 7)
See Table 27-1.
Note 1:
Setting this bit ensures that reading TM2x will return a valid value.
2:
When this bit is ‘1’, Timer2 cannot operate in Sleep mode.
3:
CKPOL should not be changed while ON = 1.
4:
Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5:
When this bit is set then the timer operation will be delayed by two TMR2 input clocks after the ON bit is set.
6:
Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value
of TMR2).
7:
When TMR2 = PR2, the next clock clears TMR2, regardless of the operating mode.
2016-2018 Microchip Technology Inc.
DS40001866B-page 354
PIC16(L)F15356/75/76/85/86
REGISTER 27-4:
T2RST: TIMER2 EXTERNAL RESET SIGNAL SELECTION REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RSEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RSEL: Timer2 External Reset Signal Source Selection bits
1111 = Reserved
1101 = LC4_out
1100 = LC3_out
1011 = LC2_out
1010 = LC1_out
1001 = ZCD1_output
1000 = C2OUT_sync
0111 = C1OUT_sync
0110 = PWM6_out
0101 = PWM5_out
0100 = PWM4_out
0011 = PWM3_out
0010 = CCP2_out
0001 = CCP1_out
0000 = T2INPPS
2016-2018 Microchip Technology Inc.
DS40001866B-page 355
PIC16(L)F15356/75/76/85/86
TABLE 27-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 7
Bit 6
Bit 5
Bit 4
CCP1CON
EN
—
OUT
FMT
MODE
CCP2CON
EN
—
OUT
FMT
MODE
INTCON
GIE
PEIE
—
—
—
—
—
—
—
—
—
—
—
—
—
PIE4
PIR4
PR2
Timer2 Module Period Register
TMR2
Holding Register for the 8-bit TMR2 Register
T2CON
ON
T2CLKCON
—
Bit 1
Bit 0
Register
on Page
364
364
—
—
INTEDG
147
—
TMR2IE
TMR1IE
134
—
TMR2IF
TMR1IF
160
337*
—
—
—
T2RST
—
—
—
T2HLT
PSYNC
CKPOL
CKSYNC
Legend:
*
Bit 2
336*
CKPS
—
Bit 3
OUTPS
353
CS
352
RSEL
355
MODE
354
— = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
Page provides register information.
2016-2018 Microchip Technology Inc.
DS40001866B-page 356
PIC16(L)F15356/75/76/85/86
28.0
CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
that allows the user to time and control different events,
and to generate Pulse-Width Modulation (PWM)
signals. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate Pulse-Width Modulated signals of
varying frequency and duty cycle.
The Capture/Compare/PWM modules available are
shown in Table 28-1.
TABLE 28-1:
AVAILABLE CCP MODULES
Device
PIC16(L)F15356/75/76/85/86
CCP1
CCP2
●
●
The Capture and Compare functions are identical for all
CCP modules.
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.
2016-2018 Microchip Technology Inc.
DS40001866B-page 357
PIC16(L)F15356/75/76/85/86
28.1
Capture Mode
Figure 28-1 shows a simplified diagram of the capture
operation.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the capture
source, the 16-bit CCPRxH:CCPRxL register pair
captures and stores the 16-bit value of the
TMR1H:TMR1L register pair, respectively. An event is
defined as one of the following and is configured by the
CCPxMODE bits of the CCPxCON register:
•
•
•
•
28.1.1
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Note:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
The capture source is selected by configuring the
CCPxCTS bits of the CCPxCAP register. The
following sources can be selected:
•
•
•
•
•
•
•
•
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIR6 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
FIGURE 28-1:
CAPTURE SOURCES
CCPxPPS input
C1OUT_sync
C2OUT_sync
IOC_interrupt
LC1_out
LC2_out
LC3_out
LC4_out
CAPTURE MODE OPERATION BLOCK DIAGRAM
Rev. 10-000158F
9/1/2015
RxyPPS
CCPx
CTS
TRIS Control
CCPx
LC4_out
111
LC3_out
110
LC2_out
101
LC1_out
100
IOC_interrupt
011
C2OUT_sync
010
C1OUT_sync
001
PPS
000
CCPRxH
CCPRxL
16
Prescaler
1,4,16
set CCPxIF
and
Edge Detect
16
MODE
TMR1H
TMR1L
CCPxPPS
2016-2018 Microchip Technology Inc.
DS40001866B-page 358
PIC16(L)F15356/75/76/85/86
28.1.2
TIMER1 MODE RESOURCE
28.1.5
CAPTURE DURING SLEEP
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
See Section 26.0 “Timer1 Module with Gate
Control” for more information on configuring Timer1.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
28.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIE6 register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIR6 register
following any change in Operating mode.
Note:
28.1.4
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4).
CCP PRESCALER
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
28.2
Compare Mode
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
•
•
•
•
•
Toggle the CCPx output
Set the CCPx output
Clear the CCPx output
Generate an Auto-conversion Trigger
Generate a Software Interrupt
There are four prescaler settings specified by the
CCPxMODE bits of the CCPxCON register.
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
The action on the pin is based on the value of the
CCPxMODE control bits of the CCPxCON
register. At the same time, the interrupt flag CCPxIF bit
is set, and an ADC conversion can be triggered, if
selected.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler. Example 28-1 demonstrates the code to
perform this function.
All Compare modes can generate an interrupt and
trigger and ADC conversion.
EXAMPLE 28-1:
Figure 28-2 shows a simplified diagram of the compare
operation.
FIGURE 28-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCPxCON
CLRF
MOVLW
MOVWF
;Set Bank bits to point
;to CCPxCON
CCPxCON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
CCPxCON
;Load CCPxCON with this
;value
CCPxMODE
Mode Select
Set CCPxIF Interrupt Flag
(PIR6)
4
CCPRxH CCPRxL
CCPx
Pin
Q
S
R
Output
Logic
Match
Comparator
TMR1H
TRIS
Output Enable
TMR1L
Auto-conversion Trigger
2016-2018 Microchip Technology Inc.
DS40001866B-page 359
PIC16(L)F15356/75/76/85/86
28.2.1
CCPX PIN CONFIGURATION
The software must configure the CCPx pin as an output
by clearing the associated TRIS bit and defining the
appropriate output pin through the RxyPPS registers.
See Section 15.0 “Peripheral Pin Select (PPS)
Module” for more details.
The CCP output can also be used as an input for other
peripherals.
Note:
28.2.2
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 26.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
Note:
28.2.3
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
AUTO-CONVERSION TRIGGER
All CCPx modes set the CCP interrupt flag (CCPxIF).
When this flag is set and a match occurs, an Autoconversion Trigger can take place if the CCP module is
selected as the conversion trigger source.
Refer to Section 20.2.4 “Auto-Conversion Trigger”
for more information.
Note:
28.2.4
Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Autoconversion Trigger and the clock edge
that generates the Timer1 Reset, will
preclude the Reset from occurring
COMPARE DURING SLEEP
Since FOSC is shut down during Sleep mode, the
Compare mode will not function properly during Sleep,
unless the timer is running. The device will wake on
interrupt (if enabled).
28.3
PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 28-3 shows a typical waveform of the PWM
signal.
28.3.1
STANDARD PWM OPERATION
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to
ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
•
•
•
•
PR2 registers
T2CON registers
CCPRxL registers
CCPxCON registers
Figure 28-4 shows a simplified block diagram of PWM
operation.
Note:
The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
FIGURE 28-3:
CCP PWM OUTPUT SIGNAL
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRxH:CCPRxL
TMR2 = 0
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
FIGURE 28-4:
SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000 157C
9/5/201 4
Duty cycle registers
CCPRxH
CCPRxL
CCPx_out
set CCPIF
10-bit Latch(2)
(Not accessible by user)
Comparator
R
PPS
Q
RxyPPS
S
TMR2 Module
R
TMR2
To Peripherals
CCPx
TRIS Control
(1)
ERS logic
Comparator
CCPx_pset
PR2
28.3.2
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for standard PWM operation:
1.
2.
3.
4.
5.
Use the desired output pin RxyPPS control to
select CCPx as the source and disable the
CCPx pin output driver by setting the associated
TRIS bit.
Load the PR2 register with the PWM period
value.
Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
Load the CCPRxL register, and the CCPRxH
register with the PWM duty cycle value and
configure the CCPxFMT bit of the CCPxCON
register to set the proper register alignment.
Configure and start Timer2:
•Clear the TMR2IF interrupt flag bit of the
PIR4 register. See Note below.
•Configure the CKPS bits of the T2CON register with the Timer prescale value.
•Enable the Timer by setting the Timer2 ON
bit of the T2CON register.
2016-2018 Microchip Technology Inc.
6.
Enable PWM output pin:
•Wait until the Timer overflows and the TMR2IF
bit of the PIR4 register is set. See Note
below.
•Enable the CCPx pin output driver by clearing
the associated TRIS bit.
Note:
28.3.3
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
CCP/PWM CLOCK SELECTION
The PIC16(L)F15356/75/76/85/86 allows each
individual CCP and PWM module to select the timer
source that controls the module. Each module has an
independent selection.
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PIC16(L)F15356/75/76/85/86
28.3.4
TIMER2 TIMER RESOURCE
This device has a newer version of the Timer2 module
that has many new modes, which allow for greater
customization and control of the PWM signals than on
older parts. Refer to Section 27.5 “Operation
Examples” for examples of PWM signal generation
using the different modes of Timer2. The CCP
operation requires that the timer used as the PWM time
base has the FOSC/4 clock source selected
28.3.5
FIGURE 28-5:
PWM 10-BIT ALIGNMENT
Rev. 10-000 160A
12/9/201 3
CCPRxH
CCPRxL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
FMT = 1
CCPRxH
CCPRxL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
PWM PERIOD
10-bit Duty Cycle
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 28-1.
EQUATION 28-1:
PWM PERIOD
PWM Period = PR2 + 1 4 T OSC
9 8 7 6 5 4 3 2 1 0
EQUATION 28-2:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is transferred from the
CCPRxL/H register pair into a 10-bit buffer.
28.3.6
T OSC (TMR2 Prescale Value)
TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Note:
PULSE WIDTH
Pulse Width = CCPRxH:CCPRxL register pair
(TMR2 Prescale Value)
Note 1:
FMT = 0
The Timer postscaler (see Section 27.4
“Timer2 Interrupt”) is not used in the
determination of the PWM frequency.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to the CCPRxH:CCPRxL register pair. The
alignment of the 10-bit value is determined by the
CCPRxFMT bit of the CCPxCON register (see
Figure 28-5). The CCPRxH:CCPRxL register pair can
be written to at any time; however the duty cycle value
is not latched into the 10-bit buffer until after a match
between PR2 and TMR2.
Equation 28-2 is used to calculate the PWM pulse
width.
Equation 28-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 28-3:
DUTY CYCLE RATIO
CCPRxH:CCPRxL register pair Duty Cycle Ratio = --------------------------------------------------------------------------------4 PR2 + 1
CCPRxH:CCPRxL register pair are used to double
buffer the PWM duty cycle. This double buffering
provides for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the
CCPRxH:CCPRxL register pair, then the CCPx pin is
cleared (see Figure 28-4).
28.3.7
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 28-4.
EQUATION 28-4:
PWM RESOLUTION
log 4 PR2 + 1 - bits
Resolution = ----------------------------------------log 2
Note:
2016-2018 Microchip Technology Inc.
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
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TABLE 28-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
Timer Prescale
PR2 Value
Maximum Resolution (bits)
TABLE 28-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
Timer Prescale
PR2 Value
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
Maximum Resolution (bits)
28.3.8
4.90 kHz
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
28.3.9
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 9.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
28.3.10
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
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28.4
Register Definitions: CCP Control
Long bit name prefixes for the CCP peripherals are
shown in Section 1.1 “Register and Bit Naming
Conventions”.
TABLE 28-4:
LONG BIT NAMES PREFIXES
FOR CCP PERIPHERALS
Peripheral
Bit Name Prefix
CCP1
CCP1
CCP2
CCP2
REGISTER 28-1:
CCPxCON: CCPx CONTROL REGISTER
R/W-0/0
U-0
R-x
R/W-0/0
EN
—
OUT
FMT
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
MODE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
EN: CCPx Module Enable bit
1 = CCPx is enabled
0 = CCPx is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
OUT: CCPx Output Data bit (read-only)
bit 4
FMT: CCPW (Pulse Width) Alignment bit
MODE = Capture mode
Unused
MODE = Compare mode
Unused
MODE = PWM mode
1 = Left-aligned format
0 = Right-aligned format
bit 3-0
MODE: CCPx Mode Select bits(1)
1111 - 1100 = PWM mode (Timer2 as the timer source)
1110 = Reserved
1101 =Reserved
1100 = Reserved
1011 =Compare mode: output will pulse 0-1-0; Clears TMR1
1010 =Compare mode: output will pulse 0-1-0
1001 =Compare mode: clear output on compare match
1000 =Compare mode: set output on compare match
0111 =Capture mode: every 16th rising edge of CCPx input
0110 =Capture mode: every 4th rising edge of CCPx input
0101 =Capture mode: every rising edge of CCPx input
0100 =Capture mode: every falling edge of CCPx input
0011 =Capture mode: every edge of CCPx input
0010 =Compare mode: toggle output on match
0001 =Compare mode: toggle output on match; clear TMR1
0000 =Capture/Compare/PWM off (resets CCPx module)
Note 1:
All modes will set the CCPxIF bit, and will trigger an ADC conversion if CCPx is selected as the ADC trigger source.
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REGISTER 28-2:
CCPxCAP: CAPTURE INPUT SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0/x
R/W-0/x
R/W-0/x
CTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
CTS: Capture Trigger Input Selection bits
CTS
CCP1.capture
111
LC4_out
110
LC3_out
101
LC2_out
100
LC1_out
011
IOC_interrupt
010
C2OUT
001
C1OUT
000
REGISTER 28-3:
R/W-x/x
CCP2.capture
CCP1PPS
CCP2PPS
CCPRxL REGISTER: CCPx REGISTER LOW BYTE
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
CCPRx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
CCPxMODE = Capture mode
CCPRxL: Capture value of TMR1L
CCPxMODE = Compare mode
CCPRxL: LS Byte compared to TMR1L
CCPxMODE = PWM modes when CCPxFMT = 0:
CCPRxL: Pulse-width Least Significant eight bits
CCPxMODE = PWM modes when CCPxFMT = 1:
CCPRxL: Pulse-width Least Significant two bits
CCPRxL: Not used.
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REGISTER 28-4:
R/W-x/x
CCPRxH REGISTER: CCPx REGISTER HIGH BYTE
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
CCPRx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
CCPxMODE = Capture mode
CCPRxH: Captured value of TMR1H
CCPxMODE = Compare mode
CCPRxH: MS Byte compared to TMR1H
CCPxMODE = PWM modes when CCPxFMT = 0:
CCPRxH: Not used
CCPRxH: Pulse-width Most Significant two bits
CCPxMODE = PWM modes when CCPxFMT = 1:
CCPRxH: Pulse-width Most Significant eight bits
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TABLE 28-5:
Name
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH CCPx
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
—
—
—
—
—
INTEDG
147
PIR6
—
—
—
—
—
—
CCP2IF
CCP1IF
144
PIE6
—
—
—
—
—
—
CCP2IE
CCP1IE
136
CCP1CON
EN
—
OUT
FMT
—
—
—
—
CCP1CAP
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
CCP2CON
CCP2CAP
MODE
—
CTS
364
365
365
366
EN
—
OUT
FMT
—
—
—
—
MODE
—
CTS
364
365
CCPR2L
Capture/Compare/PWM Register 1 (LSB)
365
CCPR2H
Capture/Compare/PWM Register 1 (MSB)
365
CCP1PPS
—
—
CCP1PPS
242
CCP2PPS
—
—
CCP2PPS
242
RxyPPS
—
—
—
RxyPPS
243
ADACT
—
—
—
ADACT
281
CLCxSELy
—
—
—
CWG1DAT
—
—
—
Legend:
LCxDyS
—
DAT
409
398
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCP module.
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PIC16(L)F15356/75/76/85/86
29.0
PULSE-WIDTH MODULATION
(PWM)
The PWMx modules generate Pulse-Width Modulated
(PWM) signals of varying frequency and duty cycle.
In addition to the CCP modules, the PIC16(L)F15356/
75/76/85/86 devices contain four 10-bit PWM modules
(PWM3, PWM4, PWM5 and PWM6). The PWM
modules reproduce the PWM capability of the CCP
modules.
FIGURE 29-1:
Q1
PWM OUTPUT
Q2
Q3
Q4
Rev. 10-000023C
8/26/2015
FOSC
PWM
Pulse Width
TMRx = 0
TMRx = PWMxDC
Note:
The PWM3/4/5/6 modules are four
instances of the same PWM module
design. Throughout this section, the lower
case ‘x’ in register and bit names is a
generic reference to the PWM module
number (which should be substituted with
3, or 4, or, 5 or 6 during code
development). For example, the control
register is generically described in this
chapter as PWMxCON, but the actual
device
registers
are
PWM3CON,
PWM4CON,
PWM5CON
and
PWM6CON. Similarly, the PWMxEN bit
represents the PWM3EN, PWM4EN,
PWM5EN and PWM6EN bits.
TMRx = PRx
(1)
(1)
(1)
Note 1: Timer dependent on PWMTMRS register settings.
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the ‘on’ state (pulse width), and the low
portion of the signal is considered the ‘off’ state. The
term duty cycle describes the proportion of the ‘on’ time
to the ‘off’ time and is expressed in percentages, where
0% is fully off and 100% is fully on. A lower duty cycle
corresponds to less power applied and a higher duty
cycle corresponds to more power applied. The PWM
period is defined as the duration of one complete cycle
or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and, in turn, the power that is applied to the
load.
Figure 29-1 shows a typical waveform of the PWM
signal.
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29.1
Standard PWM Mode
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the PWMx pin with up to
ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
•
•
•
•
•
TMR2 register
PR2 register
PWMxCON registers
PWMxDCH registers
PWMxDCL registers
Figure 29-2 shows a simplified block diagram of PWM
operation.
If PWMPOL = 0, the default state of the output is ‘0‘. If
PWMPOL = 1, the default state is ‘1’. If PWMEN = 0,
the output will be the default state.
Note:
The corresponding TRIS bit must be
cleared to enable the PWM output on the
PWMx pin
FIGURE 29-2:
SIMPLIFIED PWM BLOCK DIAGRAM
Rev. 10-000022B
9/24/2014
PWMxDCL
Duty cycle registers
PWMxDCH
PWMx_out
10-bit Latch
(Not visible to user)
R
Comparator
Q
0
1
S
To Peripherals
PPS
PWMx
Q
TMR2 Module
TMR2
R
PWMxPOL
(1)
Comparator
RxyPPS
TRIS Control
T2_match
PR2
Note 1:
8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
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PIC16(L)F15356/75/76/85/86
29.1.1
PWM CLOCK SELECTION
The PIC16(L)F15356/75/76/85/86 allows each individual CCP and PWM module to select the timer source
that controls the module. Each module has an independent selection.
29.1.2
USING THE TMR2 WITH THE PWM
MODULE
This device has a newer version of the TMR2 module
that has many new modes, which allow for greater
customization and control of the PWM signals than on
older parts. Refer to Section 27.5 “Operation
Examples” for examples of PWM signal generation
using the different modes of Timer2.
Note:
29.1.3
PWM operation requires that the timer
used as the PWM time base has the
FOSC/4 clock source selected.
PWM PERIOD
Referring to Figure 29-1, the PWM output has a period
and a pulse width. The frequency of the PWM is the
inverse of the period (1/period).
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 29-1:
29.1.4
The PWM duty cycle is specified by writing a 10-bit
value to the PWMxDC register. The PWMxDCH
contains the eight MSbs and the PWMxDCL bits
contain the two LSbs.
The PWMDC register is double-buffered and can be
updated at any time. This double buffering is essential
for glitch-free PWM operation. New values take effect
when TMR2 = PR2. Note that PWMDC is left-justified.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two
bits of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to
1:1.
Equation 29-2 is used to calculate the PWM pulse
width.
Equation 29-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 29-2:
Note 1: TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The PWMx pin is set (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM pulse width is latched from PWMxDC.
EQUATION 29-3:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
2016-2018 Microchip Technology Inc.
DUTY CYCLE RATIO
݅ݐܴ݈ܽ݁ܿݕܥݕݐݑܦൌ
29.1.5
ሺܹܲܥܦݔܯሻ
Ͷሺܴܲʹ ͳሻ
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit
resolution will result in 1024 discrete duty cycles,
whereas an 8-bit resolution will result in 256 discrete
duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 29-4.
EQUATION 29-4:
Note:
PULSE WIDTH
Pulse Widthൌሺܹܲܥܦݔܯሻ ή ܱܶܵ ܥή
ሺܶ݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯሻ
PWM PERIOD
ܹܲ ݀݅ݎ݁ܲܯൌ ሾሺܴܲʹሻ ͳሿ ή Ͷ ή ܱܶܵܥ
ή ሺܶ݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯሻ
PWM DUTY CYCLE
PWM RESOLUTION
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
DS40001866B-page 370
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29.1.6
OPERATION IN SLEEP MODE
29.1.8
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
29.1.7
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWMx registers to their Reset states.
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 9.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
TABLE 29-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
Timer Prescale
PR2 Value
Maximum Resolution (bits)
TABLE 29-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
Timer Prescale
PR2 Value
Maximum Resolution (bits)
29.1.9
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the module for using the PWMx outputs:
1.
Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Configure the PWM output polarity by
configuring the PWMxPOL bit of the PWMxCON
register.
3. Load the PR2 register with the PWM period value,
as determined by Equation 29-1.
4. Load the PWMxDCH register and bits of
the PWMxDCL register with the PWM duty cycle
value, as determined by Equation 29-2.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR4
register.
• Select the Timer2 prescale value by configuring
the CKPS bits of the T2CON register.
• Enable Timer2 by setting the Timer2 ON bit of the
T2CON register.
2016-2018 Microchip Technology Inc.
6. Wait until the TMR2IF is set.
7. When the TMR2IF flag bit is set:
• Clear the associated TRIS bit(s) to enable the output driver.
• Route the signal to the desired pin by configuring
the RxyPPS register.
• Enable the PWMx module by setting the
PWMxEN bit of the PWMxCON register.
In order to send a complete duty cycle and period on
the first PWM output, the above steps must be followed
in the order given. If it is not critical to start with a
complete PWM signal, then the PWM module can be
enabled during Step 2 by setting the PWMxEN bit of
the PWMxCON register.
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29.2
Register Definitions: PWM Control
REGISTER 29-1:
PWMxCON: PWM CONTROL REGISTER
R/W-0/0
U-0
R-0
R/W-0/0
U-0
U-0
U-0
U-0
PWMxEN
—
PWMxOUT
PWMxPOL
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PWMxEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
PWMxOUT: PWM Module Output Level when Bit is Read
bit 4
PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active-low
0 = PWM output is active-high
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 29-2:
R/W-x/u
PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PWMxDC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PWMxDC: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.
REGISTER 29-3:
R/W-x/u
PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
PWMxDC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
PWMxDC: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register.
bit 5-0
Unimplemented: Read as ‘0’
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TABLE 29-3:
Name
T2CON
SUMMARY OF REGISTERS ASSOCIATED WITH PWMx
Bit 7
Bit 6
ON
Bit 5
Bit 4
Bit 3
Bit 2
CKPS
T2TMR
Holding Register for the 8-bit TMR2 Register
T2PR
TMR2 Period Register
Bit 1
Bit 0
OUTPS
Register
on Page
353
337*
336*
RxyPPS
―
―
—
RxyPPS
CWG1DAT
—
—
—
CLCxSELy
—
—
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
201
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
212
—
243
DAT
398
LCxDyS
409
Legend: - = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWMx module.
* Page with Register information.
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30.0
COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The Complementary Waveform Generator (CWG)
produces half-bridge, full-bridge, and steering of PWM
waveforms. It is backwards compatible with previous
ECCP functions.
The CWG has the following features:
• Six operating modes:
- Synchronous Steering mode
- Asynchronous Steering mode
- Full-Bridge mode, Forward
- Full-Bridge mode, Reverse
- Half-Bridge mode
- Push-Pull mode
• Output polarity control
• Output steering
- Synchronized to rising event
- Immediate effect
• Independent 6-bit rising and falling event deadband timers
- Clocked dead band
- Independent rising and falling dead-band
enables
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
30.1
Fundamental Operation
The CWG module can operate in six different modes,
as specified by MODE of the CWG1CON0 register:
• Half-Bridge mode (Figure 30-9)
• Push-Pull mode (Figure 30-2)
- Full-Bridge mode, Forward (Figure 30-3)
- Full-Bridge mode, Reverse (Figure 30-3)
• Steering mode (Figure 30-10)
• Synchronous Steering mode (Figure 30-11)
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. Thus, all
output modes support auto-shutdown, which is covered
in 30.10 “Auto-Shutdown”.
30.1.1
HALF-BRIDGE MODE
In Half-Bridge mode, two output signals are generated
as true and inverted versions of the input as illustrated
in Figure 30-9. A non-overlap (dead-band) time is
inserted between the two outputs as described in
Section 30.5 “Dead-Band Control”.
The unused outputs CWG1C and CWG1D drive similar
signals, with polarity independently controlled by the
POLC and POLD bits of the CWG1CON1 register,
respectively.
The CWG modules available are shown in Table 30-1.
TABLE 30-1:
AVAILABLE CWG MODULES
Device
PIC16(L)F15356/75/76/85/86
2016-2018 Microchip Technology Inc.
CWG1
●
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FIGURE 30-1:
SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE)
Rev. 10-000166B
8/29/2014
CWG_data
Rising Deadband Block
See
CWGxISM
Register
CWG_dataA
clock
signal_out
CWG_dataC
signal_in
Q
CWGxISM
E
R
Q
Falling Deadband Block
CWG_dataB
clock
signal_out
signal_in
EN
SHUTDOWN
HFINTOSC
1
FOSC
0
CWGxCLK
CWG_dataD
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30.1.2
PUSH-PULL MODE
In Push-Pull mode, two output signals are generated,
alternating copies of the input as illustrated in
Figure 30-2. This alternation creates the push-pull
effect required for driving some transformer-based
power supply designs.
The push-pull sequencer is reset whenever EN = 0 or
if an auto-shutdown event occurs. The sequencer is
clocked by the first input pulse, and the first output
appears on CWG1A.
The unused outputs CWG1C and CWG1D drive copies
of CWG1A and CWG1B, respectively, but with polarity
controlled by the POLC and POLD bits of the
CWG1CON1 register, respectively.
30.1.3
FULL-BRIDGE MODES
In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by
the input data signal. In Forward Full-Bridge mode,
CWG1A is driven to its active state, CWG1B and
CWG1C are driven to their inactive state, and CWG1D
is modulated by the input signal. In Reverse Full-Bridge
mode, CWG1C is driven to its active state, CWG1A and
CWG1D are driven to their inactive states, and CWG1B
is modulated by the input signal. In Full-Bridge mode,
the dead-band period is used when there is a switch
from forward to reverse or vice-versa. This dead-band
control is described in Section 30.5 “Dead-Band Control”, with additional details in Section 30.6 “Rising
Edge and Reverse Dead Band” and Section 30.7
“Falling Edge and Forward Dead Band”.
The mode selection may be toggled between forward
and reverse toggling the MODE bit of the
CWG1CON0 while keeping MODE static, without
disabling the CWG module.
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FIGURE 30-2:
SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE)
Rev. 10-000167B
8/29/2014
CWG_data
See
CWGxISM
Register
D
Q
CWG_dataA
Q
CWG_dataC
R
CWG_dataB
Q
E
Q
CWG_dataD
CWGxISM
EN
SHUTDOWN
R
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FIGURE 30-3:
SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES)
Rev. 10-000165B
8/29/2014
Reverse Deadband Block
MODE0
clock
signal_out
See
CWGxISM
Register
signal_in
CWG_dataA
D
Q
CWG_dataB
Q
CWG_dataC
CWGxISM
E
R
CWG_dataD
Q
clock
signal_out
signal_in
Forward Deadband Block
EN
CWG_data
SHUTDOWN
HFINTOSC
FOSC
CWGxCLK
1
0
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30.1.4
STEERING MODES
In Steering modes, the data input can be steered to any
or all of the four CWG output pins. In Synchronous
Steering mode, changes to steering selection registers
take effect on the next rising input.
In Non-Synchronous mode, steering takes effect on the
next instruction cycle. Additional details are provided in
Section 30.9 “CWG Steering Mode”.
FIGURE 30-4:
SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)
Rev. 10-000164B
8/26/2015
See
CWGxISM
Register
CWG_dataA
CWG_data
CWG_dataB
CWG_dataC
CWG_dataD
D
Q
CWGxISM
E
R
Q
EN
SHUTDOWN
30.2
Clock Source
The CWG module allows the following clock sources to
be selected:
• Fosc (system clock)
• HFINTOSC (16 MHz only)
The clock sources are selected using the CS bit of the
CWG1CLKCON register.
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30.3
Selectable Input Sources
The CWG generates the output waveforms from the
input sources in Table 30-2.
TABLE 30-2:
SELECTABLE INPUT
SOURCES
Source Peripheral
Signal Name
CWG input PPS pin
CWG1PPS
CCP1
CCP1_out
CCP2
CCP2_out
PWM3
PWM3_out
PWM4
PWM4_out
PWM5
PWM5_out
PWM6
PWM6_out
NCO
NCO1_out
Comparator C1
C1OUT_sync
Comparator C2
C2OUT_sync
CLC1
LC1_out
CLC2
LC2_out
CLC3
LC3_out
CLC4
LC4_out
30.4
30.4.1
Output Control
POLARITY CONTROL
The polarity of each CWG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active-high. Clearing the
output polarity bit configures the corresponding output
as active-low. However, polarity does not affect the
override levels. Output polarity is selected with the
POLx bits of the CWG1CON1. Auto-shutdown and
steering options are unaffected by polarity.
The input sources are selected using the CWG1DAT
register.
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FIGURE 30-5:
CWG OUTPUT BLOCK DIAGRAM
Rev. 10-000171B
9/24/2014
LSAC
CWG_dataA
1
POLA
OVRA
‘1’
11
‘0’
10
High Z
01
00
0
RxyPPS
TRIS Control
1
0
PPS
CWGxA
STRA(1)
LSBD
CWG_dataB
1
POLB
OVRB
‘1’
11
‘0’
10
High Z
01
00
0
RxyPPS
TRIS Control
1
0
PPS
CWGxB
STRB(1)
LSAC
CWG_dataC
1
POLC
OVRC
‘1’
11
‘0’
10
High Z
01
00
0
RxyPPS
TRIS Control
1
0
PPS
CWGxC
STRC(1)
LSBD
CWG_dataD
1
POLD
OVRD
‘1’
11
‘0’
10
High Z
01
0
00
RxyPPS
TRIS Control
1
0
PPS
CWGxD
STRD(1)
CWG_shutdown
Note 1:
STRx is held to 1 in all modes other than Output Steering Mode.
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30.5
Dead-Band Control
The dead-band control provides non-overlapping PWM
signals to prevent shoot-through current in PWM
switches. Dead-band operation is employed for HalfBridge and Full-Bridge modes. The CWG contains two
6-bit dead-band counters. One is used for the rising
edge of the input source control in Half-Bridge mode or
for reverse dead-band Full-Bridge mode. The other is
used for the falling edge of the input source control in
Half-Bridge mode or for forward dead band in FullBridge mode.
Dead band is timed by counting CWG clock periods
from zero up to the value in the rising or falling deadband counter registers. See CWG1DBR and
CWG1DBF registers, respectively.
30.5.1
DEAD-BAND FUNCTIONALITY IN
HALF-BRIDGE MODE
In Half-Bridge mode, the dead-band counters dictate
the delay between the falling edge of the normal output
and the rising edge of the inverted output. This can be
seen in Figure 30-9.
30.5.2
DEAD-BAND FUNCTIONALITY IN
FULL-BRIDGE MODE
In Full-Bridge mode, the dead-band counters are used
when undergoing a direction change. The MODE
bit of the CWG1CON0 register can be set or cleared
while the CWG is running, allowing for changes from
Forward to Reverse mode. The CWG1A and CWG1C
signals will change upon the first rising input edge
following a direction change, but the modulated signals
(CWG1B or CWG1D, depending on the direction of the
change) will experience a delay dictated by the deadband counters. This is demonstrated in Figure 30-3.
2016-2018 Microchip Technology Inc.
30.6
Rising Edge and Reverse Dead
Band
CWG1DBR controls the rising edge dead-band time at
the leading edge of CWG1A (Half-Bridge mode) or the
leading edge of CWG1B (Full-Bridge mode). The
CWG1DBR value is double-buffered. When EN = 0,
the CWG1DBR register is loaded immediately when
CWG1DBR is written. When EN = 1, then software
must set the LD bit of the CWG1CON0 register, and the
buffer will be loaded at the next falling edge of the CWG
input signal. If the input source signal is not present for
enough time for the count to be completed, no output
will be seen on the respective output.
30.7
Falling Edge and Forward Dead
Band
CWG1DBF controls the dead-band time at the leading
edge of CWG1B (Half-Bridge mode) or the leading
edge of CWG1D (Full-Bridge mode). The CWG1DBF
value is double-buffered. When EN = 0, the
CWG1DBF register is loaded immediately when
CWG1DBF is written. When EN = 1 then software
must set the LD bit of the CWG1CON0 register, and
the buffer will be loaded at the next falling edge of the
CWG input signal. If the input source signal is not
present for enough time for the count to be completed,
no output will be seen on the respective output.
Refer to Figure 30-6 and Figure 30-7 for examples.
DS40001866B-page 383
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FIGURE 30-6:
DEAD-BAND OPERATION CWG1DBR = 01H, CWG1DBF = 02H
cwg_clock
Input Source
CWG1A
CWG1B
DEAD-BAND OPERATION, CWG1DBR = 03H, CWG1DBF = 04H, SOURCE SHORTER THAN DEAD BAND
cwg_clock
Input Source
CWG1A
CWG1B
source shorter than dead band
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FIGURE 30-7:
PIC16(L)F15356/75/76/85/86
30.8
Dead-Band Uncertainty
EQUATION 30-1:
When the rising and falling edges of the input source
are asynchronous to the CWG clock, it creates uncertainty in the dead-band time delay. The maximum
uncertainty is equal to one CWG clock period. Refer to
Equation 30-1 for more details.
DEAD-BAND
UNCERTAINTY
1
TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock
Example:
FCWG_CLOCK = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = ---------------------------Fcwg_clock
1 = ----------------16MHz
= 62.5ns
FIGURE 30-8:
EXAMPLE OF PWM DIRECTION CHANGE
MODE0
CWG1A
CWG1B
CWG1C
CWG1D
No delay
CWG1DBR
No delay
CWG1DBF
CWG1_data
Note 1:
2:
3:
WGPOL{ABCD} = 0
The direction bit MODE (Register 30-1) can be written any time during the PWM cycle, and takes effect at the
next rising CWG1_data.
When changing directions, CWG1A and CWG1C switch at rising CWG1_data; modulated CWG1B and CWG1D
are held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.
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FIGURE 30-9:
CWG HALF-BRIDGE MODE OPERATION
CWG1_clock
CWG1A
CWG1C
Falling Event Dead Band
Rising Event Dead Band
Rising Event D
Falling Event Dead Band
CWG1B
CWG1D
CWG1_data
Note: CWG1_rising_src = CCP1_out, CWG1_falling_src = ~CCP1_out
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30.9
CWG Steering Mode
30.9.1
In Steering mode (MODE = 00x), the CWG allows any
combination of the CWG1x pins to be the modulated
signal. The same signal can be simultaneously available on multiple pins, or a fixed-value output can be
presented.
When the respective STRx bit of CWG1OCON0 is ‘0’,
the corresponding pin is held at the level defined. When
the respective STRx bit of CWG1OCON0 is ‘1’, the pin
is driven by the input data signal. The user can assign
the input data signal to one, two, three, or all four output
pins.
The POLx bits of the CWG1CON1 register control the
signal polarity only when STRx = 1.
The CWG auto-shutdown operation also applies in
Steering modes as described in Section 30.10 “AutoShutdown”. An auto-shutdown event will only affect
pins that have STRx = 1.
FIGURE 30-10:
STEERING SYNCHRONIZATION
Changing the MODE bits allows for two modes of
steering, synchronous and asynchronous.
When MODE = 000, the steering event is asynchronous and will happen at the end of the instruction that
writes to STRx (that is, immediately). In this case, the
output signal at the output pin may be an incomplete
waveform. This can be useful for immediately removing
a signal from the pin.
When MODE = 001, the steering update is synchronous and occurs at the beginning of the next rising
edge of the input data signal. In this case, steering the
output on/off will always produce a complete waveform.
Figure 30-10 and Figure 30-11 illustrate the timing of
asynchronous and synchronous steering, respectively.
EXAMPLE OF ASYNCHRONOUS STEERING EVENT (MODE = 000)
Rising Event
CWG1_data
(Rising and Falling Source)
STR
CWG1
OVR Data
OVR
follows CWG1_data
FIGURE 30-11:
EXAMPLE OF STEERING EVENT (MODE = 001)
CWG1_data
(Rising and Falling Source)
STR
CWG1
OVR Data
OVR Data
follows CWG1_data
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30.10 Auto-Shutdown
30.11 Operation During Sleep
Auto-shutdown is a method to immediately override the
CWG output levels with specific overrides that allow for
safe shutdown of the circuit. The shutdown state can be
either cleared automatically or held until cleared by
software. The auto-shutdown circuit is illustrated in
Figure 30-12.
The CWG module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock and input sources selected
remain active.
30.10.1
• CWG module is enabled
• Input source is active
• HFINTOSC is selected as the clock source,
regardless of the system clock source selected.
SHUTDOWN
The shutdown state can be entered by either of the
following two methods:
• Software generated
• External Input
30.10.1.1
Software Generated Shutdown
Setting the SHUTDOWN bit of the CWG1AS0 register
will force the CWG into the shutdown state.
When the auto-restart is disabled, the shutdown state
will persist as long as the SHUTDOWN bit is set.
The HFINTOSC remains active during Sleep when all
the following conditions are met:
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
source, when the CWG is enabled and the input source
is active, then the CPU will go idle during Sleep, but the
HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the
Sleep mode current.
When auto-restart is enabled, the SHUTDOWN bit will
clear automatically and resume operation on the next
rising edge event.
30.10.2
EXTERNAL INPUT SOURCE
External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to the
selected override levels without software delay. Several
input sources can be selected to cause a shutdown condition. All input sources are active-low. The sources are:
•
•
•
•
Comparator C1OUT_sync
Comparator C2OUT_sync
Timer2 – TMR2_postscaled
CWG1IN input pin
Shutdown inputs are selected using the CWG1AS1
register (Register 30-6).
Note:
Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state cannot be cleared, except by disabling autoshutdown, as long as the shutdown input
level persists.
2016-2018 Microchip Technology Inc.
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2016-2018 Microchip Technology Inc.
FIGURE 30-12:
CWG SHUTDOWN BLOCK DIAGRAM
Write ‘1’ to
SHUTDOWN bit
Rev. 10-000172F
3/14/2017
PPS
INAS
CWGxINPPS
C1OUT_sync
C1AS
C2OUT_sync
C2AS
TMR2_postscaled
TMR2AS
S
Q
SHUTDOWN
S
D
FREEZE
REN
Write ‘0’ to
SHUTDOWN bit
Q
CWG_shutdown
R
CWG_data
CK
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30.12 Configuring the CWG
30.12.2
The following steps illustrate how to properly configure
the CWG.
After an auto-shutdown event has occurred, there are
two ways to resume operation:
1.
• Software controlled
• Auto-restart
2.
3.
4.
5.
Ensure that the TRIS control bits corresponding
to the desired CWG pins for your application are
set so that the pins are configured as inputs.
Clear the EN bit, if not already cleared.
Set desired mode of operation with the MODE
bits.
Set desired dead-band times, if applicable to
mode, with the CWG1DBR and CWG1DBF
registers.
Setup the following controls in the CWG1AS0
and CWG1AS1 registers.
a. Select the desired shutdown source.
b. Select both output overrides to the desired
levels (this is necessary even if not using autoshutdown because start-up will be from a shutdown state).
c. Set which pins will be affected by auto-shutdown with the CWG1AS1 register.
d. Set the SHUTDOWN bit and clear the REN bit.
6.
7.
Select the desired input source using the
CWG1DAT register.
Configure the following controls.
a. Select desired clock source
CWG1CLKCON register.
using
the
AUTO-SHUTDOWN RESTART
The restart method is selected with the REN bit of the
CWG1CON2 register. Waveforms of software controlled and automatic restarts are shown in Figure 30-13
and Figure 30-14.
30.12.2.1
Software Controlled Restart
When the REN bit of the CWG1AS0 register is cleared,
the CWG must be restarted after an auto-shutdown
event by software. Clearing the shutdown state
requires all selected shutdown inputs to be low, otherwise the SHUTDOWN bit will remain set. The overrides
will remain in effect until the first rising edge event after
the SHUTDOWN bit is cleared. The CWG will then
resume operation.
30.12.2.2
Auto-Restart
When the REN bit of the CWG1CON2 register is set,
the CWG will restart from the auto-shutdown state
automatically. The SHUTDOWN bit will clear automatically when all shutdown sources go low. The overrides
will remain in effect until the first rising edge event after
the SHUTDOWN bit is cleared. The CWG will then
resume operation.
b. Select the desired output polarities using the
CWG1CON1 register.
c. Set the output enables for the desired outputs.
8.
9.
Set the EN bit.
Clear TRIS control bits corresponding to the
desired output pins to configure these pins as
outputs.
10. If auto-restart is to be used, set the REN bit and
the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit to
start the CWG.
30.12.1
PIN OVERRIDE LEVELS
The levels driven to the output pins, while the shutdown
input is true, are controlled by the LSBD and LSAC bits
of the CWG1AS0 register. LSBD controls the
CWG1B and D override levels and LSAC controls
the CWG1A and C override levels. The control bit logic
level corresponds to the output logic drive level while in
the shutdown state. The polarity control does not affect
the override level.
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FIGURE 30-13: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01)
Shutdown Event Ceases
REN Cleared by Software
CWG Input
Source
Shutdown Source
SHUTDOWN
Tri-State (No Pulse)
CWG1B
CWG1D
Tri-State (No Pulse)
No Shutdown
Output Resumes
Shutdown
FIGURE 30-14:
SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01)
Shutdown Event Ceases
REN auto-cleared by hardware
CWG Input
Source
Shutdown Source
SHUTDOWN
DS40001866B-page 391
CWG1A
CWG1C
Tri-State (No Pulse)
CWG1B
CWG1D
Tri-State (No Pulse)
No Shutdown
Shutdown
Output Resumes
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CWG1A
CWG1C
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30.13 Register Definitions: CWG Control
Long bit name prefixes for the CWG peripherals are
shown in Section 1.1 “Register and Bit Naming
Conventions”.
REGISTER 30-1:
CWG1CON0: CWG1 CONTROL REGISTER 0
R/W-0/0
R/W/HC-0/0
U-0
U-0
U-0
EN
LD(1)
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
MODE
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
EN: CWG1 Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
LD: CWG1 Load Buffer bits(1)
1 = Buffers to be loaded on the next rising/falling event
0 = Buffers not loaded
bit 5-3
Unimplemented: Read as ‘0’
bit 2-0
MODE: CWG1 Mode bits
111 = Reserved
110 = Reserved
101 = CWG outputs operate in Push-Pull mode
100 = CWG outputs operate in Half-Bridge mode
011 = CWG outputs operate in Reverse Full-Bridge mode
010 = CWG outputs operate in Forward Full-Bridge mode
001 = CWG outputs operate in Synchronous Steering mode
000 = CWG outputs operate in Steering mode
Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.
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REGISTER 30-2:
CWG1CON1: CWG1 CONTROL REGISTER 1
U-0
U-0
R-x
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
IN
—
POLD
POLC
POLB
POLA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5
IN: CWG Input Value bit
bit 4
Unimplemented: Read as ‘0’
bit 3
POLD: CWG1D Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 2
POLC: CWG1C Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 1
POLB: CWG1B Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
bit 0
POLA: CWG1A Output Polarity bit
1 = Signal output is inverted polarity
0 = Signal output is normal polarity
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REGISTER 30-3:
CWG1DBR: CWG1 RISING DEAD-BAND COUNTER REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
DBR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
DBR: Rising Event Dead-Band Value for Counter bits
REGISTER 30-4:
CWG1DBF: CWG1 FALLING DEAD-BAND COUNTER REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
DBF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
DBF: Falling Event Dead-Band Value for Counter bits
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REGISTER 30-5:
CWG1AS0: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 0
R/W/HS-0/0
R/W-0/0
SHUTDOWN(1, 2)
REN
R/W-0/0
R/W-1/1
LSBD
R/W-0/0
R/W-1/1
LSAC
U-0
U-0
—
—
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SHUTDOWN: Auto-Shutdown Event Status bit(1, 2)
1 = An Auto-Shutdown state is in effect
0 = No Auto-shutdown event has occurred
bit 6
REN: Auto-Restart Enable bit
1 = Auto-restart enabled
0 = Auto-restart disabled
bit 5-4
LSBD: CWG1B and CWG1D Auto-Shutdown State Control bits
11 =A logic ‘1’ is placed on CWG1B/D when an auto-shutdown event is present
10 =A logic ‘0’ is placed on CWG1B/D when an auto-shutdown event is present
01 =Pin is tri-stated on CWG1B/D when an auto-shutdown event is present
00 =The inactive state of the pin, including polarity, is placed on CWG1B/D after the required deadband interval
bit 3-2
LSAC: CWG1A and CWG1C Auto-Shutdown State Control bits
11 =A logic ‘1’ is placed on CWG1A/C when an auto-shutdown event is present
10 =A logic ‘0’ is placed on CWG1A/C when an auto-shutdown event is present
01 =Pin is tri-stated on CWG1A/C when an auto-shutdown event is present
00 =The inactive state of the pin, including polarity, is placed on CWG1A/C after the required deadband interval
bit 1-0
Unimplemented: Read as ‘0’
Note 1: This bit may be written while EN = 0 (CWG1CON0 register) to place the outputs into the shutdown
configuration.
2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is
cleared.
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REGISTER 30-6:
CWG1AS1: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 1
U-1
U-1
U-1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
AS4E
AS3E
AS2E
AS1E
AS0E
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-5
Unimplemented: Read as ‘0’
bit 4
AS4E: CLC2 Output bit
1 = LC2_out shut-down is enabled
0 = LC2_out shut-down is disabled
bit 3
AS3E: Comparator C2 Output bit
1 = C2 output shut-down is enabled
0 = C2 output shut-down is disabled
bit 2
AS2E: Comparator C1 Output bit
1 = C1 output shut-down is enabled
0 = C1 output shut-down is disabled
bit 2
AS1E: TMR2 Postscale Output bit
1 = TMR2 Postscale shut-down is enabled
0 = TMR2 Postscale shut-down is disabled
bit 0
AS0E: CWG1 Input Pin bit
1 = Input pin selected by CWG1PPS shut-down is enabled
0 = Input pin selected by CWG1PPS shut-down is disabled
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CWG1STR: CWG1 STEERING CONTROL REGISTER(1)
REGISTER 30-7:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
OVRD
OVRC
OVRB
OVRA
STRD(2)
STRC(2)
STRB(2)
STRA(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
OVRD: Steering Data D bit
bit 6
OVRC: Steering Data C bit
bit 5
OVRB: Steering Data B bit
bit 4
OVRA: Steering Data A bit
bit 3
STRD: Steering Enable D bit(2)
1 = CWG1D output has the CWG1_data waveform with polarity control from POLD bit
0 = CWG1D output is assigned the value of OVRD bit
bit 2
STRC: Steering Enable C bit(2)
1 = CWG1C output has the CWG1_data waveform with polarity control from POLC bit
0 = CWG1C output is assigned the value of OVRC bit
bit 1
STRB: Steering Enable B bit(2)
1 = CWG1B output has the CWG1_data waveform with polarity control from POLB bit
0 = CWG1B output is assigned the value of OVRB bit
bit 0
STRA: Steering Enable A bit(2)
1 = CWG1A output has the CWG1_data waveform with polarity control from POLA bit
0 = CWG1A output is assigned the value of OVRA bit
Note 1: The bits in this register apply only when MODE = 00x.
2: This bit is effectively double-buffered when MODE = 001.
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REGISTER 30-8:
CWG1CLK: CWG1 CLOCK SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
—
—
CS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-1
Unimplemented: Read as ‘0’
bit 0
CS: CWG1 Clock Selection bit
1 = HFINTOSC 16 MHz is selected
0 = FOSC is selected
REGISTER 30-9:
CWG1DAT: CWG1 INPUT SELECTION REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
DAT: CWG1 Input Selection bits
1111 =Reserved. No channel connected.
1110 =Reserved. No channel connected.
1101 =LC4_out
1100 =LC3_out
1011 =LC2_out
1010 =LC1_out
1001 =Comparator C2 out
1000 =Comparator C1 out
0111 =NCO1 output
0110 =PWM6_out
0101 =PWM5_out
0100 =PWM4_out
0011 =PWM3_out
0010 =CCP2_out
0001 =CCP1_out
0000 =CWG11CLK
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TABLE 30-3:
SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CWG1CLKCON
—
—
—
—
—
—
CWG1DAT
—
—
—
—
CWG1DBR
—
—
Register
on Page
—
CS
398
398
DBR
—
—
CWG1CON0
EN
LD
—
—
—
CWG1CON1
—
—
IN
—
POLD
CWG1AS0
SHUTDOWN
REN
CWG1AS1
—
—
—
AS4E
AS3E
OVRD
OVRC
OVRB
OVRA
STRD
Legend:
Bit 0
DAT
CWG1DBF
CWG1STR
Bit 1
394
DBF
LSBD
394
MODE
POLC
397
POLB
POLA
393
—
—
395
AS2E
AS1E
AS0E
396
STRC
STRB
STRA
397
LSAC
– = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.
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31.0
CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) module provides
programmable logic that operates outside the speed
limitations of software execution. The logic cell selects
from 40 input signals and, through the use of
configurable gates, reduces the inputs to four logic
lines that drive one of eight selectable single-output
logic functions.
Input sources are a combination of the following:
•
•
•
•
I/O pins
Internal clocks
Peripherals
Register bits
The output can be directed internally to peripherals and
to an output pin.
Refer to Figure 31-1 for a simplified diagram showing
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
- OR-XNOR
• Latches
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
The CLC modules available are shown in Table 31-1.
TABLE 31-1:
AVAILABLE CLC MODULES
Device
CLC1 CLC2 CLC3 CLC4
PIC16(L)F15356/75/76/85/
86
Note:
●
●
●
●
The CLC1, CLC2, CLC3 and CLC4 are
four separate module instances of the
same CLC module design. Throughout
this section, the lower case ‘x’ in register
and bit names is a generic reference to
the CLC number (which should be substituted with 1, 2, 3, or 4 during code development). For example, the control register
is generically described in this chapter as
CLCxCON, but the actual device registers
are CLC1CON, CLC2CON, CLC3CON
and CLC4CON. Similarly, the LCxEN bit
represents the LC1EN, LC2EN, LC3EN
and LC4EN bits.
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FIGURE 31-1:
CLCx SIMPLIFIED BLOCK DIAGRAM
Rev. 10-000025H
11/9/2016
D
OUT
CLCxOUT
Q
Q1
.
.
.
LCx_in[n-2]
LCx_in[n-1]
LCx_in[n]
CLCx_out
Input Data Selection Gates(1)
LCx_in[0]
LCx_in[1]
LCx_in[2]
EN
lcxg1
lcxg2
lcxg3
to Peripherals
CLCxPPS
Logic
lcxq
Function
PPS
CLCx
(2)
lcxg4
POL
MODE
TRIS
Interrupt
det
INTP
INTN
set bit
CLCxIF
Interrupt
det
Note 1:
2:
See Figure 31-2: Input Data Selection and Gating.
See Figure 31-3: Programmable Logic Functions.
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31.1
CLCx Setup
Programming the CLCx module is performed by
configuring the four stages in the logic signal flow. The
four stages are:
•
•
•
•
Data selection
Data gating
Logic function selection
Output polarity
TABLE 31-2:
CLCx DATA INPUT SELECTION
LCxDyS
Value
CLCx Input Source
101000 to 111111 [40+]
Reserved
100111 [39]
CWG1B output
100110 [38]
CWG1A output
100101 [37]
MSSP2 SCK output
100100 [36]
MSSP2 SDO output
100011 [35]
MSSP1 SCK output
Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
100010 [34]
MSSP1 SDO output
100001 [33]
EUSART2 (TX/CK) output
31.1.1
DATA SELECTION
There are 40 signals available as inputs to the
configurable logic. Four 40-input multiplexers are used
to select the inputs to pass on to the next stage.
Data selection is through four multiplexers as indicated
on the left side of Figure 31-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 31-2 correlates the generic input name to the
actual signal for each CLC module. The column labeled
‘LCxDyS Value’ indicates the MUX selection code
for the selected data input. LCxDyS is an abbreviation to
identify specific multiplexers: LCxD1S through
LCxD4S.
Data inputs are selected with CLCxSEL0 through
CLCxSEL3
registers
(Register 31-3
through
Register 31-6).
2016-2018 Microchip Technology Inc.
100000 [32]
EUSART2 (DT) output
011111 [31]
EUSART1 (TX/CK) output
011110 [30]
EUSART1 (DT) output
011101 [29]
CLC4 output
011100 [28]
CLC3 output
011011 [27]
CLC2 output
011010 [26]
CLC1 output
011001 [25]
IOCIF
011000 [24]
ZCD output
010111 [23]
C2OUT
010110 [22]
C1OUT
010101 [21]
NCO1 output
010100 [20]
PWM6 output
010011 [19]
PWM5 output
010010 [18]
PWM4 output
010001 [17]
PWM3 output
010000 [16]
CCP2 output
001111 [15]
CCP1 output
001110 [14]
Timer2 overflow
001101 [13]
Timer1 overflow
001100 [12]
Timer0 overflow
001011 [11]
CLKR
001010 [10]
ADCRC
001001 [9]
SOSC
001000 [8]
MFINTOSC (32 kHz)
000111 [7]
MFINTOSC (500 kHz)
000110 [6]
LFINTOSC
000101 [5]
HFINTOSC
000100 [4]
FOSC
000011 [3]
CLCIN3PPS
000010 [2]
CLCIN2PPS
000001 [1]
CLCIN1PPS
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31.1.2
DATA GATING
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
Note:
Data gating is undefined at power-up.
The gate stage is more than just signal direction. The
gate can be configured to direct each input signal as
inverted or non-inverted data. The output of each gate
can be inverted before going on to the logic function
stage.
The gating is in essence a 1-to-4 input AND/NAND/OR/
NOR gate. When every input is inverted and the output
is inverted, the gate is an OR of all enabled data inputs.
When the inputs and output are not inverted, the gate
is an AND or all enabled inputs.
Table 31-3 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
TABLE 31-3:
CLCxGLSy
DATA GATING LOGIC
LCxGyPOL
Gate Logic
0x55
1
4-input AND
0x55
0
4-input NAND
0xAA
1
4-input NOR
0xAA
0
4-input OR
0x00
0
Logic 0
0x00
1
Logic 1
Data gating is indicated in the right side of Figure 31-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
31.1.3
LOGIC FUNCTION
There are eight available logic functions including:
•
•
•
•
•
•
•
•
AND-OR
OR-XOR
AND
S-R Latch
D Flip-Flop with Set and Reset
D Flip-Flop with Reset
J-K Flip-Flop with Reset
Transparent Latch with Set and Reset
Logic functions are shown in Figure 31-2. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
CLCx itself.
31.1.4
OUTPUT POLARITY
The last stage in the Configurable Logic Cell is the
output polarity. Setting the LCxPOL bit of the CLCxPOL
register inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
•
•
•
•
Gate 1: CLCxGLS0 (Register 31-7)
Gate 2: CLCxGLS1 (Register 31-8)
Gate 3: CLCxGLS2 (Register 31-9)
Gate 4: CLCxGLS3 (Register 31-10)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
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31.2
CLCx Interrupts
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The CLCxIF bit of the associated PIR5 register will be
set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising
edge interrupts and the LCxINTN bit enables falling
edge interrupts. Both are located in the CLCxCON
register.
To fully enable the interrupt, set the following bits:
• CLCxIE bit of the PIE5 register
• LCxINTP bit of the CLCxCON register (for a rising
edge detection)
• LCxINTN bit of the CLCxCON register (for a
falling edge detection)
• PEIE and GIE bits of the INTCON register
The CLCxIF bit of the PIR5 register, must be cleared in
software as part of the interrupt service. If another edge
is detected while this flag is being cleared, the flag will
still be set at the end of the sequence.
31.3
Output Mirror Copies
Mirror copies of all LCxCON output bits are contained
in the CLCxDATA register. Reading this register reads
the outputs of all CLCs simultaneously. This prevents
any reading skew introduced by testing or reading the
LCxOUT bits in the individual CLCxCON registers.
31.4
Effects of a Reset
31.6
CLCx Setup Steps
The following steps should be followed when setting up
the CLCx:
• Disable CLCx by clearing the LCxEN bit.
• Select desired inputs using CLCxSEL0 through
CLCxSEL3 registers (See Table 31-2).
• Clear any associated ANSEL bits.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
• Select the gate output polarities with the
LCxGyPOL bits of the CLCxPOL register.
• Select the desired logic function with the
LCxMODE bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate output polarity step).
• If driving a device pin, set the desired pin PPS
control register and also clear the TRIS bit
corresponding to that output.
• If interrupts are desired, configure the following
bits:
- Set the LCxINTP bit in the CLCxCON register
for rising event.
- Set the LCxINTN bit in the CLCxCON
register for falling event.
- Set the CLCxIE bit of the PIE5 register.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the LCxEN bit of the
CLCxCON register.
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
31.5
Operation During Sleep
The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
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FIGURE 31-2:
LCx_in
INPUT DATA SELECTION AND GATING
Data Selection
Data GATE 1
lcxd1T
LCxD1G1T
lcxd1N
LCxD1G1N
LCx_in
LCxD2G1T
LCxD1S
LCxD2G1N
lcxg1
LCx_in
LCxD3G1T
lcxd2T
LCxG1POL
LCxD3G1N
lcxd2N
LCxD4G1T
LCx_in
LCxD2S
LCxD4G1N
LCx_in
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
LCx_in
lcxg3
LCxD3S
(Same as Data GATE 1)
Data GATE 4
LCx_in
lcxg4
lcxd4T
(Same as Data GATE 1)
lcxd4N
LCx_in
LCxD4S
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FIGURE 31-3:
PROGRAMMABLE LOGIC FUNCTIONS
Rev. 10-000122A
5/18/2016
AND-OR
OR-XOR
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxq
lcxg3
lcxg3
lcxg4
lcxg4
LCxMODE = 000
LCxMODE = 001
4-input AND
S-R Latch
lcxg1
lcxg1
S
Q
lcxq
Q
lcxq
lcxg2
lcxg2
lcxq
lcxg3
lcxg3
R
lcxg4
lcxg4
LCxMODE = 010
LCxMODE = 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
lcxg4
lcxg2
D
S
lcxg4
Q
lcxq
D
lcxg2
lcxg1
lcxg1
R
lcxg3
R
lcxg3
LCxMODE = 100
LCxMODE = 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
lcxg4
lcxg2
J
Q
lcxq
lcxg2
D
lcxg3
LE
S
Q
lcxq
lcxg1
lcxg4
K
R
lcxg3
R
lcxg1
LCxMODE = 110
2016-2018 Microchip Technology Inc.
LCxMODE = 111
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31.7
Register Definitions: CLC Control
REGISTER 31-1:
CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
R/W-0/0
U-0
R-0/0
R/W-0/0
R/W-0/0
LCxEN
—
LCxOUT
LCxINTP
LCxINTN
R/W-0/0
R/W-0/0
R/W-0/0
LCxMODE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxEN: Configurable Logic Cell Enable bit
1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output
bit 6
Unimplemented: Read as ‘0’
bit 5
LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT
bit 4
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on CLCxOUT
0 = CLCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on CLCxOUT
0 = CLCxIF will not be set
bit 2-0
LCxMODE: Configurable Logic Cell Functional Mode bits
111 =Cell is 1-input transparent latch with S and R
110 =Cell is J-K flip-flop with R
101 =Cell is 2-input D flip-flop with R
100 =Cell is 1-input D flip-flop with S and R
011 =Cell is S-R latch
010 =Cell is 4-input AND
001 =Cell is OR-XOR
000 =Cell is AND-OR
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REGISTER 31-2:
CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-0/0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxPOL
—
—
—
LCxG4POL
LCxG3POL
LCxG2POL
LCxG1POL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxPOL: CLCxOUT Output Polarity Control bit
1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4
Unimplemented: Read as ‘0’
bit 3
LCxG4POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
bit 2
LCxG3POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
bit 1
LCxG2POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted
bit 0
LCxG1POL: Gate 0 Output Polarity Control bit
1 = The output of gate 0 is inverted when applied to the logic cell
0 = The output of gate 0 is not inverted
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REGISTER 31-3:
CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD1S
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
LCxD1S: CLCx Data1 Input Selection bits
See Table 31-2.
REGISTER 31-4:
CLCxSEL1: GENERIC CLCx DATA 1 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD2S
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
LCxD2S: CLCx Data 2 Input Selection bits
See Table 31-2.
REGISTER 31-5:
CLCxSEL2: GENERIC CLCx DATA 2 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD3S
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
LCxD3S: CLCx Data 3 Input Selection bits
See Table 31-2.
REGISTER 31-6:
CLCxSEL3: GENERIC CLCx DATA 3 SELECT REGISTER
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxD4S
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
LCxD4S: CLCx Data 4 Input Selection bits
See Table 31-2.
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REGISTER 31-7:
CLCxGLS0: GATE 0 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N
LCxG1D3T
LCxG1D3N
LCxG1D2T
LCxG1D2N
LCxG1D1T
LCxG1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit
1 = CLCIN3 (true) is gated into CLCx Gate 0
0 = CLCIN3 (true) is not gated into CLCx Gate 0
bit 6
LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 0
0 = CLCIN3 (inverted) is not gated into CLCx Gate 0
bit 5
LCxG1D3T: Gate 0 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 0
0 = CLCIN2 (true) is not gated into CLCx Gate 0
bit 4
LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 0
0 = CLCIN2 (inverted) is not gated into CLCx Gate 0
bit 3
LCxG1D2T: Gate 0 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 0
0 = CLCIN1 (true) is not gated into l CLCx Gate 0
bit 2
LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 0
0 = CLCIN1 (inverted) is not gated into CLCx Gate 0
bit 1
LCxG1D1T: Gate 0 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 0
0 = CLCIN0 (true) is not gated into CLCx Gate 0
bit 0
LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 0
0 = CLCIN0 (inverted) is not gated into CLCx Gate 0
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REGISTER 31-8:
CLCxGLS1: GATE 1 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N
LCxG2D3T
LCxG2D3N
LCxG2D2T
LCxG2D2N
LCxG2D1T
LCxG2D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG2D4T: Gate 1 Data 4 True (non-inverted) bit
1 = CLCIN3 (true) is gated into CLCx Gate 1
0 = CLCIN3 (true) is not gated into CLCx Gate 1
bit 6
LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 1
0 = CLCIN3 (inverted) is not gated into CLCx Gate 1
bit 5
LCxG2D3T: Gate 1 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 1
0 = CLCIN2 (true) is not gated into CLCx Gate 1
bit 4
LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 1
0 = CLCIN2 (inverted) is not gated into CLCx Gate 1
bit 3
LCxG2D2T: Gate 1 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 1
0 = CLCIN1 (true) is not gated into CLCx Gate 1
bit 2
LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 1
0 = CLCIN1 (inverted) is not gated into CLCx Gate 1
bit 1
LCxG2D1T: Gate 1 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 1
0 = CLCIN0 (true) is not gated into CLCx Gate1
bit 0
LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 1
0 = CLCIN0 (inverted) is not gated into CLCx Gate 1
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REGISTER 31-9:
CLCxGLS2: GATE 2 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N
LCxG3D3T
LCxG3D3N
LCxG3D2T
LCxG3D2N
LCxG3D1T
LCxG3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG3D4T: Gate 2 Data 4 True (non-inverted) bit
1 = CLCIN3 (true) is gated into CLCx Gate 2
0 = CLCIN3 (true) is not gated into CLCx Gate 2
bit 6
LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 2
0 = CLCIN3 (inverted) is not gated into CLCx Gate 2
bit 5
LCxG3D3T: Gate 2 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 2
0 = CLCIN2 (true) is not gated into CLCx Gate 2
bit 4
LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 2
0 = CLCIN2 (inverted) is not gated into CLCx Gate 2
bit 3
LCxG3D2T: Gate 2 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 2
0 = CLCIN1 (true) is not gated into CLCx Gate 2
bit 2
LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 2
0 = CLCIN1 (inverted) is not gated into CLCx Gate 2
bit 1
LCxG3D1T: Gate 2 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 2
0 = CLCIN0 (true) is not gated into CLCx Gate 2
bit 0
LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 2
0 = CLCIN0 (inverted) is not gated into CLCx Gate 2
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REGISTER 31-10: CLCxGLS3: GATE 3 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N
LCxG4D3T
LCxG4D3N
LCxG4D2T
LCxG4D2N
LCxG4D1T
LCxG4D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG4D4T: Gate 3 Data 4 True (non-inverted) bit
1 = CLCIN3 (true) is gated into CLCx Gate 3
0 = CLCIN3 (true) is not gated into CLCx Gate 3
bit 6
LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit
1 = CLCIN3 (inverted) is gated into CLCx Gate 3
0 = CLCIN3 (inverted) is not gated into CLCx Gate 3
bit 5
LCxG4D3T: Gate 3 Data 3 True (non-inverted) bit
1 = CLCIN2 (true) is gated into CLCx Gate 3
0 = CLCIN2 (true) is not gated into CLCx Gate 3
bit 4
LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit
1 = CLCIN2 (inverted) is gated into CLCx Gate 3
0 = CLCIN2 (inverted) is not gated into CLCx Gate 3
bit 3
LCxG4D2T: Gate 3 Data 2 True (non-inverted) bit
1 = CLCIN1 (true) is gated into CLCx Gate 3
0 = CLCIN1 (true) is not gated into CLCx Gate 3
bit 2
LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit
1 = CLCIN1 (inverted) is gated into CLCx Gate 3
0 = CLCIN1 (inverted) is not gated into CLCx Gate 3
bit 1
LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit
1 = CLCIN0 (true) is gated into CLCx Gate 3
0 = CLCIN0 (true) is not gated into CLCx Gate 3
bit 0
LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit
1 = CLCIN0 (inverted) is gated into CLCx Gate 3
0 = CLCIN0 (inverted) is not gated into CLCx Gate 3
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REGISTER 31-11: CLCDATA: CLC DATA OUTPUT
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
MLC4OUT
MLC3OUT
MLC2OUT
MLC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
MLC4OUT: Mirror copy of LC4OUT bit
bit 2
MLC3OUT: Mirror copy of LC3OUT bit
bit 1
MLC2OUT: Mirror copy of LC2OUT bit
bit 0
MLC1OUT: Mirror copy of LC1OUT bit
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TABLE 31-4:
SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
―
―
―
―
―
INTEDG
147
PIR5
CLC4IF
CLC3IF
CLC2IF
CLC1IF
—
—
—
TMR1GIF
161
PIE5
CLC4IE
CLC4IE
CLC2IE
CLC1IE
—
—
—
TMR1GIE
CLC1CON
LC1EN
―
LC1OUT
LC1INTP
LC1INTN
CLC1POL
LC1POL
―
―
―
LC1G4POL
CLC1SEL0
―
―
LC1D1S
409
CLC1SEL1
―
―
LC1D2S
409
409
Name
INTCON
LC1MODE
LC1G3POL
LC1G2POL
153
407
LC1G1POL
408
CLC1SEL2
―
―
LC1D3S
CLC1SEL3
―
―
LC1D4S
CLC1GLS0
―
―
LC1G1D3T
LC1G1D3N
LC1G1D2T
LC1G1D2N
LC1G1D1T
LC1G1D1N
CLC1GLS1
―
―
LC1G2D3T
LC1G2D3N
LC1G2D2T
LC1G2D2N
LC1G2D1T
LC1G2D1N
411
CLC1GLS2
―
―
LC1G3D3T
LC1G3D3N
LC1G3D2T
LC1G3D2N
LC1G3D1T
LC1G3D1N
412
CLC1GLS3
―
―
LC1G4D3T
LC1G4D3N
LC1G4D2T
LC1G4D2N
LC1G4D1T
LC1G4D1N
413
CLC2CON
LC2EN
―
LC2OUT
LC2INTP
LC2INTN
CLC2POL
LC2POL
―
―
―
LC2G4POL
409
LC2MODE
LC2G3POL
LC2G2POL
410
407
LC2G1POL
408
CLC2SEL0
―
―
LC2D1S
409
CLC2SEL1
―
―
LC2D2S
409
CLC2SEL2
―
―
LC2D3S
409
CLC2SEL3
―
―
CLC2GLS0
―
―
LC2G1D3T
LC2G1D3N
LC2G1D2T
LC2G1D2N
LC2G1D1T
LC2G1D1N
410
CLC2GLS1
―
―
LC2G2D3T
LC2G2D3N
LC2G2D2T
LC2G2D2N
LC2G2D1T
LC2G2D1N
411
CLC2GLS2
―
―
LC2G3D3T
LC2G3D3N
LC2G3D2T
LC2G3D2N
LC2G3D1T
LC2G3D1N
412
CLC2GLS3
―
―
LC2G4D3T
LC2G4D3N
LC2G4D2T
LC2G4D2N
LC2G4D1T
LC2G4D1N
413
CLC3CON
LC3EN
―
LC3OUT
LC3INTP
LC3INTN
CLC3POL
LC3POL
―
―
―
LC3G4POL
CLC3SEL0
―
―
LC3D1S
409
CLC3SEL1
―
―
LC3D2S
409
CLC3SEL2
―
―
LC3D3S
409
CLC3SEL3
―
―
LC3D4S
409
CLC3GLS0
―
―
LC3G1D3T
LC3G1D3N
LC3G1D2T
LC3G1D2N
LC3G1D1T
LC3G1D1N
410
CLC3GLS1
―
―
LC3G2D3T
LC3G2D3N
LC3G2D2T
LC3G2D2N
LC3G2D1T
LC3G2D1N
411
CLC3GLS2
―
―
LC3G3D3T
LC3G3D3N
LC3G3D2T
LC3G3D2N
LC3G3D1T
LC3G3D1N
412
CLC3GLS3
―
―
LC3G4D3T
LC3G4D3N
LC3G4D2T
LC3G4D2N
LC3G4D1T
LC3G4D1N
413
CLC4CON
LC4EN
―
LC4OUT
LC4INTP
LC4INTN
CLC4POL
LC4POL
―
―
―
LC4G4POL
CLC4SEL0
―
―
LC4D1S
409
CLC4SEL1
―
―
LC4D2S
409
CLC4SEL2
―
―
LC4D3S
409
CLC4SEL3
―
―
LC4D4S
409
―
―
CLC4GLS0
Legend:
LC2D4S
LC4G1D3T
LC4G1D3N
LC4G1D2T
409
LC3MODE
LC3G3POL
LC3G2POL
407
LC3G1POL
LC4MODE
LC4G3POL
LC4G1D2N
LC4G2POL
LC4G1D1T
408
407
LC4G1POL
LC4G1D1N
408
410
— = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.
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TABLE 31-4:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLC4GLS1
―
―
LC4G2D3T
LC4G2D3N
LC4G2D2T
LC4G2D2N
LC4G2D1T
LC4G2D1N
411
CLC4GLS2
―
―
LC4G3D3T
LC4G3D3N
LC4G3D2T
LC4G3D2N
LC4G3D1T
LC4G3D1N
412
CLC4GLS3
―
―
LC4G4D3T
LC4G4D3N
LC4G4D2T
LC4G4D2N
LC4G4D1T
LC4G4D1N
413
CLCIN0PPS
―
―
CLCIN0PPS
242
CLCIN1PPS
―
―
CLCIN1PPS
242
CLCIN2PPS
―
―
CLCIN2PPS
242
―
―
CLCIN3PPS
242
CLCIN3PPS
Legend:
— = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.
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32.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSPx)
MODULES
32.1
MSSP Module Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
•
•
•
•
•
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-chain connection of slave devices
Figure 32-1 is a block diagram of the SPI interface
module.
FIGURE 32-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Read
Write
SSPxBUF Reg
SSPDATPPS
SDI
PPS
SSPSR Reg
Shift
Clock
bit 0
SDO
PPS
RxyPPS
SS
SS Control
Enable
PPS
SSPSSPPS
Edge
Select
SSPCLKPPS(2)
SCK
SSPM
4
PPS
PPS
TRIS bit
2 (CKP, CKE)
Clock Select
RxyPPS(1)
Edge
Select
(
T2_match
2
)
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPxADD)
Note 1: Output selection for master mode
2: Input selection for slave mode
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The I2C interface supports the following modes and
features:
•
•
•
•
•
•
•
•
•
•
•
•
Note 1: In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCONx register names.
SSPxCON1 and SSPxCON2 registers
control different operational aspects of
the same module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Selectable SDA hold times
2: Throughout this section, generic references to an MSSPx module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names, module I/O signals, and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module
when required.
Figure 32-2 is a block diagram of the I2C interface
module in Master mode. Figure 32-3 is a diagram of the
I2C interface module in Slave mode.
FIGURE 32-2:
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal
data bus
SSPDATPPS(1)
Read
[SSPM]
Write
SDA
SDA in
PPS
SSPxBUF
Baud Rate
Generator
(SSPxADD)
SSPCLKPPS
SCL
PPS
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
(Hold off clock source)
(2)
Receive Enable (RCEN)
MSb
Clock Cntl
SSPSR
PPS
Clock arbitrate/BCOL detect
Shift
Clock
RxyPPS(1)
PPS
RxyPPS(2)
SCL in
Bus Collision
Start bit detect,
Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
Address Match detect
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCL1IF
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
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FIGURE 32-3:
MSSP BLOCK DIAGRAM (I2C SLAVE MODE)
Internal
Data Bus
Read
Write
SSPCLKPPS(2)
SCL
PPS
PPS
Clock
Stretching
RxyPPS(2)
SSPxBUF Reg
Shift
Clock
SSPSR Reg
LSb
MSb
SSPxMSK Reg
SSPDATPPS(1)
SDA
Match Detect
Addr Match
PPS
SSPxADD Reg
PPS
RxyPPS(1)
Start and
Stop bit Detect
Set, Reset
S, P bits
(SSPxSTAT Reg)
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
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32.2
SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a Chip Select known as Slave
Select.
The SPI bus specifies four signal connections:
•
•
•
•
Serial Clock (SCK)
Serial Data Out (SDO)
Serial Data In (SDI)
Slave Select (SS)
Figure 32-1 shows the block diagram of the MSSP
module when operating in SPI mode.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select
connection can be used to address each slave individually.
Figure 32-4 shows a typical connection between a
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. Data is
always shifted out one bit at a time, with the Most
Significant bit (MSb) shifted out first. At the same time,
a new Least Significant bit (LSb) is shifted into the
same register.
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
After eight bits have been shifted out, the master and
slave have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends useful data and slave sends dummy
data.
• Master sends useful data and slave sends useful
data.
• Master sends dummy data and slave sends useful
data.
Transmissions must be performed in multiples of eight
clock pulses. When there is no more data to be transmitted, the master stops sending the clock signal and it
deselects the slave.
Every slave device connected to the bus that has not
been selected through its slave select line must disregard the clock and transmission signals and must not
transmit out any data of its own.
Figure 32-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
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FIGURE 32-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SPI Master
SCK
SCK
SDO
SDI
General I/O
General I/O
SDI
General I/O
SCK
SDO
SPI Slave
#1
SS
SDI
SDO
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
32.2.1
SPI MODE REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
•
•
•
•
•
•
MSSP STATUS register (SSPxSTAT)
MSSP Control register 1 (SSPxCON1)
MSSP Control register 3 (SSPxCON3)
MSSP Data Buffer register (SSPxBUF)
MSSP Address register (SSPxADD)
MSSP Shift register (SSPxSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower six bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
In one SPI master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 32.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.
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32.2.2
SPI MODE OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1 and SSPxSTAT).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN of the
SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the
SSPxCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial port
pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the TRISx
register) appropriately programmed as follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
The MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb first.
The SSPxBUF holds the data that was written to the
SSPxSR until the received data is ready. Once the eight
bits of data have been received, that byte is moved to the
SSPxBUF register. Then, the Buffer Full Detect bit, BF of
the SSPxSTAT register, and the interrupt flag bit, SSPxIF,
are set. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPxCON1
register, will be set. User software must clear the WCOL
bit to allow the following write(s) to the SSPxBUF register
to complete successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF of the SSPxSTAT register, indicates
when SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to be
used, then software polling can be done to ensure that a
write collision does not occur.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register.
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 32-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM = 00xx
= 1010
SPI Slave SSPM = 010x
SDO
SDI
Serial Input Buffer
(SSPxBUF)
SDI
Shift Register
(SSPxSR)
MSb
Serial Input Buffer
(SSPxBUF)
LSb
SCK
General I/O
Processor 1
2016-2018 Microchip Technology Inc.
SDO
Serial Clock
Slave Select
(optional)
Shift Register
(SSPxSR)
MSb
LSb
SCK
SS
Processor 2
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32.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 32-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDO output could be
disabled (programmed as an input). The SSPxSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 32-6, Figure 32-8, Figure 32-9 and
Figure 32-10, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
•
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 * TCY)
FOSC/64 (or 16 * TCY)
Timer2 output/2
FOSC/(4 * (SSPxADD + 1))
Figure 32-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 32-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF
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32.2.4
SPI SLAVE MODE
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPxCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will
generate an interrupt. If enabled, the device will wakeup from Sleep.
32.2.4.1
Daisy-Chain Configuration
The SPI bus can sometimes be connected in a daisychain configuration. The first slave output is connected
to the second slave input, the second slave output is
connected to the third slave input, and so on. The final
slave output is connected to the master input. Each
slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The daisychain feature only requires a single Slave Select line
from the master device.
Figure 32-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPxCON3 register will enable writes
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
32.2.5
SLAVE SELECT
SYNCHRONIZATION
The Slave Select can also be used to synchronize
communication. The Slave Select line is held high until
the master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
eventually become out of sync with the master. If the
slave misses a bit, it will always be one bit off in future
transmissions. Use of the Slave Select line allows the
slave and master to align themselves at the beginning
of each transmission.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPxCON1 = 0100).
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPxCON1 =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPxSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
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FIGURE 32-7:
SPI DAISY-CHAIN CONNECTION
SPI Master
SCK
SCK
SDO
SDI
General I/O
SDI
SPI Slave
#1
SDO
SS
SCK
SDI
SPI Slave
#2
SDO
SS
SCK
SDI
SPI Slave
#3
SDO
SS
FIGURE 32-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
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FIGURE 32-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
FIGURE 32-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 7
bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
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32.2.6
SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmission/
reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
32.3
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues to either transmit or receive
data from the slave device.
FIGURE 32-11:
I2C MASTER/
SLAVE CONNECTION
VDD
SCL
SCL
VDD
Master
Slave
SDA
SDA
I2C MODE OVERVIEW
The Inter-Integrated Circuit (I2C) bus is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A slave device is
controlled through addressing.
The I2C bus specifies two signal connections:
• Serial Clock (SCL)
• Serial Data (SDA)
Figure 32-11 shows the block diagram of the MSSP
module when operating in I2C mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
Figure 32-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
The line is held high to indicate Start and Stop bits.
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is
indicated by a low-to-high transition of the SDA line
while the SCL line is held high.
In some cases, the master may want to maintain
control of the bus and re-initiate another transmission.
If so, the master device may send a Restart condition
in place of the Stop condition or last ACK bit when it is
in Receive mode.
The I2C bus specifies three message protocols:
• Single message where a master writes data to a
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
To begin communication, the master device sends out
a Start condition followed by the address byte of the
slave it intends to communicate with.
This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or
receive data from the slave device.
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32.3.1
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device
may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue.
The master that is communicating with the slave will
attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is opendrain, the slave has the ability to hold that line low until
it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
32.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a transmission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
2016-2018 Microchip Technology Inc.
32.4
I2C MODE OPERATION
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and two
interrupt flags interface the module with the PIC®
microcontroller and user software. Two pins, SDA and
SCL, are exercised by the module to communicate
with other external I2C devices.
32.4.1
BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the
eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and
reads in an acknowledge value on the next clock
pulse.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
32.4.2
DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
32.4.3
SDA AND SCL PINS
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
Note 1: Any device pin can be selected for SDA
and SCL functions with the PPS peripheral. These functions are bidirectional.
The SDA input is selected with the
SSPDATPPS registers. The SCL input is
selected with the SSPCLKPPS registers.
Outputs are selected with the RxyPPS
registers. It is the user’s responsibility to
make the selections so that both the input
and the output for each function is on the
same pin.
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32.4.4
SDA HOLD TIME
32.4.5
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPxCON3 register. Hold time is the time
SDA is held valid after the falling edge of SCL. Setting
the SDAHT bit selects a longer 300 ns minimum hold
time and may help on buses with large capacitance.
TABLE 32-1:
TERM
I2C BUS TERMS
Description
Transmitter
The device which shifts data out
onto the bus.
Receiver
The device which shifts data in
from the bus.
Master
The device that initiates a transfer,
generates clock signals and terminates a transfer.
Slave
The device addressed by the
master.
Multi-master
A bus with more than one device
that can initiate data transfers.
Arbitration
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave device that has received a
Slave
matching address and is actively
being clocked by a master.
Matching
Address byte that is clocked into a
Address
slave that matches the value
stored in SSPxADD.
Write Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Read Request
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is outputting and expected high state.
2016-2018 Microchip Technology Inc.
START CONDITION
The I2C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an active state. Figure 32-12 shows wave
forms for Start and Stop conditions.
32.4.6
STOP CONDITION
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
32.4.7
RESTART CONDITION
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave. Figure 32-13 shows the wave form for a
Restart condition.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can
issue a Restart and the high address byte with the R/
W bit set. The slave logic will then hold the clock and
prepare to clock out data.
32.4.8
START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
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FIGURE 32-12:
I2C START AND STOP CONDITIONS
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
FIGURE 32-13:
Stop
Condition
I2C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
Restart
Data Allowed
Condition
32.4.9
ACKNOWLEDGE SEQUENCE
The 9th SCL pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicates to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The result of an ACK is placed in the ACKSTAT bit of
the SSPxCON2 register.
2016-2018 Microchip Technology Inc.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPxCON2
register is set/cleared to determine the response.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPxSTAT
register or the SSPOV bit of the SSPxCON1 register
are set when a byte is received.
When the module is addressed, after the eighth falling
edge of SCL on the bus, the ACKTIM bit of the
SSPxCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
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32.5
I2C SLAVE MODE OPERATION
The MSSP Slave mode operates in one of four modes
selected by the SSPM bits of SSPxCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operate the
same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
condition.
32.5.1
SLAVE MODE ADDRESSES
The SSPxADD register (Register 32-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPxBUF register and an
interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the
software that anything happened.
The SSP Mask register (Register 32-5) affects the
address matching process. See Section 32.5.9 “SSP
Mask Register” for more information.
32.5.1.1
I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
32.5.1.2
I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb’s of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPxADD. Even if there is not an address
match; SSPxIF and UA are set, and SCL is held low
until SSPxADD is updated to receive a high byte
again. When SSPxADD is updated the UA bit is
cleared. This ensures the module is ready to receive
the high address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave
hardware will then acknowledge the read request and
prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
2016-2018 Microchip Technology Inc.
32.5.2
SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the
SSPxBUF register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPxSTAT
register is set, or bit SSPOV of the SSPxCON1 register
is set. The BOEN bit of the SSPxCON3 register
modifies this operation. For more information see
Register 32-4.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by
software.
When the SEN bit of the SSPxCON2 register is set,
SCL will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register.
32.5.2.1
7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in 7bit Addressing mode. Figure 32-14 and Figure 32-15
is used as a visual reference for this description.
This is a step by step process of what typically must
be done to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Start bit detected.
S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDA low sending an ACK to the
master, and sets SSPxIF bit.
Software clears the SSPxIF bit.
Software reads received address from
SSPxBUF clearing the BF flag.
If SEN = 1; Slave software sets CKP bit to
release the SCL line.
The master clocks out a data byte.
Slave drives SDA low sending an ACK to the
master, and sets SSPxIF bit.
Software clears SSPxIF.
Software reads the received byte from
SSPxBUF clearing BF.
Steps 8-12 are repeated for all received bytes
from the master.
Master sends Stop condition, setting P bit of
SSPxSTAT, and the bus goes idle.
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32.5.2.2
7-bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the eighth
falling edge of SCL. These additional interrupts allows
time for the slave software to decide whether it wants
to ACK the receive address or data byte.
This list describes the steps that need to be taken by
slave software to use these options for I2C
communication. Figure 32-16 displays a module using
both address and data holding. Figure 32-17 includes
the operation with the SEN bit of the SSPxCON2
register set.
1.
S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPxIF is set, and CKP is cleared in hardware after the eighth falling edge of SCL.
3. Slave clears the SSPxIF.
4. Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
5. Slave reads the address value from SSPxBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP in software.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPxIF.
Note: SSPxIF is still set after the ninth falling edge
of SCL even if there is no clock stretching
and BF has been cleared. Only if NACK is
sent to master is SSPxIF not set
11. SSPxIF set, and CKP is cleared in hardware
after eighth falling edge of SCL for a received
data byte.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPxBUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSPxSTAT register.
2016-2018 Microchip Technology Inc.
DS40001866B-page 432
2016-2018 Microchip Technology Inc.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
FIGURE 32-14:
Bus Master sends
Stop condition
From Slave to Master
Receiving Address
SDA
S
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
ACK
8
9
Receiving Data
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
D0 ACK D7
8
9
1
ACK = 1
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
SSPxIF
Cleared by software
Cleared by software
BF
SSPxBUF is read
First byte
of data is
available
in SSPxBUF
SSPOV
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
SSPxIF set on 9th
falling edge of
SCL
DS40001866B-page 433
PIC16(L)F15356/75/76/85/86
SCL
Receiving Data
2016-2018 Microchip Technology Inc.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
FIGURE 32-15:
Bus Master sends
Stop condition
Receive Address
SDA
SCL
S
Receive Data
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
R/W=0 ACK
8
9
SEN
Receive Data
D7
D6
D5
D4
D3
D2
D1
D0
ACK
1
2
3
4
5
6
7
8
9
SEN
ACK
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
P
SSPxIF
Cleared by software
BF
SSPxBUF is read
Cleared by software
SSPxIF set on 9th
falling edge of SCL
First byte
of data is
available
in SSPxBUF
SSPOV
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
CKP
DS40001866B-page 434
CKP is written to ‘1’ in software,
releasing SCL
CKP is written to ‘1’ in software,
releasing SCL
SCL is not held
low because
ACK= 1
PIC16(L)F15356/75/76/85/86
Clock is held low until CKP is set to ‘1’
2016-2018 Microchip Technology Inc.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
FIGURE 32-16:
Master sends
Stop condition
Master Releases SDA
to slave for ACK sequence
Receiving Address
SDA
Receiving Data
ACK D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 A4 A3 A2 A1
Received Data
ACK
ACK=1
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
SSPxIF
If AHEN = 1:
SSPxIF is set
ACKDT
Address is
read from
SSPxBUF
Data is read from SSPxBUF
Slave software
clears ACKDT to
CKP
Slave software
sets ACKDT to
not ACK
ACK the received
byte
When AHEN = 1:
CKP is cleared by hardware
and SCL is stretched
No interrupt
after not ACK
from Slave
Cleared by software
When DHEN = 1:
CKP is cleared by
hardware on 8th falling
edge of SCL
CKP set by software,
SCL is released
ACKTIM
ACKTIM set by hardware
on 8th falling edge of SCL
DS40001866B-page 435
S
P
ACKTIM cleared by
hardware in 9th
rising edge of SCL
ACKTIM set by hardware
on 8th falling edge of SCL
PIC16(L)F15356/75/76/85/86
BF
SSPxIF is set on
9th falling edge of
SCL, after ACK
2016-2018 Microchip Technology Inc.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
FIGURE 32-17:
R/W = 0
Receiving Address
SDA
ACK
A7 A6 A5 A4 A3 A2 A1
SCL
S
1
2 3
4
5
6 7
Master sends
Stop condition
Master releases
SDA to slave for ACK sequence
8
9
Receive Data
1
2 3
4
5
6 7
ACK
Receive Data
D7 D6 D5 D4 D3 D2 D1 D0
8
ACK
9
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3 4
5
6 7
8
9
P
SSPxIF
BF
Received
address is loaded into
SSPxBUF
Received data is
available on SSPxBUF
ACKDT
Slave software clears
ACKDT to ACK
the received byte
SSPxBUF can be
read any time before
next byte is loaded
Slave sends
not ACK
CKP
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
When DHEN = 1;
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
DS40001866B-page 436
S
P
ACKTIM is cleared by hardware
on 9th rising edge of SCL
Set by software,
release SCL
CKP is not cleared
if not ACK
PIC16(L)F15356/75/76/85/86
No interrupt after
if not ACK
from Slave
Cleared by software
PIC16(L)F15356/75/76/85/86
32.5.3
SLAVE TRANSMISSION
32.5.3.2
7-bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPxSTAT register is set. The received address is
loaded into the SSPxBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish a standard transmission. Figure 3218 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 32.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1.
The transmit data must be loaded into the SSPxBUF
register which also loads the SSPxSR register. Then
the SCL pin should be released by setting the CKP bit
of the SSPxCON1 register. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPxBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPxIF bit must be cleared by software and
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse.
32.5.3.1
Slave Mode Bus Collision
A slave receives a read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPxCON3 register is set,
the BCL1IF bit of the PIR3 register is set. Once a bus
collision is detected, the slave goes idle and waits to be
addressed again. User software can use the BCL1IF bit
to handle a slave bus collision.
2016-2018 Microchip Technology Inc.
Master sends a Start condition on SDA and
SCL.
2. S bit of SSPxSTAT is set; SSPxIF is set if
interrupt on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSPxIF bit.
4. Slave hardware generates an ACK and sets
SSPxIF.
5. SSPxIF bit is cleared by software.
6. Software reads the received address from
SSPxBUF, clearing BF.
7. R/W is set so CKP was automatically cleared by
hardware after the ACK.
8. The slave software loads the transmit data into
SSPxBUF.
9. CKP bit is set in software, releasing SCL, allowing the master to clock the data out of the slave.
10. SSPxIF is set after the ACK response from the
master is loaded into the ACKSTAT bit.
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
Note 1:If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
13. Steps 9-13 are repeated for each transmitted
byte.
14. If the master sends a not ACK; the clock is not
held, but SSPxIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
DS40001866B-page 437
2016-2018 Microchip Technology Inc.
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
FIGURE 32-18:
Master sends
Stop condition
Receiving Address
R/W = 1
A7 A6 A5 A4 A3 A2 A1
SDA
SCL
S
1
2
3
4
5
6
7
ACK
8
9
Automatic
Transmitting Data
Automatic
ACK
Transmitting Data
D7 D6 D5 D4 D3 D2 D1 D0 ACK
D7 D6 D5 D4 D3 D2 D1 D0
1
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
P
SSPxIF
Cleared by software
BF
Data to transmit is
loaded into SSPxBUF
BF is automatically
cleared after 8th falling
edge of SCL
CKP
When R/W is set
SCL is always
held low after 9th SCL
falling edge
Set by software
CKP is not
held for not
ACK
ACKSTAT
Masters not ACK
is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
DS40001866B-page 438
Indicates an address
has been received
S
P
PIC16(L)F15356/75/76/85/86
Received address
is read from SSPxBUF
PIC16(L)F15356/75/76/85/86
32.5.3.3
7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 32-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1.
Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
2. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared by hardware and SSPxIF
interrupt is generated.
3. Slave software clears SSPxIF.
4. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
5. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
6. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
7. Slave software sets the CKP bit releasing SCL.
8. Master clocks in the ACK value from the slave.
9. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
10. Slave software clears SSPxIF.
11. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
12. Slave sets the CKP bit releasing the clock.
13. Master clocks out the data from the slave and
sends an ACK value on the ninth SCL pulse.
14. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
15. Steps 10-15 are repeated for each byte transmitted to the master from the slave.
16. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
2016-2018 Microchip Technology Inc.
DS40001866B-page 439
2016-2018 Microchip Technology Inc.
FIGURE 32-19:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
Master sends
Stop condition
Master releases SDA
to slave for ACK sequence
Receiving Address
SDA
SCL
ACK
A7 A6 A5 A4 A3 A2 A1
S
1
2
3
4
5
6
Automatic
R/W = 1
7
8
9
Transmitting Data
Automatic
ACK
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
2
3
4
5
6
7
8
9
Transmitting Data
2
3
4
5
6
7
ACK
8
9
P
SSPxIF
Cleared by software
BF
Data to transmit is
loaded into SSPxBUF
BF is automatically
cleared after 8th falling
edge of SCL
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
Master’s ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
ACKTIM
DS40001866B-page 440
R/W
D/A
ACKTIM is set on 8th falling
edge of SCL
When R/W = 1;
CKP is always
cleared after ACK
Set by software,
releases SCL
ACKTIM is cleared
on 9th rising edge of SCL
CKP not cleared
after not ACK
PIC16(L)F15356/75/76/85/86
Received address
is read from SSPxBUF
PIC16(L)F15356/75/76/85/86
32.5.4
SLAVE MODE 10-BIT ADDRESS
RECEPTION
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in 10bit Addressing mode.
Figure 32-20 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
Slave sends ACK and SSPxIF is set.
Software clears the SSPxIF bit.
Software reads received address from
SSPxBUF clearing the BF flag.
Slave loads low address into SSPxADD,
releasing SCL.
Master sends matching low address byte to the
slave; UA bit is set.
32.5.5
10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPxADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 32-21 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 32-22 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
8.
Slave sends ACK and SSPxIF is set.
Note: If the low address does not match, SSPxIF
and UA are still set so that the slave
software can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
9. Slave clears SSPxIF.
10. Slave reads the received matching address
from SSPxBUF clearing BF.
11. Slave loads high address into SSPxADD.
12. Master clocks a data byte to the slave and
clocks out the slaves ACK on the ninth SCL
pulse; SSPxIF is set.
13. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
14. Slave clears SSPxIF.
15. Slave reads the received byte from SSPxBUF
clearing BF.
16. If SEN is set the slave software sets CKP to
release the SCL.
17. Steps 13-17 repeat for each received byte.
18. Master sends Stop to end the transmission.
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DS40001866B-page 441
2016-2018 Microchip Technology Inc.
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
FIGURE 32-20:
Master sends
Stop condition
Receive Second Address Byte
Receive First Address Byte
SDA
SCL
S
1
1
1
1
0 A9 A8
1
2
3
4
5
6
7
ACK
8
9
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
2
3
4
5
6
7
8
Receive Data
Receive Data
9
D7 D6 D5 D4 D3 D2 D1 D0 ACK
1
2
3
4
5
6
7
8
9
D7 D6 D5 D4 D3 D2 D1 D0 ACK
1
2
3
4
5
6
7
8
9
P
SCL is held low
while CKP = 0
Set by hardware
on 9th falling edge
Cleared by software
BF
Receive address is
read from SSPxBUF
If address matches
SSPxADD it is loaded into
SSPxBUF
Data is read
from SSPxBUF
UA
When UA = 1;
SCL is held low
Software updates SSPxADD
and releases SCL
CKP
DS40001866B-page 442
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
PIC16(L)F15356/75/76/85/86
SSPxIF
2016-2018 Microchip Technology Inc.
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
FIGURE 32-21:
Receive First Address Byte
SDA
SCL
S
Receive Second Address Byte
R/W = 0
1
1
1
1
0
A9
A8
1
2
3
4
5
6
7
ACK
8
9
UA
Receive Data
A7
A6
A5
A4
A3
A2
A1
A0
ACK
1
2
3
4
5
6
7
8
9
UA
Receive Data
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
D0 ACK D7
8
9
1
D6 D5
2
SSPxIF
Set by hardware
on 9th falling edge
Cleared by software
Cleared by software
SSPxBUF can be
read anytime before
the next received byte
Received data
is read from
SSPxBUF
ACKDT
Slave software clears
ACKDT to ACK
the received byte
UA
Update to SSPxADD is
not allowed until 9th
falling edge of SCL
CKP
DS40001866B-page 443
If when AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
Update of SSPxADD,
clears UA and releases
SCL
Set CKP with software
releases SCL
PIC16(L)F15356/75/76/85/86
BF
2016-2018 Microchip Technology Inc.
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
FIGURE 32-22:
Master sends
Restart event
Receiving Address R/W = 0
1 1 1 1 0 A9 A8
SDA
SCL
S
1
2
3
4
5
6
7
ACK
8
9
Receiving Second Address Byte
2
3
4
5
6
7 8
Transmitting Data Byte
Receive First Address Byte
A7 A6 A5 A4 A3 A2 A1 A0 ACK
1
Master sends
not ACK
1 1 1 1 0 A9 A8
1
9
2 3
4
5
6
7 8
ACK
9
Master sends
Stop condition
ACK = 1
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
P
Sr
Set by hardware
Cleared by software
Set by hardware
BF
SSPxBUF loaded
with received address
Received address is
read from SSPxBUF
Data to transmit is
loaded into SSPxBUF
UA
UA indicates SSPxADD
must be updated
CKP
After SSPxADD is
updated, UA is cleared
and SCL is released
High address is loaded
back into SSPxADD
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
ACKSTAT
Set by software
releases SCL
Masters not ACK
is copied
R/W
DS40001866B-page 444
R/W is copied from the
matching address byte
D/A
Indicates an address
has been received
PIC16(L)F15356/75/76/85/86
SSPxIF
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32.5.6
CLOCK STRETCHING
32.5.6.3
Byte NACKing
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more
time to handle data or prepare a response for the
master device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
When AHEN bit of SSPxCON3 is set; CKP is cleared
by hardware after the eighth falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPxCON3 is set; CKP is cleared after the eighth falling edge of SCL for received data.
The CKP bit of the SSPxCON1 register is used to
control stretching. Any time the CKP bit is cleared, the
module will wait for the SCL line to go low and then
hold it. Setting CKP will release SCL and allow more
communication.
32.5.7
32.5.6.1
Normal Clock Stretching
Following an ACK if the R/W bit of SSPxSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
32.5.6.2
Stretching after the eighth falling edge of SCL allows
the slave to look at the received address or data and
decide if it wants to ACK the received data.
CLOCK SYNCHRONIZATION AND THE
CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 32-23).
10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPxADD.
FIGURE 32-23:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX ‚ – 1
DX
SCL
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPxCON1
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32.5.8
GENERAL CALL ADDRESS SUPPORT
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually determines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
If the AHEN bit of the SSPxCON3 register is set, just
as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge
of SCL. The slave must then set its ACKDT value and
release the clock with communication progressing as it
would normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPxBUF and respond. Figure 3224 shows a general call reception sequence.
FIGURE 32-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
SCL
S
1
2
3
4
5
6
7
8
9
1
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
SSPxIF
BF (SSPxSTAT)
Cleared by software
GCEN (SSPxCON2)
SSPxBUF is read
’1’
32.5.9
SSP MASK REGISTER
An SSP Mask (SSPxMSK) register (Register 32-5) is
available in I2C Slave mode as a mask for the value
held in the SSPxSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
2016-2018 Microchip Technology Inc.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A.
• 10-bit Address mode: address compare of A
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
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32.6
I2C Master Mode
32.6.1
I2C MASTER MODE OPERATION
Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPxCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I 2C bus may be taken when the P bit is
set, or the bus is Idle.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
and the end of a serial transfer.
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
The following events will cause the SSP Interrupt Flag
bit, SSPxIF, to be set (SSP interrupt, if enabled):
•
•
•
•
•
Start condition generated
Stop condition generated
Data transfer byte transmitted/received
Acknowledge transmitted/received
Repeated Start generated
Note 1:The MSSP module, when configured in I2C
Master mode, does not allow queuing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 32.7 “Baud
Rate Generator” for more detail.
2: When in Master mode, Start/Stop
detection is masked and an interrupt is
generated when the SEN/PEN bit is
cleared and the generation is complete.
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32.6.2
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate
Generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD and begins counting. This ensures that the SCL high time will always be
at least one BRG rollover count in the event that the
clock is held low by an external device (Figure 32-25).
FIGURE 32-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX ‚ – 1
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
32.6.3
WCOL STATUS FLAG
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not idle.
Note:
Because queuing of events is not allowed,
writing to the lower five bits of SSPxCON2
is disabled until the Start condition is
complete.
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32.6.4
I2C MASTER MODE START
by hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
CONDITION TIMING
To initiate a Start condition (Figure 32-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2
register. If the SDA and SCL pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSPxADD and starts its count. If SCL and
SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The
action of the SDA being driven low while SCL is high is
the Start condition and causes the S bit of the
SSPxSTAT1 register to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPxADD and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
FIGURE 32-26:
Note 1:If at the beginning of the Start condition, the
SDA and SCL pins are already sampled
low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
2: The Philips I2C specification states that a
bus collision cannot occur on a Start.
FIRST START BIT TIMING
Write to SEN bit occurs here
Set S bit (SSPxSTAT)
At completion of Start bit,
hardware clears SEN bit
and sets SSPxIF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPxBUF occurs here
SDA
1st bit
2nd bit
TBRG
SCL
S
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TBRG
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32.6.5
I2C MASTER MODE REPEATED
cally cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit of the SSPxSTAT register will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
START CONDITION TIMING
A Repeated Start condition (Figure 32-27) occurs when
the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the
Baud Rate Generator is loaded and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
and begins counting. SDA and SCL must be sampled
high for one TBRG. This action is then followed by
assertion of the SDA pin (SDA = 0) for one TBRG while
SCL is high. SCL is asserted low. Following this, the
RSEN bit of the SSPxCON2 register will be automati-
FIGURE 32-27:
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
•SDA is sampled low when SCL goes
from low-to-high.
•SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data ‘1’.
REPEATED START CONDITION WAVEFORM
S bit set by hardware
Write to SSPxCON2
occurs here
SDA = 1,
SCL (no change)
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPxBUF occurs here
TBRG
SCL
Sr
TBRG
Repeated Start
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32.6.6
I2C MASTER MODE TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPxBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPxIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPxBUF, leaving SCL low and SDA
unchanged (Figure 32-28).
After the write to the SSPxBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPxCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPxIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPxBUF takes place,
holding SCL low and allowing SDA to float.
32.6.6.1
BF Status Flag
32.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPxCON2
register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
32.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Typical transmit sequence:
The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
SSPxIF is set by hardware on completion of the
Start.
SSPxIF is cleared by software.
The MSSP module will wait the required start
time before any other operation takes place.
The user loads the SSPxBUF with the slave
address to transmit.
Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The user loads the SSPxBUF with eight bits of
data.
Data is shifted out the SDA pin until all eight bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
Steps 8-11 are repeated for all transmitted data
bytes.
The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the
Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all eight bits are shifted out.
32.6.6.2
WCOL Status Flag
If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
2016-2018 Microchip Technology Inc.
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2016-2018 Microchip Technology Inc.
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
FIGURE 32-28:
Write SSPxCON2 SEN = 1
Start condition begins
From slave, clear ACKSTAT bit SSPxCON2
SEN = 0
Transmit Address to Slave
A7
SDA
A6
A5
A4
ACKSTAT in
SSPxCON2 = 1
A3
A2
Transmitting Data or Second Half
of 10-bit Address
R/W = 0
A1
ACK = 0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
1
SCL held low
while CPU
responds to SSPxIF
2
3
4
5
6
7
8
SSPxBUF written with 7-bit address and R/W
start transmit
SCL
S
1
2
3
4
5
6
7
8
9
9
P
Cleared by software
Cleared by software service routine
from SSP interrupt
BF (SSPxSTAT)
SSPxBUF written
SEN
After Start condition, SEN cleared by hardware
PEN
DS40001866B-page 452
R/W
SSPxBUF is written by software
Cleared by software
PIC16(L)F15356/75/76/85/86
SSPxIF
PIC16(L)F15356/75/76/85/86
32.6.7
I2C MASTER MODE RECEPTION
Master mode reception (Figure 32-29) is enabled by
programming the Receive Enable bit, RCEN bit of the
SSPxCON2 register.
Note:
The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPxSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPxSR are loaded into the SSPxBUF, the BF flag bit
is set, the SSPxIF flag bit is set and the Baud Rate
Generator is suspended from counting, holding SCL
low. The MSSP is now in Idle state awaiting the next
command. When the buffer is read by the CPU, the BF
flag bit is automatically cleared. The user can then
send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of
the SSPxCON2 register.
32.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It
is cleared when the SSPxBUF register is read.
32.6.7.2
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPxSR and the BF flag bit is
already set from a previous reception.
32.6.7.3
32.6.7.4
WCOL Status Flag
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
2016-2018 Microchip Technology Inc.
12.
13.
14.
15.
Typical Receive Sequence:
The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
SSPxIF is set by hardware on completion of the
Start.
SSPxIF is cleared by software.
User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
User sets the RCEN bit of the SSPxCON2
register and the master clocks in a byte from the
slave.
After the eighth falling edge of SCL, SSPxIF and
BF are set.
Master clears SSPxIF and reads the received
byte from SSPxBUF, clears BF.
Master sets ACK value sent to slave in ACKDT
bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
Master’s ACK is clocked out to the slave and
SSPxIF is set.
User clears SSPxIF.
Steps 8-13 are repeated for each received byte
from the slave.
Master sends a not ACK or Stop to end
communication.
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I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
FIGURE 32-29:
Write to SSPxCON2
to start Ackno1wledge sequence
SDA = ACKDT (SSPxCON2) = 0
Write to SSPxCON2(SEN = 1),
begin Start condition
Transmit Address to Slave
A7
SDA
A6 A5 A4 A3 A2
RCEN = 1, start
next receive
ACK
PEN bit = 1
written here
RCEN cleared
automatically
Receiving Data from Slave
Receiving Data from Slave
A1 R/W
Set ACKEN, start Acknowledge sequence
SDA = ACKDT = 1
ACK from Master
SDA = ACKDT = 0
Master configured as a receiver
by programming SSPxCON2 (RCEN = 1)
SEN = 0
Write to SSPxBUF occurs here,
RCEN cleared
ACK from Slave
automatically
start XMIT
D7 D6 D5 D4 D3 D2 D1
ACK
D0
D7 D6 D5 D4 D3 D2 D1
D0
ACK
Bus master
terminates
transfer
ACK is not sent
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
Set SSPxIF interrupt
at end of receive
Set SSPxIF interrupt
at end of Acknowledge
sequence
SSPxIF
SDA = 0, SCL = 1
while CPU
responds to SSPxIF
Cleared by software
Cleared by software
Cleared by software
BF
(SSPxSTAT)
P
Set SSPxIF at end
of receive
Cleared by software
Cleared in
software
Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
SSPOV is set because
SSPxBUF is still full
ACKEN
DS40001866B-page 454
RCEN
Master configured as a receiver
by programming SSPxCON2 (RCEN = 1)
RCEN cleared
automatically
ACK from Master
SDA = ACKDT = 0
RCEN cleared
automatically
Set SSPxIF interrupt
at end of Acknowledge sequence
Set P bit
(SSPxSTAT)
and SSPxIF
PIC16(L)F15356/75/76/85/86
Data shifted in on falling edge of CLK
9
8
PIC16(L)F15356/75/76/85/86
32.6.8
ACKNOWLEDGE SEQUENCE
TIMING
32.6.9
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPxCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPxSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 32-31).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPxCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(TBRG) and the SCL pin is deasserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the Baud Rate Generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into IDLE mode
(Figure 32-30).
32.6.8.1
32.6.9.1
WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 32-30:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPxCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
TBRG
SDA
ACK
D0
SCL
8
9
SSPxIF
SSPxIF set at
the end of receive
Cleared in
software
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 32-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPxSTAT) is set.
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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32.6.10
SLEEP OPERATION
32.6.13
2
While in Sleep mode, the I C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
32.6.11
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
32.6.12
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit of the SSPxSTAT register is
set, or the bus is Idle, with both the S and P bits clear.
When the bus is busy, enabling the SSP interrupt will
generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCL1IF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCL1IF and reset the
I2C port to its Idle state (Figure 32-32).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPxCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
if the I2C bus is free, the user can resume
communication by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 32-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high,
data does not match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt (BCL1IF)
BCL1IF
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32.6.13.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
b)
SDA or SCL are sampled low at the beginning of
the Start condition (Figure 32-33).
SCL is sampled low before SDA is asserted low
(Figure 32-34).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 32-35). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCL1IF flag is set and
• the MSSP module is reset to its Idle state
(Figure 32-33).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 32-33:
The reason that bus collision is not a
factor during a Start condition is that no
two bus masters can assert a Start condition at the exact same time. Therefore,
one master will always assert SDA before
the other. This condition does not cause a
bus collision because the two masters
must be allowed to arbitrate the first
address following the Start condition. If the
address is the same, arbitration must be
allowed to continue into the data portion,
Repeated Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCL1IF,
S bit and SSPxIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SEN
BCL1IF
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSPxIF set because
SDA = 0, SCL = 1.
SSPxIF and BCL1IF are
cleared by software
S
SSPxIF
SSPxIF and BCL1IF are
cleared by software
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FIGURE 32-34:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,
bus collision occurs. Set BCL1IF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCL1IF.
BCL1IF
Interrupt cleared
by software
’0’
’0’
SSPxIF ’0’
’0’
S
FIGURE 32-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
Set SSPxIF
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG
time-out
SEN
BCL1IF
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
’0’
S
SSPxIF
SDA = 0, SCL = 1,
set SSPxIF
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Interrupts cleared
by software
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32.6.13.2
Bus Collision During a Repeated
Start Condition
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 32-37.
A low level is sampled on SDA when SCL goes
from low level to high level (Case 1).
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’ (Case 2).
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCL pin is then deasserted
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 32-36).
If SDA is sampled high, the BRG is reloaded and begins
FIGURE 32-36:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCL1IF and release SDA and SCL.
RSEN
BCL1IF
Cleared by software
S
’0’
SSPxIF
’0’
FIGURE 32-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCL1IF
SCL goes low before SDA,
set BCL1IF. Release SDA and SCL.
Interrupt cleared
by software
RSEN
S
’0’
SSPxIF
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32.6.13.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPxADD and
counts down to zero. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 32-38). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 32-39).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out (Case 1).
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high (Case 2).
FIGURE 32-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA
SDA sampled
low after TBRG,
set BCL1IF
SDA asserted low
SCL
PEN
BCL1IF
P
’0’
SSPxIF
’0’
FIGURE 32-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL
SCL goes low before SDA goes high,
set BCL1IF
PEN
BCL1IF
P
’0’
SSPxIF
’0’
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32.7
BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPxADD register (Register 32-6).
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSP is
being operated in.
Table 32-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
EQUATION 32-1:
FOSC
FCLOCK = ------------------------------------------------- SSP1ADD + 1 4
An internal signal “Reload” in Figure 32-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 32-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM
SSPM
Reload
SCL
Control
SSPCLK
SSPxADD
Reload
BRG Down Counter
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not
valid for SSPxADD when used as a Baud
Rate Generator for I2C. This is an
implementation limitation.
TABLE 32-2:
Note:
MSSP CLOCK RATE W/BRG
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
32 MHz
8 MHz
13h
400 kHz
32 MHz
8 MHz
19h
308 kHz
32 MHz
8 MHz
4Fh
100 kHz
16 MHz
4 MHz
09h
400 kHz
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Refer to the I/O port electrical specifications in Table 37-4 to ensure the system is designed to support IOL
requirements.
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32.8
Register Definitions: MSSPx Control
REGISTER 32-1:
SSPxSTAT: SSPx STATUS REGISTER
R/W-0/0
R/W-0/0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
R/HS/HC-0
SMP
CKE(1)
D/A
P(2)
S(2)
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS/HC = Hardware set/clear
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)(1)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit(2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit (2)
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the
next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1
UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty
Note
1:
2:
Polarity of clock state is set by the CKP bit of the SSPxCON register.
This bit is cleared on Reset and when SSPEN is cleared.
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REGISTER 32-2:
SSPxCON1: SSPx CONTROL REGISTER 1
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV(1)
SSPEN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Bit is set by hardware
C = User cleared
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, the following pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3-0
SSPM: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = T2_match/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
When enabled, these pins must be properly configured as input or output. Use SSPxSSPPS, SSPxCLKPPS, SSPxDATPPS, and
RxyPPS to select the pins.
When enabled, the SDA and SCL pins must be configured as inputs. Use SSPxCLKPPS, SSPxDATPPS, and RxyPPS to select the pins.
SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead.
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REGISTER 32-3:
SSPxCON2: SSPx CONTROL REGISTER 2 (I2C MODE ONLY)(1)
R/W-0/0
R/HS/HC-0
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
R/S/HC-0/0
R/S/HC-0/0
R/S/HC-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
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REGISTER 32-4:
SSPxCON3: SSPx CONTROL REGISTER 3
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM(3)
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1
register is set, and the buffer is not updated
In I2 C Master mode and SPI Master mode:
This bit is ignored.
In I2 C Slave mode:
1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the
SSPOV bit only if the BF bit = 0.
0 = SSPxBUF is only updated when SSPOV is clear
bit 3
SDAHT: SDA Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the
PIR3 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPxCON1
register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0
DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the
SSPxCON1 register and SCL is held low.
0 = Data holding is disabled
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new
byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
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REGISTER 32-5:
R/W-1/1
SSPxMSK: SSPx MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
SSPxMSK
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
SSPxMSK: Mask bits
1 = The received address bit n is compared to SSPxADD to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0
SSPxMSK: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM = 0111 or 1111):
1 = The received address bit 0 is compared to SSPxADD to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address:
MSK0 bit is ignored.
REGISTER 32-6:
R/W-0/0
SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPxADD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
Master mode:
bit 7-0
SSPxADD: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD + 1) *4)/FOSC
10-Bit Slave mode – Most Significant Address Byte:
bit 7-3
Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit
pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1
SSPxADD: Two Most Significant bits of 10-bit address
bit 0
Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode – Least Significant Address Byte:
bit 7-0
SSPxADD: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1
SSPxADD: 7-bit address
bit 0
Not used: Unused in this mode. Bit state is a “don’t care”.
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REGISTER 32-7:
R/W-x
SSPxBUF: MSSPx BUFFER REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SSPxBUF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
SSPxBUF: MSSP Buffer bits
TABLE 32-3:
Name
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH MSSPx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
—
—
—
—
—
INTEDG
147
PIR3
RC2IF
TX2IF
RC1IF
TX1IF
BCL2IF
SSP2IF
BCL1IF
SSP1IF
141
PIE3
RC2IE
TX2IE
RC1IE
TX1IE
BCL2IE
SSP2IE
BCL1IE
SSP1IE
133
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
462
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
464
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
462
SSPM
463
SSP1MSK
SSPMSK
466
SSP1ADD
SSPADD
466
SSP1BUF
467
SSPBUF
SSP2STAT
SMP
SSP2CON1
SSP2CON2
SSP2CON3
P
S
R/W
ACKEN
RCEN
PEN
RSEN
SEN
464
BOEN
SDAHT
SBCDE
AHEN
DHEN
462
CKE
D/A
WCOL
SSPOV
SSPEN
CKP
GCEN
ACKSTAT
ACKDT
ACKTIM
PCIE
SCIE
UA
BF
SSPM
462
463
SSP2MSK
SSPMSK
466
SSP2ADD
SSPADD
466
SSPBUF
467
SSP2BUF
SSP1CLKPPS
—
—
SSP1CLKPPS
242
SSP1DATPPS
—
—
SSP1DATPPS
242
SSP1SSPPS
—
—
SSP1SSPPS
242
SSP2CLKPPS
—
—
SSP2CLKPPS
242
SSP2DATPPS
—
—
SSP2DATPPS
242
SSP2SSPPS
—
—
SSP2SSPPS
242
RxyPPS
—
—
Legend:
Note 1:
RxyPPS
243
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx module
When using designated I2C pins, the associated pin values in INLVLx will be ignored.
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33.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The EUSART module includes the following capabilities:
•
•
•
•
•
•
•
•
•
•
Full-duplex asynchronous transmit and receive
Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Programmable clock polarity in synchronous
modes
• Sleep operation
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
Note:
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 33-1 and Figure 33-2.
Two identical EUSART modules are
implemented on this device, EUSART1
and EUSART2. All references to
EUSART1 apply to EUSART2 as well.
FIGURE 33-1:
The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
SYNC
CSRC
8
TXEN
LSb
(8)
0
0
• • •
TRMT
TX9
n
Multiplier
TX_out
÷n
BRG16
SPxBRGH SPxBRGL
RX/DT pin
PPS
SYNC
FOSC
+1
Pin Buffer
and Control
Transmit Shift Register (TSR)
CKPPS
Note 1:
RxyPPS(1)
MSb
1
Baud Rate Generator
Interrupt
TXxIF
TXxREG Register
CK pin
PPS
TXxIE
x4
x16 x64
SYNC
1 X 0 0
0
BRGH
X 1 1 0
0
BRG16
X 1 0 1
0
TX9D
In Synchronous mode the DT output and RX input PPS
selections should enable the same pin.
2016-2018 Microchip Technology Inc.
0
TX/CK pin
PPS
1
RxyPPS
SYNC
CSRC
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FIGURE 33-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
RX/DT pin
CREN
OERR
RXPPS(1)
RSR Register
MSb
PPS
Pin Buffer
and Control
Baud Rate Generator
Data
Recovery
FOSC
BRG16
+1
SPxBRGH SPxBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
0
BRGH
X 1 1 0
0
BRG16
X 1 0 1
0
Stop
(8)
•••
7
1
LSb
0 Start
RX9
÷n
n
FERR
RX9D
RCxREG Register
8
Note 1:
RCIDL
In Synchronous mode the DT output and RX input PPS
selections should enable the same pin.
FIFO
Data Bus
RXxIF
RXxIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 33-1,
Register 33-2 and Register 33-3, respectively.
The RX input pin is selected with the RXxPPS. The CK
input is selected with the TXxPPS register. TX, CK, and
DT output pins are selected with each pin’s RxyPPS
register. Since the RX input is coupled with the DT output
in Synchronous mode, it is the user’s responsibility to
select the same pin for both of these functions when
operating in Synchronous mode. The EUSART control
logic will control the data direction drivers automatically.
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33.1
EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH Mark state which
represents a ‘1’ data bit, and a VOL Space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the Mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is eight bits. Each transmitted bit persists for a
period of 1/(Baud Rate). An on-chip dedicated 8-bit/16bit Baud Rate Generator is used to derive standard
baud rate frequencies from the system oscillator. See
Table 33-3 for examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
33.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 33-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXxREG register.
33.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXxSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART and
automatically configures the TX/CK I/O pin as an output.
If the TX/CK pin is shared with an analog peripheral, the
analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
Note:
33.1.1.2
Transmitting Data
A transmission is initiated by writing a character to the
TXxREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXxREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXxREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXxREG.
33.1.1.3
Transmit Data Polarity
The polarity of the transmit data can be controlled with
the SCKP bit of the BAUDxCON register. The default
state of this bit is ‘0’ which selects high true transmit idle
and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true idle and data bits. The
SCKP bit controls transmit data polarity in
Asynchronous mode only. In Synchronous mode, the
SCKP bit has a different function. See Section 33.4.1.2
“Clock Polarity”.
33.1.1.4
Transmit Interrupt Flag
The TXxIF interrupt flag bit of the PIR3 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXxREG.
In other words, the TXxIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXxREG. The TXxIF flag
bit is not cleared immediately upon writing TXxREG.
TXxIF becomes valid in the second instruction cycle
following the write execution. Polling TXxIF immediately
following the TXxREG write will return invalid results.
The TXxIF bit is read-only, it cannot be set or cleared by
software.
The TXxIF interrupt can be enabled by setting the
TXxIE interrupt enable bit of the PIE3 register. However, the TXxIF flag bit will be set whenever the
TXxREG is empty, regardless of the state of TXxIE
enable bit.
To use interrupts when transmitting data, set the TXxIE
bit only when there is more data to send. Clear the
TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG.
The TXxIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
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33.1.1.5
TSR Status
33.1.1.7
The TRMT bit of the TXxSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXxREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
Note:
33.1.1.6
1.
2.
3.
The TSR register is not mapped in data
memory, so it is not available to the user.
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXxSTA register is set, the
EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the
ninth, and Most Significant data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXxREG.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXxREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 33.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 33-3:
Write to TXxREG
BRG Output
(Shift Clock)
TX/CK
pin
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
4.
5.
6.
7.
8.
Asynchronous Transmission Set-up:
Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.3 “EUSART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the eight Least Significant data bits are an
address when the receiver is set for address
detection.
Set SCKP bit if inverted transmit is desired.
Enable the transmission by setting the TXEN
control bit. This will cause the TXxIF interrupt bit
to be set.
If interrupts are desired, set the TXxIE interrupt
enable bit of the PIE3 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXxREG register. This
will start the transmission.
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
Word 1
Transmit Shift Reg.
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FIGURE 33-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXxREG
BRG Output
(Shift Clock)
Word 1
TX/CK
pin
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
33.1.2
Word 2
Start bit
bit 0
1 TCY
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 33-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character First-InFirst-Out (FIFO) memory. The FIFO buffering allows
reception of two complete characters and the start of a
third character before software must start servicing the
EUSART receiver. The FIFO and RSR registers are not
directly accessible by software. Access to the received
data is via the RCxREG register.
33.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCxSTA register enables
the receiver circuitry of the EUSART. Clearing the SYNC
bit of the TXxSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART. The
programmer must set the corresponding TRIS bit to
configure the RX/DT I/O pin as an input.
Note:
bit 1
Word 1
33.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 33.1.2.4 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RXxIF interrupt
flag bit of the PIR3 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCxREG register.
Note:
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 33.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
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33.1.2.3
Receive Interrupts
The RXxIF interrupt flag bit of the PIR3 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RXxIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RXxIF interrupts are enabled by setting all of the
following bits:
• RXxIE, Interrupt Enable bit of the PIE3 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RXxIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
33.1.2.4
Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCxSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCxREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
33.1.2.6
Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCxSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCxREG.
33.1.2.7
Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCxSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RXxIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCxSTA register which resets the EUSART.
Clearing the CREN bit of the RCxSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
33.1.2.5
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCxREG will not clear the FERR bit.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCxSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCxSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCxSTA register.
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33.1.2.8
Asynchronous Reception Setup:
33.1.2.9
1.
Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.3 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RXxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
7. The RXxIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RXxIE interrupt enable bit was also set.
8. Read the RCxSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCxREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
FIGURE 33-5:
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.3 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RXxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
7. Enable reception by setting the CREN bit.
8. The RXxIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RXxIE interrupt enable
bit was also set.
9. Read the RCxSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
9-bit Address Detection Mode Setup
bit 1
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
bit 7/8 Stop
bit
Start
bit
Word 1
RCxREG
bit 0
bit 7/8 Stop
bit
Start
bit
bit 7/8
Stop
bit
Word 2
RCxREG
Read Rcv
Buffer Reg.
RCxREG
RXxIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
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33.2
Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (INTOSC). However, the HFINTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate. Two
methods may be used to adjust the baud rate clock, but
both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
Section 9.2.2.2 “Internal Oscillator Frequency
Adjustment” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 33.3.1 “AutoBaud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
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33.3
EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDxCON register selects 16-bit
mode.
The SPxBRGH, SPxBRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the
TXxSTA register and the BRG16 bit of the BAUDxCON
register. In Synchronous mode, the BRGH bit is ignored.
Table 33-1 contains the formulas for determining the
baud rate. Example 33-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
Asynchronous modes have been computed for your
convenience and are shown in Table 33-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
EXAMPLE 33-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
F OS C
Desired Baud Rate = ----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1
Solving for SPxBRGH:SPxBRGL:
F O SC
-------------------------------------------Desired
Baud Rate – 1
X = --------------------------------------------64
16000000
-----------------------9600 - – 1
= ----------------------64
= 25.042 = 25
16000000Calculated Baud Rate = -------------------------64 25 + 1
= 9615
Baud Rate – Desired Baud RateError = Calc.
------------------------------------------------------------------------------------------Desired Baud Rate
9615 – 9600 = 0.16%
= ---------------------------------9600
Writing a new value to the SPxBRGH, SPxBRGL
register pair causes the BRG timer to be reset (or
cleared). This ensures that the BRG does not wait for a
timer overflow before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.
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33.3.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDxCON register
starts the auto-baud calibration sequence. While the
ABD sequence takes place, the EUSART state
machine is held in Idle. On the first rising edge of the
receive line, after the Start bit, the SPxBRG begins
counting up using the BRG counter clock as shown in
Figure 33-6. The fifth rising edge will occur on the RX
pin at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPxBRGH, SPxBRGL register pair, the
ABDEN bit is automatically cleared and the RXxIF
interrupt flag is set. The value in the RCxREG needs to
be read to clear the RXxIF interrupt. RCxREG content
should be discarded. When calibrating for modes that
do not use the SPxBRGH register the user can verify
that the SPxBRGL register did not overflow by
checking for 00h in the SPxBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 33-1. During ABD,
both the SPxBRGH and SPxBRGL registers are used
as a 16-bit counter, independent of the BRG16 bit
setting. While calibrating the baud rate period, the
SPxBRGH and SPxBRGL registers are clocked at 1/
FIGURE 33-6:
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 33.3.3
“Auto-Wake-up
on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the autobaud counter starts counting at one. Upon
completion of the auto-baud sequence, to
achieve maximum accuracy, subtract 1
from the SPxBRGH:SPxBRGL register
pair.
TABLE 33-1:
BRG COUNTER CLOCK RATES
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
0
0
FOSC/64
FOSC/512
0
1
FOSC/16
FOSC/128
1
0
FOSC/16
FOSC/128
1
1
FOSC/4
FOSC/32
Note:
During the ABD sequence, SPxBRGL and
SPxBRGH registers are both used as a 16bit counter, independent of the BRG16
setting.
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
BRG Value
8th the BRG base clock rate. The resulting byte
measurement is the average bit time when clocked at
full speed.
0000h
RX pin
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RXxIF bit
(Interrupt)
Read
RCxREG
SPxBRGL
XXh
1Ch
SPxBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
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33.3.2
AUTO-BAUD OVERFLOW
33.3.3.1
Special Considerations
During the course of automatic baud detection, the
ABDOVF bit of the BAUDxCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPxBRGH:SPxBRGL
register pair. The overflow condition will set the RXxIF
flag. The counter continues to count until the fifth rising
edge is detected on the RX pin. The RCIDL bit will
remain false (‘0’) until the fifth rising edge at which time
the RCIDL bit will be set. If the RCxREG is read after
the overflow occurs but before the fifth rising edge then
the fifth rising edge will set the RXxIF again.
Break Character
Terminating the auto-baud process early to clear an
overflow condition will prevent proper detection of the
sync character fifth rising edge. If any falling edges of
the sync character have not yet occurred when the
ABDEN bit is cleared then those will be falsely detected
as Start bits. The following steps are recommended to
clear the overflow condition:
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
1.
2.
3.
Read RCxREG to clear RXxIF.
If RCIDL is ‘0’ then wait for RDCIF and repeat
step 1.
Clear the ABDOVF bit.
33.3.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDxCON register. Once set, the
normal receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a wakeup event independent of the CPU mode. A wake-up
event consists of a high-to-low transition on the RX/DT
line. (This coincides with the start of a Sync Break or a
wake-up signal character for the LIN protocol.)
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RXxIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCxREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RXxIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 33-7), and asynchronously if
the device is in Sleep mode (Figure 33-8). The interrupt
condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in IDLE mode waiting to
receive the next character.
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FIGURE 33-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RX/DT Line
RXxIF
Note 1:
Cleared due to User Read of RCxREG
The EUSART remains in Idle while the WUE bit is set.
FIGURE 33-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Bit Set by User
WUE bit
RX/DT Line
Note 1
RXxIF
Sleep Command Executed
Note 1:
2:
33.3.4
Cleared due to User Read of RCxREG
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
BREAK CHARACTER SEQUENCE
33.3.4.1
Break and Sync Transmit Sequence
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
To send a Break character, set the SENDB and TXEN
bits of the TXxSTA register. The Break character
transmission is then initiated by a write to the TXxREG.
The value of data written to TXxREG will be ignored
and all ‘0’s will be transmitted.
1.
2.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
4.
The TRMT bit of the TXxSTA register indicates when the
transmit operation is active or idle, just as it does during
normal transmission. See Figure 33-9 for the timing of
the Break character sequence.
When the TXxREG becomes empty, as indicated by
the TXxIF, the next data byte can be written to TXxREG.
2016-2018 Microchip Technology Inc.
3.
5.
Configure the EUSART for the desired mode.
Set the TXEN and SENDB bits to enable the
Break sequence.
Load the TXxREG with a dummy character to
initiate transmission (the value is ignored).
Write ‘55h’ to TXxREG to load the Sync
character into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
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33.3.5
RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCxSTA register and the received data
as indicated by RCxREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when:
• RXxIF bit is set
• FERR bit is set
• RCxREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 33.3.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RXxIF interrupt, and receive the next data byte followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDxCON register before placing the EUSART in
Sleep mode.
FIGURE 33-9:
Write to TXxREG
SEND BREAK CHARACTER SEQUENCE
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXxIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
2016-2018 Microchip Technology Inc.
SENDB Sampled Here
Auto Cleared
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33.4
EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
33.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for synchronous master operation:
•
•
•
•
•
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXxSTA register configures the device as a
master. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured
to receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART.
33.4.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the
trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are
generated as there are data bits.
2016-2018 Microchip Technology Inc.
33.4.1.2
Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDxCON register. Setting the SCKP bit
sets the clock Idle state as high. When the SCKP bit is
set, the data changes on the falling edge of each clock.
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
33.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXxREG register. If the TSR still contains all or part of
a previous character the new character data is held in
the TXxREG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXxREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
33.4.1.4
Synchronous Master Transmission
Set-up:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize the SPxBRGH, SPxBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 33.3 “EUSART
Baud Rate Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Disable Receive mode by clearing bits SREN
and CREN.
Enable Transmit mode by setting the TXEN bit.
If 9-bit transmission is desired, set the TX9 bit.
If interrupts are desired, set the TXxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
Start transmission by loading data to the
TXxREG register.
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FIGURE 33-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXxREG Reg
Write Word 1
Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
‘1’
‘1’
Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 33-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
TX/CK pin
Write to
TXxREG reg
TXxIF bit
TRMT bit
TXEN bit
33.4.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCxSTA register) or the Continuous Receive Enable
bit (CREN of the RCxSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
2016-2018 Microchip Technology Inc.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RXxIF bit is set and the
character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of
the top character in the receive FIFO are available in
RCxREG. The RXxIF bit remains set as long as there
are unread characters in the receive FIFO.
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
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33.4.1.6
Slave Clock
received. The RX9D bit of the RCxSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCxREG.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The TX/
CK pin output driver is automatically disabled when the
device is configured for synchronous slave transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One data bit is transferred for each clock cycle.
Only as many clock cycles should be received as there
are data bits.
Note:
33.4.1.7
33.4.1.9
1.
Initialize the SPxBRGH, SPxBRGL register pair
for the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
5. If interrupts are desired, set the RXxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
6. If 9-bit reception is desired, set bit RX9.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit RXxIF will be set when reception of a character is complete. An interrupt will
be generated if the enable bit RXxIE was set.
9. Read the RCxSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCxREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be cleared.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCxREG is read to access
the FIFO. When this happens the OERR bit of the
RCxSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCxREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCxSTA register or by clearing the
SPEN bit which resets the EUSART.
33.4.1.8
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCxSTA register is set the EUSART
will shift nine bits into the RSR for each character
FIGURE 33-12:
RX/DT
pin
Synchronous Master Reception Setup:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’
‘0’
RXxIF bit
(Interrupt)
Read
RCxREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
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33.4.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for synchronous slave operation:
•
•
•
•
•
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXxSTA register configures
the device for synchronous operation. Clearing the
CSRC bit of the TXxSTA register configures the device as
a slave. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured to
receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART.
33.4.2.1
The operation of the Synchronous Master and Slave
modes
are
identical
(see
Section 33.4.1.3
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
If two words are written to the TXxREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in the TXxREG
register.
The TXxIF bit will not be set.
After the first character has been shifted out of
TSR, the TXxREG register will transfer the
second character to the TSR and the TXxIF bit
will now be set.
If the PEIE and TXxIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
33.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
2016-2018 Microchip Technology Inc.
EUSART Synchronous Slave
Transmit
Synchronous Slave Transmission
Set-up:
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for the CK pin (if applicable).
Clear the CREN and SREN bits.
If interrupts are desired, set the TXxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start transmission by writing the Least
Significant eight bits to the TXxREG register.
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33.4.2.3
EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 33.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCxREG register. If the RXxIE enable bit is set,
the interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
33.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
2016-2018 Microchip Technology Inc.
Synchronous Slave Reception Setup:
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RXxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RXxIF bit will be set when reception is
complete. An interrupt will be generated if the
RXxIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCxSTA
register.
Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCxREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
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33.5
EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
33.5.1
SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCxSTA and TXxSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 33.4.2.4 “Synchronous Slave
Reception Set-up:”).
• If interrupts are desired, set the RXxIE bit of the
PIE3 register and the GIE and PEIE bits of the
INTCON register.
• The RXxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RXxIF interrupt
flag bit of the PIR3 register will be set. Thereby, waking
the processor from Sleep.
33.5.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• The RCxSTA and TXxSTA Control registers must
be configured for synchronous slave transmission
(see Section 33.4.2.2 “Synchronous Slave
Transmission Set-up:”).
• The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling
the TSR and transmit buffer.
• If interrupts are desired, set the TXxIE bit of the
PIE3 register and the PEIE bit of the INTCON
register.
• Interrupt enable bits TXxIE of the PIE3 register
and PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXxREG will transfer to the TSR
and the TXxIF flag will be set. Thereby, waking the
processor from Sleep. At this point, the TXxREG is
available to accept another character for transmission,
which will clear the TXxIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit of the INTCON register is
also set, then the Interrupt Service Routine at address
004h will be called.
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33.6
Register Definitions: EUSART Control
REGISTER 33-1:
R/W-/0
CSRC
TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send SYNCH BREAK on next transmission – Start bit, followed by 12 ‘0’ bits, followed by Stop
bit; cleared by hardware upon completion
0 = SYNCH BREAK transmission disabled or completed
Synchronous mode:
Unused in this mode – value ignored
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode – value ignored
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1:
SREN/CREN overrides TXEN in Sync mode.
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REGISTER 33-2:
RCxSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
SPEN(1)
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SPEN: Serial Port Enable bit(1)
1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6
RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Unused in this mode – value ignored
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in
the receive buffer is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Unused in this mode – value ignored
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCxREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Note 1:
The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the
associated TRIS bits for TX/CK and RX/DT to 1.
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REGISTER 33-3:
BAUDxCON: BAUD RATE CONTROL REGISTER
R/W-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5
Unimplemented: Read as ‘0’
bit 4
SCKP: Clock/Transmit Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TX) is a low level
0 = Idle state for transmit (TX) is a high level
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3
BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2
Unimplemented: Read as ‘0’
bit 1
WUE: Wake-up Enable bit
Asynchronous mode:
1 = USART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge.
0 = RX pin not monitored nor rising edge detected
Synchronous mode:
Unused in this mode – value ignored
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character – requires reception of a SYNCH field
(55h);
cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode – value ignored
2016-2018 Microchip Technology Inc.
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RCxREG(1): RECEIVE DATA REGISTER
REGISTER 33-4:
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RCxREG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
RCxREG: Lower eight bits of the received data; read-only; see also RX9D (Register 33-2)
RCxREG (including the 9th bit) is double buffered, and data is available while new data is being received.
TXxREG(1): TRANSMIT DATA REGISTER
REGISTER 33-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TXxREG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
TXxREG: Lower eight bits of the received data; read-only; see also RX9D (Register 33-1)
TXxREG (including the 9th bit) is double buffered, and can be written when previous data has started
shifting.
SPxBRGL(1): BAUD RATE GENERATOR REGISTER
REGISTER 33-6:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPxBRG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
SPxBRG: Lower eight bits of the Baud Rate Generator
Writing to SP1BRG resets the BRG counter.
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
SPxBRGH(1, 2): BAUD RATE GENERATOR HIGH REGISTER
REGISTER 33-7:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPxBRG
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Note 1:
2:
SPxBRG: Upper eight bits of the Baud Rate Generator
SPxBRGH value is ignored for all modes unless BAUDxCON is active.
Writing to SPxBRGH resets the BRG counter.
2016-2018 Microchip Technology Inc.
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TABLE 33-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH EUSART
Bit 7
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
―
―
―
―
―
INTEDG
147
PIE3
RC2IE
TX2IE
RC1IE
TX1IE
BCL2IE
SSP2IE
BCL1IE
SSP1IE
151
PIR3
RC2IF
TX2IF
RC1IF
TX1IF
BCL2IF
SSP2IF
BCL1IF
SSP1IF
159
RCxSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
488
TXxSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
487
ABDOVF
RCIDL
―
SCKP
BRG16
―
WUE
ABDEN
489
BAUDxCON
RCxREG
EUSART Receive Data Register
490*
TXxREG
EUSART Transmit Data Register
490*
SPxBRGL
SPxBRG
SPxBRGH
490*
SPxBRG
491*
RXPPS
―
―
RXPPS
242
CKPPS
―
―
CXPPS
242
RxyPPS
―
―
CLCxSELy
―
―
Legend:
*
―
RxyPPS
LCxDyS
243
409
— = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART module.
Page with register information.
2016-2018 Microchip Technology Inc.
DS40001866B-page 492
PIC16(L)F15356/75/76/85/86
TABLE 33-3:
BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
0
8-bit/Asynchronous
FOSC/[64 (n+1)]
0
1
8-bit/Asynchronous
0
1
0
16-bit/Asynchronous
0
1
1
16-bit/Asynchronous
1
0
x
8-bit/Synchronous
1
x
16-bit/Synchronous
SYNC
BRG16
BRGH
0
0
0
1
Legend:
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair.
TABLE 33-4:
BAUD RATE FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
FOSC = 32.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 20.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 18.432 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
—
—
—
—
—
—
—
—
—
—
—
—
1200
—
—
—
1221
1.73
255
1200
0.00
239
1200
0.00
143
2400
2404
0.16
207
2404
0.16
129
2400
0.00
119
2400
0.00
71
9600
9615
0.16
51
9470
-1.36
32
9600
0.00
29
9600
0.00
17
10417
10417
0.00
47
10417
0.00
29
10286
-1.26
27
10165
-2.42
16
19.2k
19.23k
0.16
25
19.53k
1.73
15
19.20k
0.00
14
19.20k
0.00
8
57.6k
55.55k
—
-3.55
—
3
—
—
—
—
—
—
—
57.60k
—
0.00
7
—
57.60k
—
0.00
2
—
—
115.2k
—
SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
FOSC = 8.000 MHz
FOSC = 4.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 3.6864 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 1.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
—
1202
—
0.16
—
103
300
1202
0.16
0.16
207
51
300
1200
0.00
191
47
300
1202
0.16
0.16
51
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
—
—
—
9600
9615
0.16
12
—
—
—
9600
0.00
5
—
—
—
10417
10417
0.00
11
10417
0.00
5
—
—
—
—
—
—
19.2k
—
—
—
—
—
—
19.20k
0.00
2
—
—
—
57.6k
—
—
—
—
—
—
0.00
0
—
—
—
115.2k
—
—
—
—
—
—
57.60k
—
—
—
—
—
—
2016-2018 Microchip Technology Inc.
0.00
DS40001866B-page 493
PIC16(L)F15356/75/76/85/86
TABLE 33-4:
BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
300
1200
FOSC = 32.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 20.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 18.432 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 11.0592 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9600
—
0.00
—
71
2400
—
—
—
—
—
—
—
—
—
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.82k
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.64k
2.12
16
113.64k
-1.36
10
115.2k
0.00
9
115.2k
0.00
5
BAUD
RATE
FOSC = 8.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 3.6864 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 1.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
300
—
—
—
—
—
—
—
—
—
300
0.16
1200
—
—
—
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
—
—
—
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
5
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
—
—
—
57.6k
55556
-3.55
8
—
—
—
57.60k
0.00
3
—
—
—
115.2k
—
—
—
—
—
—
115.2k
0.00
1
—
—
—
207
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 32.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 20.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 18.432 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 11.0592 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
300
1200
300.0
1200
0.00
-0.02
6666
3332
300.0
1200
-0.01
-0.03
4166
1041
300.0
1200
0.00
0.00
3839
959
300.0
1200
0.00
0.00
2303
575
2400
2401
-0.04
832
2399
-0.03
520
2400
0.00
479
2400
0.00
287
BAUD
RATE
9600
9615
0.16
207
9615
0.16
129
9600
0.00
119
9600
0.00
71
10417
10417
0.00
191
10417
0.00
119
10378
-0.37
110
10473
0.53
65
19.2k
19.23k
0.16
103
19.23k
0.16
64
19.20k
0.00
59
19.20k
0.00
35
57.6k
57.14k
-0.79
34
56.818
-1.36
21
57.60k
0.00
19
57.60k
0.00
11
115.2k
117.6k
2.12
16
113.636
-1.36
10
115.2k
0.00
9
115.2k
0.00
5
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
TABLE 33-4:
BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 4.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 3.6864 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 1.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
300
1200
299.9
1199
-0.02
-0.08
1666
416
300.1
1202
0.04
0.16
832
207
300.0
1200
0.00
0.00
767
191
300.5
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
—
—
—
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
5
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
—
—
—
57.6k
55556
-3.55
8
—
—
—
57.60k
0.00
3
—
—
—
115.2k
—
—
—
—
—
—
115.2k
0.00
1
—
—
—
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
BAUD
RATE
FOSC = 32.000 MHz
FOSC = 20.000 MHz
FOSC = 18.432 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
FOSC = 11.0592 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
300.0
1200
0.00
0.00
26666
6666
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.01
3332
2400
0.02
2082
2400
0.00
1919
2400
0.00
1151
Actual
Rate
9600
9604
0.04
832
9597
-0.03
520
9600
0.00
479
9600
0.00
287
10417
10417
0.00
767
10417
0.00
479
10425
0.08
441
10433
0.16
264
19.2k
19.18k
-0.08
416
19.23k
0.16
259
19.20k
0.00
239
19.20k
0.00
143
57.6k
57.55k
-0.08
138
57.47k
-0.22
86
57.60k
0.00
79
57.60k
0.00
47
115.2k
115.9k
0.64
68
116.3k
0.94
42
115.2k
0.00
39
115.2k
0.00
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 8.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 4.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 3.6864 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 1.000 MHz
SPBRG
Actual
%
value
Rate
Error
(decimal)
300
1200
300.0
1200
0.00
-0.02
6666
1666
300.0
1200
0.01
0.04
3332
832
300.0
1200
0.00
0.00
3071
767
300.1
1202
0.04
0.16
832
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
0
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
—
—
—
115.2k
117.6k
2.12
16
111.1k
-3.55
8
115.2k
0.00
7
—
—
—
BAUD
RATE
2016-2018 Microchip Technology Inc.
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PIC16(L)F15356/75/76/85/86
34.0
REFERENCE CLOCK OUTPUT
MODULE
The reference clock output module provides the ability
to send a clock signal to the clock reference output pin
(CLKR).
The reference clock output module has the following
features:
• Selectable input clock
• Programmable clock divider
• Selectable duty cycle
34.1
CLOCK SOURCE
The reference clock output module has a selectable
clock source. The CLKRCLK register (Register 34-2)
controls which input is used.
34.1.1
CLOCK SYNCHRONIZATION
Once the reference clock enable (CLKREN) is set, the
module is ensured to be glitch-free at start-up.
When the reference clock output is disabled, the output
signal will be disabled immediately.
34.3
SELECTABLE DUTY CYCLE
The CLKRDC bits of the CLKRCON register can
be used to modify the duty cycle of the output clock. A
duty cycle of 25%, 50%, or 75% can be selected for all
clock rates, with the exception of the undivided base
FOSC value.
The duty cycle can be changed while the module is
enabled; however, in order to prevent glitches on the
output, the CLKRDC bits should only be changed
when the module is disabled (CLKREN = 0).
Note:
34.4
The CLKRDC1 bit is reset to ‘1’. This
makes the default duty cycle 50% and not
0%.
OPERATION IN SLEEP MODE
The reference clock output module clock is based on
the system clock. When the device goes to Sleep, the
module outputs will remain in their current state. This
will have a direct effect on peripherals using the
reference clock output as an input signal.
Clock dividers and clock duty cycles can be changed
while the module is enabled, but glitches may occur on
the output. To avoid possible glitches, clock dividers
and clock duty cycles should be changed only when the
CLKREN is clear.
34.2
PROGRAMMABLE CLOCK
DIVIDER
The module takes the system clock input and divides it
based on the value of the CLKRDIV bits of the
CLKRCON register (Register 34-1).
The following configurations can be made based on the
CLKRDIV bits:
•
•
•
•
•
•
•
•
Base clock value
Base clock value divided by 2
Base clock value divided by 4
Base clock value divided by 8
Base clock value divided by 16
Base clock value divided by 32
Base clock value divided by 64
Base clock value divided by 128
The clock divider values can be changed while the
module is enabled; however, in order to prevent
glitches on the output, the CLKRDIV bits should
only be changed when the module is disabled
(CLKREN = 0).
2016-2018 Microchip Technology Inc.
DS40001866B-page 496
PIC16(L)F15356/75/76/85/86
FIGURE 34-1:
CLOCK REFERENCE BLOCK DIAGRAM
Rev. 10-000261A
9/10/2015
CLKRDIV
Counter Reset
Reference Clock Divider
CLKREN
See
CLKRCLK
Register
D
CLKREN
CLKRCLK
FREEZE ENABLED(1)
ICD FREEZE MODE(1)
FIGURE 34-2:
Q
128
111
64
110
32
101
16
100
8
011
4
010
2
001
CLKRDC
CLKR
Duty Cycle
PPS
To Peripherals
000
EN
CLOCK REFERENCE TIMING
P2
P1
FOSC
CLKREN
CLKR Output
CLKRDIV[2:0] = 001
CLKRDC[1:0] = 10
Duty Cycle
(50%)
FOSC / 2
CLKR Output
CLKRDIV[2:0] = 001
CLKRDC[1:0] = 01
Duty Cycle (25%)
2016-2018 Microchip Technology Inc.
DS40001866B-page 497
PIC16(L)F15356/75/76/85/86
34.5
Register Definition: Reference Clock Output Control
REGISTER 34-1:
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
U-0
U-0
CLKREN
—
—
R/W-0/0
R/W-0/0
CLKRDC
R/W-0/0
R/W-0/0
R/W-0/0
CLKRDIV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CLKREN: Reference Clock Module Enable bit
1 = Reference clock module enabled
0 = Reference clock module is disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 4-3
CLKRDC: Reference Clock Duty Cycle bits (1)
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
bit 2-0
CLKRDIV: Reference Clock Divider bits
111 = Base clock value divided by 128
110 = Base clock value divided by 64
101 = Base clock value divided by 32
100 = Base clock value divided by 16
011 = Base clock value divided by 8
010 = Base clock value divided by 4
001 = Base clock value divided by 2
000 = Base clock value
Note 1:
Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.
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REGISTER 34-2:
CLKRCLK: CLOCK REFERENCE CLOCK SELECTION REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CLKRCLK
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
CLKRCLK: CLKR Input bits
Clock Selection
1111 = Reserved
•
•
•
1011 = Reserved
1010 = LC4_out
1001 = LC3_out
1000 = LC2_out
0111 = LC1_out
0110 = NCO1_out
0101 = SOSC
0100 = MFINTOSC (31.25 kHz)
0011 = MFINTOSC (500 kHz)
0010 = LFINTOSC
0001 = HFINTOSC
0000 = FOSC
TABLE 34-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT
Bit 7
Bit 6
Bit 5
CLKRCON
CLKREN
—
—
CLKRCLK
—
—
—
CLCxSELy
—
—
RxyPPS
—
—
Legend:
Bit 4
Bit 3
Bit 2
CLKRDC
—
Bit 1
CLKRDIV
CLKRCLK
LCxDyS
—
Bit 0
RxyPPS
Register
on Page
498
499
409
243
— = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.
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35.0
IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode the program memory, User IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the “PIC16(L)F153XX
Memory Programming Specification” (DS40001838).
35.1
High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
35.2
Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’. The LVP
bit can only be reprogrammed to ‘0’ by using the HighVoltage Programming mode.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1.
2.
35.3
Common Programming Interfaces
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin, 6connector) configuration. See Figure 35-1.
FIGURE 35-1:
VDD
ICD RJ-11 STYLE
CONNECTOR INTERFACE
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
VPP/MCLR
VSS
Target
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 35-2.
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 35-3 for more
information.
MCLR is brought to VIL.
A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 8.5 “MCLR” for more
information.
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FIGURE 35-2:
PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Rev. 10-000128A
7/30/2013
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
3
4
5
6
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No connect
FIGURE 35-3:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
Rev. 10-000129A
7/30/2013
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
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36.0
INSTRUCTION SET SUMMARY
36.1
Read-Modify-Write Operations
The literal and control category contains the most
varied instruction word format.
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according in either the working
(W) register, or the originating file register, depending
on the state of the destination designator 'd' (see
Table 36-1 for more information). A read operation is
performed on a register even if the instruction writes to
that register.
Table 36-3 lists the instructions recognized by the
MPASMTM assembler.
TABLE 36-1:
Each instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine entry takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of four oscillator cycles;
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
n
FSR or INDF number. (0-1)
mm
Prepost increment-decrement mode selection
TABLE 36-2:
ABBREVIATION
DESCRIPTIONS
Field
Program Counter
TO
Time-Out bit
C
DC
Z
PD
2016-2018 Microchip Technology Inc.
Description
PC
Carry bit
Digit Carry bit
Zero bit
Power-Down bit
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36.2
General Format for Instructions
TABLE 36-3:
INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BYTE ORIENTED SKIP OPERATIONS
1(2)
1(2)
00
00
1, 2
1, 2
1011 dfff ffff
1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
1, 2
1, 2
BIT-ORIENTED SKIP OPERATIONS
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Note 1:
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
2:
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
2016-2018 Microchip Technology Inc.
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
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TABLE 36-3:
INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
2
2
2
2
2
2
2
2
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
RESET
SLEEP
TRIS
–
–
–
–
f
Clear Watchdog Timer
No Operation
Software device Reset
Go into Standby or IDLE mode
Load TRIS register with W
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
0000
0000
0000
0000
0000
0110
0000
0000
0110
0110
0100 TO, PD
0000
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
C-COMPILER OPTIMIZED
k[n]
1
1
11
00
0001 0nkk kkkk
0000 0001 0nmm Z
2, 3
1
1
11
00
1111 0nkk kkkk Z
0000 0001 1nmm
2
2, 3
1
11
1111 1nkk kkkk
2
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Section 36.3 “Instruction Descriptions” for detailed MOVIW and MOVWI instruction descriptions.
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36.3
Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operands:
0 k 255
Operation:
(W) .AND. (k) (W)
Operation:
FSR(n) + k FSR(n)
Status Affected:
Z
Status Affected:
None
Description:
Description:
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
The contents of W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
AND literal with W
k
FSRn is limited to the range 0000hFFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
k
f,d
Status Affected:
C, DC, Z
Operation:
(W) .AND. (f) (destination)
Description:
The contents of the W register are
added to the 8-bit literal ‘k’ and the
result is placed in the W register.
Status Affected:
Z
Description:
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Add W and f
ASRF
Arithmetic Right Shift
ADDWF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0 f 127
d 0,1
f,d
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) (destination)
Operation:
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
(f) dest
(f) dest,
(f) C,
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
Status Affected:
C, Z
Description:
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
register f
C
f {,d}
Operation:
(W) + (f) + (C) dest
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
2016-2018 Microchip Technology Inc.
f {,d}
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BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
0 f 127
0b7
skip if (f) = 0
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f)
Operation:
Status Affected:
None
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a 2cycle instruction.
BRA
Relative Branch
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Syntax:
[ label ] BTFSS f,b
Operands:
-256 label - PC + 1 255
-256 k 255
Operands:
0 f 127
0b VDD) ................................................................................................... 20 mA
Total power dissipation(2)................................................................................................................................ 800 mW
Note 1:
2:
Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 37-6 to calculate device
specifications.
Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
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37.2
Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
VDDMIN VDD VDDMAX
TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC16LF15356/75/76/85/86
VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V
VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC16F15356/75/76/85/86
VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V
VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1:
See Parameter Supply Voltage, DS Characteristics: Supply Voltage.
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VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16F15356/75/76/85/86
ONLY
FIGURE 37-1:
VDD (V)
5.5
2.5
2.3
0
16
10
4
32
Frequency (MHz)
Note 1:The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies.
VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16LF15356/75/76/85/86
ONLY
VDD (V)
FIGURE 37-2:
3.6
2.5
1.8
0
4
10
16
32
Frequency (MHz)
Note 1:The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies.
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37.3
DC Characteristics
TABLE 37-1:
SUPPLY VOLTAGE
PIC16LF15356/75/76/85/86
Standard Operating Conditions (unless otherwise stated)
PIC16F15356/75/76/85/86
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ.†
Max.
Units
Conditions
Supply Voltage
D002
VDD
1.8
2.5
—
—
3.6
3.6
V
V
FOSC 16 MHz
FOSC 16 MHz
D002
VDD
2.3
2.5
—
—
5.5
5.5
V
V
FOSC 16 MHz
FOSC 16 MHz
RAM Data Retention(1)
D003
VDR
1.5
—
—
V
Device in Sleep mode
D003
VDR
1.7
—
—
V
Device in Sleep mode
Power-on Reset Release Voltage(2)
D004
VPOR
—
1.6
—
V
BOR or LPBOR disabled(3)
D004
VPOR
—
1.6
—
V
BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005
VPORR
—
0.8
—
V
BOR or LPBOR disabled(3)
D005
VPORR
—
1.5
—
V
BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset
signal(2)
D006
SVDD
0.05
—
—
V
BOR or LPBOR disabled(3)
D006
SVDD
0.05
—
—
V
BOR or LPBOR disabled(3)
†
Note 1:
2:
3:
4:
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
See Figure 37-3, POR and POR REARM with Slow Rising VDD.
See Table 37-11 for BOR and LPBOR trip point information.
= F device
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FIGURE 37-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(3)
Note 1:
2:
3:
TPOR(2)
When NPOR is low, the device is held in Reset.
TPOR 1 s typical.
TVLOW 2.7 s typical.
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TABLE 37-2:
SUPPLY CURRENT (IDD)(1,2,4)
Standard Operating Conditions (unless otherwise
stated)
PIC16LF15356/75/76/85/86
PIC16F15356/75/76/85/86
Param.
No.
Symbol
Device Characteristics
Min. Typ.† Max. Units
Conditions
VDD
Note
D100
IDDXT4
XT = 4 MHz
—
360
470
A
3.0V
D100
IDDXT4
XT = 4 MHz
—
380
480
A
3.0V
D101
IDDHFO16
HFINTOSC = 16 MHz
—
1.4
2.3
mA
3.0V
D101
IDDHFO16
HFINTOSC = 16 MHz
—
1.5
2.3
mA
3.0V
D102
IDDHFOPLL
HFINTOSC = 32 MHz
—
2.6
3.6
mA
3.0V
32 MHz PIC16
D102
IDDHFOPLL
HFINTOSC = 32 MHz
—
2.7
3.7
mA
3.0V
32 MHz PIC16
D103
IDDHSPLL32
HS+PLL = 32 MHz
—
2.6
3.6
mA
3.0V
32 MHz PIC16
D103
IDDHSPLL32
HS+PLL = 32 MHz
—
2.7
3.7
mA
3.0V
32 MHz PIC16
D104
IDDIDLE
IDLE mode, HFINTOSC = 16 MHz
—
0.8
1.1
mA
3.0V
D104
IDDIDLE
IDLE mode, HFINTOSC = 16 MHz
—
0.8
1.2
mA
3.0V
D105
IDDDOZE(3)
DOZE mode, HFINTOSC = 16 MHz, Doze
Ratio = 16
—
795
—
A
3.0V
Typical value only.
D105
IDDDOZE(3)
DOZE mode, HFINTOSC = 16 MHz, Doze
Ratio = 16
—
800
—
A
3.0V
Typical value only.
†
Note 1:
2:
3:
4:
5:
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 11-2).
PMD bits are all in the default state, no modules are disabled.
= F device
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TABLE 37-3:
POWER-DOWN CURRENT (IPD)(1,2,3)
PIC16LF15356/75/76/85/86
Standard Operating Conditions (unless otherwise stated)
PIC16F15356/75/76/85/86
Standard Operating Conditions (unless otherwise stated)
VREGPM = 1
Param.
No.
Symbol
Device Characteristics
Min.
Typ.†
Max.
Max.
Units
+85°C +125°C
Conditions
VDD
6
A
3.0V
2.5
9
27
0.4
2.9
9
A
A
A
3.0V
22
—
0.5
3.3
13
A
3.0V
Secondary Oscillator (SOSC)
—
0.6
2.8
13
3.0V
IPD_SOSC
Secondary Oscillator (SOSC)
—
0.8
3.2
15
IPD_FVR
FVR
—
45
74
76
IPD_FVR
FVR
—
40
70
75
D204
IPD_BOR
Brown-out Reset (BOR)
—
10
17
19
D204
IPD_BOR
Brown-out Reset (BOR)
—
14
18
20
D205
IPD_LPBOR
Low-Power Brown-out Reset (LPBOR)
—
0.5
4
10
D205
IPD_LPBOR
Low-Power Brown-out Reset (LPBOR)
0.7
5
11
D206
IPD_ADCA
ADC - Active
—
250
—
—
D206
IPD_ADCA
ADC - Active
—
280
—
—
D207
IPD_CMP
Comparator
—
30
90
93
D207
IPD_CMP
Comparator
—
33
93
98
A
A
A
A
A
A
A
A
A
A
A
A
D200
IPD
IPD Base
—
0.05
2
D200
D200A
IPD
IPD Base
—
0.4
—
18
D201
IPD_WDT
Low-Frequency Internal Oscillator/
WDT
—
D201
IPD_WDT
Low-Frequency Internal Oscillator/
WDT
D202
IPD_SOSC
D202
D203
D203
†
Note
1:
2:
3:
4:
5:
3.0V
Note
VREGPM = 0
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
3.0V
ADC is converting (4)
3.0V
ADC is converting (4)
3.0V
3.0V
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The
peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used
when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part
in Sleep mode with all I/O pins in high-impedance state and tied to VSS.
All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available.
ADC clock source is FRC.
= F device
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TABLE 37-4:
I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
VIL
Characteristic
Min.
Typ†
Max.
Units
—
—
Conditions
—
0.8
V
4.5V VDD 5.5V
—
0.15 VDD
V
1.8V VDD 4.5V
2.0V VDD 5.5V
Input Low Voltage
I/O PORT:
D300
with TTL buffer
D301
D302
with Schmitt Trigger buffer
—
—
0.2 VDD
V
D303
with I2C levels
—
—
0.3 VDD
V
with SMBus levels
—
—
0.8
V
—
—
0.2 VDD
V
D304
D305
MCLR
VIH
2.7V VDD 5.5V
Input High Voltage
I/O PORT:
D320
with TTL buffer
D321
2
—
—
V
4.5V VDD 5.5V
0.25 VDD +
0.8
—
—
V
1.8V VDD 4.5V
2.0V VDD 5.5V
D322
with Schmitt Trigger buffer
0.8 VDD
—
—
V
D323
with I2C levels
0.7 VDD
—
—
V
D324
with SMBus levels
D325
MCLR
IIL
D340
D341
MCLR(2)
IPUR
Weak Pull-up Current
VOL
Output Low Voltage
VOH
Output High Voltage
CIO
All I/O pins
D350
D360
I/O ports
D370
I/O ports
D380
—
—
V
—
—
V
—
±5
± 125
nA
VSS VPIN VDD,
Pin at high-impedance, 85°C
—
±5
± 1000
nA
VSS VPIN VDD,
Pin at high-impedance, 125°C
—
± 50
± 200
nA
VSS VPIN VDD,
Pin at high-impedance, 85°C
25
100
200
A
VDD = 3.0V, VPIN = VSS
—
—
0.6
V
IOL = 10.0 mA, VDD = 3.0V
VDD - 0.7
—
—
V
IOH = 6.0 mA, VDD = 3.0V
—
5
50
pF
Input Leakage Current(1)
I/O Ports
D342
2.7V VDD 5.5V
2.1
0.7 VDD
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1:Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
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TABLE 37-5:
MEMORY PROGRAMMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
High Voltage Entry Programming Mode Specifications
MEM01
VIHH
Voltage on MCLR/VPP pin to enter
programming mode
8
—
9
V
MEM02
IPPGM
Current on MCLR/VPP pin during
programming mode
—
1
—
mA
(Note 2, Note 3)
(Note 2)
Programming Mode Specifications
MEM10 VBE
VDD for Bulk Erase
—
2.7
—
V
MEM11 IDDPGM
Supply Current during Programming
operation
—
—
10
mA
Program Flash Memory Specifications
MEM30 EP
Flash Memory Cell Endurance
10k
—
—
E/W
-40C TA +85C
(Note 1)
MEM32 TP_RET
Characteristic Retention
—
40
—
Year
Provided no other
specifications are violated
MEM33 VP_RD
VDD for Read operation
VDDMIN
—
VDDMAX
V
VDDMIN
—
VDDMAX
V
2.0
2.5
ms
MEM34 VP_REW VDD for Row Erase or Write
operation
MEM35 TP_REW Self-Timed Row Erase or Self-Timed —
Write
†
Note 1:
2:
3:
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed
Write. HEF feature applies only to the last 128 words of the Program Flash Memory.
Required only if CONFIG4, bit LVP is disabled.
The MPLAB® ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed
between the ICD2 and target system when programming or debugging with the ICD2.
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TABLE 37-6:
THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param.
No.
TH01
TH02
TH03
TH04
TH05
Sym.
Characteristic
JA
Thermal Resistance Junction to Ambient
JC
TJMAX
PD
Thermal Resistance Junction to Case
Maximum Junction Temperature
Power Dissipation
PINTERNAL Internal Power Dissipation
Typ.
Units
Conditions
60
C/W
80
C/W
28-pin SOIC package
90
C/W
28-pin SSOP package
28-pin SPDIP package
48
C/W
28-pin UQFN 4x4mm package
47.2
C/W
40-pin PDIP package
41.0
C/W
40-pin UQFN 5x5 package
46.0
C/W
44-pin TQFP package
24.4
C/W
44-pin QFN 8X8mm package
27.6
C/W
48-pin UQFN 6x6 package
—
C/W
48-pin TQFP 7x7 package
31.4
C/W
28-pin SPDIP package
24
C/W
28-pin SOIC package
24
C/W
28-pin SSOP package
12
C/W
28-pin UQFN 4x4mm package
24.70
C/W
40-pin PDIP package
5.5
C/W
40-pin UQFN 5x5 package
14.5
C/W
44-pin TQFP package
20.0
C/W
44-pin QFN 8X8mm package
6.7
C/W
48-pin UQFN 6x6 package
—
C/W
48-pin TQFP 7x7 package
150
C
—
W
PD = PINTERNAL + PI/O
—
W
PINTERNAL = IDD x VDD(1)
TH06
P I /O
I/O Power Dissipation
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07
PDER
Derated Power
—
W
PDER = PDMAX (TJ - TA)/JA(2)
Note 1:IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature, TJ = Junction Temperature
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37.4
AC Characteristics
FIGURE 37-4:
LOAD CONDITIONS
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins
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FIGURE 37-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS12
OS02
OS11
OS03
CLKOUT
(CLKOUT Mode)
Note
1:
See Table 37-7.
TABLE 37-7:
EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
ECL Oscillator
OS1
FECL
Clock Frequency
—
—
500
kHz
OS2
TECL_DC
Clock Duty Cycle
40
—
60
%
ECM Oscillator
OS3
FECM
Clock Frequency
—
—
4
MHz
OS4
TECM_DC
Clock Duty Cycle
40
—
60
%
ECH Oscillator
OS5
FECH
Clock Frequency
—
—
32
MHz
OS6
TECH_DC
Clock Duty Cycle
40
—
60
%
Clock Frequency
—
—
100
kHz
Note 4
Clock Frequency
—
—
4
MHz
Note 4
Clock Frequency
—
—
20
MHz
LP Oscillator
OS7
FLP
XT Oscillator
OS8
FXT
HS Oscillator
OS9
FHS
System Oscillator
OS20
FOSC
System Clock Frequency
—
—
32
MHz
OS21
FCY
Instruction Frequency
—
FOSC/4
—
MHz
OS22
TCY
Instruction Period
125
1/FCY
—
ns
*
†
Note 1:
2:
3:
4:
(Note 2, Note 3)
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 9.0
“Oscillator Module (with Fail-Safe Clock Monitor)”.
The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 “Standard
Operating Conditions”.
LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking
the device with the external square wave, one of the EC mode selections must be used.
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INTERNAL OSCILLATOR PARAMETERS(1)
TABLE 37-8:
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Precision Calibrated HFINTOSC
Frequency
Min.
Typ†
Max. Units
—
4
8
12
16
32
—
0.93
1.86
1
2
1.07
2.14
MHz
MHz
OS50
FHFOSC
OS51
FHFOSCLP Low-Power Optimized HFINTOSC
Frequency
OS52
FMFOSC
Internal Calibrated MFINTOSC
Frequency
—
500
—
kHz
OS53
FLFOSC
Internal LFINTOSC Frequency
—
31
—
kHz
OS54
THFOSCST HFINTOSC
Wake-up from Sleep Start-up
Time
—
—
11
50
20
—
s
s
OS56
TLFOSCST
—
0.2
—
ms
LFINTOSC
Wake-up from Sleep Start-up Time
Conditions
MHz (Note 2)
(Note 3)
VREGPM = 0
VREGPM = 1
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature.
3: See Figure 38-87: LFINTOSC Frequency, PIC16LF15356/75/76/85/86 devices only and Figure 38-88:
LFINTOSC Frequency, PIC16F15356/75/76/85/86 devices only.
FIGURE 37-6:
PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE
VDD AND TEMPERATURE
125
± 5%
Temperature (°C)
85
± 3%
60
± 2%
0
± 5%
-40
1.8
2.0
2.3
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
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TABLE 37-9:
PLL SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated) VDD 2.5V
Param.
No.
Sym.
Characteristic
PLL Input Frequency Range
Min.
Typ†
Max.
Units Conditions
4
—
8
MHz
MHz Note 1
PLL01
FPLLIN
PLL02
FPLLOUT PLL Output Frequency Range
16
—
32
PLL03
TPLLST
PLL Lock Time from Start-up
—
200
—
s
PLL04
FPLLJIT
PLL Output Frequency Stability (Jitter)
-0.25
—
0.25
%
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002.
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FIGURE 37-7:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Q1
Q4
Read
Execute
Q2
Q3
FOSC
IO2
IO1
IO10
CLKOUT
IO8, IO9
IO6, IO7
IO5
IO4
I/O pin
(Input)
IO3
I/O pin
(Output)
New Value
Old Value
IO6, IO7, IO8, IO9
TABLE 37-10:
I/O AND CLKOUT TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
IO7*
CLKOUT rising edge delay (rising
edge FOSC (Q1 cycle) to falling edge
CLKOUT
CLKOUT falling edge delay (rising
TCLKOUTL
edge FOSC (Q3 cycle) to rising edge
CLKOUT
TIO_VALID
Port output valid time (rising edge
Fosc (Q1 cycle) to port valid)
Port input setup time (Setup time
TIO_SETUP
before rising edge Fosc – Q2 cycle)
Port input hold time (Hold time after
TIO_HOLD
rising edge Fosc – Q2 cycle)
TIOR_SLREN Port I/O rise time, slew rate enabled
TIOR_SLRDIS Port I/O rise time, slew rate disabled
IO8*
TIOF_SLREN
Port I/O fall time, slew rate enabled
—
25
—
ns
VDD = 3.0V
IO9*
TIOF_SLRDIS Port I/O fall time, slew rate disabled
—
5
—
ns
VDD = 3.0V
IO10*
TINT
25
—
—
ns
IO11*
TIOC
25
—
—
ns
IO1*
IO2*
IO3*
IO4*
IO5*
IO6*
TCLKOUTH
INT pin high or low time to trigger an
interrupt
Interrupt-on-Change minimum high or
low time to trigger interrupt
*These parameters are characterized but not tested.
2016-2018 Microchip Technology Inc.
—
—
70
ns
—
—
72
ns
—
50
70
ns
20
—
—
ns
50
—
—
ns
—
25
—
ns
VDD = 3.0V
—
5
—
ns
VDD = 3.0V
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FIGURE 37-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
RST01
Internal
POR
RST04
PWRT
Time-out
RST05
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
RST03
RST02
RST02
I/O pins
Note 1:Asserted low.
FIGURE 37-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR + VHYST
VBOR
(Device not in Brown-out Reset)
(Device in Brown-out Reset)
(RST08)(1)
Reset
(due to BOR)
(RST04)(1)
Note 1:64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms
delay if PWRTE = 0.
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TABLE 37-11: RESET, WDT, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT
RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
RST01*
TMCLR
MCLR Pulse Width Low to ensure Reset
2
—
—
s
RST02*
TIOZ
I/O high-impedance from Reset detection
—
—
2
s
RST03
TWDT
Watchdog Timer Time-out Period
—
16
—
ms
RST04*
TPWRT
Power-up Timer Period
—
65
—
ms
RST05
TOST
Oscillator Start-up Timer Period(1,2)
RST06
VBOR
Brown-out Reset Voltage
RST07
VBORHYS
RST08
TBORDC
RST09
VLPBOR
—
1024
—
TOSC
2.55
2.30
1.80
2.70
2.45
1.90
2.85
2.60
2.10
V
V
V
Brown-out Reset Hysteresis
—
40
—
mV
Brown-out Reset Response Time
—
3
—
s
Low-Power Brown-out Reset Voltage
1.8
2.0
2.2
V
Conditions
16 ms Nominal Reset Time
BORV = 0
BORV = 1 (F devices)
BORV = 1 (LF devices)
LF Devices Only
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible.
0.1 F and 0.01 F values in parallel are recommended.
TABLE 37-12:
ANALOG-TO-DIGITAL CONVERTER (ADC) ACCURACY SPECIFICATIONS(1,2):
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
bit
Conditions
AD01
NR
Resolution
—
—
10
AD02
EIL
Integral Error
—
±0.1
±1.0
AD03
EDL
Differential Error
—
±0.1
±1.0
LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD04
EOFF
Offset Error
—
0.5
2.0
LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD05
EGN
Gain Error
—
±0.2
±1.0
LSb ADCREF+ = 3.0V, ADCREF-= 0V
AD06
VADREF ADC Reference Voltage
(ADREF+)(3)
1.8
—
VDD
V
AD07
VAIN
Full-Scale Range
ADREF-
—
ADREF+
V
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
—
10
—
k
AD09
RVREF
ADC Voltage Reference Ladder
Impedance
—
50
—
k
LSb ADCREF+ = 3.0V, ADCREF-= 0V
Note 3
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1:Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.
2: The ADC conversion result never decreases with an increase in the input and has no missing codes.
3: This is the impedance seen by the VREF pads when the external reference pads are selected.
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TABLE 37-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym.
No.
AD20
TAD
Characteristic
Min.
Typ†
Max.
Units
1
—
9
s
The requirement is to set ADCCS
correctly to produce this period/
frequency.
1
2
6
s
Using FRC as the ADC clock
source ADOSC = 1
Set of GO/DONE bit to Clear of GO/
DONE bit
ADC Clock Period
AD21
AD22
TCNV
Conversion Time
—
11
—
TAD
AD23
TACQ Acquisition Time
—
2
—
s
AD24
THCD Sample and Hold Capacitor
Disconnect Time
—
—
—
s
*
†
Conditions
FOSC-based clock source
FRC-based clock source
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)
FIGURE 37-10:
BSF ADCON0, GO
AD24
1 TCY
AD22
Q4
9
ADC Data
8
6
7
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD23
FIGURE 37-11:
ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC)
BSF ADCON0, GO
AD24
1 TCY
AD22
Q4
AD20
ADC_clk
9
ADC Data
8
7
6
OLD_DATA
ADRES
2
1
0
NEW_DATA
1 TCY
ADIF
GO
Sample
3
DONE
AD23
2016-2018 Microchip Technology Inc.
Sampling Stopped
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TABLE 37-14:
COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
No.
CM01
Sym.
VIOFF
Characteristics
Input Offset Voltage
Min.
Typ.
Max.
Units
—
—
±50
mV
Comments
VICM = VDD/2
CM02
VICM
Input Common Mode Range
GND
—
VDD
V
CM03
CMRR
Common Mode Input Rejection Ratio
—
50
—
dB
CM04
VHYST
Comparator Hysteresis
15
25
35
mV
CM05
TRESP(1)
Response Time, Rising Edge
—
300
600
ns
Response Time, Falling Edge
—
220
500
ns
CMOS6
TMCV2VO(2)
Mode Change to Valid Output
—
—
10
µs
*
Note 1:
2:
These parameters are characterized but not tested.
Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.
A mode change includes changing any of the control register values, including module enable.
TABLE 37-15: 5-BIT DAC SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
No.
DSB01
Sym.
Characteristics
Min.
Typ.
Max.
Units
—
(VDACREF+ -VDACREF-) /32
—
V
LSb
VLSB
Step Size
DSB01
VACC
Absolute Accuracy
—
—
0.5
DSB03*
RUNIT
Unit Resistor Value
—
5000
—
DSB04*
TST
Settling Time(1)
—
—
10
s
*
†
Note 1:
Comments
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Settling time measured while DACR transitions from ‘00000’ to ‘01111’.
TABLE 37-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
FVR01
VFVR1
1x Gain (1.024V)
-4
—
+4
%
VDD 2.5V, -40°C to
85°C
FVR02
VFVR2
2x Gain (2.048V)
-4
—
+4
%
VDD 2.5V, -40°C to
85°C
FVR03
VFVR4
4x Gain (4.096V)
-6
—
+6
%
VDD 4.75V, -40°C
to 85°C
FVR04
TFVRST
FVR Start-up Time
—
25
—
us
FVR05
FVRA1X/FVRC1X
FVR output voltage for 1x setting stored in
the DIA
—
1024
—
mV
FVR06
FVRA2X/FVRC2X
FVR output voltage for 2x setting stored in
the DIA
—
2048
—
mV
FVR07
FVRA4X/FVRC4X
FVR output voltage for 4x setting stored in
the DIA
—
4096
—
mV
Note 1:
Note 1
Available only on PIC16F15354/55.
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TABLE 37-17: ZERO CROSS DETECT (ZCD) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param.
No.
Sym.
Characteristics
ZC01
ZPCINV
Voltage on Zero Cross Pin
ZC02
ZCDRV
ZC04
ZCISW
ZC05
ZCOUT
†
Min.
Typ†
Max.
Units
—
0.75
—
V
Maximum source or sink current
—
—
600
A
Response Time, Rising Edge
—
1
—
s
Response Time, Falling Edge
—
1
—
s
Response Time, Rising Edge
—
1
—
s
Response Time, Falling Edge
—
1
—
s
Comments
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 37-12:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
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TABLE 37-18: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No.
Sym.
TT0H
40*
Characteristic
T0CKI High-Pulse Width
Min.
No Prescaler
With Prescaler
TT0L
41*
T0CKI Low-Pulse Width
No Prescaler
With Prescaler
42*
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler
Time
Synchronous, with Prescaler
Asynchronous
TT1L
46*
T1CKI Low
Time
Max.
Units
0.5 TCY + 20
—
—
ns
10
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of: 20
or (TCY +40)*N
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
ns
30
—
—
Synchronous, No Prescaler
0.5 TCY + 20
—
—
ns
Synchronous, with Prescaler
15
—
—
ns
30
—
—
ns
Greater of: 30
or (TCY +40)*N
—
—
ns
Asynchronous
47*
TT1P
T1CKI Input Synchronous
Period
48
F T1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
Asynchronous
*
†
Typ†
60
—
—
ns
32.4
32.768
33.1
kHz
2 TOSC
—
7 TOSC
—
Conditions
N = prescale value
(2, 4,...256)
N = prescale value
(2, 4,...256)
Timers in Sync
mode
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
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FIGURE 37-13:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01
CC02
CC03
Note:
Refer to Figure 37-4 for load conditions.
TABLE 37-19: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
Sym.
No.
Characteristic
CC01*
TccL
CCPx Input Low Time
No Prescaler
CC02*
TccH
CCPx Input High Time
No Prescaler
With Prescaler
With Prescaler
CC03*
*
†
TccP
CCPx Input Period
Min.
Typ†
Max.
Units
0.5TCY + 20
—
—
ns
ns
20
—
—
0.5TCY + 20
—
—
ns
20
—
—
ns
(3TCY +40)*N
—
—
ns
Conditions
N = prescale value (1,4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
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FIGURE 37-14:
CLC PROPAGATION TIMING
Rev. 10-000031A
6/16/2016
CLCxINn
CLC
Input time
CLCxINn
CLC
Input time
LCx_in[n](1)
LCx_in[n](1)
CLC01
Note 1:
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC
Module
LCx_out(1)
CLC
Output time
CLCx
CLC02
CLC03
See Figure 31-1 to identify specific CLC signals.
TABLE 37-20: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
CLC01* TCLCIN
CLC input pin (CKCxIN) to CKC Module Input
select (LCx_IN) propagation time
—
7
IO5
ns
(Note 1)
CLC02* TCLC
CLC Module input to output propagation delay
—
—
24
12
—
—
ns
ns
VDD = 1.8V
VDD > 3.6V
CLC03* TCLCOUT CLC Module output time
CLC04* FCLCMAX CLC Maximum switching frequency
—
IO7
—
—
Rise Time (Note 1)
—
IO8
—
—
Fall Time (Note 1)
—
32
FOSC
MHz
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1:See Table 37-10 for IO5, IO7 and IO8 rise and fall times.
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FIGURE 37-15:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121
US121
DT
US122
US120
Note:
Refer to Figure 37-4 for load conditions.
TABLE 37-21: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
US120
TCKH2DTV
SYNC XMIT (Master and Slave)
Clock high to data-out valid
—
80
ns
3.0V VDD 5.5V
—
100
ns
1.8V VDD 5.5V
US121
TCKRF
Clock out rise time and fall time
(Master mode)
—
45
ns
3.0V VDD 5.5V
—
50
ns
1.8V VDD 5.5V
Data-out rise time and fall time
—
45
ns
3.0V VDD 5.5V
—
50
ns
1.8V VDD 5.5V
US122
TDTRF
FIGURE 37-16:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
US125
DT
US126
Note: Refer to Figure 37-4 for load conditions.
TABLE 37-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param.
No.
Symbol
US125
TDTV2CKL
US126
TCKL2DTL
Characteristic
Min.
Max.
Units
SYNC RCV (Master and Slave)
Data-setup before CK (DT hold time)
10
—
ns
Data-hold after CK (DT hold time)
15
—
ns
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Conditions
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FIGURE 37-17:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 37-4 for load conditions.
FIGURE 37-18:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
SP78
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 37-4 for load conditions.
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FIGURE 37-19:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
MSb
SDO
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 37-4 for load conditions.
FIGURE 37-20:
SS
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SP83
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
MSb
SDO
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 37-4 for load conditions.
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TABLE 37-23: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
SP70*
Symbol
Characteristic
Min.
Typ†
Max.
Units
TSSL2SCH,
TSSL2SCL
SS to SCK or SCK input
2.25*TCY
—
—
ns
SP71*
TSCH
SCK input high time (Slave mode)
TCY + 20
—
—
ns
SP72*
TSCL
SCK input low time (Slave mode)
TCY + 20
—
—
ns
SP73*
TDIV2SCH,
TDIV2SCL
Setup time of SDI data input to SCK
edge
100
—
—
ns
SP74*
TSCH2DIL,
TSCL2DIL
Hold time of SDI data input to SCK edge
100
—
—
ns
SP75*
TDOR
SDO data output rise time
Conditions
—
10
25
ns
3.0V VDD 5.5V
—
25
50
ns
1.8V VDD 5.5V
SDO data output fall time
—
10
25
ns
SP76*
TDOF
SP77*
TSSH2DOZ
SS to SDO output high impedance
10
—
50
ns
SP78*
TSCR
SCK output rise time
(Master mode)
—
10
25
ns
3.0V VDD 5.5V
—
25
50
ns
1.8V VDD 5.5V
25
ns
SP79*
TSCF
SCK output fall time (Master mode)
—
10
SP80*
TSCH2DOV,
TSCL2DOV
SDO data output valid after SCK edge
—
—
50
ns
3.0V VDD 5.5V
—
—
145
ns
1.8V VDD 5.5V
SP81*
TDOV2SCH,
TDOV2SCL
SDO data output setup to SCK edge
1 Tcy
—
—
ns
SP82*
TSSL2DOV
SDO data output valid after SS edge
—
—
50
ns
SP83*
TSCH2SSH,
TSCL2SSH
SS after SCK edge
1.5 TCY + 40
—
—
ns
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
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FIGURE 37-21:
I2C BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 37-4 for load conditions.
TABLE 37-24: I2C BUS START/STOP BITS REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
SP90*
Symbol
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
THD:STO
SP93
*
Characteristic
Min.
Typ
Max.
Units
Conditions
ns
Only relevant for Repeated Start
condition
ns
After this period, the first clock
pulse is generated
Start condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
Start condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
Stop condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
Stop condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
ns
ns
These parameters are characterized but not tested.
FIGURE 37-22:
I2C BUS DATA TIMING
SP103
SCL
SP100
SP90
SP102
SP101
SP106
SP107
SP91
SDA
In
SP92
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 37-4 for load conditions.
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TABLE 37-25: I2C BUS DATA REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
SP100*
Symbol
THIGH
Characteristic
Clock high time
Min.
Max.
Units
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1.5TCY
—
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
SSP module
SP101*
Clock low time
TLOW
SSP module
SP102*
SDA and SCL rise
time
TR
SP103*
SP106*
THD:DAT
TSU:DAT
SP107*
SP109*
Data input hold time
Data input setup time
Output valid from
clock
TAA
SP110*
1.5 TCY
—
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
SDA and SCL fall time 100 kHz mode
TF
Bus free time
TBUF
Conditions
—
250
ns
400 kHz mode
20 + 0.1 CB
250
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
—
400
pF
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
SP111
CB
*
Note 1:
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL
line is released.
2:
Bus capacitive loading
TABLE 37-26: TEMPERATURE INDICATOR REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param No.
Symbol
Characteristic
Min.
TS01
TACQMIN
Minimum ADC Acquisition Time Delay
TS02
MV
Voltage Sensitivity
Typ†
Max.
Units
Conditions
—
25
—
s
High Range
—
-3.684
—
mV/°C
TSRNG = 1
Low Range
—
-2.456
—
mV/°C
TSRNG = 0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2016-2018 Microchip Technology Inc.
DS40001866B-page 543
PIC16(L)F15356/75/76/85/86
38.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Unless otherwise noted, all graphs apply to both the L and LF devices.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
2016-2018 Microchip Technology Inc.
DS40001866B-page 544
PIC16(L)F15356/75/76/85/86
1.0
1.0
0.5
0.5
DNL (LSb)
DNL (LSb)
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
0.0
0.0
-0.5
-0.5
-1.0
-1.0
0
128
256
384
512
640
768
896
0
1024
128
256
384
1.0
1.0
0.5
0.5
0.0
-0.5
768
896
1024
0.0
-0.5
-1.0
-1.0
0
128
256
384
512
640
768
896
1024
0
128
256
384
Output Code
512
640
768
896
1024
Output Code
FIGURE 38-3:
ADC 10-bit Mode, SingleEnded DNL, VDD= 3.0V, VREF = 3.0V, TAD = 8
uS, 25°C.
FIGURE 38-4:
ADC 10-bit Mode, SingleEnded INL, VDD= 3.0V, VREF = 3.0V, TAD = 1 uS,
25°C.
2.0
1.0
2.0
1.0
1.5
1.5
1.0
1.0
0.5
0.5
0.5
0.5
INL (LSb)
DNL (LSb)
INL (LSb)
DNL (LSb)
640
FIGURE 38-2:
ADC 10-bit Mode, SingleEnded DNL, VDD= 3.0V, VREF = 3.0V, TAD = 4
uS, 25°C.
INL (LSb)
DNL (LSb)
FIGURE 38-1:
ADC 10-bit Mode, SingleEnded DNL, VDD= 3.0V, VREF = 3.0V, TAD = 1
uS, 25°C.
0.0
-0.5
0.0
-1.0
-1.5
-2.0
-0.5
512
Output Code
Output Code
0.0
-0.5
0.0
-1.0
-1.5
0
512
1024
1536
2048
2560
3072
3584
4096
-2.0
-0.5
0
512
1024
1536
Output Code
2048
2560
3072
3584
4096
640
768
896
1024
Output Code
-1.0
-1.0
0
128
256
384
512
640
768
896
1024
Output Code
FIGURE 38-5:
ADC 10-bit Mode, SingleEnded INL, VDD= 3.0V, VREF = 3.0V, TAD = 4 uS,
25°C.
DS40001866A-page 545
0
128
256
384
512
Output Code
FIGURE 38-6:
ADC 10-bit Mode, SingleEnded INL, VDD= 3.0V, VREF = 3.0V, TAD = 8 uS,
25°C.
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
0.5
0.5
INL (LSB)
1
DNL (LSB)
1
0
-0.5
-0.5
Max 25°C
Min 25°C
Max -40°C
Min -40°C
Max 85°C
Min 85°C
-1
0.5
0.8
1
2
4
0
Max 25°C
Min 25°C
Max -40°C
Min -40°C
Max 85°C
Min 85°C
-1
0.5
8
0.8
1
2
4
8
TADs
TADs
FIGURE 38-7:
ADC 10-bit Mode, SingleEnded DNL, VDD= 3.0V, VREF = 3.0V
FIGURE 38-8:
ADC 10-bit Mode, SingleEnded INL, VDD= 3.0V, VREF = 3.0V
1
2
1.5
0.5
1
INL(LSB)
DNL(LSB)
0.5
0
0
-0.5
-0.5
-1
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-1
1.8
2.3
2.5
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-1.5
-2
3
1.8
2.3
VREF
FIGURE 38-9:
ADC 10-bit Mode, SingleEnded DNL, VDD= 3.0V, TAD = 1 uS
3
FIGURE 38-10:
ADC 10-bit Mode, SingleEnded INL, VDD= 3.0V, TAD = 1 uS
6
3
5
2.5
4
2
3
1.5
2
1
1
0.5
(LSB)
(LSB)
2.5
VREF
0
-1
0
-0.5
-2
-1
-3
-1.5
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-4
-5
-6
1.8
2.3
2.5
-2.5
-3
3
VREF
FIGURE 38-11:
ADC 10-bit Mode, SingleEnded Gain Error, VDD= 3.0V, TAD = 1 uS
2016-2018 Microchip Technology Inc.
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-2
1.8
2.3
2.5
3
VREF
FIGURE 38-12:
ADC 10-bit Mode, SingleEnded Offset Error, VDD= 3.0V, TAD = 1 uS
DS40001866A-page 546
PIC16(L)F15356/75/76/85/86
1
1
0.5
0.5
INL(LSB)
DNL(LSB)
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
0
-0.5
-0.5
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-1
1.8
2.3
2.5
0
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-1
3
1.8
2.3
2.5
VREF
3
VREF
FIGURE 38-13:
ADC 10-bit Mode, SingleEnded DNL, VDD= 3.0V, TAD = 4 uS.
FIGURE 38-14:
ADC 10-bit Mode, SingleEnded INL, VDD= 3.0V, TAD = 4 uS.
1
6
5
4
0.5
3
2
(LSB)
(LSB)
1
0
0
-1
-2
-3
-0.5
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-4
-5
-6
1.8
2.3
2.5
Max 85°C
Max 25°C
Max -40°C
Min 85°C
Min 25°C
Min -40°C
-1
1.8
3
2.3
2.5
FIGURE 38-15:
ADC 10-bit Mode, SingleEnded Gain Error, VDD= 3.0V, TAD = 4 uS
FIGURE 38-16:
ADC 10-bit Mode, SingleEnded Offset Error, VDD= 3.0V, TAD = 4 uS
2
2
1.5
1.5
1
1
0.5
0.5
(LSB)
(LSB)
3
VREF
VREF
0
0
-0.5
-0.5
-1
-1
Max
Max
-1.5
-1.5
Typical
Typical
Min
Min
-2
-2
0.5
0.8
1
2
4
TADs
FIGURE 38-17:
ADC 10-bit Mode, SingleEnded Gain Error, VDD= 3.0V, VREF = 3.0V, 40°C to 85°C.
DS40001866A-page 547
8
0.5
0.8
1
2
4
8
TADs
FIGURE 38-18:
ADC 10-bit Mode, SingleEnded Offset Error, VDD= 3.0V, VREF = 3.0V, 40°C to 85°C
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
5.0
4.0
Typical 25°C
4.5
+3ı (-40°C to +125°C)
4.0
3.5
-3ı (-40°C to +125°C)
3.0
2.5
3.0
Time (us)
Time (us)
3.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
Typical 25°C
0.5
0.5
+3ı (-40°C to +125°C)
-3ı (-40°C to +125°C)
0.0
0.0
1.7
1.9
2.1
2.3
2.5
2.7
VDD (V)
2.9
3.1
3.3
3.5
3.7
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
VDD (V)
FIGURE 38-19:
ADC RC Oscillator Period,
PIC16LF15356/75/76/85/86 devices only.
FIGURE 38-20:
ADC RC Oscillator Period,
PIC16F15356/75/76/85/86 devices only.
5.0
70
Typical 25°C
Typical 25°C
4.5
+3ı (-40°C to +125°C)
60
+3 Sigma 125°C
4.0
3.5
Time (us)
Time (us)
50
40
30
3.0
2.5
2.0
1.5
1.0
20
0.5
10
0.0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
2.6
2.7
2.8
2.9
3.0
3.1
FIGURE 38-21:
Band Gap Ready
3.3
3.4
3.5
3.6
3.7
FIGURE 38-22:
Brown-out Reset Response
Time, PIC16LF15356/75/76/85/86 devices only.
7
3.00
Typical 25°C
+3 Sigma
2.95
+3 Sigma 125°C
6
3.2
VDD (V)
VDD (V)
-3 Sigma
2.90
Typical
2.85
5
Voltage (V)
Time (us)
2.80
4
3
2.75
2.70
2.65
2.60
2
2.55
2.50
1
2.45
2.40
-60
0
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
5.4
5.6
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
VDD (V)
FIGURE 38-23:
Brown-out Reset Response
Time, PIC16F15356/75/76/85/86 devices only.
2016-2018 Microchip Technology Inc.
FIGURE 38-24:
Brown-out Reset Voltage,
Trip Point (BORV = 00)
DS40001866A-page 548
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
70.0
2.00
Typical
+3 Sigma
60.0
-3 Sigma
1.95
40.0
Voltage (V)
Voltage (mV)
50.0
30.0
1.90
20.0
1.85
+3 Sigma
-3 Sigma
10.0
Typical
1.80
0.0
-60
-40
-20
0
20
40
60
80
100
120
-60
140
-40
-20
0
20
Temperature (°C)
40
60
80
100
120
140
Temperature (°C)
FIGURE 38-25:
Brown-out Reset
Hysteresis, Low-Trip Point (BORV = 00)
FIGURE 38-26:
Brown-out Reset Voltage,
Trip Point (BORV = 01)
40.0
2.60
35.0
2.50
30.0
2.40
+3 Sigma
-3 Sigma
2.30
Voltage (V)
25.0
Voltage (mV)
Typical
20.0
15.0
2.20
2.10
2.00
10.0
Typical
1.90
+3 Sigma
5.0
-3 Sigma
1.80
0.0
-60
-40
-20
0
20
40
60
80
100
120
140
1.70
-60
-40
-20
0
Temperature (°C)
20
40
60
80
100
120
140
Temperature (°C)
FIGURE 38-27:
Brown-out Reset
Hysteresis, Trip Point (BORV = 01)
FIGURE 38-28:
LPBOR Reset Voltage
300
50
Typical 25°C
Typical
45
+3 Sigma 125°C
+3 Sigma
40
250
-3 Sigma
35
200
Time (ns)
Voltage (mV)
30
25
20
15
150
100
10
5
50
0
-60
-40
-20
0
20
40
60
80
100
120
140
0
1.7
Temperature (°C)
FIGURE 38-29:
DS40001866A-page 549
LPBOR Reset Hysteresis
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VDD (V)
FIGURE 38-30:
Comparator Response Time
Falling Edge, PIC16LF15356/75/76/85/86
devices only.
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
700
250
Typical 25°C
Typical 25°C
+3 Sigma 125°C
600
+3 Sigma 125°C
200
150
Time (ns)
Time (ns)
500
400
300
100
200
50
100
0
0
1.7
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VDD (V)
VDD (V)
FIGURE 38-31:
Comparator Response Time
Falling Edge, PIC16F15356/75/76/85/86 devices
only.
FIGURE 38-32:
Comparator Response Time
Rising Edge, PIC16LF15356/75/76/85/86
devices only.
45
900
Typical 25°C
800
43
-40°C
+3 Sigma 125°C
41
Hysteresis (mV)
700
Time (ns)
600
500
400
39
25°C
37
85°C
35
125°
33
300
31
200
29
100
27
0
25
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VDD (V)
Common Mode Voltage (V)
FIGURE 38-34:
Comparator Hysteresis,
Normal Power Mode (CxSP = 1), VDD = 3.0V,
Typical Measured Values
30
30
25
25
20
20
15
15
Offset Voltage (mV)
Offset Voltage (mV)
FIGURE 38-33:
Comparator Response Time
Rising Edge, PIC16F15356/75/76/85/86 devices
only.
10
MAX
5
0
-5
10
MAX
5
0
-5
MIN
MIN
-10
-10
-15
-15
-20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Common Mode Voltage (V)
FIGURE 38-35:
Comparator Offset, Normal
Power Mode (CxSP = 1), VDD = 3.0V, Typical
Measured Values at 25°C.
2016-2018 Microchip Technology Inc.
-20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Common Mode Voltage (V)
FIGURE 38-36:
Comparator Offset, Normal
Power Mode (CxSP = 1), VDD = 3.0V, Typical
Measured Values from -40°C to 125°C.
DS40001866A-page 550
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
30
50
25
20
40
25°C
125°
35
Hysteresis (mV)
Hysteresis (mV)
45
15
MAX
10
5
0
85°
30
-5
-40°C
-10
MIN
25
-15
-20
20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
5.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Common Mode Voltage (V)
Common Mode Voltage (V)
FIGURE 38-37:
Comparator Hysteresis,
Normal Power Mode (CxSP = 1), VDD = 5.5V,
Typical Measured Values, PIC16F15356/75/76/
85/86 devices only.
FIGURE 38-38:
Comparator Offset, Normal
Power Mode (CxSP = 1), VDD = 5.0V, Typical
Measured Values at 25°C, PIC16F15356/75/76/
85/86 devices only.
140
40
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
120
30
Offset Voltage (mV)
100
20
Time (nS)
125°C
MAX
10
80
25°C
60
0
40
-40°C
-10
20
MIN
-20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.7
2.0
2.3
2.6
Common Mode Voltage (V)
2.9
3.2
3.5
VDD (V)
FIGURE 38-39:
Comparator Offset, Normal
Power Mode (CxSP = 1), VDD = 5.5V, Typical
Measured Values from -40°C to 125°C,
PIC16F15356/75/76/85/86 devices only.
90
FIGURE 38-40:
Comparator Response Time
Over Voltage, Normal Power Mode (CxSP = 1),
Typical Measured Values, PIC16LF15356/75/76/
85/86 devices only.
1,400
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
80
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
1,200
70
Time (nS)
Time (nS)
1,000
125°C
60
50
25°C
40
800
125°C
600
30
25°C
400
-40°C
20
200
10
-40°C
0
0
2.2
2.5
2.8
3.1
3.4
3.7
4.0
4.3
4.6
4.9
5.2
5.5
VDD (V)
FIGURE 38-41:
Comparator Response Time
Over Voltage, Normal Power Mode (CxSP = 1),
Typical Measured Values, PIC16F15356/75/76/
85/86 devices only.
DS40001866A-page 551
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDD (V)
FIGURE 38-42:
Comparator Output Filter
Delay Time Over Temperature, Normal Power
Mode (CxSP = 1), Typical Measured Values,
PIC16LF15356/75/76/85/86 devices only.
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
0.025
800
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
700
0.02
0.015
600
DNL (LSb)
Time (nS)
0.01
500
125°C
400
0.005
-40°C
25°C
0
85°C
300
25°C
125°C
-0.005
200
-0.01
100
-40°C
-0.015
0
2.2
2.5
2.8
3.1
3.4
3.7
4
4.3
4.6
4.9
5.2
-0.02
5.5
0
VDD (V)
FIGURE 38-43:
Comparator Output Filter
Delay Time Over Temperature, Normal Power
Mode (CxSP = 1), Typical Measured Values,
PIC16F15356/75/76/85/86 devices only
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
Output Code
FIGURE 38-44:
Typical DAC DNL Error,
VDD = 3.0V, VREF = External 3V
0.45
0.4
0.00
Vref = Int. Vdd
0.4
-0.05
Vref = Ext. 1.8V
Vref = Ext. 2.0V
-0.10
INL (LSb)
-0.15
-0.20
-40°C
25°C
-0.25
85°C
125°C
-0.30
AbsoluteAbsolute
DNL (LSb)
DNL (LSb)
0.35
Vref = Ext. 3.0V
0.3
0.3
0.25
Vref = Int. Vdd
Vref = Ext. 1.8V
0.2
Vref = Ext. 2.0V
0.15
0.2
Vref = Ext. 3.0V
0.1
0.05
0
0.1 -50
-0.35
0
50
Temperature (°C)
100
150
-0.40
-0.45
0.0
0 14 28 42 56 70 84 98 112126140 154168 182196210 224238 252
Output Code
-60
FIGURE 38-45:
Typical DAC INL Error,
VDD = 3.0V, VREF = External 3V
0.90
-2.1
Vref = Int. Vdd
0
20
40
60
Temperature (°C)
80
100
120
140
70
Typical 25°C
Vref = Ext. 2.0V
+3ı (-40°C to +125°C)
60
Vref = Ext. 3.0V
50
-40
-2.7
0.86
25
-2.9
85
0.84
-3.1
125
-3.3
0.82
-3.5
0.0
Time (us)
AbsoluteAbsolute
INL (LSb)INL (LSb)
-2.5
-20
FIGURE 38-46:
Absolute Value of DAC DNL
Error, VDD = 3.0V, VREF= VDD
Vref = Ext. 1.8V
-2.3
0.88
-40
40
30
20
1.0
2.0
3.0
Temperature (°C)
0.80
4.0
5.0
10
Note:
The FVR Stabiliztion Period applies when coming out of
RESET or exiting sleep mode.
0
0.78
-60.0
1.6
-40.0
-20.0
0.0
20.0
40.0
60.0
Temperature (°C)
80.0
100.0
120.0
140.0
FIGURE 38-47:
Absolute Value of DAC INL
Error, VDD = 3.0V, VREF= VDD
2016-2018 Microchip Technology Inc.
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (MV)
FIGURE 38-48:
FVR Stabilization Period,
PIC16LF15356/75/76/85/86 devices only
DS40001866A-page 552
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
1.1%
1.2%
Typical -40°C
Typical 25°C
Typical 85°C
Typical 125°C
1.0%
0.9%
Typical -40°C
Typical 25°C
Typical 85°C
Typical 125°C
1.0%
0.8%
0.8%
Error (%)
Error (%)
0.7%
0.6%
0.5%
0.6%
0.4%
0.4%
0.3%
0.2%
0.2%
0.1%
0.0%
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0.0%
3.7
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDD (V)
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
VDD (V)
FIGURE 38-49:
Typical FVR Voltage 1X,
PIC16F15356/75/76/85/86 devices only
FIGURE 38-50:
FVR Voltage Error 1X,
PIC16F15356/75/76/85/86 devices only
1.0%
1.0%
0.8%
0.8%
0.6%
Error (%)
Error (%)
0.6%
0.4%
0.2%
0.4%
0.2%
0.0%
Typical -40°C
Typical 25°C
Typical 85°C
Typical 125°C
-0.2%
-0.2%
-0.4%
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Typical -40°C
Typical 25°C
Typical 85°C
Typical 125°C
0.0%
2.4
3.7
2.6
2.8
3.0
3.2
3.4
3.6
FIGURE 38-51:
FVR Voltage Error 2X,
PIC16LF15356/75/76/85/86 devices only
1.0%
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
3.0%
2.0%
1.0%
0.6%
0.0%
0.4%
Error (%)
Error (%)
4.0
FIGURE 38-52:
FVR Voltage Error 2X,
PIC16F15356/75/76/85/86 devices only
Typical -40°C
Typical 25°C
Typical 85°C
Typical 125°C
0.8%
3.8
VDD (V)
VDD (V)
0.2%
-1.0%
-2.0%
0.0%
-3.0%
-0.2%
Typical 25°C
+3ı (-40°C to +125°C)
-4.0%
-3ı (-40°C to +125°C)
-5.0%
-0.4%
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
VDD (V)
FIGURE 38-53:
FVR Voltage Error 4X,
PIC16F15356/75/76/85/86 devices only
DS40001866A-page 553
5.6
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 38-54:
HFINTOSC Typical
Frequency Error, PIC16LF15356/75/76/85/86
devices only
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
500
500
Max: 85°C + 3ı
Typical: 25°C
450
Max
400
400
350
Typical
350
Max
300
IDD (µA)
300
IDD (µA)
Max: 85°C + 3ı
Typical: 25°C
450
Typical
250
250
200
200
150
150
100
100
50
50
0
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
VDD (V)
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 38-55:
IDD, XT Oscillator 4 MHz,
PIC16F15356/75/76/85/86 devices only
FIGURE 38-56:
IDD, XT Oscillator 4 MHz,
PIC16F15356/75/76/85/86 devices only
4.0
4.0
3.5
Max: 85°C + 3ı
Typical: 25°C
3.5
Max: 85°C + 3ı
Typical: 25°C
3.0
3.0
Max
2.5
Max
IDD (MA)
IDD (MA)
2.5
2.0
Typical
1.5
2.0
Typical
1.5
1.0
1.0
0.5
0.5
0.0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
1.5
3.8
2.0
2.5
3.0
VDD (V)
4.5
5.0
5.5
6.0
FIGURE 38-58:
IDD, HS Oscillator 32 MHz,
PIC16F15356/75/76/85/86 devices only
4.0
4.0
Max: 85°C + 3ı
Typical: 25°C
3.5
3.0
Max: 85°C + 3ı
Typical: 25°C
Max
3.0
Max
2.5
IDD (MA)
2.5
IDD (MA)
4.0
VDD (V)
FIGURE 38-57:
IDD, HS Oscillator 32 MHz,
PIC16LF15356/75/76/85/86 devices only
3.5
3.5
2.0
Typical
1.5
Typical
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VDD (V)
FIGURE 38-59:
IDD, HFINTOSC Mode,
FOSC = 32 MHz, PIC16LF15356/75/76/85/86
devices only
2016-2018 Microchip Technology Inc.
3.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 38-60:
IDD, HFINTOSC Mode,
FOSC = 32 MHz, PIC16F15356/75/76/85/86
devices only
DS40001866A-page 554
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
2.0
2.0
Max: 85°C + 3ı
Typical: 25°C
1.8
1.8
Max
1.6
1.6
1.4
1.4
Max
Typical-
1.2
1.0
IDD (MA)
1.2
IDD (MA)
Max: 85°C + 3ı
Typical: 25°C
Typical
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.0
3.8
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
VDD (V)
FIGURE 38-61:
IDD, HFINTOSC Mode,
FOSC = 16 MHz, PIC16LF15356/75/76/85/86
devices only
FIGURE 38-62:
IDD, HFINTOSC Mode,
FOSC = 16 MHz, PIC16F15356/75/76/85/86
devices only
1,200
1,200
Max: 85°C + 3ı
Typical: 25°C
Max: 85°C + 3ı
Typical: 25°C
Max
1,000
1,000
Max
800
800
600
IDD (µA)
IDD (µA)
Typical
Typical
600
400
400
200
200
0
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.0
3.8
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
VDD (V)
FIGURE 38-63:
IDD, HFINTOSC Idle Mode,
FOSC = 16 MHz, PIC16LF15356/75/76/85/86
devices only
FIGURE 38-64:
IDD, HFINTOSC Idle Mode,
FOSC = 16 MHz, PIC16F15356/75/76/85/86
devices only
1,200
1,200
Max: 85°C + 3ı
Typical: 25°C
Max: 85°C + 3ı
Typical: 25°C
1,000
Max
1,000
Max
800
IDD (µA)
IDD (µA)
800
Typical
600
600
400
400
200
200
0
Typical
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 38-65:
IDD, HFINTOSC Doze
Mode, FOSC = 16 MHz, PIC16LF15356/75/76/85/
86 devices only
DS40001866A-page 555
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 38-66:
IDD, HFINTOSC Doze
Mode, FOSC = 16 MHz, PIC16F15356/75/76/85/
86 devices only
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
Title
4
Schmitt Trigger Low Values
2.5
Typical 25°C
3.5
+3ı (-40°C to +125°C)
2
-3ı (-40°C to +125°C)
3
2.5
Voltage (V)
Voltage (V)
Typical 25°C
+3ı (-40°C to +125°C)
2
1.5
1
-3ı (-40°C to +125°C)
1.5
1
0.5
0.5
0
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
VDD (V)
FIGURE 38-67:
Schmitt Trigger High Values
FIGURE 38-68:
50
1.8
Typical 25°C
Typical 25°C
1.6
+3ı (-40°C to +125°C)
1.4
-3ı (-40°C to +125°C)
45
+3 Sigma (-40°C to
125°C)
40
35
1.2
Time (ns)
Voltage (V)
Schmitt Trigger Low Values
1
0.8
30
25
20
15
0.6
10
0.4
5
0.2
0
0
1.5
1.5
2.0
2.5
FIGURE 38-69:
Thresholds
3.0
3.5
VDD (V)
4.0
4.5
5.0
Input Level TTL Trip
FIGURE 38-70:
Control Enabled
3.5
VDD (V)
4.5
Typical 25°C
Typical 25°C
+3 Sigma (-40°C to
125°C)
50
5.5
Rise Time, Slew Rate
30
60
+3 Sigma (-40°C to
125°C)
25
20
Time (ns)
40
Time (ns)
2.5
5.5
30
15
20
10
10
5
0
0
1.5
2.5
FIGURE 38-71:
Enabled
3.5
VDD (V)
4.5
5.5
Fall Time, Slew Rate Control
2016-2018 Microchip Technology Inc.
1.5
2.5
FIGURE 38-72:
Control Disabled
3.5
VDD (V)
4.5
5.5
Rise Time, Slew Rate
DS40001866A-page 556
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
600
20
Typical 25°C
18
+3 Sigma (-40°C to
125°C)
16
14
IPD (nA)
400
12
Time (ns)
Max.
Max: 85°C + 3ı
Typical: 25°C
500
10
300
8
200
6
4
Typical
100
2
0
1.5
2.5
3.5
VDD (V)
4.5
0
5.5
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 38-73:
Control Disabled
Rise Time, Slew Rate
FIGURE 38-74:
IPD Base, Low-Power Sleep
Mode, PIC16LF15356/75/76/85/86 devices only
1.0
1.4
Max: 85°C + 3ı
Typical: 25°C
0.9
Max: 85°C + 3ı
Typical: 25°C
1.2
Max.
0.8
Max.
0.7
1.0
IPD (µA)
IPD (µA)
0.6
Typical
0.5
Typical
0.8
0.4
0.6
0.3
0.2
0.4
0.1
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
0.2
3.8
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 38-75:
IPD, Watchdog Timer
(WDT), PIC16LF15356/75/76/85/86 devices only
FIGURE 38-76:
IPD, Watchdog Timer
(WDT), PIC16F15356/75/76/85/86 devices only
60
60
Max: 85°C + 3ı
Typical: 25°C
55
Max: 85°C + 3ı
Typical: 25°C
55
50
50
45
40
IPD (µA)
IPD (µA)
45
40
Max.
35
30
35
Max.
Typical
25
30
20
Typical
25
15
10
20
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 38-77:
IPD, Fixed Voltage
Reference (FVR), PIC16LF15356/75/76/85/86
devices only
DS40001866A-page 557
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 38-78:
IPD, Fixed Voltage
Reference (FVR), PIC16F15356/75/76/85/86
devices only
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
14
16
Max: 85°C + 3ı
Typical: 25°C
13
14
12
12
IPD (µA)
IPD (µA)
Max: 85°C + 3ı
Typical: 25°C
11
10
Typical
10
8
Typical
9
6
4
8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.0
3.8
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 38-79:
IPD, Brown-out Reset
(BOR), BORV = 1, PIC16LF15356/75/76/85/86
devices only
FIGURE 38-80:
IPD, Brown-out Reset
(BOR), BORV = 1, PIC16F15356/75/76/85/86
devices only
1.2
1.4
Max: 85°C + 3ı
Typical: 25°C
1
Max.
Max: 85°C + 3ı
Typical: 25°C
1.2
Max.
1.0
IPD (µA)
IPD (nA)
0.8
0.6
0.8
0.6
Typical
0.4
0.4
0.2
0.2
Typical
0
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
VDD (V)
FIGURE 38-81:
IPD, Low-Power Brown-out
Reset (LPBOR = 0), PIC16LF15356/75/76/85/86
devices only
FIGURE 38-82:
IPD, Low-Power Brown-out
Reset (LPBOR = 0), PIC16F15356/75/76/85/86
devices only
40
40
Max: 85°C + 3ı
Typical: 25°C
38
Max: 85°C + 3ı
Typical: 25°C
39
38
36
Max.
37
Max.
36
IPD (µA)
IPD (µA)
34
32
Typical
35
34
30
Typical
33
28
32
26
31
24
30
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
VDD (V)
FIGURE 38-83:
IPD, Comparator,
PIC16LF15356/75/76/85/86 devices only
2016-2018 Microchip Technology Inc.
3.6
3.8
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 38-84:
IPD, Comparator,
PIC16F15356/75/76/85/86 devices only
DS40001866A-page 558
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
30
1
Max: 85°C + 3ı
Typical: 25°C
25
Max.
0.9
Max.
Max: 85°C + 3ı
Typical: 25°C
0.8
0.7
IPD (µA)
IPD (µA)
20
Typical
15
0.6
Typical
0.5
0.4
10
0.3
0.2
5
0.1
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
VDD (V)
4.0
4.5
5.5
6.0
VDD (V)
FIGURE 38-85:
Ipd Base, 01, PIC16F15356/
75/76/85/86 devices only
FIGURE 38-86:
Ipd Base, 11, PIC16F15356/
75/76/85/86 devices only
36,000
36,000
Typical 25°C
Typical 25°C
+3 Sigma (-40°C to 125°C)
35,000
+3 Sigma (-40°C to 125°C)
35,000
-3 Sigma (-40°C to 125°C)
-3 Sigma (-40°C to 125°C)
34,000
34,000
33,000
Frequency (Hz)
33,000
Frequency (Hz)
5.0
32,000
31,000
32,000
31,000
30,000
30,000
29,000
29,000
28,000
28,000
2.2 2.4 2.6 2.8
1.7
2.0
2.3
2.6
2.9
3.2
3
3.2 3.4 3.6 3.8
3.5
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6
VDD (V)
VDD (V)
FIGURE 38-87:
LFINTOSC Frequency,
PIC16LF15356/75/76/85/86 devices only
FIGURE 38-88:
LFINTOSC Frequency,
PIC16F15356/75/76/85/86 devices only
4.00%
1.6
Max: Typical + 3ı (-40°C to +125°C)
Typical; statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
1.55
2.00%
1.5
1.00%
1.45
Voltage (V)
Error (%)
3.00%
0.00%
-1.00%
+3 Sigma
Typical
1.4
1.35
-2.00%
-3 Sigma
1.3
Max
1.25
Min
-3.00%
Average
1.2
-4.00%
-32
Min
-24
-16
-8
Center
0
8
16
24
Max
32
-60
-40
-20
FIGURE 38-89:
OCSTUNE Center
Frequency, PIC16(L)F15356/75/76/85/86
devices only
DS40001866A-page 559
0
20
40
60
80
100
120
140
Temperature (°C)
OSCTUNE Setting
FIGURE 38-90:
Voltage
Power-on Reset Release
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
1.64
1.8
Max: Typical + 3ı
Typical: 25°C
Min: Typical - 3ı
1.63
1.75
74.0
72.0
+3 Sigma
1.7
1.61
70.0
Time (ms)
Voltage
Voltage
(V) (V)
1.62
Typical
1.6
1.65
1.59
1.6
1.58
-40
-20
0
20
1.55
66.0
64.0
-3 Sigma
60
40
68.0
80
100
120
Typical 25°C
+ 3ı (-40°C to +125°C)
- 3ı (-40°C to +125°C)
62.0
Temperature (°C)
60.0
1.5
-60
-40
-20
0
20
40
60
80
100
120
2.0
140
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
Temperature (°C)
FIGURE 38-91:
Power-on Reset Rearm
Voltage, Normal Power Mode, PIC16(L)F15356/
75/76/85/86 devices only
FIGURE 38-92:
PWRT Period,
PIC16F15356/75/76/85/86 devices only
6
Graph represents 3ı Limits
75.0
5
73.0
-40°C
71.0
4
Typical
VOH (V)
Time (ms)
69.0
67.0
3
125°C
65.0
2
63.0
61.0
1
Typical 25°C
+ 3ı (-40°C to +125°C)
- 3ı (-40°C to +125°C)
59.0
57.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
0
3.8
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
VDD (V)
IOH (mA)
FIGURE 38-93:
PWRT Period,
PIC16LF15356/75/76/85/86 devices only
FIGURE 38-94:
VOH Vs. IOH Over
Temperature, VDD = 5.5V, PIC16F15356/75/76/
85/86 devices only
3.5
3
Graph represents 3ı Limits
Graph represents 3ı Limits
3.0
2.5
VOL (V)
VOH (V)
2
-40°C
2.0
Typical
125°C
1.5
125°C
1
Typical
1.0
-40°C
0.5
0.0
0
0
10
20
30
IOL (mA)
40
50
60
FIGURE 38-95:
VOL Vs. IOL Over
Temperature, VDD = 5.5V, PIC16F15356/75/76/
85/86 devices only
2016-2018 Microchip Technology Inc.
-30
-25
-20
-15
-10
-5
0
IOH (mA)
FIGURE 38-96:
VOH Vs. IOH Over
Temperature, VDD = 3.0V
DS40001866A-page 560
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
3.0
2.0
Graph represents 3ı Limits
1.8
Graph represents 3ı Limits
2.5
1.6
1.4
Typical
1.5
-40°C
VOH (V)
VOL (V)
2.0
125°C
1.2
125°C
1.0
Typical
0.8
1.0
0.6
-40°C
0.4
0.5
0.2
0.0
0.0
0
5
10
15
20
25
30
35
40
45
50
55
-8
60
-7.5
-7
-6.5
-6
-5.5
-5
IOL (mA)
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
IOH (mA)
FIGURE 38-97:
VOL Vs. IOL Over
Temperature, VDD = 3.0V
FIGURE 38-98:
VOH Vs. IOH Over
Temperature, VDD = 1.8V, PIC16LF15356/75/76/
85/86 devices only
1.8
18
Graph represents 3ı Limits
1.6
Typical 25°C
+3ı (-40°C to +125°C)
17
1.4
1.2
Typical
16
-40°C
Time (us)
VOL (V)
125°C
1
0.8
15
0.6
14
0.4
13
0.2
12
0
0
1
2
3
4
5
6
7
8
9
1.5
10 11 12 13 14 15 16 17 18 19 20
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
IOL (mA)
FIGURE 38-99:
VOL Vs. IOL Over
Temperature, VDD = 3.0V, PIC16F15356/75/76/
85/86 devices only
FIGURE 38-100:
Wake From Sleep,
VREGPM = 0, HFINTOSC = 4 MHz,
PIC16F15356/75/76/85/86 devices only
28
120
Typical 25°C
Typical 25°C
110
27
+3ı (-40°C to +125°C)
+3ı (-40°C to +125°C)
100
26
25
80
Time (us)
Time (us)
90
70
60
24
23
50
22
40
21
30
20
20
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (V)
FIGURE 38-101:
Wake from Sleep,
VREGPM = 1, HFINTOSC = 4 MHz,
PIC16F15356/75/76/85/86 devices only
DS40001866A-page 561
5.5
6.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 38-102:
Wake from Sleep,
VREGPM = 1, HFINTOSC = 16 MHZ,
PIC16F15356/75/76/85/86 devices only
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
700
Typical 25°C
+3ı (-40°C to +125°C)
Typical 25°C
110
650
100
600
90
550
Time (us)
Time (us)
120
80
+ 3ı (-40°C to +125°C)
500
450
70
400
60
350
50
300
40
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
6.0
VDD (V)
VDD (V)
FIGURE 38-103:
Wake from Sleep,
VREGPM = 1, HFINTOSC = 16 MHz,
PIC16F15356/75/76/85/86 devices only
FIGURE 38-104:
Wake from Sleep,
VREGPM = 1, PIC16F15356/75/76/85/86
devices only
700
700
Typical 25°C
650
600
600
550
550
Time (us)
Time (us)
Typical 25°C
+ 3ı (-40°C to +125°C)
650
500
+ 3ı (-40°C to +125°C)
500
450
450
400
400
350
350
300
300
1.7
2.2
2.7
3.2
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
3.7
VDD (V)
VDD (V)
FIGURE 38-105:
Wake from Sleep,
PIC16LF15356/75/76/85/86 devices only
FIGURE 38-106:
Wake from Sleep,
VREGPM = 1, LFINTOSC, PIC16F15356/75/76/
85/86 devices only
700
4.2
Typical 25°C
+ 3ı (-40°C to +125°C)
650
600
4.1
Time (ms)
Time (us)
550
500
450
4.0
3.9
400
Typical 25°C
+3ı (-40°C to +125°C)
-3ı (-40°C to +125°C)
350
3.8
300
1.7
2.2
2.7
3.2
3.7
VDD (V)
FIGURE 38-107:
Wake from Sleep,
LFINTOSC, PIC16LF15356/75/76/85/86 devices
only
2016-2018 Microchip Technology Inc.
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 38-108:
Watchdog Timer Time-out
Period, PIC16F15356/75/76/85/86 devices only
DS40001866A-page 562
PIC16(L)F15356/75/76/85/86
Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.
300.0
4.2
Typical 25°C
+ 3ı (-40°C to +125°C)
Pull-Up Current (uA)
250.0
Time (ms)
4.1
4.0
- 3ı (-40°C to +125°C)
200.0
150.0
100.0
3.9
50.0
Typical 25°C
+3ı (-40°C to +125°C)
-3ı (-40°C to +125°C)
3.8
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
2.1
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
5.7
VDD (V)
VDD (V)
FIGURE 38-109:
Watchdog Timer Time-out
Period, PIC16LF15356/75/76/85/86 devices only
FIGURE 38-110:
Weak Pull-up Current,
PIC16F15356/75/76/85/86 devices only
180.0
-3.450
+ 3ı (-40°C to +125°C)
140.0
- 3ı (-40°C to +125°C)
-3.500
Typical
-3.550
+3 Sigma
120.0
-3.600
Slope (mV/C)
Pull-Up Current (uA)
Typical 25°C
160.0
100.0
80.0
60.0
-3 Sigma
-3.650
-3.700
-3.750
40.0
-3.800
20.0
-3.850
-3.900
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (oC)
VDD (V)
FIGURE 38-111:
Weak Pull-up Current,
PIC16LF15356/75/76/85/86 devices only
FIGURE 38-112:
High Range Temperature
Indicator Voltage Sensitivity Across Temperature
-2.300
-2.350
Typical
+3 Sigma
Slope (mV/C)
-2.400
-3 Sigma
-2.450
-2.500
-2.550
-2.600
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (oC)
FIGURE 38-113:
Low Range Temperature
Indicator Voltage Sensitivity Across Temperature
DS40001866A-page 563
2016-2018 Microchip Technology Inc.
PIC16(L)F15356/75/76/85/86
39.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
- MPLAB® XPRESS IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
39.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2016-2018 Microchip Technology Inc.
DS40001866B-page 564
PIC16(L)F15356/75/76/85/86
39.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
39.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
39.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
39.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
2016-2018 Microchip Technology Inc.
DS40001866B-page 565
PIC16(L)F15356/75/76/85/86
39.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
39.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE
offers significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2016-2018 Microchip Technology Inc.
39.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
39.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
39.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS40001866B-page 566
PIC16(L)F15356/75/76/85/86
39.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
39.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2016-2018 Microchip Technology Inc.
DS40001866B-page 567
PIC16(L)F15356/75/76/85/86
40.0
40.1
PACKAGING INFORMATION
Package Marking Information
28-Lead SPDIP (.300”)
Example
PIC16F15356
/SP e3
1525017
28-Lead SOIC (7.50 mm)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP (5.30 mm)
Example
PIC16LF15356
/SO e3
1525017
Example
PIC16F15356
/SS e3
1525017
Legend: XX...X
Y
YY
WW
NNN
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2018 Microchip Technology Inc.
DS40001866B-page 568
PIC16(L)F15356/75/76/85/86
40.1
Package Marking Information (Continued)
28-Lead UQFN (4x4x0.5 mm) and 28-Lead QFN (6x6 mm)
PIN 1
PIN 1
Example
PIC16
F15356
/MV
e3
525017
Legend: XX...X
Y
YY
WW
NNN
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2018 Microchip Technology Inc.
DS40001866B-page 569
PIC16(L)F15356/75/76/85/86
40.1
Package Marking Information (Continued)
40-Lead PDIP (600 mil)
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F15375
/P e3
1525017
40-Lead UQFN (5x5x0.5 mm)
PIN 1
Example
PIN 1
PIC16
LF15375
/MV e
1525017
3
28-Lead QFN (6x6 mm)
PIN 1
Example
PIN 1
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
*
Note:
PIC16
LF15375
/MV
1525017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2018 Microchip Technology Inc.
DS40001866B-page 570
PIC16(L)F15356/75/76/85/86
40.1
Package Marking Information (Continued)
Example
44-Lead TQFP (10x10x1 mm)
16F15376
/PT e3
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
1525017
44-Lead QFN (8x8x0.9 mm)
PIN 1
Example
PIN 1
16LF15376
/ML
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
*
Note:
1525017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2018 Microchip Technology Inc.
DS40001866B-page 571
PIC16(L)F15356/75/76/85/86
40.1
Package Marking Information (Continued)
48-Lead UQFN (6x6x0.5 mm)
PIN 1
Example
PIN 1
XXXXXXXX
XXXXXXXX
YYWWNNN
16F15386
/MV e3
1525017
48-Lead TQFP (7x7x1 mm)
Example
XXXXXXX
XXXYYWW
NNN
16F15386
/PT1525 e3
017
Legend: XX...X
Y
YY
WW
NNN
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2018 Microchip Technology Inc.
DS40001866B-page 572
PIC16(L)F15356/75/76/85/86
The following sections give the technical details of the packages.
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2016-2018 Microchip Technology Inc.
DS40001866B-page 573
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 574
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 575
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 576
PIC16(L)F15356/75/76/85/86
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2016-2018 Microchip Technology Inc.
DS40001866B-page 577
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 578
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 579
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 580
PIC16(L)F15356/75/76/85/86
2016-2018 Microchip Technology Inc.
DS40001866B-page 581
PIC16(L)F15356/75/76/85/86
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2016-2018 Microchip Technology Inc.
DS40001866B-page 582
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 583
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 584
PIC16(L)F15356/75/76/85/86
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS40001866B-page 585
PIC16(L)F15356/75/76/85/86
2016-2018 Microchip Technology Inc.
DS40001866B-page 586
PIC16(L)F15356/75/76/85/86
2016-2018 Microchip Technology Inc.
DS40001866B-page 587
PIC16(L)F15356/75/76/85/86
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