PIC16F1823T-I/SL

PIC12(L)F1822/16(L)F1823 8/14-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 32 MHz oscillator/clock input - DC – 125 ns instruction cycle • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory Flexible Oscillator Structure • Precision 32 MHz internal Oscillator Block: - Factory calibrated to ± 1%, typical - Software selectable frequencies range of 31 kHz to 32 MHz • 31 kHz Low-Power Internal Oscillator • Four Crystal modes up to 32 MHz • Three External Clock modes up to 32 MHz • 4X Phase Lock Loop (PLL) • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops • Two-Speed Oscillator Start-up • Reference Clock module: - Programmable clock output frequency and duty-cycle Special Microcontroller Features • • • • • • • • • • • • Full 5.5V Operation – PIC12F1822/16F1823 1.8V-3.6V Operation – PIC12LF1822/16LF1823 Self-Reprogrammable under Software Control Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Programmable Brown-out Reset (BOR) Extended Watchdog Timer (WDT) In-Circuit Serial Programming™ (ICSP™) via Two Pins In-Circuit Debug (ICD) via Two Pins Enhanced Low-Voltage Programming (LVP) Operating Voltage Range: - 1.8V-5.5V (PIC12F1822/16F1823) - 1.8V-3.6V (PIC12LF1822/16LF1823) Programmable Code Protection Self-Programmable under Software Control  2010-2015 Microchip Technology Inc. Extreme Low-Power Management PIC12LF1822/16LF1823 with XLP • • • • Sleep mode: 20 nA @ 1.8V, typical Watchdog Timer: 300 nA @ 1.8V, typical Timer1 Oscillator: 650 nA @ 32 kHz, typical Operating Current: 30 µA/MHz @ 1.8V, typical Analog Features • Analog-to-Digital Converter (ADC) module: - 10-bit resolution, up to 8 channels - Conversion available during Sleep • Analog Comparator module: - Up to two rail-to-rail analog comparators - Power mode control - Software controllable hysteresis • Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection Peripheral Highlights • Up to 11 I/O Pins and 1 Input-Only Pin: - High current sink/source 25 mA/25 mA - Programmable weak pull-ups - Programmable interrupt-on-change pins • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated, low-power 32 kHz oscillator driver • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Enhanced CCP (ECCP) modules: - Software selectable time bases - Auto-shutdown and auto-restart - PWM steering • Master Synchronous Serial Port (MSSP) with SPI and I2CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility • Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module: - RS-232, RS-485 and LIN compatible - Auto-Baud Detect • Capacitive Sensing (CPS) module (mTouch™): - Up to 8 input channels DS40001413E-page 1 PIC12(L)F1822/16(L)F1823 Peripheral Features (Continued) • Data Signal Modulator module - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications Data EEPROM (bytes) Data SRAM (bytes) I/O’s(2) 10-bit ADC (ch) CapSense (ch) Comparators Timers (8/16-bit) EUSART MSSP (I2C™/SPI) ECCP (Full-Bridge) ECCP (Half-Bridge) CCP Debug(1) XLP PIC12(L)F1822 (1) 2K 256 128 6 4 4 1 2/1 1 1 0/1/0 Y I/H Y PIC12(L)F1840 (2) 4K 256 256 6 4 4 1 2/1 1 1 0/1/0 Y I/H Y PIC16(L)F1823 (1) 2K 256 128 12 8 8 2 2/1 1 1 1/0/0 Y I/H Y PIC16(L)F1824 (3) 4K 256 256 12 8 8 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1825 (4) 8K 256 1024 12 8 8 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1826 (5) 2K 256 256 16 12 12 2 2/1 1 1 1/0/0 Y I/H Y PIC16(L)F1827 (5) 4K 256 384 16 12 12 2 4/1 1 2 1/1/2 Y I/H Y PIC16(L)F1828 (3) 4K 256 256 18 12 12 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1829 (4) 8K 256 1024 18 12 12 2 4/1 1 2 1/1/2 Y I/H Y PIC16(L)F1847 (6) 8K 256 1024 16 12 12 2 4/1 1 2 1/1/2 Y I/H Y SR Latch Device Program Memory Flash (words) PIC12(L)F1822/1840/PIC16(L)F182X/1847 FAMILY TYPES Data Sheet Index TABLE 1: Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41413 PIC12(L)F1822/PIC16(L)F1823 Data Sheet, 8/14-Pin Flash Microcontrollers. 2: DS41441 PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers. 3: DS41419 PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers. 4: DS41440 PIC16(L)F1825/1829 Data Sheet, 14/20-Pin Flash Microcontrollers. 5: DS41391 PIC16(L)F1826/1827 Data Sheet, 18/20/28-Pin Flash Microcontrollers. 6: DS41453 PIC16(L)F1847 Data Sheet, 18/20/28-Pin Flash Microcontrollers. Note: For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. DS40001413E-page 2  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 1: 8-PIN DIAGRAM FOR PIC12(L)F1822 VDD 1 RA5 RA4 2 3 4 MCLR/VPP/RA3 8 7 6 5 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 — RA3 4 — — — RA4 3 AN3 — RA5 2 — — VDD 1 — — — — — — — — — — VSS 8 — — — — — — — — — — C1IN+ — — P1B(1) TX(1) CK(1) SDO(1) SS(1) IOC MDOUT Y ICSPDAT ICDDAT C1IN0- SRI — — RX(1) DT(1) SCL SCK IOC MDMIN Y ICSPCLK ICPCLK CPS2 C1OUT SRQ T0CKI CCP1(1) P1A(1) FLT0 — SDA SDI INT/ IOC MDCIN1 Y — — — T1G(1) — — SS(1) IOC — Y MCLR VPP CPS3 C1IN1- — T1G(1) T1OSO P1B(1) TX(1) CK(1) SDO(1) IOC MDCIN2 Y OSC2 CLKOUT CLKR — — SRNQ T1CKI T1OSI CCP1(1) P1A(1) RX(1) DT(1) — IOC — Y OSC1 CLKIN — — VDD — — VSS Cap Sense Basic AN2 Pull-up 5 Modulator RA2 Interrupt VREF+ MSSP AN1 EUSART 6 ECCP RA1 Timers AN0 SR Latch 7 Comparator A/D RA0 Reference 8-Pin PDIP/SOIC/DFN/UDFN 8-PIN ALLOCATION TABLE (PIC12(L)F1822) I/O TABLE 2: PIC12(L)F1822 PDIP, SOIC, DFN, UDFN DACOUT CPS0 CPS1 Note 1: Pin function is selectable via the APFCON register.  2010-2015 Microchip Technology Inc. DS40001413E-page 3 PIC12(L)F1822/16(L)F1823 FIGURE 2: 14-PIN DIAGRAM FOR PIC16(L)F1823 PDIP, SOIC, TSSOP FIGURE 3: 1 RA5 2 RA4 3 MCLR/VPP/RA3 4 RC5 5 RC4 6 RC3 7 PIC16(L)F1823 VDD 14 VSS 13 RA0/ICSPDAT 12 RA1/ICSPCLK 11 RA2 10 RC0 9 RC1 8 RC2 16-PIN DIAGRAM FOR PIC16(L)F1823 RA4 2 VDD NC NC VSS 15 14 13 RA5 1 16 QFN, UQFN 11 RA1/ICSPCLK PIC16(L)F1823 RC1 8 9 RC0 RC2 7 RC5 4 RC3 6 10 RA2 5 MCLR/VPP/RA3 3 RC4 DS40001413E-page 4 12 RA0/ICSPDAT  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 14-PIN ALLOCATION TABLE (PIC16(L)F1823) Cap Sense Comparator SR Latch Timers ECCP MSSP Interrupt Modulator Pull-up Basic 13 12 AN0 DACOUT CPS0 C1IN+ — — — TX(1) CK(1) — IOC — Y ICSPDAT ICDDAT RA1 12 11 AN1 VREF+ CPS1 C12IN0- SRI — — RX(1) DT(1) — IOC — Y ICSPCLK ICDCLK RA2 11 10 AN2 — CPS2 C1OUT SRQ T0CKI FLT0 — — INT/ IOC — Y — RA3 4 3 — — — — — T1G(1) — — SS(1) IOC — Y MCLR VPP RA4 3 2 AN3 — CPS3 — — T1G(1) T1OSO — SDO(1) IOC — Y OSC2 CLKOUT CLKR RA5 2 1 — — — — — T1CKI T1OSI — — — IOC — Y OSC1 CLKIN RC0 10 9 AN4 — CPS4 C2IN+ — — — — SCL SCK — — Y — RC1 9 8 AN5 — CPS5 C12IN1- — — — — SDA SDI — — Y — RC2 8 7 AN6 — CPS6 C12IN2- — — P1D — SDO(1) — MDCIN1 Y — RC3 7 6 AN7 — CPS7 C12IN3- — — P1C — SS(1) — MDMIN Y — RC4 6 5 — — — C2OUT SRNQ — P1B TX(1) CK(1) — — MDOUT Y — RC5 5 4 — — — — — — CCP1 P1A RX(1) DT(1) — — MDCIN2 Y — VDD 1 16 — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — VSS Note 1: EUSART Reference RA0 I/O A/D 16-Pin QFN/UQFN 14-Pin PDIP/SOIC/TSSOP TABLE 3: Pin function is selectable via the APFCON register.  2010-2015 Microchip Technology Inc. DS40001413E-page 5 PIC12(L)F1822/16(L)F1823 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 8 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15 3.0 Memory Organization ................................................................................................................................................................. 17 4.0 Device Configuration .................................................................................................................................................................. 45 5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51 6.0 Reference Clock Module ............................................................................................................................................................ 68 7.0 Resets ........................................................................................................................................................................................ 71 8.0 Interrupts .................................................................................................................................................................................... 80 9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 92 10.0 Watchdog Timer ......................................................................................................................................................................... 95 11.0 Data EEPROM and Flash Program Memory Control ................................................................................................................. 98 12.0 I/O Ports ................................................................................................................................................................................... 112 13.0 Interrupt-On-Change ................................................................................................................................................................ 123 14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 127 15.0 Temperature Indicator Module ................................................................................................................................................. 129 16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 130 17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 143 18.0 SR Latch................................................................................................................................................................................... 147 19.0 Comparator Module.................................................................................................................................................................. 152 20.0 Timer0 Module ......................................................................................................................................................................... 162 21.0 Timer1 Module with Gate Control............................................................................................................................................. 165 22.0 Timer2 Module ......................................................................................................................................................................... 176 23.0 Data Signal Modulator .............................................................................................................................................................. 180 24.0 Capture/Compare/PWM Modules ............................................................................................................................................ 190 25.0 Master Synchronous Serial Port Module .................................................................................................................................. 217 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 268 27.0 Capacitive Sensing (CPS) Module ........................................................................................................................................... 296 28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 305 29.0 Instruction Set Summary .......................................................................................................................................................... 308 30.0 Electrical Specifications............................................................................................................................................................ 322 31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 359 32.0 Development Support............................................................................................................................................................... 387 33.0 Packaging Information.............................................................................................................................................................. 391 Appendix A: Data Sheet Revision History.......................................................................................................................................... 418 Appendix B: Migrating From Other PIC® Devices ............................................................................................................................. 418 The Microchip Web Site ..................................................................................................................................................................... 419 Customer Change Notification Service .............................................................................................................................................. 419 Customer Support .............................................................................................................................................................................. 419 Product Identification System............................................................................................................................................................. 420 DS40001413E-page 6  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010-2015 Microchip Technology Inc. DS40001413E-page 7 PIC12(L)F1822/16(L)F1823 1.0 DEVICE OVERVIEW The PIC12(L)F1822/16(L)F1823 are described within this data sheet. They are available in 8/14 pin packages. Figure 1-1 shows a block diagram of the PIC12(L)F1822/16(L)F1823 devices. Tables 1-2 and 1-3 show the pinout descriptions. Reference Table 1-1 for peripherals available per device. Peripheral PIC16(L)F1823 DEVICE PERIPHERAL SUMMARY PIC12(L)F1822 TABLE 1-1: ADC ● ● Capacitive Sensing (CPS) Module ● ● Data EEPROM ● ● Digital-to-Analog Converter (DAC) ● ● Digital Signal Modulator (DSM) ● ● EUSART ● ● Fixed Voltage Reference (FVR) ● ● SR Latch ● ● ECCP1 ● ● C1 ● ● Capture/Compare/PWM Modules Comparators C2 ● Master Synchronous Serial Ports MSSP ● ● Timer0 ● ● Timer1 ● ● Timer2 ● ● Timers DS40001413E-page 8  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 1-1: PIC12(L)F1822/16(L)F1823 BLOCK DIAGRAM Program Flash Memory CLKR RAM EEPROM Clock Reference OSC2/CLKOUT Timing Generation OSC1/CLKIN INTRC Oscillator PORTA CPU (Figure 2-1) PORTC(3) MCLR Note 1: 2: 3: SR Latch Timer0 Timer1 ADC 10-Bit DAC Comparators ECCP1 MSSP Modulator EUSART FVR CapSense See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 9 PIC12(L)F1822/16(L)F1823 TABLE 1-2: PIC12(L)F1822 PINOUT DESCRIPTION Name Function Input Type RA0/AN0/CPS0/C1IN+/ DACOUT/TX(1)/CK(1)/SDO(1)/ SS(1)/P1B(1)/MDOUT/ICSPDAT/ ICDDAT RA0 TTL AN0 AN RA1/AN1/CPS1/VREF+/C1IN0-/ SRI/RX(1)/DT(1)/SCL/SCK/ MDMIN/ICSPCLK/ICDCLK RA2/AN2/CPS2/C1OUT/SRQ/ T0CKI/CCP1(1)/P1A(1)/FLT0/ SDA/SDI/INT/MDCIN1 RA3/SS(1)/T1G(1)/VPP/MCLR Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0. C1IN+ AN — Comparator C1 positive input. DACOUT — AN Digital-to-Analog Converter output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. SDO — CMOS SPI data output. SS ST P1B — — Slave Select input. CMOS PWM output. MDOUT — CMOS Modulator output. ICSPDAT ST CMOS ICSP™ Data I/O. RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. CPS1 AN — Capacitive sensing input 1. VREF+ AN — A/D and DAC Positive Voltage Reference input. C1IN0- AN — Comparator C1 or C2 negative input. SRI ST — SR latch input. — USART asynchronous input. RX ST DT ST SCL I2C™ SCK ST CMOS USART synchronous data. OD I2C™ clock. CMOS SPI clock. MDMIN ST — Modulator source input. ICSPCLK ST — Serial Programming Clock. RA2 ST AN2 AN CMOS General purpose I/O. CPS2 AN C1OUT — CMOS Comparator C1 output. CMOS SR latch non-inverting output. — A/D Channel 2 input. — Capacitive sensing input 2. SRQ — T0CKI ST CCP1 ST CMOS Capture/Compare/PWM 1. P1A — CMOS PWM output. FLT0 ST — ECCP Auto-Shutdown Fault input. SDA I2C™ OD I2C™ data input/output. SDI CMOS — SPI data input. INT ST — External interrupt. MDCIN1 ST — Modulator Carrier Input 1. RA3 TTL — General purpose input. — Timer0 clock input. SS ST — Slave Select input. T1G ST — Timer1 Gate input. VPP HV — Programming voltage. MCLR ST — Master Clear with internal pull-up. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1). DS40001413E-page 10  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 1-2: PIC12(L)F1822 PINOUT DESCRIPTION (CONTINUED) Name Function Input Type RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/C1IN1-/CLKR/ SDO(1)/CK(1)/TX(1)/P1B(1)/ T1G(1)/MDCIN2 RA4 TTL Output Type Description CMOS General purpose I/O. AN3 AN — CPS3 AN — A/D Channel 3 input. OSC2 XTAL XTAL CLKOUT — T1OSO XTAL XTAL C1IN1- AN — CLKR — CMOS Clock Reference output. SDO — CMOS SPI data output. CK ST CMOS USART synchronous clock. TX — CMOS USART asynchronous transmit. P1B — CMOS PWM output. T1G ST Capacitive sensing input 3. Crystal/Resonator (LP, XT, HS modes). CMOS FOSC/4 output. Timer1 oscillator connection. Comparator C1 negative input. — Timer1 Gate input. — Modulator Carrier Input 2. MDCIN2 ST RA5 TTL CLKIN CMOS — External clock input (EC mode). OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). T1OSI XTAL XTAL T1CKI ST — SRNQ — CMOS SR latch inverting output. P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM 1. DT ST CMOS USART synchronous data. RX ST — USART asynchronous input. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. RA5/CLKIN/OSC1/T1OSI/ T1CKI/SRNQ/P1A(1)/CCP1(1)/ DT(1)/RX(1) CMOS General purpose I/O. Timer1 oscillator connection. Timer1 clock input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).  2010-2015 Microchip Technology Inc. DS40001413E-page 11 PIC12(L)F1822/16(L)F1823 TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION Name Function Input Type RA0/AN0/CPS0/C1IN+/ DACOUT/TX(1)/CK(1)/ICSPDAT/ ICDDAT RA0 TTL AN0 AN RA1/AN1/CPS1/C12IN0-/VREF+/ SRI/RX(1)/DT(1)/ICSPCLK/ ICDCLK RA2/AN2/CPS2/T0CKI/INT/ C1OUT/SRQ/FLT0 RA3/SS(1)/T1G(1)/VPP/MCLR RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/CLKR/SDO(1)/ T1G(1) Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0. C1IN+ AN — Comparator C1 positive input. DACOUT — AN Digital-to-Analog Converter output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. ICSPDAT ST CMOS ICSP™ Data I/O. RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. CPS1 AN — Capacitive sensing input 1. C12IN0- AN — Comparator C1 or C2 negative input. VREF+ AN — A/D and DAC Positive Voltage Reference input. SRI ST — SR latch input. — USART asynchronous input. RX ST DT ST ICSPCLK ST RA2 ST CMOS USART synchronous data. — Serial Programming Clock. CMOS General purpose I/O. AN2 AN — CPS2 AN — A/D Channel 2 input. Capacitive sensing input 2. T0CKI ST — Timer0 clock input. INT ST — External interrupt. C1OUT — CMOS Comparator C1 output. SRQ — CMOS SR latch non-inverting output. FLT0 ST — ECCP Auto-Shutdown Fault input. RA3 TTL — General purpose input. SS ST — Slave Select input. T1G ST — Timer1 Gate input. VPP HV — Programming voltage. MCLR ST — Master Clear with internal pull-up. RA4 TTL AN3 AN — CPS3 AN — OSC2 XTAL XTAL CMOS General purpose I/O. A/D Channel 3 input. Capacitive sensing input 3. Crystal/Resonator (LP, XT, HS modes). CMOS FOSC/4 output. CLKOUT — T1OSO XTAL CLKR — CMOS Clock Reference output. SDO — CMOS SPI data output. T1G ST XTAL — Timer1 oscillator connection. Timer1 Gate input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1). DS40001413E-page 12  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION (CONTINUED) Name Function Input Type RA5/CLKIN/OSC1/T1OSI/T1CKI RA5 TTL CLKIN CMOS — OSC1 XTAL — T1OSI XTAL XTAL T1CKI ST — RC0 TTL AN4 AN RC0/AN4/CPS4/C2IN+/SCL/ SCK RC1/AN5/CPS5/C12IN1-/SDA/ SDI RC2/AN6/CPS6/C12IN2-/P1D/ SDO(1)/MDCIN1 RC3/AN7/CPS7/C12IN3-/P1C/ SS(1)/MDMIN RC4/C2OUT/SRNQ/P1B/CK(1)/ TX(1)/MDOUT RC5/P1A/CCP1/DT(1)/RX(1)/ MDCIN2 Output Type Description CMOS General purpose I/O. External clock input (EC mode). Crystal/Resonator (LP, XT, HS modes). Timer1 oscillator connection. Timer1 clock input. CMOS General purpose I/O. — A/D Channel 4 input. CPS4 AN — Capacitive sensing input 4. C2IN+ AN — Comparator C2 positive input. SCL I2C™ OD I2C™ clock. SCK ST CMOS SPI clock. RC1 TTL CMOS General purpose I/O. AN5 AN — CPS5 AN — Capacitive sensing input 5. C12IN1- AN — Comparator C1 or C2 negative input. SDA I2C™ OD I2C™ data input/output. — SPI data input. SDI CMOS RC2 TTL AN6 AN A/D Channel 5 input. CMOS General purpose I/O. — A/D Channel 6 input. CPS6 AN — Capacitive sensing input 6. C12IN2- AN — Comparator C1 or C2 negative input. P1D — CMOS PWM output. SDO — CMOS SPI data output. MDCIN1 ST RC6 TTL — Modulator Carrier Input 1. CMOS General purpose I/O. AN7 AN — A/D Channel 6 input. CPS7 AN — Capacitive sensing input 6. C12IN3- AN — Comparator C1 or C2 negative input. P1C — CMOS PWM output. SS ST — Slave Select input. MDMIN ST — Modulator source input. RC4 TTL C2OUT — CMOS Comparator C2 output. SRNQ — CMOS SR latch inverting output. P1B — CMOS PWM output. CK ST CMOS USART synchronous clock. TX — CMOS USART asynchronous transmit. MDOUT — RC5 TTL CMOS General purpose I/O. CMOS Modulator output. CMOS General purpose I/O. P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM 1. CMOS USART synchronous data. DT ST RX ST — USART asynchronous input. MDCIN2 ST — Modulator Carrier Input 2. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).  2010-2015 Microchip Technology Inc. DS40001413E-page 13 PIC12(L)F1822/16(L)F1823 TABLE 1-3: PIC16(L)F1823 PINOUT DESCRIPTION (CONTINUED) Function Input Type Output Type VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Name Description Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1). DS40001413E-page 14  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. • • • • Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” for more details.  2010-2015 Microchip Technology Inc. DS40001413E-page 15 PIC12(L)F1822/16(L)F1823 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W Reg Internal Oscillator Block VDD DS40001413E-page 16 VSS  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM - Device Memory Maps - Special Function Registers Summary • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC12(L)F1822/16(L)F1823 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. Note 1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC12(L)F1822 PIC16(L)F1823  2010-2015 Microchip Technology Inc. Program Memory Space (Words) Last Program Memory Address 2,048 07FFh DS40001413E-page 17 PIC12(L)F1822/16(L)F1823 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12(L)F1822/16(L)F1823 PC CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. Stack Level 15 EXAMPLE 3-1: 0000h Interrupt Vector 0004h 0005h Page 0 Rollover to Page 0 Wraps to Page 0 07FFh 0800h RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. Wraps to Page 0 Rollover to Page 0 constants BRW my_function ;… LOTS OF CODE… MOVLW DATA_INDEX CALL constants ;… THE CONSTANT IS IN W Wraps to Page 0 DS40001413E-page 18 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 Reset Vector On-chip Program Memory 3.1.1 7FFFh  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The High directive will set bit if a label points to a location in program memory. EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.2 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC12(L)F1822/16(L)F1823. These registers are listed below: • • • • • • • • • • • • INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON Note: The core registers are the first 12 addresses of every data memory bank. Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 “Indirect Addressing” for more information.  2010-2015 Microchip Technology Inc. DS40001413E-page 19 PIC12(L)F1822/16(L)F1823 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 29.0 “Instruction Set Summary”). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 — For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). — U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. DS40001413E-page 20  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 3.2.2 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 “Linear Data Memory” for more information. 3.2.4 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: MEMORY MAP TABLES Device GENERAL PURPOSE RAM There are up to 80 bytes of GPR in each data memory bank. 3.2.3.1 3.2.5 PIC12(L)F1822/16(L)F1823 Banks Table No. 0-7 Table 3-3 8-15 Table 3-4 16-23 Table 3-5 24-31 Table 3-6 31 Table 3-7 COMMON RAM There are 16 bytes of common RAM accessible from all banks. FIGURE 3-2: 7-bit Bank Offset BANKED MEMORY PARTITIONING Memory Region 00h 0Bh 0Ch Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh  2010-2015 Microchip Technology Inc. DS40001413E-page 21 PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 0-7 BANK 0 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA — PORTC(1) — — PIR1 PIR2 — — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — CPSCON0 CPSCON1  2010-2015 Microchip Technology Inc. General Purpose Register 80 Bytes 06Fh 070h BANK 1 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h 0BFh 0CFh 0EFh 0F0h Legend: Note 1: Unimplemented Read as ‘0’ BANK 2 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h 0FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA — LATC(1) — — CM1CON0 CM1CON1 CM2CON0(1) CM2CON1(1) CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 — APFCON — — 16Fh 170h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA — ANSELC(1) — — EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 — — RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON Accesses 70h – 7Fh 17Fh BANK 4 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h Unimplemented Read as ‘0’ 1EFh 1F0h = Unimplemented data memory locations, read as ‘0’. Available only on PIC16(L)F1823. BANK 3 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h Unimplemented Read as ‘0’ Accesses 70h – 7Fh Common RAM 07Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA — TRISC(1) — — PIE1 PIE2 — — OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 — General Purpose Register 32 Bytes BANK 5 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h Unimplemented Read as ‘0’ 26Fh 270h Accesses 70h – 7Fh 1FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA — WPUC(1) — — SSP1BUF SSP1ADD SSP1MASK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3 — — — — — — — — BANK 6 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h Unimplemented Read as ‘0’ BANK 7 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h Unimplemented Read as ‘0’ Accesses 70h – 7Fh 2FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh 27Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON — — — — — — — — — Unimplemented Read as ‘0’ 3EFh 3F0h Accesses 70h – 7Fh 37Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — IOCAP IOCAN IOCAF — — — — — — CLKRCON — MDCON MDSRC MDCARL MDCARH Accesses 70h – 7Fh 3FFh PIC12(L)F1822/16(L)F1823 DS40001413E-page 22 TABLE 3-3:  2010-2015 Microchip Technology Inc. TABLE 3-4: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 8-15 BANK 8 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h Unimplemented Read as ‘0’ DS40001413E-page 23 46Fh 470h Legend: BANK 10 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h Unimplemented Read as ‘0’ 4EFh 4F0h Accesses 70h – 7Fh 47Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 11 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h Unimplemented Read as ‘0’ 56Fh 570h Accesses 70h – 7Fh 4FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ 5EFh 5F0h Accesses 70h – 7Fh 57Fh = Unimplemented data memory locations, read as ‘0’. BANK 12 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h BANK 13 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h Unimplemented Read as ‘0’ 66Fh 670h Accesses 70h – 7Fh 5FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 14 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Unimplemented Read as ‘0’ 6EFh 6F0h Accesses 70h – 7Fh 67Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 15 780h 781h 782h 783h 784h 785h 786h 787h 788h 789h 78Ah 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as ‘0’ 76Fh 770h Accesses 70h – 7Fh 6FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ 7EFh 7F0h Accesses 70h – 7Fh 77Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh 7FFh PIC12(L)F1822/16(L)F1823 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 16-23 BANK 16  2010-2015 Microchip Technology Inc. 800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 17 880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h Unimplemented Read as ‘0’ 86Fh 870h Legend: BANK 18 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h Unimplemented Read as ‘0’ 8EFh 8F0h 8FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 19 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h Unimplemented Read as ‘0’ INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh 97Fh = Unimplemented data memory locations, read as ‘0’. BANK 20 A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h Unimplemented Read as ‘0’ 9EFh 9F0h 96Fh 970h Accesses 70h – 7Fh Accesses 70h – 7Fh 87Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 21 A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h Unimplemented Read as ‘0’ BANK 22 B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h Unimplemented Read as ‘0’ Accesses 70h – 7Fh A7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — AEFh AF0h A6Fh A70h Accesses 70h – 7Fh 9FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 23 B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ Accesses 70h – 7Fh B7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BEFh BF0h B6Fh B70h Accesses 70h – 7Fh AFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh BFFh PIC12(L)F1822/16(L)F1823 DS40001413E-page 24 TABLE 3-5:  2010-2015 Microchip Technology Inc. TABLE 3-6: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANKS 24-31 BANK 24 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 25 C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as ‘0’ DS40001413E-page 25 C6Fh C70h CFFh BANK 26 D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Unimplemented Read as ‘0’ CEFh CF0h Accesses 70h – 7Fh Legend: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 27 D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h Unimplemented Read as ‘0’ D6Fh D70h Accesses 70h – 7Fh CFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ DEFh DF0h Accesses 70h – 7Fh D7Fh = Unimplemented data memory locations, read as ‘0’. BANK 28 E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h BANK 29 E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h Unimplemented Read as ‘0’ E6Fh E70h Accesses 70h – 7Fh DFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 30 F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h Unimplemented Read as ‘0’ EEFh EF0h Accesses 70h – 7Fh E7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 31 F80h INDF0 F81h INDF1 F82h PCL F83h STATUS F84h FSR0L F85h FSR0H F86h FSR1L F87h FSR1H F88h BSR F89h WREG F8Ah PCLATH F8Bh INTCON F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-7 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h Unimplemented Read as ‘0’ F6Fh F70h Accesses 70h – 7Fh EFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — FEFh FF0h Accesses 70h – 7Fh F7Fh Accesses 70h – 7Fh FFFh PIC12(L)F1822/16(L)F1823 C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h PIC12(L)F1822/16(L)F1823 TABLE 3-7: PIC12(L)F1822/16(L)F1823 MEMORY MAP, BANK 31 Bank 31 FA0h Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’. DS40001413E-page 26 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC12(L)F1822 PIC16(L)F1823 Bank(s) Page No. 0 27 1 28 2 29 3 30 4 31 5 32 6 33 7 34 8 35 9-30 36 31 37  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(1) PCL Program Counter (PC) Least Significant Byte 003h(1) STATUS 004h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h(1) FSR1H Indirect Data Memory Address 1 High Pointer 008h(1) BSR 009h(1) WREG 00Ah(1) PCLATH — 00Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --xx xxxx — — — — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 00Dh — 00Eh PORTC(2) 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF C2IF(2) C1IF EEIF BCL1IF — — — 0000 0--- 0000 0--- 013h — Unimplemented — — 014h — Unimplemented — — 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 018h T1CON TMR1CS1 TMR1CS0 019h T1GCON TMR1GE T1GPOL 01Ah TMR2 Timer2 Module Register 01Bh PR2 Timer2 Period Register 01Ch T2CON Unimplemented — — — T1CKPS T1GTM T1GSPM T1OSCEN T1SYNC T1GGO/ DONE T1GVAL TMR2ON — CPSCON0 CPSON CPSRM — — CPSRNG 01Fh CPSCON1 — — — — CPSCH(2) 1: 2: 3: 4: TMR1ON T1GSS 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 1111 1111 1111 1111 T2OUTPS 01Eh Note xxxx xxxx uuuu uuuu — 0000 0000 0000 0000 01Dh Legend: T2CKPS Unimplemented -000 0000 -000 0000 — CPSOUT T0XCS CPSCH — 00-- 0000 00-- 0000 ---- 0000 ---- 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. — DS40001413E-page 27 PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(1) PCL Program Counter (PC) Least Significant Byte 083h(1) STATUS 084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 088h(1) BSR 089h(1) WREG 08Ah(1) PCLATH — 08Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 08Ch TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 — — — — 0000 0000 0000 0000 — TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 08Dh — 08Eh TRISC(2) 08Fh — Unimplemented — — 090h — Unimplemented — — 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE C2IE(2) C1IE EEIE BCL1IE — — — 0000 0--- 0000 0--- 093h — Unimplemented — — 094h — Unimplemented — — 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE STKOVF STKUNF — — — — — Unimplemented — 096h PCON 097h WDTCON 098h OSCTUNE — 099h OSCCON SPLLEN OSCSTAT 09Bh ADRESL A/D Result Register Low 09Ch ADRESH A/D Result Register High 09Dh ADCON0 — 09Eh ADCON1 ADFM 09Fh — Note 1: 2: 3: 4: PSA PLLR PS RMCLR RI POR WDTPS OSTS HFIOFR BOR 00-- 11qq qq-- qquu SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 — HFIOFL SCS MFIOFR LFIOFR HFIOFS 0011 1-00 0011 1-00 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CHS ADCS GO/DONE — — ADON ADPREF Unimplemented -000 0000 -000 0000 0000 --00 0000 --00 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only. DS40001413E-page 28 — 1111 1111 1111 1111 TUN IRCF 09Ah Legend: T1OSCR —  2010-2015 Microchip Technology Inc. — PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(1) PCL Program Counter (PC) Least Significant Byte 103h(1) STATUS 104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 108h(1) BSR 109h(1) WREG 10Ah(1) PCLATH — 10Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 --xx xxxx --uu uuuu — — — — 0000 0000 0000 0000 — TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 10Dh — 10Eh LATC(2) 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN C2ON C2OUT C2INTP C2INTN — — — Unimplemented — — (2) C1OE C1POL — C1SP C1HYS — — — C2SP — — — — — MC2OUT(2) MC1OUT ---- --00 ---- --00 — — — BORRDY 1--- ---q u--- ---u C1PCH 113h CM2CON0 114h CM2CON1(2) 115h CMOUT 116h BORCON SBOREN — — — 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR 118h DACCON0 DACEN DACLPS DACOE — DACPSS — — C2OE — C2POL C2PCH C1SYNC 0000 -100 0000 -100 C1NCH1(2) C1NCH0 0000 ---0 0000 ---0 C2HYS C2SYNC C2NCH ADFVR — — 0000 -100 0000 -100 0000 --00 0000 --00 0q00 0000 0q00 0000 000- 00-- 000- 00-- 119h DACCON1 11Ah SRCON0 SRLEN 11Bh SRCON1 SRSPE 11Ch — 11Dh APFCON 11Eh — Unimplemented — — 11Fh — Unimplemented — — Legend: Note 1: 2: 3: 4: — DACR SRCLK SRSCKE ---0 0000 ---0 0000 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 SRRC2E SRRC1E 0000 0000 0000 0000 CCP1SEL 000- 0000 000- 0000 SRSC2E(2) SRSC1E SRRPE SRRCKE SSSEL --- T1GSEL TXCKSEL P1BSEL(4) (2) Unimplemented RXDTSEL SDOSEL — (4) x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. — DS40001413E-page 29 PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(1) PCL Program Counter (PC) Least Significant Byte 183h(1) STATUS 184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 188h(1) BSR 189h(1) WREG 18Ah(1) PCLATH — 18Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 — — — ANSC3 ANSC2 ANSC1 ANSC0 ---- 1111 ---- 1111 — — — 0000 0000 0000 0000 — — TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 18Dh — 18Eh ANSELC(2) 18Fh — Unimplemented — — 190h — Unimplemented — — 191h EEADRL EEPROM / Program Memory Address Register Low Byte 192h EEADRH 193h EEDATL 194h EEDATH 195h EECON1 196h EECON2 EEPROM control register 2 197h — Unimplemented — — 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: Note 1: 2: 3: 4: Unimplemented — —(3) — 0000 0000 0000 0000 EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000 EEPROM / Program Memory Read Data Register Low Byte — — EEPGD CFGS xxxx xxxx uuuu uuuu EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR --xx xxxx --uu uuuu RD 0000 x000 0000 q000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only. DS40001413E-page 30 —  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(1) PCL Program Counter (PC) Least Significant Byte 203h(1) STATUS 204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 208h(1) BSR 209h(1) WREG 20Ah(1) PCLATH — 20Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 000x 0000 000u 20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 --11 1111 --11 1111 — — — — 0000 0000 0000 0000 — TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 20Dh — 20Eh WPUC(2) 20Fh — Unimplemented — — 210h — Unimplemented — — 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register Unimplemented — — — xxxx xxxx uuuu uuuu 212h SSP1ADD ADD 213h SSP1MSK MSK 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — Unimplemented — — 219h — Unimplemented — — 21Ah — Unimplemented — — 21Bh — Unimplemented — — 21Ch — Unimplemented — — 21Dh — Unimplemented — — 21Eh — Unimplemented — — 21Fh — Unimplemented — — Legend: Note 1: 2: 3: 4: 0000 0000 0000 0000 1111 1111 1111 1111 S R/W UA BF SSPM 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 31 PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(1) PCL Program Counter (PC) Least Significant Byte 283h(1) STATUS 284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 288h(1) BSR 289h(1) WREG 28Ah(1) PCLATH — 28Bh(1) INTCON GIE 28Ch — Unimplemented — — 28Dh — Unimplemented — — 28Eh — Unimplemented — — 28Fh — Unimplemented — — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON 294h PWM1CON 295h CCP1AS 296h PSTR1CON 297h — Unimplemented — — 298h — Unimplemented — — 299h — Unimplemented — — 29Ah — Unimplemented — — 29Bh — Unimplemented — — 29Ch — Unimplemented — — 29Dh — Unimplemented — — 29Eh — Unimplemented — — 29Fh — Unimplemented — — Legend: Note 1: 2: 3: 4: — — — — — 0000 0000 0000 0000 TO PD Z DC C 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE P1M TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF xxxx xxxx uuuu uuuu DC1B CCP1M 0000 0000 0000 0000 P1DC CCP1ASE CCP1AS — — 0000 000x 0000 000u xxxx xxxx uuuu uuuu P1RSEN — ---1 1000 ---q quuu 0000 0000 0000 0000 PSS1AC STR1SYNC STR1D PSS1BD STR1C STR1B STR1A 0000 0000 0000 0000 ---0 0001 ---0 0001 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only. DS40001413E-page 32  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(1) PCL Program Counter (PC) Least Significant Byte 303h(1) STATUS 304h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 305h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 306h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 307h(1) FSR1H Indirect Data Memory Address 1 High Pointer 308h(1) BSR 309h(1) WREG 30Ah(1) PCLATH — 30Bh(1) INTCON GIE 30Ch — Unimplemented — — 30Dh — Unimplemented — — 30Eh — Unimplemented — — 30Fh — Unimplemented — — 310h — Unimplemented — — 311h — Unimplemented — — 312h — Unimplemented — — 313h — Unimplemented — — 314h — Unimplemented — — 315h — Unimplemented — — 316h — Unimplemented — — 317h — Unimplemented — — 318h — Unimplemented — — 319h — Unimplemented — — 31Ah — Unimplemented — — 31Bh — Unimplemented — — 31Ch — Unimplemented — — 31Dh — Unimplemented — — 31Eh — Unimplemented — — 31Fh — Unimplemented — — Legend: Note 1: 2: 3: 4: — — — — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 33 PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(1) PCL Program Counter (PC) Least Significant Byte 383h(1) STATUS 384h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 385h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 386h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 387h(1) FSR1H Indirect Data Memory Address 1 High Pointer 388h(1) BSR 389h(1) WREG 38Ah(1) PCLATH — 38Bh(1) INTCON GIE 38Ch — Unimplemented — — 38Dh — Unimplemented — — 38Eh — Unimplemented — — 38Fh — Unimplemented — — 390h — Unimplemented — — 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h — Unimplemented — — 395h — Unimplemented — — 396h — Unimplemented — — 397h — Unimplemented — — 398h — Unimplemented — — 399h — Unimplemented — — 39Ah CLKRCON — — CLKREN 39Bh — MDCON MDEN 39Dh MDSRC MDMSODIS 39Eh MDCARL MDCLODIS 39Fh MDCARH MDCHODIS Note 1: 2: 3: 4: — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 39Ch Legend: — 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE CLKROE TMR0IE CLKRSLR INTE IOCIE -000 0000 -000 0000 TMR0IF CLKRDC INTF IOCIF CLKRDIV 0000 000x 0000 000u 0011 0000 0011 0000 Unimplemented — MDOE MDOUT MDOPOL — — — MDMS x--- xxxx u--- uuuu MDCLPOL MDCLSYNC — MDCL xxx- xxxx uuu- uuuu MDCHPOL MDCHSYNC — MDCH xxx- xxxx uuu- uuuu — — MDBIT 0010 ---0 0010 ---0 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only. DS40001413E-page 34 — MDSLR  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 8 400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(1) PCL Program Counter (PC) Least Significant Byte 403h(1) STATUS 404h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 405h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 406h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 407h(1) FSR1H Indirect Data Memory Address 1 High Pointer 408h(1) BSR 409h(1) WREG 40Ah(1) PCLATH — 40Bh(1) INTCON GIE 40Ch — Unimplemented — — 40Dh — Unimplemented — — 40Eh — Unimplemented — — 40Fh — Unimplemented — — 410h — Unimplemented — — 411h — Unimplemented — — 412h — Unimplemented — — 413h — Unimplemented — — 414h — Unimplemented — — 415h — Unimplemented — — 416h — Unimplemented — — 417h — Unimplemented — — 418h — Unimplemented — — 419h — Unimplemented — — 41Ah — Unimplemented — — 41Bh — Unimplemented — — 41Ch — Unimplemented — — 41Dh — Unimplemented — — 41Eh — Unimplemented — — 41Fh — Unimplemented — — Legend: Note 1: 2: 3: 4: — — — — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 35 PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 9-30 x00h/ x80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h/ x83h(1) STATUS x04h/ x84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h/ x85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h/ x86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h/ x87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h/ x88h(1) BSR x09h/ x89h(1) WREG x0Ah/ x8Ah(1) PCLATH — x0Bh/ x8Bh(1) INTCON GIE x0Ch/ x8Ch — x1Fh/ x9Fh — Legend: Note 1: 2: 3: 4: — — — — — TO PD — Z DC C BSR ---1 1000 ---q quuu ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF Unimplemented INTF IOCIF 0000 000x 0000 000u — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only. DS40001413E-page 36  2010-2015 Microchip Technology Inc. — PIC12(L)F1822/16(L)F1823 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(1) PCL Program Counter (PC) Least Significant Byte F83h(1) STATUS F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer F88h(1) BSR F89h(1) WREG F8Ah(1) PCLATH — F8Bh(1) INTCON GIE F8Ch — FE3h — FE4h STATUS_ — — — — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF Unimplemented — 0000 000x 0000 000u — — — — — Z_SHAD DC_SHAD C_SHAD — ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ SHAD FECh — FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Note 1: 2: 3: 4: Unimplemented — — — — Current Stack pointer Top-of-Stack Low byte — Top-of-Stack High byte xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1823 only. Unimplemented. Read as ‘1’. PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. — ---1 1111 ---1 1111 DS40001413E-page 37 PIC12(L)F1822/16(L)F1823 3.3 3.3.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 3-3: If using the CALL instruction, the PCH and PCL registers are loaded with the operand of the CALL instruction. PCH is loaded with PCLATH. PC LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 14 PCH PCL 0 PCLATH PC 8 ALU Result PCL 0 4 0 11 OPCODE PC 14 PCH PCL 0 CALLW 6 PCLATH PC Instruction with PCL as Destination GOTO, CALL 6 PCLATH 0 14 7 0 PCH 8 W PCL 0 BRW 14 PCH 3.3.4 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC + W PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. PCL 0 BRA 15 PC + OPCODE 3.3.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.3.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). DS40001413E-page 38  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 3.4 3.4.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-4 through 3-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement STKPTR. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL  2010-2015 Microchip Technology Inc. 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) DS40001413E-page 39 PIC12(L)F1822/16(L)F1823 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL DS40001413E-page 40 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2010-2015 Microchip Technology Inc. DS40001413E-page 41 PIC12(L)F1822/16(L)F1823 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001413E-page 42  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x00 0x7F  2010-2015 Microchip Technology Inc. DS40001413E-page 43 PIC12(L)F1822/16(L)F1823 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF DS40001413E-page 44 0xF6F 0xFFFF 0x7FFF  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 register at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2010-2015 Microchip Technology Inc. DS40001413E-page 45 PIC12(L)F1822/16(L)F1823 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN R/P-1/1 R/P-1/1 BOREN bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE R/P-1/1 CPD bit 8 R/P-1/1 R/P-1/1 WDTE R/P-1/1 R/P-1/1 R/P-1/1 FOSC bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of the WPUA register. bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled Note 1: 2: 3: Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. DS40001413E-page 46  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 4-1: bit 2-0 Note 1: 2: 3: CONFIGURATION WORD 1 (CONTINUED) FOSC: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off.  2010-2015 Microchip Technology Inc. DS40001413E-page 47 PIC12(L)F1822/16(L)F1823 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1/1 R/P-1/1 U-1 R/P-1/1 R/P-1/1 R/P-1/1 LVP(1) DEBUG(2) — BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 R-1 U-1 U-1 — — — Reserved — — R/P-1/1 R/P-1/1 WRT bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(2) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 Unimplemented: Read as ‘1’ bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = Brown-out Reset voltage (Vbor), low trip point selected 0 = Brown-out Reset voltage (Vbor), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-5 Unimplemented: Read as ‘1’ bit 4 Reserved: This location should be programmed to a ‘1’. bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT: Flash Memory Self-Write Protection bits 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control Note 1: 2: 3: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. The DEBUG bit in Configuration Word is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. See Vbor parameter for specific trip point voltages. DS40001413E-page 48  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.3 “Write Protection” for more information. 4.2.2 DATA EEPROM PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 4.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT bits in Configuration Word 2 define the size of the program memory block that is protected. 4.4 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27/PIC12F/LF1822 Memory Programming Specification” (DS41390).  2010-2015 Microchip Technology Inc. DS40001413E-page 49 PIC12(L)F1822/16(L)F1823 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. DEVICEID: DEVICE ID REGISTER(1) REGISTER 4-3: R R R R R R DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 13 bit 8 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared bit 13-5 DEV: Device ID bits 100111000 = PIC12F1822 100111001 = PIC16F1823 101000000 = PIC12LF1822 101000001 = PIC16LF1823 bit 4-0 REV: Revision ID bits ‘1’ = Bit is set These bits are used to identify the revision. Note 1: This location cannot be written. DS40001413E-page 50  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 5.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 5.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources  2010-2015 Microchip Technology Inc. The oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM – External Clock Medium-Power mode (0.5 MHz to 4 MHz) ECH – External Clock High-Power mode (4 MHz to 32 MHz) LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) RC – External Resistor-Capacitor (RC). INTOSC – Internal oscillator (31 kHz to 32 MHz). Clock Source modes are selected by the FOSC bits in the Configuration Word 1. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces low, medium, and high frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these three clock sources. DS40001413E-page 51 PIC12(L)F1822/16(L)F1823 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 5-1: External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Oscillator Timer1 FOSC = 100 T1OSO T1OSCEN Enable Oscillator IRCF HFPLL 500 kHz Source 16 MHz (HFINTOSC) Postscaler Internal Oscillator Block 500 kHz (MFINTOSC) 31 kHz Source 31 kHz 31 kHz (LFINTOSC) DS40001413E-page 52 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz MUX T1OSI Sleep T1OSC MUX OSC1 CPU and Peripherals Internal Oscillator Clock Control FOSC SCS Clock Source Option for other modules WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 5.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained internally within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Locked Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3 “Clock Switching” for additional information. 5.2.1 FIGURE 5-2: OSC1/CLKIN Clock from Ext. System PIC® MCU FOSC/4 or I/O(1) Note 1: EXTERNAL CLOCK (EC) MODE OPERATION OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Word 1. EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: • Program the FOSC bits in the Configuration Word 1 to select an external clock source that will be used as the default system clock upon a device Reset. • Write the SCS bits in the OSCCON register to switch the system clock source to: - Timer1 Oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 5.3 “Clock Switching”for more information. 5.2.1.1 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode. 5.2.1.2 LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Word 1: • High power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low power, 0-0.5 MHz (FOSC = 101)  2010-2015 Microchip Technology Inc. DS40001413E-page 53 PIC12(L)F1822/16(L)F1823 FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 5-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 Note 1: 2: C1 To Internal Logic Quartz Crystal C2 OSC1/CLKIN RS(1) RF(2) Sleep RP(3) OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. C2 Ceramic RS(1) Resonator Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) To Internal Logic RF(2) Sleep OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 5.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4 “Two-Speed Clock Start-up Mode”). 5.2.1.4 4X PLL The oscillator module contains a 4X PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4X PLL must fall within specifications. See the PLL Clock Timing Specifications in Section 30.0 “Electrical Specifications”. The 4X PLL may be enabled for use by one of two methods: 1. 2. DS40001413E-page 54 Program the PLLEN bit in Configuration Word 2 to a ‘1’. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Word 2 is programmed to a ‘1’, then the value of SPLLEN is ignored.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 5.2.1.5 5.2.1.6 TIMER1 Oscillator External RC Mode The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The Timer1 Oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3 “Clock Switching” for more information. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. FIGURE 5-5: QUARTZ CRYSTAL OPERATION (TIMER1 OSCILLATOR) Figure 5-6 shows the external RC mode connections. FIGURE 5-6: VDD PIC® MCU PIC® MCU REXT OSC1/CLKIN T1OSI C1 To Internal Logic 32.768 kHz Quartz Crystal Internal Clock CEXT VSS FOSC/4 or I/O(1) C2 EXTERNAL RC MODES OSC2/CLKOUT T1OSO Recommended values: 10 k  REXT  100 k, 20 pF, 2-5V Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288)  2010-2015 Microchip Technology Inc. Note 1: Output depends upon CLKOUTEN bit of the Configuration Word 1. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. DS40001413E-page 55 PIC12(L)F1822/16(L)F1823 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 “Clock Switching”for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. The internal oscillator block has two independent oscillators and a dedicated Phase-Locked Loop, HFPLL that can produce one of three internal system clock sources. 1. 2. 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Locked Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. 5.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the HFINTOSC can be selected via software using the IRCF bits of the OSCCON register. See Section 5.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The HFINTOSC is enabled by: • Configure the IRCF bits of the OSCCON register for the desired HF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’. The High Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running and can be utilized. The High Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 5.2.2.2 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF bits of the OSCCON register. See Section 5.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF bits of the OSCCON register for the desired HF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. DS40001413E-page 56  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 5.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 5.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF bits of the OSCCON register. See Section 5.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF of the OSCCON register. The outputs of the 16 MHz HFINTOSC postscaler and the LFINTOSC connect to a multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: • • • • • • • • • • • • 32 MHz (requires 4X PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (Default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF bits of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. The IRCF bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. • Configure the IRCF bits of the OSCCON register for the desired LF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized.  2010-2015 Microchip Technology Inc. DS40001413E-page 57 PIC12(L)F1822/16(L)F1823 5.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4X PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Word 1 must be set to use the INTOSC source as the device system clock (FOSC = 100). • The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC in Configuration Word 1 (SCS = 00). • The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC set to use (IRCF = 1110). • The SPLLEN bit in the OSCCON register must be set to enable the 4xPLL, or the PLLEN bit of the Configuration Word 2 must be programmed to a ‘1’. Note: When using the PLLEN bit of the Configuration Word 2, the 4xPLL cannot be disabled by software and the 8 MHz HFINTOSC option will no longer be available. The 4xPLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4xPLL with the internal oscillator. DS40001413E-page 58 5.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. IRCF bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 5-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 30.0 “Electrical Specifications”.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ MFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Oscillator Delay(1) 2-cycle Sync Running LFINTOSC IRCF 0 0 System Clock LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF =0 0 System Clock Note 1: See Table 5-1, Oscillator Switching Delays, for more information.  2010-2015 Microchip Technology Inc. DS40001413E-page 59 PIC12(L)F1822/16(L)F1823 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. • Default system oscillator determined by FOSC bits in Configuration Word 1 • Timer1 32 kHz crystal oscillator • Internal Oscillator Block (INTOSC) The Timer1 oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 21.0 “Timer1 Module with Gate Control” for more information about the Timer1 peripheral. 5.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. • When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC bits in the Configuration Word 1. • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: 5.3.4 TIMER1 OSCILLATOR READY (T1OSCR) BIT The user must ensure that the Timer1 Oscillator is ready to be used before it is selected as a system clock source. The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1. 5.3.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC bits in the Configuration Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 Oscillator. DS40001413E-page 60  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 5.4 5.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word 1) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). • SCS (of the OSCCON register) = 00. • FOSC bits in the Configuration Word 1 configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) Sleep/POR MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz Oscillator Warm-up Delay Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each Sleep/POR Timer1 Oscillator LP, XT, HS(1) 32 kHz-20 MHz 1024 Clock Cycles (OST) Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC(1) 31 kHz 1 cycle of each Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32 MHz 2 ms (approx.) Note 1: PLL inactive.  2010-2015 Microchip Technology Inc. DS40001413E-page 61 PIC12(L)F1822/16(L)F1823 5.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 5.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 5-8: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC bits in the Configuration Word 1, or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS40001413E-page 62  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 5.5 5.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC). FIGURE 5-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock S LFINTOSC Oscillator ÷ 64 31 kHz (~32 s) 488 Hz (~2 ms) R Q Sample Clock The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware. 5.5.4 Q Clock Failure Detected FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note: 5.5.1 FAIL-SAFE CONDITION CLEARING Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2010-2015 Microchip Technology Inc. DS40001413E-page 63 PIC12(L)F1822/16(L)F1823 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS40001413E-page 64  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 5.6 Oscillator Control Registers REGISTER 5-1: R/W-0/0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-1/1 SPLLEN R/W-1/1 IRCF R/W-1/1 U-0 R/W-0/0 — R/W-0/0 SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Word 1 = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Word 1 = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF: Internal Oscillator Frequency Select bits 000x = 31 kHz LF 0010 = 31.25 kHz MF 0011 = 31.25 kHz HF(1) 0100 = 62.5 kHz MF 0101 = 125 kHz MF 0110 = 250 kHz MF 0111 = 500 kHz MF (default upon Reset) 1000 = 125 kHz HF(1) 1001 = 250 kHz HF(1) 1010 = 500 kHz HF(1) 1011 = 1 MHz HF 1100 = 2 MHz HF 1101 = 4 MHz HF 1110 = 8 MHz or 32 MHz HF(see Section 5.2.2.1 “HFINTOSC”) 1111 = 16 MHz HF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC in Configuration Word 1. Note 1: Duplicate frequency derived from HFINTOSC.  2010-2015 Microchip Technology Inc. DS40001413E-page 65 PIC12(L)F1822/16(L)F1823 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC bits of the Configuration Word 1 0 = Running from an internal oscillator (FOSC = 100) bit 4 HFIOFR: High Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS40001413E-page 66  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN: Frequency Tuning bits 011111 = Maximum frequency 011110 = • • • 000001 = 000000 = Oscillator module is running at the factory-calibrated frequency. 111111 = • • • 100000 = Minimum frequency TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 OSCCON SPLLEN OSCSTAT T1OSCR OSCTUNE PIE2 Legend: Note 1: OSTS Bit 3 Bit 2 HFIOFR HFIOFL MFIOFR BCL1IE IRCF — C1IE EEIE OSFIF (1) C1IF EEIF C2IF Bit 1 — C2IE(1) Bit 0 SCS T1CKPS Register on Page 65 LFIOFR HFIOFS — — — BCL1IF — — — 90 T1OSCEN T1SYNC — TMR1ON 173 TUN TMR1CS 66 67 88 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. PIC16(L)F1823 only. TABLE 5-3: CONFIG1 PLLR Bit 4 — T1CON Name Bit 5 OSFIE PIR2 Legend: Note 1: Bit 6 Bits SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 — — FCMEN 7:0 CP MCLRE PWRTE Bit 10/2 Bit 9/1 BOREN WDTE FOSC Bit 8/0 CPD Register on Page 46 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. PIC12F1822/16F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 67 PIC12(L)F1822/16(L)F1823 6.0 REFERENCE CLOCK MODULE 6.3 Conflicts with the CLKR pin The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR) and provide a secondary internal clock source to the modulator module. This module is available in all oscillator configurations and allows the user to select a greater range of clock sub-multiples to drive external devices in the application. The reference clock module includes the following features: There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • • • • • • 6.3.1 System clock is the source Available in all oscillator configurations Programmable clock divider Output enable to a port pin Selectable duty cycle Slew rate control The reference clock module is controlled by the CLKRCON register (Register 6-1) and is enabled when setting the CLKREN bit. To output the divided clock signal to the CLKR port pin, the CLKROE bit must be set. The CLKRDIV bits enable the selection of eight different clock divider options. The CLKRDC bits can be used to modify the duty cycle of the output clock(1). The CLKRSLR bit controls slew rate limiting. Note 1: If the base clock rate is selected without a divider, the output clock will always have a duty cycle equal to that of the source clock, unless a 0% duty cycle is selected. If the clock divider is set to base clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock. For information on using the reference clock output with the modulator module, see Section 23.0 “Data Signal Modulator”. 6.1 • LP, XT or HS oscillator mode is selected. • CLKOUT function is enabled. Even if either of these cases are true, the module can still be enabled and the reference clock signal may be used in conjunction with the modulator module. OSCILLATOR MODES If LP, XT or HS oscillator modes are selected, the OSC2/CLKR pin must be used as an oscillator input pin and the CLKR output cannot be enabled. See Section 5.2 “Clock Source Types” for more information on different oscillator modes. 6.3.2 CLKOUT FUNCTION The CLKOUT function has a higher priority than the reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configuration Word 1, FOSC/4 will always be output on the port pin. Reference Section 4.0 “Device Configuration” for more information. 6.4 Operation During Sleep As the reference clock module relies on the system clock as its source, and the system clock is disabled in Sleep, the module does not function in Sleep, even if an external clock source or the Timer1 clock source is configured as the system clock. The module outputs will remain in their current state until the device exits Sleep. Slew Rate The slew rate limitation on the output port pin can be disabled. The Slew Rate limitation can be removed by clearing the CLKRSLR bit in the CLKRCON register. 6.2 Effects of a Reset Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. DS40001413E-page 68  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC R/W-0/0 R/W-0/0 CLKRDIV bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference clock module is enabled 0 = Reference clock module is disabled bit 6 CLKROE: Reference Clock Output Enable bit(3) 1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin bit 5 CLKRSLR: Reference Clock Slew Rate Control limiting enable bit 1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled bit 4-3 CLKRDC: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 CLKRDIV Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration Word 1 = 0 will result in FOSC/4. See Section 6.3 “Conflicts with the CLKR pin” for details.  2010-2015 Microchip Technology Inc. DS40001413E-page 69 PIC12(L)F1822/16(L)F1823 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Name CLKRCON Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CLKREN CLKROE CLKRSLR CLKRDC1 CLKRDC0 CLKRDIV2 CONFIG1 Legend: Bit 0 CLKRDIV1 CLKRDIV0 Register on Page 69 — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. TABLE 6-2: Name Bit 1 Bits SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD 7:0 CP MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 Register on Page 46 — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. DS40001413E-page 70  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 7.0 RESETS There are multiple ways to reset this device: • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 7-1. FIGURE 7-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLRE MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD Brown-out Reset BOR Enable PWRT Zero LFINTOSC 64 ms PWRTEN  2010-2015 Microchip Technology Inc. DS40001413E-page 71 PIC12(L)F1822/16(L)F1823 7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 7.1.1 • • • • POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Word 1. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). TABLE 7-1: The Brown-out Reset module has four operating modes controlled by the BOREN bits in Configuration Word 1. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 7-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Word 2. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 7-3 for more information. BOR OPERATING MODES SBOREN Device Mode BOR Mode Device Device Operation upon Operation upon wake- up from release of POR Sleep BOR_ON (11) X X Active Waits for BOR ready(1) BOR_NSLEEP (10) X Awake Active BOR_NSLEEP (10) X Sleep Disabled BOR_SBOREN (01) 1 X Active Begins immediately BOR_SBOREN (01) 0 X Disabled Begins immediately BOR_OFF (00) X X Disabled Begins immediately BOREN Config bits Waits for BOR ready Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN bits. 7.2.1 BOR IS ALWAYS ON 7.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Word 1 are set to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. When the BOREN bits of Configuration Word 1 are set to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS40001413E-page 72  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 7.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Word 1 are set to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. FIGURE 7-2: BROWN-OUT READY SBOREN TBORRDY BORRDY FIGURE 7-3: BOR Protection Active BROWN-OUT SITUATIONS VDD Internal Reset VBOR TPWRT(1) VDD Internal Reset VBOR < TPWRT TPWRT(1) VDD Internal Reset Note 1: VBOR TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.  2010-2015 Microchip Technology Inc. DS40001413E-page 73 PIC12(L)F1822/16(L)F1823 REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN — — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN in Configuration Word 1  01: SBOREN is read/write, but has no effect on the BOR. If BOREN in Configuration Word 1 = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive DS40001413E-page 74  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 7.3 MCLR 7.8 Power-Up Timer The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table 7-2). The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. TABLE 7-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Word 1. MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 7.3.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 7.3.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.2 “PORTA Registers” for more information. 7.4 7.9 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 7-4). This is useful for testing purposes or to synchronize more than one device operating in parallel. Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 10.0 “Watchdog Timer” for more information. 7.5 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table 7-4 for default conditions after a RESET instruction has occurred. 7.6 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word 2. See Section 3.4.2 “Overflow/Underflow Reset” for more information. 7.7 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred.  2010-2015 Microchip Technology Inc. DS40001413E-page 75 PIC12(L)F1822/16(L)F1823 FIGURE 7-4: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC DS40001413E-page 76  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 7.10 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset conditions of these registers. TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR RI POR BOR TO PD Condition 0 0 1 1 0 x 1 1 Power-on Reset 0 0 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 0 x x 0 Illegal, PD is set on POR 0 0 1 1 u 0 1 1 Brown-out Reset u u u u u u 0 u WDT Reset u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u 1 0 Interrupt Wake-up from Sleep u u 0 u u u u u MCLR Reset during normal operation u u 0 u u u 1 0 MCLR Reset during Sleep u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as ‘0’.  2010-2015 Microchip Technology Inc. DS40001413E-page 77 PIC12(L)F1822/16(L)F1823 7.11 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR) The PCON register bits are shown in Register 7-2. REGISTER 7-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — — RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to ‘0’ by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to ‘0’ by firmware bit 5-4 Unimplemented: Read as ‘0’ bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS40001413E-page 78  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN — — — — — — BORRDY 74 PCON STKOVF STKUNF — — RMCLR RI POR BOR 78 STATUS — — — TO PD Z DC C 20 WDTCON — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 97 Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.  2010-2015 Microchip Technology Inc. DS40001413E-page 79 PIC12(L)F1822/16(L)F1823 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC Wake-up (If in Sleep mode) TMR0IF TMR0IE INTF Interrupt to CPU INTE IOCIF IOCIE From Peripheral Interrupt Logic (Figure 8-2) PEIE GIE DS40001413E-page 80  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE To Interrupt Logic (Figure 8-1) TMR2IF TMR2IE EEIF EEIE OSFIF OSFIE C1IF C1IE C2IF(1) C2IE(1) BCLIF BCLIE Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 81 PIC12(L)F1822/16(L)F1823 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 8-3 and Figure 8.3 for more details. The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section 8.5 “Automatic Context Saving”.”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001413E-page 82  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 8-3: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC  2010-2015 Microchip Technology Inc. PC+2 NOP NOP DS40001413E-page 83 PIC12(L)F1822/16(L)F1823 FIGURE 8-4: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 30.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001413E-page 84  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 9.0 “PowerDown Mode (Sleep)” for more details. 8.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • • • • • W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.  2010-2015 Microchip Technology Inc. DS40001413E-page 85 PIC12(L)F1822/16(L)F1823 8.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 8-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register have been cleared by software. DS40001413E-page 86  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 8.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 8-2. REGISTER 8-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt  2010-2015 Microchip Technology Inc. DS40001413E-page 87 PIC12(L)F1822/16(L)F1823 8.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 8-3. REGISTER 8-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 OSFIE C2IE(1) C1IE EEIE BCLIE — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit(1) 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1823 only. DS40001413E-page 88  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 8.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 8-4. REGISTER 8-4: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending  2010-2015 Microchip Technology Inc. DS40001413E-page 89 PIC12(L)F1822/16(L)F1823 8.5.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 8-5. REGISTER 8-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 OSFIF C2IF(1) C1IF EEIF BCLIF — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1823 only. DS40001413E-page 90  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 8-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON OPTION_REG Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 164 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 Legend: Note 1: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 91 PIC12(L)F1822/16(L)F1823 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. 6. Timer1 oscillator is unaffected and peripherals that operate from it may continue operation in Sleep. 7. ADC is unaffected, if the dedicated FRC clock is selected. 8. Capacitive Sensing oscillator is unaffected. 9. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). 10. Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: • • • • • • I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using Timer1 oscillator External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 7.10 “Determining the Cause of a Reset”. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 17.0 “Digital-to-Analog Converter (DAC) Module” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these modules. DS40001413E-page 92  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared. FIGURE 9-1: • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) XT, HS or LP Oscillator mode assumed. CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.  2010-2015 Microchip Technology Inc. DS40001413E-page 93 PIC12(L)F1822/16(L)F1823 TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 125 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 125 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 125 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 IOCAP PIE1 PIE2 OSFIE PIR1 TMR1GIF PIR2 STATUS WDTCON Legend: Note 1: OSFIF C2IE (1) ADIF C2IF (1) C1IE EEIE BCL1IE — — — 88 RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 C1IF EEIF BCL1IF — — — 90 — — — TO PD Z DC C 20 — — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN 97 — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. PIC16(L)F1823 only. DS40001413E-page 94  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 10.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE = 01 SWDTEN WDTE = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE = 10 Sleep  2010-2015 Microchip Technology Inc. WDTPS DS40001413E-page 95 PIC12(L)F1822/16(L)F1823 10.1 Independent Clock Source 10.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. 10.2 Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds. After a Reset, the default time-out period is two seconds. WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE bits in Configuration Word 1. See Table 10-1. 10.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Word 1 are set to ‘11’, the WDT is always on. WDT protection is active during Sleep. 10.2.2 WDT IS OFF IN SLEEP When the WDTE bits of Configuration Word 1 are set to ‘10’, the WDT is on, except in Sleep. WDT protection is not active during Sleep. 10.2.3 When the WDTE bits of Configuration Word 1 are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register. TABLE 10-1: by Sleep. See WDT OPERATING MODES WDTE Config bits SWDTEN Device Mode WDT Mode WDT_ON (11) X X Active WDT_NSLEEP (10) X Awake Active WDT_NSLEEP (10) X Sleep Disabled WDT_SWDTEN (01) 1 X Active WDT_SWDTEN (01) 0 X Disabled WDT_OFF (00) X X Disabled TABLE 10-2: Clearing the WDT The WDT is cleared when any of the following conditions occur: • • • • • • • Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail event WDT is disabled OST is running See Table 10-2 for more information. 10.5 WDT CONTROLLED BY SOFTWARE WDT protection is unchanged Table 10-1 for more details. 10.4 Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See Section 3.0 “Memory Organization” and The STATUS register (Register 3-1) for more information. WDT CLEARING CONDITIONS Conditions WDT WDTE = 00 WDTE = 01 and SWDTEN = 0 WDTE = 10 and enter Sleep CLRWDT Command Cleared Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) DS40001413E-page 96 Cleared until the end of OST Unaffected  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 WDTPS bit 7 R/W-0/0 SWDTEN bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS: Watchdog Timer Period Select bits Bit Value = Prescale Rate 00000 = 1:32 (Interval 1 ms typ) 00001 = 1:64 (Interval 2 ms typ) 00010 = 1:128 (Interval 4 ms typ) 00011 = 1:256 (Interval 8 ms typ) 00100 = 1:512 (Interval 16 ms typ) 00101 = 1:1024 (Interval 32 ms typ) 00110 = 1:2048 (Interval 64 ms typ) 00111 = 1:4096 (Interval 128 ms typ) 01000 = 1:8192 (Interval 256 ms typ) 01001 = 1:16384 (Interval 512 ms typ) 01010 = 1:32768 (Interval 1s typ) 01011 = 1:65536 (Interval 2s typ) (Reset value) 01100 = 1:131072 (217) (Interval 4s typ) 01101 = 1:262144 (218) (Interval 8s typ) 01110 = 1:524288 (219) (Interval 16s typ) 01111 = 1:1048576 (220) (Interval 32s typ) 10000 = 1:2097152 (221) (Interval 64s typ) 10001 = 1:4194304 (222) (Interval 128s typ) 10010 = 1:8388608 (223) (Interval 256s typ) 10011 = Reserved. Results in minimum interval (1:32) • • • 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE = 00: This bit is ignored. If WDTE = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE = 1x: This bit is ignored.  2010-2015 Microchip Technology Inc. DS40001413E-page 97 PIC12(L)F1822/16(L)F1823 11.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs). There are six SFRs used to access these memories: • • • • • • EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh. When accessing the program memory block, the EEDATH:EEDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read. The EEPROM data memory allows byte read and write. An EEPROM byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. Depending on the setting of the Flash Program Memory Self Write Enable bits WRT of the Configuration Word 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register. 11.1.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. Interrupt flag bit EEIF of the PIR2 register is set when write is complete. It must be cleared in the software. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. DS40001413E-page 98  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 11.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 30.0 “Electrical Specifications”. If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. 11.2.1 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation). EXAMPLE 11-1: DATA EEPROM READ BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory ;Address to read BCF EECON1, CFGS ;Deselect Config space BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read MOVF EEDATL, W ;W = EEDATL Note: Data EEPROM can be read regardless of the setting of the CPD bit. 11.2.2 WRITING TO THE DATA EEPROM MEMORY To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. 11.2.3 PROTECTION AGAINST SPURIOUS WRITE There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out • Power Glitch • Software Malfunction 11.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Word 1 (Register 5-1) to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM.  2010-2015 Microchip Technology Inc. DS40001413E-page 99 PIC12(L)F1822/16(L)F1823 Required Sequence EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write ;Enable Interrupts ;Disable writes ;Wait for write to complete ;Done FIGURE 11-1: GIE WR GIE WREN WR FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here EEADRH,EEADRL INSTR (PC + 1) BSF EECON1,RD executed here PC +3 PC+3 EEDATH,EEDATL INSTR(PC + 1) executed here PC + 5 PC + 4 INSTR (PC + 3) Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDATL Register EERHLT DS40001413E-page 100  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 11.3 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software. Flash program memory may only be written or erased if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT of Configuration Word 2. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the EEDATH:EEDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. The number of data write latches may not be equivalent to the number of row locations. During programming, user software may need to fill the set of write latches and initiate a programming operation multiple times in order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. 11.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. 4. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair. Clear the CFGS bit of the EECON1 register. Set the EEPGD control bit of the EECON1 register. Then, set control bit RD of the EECON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored. The data is available in the very next cycle, in the EEDATH:EEDATL register pair; therefore, it can be read as two bytes in the following instructions. EEDATH:EEDATL register pair will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. The size of a program memory row and the number of program memory write latches may vary by device. See Table 11-1 for details. TABLE 11-1: Device PIC12(L)F1822 PIC16(L)F1823 FLASH MEMORY ORGANIZATION BY DEVICE Erase Block (Row) Size/ Boundary Number of Write Latches/ Boundary 16 words, EEADRL = 0000 16 words, EEADRL = 0000  2010-2015 Microchip Technology Inc. DS40001413E-page 101 PIC12(L)F1822/16(L)F1823 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Do not select Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 11-1) Ignored (Figure 11-1) Restore interrupts MOVF MOVWF MOVF MOVWF EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS40001413E-page 102  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 11.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE, and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation. Poll the WR bit in the EECON1 register to determine when the row erase has completed. See Example 11-4. After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. 11.3.3 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the starting address of the word(s) to be programmed. Load the write latches with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 11-2 (block writes to program memory with 16 write latches) for more details. The write latches are aligned to the address boundary defined by EEADRL as shown in Table 11-1. Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF.  2010-2015 Microchip Technology Inc. The following steps should be completed to load the write latches and program a block of program memory. These steps are divided into two parts. First, all write latches are loaded with data except for the last program memory location. Then, the last write latch is loaded and the programming sequence is initiated. A special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. This unlock sequence should not be interrupted. 1. Set the EEPGD and WREN bits of the EECON1 register. 2. Clear the CFGS bit of the EECON1 register. 3. Set the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the EEADRH:EEADRL register pair with the address of the location to be written. 5. Load the EEDATH:EEDATL register pair with the program memory data to be written. 6. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The write latch is now loaded. 7. Increment the EEADRH:EEADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is ‘0’, the write sequence will initiate the write to Flash program memory. 10. Load the EEDATH:EEDATL register pair with the program memory data to be written. 11. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The entire latch block is now written to Flash program memory. It is not necessary to load the entire write latch block with user program data. However, the entire write latch block will be written to program memory. An example of the complete write sequence for eight words is shown in Example 11-5. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. DS40001413E-page 103 PIC12(L)F1822/16(L)F1823 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will FIGURE 11-2: continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES 7 5 0 0 7 EEDATH EEDATA 8 6 Last word of block to be written First word of block to be written 14 EEADRL = 0000 14 EEADRL = 0010 EEADRL = 0001 Buffer Register 14 Buffer Register 14 EEADRL = 1111 Buffer Register Buffer Register Program Memory DS40001413E-page 104  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF BANKSEL MOVF MOVWF MOVF MOVWF BSF BCF BSF BSF INTCON,GIE EEADRL ADDRL,W EEADRL ADDRH,W EEADRH EECON1,EEPGD EECON1,CFGS EECON1,FREE EECON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP 55h EECON2 0AAh EECON2 EECON1,WR NOP ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; ; ; ; Point to program memory Not configuration space Specify an erase operation Enable writes ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase Any instructions here are ignored as processor halts to begin erase sequence Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction BCF BSF EECON1,WREN INTCON,GIE  2010-2015 Microchip Technology Inc. ; Disable writes ; Enable interrupts DS40001413E-page 105 PIC12(L)F1822/16(L)F1823 EXAMPLE 11-5: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF INTCON,GIE EEADRH ADDRH,W EEADRH ADDRL,W EEADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ EEDATL FSR0++ EEDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO EEADRL,W 0x07 0x07 STATUS,Z START_WRITE ; Check if lower bits of address are '000' ; Check if we're on the last of 8 addresses ; ; Exit if last of eight words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; Load initial data address Load initial data address Point to program memory Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP EEADRL,F LOOP ; Still loading latches Increment address ; Write next latches EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; NOP BCF BSF DS40001413E-page 106 EECON1,WREN INTCON,GIE Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 11.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. Repeat steps 6 and 7 as many times as required to reprogram the erased row. TABLE 11-2: 11.5 User ID, Device ID and Configuration Word Access Instead of accessing program memory or EEPROM data memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the EECON1 register. This is the region that would be pointed to by PC = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the EEDATH:EEDATL register pair is cleared. USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function 8000h-8003h 8006h 8007h-8008h Read Access Write Access Yes Yes Yes Yes No No User IDs Device ID/Revision ID Configuration Words 1 and 2 EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF EEADRL PROG_ADDR_LO EEADRL EEADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF EECON1,CFGS INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 11-1) Ignored (See Figure 11-1) Restore interrupts MOVF MOVWF MOVF MOVWF EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location  2010-2015 Microchip Technology Inc. DS40001413E-page 107 PIC12(L)F1822/16(L)F1823 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 11-6) to the desired value to be written. Example 11-6 shows how to verify a write to EEPROM. EXAMPLE 11-6: EEPROM WRITE VERIFY BANKSEL EEDATL MOVF EEDATL, W BSF XORWF BTFSS GOTO : ; ;EEDATL not changed ;from previous write EECON1, RD ;YES, Read the ;value written EEDATL, W ; STATUS, Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue DS40001413E-page 108  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 11-1: R/W-x/u EEDATL: EEPROM DATA REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDAT: Read/write value for Most Significant bits of program memory REGISTER 11-3: R/W-0/0 EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR: Specifies the Least Significant bits for program memory address or EEPROM address REGISTER 11-4: U-1 EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 —(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 Note EEADR: Specifies the Most Significant bits for program memory address or EEPROM address 1: Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. DS40001413E-page 109 PIC12(L)F1822/16(L)F1823 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory bit 5 LWLO: Load Write Latches Only bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after completion of erase). 0 = Performs a write operation on the next WR command. If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read. DS40001413E-page 110  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 11-6: W-0/0 EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section 11.2.2 “Writing to the Data EEPROM Memory” for more information. TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 110 EECON2 EEPROM Control Register 2 (not a physical register) EEADRL EEADRL EEADRH —(2) 111* 109 EEADRH EEDATL 109 EEDATL 109 EEDATH — — INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 Legend: * Note 1: 2: EEDATH 109 — = unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module. Page provides register information. PIC16(L)F1823 only. Unimplemented. Read as ‘1’.  2010-2015 Microchip Technology Inc. DS40001413E-page 111 PIC12(L)F1822/16(L)F1823 12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT OPERATION Depending on the device selected and peripherals enabled, there are up to two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Read LATx Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Some ports may have one or more of the following additional registers. These registers are: Write LATx Write PORTx Q CK VDD Data Register Data Bus I/O pin Read PORTx • ANSELx (analog select) • WPUx (weak pull-up) • INLVLx (input level control) To peripherals ANSELx VSS Device PIC12(L)F1822 ● PIC16(L)F1823 ● PORTC PORT AVAILABILITY PER DEVICE PORTA TABLE 12-1: D TRISx ● The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same affect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. DS40001413E-page 112  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register 12-1. For this device family, the following functions can be moved between different pins. • • • • • • • RX/DT TX/CK SDO SS (Slave Select) T1G P1B CCP1/P1A These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.  2010-2015 Microchip Technology Inc. DS40001413E-page 113 PIC12(L)F1822/16(L)F1823 REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(1) CCP1SEL(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RXDTSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = RX/DT function is on RA1 1 = RX/DT function is on RA5 For 14-Pin Devices (PIC16(L)F1823): 0 = RX/DT function is on RC5 1 = RX/DT function is on RA1 bit 6 SDOSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = SDO function is on RA0 1 = SDO function is on RA4 For 14-Pin Devices (PIC16(L)F1823): 0 = SDO function is on RC2 1 = SDO function is on RA4 bit 5 SSSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = SS function is on RA3 1 = SS function is on RA0 For 14-Pin Devices (PIC16(L)F1823): 0 = SS function is on RC3 1 = SS function is on RA3 bit 4 Unimplemented: Read as ‘0’ bit 3 T1GSEL: Pin Selection bit 0 = T1G function is on RA4 1 = T1G function is on RA3 bit 2 TXCKSEL: Pin Selection bit For 8-Pin Devices (PIC12(L)F1822): 0 = TX/CK function is on RA0 1 = TX/CK function is on RA4 For 14-Pin Devices (PIC16(L)F1823): 0 = TX/CK function is on RC4 1 = TX/CK function is on RA0 bit 1 P1BSEL: Pin Selection bit(1) For 8-Pin Devices (PIC12(L)F1822): 0 = P1B function is on RA0 1 = P1B function is on RA4 For 14-Pin Devices (PIC16(L)F1823): P1B function is always on RC4 bit 0 CCP1SEL: Pin Selection bit(1) For 8-Pin Devices (PIC12(L)F1822): 0 = CCP1/P1A function is on RA2 1 = CCP1/P1A function is on RA5 For 14-Pin Devices (PIC16(L)F1823): CCP1/P1A function is always on RC5 Note 1: PIC12(L)F1822 only. DS40001413E-page 114  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 12.2 PORTA Registers PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’. Example 12-1 shows how to initialize PORTA. Reading the PORTA register (Register 12-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). The TRISA register (Register 12-3) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 12.2.1 ANSELA REGISTER The ANSELA register (Register 12-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. EXAMPLE 12-1: BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF INITIALIZING PORTA PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA as inputs ;and set RA as ;outputs  2010-2015 Microchip Technology Inc. DS40001413E-page 115 PIC12(L)F1822/16(L)F1823 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input functions, such as ADC, comparator and CapSense inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. RA0 1. 2. 3. 4. 5. 6. 7. ICSPDAT ICDDAT DACOUT (DAC) MDOUT (PIC12(L)F1822 only) TX/CK (EUSART) SDO (PIC12(L)F1822 only) P1B (PIC12(L)F1822 only) RA3 No output priorities. Input only pin. RA4 1. 2. 3. 4. 5. 6. 7. OSC2 CLKOUT T1OSO (Timer1 Oscillator) CLKR TX/CK (PIC12(L)F1822 only) SDO P1B (PIC12(L)F1822 only) RA5 1. 2. 3. 4. 5. OSC1 T1OSI (Timer1 Oscillator) SRNQ (PIC12(L)F1822 only) RX/DT (PIC12(L)F1822 only) CCP1/P1A (PIC12(L)F1822 only) RA1 1. 2. 3. 4. 5. ICSPCLK ICDCLK SCL (PIC12(L)F1822 only) RX/DT (EUSART) SCK (PIC12(L)F1822 only) RA2 1. 2. 3. 4. SRQ C1OUT (Comparator) SDA (PIC12(L)F1822 only) CCP1/P1A (PIC12(L)F1822 only) DS40001413E-page 116  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 12-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-0 RA: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-4 TRISA: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 TRISA3: RA3 Port Tri-State Control bit This bit is always ‘1’ as RA3 is an input only bit 2-0 TRISA: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output  2010-2015 Microchip Technology Inc. DS40001413E-page 117 PIC12(L)F1822/16(L)F1823 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-4 LATA: RA Output Latch Value bits(1) bit 3 Unimplemented: Read as ‘0 bit 2-0 LATA: RA Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 3 Unimplemented: Read as ‘0’ bit 2-0 ANSA: Analog Select between Analog or Digital Function on pins RA, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001413E-page 118  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSA2 ANSA1 ANSA0 118 ANSELA — — — ANSA4 — APFCON RXDTSEL SDOSEL SSSEL — T1GSEL — — LATA5 LATA4 — WPUEN INTEDG TMR0CS TMR0SE PSA PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 117 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 119 LATA OPTION_REG Legend: Note 1: CONFIG1 Legend: LATA2 LATA1 LATA0 PS 114 118 164 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. PIC12F1822 only. TABLE 12-3: Name TXCKSEL P1BSEL(1) CCP1SEL(1) Bits SUMMARY OF CONFIGURATION WORD WITH PORTA Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 — — FCMEN 7:0 CP MCLRE PWRTE Bit 10/2 WDTE Bit 9/1 Bit 8/0 BOREN CPD FOSC Register on Page 46 — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.  2010-2015 Microchip Technology Inc. DS40001413E-page 119 PIC12(L)F1822/16(L)F1823 12.3 PORTC Registers (PIC16(L)F1823 only) PORTC is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 12-8). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-2 shows how to initialize PORTC. Reading the PORTC register (Register 12-7) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). 12.3.2 Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. RC0 1. 2. SCL (MSSP) SCK (MSSP) The TRISC register (Register 12-8) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. RC1 12.3.1 RC3 ANSELC REGISTER The ANSELC register (Register 12-10) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no affect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELC register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. EXAMPLE 12-2: BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTC FUNCTIONS AND OUTPUT PRIORITIES 1. SDA (MSSP) RC2 1. 2. SDO (MSSP) P1D 1. P1C RC4 1. 2. 3. 4. 5. MDOUT SRNQ C2OUT TX/CK P1B RC5 1. 2. RX/DT CCP1/P1A INITIALIZING PORTC PORTC ; PORTC ;Init PORTC LATC ;Data Latch LATC ; ANSELC ANSELC ;Make RC digital TRISB ; B’00110000’;Set RC as inputs ;and RC as outputs TRISC ; DS40001413E-page 120  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 12-7: PORTC: PORTC REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 12-8: TRISC: PORTC TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 12-9: LATC: PORTC DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LATC: PORTC Output Latch Value bits(1) Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.  2010-2015 Microchip Technology Inc. DS40001413E-page 121 PIC12(L)F1822/16(L)F1823 REGISTER 12-10: ANSELC: PORTC ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — — — ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ANSC: Analog Select between Analog or Digital Function on pins RC, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-11: WPUC: WEAK PULL-UP PORTC REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUC: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-4: Name ANSELC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 LATC2 LATC1 LATC0 — — LATC5 LATC4 LATC3 WPUEN INTEDG TMR0CS TMR0SE PSA PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 121 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 WPUC — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 122 LATC OPTION_REG Legend: Note 1: PS 121 164 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. PIC16(L)F1823 only. DS40001413E-page 122  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 13.0 INTERRUPT-ON-CHANGE The PORTA pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTA pin, or combination of PORTA pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: • • • • Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags Figure 13-1 is a block diagram of the IOC module. 13.1 Enabling the Module To allow individual PORTA pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 13.3 Interrupt Flags The IOCAFx bits located in the IOCAF register are status flags that correspond to the Interrupt-on-change pins of PORTA. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCAFx bits. 13.4 Clearing Interrupt Flags The individual status flags, (IOCAFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 13-1: 13.2 Individual Pin Configuration For each PORTA pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCAPx bit of the IOCAP register is set. To enable a pin to detect a falling edge, the associated IOCANx bit of the IOCAN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCAPx bit and the IOCANx bit of the IOCAP and IOCAN registers, respectively. MOVLW XORWF ANDWF 13.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCAF register will be updated prior to the first instruction executed out of Sleep.  2010-2015 Microchip Technology Inc. DS40001413E-page 123 PIC12(L)F1822/16(L)F1823 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK edge detect R RBx IOCBPx D data bus = 0 or 1 Q write IOCBFx CK D S Q to data bus IOCBFx CK IOCIE R Q2 from all other IOCBFx individual pin detectors Q1 Q3 Q4 Q4Q1 DS40001413E-page 124 Q1 Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Q4Q1  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAN: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change.  2010-2015 Microchip Technology Inc. DS40001413E-page 125 PIC12(L)F1822/16(L)F1823 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 125 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 125 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 125 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 Name IOCAP — — IOCAP5 TRISA — — TRISA5 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. DS40001413E-page 126  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 14.0 FIXED VOLTAGE REFERENCE (FVR) 14.1 The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • • Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 16.0 “Analog-to-Digital Converter (ADC) Module” for additional information. ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) Capacitive Sensing (CPS) module The FVR can be enabled by setting the FVREN bit of the FVRCON register. The CDAFVR bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to Comparators, DAC and CPS module. Reference Section 17.0 “Digital-toAnalog Converter (DAC) Module”, Section 19.0 “Comparator Module” and Section 27.0 “Capacitive Sensing (CPS) Module” for additional information. 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 30.0 “Electrical Specifications” for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR CDAFVR FVREN FVRRDY  2010-2015 Microchip Technology Inc. 2 X1 X2 X4 FVR BUFFER1 (To ADC Module) X1 X2 X4 FVR BUFFER2 (To Comparators, DAC, CPS) 2 + _ 1.024V Fixed Reference DS40001413E-page 127 PIC12(L)F1822/16(L)F1823 REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG R/W-0/0 R/W-0/0 R/W-0/0 CDAFVR R/W-0/0 ADFVR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use bit 5 TSEN: Temperature Indicator Enable bit 0 = Temperature Indicator is disabled 1 = Temperature Indicator is enabled bit 4 TSRNG: Temperature Indicator Range Selection bit 0 = VOUT = VDD - 2VT (Low Range) 1 = VOUT = VDD - 4VT (High Range) bit 3-2 CDAFVR: Comparator and DAC Fixed Voltage Reference Selection bits 00 = Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is off 01 = Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) bit 1-0 ADFVR: ADC Fixed Voltage Reference Selection bits 00 = ADC Fixed Voltage Reference Peripheral output is off 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) Note 1: 2: FVRRDY is always ‘1’ on PIC12F1822/16F1823 only. Fixed Voltage Reference output cannot exceed VDD. TABLE 14-1: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 128 Shaded cells are unused by the Fixed Voltage Reference module. DS40001413E-page 128  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 15.1 TEMPERATURE CIRCUIT DIAGRAM VOUT ADC MUX ADC n CHS bits (ADCON0 register) Circuit Operation Figure 15-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 15-1 describes the output characteristics of the temperature indicator. EQUATION 15-1: VOUT RANGES High Range: VOUT = VDD - 4VT Low Range: VOUT = VDD - 2VT 15.2 Minimum Operating VDD vs. Minimum Sensing Temperature When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 15-1 shows the recommended minimum VDD vs. range setting. TABLE 15-1: The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2010-2015 Microchip Technology Inc. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 15.3 Temperature Output The output of the circuit is measured using the internal analog to digital converter. A channel is reserved for the temperature circuit output. Refer to Section 16.0 “Analog-to-Digital Converter (ADC) Module” for detailed information. 15.3.1 ADC ACQUISITION TIME To ensure accurate temperature measurements, the user must wait at least 200 usec after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 usec between sequential conversions of the temperature indicator output. DS40001413E-page 129 PIC12(L)F1822/16(L)F1823 16.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 00 ADPREF = 11 VREF+ AN0 00000 AN1 00001 AN2 00010 AN3 00011 AN4(2) 00100 AN5(2) 00101 AN6(2) 00110 AN7(2) 00111 ADPREF = 10 ADC 10 GO/DONE Temp Indicator DAC_output 11101 11110 FVR Buffer1 11111 CHS Note 1: 2: ADFM 0 = Left Justify 1 = Right Justify ADON(1) 16 VSS ADRESH ADRESL When ADON = 0, all multiplexer inputs are disconnected. Not available on PIC12(L)F1822. DS40001413E-page 130  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.0 “I/O Ports” for more information. Note: 16.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION There are up to 11 channel selections available: • • • • • AN pins (PIC12(L)F1822 only) AN pins (PIC16(L)F1823 only) Temperature Indicator DAC_output FVR Buffer1 Output 16.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • • • • • • • FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 16-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 30.0 “Electrical Specifications” for more information. Table 16-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. Refer to Section 17.0 “Digital-to-Analog Converter (DAC) Module”, Section 14.0 “Fixed Voltage Reference (FVR)” and Section 15.0 “Temperature Indicator Module” for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 16.2 “ADC Operation” for more information. 16.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • • • • VREF+ pin VDD FVR 2.048V FVR 4.096V (Not available on LF devices) See Section 14.0 “Fixed Voltage Reference (FVR)” for more details on the Fixed Voltage Reference.  2010-2015 Microchip Technology Inc. DS40001413E-page 131 PIC12(L)F1822/16(L)F1823 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns (2) (2) (2) (2) Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) Fosc/16 101 800 ns 800 ns 010 1.0 s Fosc/64 110 FRC x11 Fosc/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 1.0 s 2.0 s 4.0 s 16.0 s(3) 1.6 s 2.0 s 4.0 s 2.0 s 3.2 s 4.0 s 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 200 ns 250 ns 500 ns 8.0 s (3) 8.0 s 16.0 s (3) 1.0-6.0 s(1,4) (3) 1.0-6.0 s(1,4) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS40001413E-page 132  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 16-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result bit 0 Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 Unimplemented: Read as ‘0’  2010-2015 Microchip Technology Inc. LSB bit 0 bit 7 bit 0 10-bit A/D Result DS40001413E-page 133 PIC12(L)F1822/16(L)F1823 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “A/D Conversion Procedure”. COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit • Update the ADRESH and ADRESL registers with new conversion result 16.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. DS40001413E-page 134 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 16.2.5 SPECIAL EVENT TRIGGER The Special Event Trigger of the CCPx/ECCPX module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. TABLE 16-2: SPECIAL EVENT TRIGGER Device CCP1/ECCP1 PIC12(L)F1822/16(L)F1823 CCP1 Using the Special Event Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. Refer to Section 24.0 “Capture/Compare/PWM Modules” for more information.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 16.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 16-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, Frc ;clock MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 16.3 “A/D Acquisition Requirements”.  2010-2015 Microchip Technology Inc. DS40001413E-page 135 PIC12(L)F1822/16(L)F1823 16.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 16-1: U-0 ADCON0: A/D CONTROL REGISTER 0 R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 CHS R/W-0/0 R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4(1) 00101 = AN5(1) 00110 = AN6(1) 00111 = AN7(1) 01001 = Reserved. No channel connected. • • • 11100 = Reserved. No channel connected. 11101 = Temperature Indicator(4) 11110 = DAC output(2) 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: 4: PIC16(L)F1823 only. For PIC12(L)F1822 it is “Reserved. No channel connected”. See Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. See Section 15.0 “Temperature Indicator Module” for more information. DS40001413E-page 136  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 16-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADPREF: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to AVDD 01 = Reserved 10 = VREF+ is connected to external VREF+(1) 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1) Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section 30.0 “Electrical Specifications” for details.  2010-2015 Microchip Technology Inc. DS40001413E-page 137 PIC12(L)F1822/16(L)F1823 REGISTER 16-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-4: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u ADRES R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS40001413E-page 138  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 16-6: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES: ADC Result Register bits Lower eight bits of 10-bit conversion result  2010-2015 Microchip Technology Inc. DS40001413E-page 139 PIC12(L)F1822/16(L)F1823 16.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 16-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k  5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2µs + T C +   Temperature - 25°C   0.05µs/°C   The value for TC can be approximated with the following equations: 1  = V CHOLD V AP P LI ED  1 – -------------------------n+1   2 –1 ;[1] VCHOLD charged to within 1/2 lsb –TC ----------  RC V AP P LI ED  1 – e  = V CHOLD   ;[2] VCHOLD charge response to VAPPLIED – Tc ---------  1 RC  ;combining [1] and [2] V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------n+1    2 –1 Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD  R IC + R SS + R S  ln(1/2047) = – 12.5pF  1k  + 7k  + 10k   ln(0.0004885) = 1.72 µs Therefore: T ACQ = 2µs + 1.72µs +   50°C- 25°C   0.05µs/°C   = 4.97µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS40001413E-page 140  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT  0.6V CPIN 5 pF VA RIC  1k Sampling Switch SS Rss I LEAKAGE(1) VT  0.6V CHOLD = 12.5 pF VSS/VREF- 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance Legend: CHOLD CPIN RSS I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage 5 6 7 8 9 10 11 Sampling Switch (k) Note 1: Refer to Section 30.0 “Electrical Specifications”. FIGURE 16-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB VSS/VREF-  2010-2015 Microchip Technology Inc. Zero-Scale Transition 1.5 LSB Full-Scale Transition VREF+ DS40001413E-page 141 PIC12(L)F1822/16(L)F1823 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 136 ADCON1 ADFM ADCS2 ADCS1 ADCS0 — — ADPREF1 ADPREF0 137 ADRESH A/D Result Register High 130* ADRESL A/D Result Register Low 130* ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 ANSELC(1) — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 213 DACCON0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — — 146 DACCON1 FVRCON — — — DACR4 DACR3 DACR2 DACR1 DACR0 146 FVREN FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 128 GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 INTCON TRISA TRISC(1) Legend: * Note 1: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Page provides register information. PIC16(L)F1823 only. DS40001413E-page 142  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 17.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR bits of the DACCON1 register. The DAC output voltage is determined by the following equations: • External VREF pins • VDD supply voltage • FVR Buffer2 The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • ADC input channel • DACOUT pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. EQUATION 17-1: DAC OUTPUT VOLTAGE IF DACEN = 1 DACR  4:0  VOUT =   VSOURCE+ – VSOURCE-   ----------------------------+ VSOURCE5   2 IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111 V OUT = V SOURCE + IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000 V OUT = V SOURCE – VSOURCE+ = VDD or FVR BUFFER 2 VSOURCE- = VSS 17.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section 30.0 “Electrical Specifications”. 17.3 DAC Voltage Reference Output The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to ‘1’. Selecting the DAC reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure 17-2 shows an example buffering technique.  2010-2015 Microchip Technology Inc. DS40001413E-page 143 PIC12(L)F1822/16(L)F1823 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD 5 VREF+ R R 2 R DACEN DACLPS R R 32 Steps R 32-to-1 MUX DACPSS DACR DAC_output (To Comparator, CPS and ADC Modules) R DACOUT R DACOE VSOURCE- FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS40001413E-page 144 DACOUT + – Buffered DAC Output  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 17.4 Low-Power Voltage State In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the negative voltage source, (VSOURCE-) can be disabled. The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 17.4.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE The DAC output voltage can be set to VSOURCE+ with the least amount of power consumption by performing the following: • Clearing the DACEN bit in the DACCON0 register. • Setting the DACLPS bit in the DACCON0 register. • Configuring the DACPSS bits to the proper positive source. • Configuring the DACR bits to ‘11111’ in the DACCON1 register. FIGURE 17-3: This is also the method used to output the voltage level from the FVR to an output pin. See Section 17.5 “Operation During Sleep” for more information. Reference Figure 17-3 for output clamping examples. 17.4.2 OUTPUT CLAMPED TO NEGATIVE VOLTAGE SOURCE The DAC output voltage can be set to VSOURCE- with the least amount of power consumption by performing the following: • Clearing the DACEN bit in the DACCON0 register. • Clearing the DACLPS bit in the DACCON0 register. • Configuring the DACR bits to ‘00000’ in the DACCON1 register. This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC module. Reference Figure 17-3 for output clamping examples. OUTPUT VOLTAGE CLAMPING EXAMPLES Output Clamped to Positive Voltage Source VSOURCE+ Output Clamped to Negative Voltage Source VSOURCE+ R R DACR = 11111 R DACEN = 0 DACLPS = 1 R DAC Voltage Ladder (see Figure 17-1) DACEN = 0 DACLPS = 0 R VSOURCE- 17.5 DAC Voltage Ladder (see Figure 17-1) R DACR = 00000 VSOURCE- Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 17.6 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR range select bits are cleared.  2010-2015 Microchip Technology Inc. DS40001413E-page 145 PIC12(L)F1822/16(L)F1823 REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 DACEN DACLPS DACOE — R/W-0/0 R/W-0/0 DACPSS U-0 U-0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS: DAC Positive Source Select bits VDD VREF+ pin 00 = 01 = 10 = 11 = bit 1-0 FVR Buffer2 output Reserved, do not use Unimplemented: Read as ‘0’ REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DACR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR: DAC Voltage Output Select bits TABLE 17-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Bit 7 Bit 6 FVRCON FVREN DACCON0 DACEN — DACCON1 Legend: Register on page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FVRRDY TSEN TSRNG CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 128 DACLPS DACOE — DACPSS1 DACPSS0 — — 146 — — DACR4 DACR3 DACR2 DACR1 DACR0 146 — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module. DS40001413E-page 146  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 18.0 SR LATCH The module consists of a single SR latch with multiple Set and Reset inputs as well as separate latch outputs. The SR latch module includes the following features: • • • • Programmable input selection SR latch output is available externally Separate Q and Q outputs Firmware Set and Reset The SR latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications. 18.1 Latch Operation The latch is a Set-Reset Latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by: 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR latch outputs may be directly output to an I/O pin at the same time. The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver. 18.3 Effects of a Reset Upon any device Reset, the SR latch output is not initialized to a known state. The user’s firmware is responsible for initializing the latch output before enabling the output pins. • Software control (SRPS and SRPR bits) • Comparator C1 output (sync_C1OUT) • Comparator C2 output (sync_C2OUT) (PIC16(L)F1823 only) • SRI pin • Programmable clock (SRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR latch. The output of either Comparator can be synchronized to the Timer1 clock source. See Section 19.0 “Comparator Module” and Section 21.0 “Timer1 Module with Gate Control” for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR latch. An internal clock source is available that can periodically set or reset the SR latch. The SRCLK bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to Set or Reset the SR latch, respectively.  2010-2015 Microchip Technology Inc. DS40001413E-page 147 PIC12(L)F1822/16(L)F1823 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRPS Pulse Gen(2) SRLEN SRQEN SRI S SRSPE SRCLK Q SRQ SRSCKE (3, 4) SYNC_C2OUT SRSC2E(4) SYNC_C1OUT (3) SR Latch(1) SRSC1E SRPR Pulse Gen(2) SRI SRRPE SRCLK SRRCKE (3, 4) SYNC_C2OUT SRRC2E(4) SYNC_C1OUT R Q SRNQ SRLEN SRNQEN (3) SRRC1E Note 1: 2: 3: 4: DS40001413E-page 148 If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 18-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 110 256 62.5 kHz 39.0 kHz 31.3 kHz 7.81 kHz 1.95 kHz 125 kHz 78.1 kHz 62.5 kHz 15.6 kHz 3.90 kHz 101 100 128 250 kHz 156 kHz 125 kHz 31.25 kHz 7.81 kHz 64 500 kHz 313 kHz 250 kHz 62.5 kHz 15.6 kHz 011 32 1 MHz 625 kHz 500 kHz 125 kHz 31.3 kHz 010 16 2 MHz 1.25 MHz 1 MHz 250 kHz 62.5 kHz 001 8 4 MHz 2.5 MHz 2 MHz 500 kHz 125 kHz 000 4 8 MHz 5 MHz 4 MHz 1 MHz 250 kHz REGISTER 18-1: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only bit 7 SRLEN: SR Latch Enable bit 1 = SR latch is enabled 0 = SR latch is disabled bit 6-4 SRCLK: SR Latch Clock Divider bits 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock bit 3 SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = External Q output is disabled If SRLEN = 0: SR latch is disabled bit 2 SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = External Q output is disabled If SRLEN = 0: SR latch is disabled bit 1 SRPS: Pulse Set Input of the SR Latch bit(1) 1 = Pulse set input for 1 Q-clock period 0 = No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit(1) 1 = Pulse reset input for 1 Q-clock period 0 = No effect on reset input. Note 1: Set only, always reads back ‘0’.  2010-2015 Microchip Technology Inc. DS40001413E-page 149 PIC12(L)F1822/16(L)F1823 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE SRSC2E(1) SRSC1E SRRPE SRRCKE SRRC2E(1) SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR latch is set when the SRI pin is high 0 = SRI pin has no effect on the set input of the SR latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the set input of the SR latch bit 5 SRSC2E: SR Latch C2 Set Enable bit(1) 1 = SR latch is set when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the set input of the SR latch bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = SR latch is set when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the set input of the SR latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SR latch is reset when the SRI pin is high 0 = SRI pin has no effect on the reset input of the SR latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the reset input of the SR latch bit 1 SRRC2E: SR Latch C2 Reset Enable bit(1) 1 = SR latch is reset when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the reset input of the SR latch bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = SR latch is reset when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the reset input of the SR latch Note 1: PIC16(L)F1823 only. DS40001413E-page 150  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 18-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 SRCON0 SRLEN SRCLK2 SRCLK1 SRCLK0 SRQEN SRNQEN SRPS SRPR 149 SRCON1 SRSPE SRSCKE SRSC2E(1) SRSC1E SRRPE SRRCKE SRRC2E(1) SRRC1E 150 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISA Legend: Note 1: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 151 PIC12(L)F1822/16(L)F1823 19.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • • • • • • • • • Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and Fixed Voltage Reference 19.1 Comparator Overview FIGURE 19-1: SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. DS40001413E-page 152  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 19-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM (PIC12(L)F1822) CxNCH C1ON(1) 2 C1INTP Interrupt det C1IN0- Set C1IF 0 (2) C1IN1- det 1 C1POL C1VN D Cx(3) C1VP DAC_output 0 MUX 1 (2) FVR Buffer2 2 C1IN+ C1OUT MC1OUT Q To Data Bus + EN Q1 C1HYS C1SP To ECCP PWM Logic 3 C1SYNC C1ON VSS C1INTN Interrupt MUX C1PCH 0 C1OE TRIS bit C1OUT 2 D (from Timer1) T1CLK Q 1 To Timer1 or SR Latch sync_C1OUT Note 1: 2: 3: When C1ON = 0, the Comparator will produce a ‘0’ at the output. When C1ON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging.  2010-2015 Microchip Technology Inc. DS40001413E-page 153 PIC12(L)F1822/16(L)F1823 FIGURE 19-3: COMPARATOR 1 AND 2 MODULES SIMPLIFIED BLOCK DIAGRAM (PIC16(L)F1823) CxNCH CxON(1) 2 CxINTP Interrupt det C12IN0- 0 C12IN1- 1 MUX 2 (2) C12IN2C12IN3- 3 Set CxIF det CXPOL CxVN D Cx(3) CxVP DAC_output 0 MUX 1 (2) FVR Buffer2 2 CXIN+ CXOUT MCXOUT Q To Data Bus + EN Q1 CxHYS CxSP To ECCP PWM Logic 3 CXSYNC CxON VSS CxINTN Interrupt CXPCH 0 CXOE TRIS bit CXOUT 2 D (from Timer1) T1CLK Note 1: 2: 3: Q 1 To Timer1 or SR Latch sync_CxOUT When CxON = 0, the Comparator will produce a ‘0’ at the output. When CxON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging. DS40001413E-page 154  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 19.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 18-1) contain Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization The CMxCON1 registers (see Register 18-2) contain Control bits for the following: • • • • Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 19.2.1 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 19.2.2 COMPARATOR OUTPUT SELECTION 19.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 19-1 shows the output state versus input conditions, including polarity control. TABLE 19-1: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 19.2.4 COMPARATOR SPEED/POWER SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.  2010-2015 Microchip Technology Inc. DS40001413E-page 155 PIC12(L)F1822/16(L)F1823 19.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. 19.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a Falling edge detector are present. See Section 30.0 “Electrical Specifications” for more information. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 19.4 To enable the interrupt, you must set the following bits: Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 21.6 “Timer1 Gate” for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 19.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagrams (Figures 19-2 and 19-3) and the Timer1 Block Diagram (Figure 21-1) for more information. • CxON, CxPOL and CxSP bits of the CMxCON0 register • CxIE bit of the PIE2 register • CxINTP bit of the CMxCON1 register (for a rising edge detection) • CxINTN bit of the CMxCON1 register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: 19.6 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. Comparator Positive Input Selection Configuring the CxPCH bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • • • • C1IN+ or C2IN+ analog pin DAC_output FVR Buffer2 VSS (Ground) See Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. DS40001413E-page 156  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 19.7 Comparator Negative Input Selection The CxNCH bits of the CMxCON0 register direct one of four analog pins to the comparator inverting input. Note: 19.8 To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 30.0 “Electrical Specifications” for more details. 19.9 Interaction with ECCP Logic 19.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparator signals. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM. Note: When the Comparator module is first initialized the output state is unknown. Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP Auto-Shutdown mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 157 PIC12(L)F1822/16(L)F1823 FIGURE 19-4: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT  0.6V RIC To Comparator VA CPIN 5 pF VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Source Impedance RS = Analog Voltage VA = Threshold Voltage VT Note 1: DS40001413E-page 158 See Section 30.0 “Electrical Specifications”  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 19-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous.  2010-2015 Microchip Technology Inc. DS40001413E-page 159 PIC12(L)F1822/16(L)F1823 REGISTER 19-2: R/W-0/0 CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 CxINTP R/W-0/0 CxINTN R/W-0/0 CxPCH U-0 — U-0 — R/W-0/0 (1) CxNCH1 bit 7 R/W-0/0 CxNCH0 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH: Comparator Positive Input Channel Select bits 00 = CxVP connects to CxIN+ pin 01 = CxVP connects to DAC Voltage Reference 10 = CxVP connects to FVR Voltage Reference 11 = CxVP connects to VSS bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CxNCH: Comparator Negative Input Channel Select bits PIC12(L)F1822: 0 = C1VN connects to C1IN0- pin 1 = C1VN connects to C1IN1- pin PIC16(L)F1823: 00 = CxVN connects to C12IN0- pin 01 = CxVN connects to C12IN1- pin 10 = CxVN connects to C12IN2- pin 11 = CxVN connects to C12IN3- pin Note 1: PIC16(L)F1823 only. REGISTER 19-3: U-0 CMOUT: COMPARATOR OUTPUT REGISTER U-0 — U-0 — — U-0 — U-0 — U-0 R-0/0 R-0/0 — MC2OUT(1) MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit(1) bit 0 MC1OUT: Mirror Copy of C1OUT bit Note 1: PIC16(L)F1823 only. DS40001413E-page 160  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 19-2: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 159 CM1CON1 C1INTP C1INTN C1PCH1 C1PCH0 — — C1NCH1(1) C1NCH0 160 CM2CON0(1) C2ON C2OUT C2OE C2POL — C2SP C2HYS C2SYNC 159 CM2CON1(1) C2INTP C2INTN C2PCH1 C2PCH0 — — C2NCH1 C2NCH0 160 CMOUT — — — — — — MC2OUT(1) MC1OUT 160 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 87 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TRISA TRISC(1) Legend: Note 1: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 161 PIC12(L)F1822/16(L)F1823 20.0 20.1.2 TIMER0 MODULE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. The Timer0 module is an 8-bit timer/counter with the following features: • • • • • • 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘1’ and resetting the T0XCS bit in the CPSCON0 register to ‘0’. 8-Bit Counter mode using the Capacitive Sensing Oscillator (CPSCLK) signal is selected by setting the TMR0CS bit in the OPTION register to ‘1’ and setting the T0XCS bit in the CPSCON0 register to ‘1’. Figure 20-1 is a block diagram of the Timer0 module. 20.1 The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION register. Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 20.1.1 8-BIT COUNTER MODE 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 0 From CPSCLK Sync 2 TCY 1 TMR0 0 1 TMR0SE TMR0CS 8-bit Prescaler PSA T0XCS Set Flag bit TMR0IF on Overflow Overflow to Timer1 8 PS DS40001413E-page 162  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 20.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 20.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 163 PIC12(L)F1822/16(L)F1823 REGISTER 20-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS: Prescaler Rate Select bits TABLE 20-1: Name CPSCON0 INTCON TRISA Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 CPSON CPSRM — — GIE PEIE TMR0IE INTE OPTION_REG WPUEN TMR0 Bit Value INTEDG TMR0CS TMR0SE Bit 3 Bit 2 Bit 1 CPSRNG1 CPSRNG0 CPSOUT Bit 0 Register on Page T0XCS 302 IOCIE TMR0IF INTF IOCIF 86 PSA PS2 PS1 PS0 164 TRISA3 TRISA2 TRISA1 TRISA0 Timer0 Module Register — — TRISA5 162* TRISA4 117 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. DS40001413E-page 164  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 21.0 • • • • TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: Figure 21-1 is a block diagram of the Timer1 module. • • • • • • • • 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with CCP/ECCP) • Selectable Gate Source Polarity FIGURE 21-1: Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt TIMER1 BLOCK DIAGRAM T1GSS T1G T1GSPM 00 From Timer0 Overflow 01 Comparator 1 sync_C1OUT 10 Comparator 2 sync_C2OUT 11 0 T1G_IN T1GVAL 0 Single Pulse TMR1ON T1GPOL D Q CK R Q 1 Acq. Control 1 Q1 Data Bus D Q RD T1GCON EN Interrupt T1GGO/DONE Set TMR1GIF det T1GTM TMR1GE Set flag bit TMR1IF on Overflow TMR1ON To Comparator Module TMR1(2) TMR1H EN TMR1L Q D T1CLK Synchronized clock input 0 1 TMR1CS T1OSO OUT T1OSC T1OSI Cap. Sensing Oscillator T1SYNC 11 1 Synchronize(3) Prescaler 1, 2, 4, 8 det 10 EN 0 T1OSCEN (1) FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 T1CKPS FOSC/2 Internal Clock Sleep input T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2010-2015 Microchip Technology Inc. DS40001413E-page 165 PIC12(L)F1822/16(L)F1823 21.1 Timer1 Operation 21.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 21-2 displays the clock source selections. 21.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 21-1 displays the Timer1 enable selections. TABLE 21-1: Clock Source Selection TIMER1 ENABLE SELECTIONS The following asynchronous sources may be used: • Asynchronous event on the T1G pin to Timer1 Gate • C1 or C2 comparator input to Timer1 Gate Timer1 Operation TMR1ON TMR1GE 0 0 Off 0 1 Off 21.2.2 1 0 Always On 1 1 Count Enabled When the external clock source is selected, the Timer1 module may work as a timer or a counter. EXTERNAL CLOCK SOURCE When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • • TABLE 21-2: Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. CLOCK SOURCE SELECTIONS TMR1CS1 TMR1CS0 T1OSCEN 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 1 x Capacitive Sensing Oscillator 1 0 0 External Clocking on T1CKI Pin 1 0 1 Osc.Circuit On T1OSI/T1OSO Pins DS40001413E-page 166 Clock Source  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 21.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 21.6 Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 Gate can also be driven by multiple selectable sources. 21.6.1 21.4 Timer1 Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. Note: 21.5 The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 21.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: 21.5.1 When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. Timer1 Gate TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 21-3 for timing details. TABLE 21-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G  0 0 Counts  0 1 Holds Count  1 0 Holds Count  1 1 Counts 21.6.2 Timer1 Operation TIMER1 GATE SOURCE SELECTION The Timer1 Gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 21-4: T1GSS TIMER1 GATE SOURCES Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 10 Comparator 1 Output sync_C1OUT (optionally Timer1 synchronized output) 11 Comparator 2 Output sync_C2OUT (optionally Timer1 synchronized output) For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.  2010-2015 Microchip Technology Inc. DS40001413E-page 167 PIC12(L)F1822/16(L)F1823 21.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 Gate circuitry. 21.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 Gate circuitry. 21.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 Gate Control. The Comparator 1 output (sync_C1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 19.4.1 “Comparator Output Synchronization”. 21.6.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1 Gate Control. The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 19.4.1 “Comparator Output Synchronization”. 21.6.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 Gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 21-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 21.6.4 TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure 21-5 for timing details. If the Single Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 Gate source to be measured. See Figure 21-6 for timing details. 21.6.5 TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). 21.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. DS40001413E-page 168  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 21.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Note: 21.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • 21.9 ECCP/CCP Capture/Compare Time Base The CCP1 module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see “Capture/Compare/PWM Modules”. Section 24.0 21.10 ECCP/CCP Special Event Trigger When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured • T1OSCEN bit of the T1CON register must be configured Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. For more information, see Section 16.2.5 “Special Event Trigger”. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 21-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010-2015 Microchip Technology Inc. DS40001413E-page 169 PIC12(L)F1822/16(L)F1823 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 N DS40001413E-page 170 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software  2010-2015 Microchip Technology Inc. N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software DS40001413E-page 171 PIC12(L)F1822/16(L)F1823 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF DS40001413E-page 172 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL N+4 Cleared by software  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 21.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 21-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 21-1: R/W-0/u T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u TMR1CS R/W-0/u T1CKPS R/W-0/u R/W-0/u U-0 R/W-0/u T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS: Timer1 Clock Source Select bits 11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS = 0X This bit is ignored. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop  2010-2015 Microchip Technology Inc. DS40001413E-page 173 PIC12(L)F1822/16(L)F1823 21.12 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 21-2, is used to control Timer1 Gate. REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 11 = Comparator 2 optionally synchronized output (sync_C2OUT) DS40001413E-page 174  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 21-5: Name ANSELA CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 213 86 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register INTCON TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL 169* 169* TRISA1 TRISA0 117 — TMR1ON 173 T1GSS1 T1GSS0 174 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 175 PIC12(L)F1822/16(L)F1823 22.0 TIMER2 MODULE The Timer2 module incorporate the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP1 modules (Timer2 only) See Figure 22-1 for a block diagram of Timer2. FIGURE 22-1: TIMER2 BLOCK DIAGRAM TMR2 Output FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 2 TMR2 Comparator Sets Flag bit TMR2IF Reset EQ Postscaler 1:1 to 1:16 T2CKPS PR2 4 T2OUTPS DS40001413E-page 176  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 22.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output Section 22.2 “Timer2 counter/postscaler (see Interrupt”). 22.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP1 module, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP1 module operating in SPI mode. Additional information is provided in Section 25.1 “Master SSP (MSSP1) Module Overview” 22.4 Timer2 Operation During Sleep The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode. The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • • • • • • • • • a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: 22.2 TMR2 is not cleared when T2CON is written. Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS, of the T2CON register.  2010-2015 Microchip Technology Inc. DS40001413E-page 177 PIC12(L)F1822/16(L)F1823 REGISTER 22-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 T2OUTPS R/W-0/0 R/W-0/0 TMR2ON bit 7 R/W-0/0 T2CKPS bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 DS40001413E-page 178  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 PR2 Timer2 Module Period Register PIE1 T2CON TMR2 — T2OUTPS 176* TMR2ON T2CKPS1 T2CKPS0 Holding Register for the 8-bit TMR2 Register 178 176* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information.  2010-2015 Microchip Technology Inc. DS40001413E-page 179 PIC12(L)F1822/16(L)F1823 23.0 Using this method, the DSM can generate the following types of Key Modulation schemes: DATA SIGNAL MODULATOR The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. • • • • • • • The modulated output signal is generated by performing a logical “AND” operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. FIGURE 23-1: Carrier Synchronization Carrier Source Polarity Select Carrier Source Pin Disable Programmable Modulator Data Modulator Source Pin Disable Modulated Output Polarity Select Slew Rate Control Figure 23-1 shows a Simplified Block Diagram of the Data Signal Modulator peripheral. SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH VSS MDCIN1 MDCIN2 CLKR CCP1 CCP2 CCP3 CCP4 Reserved No Channel Selected MDEN 0000 0001 0010 0011 0100 0101 CARH 0110 0111 1000 * * 1111 EN Data Signal Modulator MDCHPOL D SYNC MDMS MDBIT MDMIN CCP1 CCP2 CCP3 CCP4 Comparator C1 Comparator C2 MSSP1 SDO1 MSSP2 SDO2 EUSART Reserved No Channel Selected Q 0000 0001 0010 0011 0100 0101 0110 MOD 0111 1000 1001 1010 0011 * * 1111 1 0 MDCHSYNC MDOUT MDOPOL MDOE D SYNC MDCL VSS MDCIN1 MDCIN2 CLKR CCP1 CCP2 CCP3 CCP4 Reserved No Channel Selected Q 0000 0001 0010 0011 0100 0101 CARL 0110 0111 1000 * * 1111 DS40001413E-page 180 1 0 MDCLSYNC MDCLPOL  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 23.1 DSM Operation The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current. The values used to select the carrier high, carrier low, and modulator sources held by the Modulation Source, Modulation High Carrier, and Modulation Low Carrier control registers are not affected when the MDEN bit is cleared and the DSM module is disabled. The values inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, carrier low and modulator signals will once again be selected when the MDEN bit is set and the DSM module is again enabled and active. The modulated output signal can be disabled without shutting down the DSM module. The DSM module will remain active and continue to mix signals, but the output value will not be sent to the MDOUT pin. During the time that the output is disabled, the MDOUT pin will remain low. The modulated output can be disabled by clearing the MDOE bit in the MDCON register. 23.2 Modulator Signal Sources The modulator signal can be supplied from the following sources: • • • • • • • CCP1 Signal MSSP1 SDO1 Signal (SPI mode Only) Comparator C1 Signal Comparator C2 Signal (PIC16(L)F1823 only) EUSART TX Signal External Signal on MDMIN pin MDBIT bit in the MDCON register 23.3 Carrier Signal Sources The carrier high signal and carrier low signal can be supplied from the following sources: • • • • • CCP1 Signal Reference Clock Module Signal External Signal on MDCIN1 pin External Signal on MDCIN2 pin VSS The carrier high signal is selected by configuring the MDCH bits in the MDCARH register. The carrier low signal is selected by configuring the MDCL bits in the MDCARL register. 23.4 Carrier Synchronization During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal can be enabled by setting the MDCHSYNC bit in the MDCARH register. Synchronization for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 23-1 through Figure 23-5 show timing diagrams of using various synchronization methods. The modulator signal is selected by configuring the MDMS bits in the MDSRC register.  2010-2015 Microchip Technology Inc. DS40001413E-page 181 PIC12(L)F1822/16(L)F1823 FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State FIGURE 23-3: CARH CARL CARH CARL CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier State DS40001413E-page 182 CARH both CARL CARH both CARL  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State FIGURE 23-5: CARH CARL CARH CARL FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Falling edges used to sync Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State CARH  2010-2015 Microchip Technology Inc. CARL CARH CARL DS40001413E-page 183 PIC12(L)F1822/16(L)F1823 23.5 Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register. 23.6 Carrier Source Pin Disable Some peripherals assert control over their corresponding output pin when they are enabled. For example, when the CCP1 module is enabled, the output of CCP1 is connected to the CCP1 pin. This default connection to a pin can be disabled by setting the MDCHODIS bit in the MDCARH register for the carrier high source and the MDCLODIS bit in the MDCARL register for the carrier low source. 23.7 Programmable Modulator Data The MDBIT of the MDCON register can be selected as the source for the modulator signal. This gives the user the ability to program the value used for modulation. 23.8 23.9 Modulated Output Polarity The modulated output signal provided on the MDOUT pin can also be inverted. Inverting the modulated output signal is enabled by setting the MDOPOL bit of the MDCON register. 23.10 Slew Rate Control The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register. 23.11 Operation in Sleep Mode The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep. 23.12 Effects of a Reset Upon any device Reset, the Data Signal Modulator module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. Modulator Source Pin Disable The modulator source default connection to a pin can be disabled by setting the MDMSODIS bit in the MDSRC register. DS40001413E-page 184  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0 MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output enabled 0 = Modulator pin output disabled bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting enabled 0 = MDOUT pin slew rate limiting disabled bit 4 MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted bit 3 MDOUT: Modulator Output bit Displays the current output value of the Modulator module.(1) bit 2-1 Unimplemented: Read as ‘0’ bit 0 MDBIT: Allows software to manually set modulation source input to module(2) 1 = Modulator uses High Carrier source 0 = Modulator uses Low Carrier source Note 1: 2: The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. MDBIT must be selected as the modulation source in the MDSRC register for this operation.  2010-2015 Microchip Technology Inc. DS40001413E-page 185 PIC12(L)F1822/16(L)F1823 REGISTER 23-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x/u U-0 U-0 U-0 MDMSODIS — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDMS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDMSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS) is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 MDMS Modulation Source Selection bits 1111 = Reserved. No channel connected. 1110 = Reserved. No channel connected. 1101 = Reserved. No channel connected. 1100 = Reserved. No channel connected. 1011 = Reserved. No channel connected. 1010 = EUSART TX output 1001 = Reserved. No channel selected. 1000 = MSSP1 SDO1 output 0111 = Comparator 2 output (PIC16(L)F1823 only. PIC12(L)F1822; Reserved, no channel connected.) 0110 = Comparator 1 output 0101 = Reserved. No channel connected. 0100 = Reserved. No channel connected. 0011 = Reserved. No channel connected. 0010 = CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS40001413E-page 186  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCHODIS MDCHPOL MDCHSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH) is enabled bit 6 MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 5 MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator Output is not synchronized to the high time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCH Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal (CLKR) 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.  2010-2015 Microchip Technology Inc. DS40001413E-page 187 PIC12(L)F1822/16(L)F1823 REGISTER 23-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 MDCLODIS MDCLPOL MDCLSYNC — R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL of the MDCARL register) is enabled bit 6 MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted bit 5 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator Output is not synchronized to the low time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCL Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = Reserved. No channel connected. 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS40001413E-page 188  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 23-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE Bit 3 Bit 6 Bit 5 Bit 4 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 ANSELC(1) — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH 187 MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL 188 MDCON MDEN MDOE MDSLR MDOPOL MDSRC MDMSODIS — — — MDOUT Bit 2 — Bit 1 Bit 0 Register on Page Bit 7 MDBIT — MDMS 185 186 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 119 WPUC(1) — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 122 Legend: Note 1: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 189 PIC12(L)F1822/16(L)F1823 24.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains one Enhanced Capture/ Compare/PWM module (ECCP1). The Full-Bridge ECCP module has four available I/O pins, while the Half-Bridge ECCP module only has two. See Table 24-1. TABLE 24-1: PWM RESOURCES Device Name ECCP1 PIC12(L)F1822 Enhanced PWM Half-Bridge PIC16(L)F1823 Enhanced PWM Full-Bridge DS40001413E-page 190  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.1 24.1.2 Capture Mode Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCP1 pin, the 16-bit CCPR1H:CCPR1L register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCP1M bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value. Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP1 module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section 21.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. 24.1.3 Note: CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. Also, the CCP1 pin function may be moved to alternative pins using the APFCON register. Refer to Section 12.1 “Alternate Pin Function” for more details. Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition. FIGURE 24-1: Prescaler  1, 4, 16 CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF (PIR1 register) CCP1 pin 24.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCP1 pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP1 PRESCALER There are four prescaler settings specified by the CCP1M bits of the CCP1CON register. Whenever the CCP1 module is turned off, or the CCP1 module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler. Example 24-1 demonstrates the code to perform this function. EXAMPLE 24-1: CHANGING BETWEEN CAPTURE PRESCALERS BANKSEL CCP1CON CCPR1H and Edge Detect SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in Operating mode. Figure 24-1 shows a simplified diagram of the Capture operation. 24.1.1 TIMER1 MODE RESOURCE CCPR1L Capture Enable TMR1H CCP1M System Clock (FOSC)  2010-2015 Microchip Technology Inc. TMR1L CLRF MOVLW MOVWF ;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP1 module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP1 ON CCP1CON ;Load CCP1CON with this ;value DS40001413E-page 191 PIC12(L)F1822/16(L)F1823 24.1.5 CAPTURE DURING SLEEP 24.1.6 Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 “Alternate Pin Function” for more information. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. TABLE 24-2: Name APFCON SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) CCP1CON P1M DC1B CCPR1L Capture/Compare/PWM Register x Low Byte (LSB) CCPR1H Capture/Compare/PWM Register x High Byte (MSB) CCP1M Register on Page 114 213 191 191 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 T1OSCEN T1SYNC — TMR1ON 173 T1GGO/DONE T1GVAL INTCON T1CON T1GCON TMR1CS TMR1GE T1GPOL T1CKPS T1GTM T1GSPM TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1GSS 174 169 169 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 192  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.2 24.2.2 Compare Mode Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPR1H:CCPR1L register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt TIMER1 MODE RESOURCE In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 21.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. Note: The action on the pin is based on the value of the CCP1M control bits of the CCP1CON register. At the same time, the interrupt flag CCP1IF bit is set. Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCP1 pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. All Compare modes can generate an interrupt. 24.2.3 Figure 24-2 shows a simplified diagram of the Compare operation. When Generate Software Interrupt mode is chosen (CCP1M = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register). FIGURE 24-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCP1M Mode Select Set CCP1IF Interrupt Flag (PIR1) 4 CCPR1H CCPR1L CCP1 Pin Q S R Output Logic Match TRIS Output Enable Comparator TMR1H TMR1L Special Event Trigger 24.2.1 CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Also, the CCP1 pin function may be moved to alternative pins using the APFCON register. Refer to Section 12.1 “Alternate Pin Function” for more details. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch. 24.2.4 SOFTWARE INTERRUPT MODE SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCP1M = 1011), the CCP1 module does the following: • Resets Timer1 • Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode. The Special Event Trigger output of the CCP1 occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. TABLE 24-3: SPECIAL EVENT TRIGGER Device CCP1/ECCP1 PIC12(L)F1822/16(L)F1823 CCP1 Refer to Section 16.0 “Analog-to-Digital Converter (ADC) Module” for more information. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.  2010-2015 Microchip Technology Inc. DS40001413E-page 193 PIC12(L)F1822/16(L)F1823 24.2.5 COMPARE DURING SLEEP 24.2.6 The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. TABLE 24-4: Name APFCON This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 “Alternate Pin Function” for more information. SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 CCP1CON P1M DC1B CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) INTCON ALTERNATE PIN LOCATIONS CCP1M 213 191 191 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 T1OSCEN T1SYNC — TMR1ON 173 T1GGO/DONE T1GVAL T1CON T1GCON TMR1CS TMR1GE T1GPOL T1CKPS T1GTM T1GSPM TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1GSS 174 169 169 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 194  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. FIGURE 24-3: CCP1 PWM OUTPUT SIGNAL Period Pulse Width TMR2 = PR2 TMR2 = CCPR1H:CCP1CON TMR2 = 0 FIGURE 24-4: SIMPLIFIED PWM BLOCK DIAGRAM PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. Duty Cycle Registers The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. CCPR1H(2) (Slave) CCP1CON CCPR1L CCP1 R Comparator TMR2 (1) Q S Figure 24-3 shows a typical waveform of the PWM signal. TRIS Comparator 24.3.1 STANDARD PWM OPERATION The standard PWM mode generates a Pulse-Width modulation (PWM) signal on the CCP1 pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • PR2 registers T2CON registers CCPR1L registers CCP1CON registers PR2 Note 1: 2: Clear Timer, toggle CCP1 pin and latch duty cycle The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register. Figure 24-4 shows a simplified block diagram of PWM operation. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCP1 pin. 2: Clearing the CCP1CON register will relinquish control of the CCP1 pin.  2010-2015 Microchip Technology Inc. DS40001413E-page 195 PIC12(L)F1822/16(L)F1823 24.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP1 module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCP1 pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP1 module for the PWM mode by loading the CCP1CON register with the appropriate values. Load the CCPR1L register and the DC1B1 bits of the CCP1CON register, with the PWM duty cycle value. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. • Configure the T2CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR1 register is set. See Note below. • Enable the CCP1 pin output driver by clearing the associated TRIS bit. Note: 24.3.3 In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPR1L into CCPR1H. Note: 24.3.4 The Timer postscaler (see Section 22.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 24-2 is used to calculate the PWM pulse width. Equation 24-3 is used to calculate the PWM duty cycle ratio. EQUATION 24-2: PULSE WIDTH Pulse Width =  CCPR1L:CCP1CON   T OSC  (TMR2 Prescale Value) PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 24-1. EQUATION 24-1: PWM PERIOD PWM Period =   PR2  + 1   4  T OSC  (TMR2 Prescale Value) Note 1: TOSC = 1/FOSC EQUATION 24-3: DUTY CYCLE RATIO  CCPRxL:CCPxCON  Duty Cycle Ratio = ----------------------------------------------------------------------4  PRx + 1  The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure 24-4). DS40001413E-page 196  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.3.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 24-4. EQUATION 24-4: PWM RESOLUTION log  4  PR2 + 1   Resolution = ------------------------------------------ bits log  2  Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 24-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency 1.95 kHz Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 24-6: 31.25 kHz 125 kHz 250 kHz 333.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 24-7: 7.81 kHz EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)  2010-2015 Microchip Technology Inc. 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 DS40001413E-page 197 PIC12(L)F1822/16(L)F1823 24.3.6 OPERATION IN SLEEP MODE 24.3.9 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 24.3.7 CHANGES IN SYSTEM CLOCK FREQUENCY ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 “Alternate Pin Function” for more information. The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 24.3.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 24-8: Name APFCON SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 CCP1CON CCPR1L INTCON P1M DC1B CCP1M 213 Capture/Compare/PWM Register x Low Byte (LSB) 191 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PR2 T2CON TMR2 Timer2 Period Register — 86 176* T2OUTPS TMR2ON T2CKPS1 Timer2 Module Register 178 176* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 198  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.4 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the bits CCP1M in the CCP1CON register appropriately. PWM (Enhanced Mode) The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal on up to four different output pins with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • Figure 24-5 shows an example of a simplified block diagram of the Enhanced PWM module. PR2 registers T2CON registers CCPR1L registers CCP1CON registers Table 24-9 shows the pin assignments for various Enhanced PWM modes. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCP1 pin. The ECCP modules have the following additional PWM registers which control Auto-shutdown, Auto-restart, Dead-band Delay and PWM Steering modes: 2: Clearing the CCP1CON register will relinquish control of the CCP1 pin. • CCP1AS registers • PSTR1CON registers • PWM1CON registers 3: Any pin not used in the enhanced PWM mode is available for alternate pin functions, if applicable. The enhanced PWM module can generate the following four PWM Output modes: • • • • 4: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. Single PWM Half-Bridge PWM Full-Bridge PWM (PIC16(L)F1823 only) Single PWM with PWM Steering mode To select an Enhanced PWM Output mode, the P1M bits of the CCP1CON register must be configured appropriately. FIGURE 24-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE Duty Cycle Registers DC1B CCP1M 4 P1M 2 CCPR1L CCP1/P1A CCP1/P1A TRISx CCPR1H (Slave) P1B R Comparator Q Output Controller P1B TRISx P1C(2) TMR2 Comparator PR2 Note (1) P1C(2) TRISx S P1D(2) Clear Timer, toggle PWM pin and latch duty cycle P1D(2) TRISx PWM1CON 1: The 8-bit timer TMR1 register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time base. 2: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 199 PIC12(L)F1822/16(L)F1823 TABLE 24-9: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode Single Half-Bridge P1M CCP1/P1A P1B P1C(2) P1D(2) 00 Yes(1) Yes(1) Yes(1) Yes(1) 10 Yes Yes No No Forward(2) 01 Yes Yes Yes Yes Full-Bridge, Reverse(2) 11 Yes Yes Yes Yes Full-Bridge, Note 1: 2: PWM Steering enables outputs in Single mode. PIC16(L)F1823 only. FIGURE 24-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) PxM Signal PRX+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated Delay Delay PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON) DS40001413E-page 200  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 24-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM Signal PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay Delay PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON)  2010-2015 Microchip Technology Inc. DS40001413E-page 201 PIC12(L)F1822/16(L)F1823 24.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 24-9). This mode can be used for Half-Bridge applications, as shown in Figure 24-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in HalfBridge power devices. The value of the PDC bits of the PWM1CON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 24.4.5 “Programmable Dead-Band Delay Mode” for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. FIGURE 24-8: Period Period Pulse Width P1A(2) td td P1B(2) (1) (1) (1) td = Dead-Band Delay Note 1: 2: FIGURE 24-9: EXAMPLE OF HALFBRIDGE PWM OUTPUT At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver FET Driver P1A FET Driver Load FET Driver P1B DS40001413E-page 202  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.4.2 FULL-BRIDGE MODE (PIC16(L)F1823 ONLY) In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 24-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 24-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 24-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. FIGURE 24-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D  2010-2015 Microchip Technology Inc. DS40001413E-page 203 PIC12(L)F1822/16(L)F1823 FIGURE 24-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high. DS40001413E-page 204  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register. The following sequence occurs four Timer cycles prior to the end of the current PWM period: • The modulated outputs (P1B and P1D) are placed in their inactive state. • The associated unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. • PWM modulation resumes at the beginning of the next period. See Figure 24-12 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. Figure 24-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output P1A and P1D become inactive, while output P1C becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 24-10) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 24-12: EXAMPLE OF PWM DIRECTION CHANGE Period(1) Signal Period P1A (Active-High) P1B (Active-High) Pulse Width P1C (Active-High) (2) P1D (Active-High) Pulse Width Note 1: 2: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer counts.  2010-2015 Microchip Technology Inc. DS40001413E-page 205 PIC12(L)F1822/16(L)F1823 FIGURE 24-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: T = TOFF – TON All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. DS40001413E-page 206  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.4.3 ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the CCP1ASE bit is disabled while an auto-shutdown condition persists. The auto-shutdown sources are selected using the CCP1AS bits of the CCP1AS register. A shutdown event may be generated by: 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period. • A logic ‘0’ on the FLT0 pin • A logic ‘1’ on a Comparator (C1) output 4: Prior to an auto-shutdown event caused by a comparator output or FLT0 pin event, a software shutdown can be triggered in firmware by setting the CCP1ASE bit of the CCP1AS register to ‘1’. The autorestart feature tracks the active status of a shutdown caused by a comparator output or FLT0 pin event only. If it is enabled at this time, it will immediately clear this bit and restart the ECCP module at the beginning of the next PWM period. A shutdown condition is indicated by the CCP1ASE (Auto-Shutdown Event Status) bit of the CCP1AS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The CCP1ASE bit is set to ‘1’. The CCP1ASE will remain set until cleared in firmware or an auto-restart occurs (see Section 24.4.4 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSS1AC and PSS1BD bits of the CCP1AS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) FIGURE 24-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (P1RSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCP1ASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCP1ASE bit Shutdown Event Occurs  2010-2015 Microchip Technology Inc. Shutdown Event Clears PWM Resumes CCP1ASE Cleared by Firmware DS40001413E-page 207 PIC12(L)F1822/16(L)F1823 24.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit in the PWM1CON register. If auto-restart is enabled, the CCP1ASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCP1ASE bit will be cleared via hardware and normal operation will resume. FIGURE 24-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (P1RSEN = 1) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCP1ASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCP1ASE bit PWM Resumes Shutdown Event Occurs Shutdown Event Clears DS40001413E-page 208 CCP1ASE Cleared by Hardware  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 24-16: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. Period Period Pulse Width P1A(2) td td P1B(2) (1) (1) (1) td = Dead-Band Delay Note 1: 2: In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 24-16 for illustration. The lower seven bits of the associated PWM1CON register (Register 24-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 24-17: EXAMPLE OF HALFBRIDGE PWM OUTPUT At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + V - P1A Load FET Driver + V - P1B V-  2010-2015 Microchip Technology Inc. DS40001413E-page 209 PIC12(L)F1822/16(L)F1823 24.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCP1M = 11 and P1M = 00 of the CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR1 bits of the PSTR1CON register, as shown in Table 24-9. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, the CCP1M bits of the CCP1CON register determine the polarity of the output pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section 24.4.3 “Enhanced PWM Auto-shutdown mode”. An autoshutdown event will only affect pins that have PWM outputs enabled. FIGURE 24-18: SIMPLIFIED STEERING BLOCK DIAGRAM STR1A P1A Signal CCP1M1 1 PORT Data 0 P1A pin STR1B CCP1M0 1 PORT Data 0 STR1C CCP1M1 1 PORT Data 0 PORT Data P1B pin TRIS P1C pin(3) TRIS STR1D CCP1M0 TRIS P1D pin(3) 1 0 TRIS DS40001413E-page 210 Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M = 00 and CCP1M = 11. 2: Single PWM output requires setting at least one of the STR1 bits. 3: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 24.4.6.1 Steering Synchronization The STR1SYNC bit of the PSTR1CON register gives the user two selections of when the steering event will happen. When the STR1SYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTR1CON register. In this case, the output signal at the output pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STR1SYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 24-19 and 24-20 illustrate the timing diagrams of the PWM steering depending on the STR1SYNC setting. 24.4.7 drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. Note: START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output FIGURE 24-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STR1SYNC = 0) PWM Period PWM STR1 P1 PORT Data PORT Data P1n = PWM FIGURE 24-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STR1SYNC = 1) PWM STR1 P1 PORT Data PORT Data P1n = PWM  2010-2015 Microchip Technology Inc. DS40001413E-page 211 PIC12(L)F1822/16(L)F1823 24.4.8 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function” for more information. TABLE 24-10: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM Name APFCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) CCP1CON P1M DC1B PSS1AC 114 213 CCP1AS CCP1ASE INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PR2 CCP1AS CCP1M Register on Page PSS1BD Timer2 Period Register PSTR1CON — PWM1CON P1RSEN T2CON TMR2 — — STR1SYNC STR1D(1) STR1C(1) STR1B STR1A T2OUTPS (1) TRISC 216 215 TMR2ON T2CKPS1 Timer2 Module Register TRISA 89 176* P1DC — 214 178 176* — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. Note 1: PIC16(L)F1823 only. 2: PIC12(L)F1822 only. DS40001413E-page 212  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 24-1: R/W-00 CCP1CON: CCP1 CONTROL REGISTER R/W-0/0 R/W-0/0 P1M(1) R/W-0/0 R/W-0/0 DC1B R/W-0/0 R/W-0/0 R/W-0/0 CCP1M bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 P1M: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused PWM mode: If CCP1M = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins(1) If CCP1M = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive(1) 10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive(1) bit 5-4 DC1B: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M: ECCP1 Mode Select bits 0000 = 0001 = 0010 = 0011 = Capture/Compare/PWM off (resets ECCP1 module) Reserved Compare mode: toggle output on match Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = 1001 = 1010 = 1011 = Compare mode: initialize ECCP1 pin low; set output on compare match (set CCP1IF) Compare mode: initialize ECCP1 pin high; clear output on compare match (set CCP1IF) Compare mode: generate software interrupt only; ECCP1 pin reverts to I/O state Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D conversion if A/D module is enabled) PWM mode: 1100 = PWM mode: P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode: P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low Note 1: PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 213 PIC12(L)F1822/16(L)F1823 REGISTER 24-2: R/W-0/0 CCP1AS: CCP1 AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 CCP1ASE R/W-0/0 R/W-0/0 CCP1AS R/W-0/0 R/W-0/0 R/W-0/0 PSS1AC R/W-0/0 PSS1BD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP1ASE: CCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCP1 outputs are in shutdown state 0 = CCP1 outputs are operating bit 6-4 CCP1AS: CCP1 Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator C1 output high(1) 010 = Comparator C2 output high(1, 2) 011 = Either Comparator C1 or C2 high(1, 2) 100 = VIL on FLT0 pin 101 = VIL on FLT0 pin or Comparator C1 high(1) 110 = VIL on FLT0 pin or Comparator C2 high(1, 2) 111 = VIL on FLT0 pin or Comparator C1 or Comparator C2 high(1, 2) bit 3-2 PSS1AC: Pins P1A and P1C Shutdown State Control bits(2) 00 = Drive pins P1A and P1C to ‘0’ 01 = Drive pins P1A and P1C to ‘1’ 1x = Pins P1A and P1C tri-state bit 1-0 PSS1BD: Pins P1B and P1D Shutdown State Control bits(2) 00 = Drive pins P1B and P1D to ‘0’ 01 = Drive pins P1B and P1D to ‘1’ 1x = Pins P1B and P1D tri-state Note 1: 2: If C1SYNC is enabled, the shutdown will be delayed by Timer1. C2, P1C and P1D available on PIC16(L)F1823 only. DS40001413E-page 214  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 24-3: R/W-0/0 PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 P1RSEN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 P1DC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCP1ASE must be cleared in software to restart the PWM bit 6-0 P1DC: PWM Delay Count bits P1DC1 = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled.  2010-2015 Microchip Technology Inc. DS40001413E-page 215 PIC12(L)F1822/16(L)F1823 PSTR1CON: PWM STEERING CONTROL REGISTER(1) REGISTER 24-4: U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STR1SYNC STR1D STR1C STR1B STR1A bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STR1SYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STR1D: Steering Enable bit D(2) 1 = P1D pin has the PWM waveform with polarity control from CCP1M 0 = P1D pin is assigned to port pin bit 2 STR1C: Steering Enable bit C(2) 1 = P1C pin has the PWM waveform with polarity control from CCP1M 0 = P1C pin is assigned to port pin bit 1 STR1B: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCP1M 0 = P1B pin is assigned to port pin bit 0 STR1A: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCP1M 0 = P1A pin is assigned to port pin Note 1: 2: The PWM Steering mode is available only when the CCP1CON register bits CCP1M = 11 and P1M = 00. PIC16(L)F1823 only. DS40001413E-page 216  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 25.1 Master SSP (MSSP1) Module Overview The Master Synchronous Serial Port (MSSP1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP1 module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) The SPI interface supports the following modes and features: • • • • • Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 25-1 is a block diagram of the SPI interface module. FIGURE 25-1: MSSP1 BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSP1BUF Reg SDI SSP1SR Reg SDO bit 0 SS SS Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSP1M 4 SCK Edge Select TRIS bit  2010-2015 Microchip Technology Inc. ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud rate generator (SSP1ADD) DS40001413E-page 217 PIC12(L)F1822/16(L)F1823 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 25-2 is a block diagram of the I2C interface module in Master mode. Figure 25-3 is a diagram of the I2C interface module in Slave mode. MSSP1 BLOCK DIAGRAM (I2C™ MASTER MODE) Internal data bus Read [SSP1M 3:0] Write SSP1BUF Baud rate generator (SSP1ADD) SDA in Receive Enable (RCEN) SCL SCL in Bus Collision DS40001413E-page 218 LSb Start bit, Stop bit, Acknowledge Generate (SSP1CON2) Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Clock Cntl SSP1SR MSb (Hold off clock source) Shift Clock SDA Clock arbitrate/BCOL detect FIGURE 25-2: Set/Reset: S, P, SSP1STAT, WCOL, SSP1OV Reset SEN, PEN (SSP1CON2) Set SSP1IF, BCL1IF  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 25-3: MSSP1 BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSP1BUF Reg SCL Shift Clock SSP1SR Reg SDA MSb LSb SSP1MSK Reg Match Detect Addr Match SSP1ADD Reg Start and Stop bit Detect  2010-2015 Microchip Technology Inc. Set, Reset S, P bits (SSP1STAT Reg) DS40001413E-page 219 PIC12(L)F1822/16(L)F1823 25.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) Figure 25-1 shows the block diagram of the MSSP1 module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 25-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Master sends useful data and slave sends dummy data. • Master sends useful data and slave sends useful data. • Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure 25-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and DS40001413E-page 220  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 25.2.1 SPI MODE REGISTERS The MSSP1 module has five registers for SPI mode operation. These are: • • • • • • MSSP1 STATUS register (SSP1STAT) MSSP1 Control Register 1 (SSP1CON1) MSSP1 Control Register 3 (SSP1CON3) MSSP1 Data Buffer register (SSP1BUF) MSSP1 Address register (SSP1ADD) MSSP1 Shift register (SSP1SR) (Not directly accessible) SSP1CON1 and SSP1STAT are the control and STATUS registers in SPI mode operation. The SSP1CON1 register is readable and writable. The lower 6 bits of the SSP1STAT are read-only. The upper two bits of the SSP1STAT are read/write. In one SPI master mode, SSP1ADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 25.7 “Baud Rate Generator”. SSP1SR is the shift register used for shifting data in and out. SSP1BUF provides indirect access to the SSP1SR register. SSP1BUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSP1SR and SSP1BUF together create a buffered receiver. When SSP1SR receives a complete byte, it is transferred to SSP1BUF and the SSP1IF interrupt is set. During transmission, the SSP1BUF is not buffered. A write to SSP1BUF will write to both SSP1BUF and SSP1SR.  2010-2015 Microchip Technology Inc. 25.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSP1CON1 and SSP1STAT). These control bits allow the following to be specified: • • • • Master mode (SCK1 is the clock output) Slave mode (SCK1 is the clock input) Clock Polarity (Idle state of SCK1) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK1) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) To enable the serial port, SSP1 Enable bit, SSP1EN of the SSP1CON1 register must be set. To reset or reconfigure SPI mode, clear the SSP1EN bit, re-initialize the SSP1CONx registers and then set the SSP1EN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. DS40001413E-page 221 PIC12(L)F1822/16(L)F1823 The MSSP1 consists of a transmit/receive shift register (SSP1SR) and a buffer register (SSP1BUF). The SSP1SR shifts the data in and out of the device, MSb first. The SSP1BUF holds the data that was written to the SSP1SR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSP1BUF register. Then, the Buffer Full Detect bit, BF of the SSP1STAT register, and the interrupt flag bit, SSP1IF, are set. This double-buffering of the received data (SSP1BUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSP1BUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL, of the SSP1CON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSP1BUF register to complete successfully. FIGURE 25-5: When the application software is expecting to receive valid data, the SSP1BUF should be read before the next byte of data to transfer is written to the SSP1BUF. The Buffer Full bit, BF of the SSP1STAT register, indicates when SSP1BUF has been loaded with the received data (transmission is complete). When the SSP1BUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP1 interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSP1SR is not directly readable or writable and can only be accessed by addressing the SSP1BUF register. Additionally, the SSP1STAT register indicates the various Status conditions. SPI MASTER/SLAVE CONNECTION SPI Master SSP1M = 00xx = 1010 SPI Slave SSP1M = 010x SDI SDO Serial Input Buffer (BUF) SDI Shift Register (SSP1SR) MSb Serial Input Buffer (SSP1BUF) LSb SCK General I/O Processor 1 DS40001413E-page 222 SDO Serial Clock Slave Select (optional) Shift Register (SSP1SR) MSb LSb SCK SS Processor 2  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 25-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSP1BUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSP1SR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSP1BUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSP1CON1 register and the CKE bit of the SSP1STAT register. This then, would give waveforms for SPI communication as shown in Figure 25-6, Figure 25-8, Figure 25-9 and Figure 25-10, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSP1ADD + 1)) Figure 25-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSP1BUF is loaded with the received data is shown. FIGURE 25-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSP1BUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSP1IF SSP1SR to SSP1BUF  2010-2015 Microchip Technology Inc. DS40001413E-page 223 PIC12(L)F1822/16(L)F1823 25.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSP1IF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSP1CON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 25.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 25-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSP1CON3 register will enable writes to the SSP1BUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 25.2.5 SLAVE SELECT SYNCHRONIZATION The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSP1CON1 = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSP1CON1 = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSP1STAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSP1EN bit. DS40001413E-page 224  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 25-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Shift register SSP1SR and bit count are reset SSP1BUF to SSP1SR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF  2010-2015 Microchip Technology Inc. DS40001413E-page 225 PIC12(L)F1822/16(L)F1823 FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active DS40001413E-page 226  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP1 clock is much faster than the system clock. In Slave mode, when MSSP1 interrupts are enabled, after the master completes sending data, an MSSP1 interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP1 interrupts should be disabled. TABLE 25-1: Name ANSELA In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP1 interrupt flag bit will be set and if enabled, will wake the device. SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 118 ANSELC — — — — ANSC3 ANSC2 ANSC1 ANSC0 122 APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL(2) CCP1SEL(2) 114 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SSP1STAT 221* SSPM SDAHT SBCDE AHEN 264 DHEN 266 263 SMP CKE D/A P S R/W UA BF TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: Note * 1: 2: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode. Page provides register information. PIC16(L)F1823 only. PIC12(L)F1822 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 227 PIC12(L)F1822/16(L)F1823 25.3 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 25-11 shows the block diagram of the MSSP1 module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 25-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: • Master Transmit mode (master is transmitting data to a slave) • Master Receive mode (master is receiving data from a slave) • Slave Transmit mode (slave is transmitting data to a master) • Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS40001413E-page 228 I2C MASTER/ SLAVE CONNECTION FIGURE 25-11: SCL VDD Master Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; • Single message where a master writes data to a slave. • Single message where a master reads data from a slave. • Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. 25.3.1 Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of Clock Stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 25.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels don’t match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message.  2010-2015 Microchip Technology Inc. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. 25.4 I2C Mode Operation All MSSP1 I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 25.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 25.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C™ specification. 25.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSP1EN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. DS40001413E-page 229 PIC12(L)F1822/16(L)F1823 25.4.4 SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSP1CON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS40001413E-page 230 TABLE 25-2: TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSP1ADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.4.5 START CONDITION has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 25-13 shows wave forms for a Restart condition. 2 The I C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 25-12 shows wave forms for Start and Stop conditions. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 25.4.6 STOP CONDITION After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. 25.4.7 25.4.8 The SCIE and PCIE bits of the SSP1CON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. RESTART CONDITION A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart FIGURE 25-12: START/STOP CONDITION INTERRUPT MASKING I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 25-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition  2010-2015 Microchip Technology Inc. DS40001413E-page 231 PIC12(L)F1822/16(L)F1823 25.4.9 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSP1CON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSP1CON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSP1CON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSP1STAT register or the SSP1OV bit of the SSP1CON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSP1CON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. 25.5 I2C SLAVE MODE OPERATION The MSSP1 Slave mode operates in one of four modes selected in the SSP1M bits of SSP1CON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operated the same as the other modes with SSP1IF additionally getting set upon detection of a Start, Restart, or Stop condition. 25.5.1 SLAVE MODE ADDRESSES The SSP1ADD register (Register 25-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSP1BUF register and an interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the software that anything happened. The SSP Mask register (Register 25-5) affects the address matching process. See Section 25.5.9 “SSP1 Mask Register” for more information. 25.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 25.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSbs of the 10-bit address and stored in bits 2 and 1 of the SSP1ADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSP1ADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSP1ADD. Even if there is not an address match; SSP1IF and UA are set, and SCL is held low until SSP1ADD is updated to receive a high byte again. When SSP1ADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001413E-page 232  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSP1STAT register is cleared. The received address is loaded into the SSP1BUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSP1STAT register is set, or bit SSP1OV of the SSP1CON1 register is set. The BOEN bit of the SSP1CON3 register modifies this operation. For more information see Register 25-4. An MSSP1 interrupt is generated for each transferred data byte. Flag bit, SSP1IF, must be cleared by software. When the SEN bit of the SSP1CON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSP1CON1 register, except sometimes in 10-bit mode. See Section 25.2.3 “SPI Master Mode” for more detail. 25.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP1 module configured as an I2C Slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 25-14 and Figure 25-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears the SSP1IF bit. Software reads received address from SSP1BUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears SSP1IF. Software reads the received byte from SSP1BUF clearing BF. Steps 8-12 are repeated for all received bytes from the Master. Master sends Stop condition, setting P bit of SSP1STAT, and the bus goes Idle.  2010-2015 Microchip Technology Inc. 25.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 25-16 displays a module using both address and data holding. Figure 25-17 includes the operation with the SEN bit of the SSP1CON2 register set. 1. S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSP1IF is set and CKP cleared after the 8th falling edge of SCL. 3. Slave clears the SSP1IF. 4. Slave can look at the ACKTIM bit of the SSP1CON3 register to determine if the SSP1IF was after or before the ACK. 5. Slave reads the address value from SSP1BUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSP1IF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSP1IF. Note: SSP1IF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to Master is SSP1IF not set 11. SSP1IF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSP1CON3 to determine the source of the interrupt. 13. Slave reads the received data from SSP1BUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. DS40001413E-page 233 DS40001413E-page 234 SSP1OV BF SSP1IF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSP1BUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSP1BUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 8 D0 SSP1OV set because SSP1BUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master 9 P SSP1IF set on 9th falling edge of SCL ACK = 1 FIGURE 25-14: SCL SDA Receiving Address Bus Master sends Stop condition PIC12(L)F1822/16(L)F1823 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)  2010-2015 Microchip Technology Inc.  2010-2015 Microchip Technology Inc. CKP SSP1OV BF SSP1IF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSP1BUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSP1BUF 6 D2 7 D1 SSP1OV set because SSP1BUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to ‘1’ in software, releasing SCL 1 D7 Receive Data 8 D0 9 ACK SCL is not held low because ACK= 1 SSP1IF set on 9th falling edge of SCL P FIGURE 25-15: SDA Receive Address Bus Master sends Stop condition PIC12(L)F1822/16(L)F1823 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001413E-page 235 DS40001413E-page 236 P S ACKTIM CKP ACKDT BF SSP1IF S Receiving Address 2 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSP1IF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN = 1: CKP is cleared by hardware and SCL is stretched 1 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN = 1: CKP is cleared by hardware on 8th falling edge of SCL SSP1IF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSP1BUF 9 ACK 9 P No interrupt after not ACK from Slave ACK= 1 Master sends Stop condition FIGURE 25-16: SCL SDA Master Releases SDA to slave for ACK sequence PIC12(L)F1822/16(L)F1823 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)  2010-2015 Microchip Technology Inc.  2010-2015 Microchip Technology Inc. P S ACKTIM CKP ACKDT BF SSP1IF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSP1BUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSP1BUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSP1BUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 25-17: SCL SDA R/W = 0 Master releases SDA to slave for ACK sequence PIC12(L)F1822/16(L)F1823 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) DS40001413E-page 237 PIC12(L)F1822/16(L)F1823 25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSP1STAT register is set. The received address is loaded into the SSP1BUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 25-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 25.5.6 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSP1BUF register which also loads the SSP1SR register. Then the SCL pin should be released by setting the CKP bit of the SSP1CON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSP1CON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes Idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSP1BUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP1 interrupt is generated for each data transfer byte. The SSP1IF bit must be cleared by software and the SSP1STAT register is used to determine the status of the byte. The SSP1IF bit is set on the falling edge of the ninth clock pulse. 25.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSP1CON3 register is set, the BCL1IF bit of the PIRx register is set. Once a bus collision is detected, the slave goes Idle and waits to be addressed again. User software can use the BCL1IF bit to handle a slave bus collision. DS40001413E-page 238 Master sends a Start condition on SDA and SCL. 2. S bit of SSP1STAT is set; SSP1IF is set if interrupt-on-Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSP1IF bit. 4. Slave hardware generates an ACK and sets SSP1IF. 5. SSP1IF bit is cleared by user. 6. Software reads the received address from SSP1BUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSP1BUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSP1IF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSP1IF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSP1IF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed.  2010-2015 Microchip Technology Inc.  2010-2015 Microchip Technology Inc. P S D/A R/W ACKSTAT CKP BF SSP1IF S Receiving Address 1 2 5 6 7 8 Indicates an address has been received R/W is copied from the matching address byte 9 R/W = 1 Automatic ACK Received address is read from SSP1BUF 4 When R/W is set SCL is always held low after 9th SCL falling edge 3 A7 A6 A5 A4 A3 A2 A1 Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSP1BUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P FIGURE 25-18: SCL SDA Master sends Stop condition PIC12(L)F1822/16(L)F1823 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) DS40001413E-page 239 PIC12(L)F1822/16(L)F1823 25.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSP1CON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure 25-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSP1STAT is set; SSP1IF is set if interrupt-on-Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSP1IF interrupt is generated. 4. Slave software clears SSP1IF. 5. Slave software reads ACKTIM bit of SSP1CON3 register, and R/W and D/A of the SSP1STAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSP1BUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSP1CON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSP1IF after the ACK if the R/W bit is set. 11. Slave software clears SSP1IF. 12. Slave loads value to transmit to the master into SSP1BUF setting the BF bit. Note: SSP1BUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSP1CON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus, allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001413E-page 240  2010-2015 Microchip Technology Inc.  2010-2015 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSP1IF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSP1BUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSP1BUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCL Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master’s ACK response is copied to SSP1STAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 25-19: SCL SDA Master releases SDA to slave for ACK sequence PIC12(L)F1822/16(L)F1823 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) DS40001413E-page 241 PIC12(L)F1822/16(L)F1823 25.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP1 module configured as an I2C Slave in 10-bit Addressing mode. Figure 25-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSP1STAT is set; SSP1IF is set if interrupt-on-Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSP1STAT register is set. Slave sends ACK and SSP1IF is set. Software clears the SSP1IF bit. Software reads received address from SSP1BUF clearing the BF flag. Slave loads low address into SSP1ADD, releasing SCL. Master sends matching low address byte to the Slave; UA bit is set. 25.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSP1ADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 25-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 25-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSP1ADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSP1IF is set. Note: If the low address does not match, SSP1IF and UA are still set so that the slave software can set SSP1ADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSP1IF. 11. Slave reads the received matching address from SSP1BUF clearing BF. 12. Slave loads high address into SSP1ADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSP1IF is set. 14. If SEN bit of SSP1CON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSP1IF. 16. Slave reads the received byte from SSP1BUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001413E-page 242  2010-2015 Microchip Technology Inc.  2010-2015 Microchip Technology Inc. CKP UA BF SSP1IF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSP1ADD it is loaded into SSP1BUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSP1ADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSP1BUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSP1BUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 25-20: SCL SDA Master sends Stop condition PIC12(L)F1822/16(L)F1823 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001413E-page 243 DS40001413E-page 244 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSP1ADD is not allowed until 9th falling edge of SCL SSP1BUF can be read anytime before the next received byte Cleared by software 1 A7 Receive Second Address Byte 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSP1ADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSP1BUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 25-21: SSP1IF 1 SCL S 1 SDA Receive First Address Byte PIC12(L)F1822/16(L)F1823 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)  2010-2015 Microchip Technology Inc.  2010-2015 Microchip Technology Inc. D/A R/W ACKSTAT CKP UA BF SSP1IF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSP1ADD must be updated SSP1BUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSP1ADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSP1ADD Received address is read from SSP1BUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSP1BUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 25-22: SDA Master sends Restart event PIC12(L)F1822/16(L)F1823 I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) DS40001413E-page 245 PIC12(L)F1822/16(L)F1823 25.5.6 CLOCK STRETCHING 25.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSP1CON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 25.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSP1STAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSP1BUF with data to transfer to the master. If the SEN bit of SSP1CON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSP1BUF was read before the ninth falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSP1BUF was loaded before the ninth falling edge of SCL. It is now always cleared for read requests. FIGURE 25-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSP1ADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 25.5.6.3 Byte NACKing When AHEN bit of SSP1CON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When DHEN bit of SSP1CON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 25.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 25-23). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSP1CON1 DS40001413E-page 246  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.5.8 GENERAL CALL ADDRESS SUPPORT software can read SSP1BUF Figure 25-24 shows a general sequence. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. respond. reception In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. If the AHEN bit of the SSP1CON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSP1CON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSP1ADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave FIGURE 25-24: and call SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSP1IF BF (SSP1STAT) Cleared by software GCEN (SSP1CON2) SSP1BUF is read ’1’ 25.5.9 SSP1 MASK REGISTER An SSP1 Mask (SSP1MSK) register (Register 25-5) is available in I2C Slave mode as a mask for the value held in the SSP1SR register during an address comparison operation. A zero (‘0’) bit in the SSP1MSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP1 operation until written with a mask value. The SSP1 Mask register is active during: • 7-bit Address mode: address compare of A. • 10-bit Address mode: address compare of A only. The SSP1 mask has no effect during the reception of the first (high) byte of the address.  2010-2015 Microchip Technology Inc. DS40001413E-page 247 PIC12(L)F1822/16(L)F1823 25.6 I2C MASTER MODE Master mode is enabled by setting and clearing the appropriate SSP1M bits in the SSP1CON1 register and by setting the SSP1EN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP1 hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP1 module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP1 Interrupt Flag bit, SSP1IF, to be set (SSP1 interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP1 module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSP1BUF register to initiate transmission before the Start condition is complete. In this case, the SSP1BUF will not be written to and the WCOL bit will be set, indicating that a write to the SSP1BUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS40001413E-page 248 25.6.1 I2C MASTER MODE OPERATION The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 25.7 “Baud Rate Generator” for more detail. 25.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 25-25).  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 25-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL allowed to transition high SCL deasserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 25.6.3 WCOL STATUS FLAG high is the Start condition and causes the S bit of the SSP1STAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSP1ADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSP1CON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. If the user writes the SSP1BUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSP1BUF was attempted while the module was not Idle. Note: 25.6.4 Because queuing of events is not allowed, writing to the lower five bits of SSP1CON2 is disabled until the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCL1IF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. I2C MASTER MODE START CONDITION TIMING To initiate a Start condition (Figure 25-26), the user sets the Start Enable bit, SEN bit of the SSP1CON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is FIGURE 25-26: 2: The Philips I2C™ Specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSP1STAT) At completion of Start bit, hardware clears SEN bit and sets SSP1IF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSP1BUF occurs here SDA 1st bit 2nd bit TBRG SCL S  2010-2015 Microchip Technology Inc. TBRG DS40001413E-page 249 PIC12(L)F1822/16(L)F1823 25.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING cally cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSP1STAT register will be set. The SSP1IF bit will not be set until the Baud Rate Generator has timed out. A Repeated Start condition (Figure 25-27) occurs when the RSEN bit of the SSP1CON2 register is programmed high and the Master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSP1CON2 register will be automati- FIGURE 25-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSP1CON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSP1IF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSP1BUF occurs here TBRG SCL Sr TBRG Repeated Start 25.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSP1BUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit DS40001413E-page 250 on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSP1IF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSP1BUF, leaving SCL low and SDA unchanged (Figure 25-28). After the write to the SSP1BUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSP1CON2 register. Following the falling edge of the ninth clock transmission of the address, the SSP1IF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSP1BUF takes place, holding SCL low and allowing SDA to float.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.6.6.1 BF Status Flag In Transmit mode, the BF bit of the SSP1STAT register is set when the CPU writes to SSP1BUF and is cleared when all eight bits are shifted out. 25.6.6.2 WCOL Status Flag If the user writes the SSP1BUF when a transmit is already in progress (i.e., SSP1SR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. 25.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSP1CON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 25.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical Transmit Sequence: The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. The MSSP1 module will wait the required start time before any other operation takes place. The user loads the SSP1BUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSP1BUF is written to. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. The MSSP1 module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. The user loads the SSP1BUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSP1CON2 register. Interrupt is generated once the Stop/Restart condition is complete.  2010-2015 Microchip Technology Inc. DS40001413E-page 251 DS40001413E-page 252 S R/W PEN SEN BF (SSP1STAT) SSP1IF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSP1BUF written 1 D7 1 SCL held low while CPU responds to SSP1IF ACK = 0 R/W = 0 SSP1BUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSP1BUF is written by software Cleared by software service routine from SSP1 interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address P Cleared by software 9 ACK From slave, clear ACKSTAT bit SSP1CON2 ACKSTAT in SSP1CON2 = 1 FIGURE 25-28: SEN = 0 Write SSP1CON2 SEN = 1 Start condition begins PIC12(L)F1822/16(L)F1823 I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 25-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP1 module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSP1SR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSP1SR are loaded into the SSP1BUF, the BF flag bit is set, the SSP1IF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP1 is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSP1CON2 register. 25.6.7.1 8. 9. 10. 11. 12. 13. 14. 15. User sets the RCEN bit of the SSP1CON2 register and the Master clocks in a byte from the slave. After the eighth falling edge of SCL, SSP1IF and BF are set. Master clears SSP1IF and reads the received byte from SSP1UF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSP1CON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the Slave and SSP1IF is set. User clears SSP1IF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSP1BUF from SSP1SR. It is cleared when the SSP1BUF register is read. 25.6.7.2 SSP1OV Status Flag In receive operation, the SSP1OV bit is set when eight bits are received into the SSP1SR and the BF flag bit is already set from a previous reception. 25.6.7.3 WCOL Status Flag If the user writes the SSP1BUF when a receive is already in progress (i.e., SSP1SR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 25.6.7.4 1. 2. 3. 4. 5. 6. 7. Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. User writes SSP1BUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSP1BUF is written to. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. The MSSP1 module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit.  2010-2015 Microchip Technology Inc. DS40001413E-page 253 DS40001413E-page 254 RCEN ACKEN SSP1OV BF (SSP1STAT) SDA = 0, SCL = 1 while CPU responds to SSP1IF SSP1IF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSP1IF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA\ = ACKDT = 0 Cleared in software Set SSP1IF at end of receive 9 ACK is not sent ACK RCEN cleared automatically P Set SSP1IF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSP1STAT) and SSP1IF PEN bit = 1 written here SSP1OV is set because SSP1BUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Last bit is shifted into SSP1SR and contents are unloaded into SSP1BUF Cleared by software Set SSP1IF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Master configured as a receiver by programming SSP1CON2 (RCEN = 1) A1 R/W RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 FIGURE 25-29: SCL SDA Master configured as a receiver by programming SSP1CON2 (RCEN = 1) SEN = 0 Write to SSP1BUF occurs here, RCEN cleared ACK from Slave automatically start XMIT Write to SSP1CON2(SEN = 1), begin Start condition Write to SSP1CON2 to start Acknowledge sequence SDA = ACKDT (SSP1CON2) = 0 PIC12(L)F1822/16(L)F1823 I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.6.8 ACKNOWLEDGE SEQUENCE TIMING 25.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSP1CON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSP1STAT register is set. A TBRG later, the PEN bit is cleared and the SSP1IF bit is set (Figure 25-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSP1CON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP1 module then goes into Idle mode (Figure 25-30). 25.6.8.1 25.6.9.1 WCOL Status Flag If the user writes the SSP1BUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSP1BUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 25-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSP1CON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSP1IF SSP1IF set at the end of receive Cleared in software Cleared in software SSP1IF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSP1STAT) is set. Write to SSP1CON2, set PEN PEN bit (SSP1CON2) is cleared by hardware and the SSP1IF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period.  2010-2015 Microchip Technology Inc. DS40001413E-page 255 PIC12(L)F1822/16(L)F1823 25.6.10 SLEEP OPERATION 25.6.13 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP1 interrupt is enabled). 25.6.11 EFFECTS OF A RESET A Reset disables the MSSP1 module and terminates the current transfer. 25.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP1 module is disabled. Control of the I 2C bus may be taken when the P bit of the SSP1STAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCL1IF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF, and reset the I2C port to its Idle state (Figure 25-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSP1BUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSP1CON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSP1IF bit will be set. A write to the SSP1BUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSP1STAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF DS40001413E-page 256  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 25-33). SCL is sampled low before SDA is asserted low (Figure 25-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 25-35). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCL1IF flag is set and • the MSSP1 module is reset to its Idle state (Figure 25-33). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 25-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSP1IF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP1 module reset into Idle state. SEN BCL1IF SDA sampled low before Start condition. Set BCL1IF. S bit and SSP1IF set because SDA = 0, SCL = 1. SSP1IF and BCL1IF are cleared by software S SSP1IF SSP1IF and BCL1IF are cleared by software  2010-2015 Microchip Technology Inc. DS40001413E-page 257 PIC12(L)F1822/16(L)F1823 FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software ’0’ ’0’ SSP1IF ’0’ ’0’ S FIGURE 25-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA SCL TBRG SDA pulled low by other master. Reset BRG and assert SDA. S SCL pulled low after BRG time-out SEN BCL1IF Set SSP1IF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSP1IF SDA = 0, SCL = 1, set SSP1IF DS40001413E-page 258 Interrupts cleared by software  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 25.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 25-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’ (Case 2). If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 25-37. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSP1ADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 25-36: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL1IF Cleared by software S ’0’ SSP1IF ’0’ FIGURE 25-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCL1IF SCL goes low before SDA, set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN S ’0’ SSP1IF  2010-2015 Microchip Technology Inc. DS40001413E-page 259 PIC12(L)F1822/16(L)F1823 25.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSP1ADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 25-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 25-39). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 25-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCL1IF SDA asserted low SCL PEN BCL1IF P ’0’ SSP1IF ’0’ FIGURE 25-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCL1IF PEN BCL1IF P ’0’ SSP1IF ’0’ DS40001413E-page 260  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 25-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE(1) C1IE EEIE BCL1IE — — — 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF PIR2 OSFIF C2IF(1) C1IF EEIF BCL1IF — — — 90 SSP1ADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 267 SSP1BUF SSP1CON1 89 Synchronous Serial Port Receive Buffer/Transmit Register 221* WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 265 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 266 SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 267 SSP1STAT SMP CKE D/A P S R/W UA BF 263 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TRISA (1) TRISC Legend: * Note 1: SSPM 264 — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. Page provides register information. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 261 PIC12(L)F1822/16(L)F1823 25.7 BAUD RATE GENERATOR The MSSP1 module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSP1ADD register (Register 25-6). When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP1 is being operated in. Table 25-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSP1ADD. EQUATION 25-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1   4  An internal signal “Reload” in Figure 25-40 triggers the value from SSP1ADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 25-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSP1M SSP1M Reload SCL Control SSP1CLK SSP1ADD Reload BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSP1ADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 25-4: Note 1: MSSP1 CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical and timing specifications in Table 30-4 and Figure 30-7 to ensure the system is designed to support the I/O requirements. DS40001413E-page 262  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 25-1: SSP1STAT: SSP1 STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP1 is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSP1ADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSP1BUF is full 0 = Receive not complete, SSP1BUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty  2010-2015 Microchip Technology Inc. DS40001413E-page 263 PIC12(L)F1822/16(L)F1823 REGISTER 25-2: SSP1CON1: SSP1 CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSP1OV SSP1EN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSP1M bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSP1OV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register (must be cleared in software). 0 = No overflow In I2 C mode: 1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSP1EN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Master mode: Unused in this mode bit 3-0 SSP1M: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave Idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDA and SCL pins must be configured as inputs. SSP1ADD values of 0, 1 or 2 are not supported for I2C Mode. SSP1ADD value of ‘0’ is not supported. Use SSP1M = 0000 instead. DS40001413E-page 264  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 25-3: SSP1CON2: SSP1 CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).  2010-2015 Microchip Technology Inc. DS40001413E-page 265 PIC12(L)F1822/16(L)F1823 REGISTER 25-4: SSP1CON3: SSP1 CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSP1OV bit of the SSP1CON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSP1OV bit only if the BF bit = 0. 0 = SSP1BUF is only updated when SSP1OV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes Idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSP1CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP1CON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. DS40001413E-page 266  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 25-5: R/W-1/1 SSP1MSK: SSP1 MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK: Mask bits 1 = The received address bit n is compared to SSP1ADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSP1M = 0111 or 1111): 1 = The received address bit 0 is compared to SSP1ADD to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 25-6: R/W-0/0 SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD: Baud Rate Clock Divider bits SCL pin clock period = ((ADD + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2010-2015 Microchip Technology Inc. DS40001413E-page 267 PIC12(L)F1822/16(L)F1823 26.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) • • • • • • • • • • Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes • Sleep operation The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 26-1: The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 26-1 and Figure 26-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXIF TXREG Register 8 MSb TX/CK pin LSb (8) • • • 0 Pin Buffer and Control TRMT SPEN Transmit Shift Register (TSR) TXEN Baud Rate Generator FOSC TX9 n BRG16 +1 SPBRGH ÷n SPBRGL DS40001413E-page 268 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 TX9D  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGH SPBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register 26-1, Register 26-2 and Register 26-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output.  2010-2015 Microchip Technology Inc. DS40001413E-page 269 PIC12(L)F1822/16(L)F1823 26.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 26-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 26.1.1 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 26-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register. 26.1.1.1 Enabling the Transmitter 26.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG. 26.1.1.3 Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG. The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note 1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. DS40001413E-page 270  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.1.1.4 TSR Status 26.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 26.1.1.5 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. 4. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. 5. 6. 7. Asynchronous Transmission Set-up: Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. A special 9-bit Address mode is available for use with multiple receivers. See Section 26.1.2.7 “Address Detection” for more information on the address mode. FIGURE 26-3: Write to TXREG BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 TX/CK pin Start bit FIGURE 26-4: bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) bit 0 1 TCY Word 1 Transmit Shift Reg. ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG BRG Output (Shift Clock) Word 1 TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Start bit bit 0 1 TCY bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions.  2010-2015 Microchip Technology Inc. DS40001413E-page 271 PIC12(L)F1822/16(L)F1823 TABLE 26-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 ABDOVF GIE PIE1 PIR1 BAUDCON INTCON RCSTA TRISC TXREG TXSTA Legend: * Note 1: Bit 0 Register on Page BRG16 — WUE ABDEN 279 IOCIE TMR0IF INTF IOCIF 86 TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 CREN ADDEN FERR OERR RX9D Bit 3 RCIDL — SCKP PEIE TMR0IE INTE TMR1GIE ADIE RCIE TMR1GIF ADIF RCIF SPEN RX9 SREN BRG SPBRGH (1) Bit 1 Bit 4 SPBRGL TRISA Bit 2 Bit 5 BRG 280* — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 EUSART Transmit Data Register CSRC TX9 TXEN 278 280* 117 121 270* SYNC SENDB BRGH TRMT TX9D 277 — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission. Page provides register information. PIC16(L)F1823 only. DS40001413E-page 272  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 26-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 26.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note 1: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 26.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 26.1.2.4 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: 26.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 26.1.2.5 “Receive Overrun Error” for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE interrupt enable bit of the PIE1 register • PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.  2010-2015 Microchip Technology Inc. DS40001413E-page 273 PIC12(L)F1822/16(L)F1823 26.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 26.1.2.5 26.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 26.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. DS40001413E-page 274  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.1.2.8 Asynchronous Reception Set-up: 26.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 26-5: This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Set-up bit 1 Rcv Shift Reg Rcv Buffer Reg. RCIDL bit 7/8 Stop bit Start bit Word 1 RCREG bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2010-2015 Microchip Technology Inc. DS40001413E-page 275 PIC12(L)F1822/16(L)F1823 TABLE 26-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 ABDOVF GIE PIE1 PIR1 BAUDCON INTCON Bit 1 Bit 0 Register on Page BRG16 — WUE ABDEN 279 IOCIE TMR0IF INTF IOCIF 86 TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 TXIF SSPIF CCP1IF TMR2IF TMR1IF 87 OERR RX9D Bit 4 Bit 3 RCIDL — SCKP PEIE TMR0IE INTE TMR1GIE ADIE RCIE TMR1GIF ADIF RCIF SPEN RX9 SREN RCREG RCSTA Bit 2 Bit 5 EUSART Receive Data Register CREN ADDEN 273* FERR 278 SPBRGL BRG 280* SPBRGH BRG 280* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 TXSTA Legend: * Note 1: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Reception. Page provides register information. PIC16(L)F1823 only. DS40001413E-page 276  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 26-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 5.2.2 “Internal Clock Sources” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 26.3.1 “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 277 PIC12(L)F1822/16(L)F1823 RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) REGISTER 26-2: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001413E-page 278  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 26-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2010-2015 Microchip Technology Inc. DS40001413E-page 279 PIC12(L)F1822/16(L)F1823 26.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 26-3 contains the formulas for determining the baud rate. Example 26-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 26-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. EXAMPLE 26-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -----------------------------------------------------------------------64  [SPBRGH:SPBRGL] + 1  Solving for SPBRGH:SPBRGL: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- – 1 64 16000000 -----------------------9600 = ------------------------ – 1 64 =  25.042  = 25 16000000 Calculated Baud Rate = --------------------------64  25 + 1  = 9615 Calc. Baud Rate – Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate  9615 – 9600  = ---------------------------------- = 0.16% 9600 Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. DS40001413E-page 280  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 26-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: Name BAUDCON SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 SPBRGL BRG SPBRGH BRG TXSTA FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGH, SPBRGL register pair. TABLE 26-4: RCSTA FOSC/[16 (n+1)] CSRC TX9 TXEN SYNC SENDB 280* 280* BRGH TRMT TX9D 277 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information.  2010-2015 Microchip Technology Inc. DS40001413E-page 281 PIC12(L)F1822/16(L)F1823 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 DS40001413E-page 282  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate FOSC = 20.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 71 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — —  2010-2015 Microchip Technology Inc. DS40001413E-page 283 PIC12(L)F1822/16(L)F1823 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 832 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS40001413E-page 284  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence (Figure 26-6). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 26-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRGL register did not overflow by checking for 00h in the SPBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 26-6. During ABD, both the SPBRGH and SPBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH FIGURE 26-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 26.3.3 “Auto-Wake-up on Break”). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRGL register pair. TABLE 26-6: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 FOSC/4 FOSC/32 1 Note: During the ABD sequence, SPBRGL and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. 0000h RX pin 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 285 PIC12(L)F1822/16(L)F1823 26.3.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCON register. The RCIF flag can be subsequently cleared by reading the RCREG register. The ABDOVF flag of the BAUDCON register can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 26.3.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 26-7), and asynchronously if the device is in Sleep mode (Figure 26-8). The interrupt condition is cleared by reading the RCREG register. 26.3.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all ‘0’s. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001413E-page 286  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set. FIGURE 26-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.  2010-2015 Microchip Technology Inc. DS40001413E-page 287 PIC12(L)F1822/16(L)F1823 26.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 26-9 for the timing of the Break character sequence. 26.3.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 26.3.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the Received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; • RCIF bit is set • FERR bit is set • RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 26.3.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 26-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) DS40001413E-page 288 SENDB Sampled Here Auto Cleared  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 26.4.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART for Synchronous Master operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 26.4.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.  2010-2015 Microchip Technology Inc. 26.4.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 26.4.1.3 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 26.4.1.4 Synchronous Master Transmission Set-up: 1. 2. 3. 4. 5. 6. 7. 8. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 26.3 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register. DS40001413E-page 289 PIC12(L)F1822/16(L)F1823 FIGURE 26-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 26-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 2 bit 1 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 26-7: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 ABDOVF GIE PIE1 PIR1 BAUDCON INTCON RCSTA Bit 2 Bit 1 Bit 0 Register on Page BRG16 — WUE ABDEN 279 IOCIE TMR0IF INTF IOCIF 86 SSPIE CCP1IE TMR2IE TMR1IE 87 TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 CREN ADDEN FERR OERR RX9D Bit 5 Bit 4 Bit 3 RCIDL — SCKP PEIE TMR0IE INTE TMR1GIE ADIE RCIE TXIE TMR1GIF ADIF RCIF SPEN RX9 SREN SPBRGL SPBRGH 278 BRG 280* BRG 280* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 CSRC TX9 TXEN BRGH TRMT TX9D TXREG EUSART Transmit Data Register TXSTA Legend: Note * 1: SYNC SENDB 270* 277 — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission. Page provides register information. PIC16(L)F1823 only. DS40001413E-page 290  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: 26.4.1.6 If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: 26.4.1.7 If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. 26.4.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. 26.4.1.9 Synchronous Master Reception Set-up: 1. Initialize the SPBRGH, SPBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO  2010-2015 Microchip Technology Inc. DS40001413E-page 291 PIC12(L)F1822/16(L)F1823 FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 26-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 ABDOVF GIE PIE1 PIR1 BAUDCON INTCON Bit 1 Bit 0 Register on Page BRG16 — WUE ABDEN 279 IOCIE TMR0IF INTF IOCIF 86 TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 TXIF SSPIF CCP1IF TMR2IF TMR1IF Bit 4 Bit 3 RCIDL — SCKP PEIE TMR0IE INTE TMR1GIE ADIE RCIE TMR1GIF ADIF RCIF RCREG RCSTA Bit 2 Bit 5 EUSART Receive Data Register SPEN RX9 SREN CREN ADDEN 89 273* FERR OERR RX9D 278 SPBRGL BRG 280* SPBRGH BRG 280* TRISA TRISC (1) TXSTA Legend: * Note 1: — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception. Page provides register information. PIC16(L)F1823 only. DS40001413E-page 292  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 26.4.2.1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 5. 26.4.2.2 1. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave Section 26.4.1.3 modes are identical (see “Synchronous Master Transmission”), except in the case of the Sleep mode. 2. 3. 4. 5. 6. 7. 8. TABLE 26-9: The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXREG register. SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 278 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 TRMT TX9D Name BAUDCON INTCON TXREG TXSTA Legend: * Note 1: EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB BRGH 270* 277 — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. Page provides register information. PIC16(L)F1823 only.  2010-2015 Microchip Technology Inc. DS40001413E-page 293 PIC12(L)F1822/16(L)F1823 26.4.2.3 EUSART Synchronous Slave Reception 26.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 26.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name BAUDCON INTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 279 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 89 OERR RX9D RCREG EUSART Receive Data Register SPEN RX9 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 277 TXSTA Legend: * Note 1: SREN CREN ADDEN 273* RCSTA FERR 278 — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. Page provides register information. PIC16(L)F1823 only. DS40001413E-page 294  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 26.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 26.5.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: • RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 26.4.2.4 “Synchronous Slave Reception Set-up:”). • If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. • The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.  2010-2015 Microchip Technology Inc. 26.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • RCSTA and TXSTA Control registers must be configured for Synchronous Slave Transmission (see Section 26.4.2.2 “Synchronous Slave Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. • If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. • Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. 26.5.3 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section 12.1 “Alternate Pin Function”for more information. DS40001413E-page 295 PIC12(L)F1822/16(L)F1823 27.0 CAPACITIVE SENSING (CPS) MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the CPS module. The CPS module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • • • • • • • Analog MUX for monitoring multiple inputs Capacitive sensing oscillator Multiple current ranges Multiple voltage reference modes Multiple timer resources Software control Operation during Sleep FIGURE 27-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module FOSC/4 T0CKI 0 TMR0 0 Overflow 1 CPSCH CPSON(2) Set TMR0IF TMR0CS T0XCS 1 CPSRNG CPSON CPS0 Capacitive Sensing Oscillator CPS1 CPSOSC Timer1 Module T1CS CPS2 CPS3 0 CPS4(1) Ref- (1) CPS5 DAC_output Int. Ref. CPSOUT 1 CPS6(1) 0 Ref+ CPS7(1) CPSCLK 1 FVR Buffer2 FOSC FOSC/4 T1OSC/ T1CKI EN TMR1H:TMR1L T1GSEL T1G Timer1 Gate Control Logic sync_C1OUT sync_C2OUT CPSRM Note 1: 2: Reference CPSCON1 register (Register 27-2) for channels implemented on each device. If CPSON = 0, disabling capacitive sensing, no channel is selected. DS40001413E-page 296  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 27-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) + (2) - S CPSx (1) Analog Pin - (2) Q CPSCLK R + Internal References Ref- 0 0 Ref+ 1 DAC_output 1 FVR Buffer2 CPSRM Note 1: 2: Module Enable and Current mode selections are not shown. Comparators remain active in Noise Detection mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 297 PIC12(L)F1822/16(L)F1823 27.1 Analog MUX The CPS module can monitor up to four inputs for the PIC12(L)F1822 (CPSCH) and up to eight inputs for the PIC16(L)F1823 (CPSCH). See Register 27-2 for details. To determine if a frequency change has occurred the user must: • Select the appropriate CPS pin by setting the appropriate CPSCH bits of the CPSCON1 register. • Set the corresponding ANSEL bit. • Set the corresponding TRIS bit. • Run the software algorithm. Selection of the CPSx pin while the module is enabled will cause the capacitive sensing oscillator to be on the CPSx pin. Failure to set the corresponding ANSEL and TRIS bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. 27.2 Capacitive Sensing Oscillator The capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. The CPSOUT bit of the CPSCON0 register shows the status of the capacitive sensing oscillator, whether it is a sinking or sourcing current. The oscillator is designed to drive a capacitive load (single PCB pad) and at the same time, be a clock source to either Timer0 or Timer1. The oscillator has three different current settings as defined by CPSRNG of the CPSCON0 register. The different current settings for the oscillator serve two purposes: • Maximize the number of counts in a timer for a fixed time base. • Maximize the count differential in the timer during a change in frequency. DS40001413E-page 298 27.3 Voltage References The capacitive sensing oscillator uses voltage references to provide two voltage thresholds for oscillation. The upper voltage threshold is referred to as Ref+ and the lower voltage threshold is referred to as Ref-. The user can elect to use Fixed Voltage References, which are internal to the capacitive sensing oscillator, or variable voltage references, which are supplied by the Fixed Voltage Reference (FVR) module and the Digital-to-Analog Converter (DAC) module. When the Fixed Voltage References are used, the VSS voltage determines the lower threshold level (Ref-) and the VDD voltage determines the upper threshold level (Ref+). When the variable voltage references are used, the DAC voltage determines the lower threshold level (Ref-) and the FVR voltage determines the upper threshold level (Ref+). An advantage of using these reference sources is that oscillation frequency remains constant with changes in VDD. Different oscillation frequencies can be obtained through the use of these variable voltage references. The more the upper voltage reference level is lowered and the more the lower voltage reference level is raised, the higher the capacitive sensing oscillator frequency becomes. Selection between the voltage references is controlled by the CPSRM bit of the CPSCON0 register. Setting this bit selects the variable voltage references and clearing this bit selects the Fixed Voltage References. Please see Section 14.0 “Fixed Voltage Reference (FVR)” and Section 17.0 “Digital-to-Analog Converter (DAC) Module” for more information on configuring the variable voltage levels.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 27.4 Current Ranges The Capacitive Sensing Oscillator can operate within several different current ranges, depending on the Voltage Reference mode and current range selections. Within each of the two Voltage Reference modes there are four current ranges. Selection between the Voltage Reference modes is controlled by the CPSRM bit of the CPSCON0 register. Clearing this bit selects the Fixed Voltage References provided by the capacitive sensing oscillator module. Setting this bit selects the variable voltage references supplied by the Fixed Voltage Reference (FVR) module and the Digital-to-Analog Converter (DAC) module. See Section 27.3 “Voltage References” for more information on configuring the voltage references. Selecting the current range within the Voltage Reference mode is controlled by configuring the CPSRNG bits in the CPSCON0 register. See Table 27-1 for proper current mode selection. TABLE 27-1: CURRENT MODE SELECTION CPSRM Voltage Reference Mode 0 1 Note 1: The Noise Detection mode is unique in that it disables the constant-current source associated with the selected input pin, but leaves the rest of the oscillator circuitry and pin structure active. This eliminates the oscillation frequency on the analog pin and greatly reduces the current consumed by the oscillator module. When noise is introduced onto the pin, the oscillator is driven at the frequency determined by the noise. This produces a detectable signal at the comparator stage, indicating the presence of activity on the pin. Figure 27-2 shows a more detailed drawing of the constant-current sources and comparators associated with the oscillator and input pin. Fixed Variable CPSRNG Current Range(1) 00 Off 01 Low 10 Medium 11 High 00 Noise Detection 01 Low 10 Medium 11 High See Power-Down Currents (IPD) in Section 30.3 “DC Characteristics: PIC16(L)F1824/8-I/E (Power-Down)” for more information.  2010-2015 Microchip Technology Inc. DS40001413E-page 299 PIC12(L)F1822/16(L)F1823 27.5 Timer Resources 27.7 To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer divided by the period of the fixed time base. 27.6 Fixed Time Base To measure the frequency of the capacitive sensing oscillator, a fixed time base is required. Any timer resource or software loop can be used to establish the fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. Note: 27.6.1 The fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking. TIMER0 To select Timer0 as the timer resource for the CPS module: • Set the T0XCS bit of the CPSCON0 register. • Clear the TMR0CS bit of the OPTION register. When Timer0 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer0. Refer to Section 20.0 “Timer0 Module” for additional information. 27.6.2 TIMER1 To select Timer1 as the timer resource for the CPS module, set the TMR1CS of the T1CON register to ‘11’. When Timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the Timer0 overflow flag. It is recommend that the Timer0 overflow flag, in conjunction with the Toggle mode of the Timer1 Gate, be used to develop the fixed time base required by the software portion of the CPS module. Refer to Section 21.12 “Timer1 Gate Control Register” for additional information. TABLE 27-2: TIMER1 ENABLE FUNCTION TMR1ON TMR1GE Timer1 Operation 0 0 Off 0 1 Off 1 0 On 1 1 Count Enabled by input DS40001413E-page 300 Software Control The software portion of the CPS module is required to determine the change in frequency of the capacitive sensing oscillator. This is accomplished by the following: • Setting a fixed time base to acquire counts on Timer0 or Timer1. • Establishing the nominal frequency for the capacitive sensing oscillator. • Establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load. • Set the frequency threshold. 27.7.1 NOMINAL FREQUENCY (NO CAPACITIVE LOAD) To determine the nominal frequency of the capacitive sensing oscillator: • Remove any extra capacitive load on the selected CPSx pin. • At the start of the fixed time base, clear the timer resource. • At the end of the fixed time base save the value in the timer resource. The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. 27.7.2 REDUCED FREQUENCY (ADDITIONAL CAPACITIVE LOAD) The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator: • Add a typical capacitive load on the selected CPSx pin. • Use the same fixed time base as the nominal frequency measurement. • At the start of the fixed time base, clear the timer resource. • At the end of the fixed time base save the value in the timer resource. The value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer divided by the period of the fixed time base. This frequency should be less than the value obtained during the nominal frequency measurement.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 27.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for CPS module. Note: For more information on general capacitive sensing refer to Application Notes: • AN1101, “Introduction to Capacitive Sensing” (DS01101) • AN1102, “Layout and Physical Design Guidelines for Capacitive Sensing” (DS01102) 27.8 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore cannot be used for capacitive sense measurements in Sleep.  2010-2015 Microchip Technology Inc. DS40001413E-page 301 PIC12(L)F1822/16(L)F1823 REGISTER 27-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 CPSON CPSRM — — R/W-0/0 R/W-0/0 CPSRNG R-0/0 R/W-0/0 CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: Capacitive Sensing Module Enable bit 1 = CPS module is enabled 0 = CPS module is disabled bit 6 CPSRM: Capacitive Sensing Reference Mode bit 1 = Capacitive Sensing module is in Variable Voltage Reference mode 0 = Capacitive Sensing module is in Fixed Voltage Reference mode bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CPSRNG: Capacitive Sensing Current Range bits If CPSRM = 0 (Fixed Voltage Reference mode): 00 = Oscillator is off 01 = Oscillator is in low range 10 = Oscillator is in medium range 11 = Oscillator is in high range If CPSRM = 1 (Variable Voltage Reference mode): 00 = Oscillator is on. Noise Detection mode. No Charge/Discharge current is supplied. 01 = Oscillator is in low range 10 = Oscillator is in medium range 11 = Oscillator is in high range bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out of the pin) 0 = Oscillator is sinking current (Current flowing into the pin) bit 0 T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1: The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0: Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 DS40001413E-page 302  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0(1) R/W-0/0 R/W-0/0 CPSCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSCH: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4)(1) 0101 = channel 5, (CPS5)(1) 0110 = channel 6, (CPS6)(1) 0111 = channel 7, (CPS7)(1) 1000 = Reserved. Do not use. • • • 1111 = Reserved. Do not use. Note 1: These channels are only implemented on the PIC16(L)F1823.  2010-2015 Microchip Technology Inc. DS40001413E-page 303 PIC12(L)F1822/16(L)F1823 TABLE 27-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Register on Page ANSA1 ANSA0 118 ANSC1 ANSC0 122 CPSOUT T0XCS 302 CPSCH1 CPSCH0 303 TMR0IF INTF IOCIF 86 Bit 6 Bit 5 Bit 4 ANSELA — — — ANSA4 — ANSA2 ANSELC(1) — — — — ANSC3 ANSC2 CPSCON0 CPSON CPSRM — — CPSRNG1 CPSRNG0 CPSCON1 — — — — CPSCH3(1) CPSCH2(1) GIE PEIE TMR0IE INTE INTCON OPTION_REG Bit 3 Bit 0 Bit 7 IOCIE Bit 2 Bit 1 WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 164 T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC — TMR1ON 173 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 117 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 121 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the CPS module. Note 1: PIC16(L)F1823 only. DS40001413E-page 304  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification” (DS41403). 28.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure 28-1 for example circuit. FIGURE 28-1: VPP LIMITER EXAMPLE CIRCUIT RJ11-6PIN 6 5 4 3 2 1 1 VPP 2 VDD 3 VSS 4 ICSP_DATA 5 ICSP_CLOCK 6 NC RJ11-6PIN ® To MPLAB ICD 2 R1 To Target Board 270 Ohm LM431BCMX 1 2 A K 3 A U1 6 A NC 4 7 A NC 5 R2 VREF 8 10k 1% Note: R3 24k 1% The MPLAB ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC12(L)F1822/16(L)F1823.  2010-2015 Microchip Technology Inc. DS40001413E-page 305 PIC12(L)F1822/16(L)F1823 28.2 FIGURE 28-2: Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC12(L)F1822/16(L)F1823 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 VPP/MCLR MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. VSS Target PC Board Bottom Side Pin Description* 1 = VPP/MCLR Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 7.3 “MCLR” for more information. 5 = ICSPCLK 6 = No Connect The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. 28.3 ICD RJ-11 STYLE CONNECTOR INTERFACE Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 28-3. Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure 28-2. FIGURE 28-3: PICkit™ STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 2 3 4 5 6 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * DS40001413E-page 306 The 6-pin header (0.100" spacing) accepts 0.025" square pins.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 28-4 for more information. FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2010-2015 Microchip Technology Inc. DS40001413E-page 307 PIC12(L)F1822/16(L)F1823 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 29-1: Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 29-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 29-2: ABBREVIATION DESCRIPTIONS Field PC Program Counter TO Time-out bit C DC Z PD DS40001413E-page 308 Description Carry bit Digit carry bit Zero bit Power-down bit  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE  2010-2015 Microchip Technology Inc. DS40001413E-page 309 PIC12(L)F1822/16(L)F1823 TABLE 29-3: PIC12(L)F1822/16(L)F1823 ENHANCED INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 1, 2 1, 2 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 01 01 10bb bfff ffff 11bb bfff ffff 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. DS40001413E-page 310  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 29-3: PIC12(L)F1822/16(L)F1823 ENHANCED INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z 2, 3 1 1 11 00 1111 0nkk kkkk Z 0000 0001 1nmm 2 2, 3 1 11 1111 1nkk kkkk 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions.  2010-2015 Microchip Technology Inc. DS40001413E-page 311 PIC12(L)F1822/16(L)F1823 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32  k  31 n  [ 0, 1] Operands: 0  k  255 Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. AND W with f k FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W ANDWF Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0  f  127 d 0,1 Operation: (W) .AND. (f)  (destination) k Operands: 0  k  255 Operation: (W) + k  (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. ADDWF Add W and f f,d Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF Syntax: [ label ] ASRF Operands: 0  f  127 d 0,1 Operands: 0  f  127 d [0,1] Operation: (W) + (f)  (destination) Operation: (f) dest (f)  dest, (f)  C, f,d Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. DS40001413E-page 312 f {,d} Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f C f {,d}  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0  f  127 0b7 Operands: 0  f  127 0b7 Operands: Operation: 0  (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: 0  f  127 0b VDD) 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin............................................................................................... 25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001413E-page 322  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 PIC12F1822/16F1823 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C FIGURE 30-1: VDD (V) 5.5 2.5 1.8 4 0 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies. PIC12LF1822/16LF1823 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C VDD (V) FIGURE 30-2: 3.6 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each oscillator mode’s supported frequencies.  2010-2015 Microchip Technology Inc. DS40001413E-page 323 PIC12(L)F1822/16(L)F1823 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 25 ± 2% 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001413E-page 324  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 30.1 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) PIC12LF1822/16LF1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC12F1822/16F1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param. No. D001 Sym. VDD D001 D002* VDR D002* Characteristic Min. Typ† Max. Units Conditions PIC12LF1822/16LF1823 1.8 2.5 — — 3.6 3.6 V V FOSC  16 MHz: FOSC  32 MHz (Note 2) PIC12F1822/16F1823 1.8 2.5 — — 5.5 5.5 V V FOSC  16 MHz: FOSC  32 MHz (Note 2) Supply Voltage RAM Data Retention Voltage(1) PIC12LF1822/16LF1823 1.5 — — V Device in Sleep mode PIC12F1822/16F1823 1.7 — — V Device in Sleep mode — 1.6 — V PIC12LF1822/16LF1823 — 0.8 — V PIC12F1822/16F1823 — 1.4 — V Device in Sleep mode VPOR* Power-on Reset Release Voltage VPORR* Power-on Reset Rearm Voltage Device in Sleep mode D003 VADFVR Fixed Voltage Reference Voltage for ADC -8 -8 -8 6 6 6 % 1.024V, VDD  2.5V 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003A VCDAFVR Fixed Voltage Reference Voltage for Comparator and DAC -11 -11 -11 7 7 7 % 1.024V, VDD  2.5V 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003C* TCVFVR Temperature Coefficient, Fixed Voltage Reference — -114 — ppm/ °C D003D* VFVR/ VIN Line Regulation, Fixed Voltage Reference — 0.225 — %/V D004* VDD Rise Rate to ensure internal Power-on Reset signal 0.05 — — V/ms SVDD See Section 7.1 “Power-on Reset (POR)” for details. * † Note These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation.  2010-2015 Microchip Technology Inc. DS40001413E-page 325 PIC12(L)F1822/16(L)F1823 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: DS40001413E-page 326 TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) PIC12LF1822/16LF1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC12F1822/16F1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units VDD Note Supply Current (IDD)(1, 2) — 5.0 15 A 1.8 — 8.0 19 A 3.0 — 24 36 A 1.8 — 30 48 A 3.0 — 32 66 A 5.0 D010A — 5.0 21 A 1.8 — 7.5 25 A 3.0 D010A — 24 60 A 1.8 — 30 70 A 3.0 — 32 80 A 5.0 — 60 115 A 1.8 — 111 200 A 3.0 — 82 135 A 1.8 — 141 225 A 3.0 — 200 320 A 5.0 D012 — 145 280 A 1.8 — 260 460 A 3.0 D012 — 165 300 A 1.8 — 290 500 A 3.0 — 368 700 A 5.0 — 34 170 A 1.8 — 59 250 A 3.0 — 60 200 A 1.8 — 92 260 A 3.0 — 126 350 A 5.0 — 118 250 A 1.8 — 210 420 A 3.0 D010 D010 D011 D011 D013 D013 D014 * † Note 1: 2: 3: 4: 5: FOSC = 32 kHz, -40°C to +85°C LP Oscillator mode FOSC = 32 kHz, -40°C to +85°C LP Oscillator mode FOSC = 32 kHz, -40°C to +125°C LP Oscillator mode FOSC = 32 kHz, -40°C to +125°C LP Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz EC Oscillator mode, Medium-power mode FOSC = 1 MHz EC Oscillator mode Medium-power mode FOSC = 4 MHz EC Oscillator mode, Medium-power mode These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2010-2015 Microchip Technology Inc. DS40001413E-page 327 PIC12(L)F1822/16(L)F1823 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) PIC12LF1822/16LF1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC12F1822/16F1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Conditions Device Characteristics Min. Typ† Max. Units VDD — 143 260 A 1.8 — 240 450 A 3.0 — 300 550 A 5.0 D015 — 2.0 20 A 1.8 — 4.0 22 A 3.0 D015 — 21 45 A 1.8 — 27 50 A 3.0 — 28 60 A 5.0 — 110 250 A 1.8 — 150 280 A 3.0 — 132 190 A 1.8 — 165 230 A 3.0 D014 Supply Current (IDD) D016 D016 — 210 280 A 5.0 — 0.55 0.8 mA 1.8 — 0.8 1.25 mA 3.0 D017* — 0.6 0.9 mA 1.8 — 0.9 1.4 mA 3.0 — 1.0 1.5 mA 5.0 — 0.8 1.2 mA 1.8 — 1.3 1.9 mA 3.0 — 0.8 1.2 mA 1.8 — 1.3 1.8 mA 3.0 D018 — 1.5 2.0 mA 5.0 D019 — 2.2 3.3 mA 3.0 — 2.3 3.6 mA 3.6 D019 — 2.2 3.3 mA 3.0 — 2.3 3.6 mA 5.0 * † Note 1: 2: 3: 4: 5: FOSC = 4 MHz EC Oscillator mode Medium-power mode (1, 2) D017* D018 Note FOSC = 31 kHz LFINTOSC mode FOSC = 31 kHz LFINTOSC mode FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode FOSC = 32 MHz HFINTOSC mode (Note 3) FOSC = 32 MHz HFINTOSC mode (Note 3) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k DS40001413E-page 328  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 30.2 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Industrial, Extended) PIC12LF1822/16LF1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC12F1822/16F1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max. Units VDD Note Supply Current (IDD)(1, 2) D020 D020 D021 D021 * † Note 1: 2: 3: 4: 5: — 2.0 3.1 mA 3.0 — 2.5 3.5 mA 3.6 — 2.0 3.1 mA 3.0 — 2.5 3.5 mA 5.0 — 210 425 A 1.8 — 470 800 A 3.0 — 350 435 A 1.8 — 550 800 A 3.0 — 620 850 A 5.0 FOSC = 32 MHz HS Oscillator mode (Note 4) FOSC = 32 MHz HS Oscillator mode (Note 4) FOSC = 4 MHz EXTRC mode (Note 5) FOSC = 4 MHz EXTRC mode (Note 5) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2010-2015 Microchip Technology Inc. DS40001413E-page 329 PIC12(L)F1822/16(L)F1823 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down) PIC12LF1822/16LF1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC12F1822/16F1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Power-down Base Current Min. Typ† Conditions Max. +85°C Max. +125°C Units A VDD D022 — 0.02 1.0 4.0 — 0.03 1.8 4.8 A 3.0 D022 — 20 40 50 A 1.8 — 22 45 55 A 3.0 — 24 50 60 A 5.0 — 0.3 1.8 10.5 A 1.8 — 0.5 2.0 16 A 3.0 — 20 41 56 A 1.8 — 22 46 61 A 3.0 D023 D023 D023A D023A Note (IPD)(2) 1.8 — 24 51 71 A 5.0 — 12 25 35 A 1.8 — 13 27 37 A 3.0 — 32 65 70 A 1.8 — 38 75 80 A 3.0 WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive LPWDT Current (Note 1) LPWDT Current (Note 1) FVR current (Note 1) FVR current (Note 1) — 68 115 120 A 5.0 D024 — 8.0 15 20 A 3.0 BOR Current (Note 1) D024 — 30 55 65 A 3.0 BOR Current (Note 1) — 33 75 85 A 5.0 D025 — 0.65 4.0 7.0 A 1.8 — 2.3 4.5 7.5 A 3.0 D025 — 20 42 55 A 1.8 — 23 45 60 A 3.0 — 25 48 70 A 5.0 — 0.1 1.8 4.0 A 1.8 — 0.1 2.0 5.0 A 3.0 — 20 40 55 A 1.8 — 22 45 60 A 3.0 — 24 50 70 A 5.0 D026 D026 * † Note 1: 2: 3: T1OSC Current (Note 1) T1OSC Current (Note 1) A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), no conversion in progress These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. DS40001413E-page 330  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down) (Continued) PIC12LF1822/16LF1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC12F1822/16F1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Min. Power-down Base Current (IPD) D026A* D026A* Typ† Conditions Max. +85°C Max. +125°C Units VDD — 250 — — A 1.8 — 250 — — A 3.0 — 280 — — A 1.8 — 280 — — A 3.0 — 280 — — A 5.0 D027 — 2.2 7.0 10 A 1.8 — 4.2 9.0 12 A 3.0 D027 — 21 41 45 A 1.8 — 23 47 55 A 3.0 — 24 53 68 A 5.0 — 6.3 9 16 A 1.8 — 7.9 12 21 A 3.0 — 21 45 50 A 1.8 — 23 55 60 A 3.0 D027A D027A D027B D027B D028 D028 D028A D028A * † Note 1: 2: 3: Note (2) — 25 60 75 A 5.0 — 16 25 35 A 1.8 — 41 45 45 A 3.0 — 23 62 100 A 1.8 — 25 90 105 A 3.0 — 26 100 115 A 5.0 — 8.0 17 22 A 1.8 — 8.1 20 25 A 3.0 — 30 50 55 A 1.8 — 33 60 65 A 3.0 — 35 65 85 A 5.0 — 8.2 18 24 A 1.8 — 8.3 21 27 A 3.0 — 30 51 56 A 1.8 — 32 61 66 A 3.0 — 33 67 87 A 5.0 A/D Current (Note 1, Note 3), conversion in progress A/D Current (Note 1, Note 3), conversion in progress Cap Sense Low Power Oscillator mode (Note 1) Cap Sense Low Power Oscillator mode (Note 1) Cap Sense Medium Power Oscillator mode (Note 1) Cap Sense Medium Power Oscillator mode (Note 1) Cap Sense High Power Oscillator mode (Note 1) Cap Sense High Power Oscillator mode (Note 1) Comparator Current, Low Power mode, one comparator enabled (Note 1) Comparator Current, Low Power mode, one comparator enabled (Note 1) Comparator Current, Low Power mode, two comparators enabled (Note 1) Comparator Current, Low Power mode, two comparators enabled (Note 1) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC.  2010-2015 Microchip Technology Inc. DS40001413E-page 331 PIC12(L)F1822/16(L)F1823 30.3 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E (Power-Down) (Continued) PIC12LF1822/16LF1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended PIC12F1822/16F1823 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param No. Device Characteristics Min. Power-down Base Current (IPD) D028B D028B D028C D028C * † Note 1: 2: 3: Typ† Conditions Max. +85°C Max. +125°C Units VDD Note Comparator Current, High Power mode, one comparator enabled (Note 1) (2) — 30 50 60 A 1.8 — 31 55 70 A 3.0 — 60 85 90 A 1.8 — 62 90 95 A 3.0 — 64 95 100 A 5.0 — 31 51 61 A 1.8 — 32 56 71 A 3.0 — 61 85 90 A 1.8 — 63 90 95 A 3.0 — 65 95 100 A 5.0 Comparator Current, High Power mode, one comparator enabled (Note 1) Comparator Current, High Power mode, two comparators enabled Comparator Current, High Power mode, two comparators enabled (Note 1) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC. DS40001413E-page 332  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 30.4 DC Characteristics: PIC12(L)F1822/16(L)F1823-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Min. Typ† Max. Units — — with Schmitt Trigger buffer with I2C™ levels Conditions — 0.8 V 4.5V  VDD  5.5V — 0.15 VDD V 1.8V  VDD  4.5V — — 0.2 VDD V 2.0V  VDD  5.5V — — 0.3 VDD V Input Low Voltage I/O PORT: D030 with TTL buffer D030A D031 with SMBus levels D032 D033 VIH — 0.8 V — — 0.2 VDD V OSC1 (HS mode) — — 0.3 VDD V — — 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V with I2C™ levels 0.7 VDD — — V Input High Voltage I/O ports: D040 with TTL buffer D040A D041 2.7V  VDD  5.5V — MCLR, OSC1 (RC mode)(1) with SMBus levels 2.7V  VDD  5.5V 2.1 — — V D042 MCLR 0.8 VDD — — V D043A OSC1 (HS mode) 0.7 VDD — — V D043B OSC1 (RC mode) 0.9 VDD — — V VDD > 2.0V, (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ±5 ± 125 nA ±5 ± 1000 nA VSS  VPIN  VDD, Pin at high-impedance at 85°C 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD at 85°C 25 25 100 140 200 300 A VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS — — 0.6 V IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VDD - 0.7 — — V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V — — 15 pF — — 50 pF IPUR Weak Pull-up Current D070* VOL D080 Output Low Voltage(4) I/O ports VOH D090 Output High Voltage(4) I/O ports Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin D101A* CIO * † Note 1: 2: 3: 4: All I/O pins In XT, HS and LP modes when external clock is used to drive OSC1 These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode.  2010-2015 Microchip Technology Inc. DS40001413E-page 333 PIC12(L)F1822/16(L)F1823 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory High-Voltage Programming Specifications D110 VIHH Voltage on MCLR/VPP/RA5 pin 8.0 — 9.0 V D111 IDDVPP Programming/Erase Current on VPP, High Voltage Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.7 — VDD max. V D113 VPEW VDD for Write or Row Erase VDD min. — VDD max. V D114 IPPPGM Programming/Erase Current on VPP, Low Voltage Programming — 1.0 — mA D115 IDDPGM Programming/Erase Current on VDD, High or Low Voltage Programming — 5.0 — mA D116 ED Byte Endurance 100K — — E/W D117 VDRW VDD for Read/Write VDD min. — VDD max. V (Note 3, Note 4) Data EEPROM Memory -40C to +85C D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D120 TREF Number of Total Erase/Write Cycles before Refresh(2) 1M 10M — E/W -40°C to +85°C D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPR VDD for Read VDD min. — VDD max. V D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Program Flash Memory † Note 1: 2: 3: 4: Provided no other specifications are violated Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Self-write and Block Erase. Refer to Section 11.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. Required only if single-supply programming is disabled. The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the MPLAB ICD 2 VPP voltage must be placed between the MPLAB ICD 2 and target system when programming or debugging with the MPLAB ICD 2. DS40001413E-page 334  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 89.3 C/W 149.5 C/W 8-pin SOIC package 56.7 C/W 8-pin DFN 3X3mm package 39.4 C/W 8-pin UDFN 3X3mm package 70.0 C/W 14-pin PDIP package 95.3 C/W 14-pin SOIC package 100 C/W 14-pin TSSOP 4x4mm package 45.7 C/W 16-pin QFN 4X4mm package 31.8 C/W 16-pin UQFN 4X4mm package 43.1 C/W 8-pin PDIP package 39.9 C/W 8-pin SOIC package 9.0 C/W 8-pin DFN 3X3mm package 40.3 C/W 8-pin UDFN 3X3mm package 32.0 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 24.4 C/W 14-pin TSSOP 4x4mm package 8-pin PDIP package 6.3 C/W 16-pin QFN 4X4mm package 24.4 C/W 16-pin UQFN 4X4mm package 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Legend: TBD = To Be Determined Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. TJ = Junction Temperature.  2010-2015 Microchip Technology Inc. DS40001413E-page 335 PIC12(L)F1822/16(L)F1823 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDIx do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 30-5: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCKx SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output DS40001413E-page 336  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 30.8 AC Characteristics: PIC12(L)F1822/16(L)F1823-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) OS02 TOSC External CLKIN Period(1) Oscillator Period(1) OS03 TCY Instruction Cycle Time(1) OS04* TosH, TosL External CLKIN High, External CLKIN Low TosR, TosF External CLKIN Rise, External CLKIN Fall OS05* Min. Typ† Max. Units Conditions DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 32 MHz EC Oscillator mode (high) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode, VDD  2.7V 1 — 20 MHz HS Oscillator mode, VDD > 2.7V DC — 4 MHz RC Oscillator mode 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 31.25 —  ns EC Oscillator mode — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode 200 — DC ns TCY = FOSC/4 2 — — s LP oscillator 100 — — ns XT oscillator 20 — — ns HS oscillator 0 —  ns LP oscillator 0 —  ns XT oscillator 0 —  ns HS oscillator * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2010-2015 Microchip Technology Inc. DS40001413E-page 337 PIC12(L)F1822/16(L)F1823 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Sym. HFOSC OS08A MFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2) Internal Calibrated MFINTOSC Frequency(2) Internal LFINTOSC Frequency OS09 LFOSC OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time Freq. Tolerance Min. Typ† Max. Units Conditions 2% — 16.0 — MHz 0°C  TA  +60°C, VDD  2.5V 3% — 16.0 — MHz 60°C  TA  +85°C, VDD  2.5V 5% — 16.0 — MHz -40°C  TA  +125°C 2% — 500 — kHz 0°C  TA  +60°C, VDD  2.5V 3% — 500 — kHz 60°C  TA  +85°C, VDD  2.5V 5% — 500 — kHz -40°C  TA  +125°C 25% — 31 — kHz -40°C  TA  +125°C — — 3.2 8 s — — 24 35 s * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design. TABLE 30-3: Param No. Sym. F10 PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Min. Typ† Max. Units FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % F13* Characteristic Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001413E-page 338  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 30-7: Cycle CLKOUT AND I/O TIMING Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19  2010-2015 Microchip Technology Inc. DS40001413E-page 339 PIC12(L)F1822/16(L)F1823 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.0-5.0V — — 72 ns VDD = 3.0-5.0V FOSC to CLKOUT (1) OS11 TosH2ckL OS12 TosH2ckH FOSC to CLKOUT (1) OS13 TckL2ioV CLKOUT to Port out valid OS14 OS15 OS16 TioV2ckH TosH2ioV TosH2ioI OS17 TioV2osH OS18* TioR Port input valid before CLKOUT(1) Fosc (Q1 cycle) to Port out valid Fosc (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc(Q2 cycle) (I/O in setup time) Port output rise time OS19* TioF Port output fall time (1) — — 20 ns TOSC + 200 ns — 50 — 50 — — 70* — ns ns ns 20 — — ns — — — — 25 25 40 15 28 15 — — 72 32 55 30 — — ns OS20* Tinp OS21* Tioc INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. FIGURE 30-8: ns VDD = 3.0-5.0V VDD = 3.0-5.0V VDD = 1.8V VDD = 3.0-5.0V VDD = 1.8V VDD = 3.0-5.0V ns ns RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1: Asserted low. DS40001413E-page 340  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’. 2 ms delay if PWRTE = 0.  2010-2015 Microchip Technology Inc. DS40001413E-page 341 PIC12(L)F1822/16(L)F1823 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDTLP Watchdog Timer Time-out Period 12 16 20 ms 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc 33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s 35 VBOR Brown-out Reset Voltage 2.55 1.80 2.7 1.9 2.85 2.11 V 36* VHYST Brown-out Reset Hysteresis 20 35 75 mV -40°C to +85°C 37* TBORDC Brown-out Reset DC Response Time 1 3 35 s VDD  VBOR VDD = 3.3V-5V, 1:16 Prescaler used BORV= 0 BORV= 1 * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the oscillators start-up (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 DS40001413E-page 342  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.5 TCY + 20 — — ns 15 — — ns Asynchronous TT1L 46* T1CKI Low Time 30 — — ns Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Greater of: 30 or TCY + 40 N — — ns 47* TT1P T1CKI Input Synchronous Period 48 FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * † Units 10 With Prescaler 42* Max. 0.5 TCY + 20 With Prescaler 41* Typ† 60 — — ns 32.4 32.768 33.1 kHz 2 TOSC — 7 TOSC — Conditions N = prescale value (2, 4, ..., 256) N = prescale value (1, 2, 4, 8) Timers in Sync mode These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 30-5 for load conditions. TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param Sym. No. CC01* TccL CC02* TccH CC03* TccP * † Characteristic CCP Input Low Time CCP Input High Time CCP Input Period Min. Typ† Max. Units No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns 3TCY + 40 N — — ns Conditions N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010-2015 Microchip Technology Inc. DS40001413E-page 343 PIC12(L)F1822/16(L)F1823 TABLE 30-8: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS:(1, 2, 3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — — ±1.7 AD03 EDL Differential Error — — ±1 AD04 EOFF Offset Error — — ±2.5 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.0V AD06 VREF Reference Voltage(4) AD07 VAIN Full-Scale Range AD08 ZAIN Recommended Impedance of Analog Voltage Source * † Note 1: 2: 3: 4: Gain Error bit LSb VREF = 3.0V LSb No missing codes VREF = 3.0V — — ±2.0 1.8 — VDD V VSS — VREF V — — 10 k VREF = (VREF+ minus VREF-) Can go higher if external 0.01F capacitor is present on input pin. These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. ADC Reference Voltage (REF+) is the selected input, VREF+ pin, VDD pin or the FVR Buffer 1. When the FVR is selected as the reference input, the FVR Buffer 1 output selection must be 2.048V or 4.096V (ADFVR = 1x). TABLE 30-9: ADC CONVERSION REQUIREMENTS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param No. Sym. AD130* TAD AD131 TCNV AD132* TACQ Characteristic Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator Period 1.0 2.5 6.0 s ADCS = 11 (ADRC mode) Conversion Time (not including Acquisition Time)(1) — 11 — TAD Set GO/DONE bit to conversion complete Acquisition Time — 5.0 — s * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. DS40001413E-page 344  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 30-12: PIC12(L)F1822/16(L)F1823 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 30-13: PIC12(L)F1822/16(L)F1823 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.  2010-2015 Microchip Technology Inc. DS40001413E-page 345 PIC12(L)F1822/16(L)F1823 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param No. Sym. Characteristics Min. Typ. Max. Units Comments VICM = VDD/2, High-Power mode CM01 VIOFF Input Offset Voltage — ±7.5 ±60 mV CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio — 50 — dB CM04A Response Time Rising Edge — 400 800 ns High-Power mode CM04B Response Time Falling Edge — 200 400 ns High-Power mode CM04C TRESP(1) CM04D Response Time Rising Edge — 1200 — ns Low-Power mode Response Time Falling Edge — 550 — ns Low-Power mode Comparator Mode Change to Output Valid* — — 10 s — 45 — mV CM05 TMC2OV CM06 CHYSTER Comparator Hysteresis(2) * Note 1: 2: Hysteresis on These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled. TABLE 30-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param No. Sym. Characteristics Min. Typ. Max. Units DAC01* CLSB Step Size — VDD/32 — V DAC02* CACC Absolute Accuracy — —  1/2 LSb DAC03* CR Unit Resistor Value (R) — 5K —  DAC04* CST Settling Time(1) — — 10 s * Note 1: Comments These parameters are characterized but not tested. Settling time measured while DACR transitions from ‘0000’ to ‘1111’. FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 Note: US122 Refer to Figure 30-5 for load conditions. DS40001413E-page 346  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units — 80 ns US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 30-15: Conditions USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 30-5 for load conditions. TABLE 30-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) US126 TCKL2DTL Data-hold after CK  (DT hold time)  2010-2015 Microchip Technology Inc. Min. Max. Units 10 — ns 15 — ns Conditions DS40001413E-page 347 PIC12(L)F1822/16(L)F1823 FIGURE 30-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDOx LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions. FIGURE 30-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SSx SP81 SCKx (CKP = 0) SP71 SP72 SP79 SP73 SCKx (CKP = 1) SP80 SDOx MSb bit 6 - - - - - -1 SP78 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 30-5 for load conditions. DS40001413E-page 348  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE = 0) SSx SP70 SCKx (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCKx (CKP = 1) SP80 MSb SDOx LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 30-5 for load conditions. FIGURE 30-19: SSx SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCKx (CKP = 0) SP71 SP72 SCKx (CKP = 1) SP80 SDOx MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 30-5 for load conditions.  2010-2015 Microchip Technology Inc. DS40001413E-page 349 PIC12(L)F1822/16(L)F1823 TABLE 30-14: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SSx to SCKx or SCKx input TSSL2SCL Min. Typ† Max. Units Conditions 2.25 TCY — — ns SP71* TSCH SCKx input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCKx input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns — 10 25 ns SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge TDIV2SCL SP74* TSCH2DIL, TSCL2DIL Hold time of SDIx data input to SCKx edge SP75* TDOR SDO data output rise time SP76* TDOF SDOx data output fall time SP77* TSSH2DOZ SSx to SDOx output high-impedance 10 — 50 ns SP78* TSCR SCKx output rise time (Master mode) — 10 25 ns SP79* TSCF SCKx output fall time (Master mode) 3.0-5.5V — 25 50 ns — 10 25 ns 3.0-5.5V — — 50 ns 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDOx data output setup to SCKx edge TDOV2SCL Tcy — — ns SDOx data output valid after SS edge — — 50 ns 1.5TCY + 40 — — ns SP80* TSCH2DOV, SDOx data output valid after TSCL2DOV SCKx edge SP82* TSSL2DOV 1.8-5.5V SP83* TSCH2SSH, SSx after SCKx edge TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING SCLx SP93 SP91 SP90 SP92 SDAx Start Condition Stop Condition Note: Refer to Figure 30-5 for load conditions. DS40001413E-page 350  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SCLx SP100 SP90 SP102 SP101 SP106 SP107 SP92 SP91 SDAx In SP110 SP109 SP109 SDAx Out Note: Refer to Figure 30-5 for load conditions. TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Characteristic Start condition Typ 4700 — Max. Units — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * 100 kHz mode Min. 400 kHz mode 600 — — 100 kHz mode 4000 — — 400 kHz mode 600 — — Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested.  2010-2015 Microchip Technology Inc. DS40001413E-page 351 PIC12(L)F1822/16(L)F1823 TABLE 30-16: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH SP101* TLOW SP102* TR SP103* TF SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* SP111 * Note 1: 2: TBUF CB Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSPx module 1.5TCY — — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDAx and SCLx fall 100 kHz mode time 400 kHz mode — 250 ns 20 + 0.1CB 250 ns Clock low time SDAx and SCLx rise time Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx signal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS40001413E-page 352  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. CS01 CS02 Symbol ISRC ISNK Characteristic Current Source Current Sink Min. Typ† Max. Units High — -8 — A Medium — -1.5 — A Low — -0.3 — A High — 7.5 — A Medium — 1.5 — A Low — 0.25 — A CS03 VCTH Cap Threshold — 0.8 — mV CS04 VCTL Cap Threshold — 0.4 — mV CS05 VCHYST CAP HYSTERESIS (VCTH - VCTL) High — 525 — mV Medium — 375 — mV Low — 300 — mV Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC Enabled  2010-2015 Microchip Technology Inc. ISNK Enabled DS40001413E-page 353 PIC12(L)F1822/16(L)F1823 30.9 High Temperature Operation This section outlines the specifications for the following devices operating in the high temperature range between -40°C and 150°C.(2) Note 1: Writes are not allowed for Flash program memory above 125°C. 2: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. • PIC12F1822(4) • PIC16F1823(4) When the value of any parameter is identical for both the 125°C Extended and the 150°C High Temp. temperature ranges, then that value will be found in the standard specification tables shown earlier in this chapter, under the fields listed for the 125°C Extended temperature range. If the value of any parameter is unique to the 150°C High Temp. temperature range, then it will be listed here, in this section of the data sheet. 3: The temperature range indicator in the catalog part number and device marking is “H” for -40°C to 150°C. Example: PIC12F1822T-H/SN indicates the device is shipped in a Tape and Reel configuration, in the SOIC package, and is rated for operation from -40°C to 150°C. If a Silicon Errata exists for the product and it lists a modification to the 125°C Extended temperature range value, one that is also shared at the 150°C High Temp. temperature range, then that modified value will apply to both temperature ranges. 4: The low voltage versions of these devices, PIC12LF1822 and PIC16LF1823, is not released for operation above +125°C. 5: Errata Sheet DS80502 lists various mask revisions. 150°C operation applies only to revisions A9 and later. 6: The Capacitive Sensing module (CPS) should not be used in High Temperature devices. Function and its parametrics are not warranted. 7: Only SOIC (SN or SL), TSSOP (ST), and DFN/QFN (MF or ML) packages will be offered, not PDIP or UQFN. TABLE 30-18: ABSOLUTE MAXIMUM RATINGS Parameter Condition Value Max. Current: VDD Source 15 mA Max. Current: VSS Sink 15 mA Max. Current: Pin Source 5 mA Max. Current: Pin Sink 5 mA Max. Storage Temperature — -65°C to 155°C Max. Junction Temperature — +155°C Ambient Temperature under Bias — -40°C to +150°C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001413E-page 354  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 PIC12F1822/16F1823 VOLTAGE FREQUENCY GRAPH, -40°C  TA +150°C FIGURE 30-23: VDD (V) 5.5 2.5 1.8 4 0 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 30-1 for each Oscillator mode’s supported frequencies. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 30-24: 150 ± 10% No Operation Temperature (°C) 125 85 25 ± 5% 0 -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 355 PIC12(L)F1822/16(L)F1823 TABLE 30-19: DC CHARACTERISTICS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) Operating Temperature: -40°C  TA  +150°C for High Temperature PIC12F1822/16F1823 Param No. D001 Sym. VDD D002* VDR Characteristics Supply Voltage Typ. Max. Units Condition 2.5 — 5.5 V FOSC  32 MHz (Note 1) 2.1 — 5.5 V Device in Sleep mode VADFVR Fixed Voltage Reference Voltage for ADC -10 — 8 % 1.024V, VDD  2.5V 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003A VCDAFV Fixed Voltage Reference R Voltage for ADC -13 — 9 % 1.024V, VDD  2.5V 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003 RAM Data Retention Voltage Min. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: PLL required for 32 MHz operation. DS40001413E-page 356  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 TABLE 30-20: MEMORY PROGRAMMING REQUIREMENTS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) Operating Temperature: -40°C  TA  +150°C for High Temperature PIC12F1822/16F1823 Param No. Sym. Characteristic Min. Typ. Max. Units Conditions Data EEPROM Memory D116 ED Byte Endurance 50K — — E/W -40°C to +150°C D118 TDEW Erase/Write Cycle Time — — 6.0 ms -40°C to +150°C D119 TRETD Data Retention — 20 — Years  50K Programming cycles Program Flash Memory D121 EP Cell Endurance — — — — D124 TRETD Data Retention — 20 — Years Programming the Flash memory above +125°C is not permitted TABLE 30-21: OSCILLATOR PARAMETERS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) Operating Temperature: -40°C  TA  +150°C for High Temperature PIC12F1822/16F1823 Param No. OS08 Sym. Characteristic HFOSC Int. Calibrated HFINTOSC Freq.(1) OS08A MFOSC Int. Calibrated MFINTOSC Freq.(1) OS09 LFOSC Internal LFINTOSC Freq. Frequency Tolerance Min. Typ. Max. Units ±5% — 16.0 — MHz -40°C TA 125°C VDD 2.5V ±10% — 16.0 — MHz -40°C TA 150°C VDD 2.5V ±5% — 500 — kHz -40°C TA 125°C VDD 2.5V ±10% — 500 — kHz -40°C TA 150°C VDD 2.5V ±35% — 31 — kHz -40°C TA 150°C VDD 2.5V Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) Operating Temperature: -40°C  TA  +150°C for High Temperature PIC12F1822/16F1823 Param No. Sym. Characteristic 31 TWDTLP Low-Power Watchdog Timer Time-out Period (No Prescaler) 35 VBOR Brown-out Reset Voltage(1) Min. Typ. Max. Units Conditions 10 16 24 ms VDD = 3.3V-5V 1:16 Prescaler used 2.50 — 2.70 — 2.90 — V — BORV = 0 BORV = 1 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.  2010-2015 Microchip Technology Inc. DS40001413E-page 357 PIC12(L)F1822/16(L)F1823 TABLE 30-23: A/D CONVERTER (ADC) CHARACTERISTICS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) Operating Temperature: -40°C  TA  +150°C for High Temperature PIC12F1822/16F1823 Param No. AD04 Sym. EOFF Characteristic Offset Error Min. Typ. — — Max. Units 3.5 Conditions LSB No missing codes VREF = 3.0V † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. TABLE 30-24: COMPARATOR SPECIFICATIONS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) Operating Temperature: -40°C  TA  +150°C for High Temperature PIC12F1822/16F1823 Param No. CM01 Sym. VIOFF Characteristic Input Offset Voltage Min. Typ. Max. Units — — ±70 mV Conditions High-Power mode, VICM = VDD/2 TABLE 30-25: CAP SENSE OSCILLATOR SPECIFICATIONS FOR PIC12F1822/16F1823-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) Operating Temperature: -40°C  TA  +150°C for High Temperature PIC12F1822/16F1823 Param No. All Sym. All Characteristic All DS40001413E-page 358 Min. Typ. — — Max. Units — — Conditions This module is not intended for use in high temperature devices.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range.  2010-2015 Microchip Technology Inc. DS40001413E-page 359 PIC12(L)F1822/16(L)F1823 FIGURE 31-1: IDD, LP OSCILLATOR MODE (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 25 Max. Max: 85°C + 3ı Typical: 25°C IDD (μA) 20 15 10 Typical 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, LP OSCILLATOR MODE (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY FIGURE 31-2: 80 Max: 85°C + 3ı Typical: 25°C 70 Max. 60 IDD (μA) 50 40 Typical 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 360  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 600 Typical: 25°C 500 4 MHz EXTRC 400 IDD (μA) 4 MHz XT 300 1 MHz EXTRC 200 100 1 MHz XT 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 1000 Max: 85°C + 3ı 900 800 4 MHz EXTRC IDD (μA) 700 600 4 MHz XT 500 400 1 MHz EXTRC 300 200 1 MHz XT 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 361 PIC12(L)F1822/16(L)F1823 FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY 800 Typical: 25°C 700 4 MHz EXTRC 600 IDD (μA) 500 400 4 MHz XT 300 1 MHz EXTRC 200 100 1 MHz XT 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY FIGURE 31-6: 900 Max: 85°C + 3ı 800 4 MHz EXTRC 700 4 MHz XT IDD (μA) 600 500 1 MHz EXTRC 400 300 1 MHz XT 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 362  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-7: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 18 Max: 85°C + 3ı Typical: 25°C 16 Max. 14 IDD (μA) 12 10 8 6 Typical 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-8: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY 45 Max: 85°C + 3ı Typical: 25°C 40 Max. 35 IDD (μA) 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 363 PIC12(L)F1822/16(L)F1823 FIGURE 31-9: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 500 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 80 Max: 85°C + 3ı Typical: 25°C 70 Max. 60 IDD (μA) 50 40 Typical 30 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-10: IDD, EC OSCILLATOR, LOW-POWER MODE (FOSC = 500 kHz), PIC12F1822 AND PIC16F1823 ONLY 50 Max: 85°C + 3ı Typical: 25°C 45 Max. 40 IDD (μA) 35 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 364  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-11: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC12LF1822 AND PIC16LF1823 ONLY 400 350 4 MHz Typical: 25°C 300 IDD (μA) 250 200 150 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-12: , IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC12LF1822 AND, PIC16LF1823 ONLY 450 400 4 MHz Max: 85°C + 3ı 350 IDD (μA) 300 250 200 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 365 PIC12(L)F1822/16(L)F1823 FIGURE 31-13: IDD TYPICAL, EC OSCILLATOR, MEDIUM-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY 450 400 Typical: 25°C 350 4 MHz IDD (μA) 300 250 200 1 MHz 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) IDD MAXIMUM, EC OSCILLATOR, MEDIUM-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY FIGURE 31-14: 450 Max: 85°C + 3ı 400 4 MHz 350 IDD (μA) 300 250 1 MHz 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) DS40001413E-page 366  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-15: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1822 AND PIC16LF1823 ONLY 3.0 Typical: 25°C 2.5 32 MHz (PLL) IDD (mA) 2.0 1.5 16 MHz 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.6 3.8 VDD (V) FIGURE 31-16: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1822 AND PIC16LF1823 ONLY 3.5 3.0 32 MHz (PLL) Max: 85°C + 3ı IDD (mA) 2.5 2.0 16 MHz 1.5 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 367 PIC12(L)F1822/16(L)F1823 FIGURE 31-17: IDDTYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY 2.5 Typical: 25°C 32 MHz (PLL) 2.0 IDD (mA) 1.5 16 MHz 1.0 8 MHz 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.5 6.0 VDD (V) FIGURE 31-18: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1822 AND PIC16F1823 ONLY 3.0 32 MHz (PLL) Max: 85°C + 3ı 2.5 IDD (mA) 2.0 16 MHz 1.5 1.0 8 MHz 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) DS40001413E-page 368  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-19: IDD, LFINTOSC MODE (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 25 Max. IDD (μA) 20 15 10 Max: 85°C + 3ı Typical: 25°C 5 Typical 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-20: IDD, LFINTOSC MODE (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY 50 45 Max. 40 IDD (μA) 35 30 Typical 25 20 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 369 PIC12(L)F1822/16(L)F1823 FIGURE 31-21: IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 200 Max: 85°C + 3ı Typical: 25°C 180 Max. 160 IDD (μA) 140 120 Typical 100 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IDD, MFINTOSC MODE (FOSC = 500 kHz), PIC12F1822 AND PIC16F1823 ONLY FIGURE 31-22: 350 Max: 85°C + 3ı Typical: 25°C 300 Max. IDD (μA) 250 Typical 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 370  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-23: IDD TYPICAL, HFINTOSC MODE, PIC12LF1822 AND PIC16LF1823 ONLY 2500 32 MHz (PLL) Typical: 25°C IDD (μA) 2000 16 MHz 1500 1000 8 MHz 500 4 MHz 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-24: IDD MAXIMUM, HFINTOSC MODE, PIC12LF1822 AND PIC16LF1823 ONLY 3500 32 MHz (PLL) Max: 85°C + 3ı 3000 IDD (μA) 2500 16 MHz 2000 1500 8 MHz 1000 4 MHz 500 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 371 PIC12(L)F1822/16(L)F1823 FIGURE 31-25: IDD TYPICAL, HFINTOSC MODE, PIC12F1822 AND PIC16F1823 ONLY 3000 Typical: 25°C 32 MHz (PLL) 2500 IDD (μA) 2000 16 MHz 1500 8 MHz 1000 4 MHz 500 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-26: IDD MAXIMUM, HFINTOSC MODE, PIC12F1822 AND PIC16F1823 ONLY 4000 32 MHz (PLL) Max: 85°C + 3ı 3500 3000 IDD (μA) 2500 16 MHz 2000 8 MHz 1500 4 MHz 1000 500 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 372  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-27: IDD TYPICAL, HS OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 2.5 Typical: 25°C 2.0 20 MHz IDD (mA) 1.5 1.0 8 MHz 0.5 4 MHz 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-28: IDD MAXIMUM, HS OSCILLATOR, PIC12LF1822 AND PIC16LF1823 ONLY 3.0 Max: 85°C + 3ı 2.5 20 MHz IDD (mA) 2.0 1.5 8 MHz 1.0 0.5 4 MHz 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 373 PIC12(L)F1822/16(L)F1823 FIGURE 31-29: IDD TYPICAL, HS OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY 2500 Typical: 25°C 2000 20 MHz IDD (μA) 1500 8 MHz 1000 500 4 MHz 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-30: IDD MAXIMUM, HS OSCILLATOR, PIC12F1822 AND PIC16F1823 ONLY 3000 Max: 85°C + 3ı 2500 20 MHz IDD (μA) 2000 1500 8 MHz 1000 500 4 MHz 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 374  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-31: IPD BASE, LOW-POWER SLEEP MODE, PIC12LF1822 AND PIC16LF1823 ONLY 1.4 Max: 85°C + 3ı Typical: 25°C 1.2 Max. IPD (μA) 1.0 0.8 0.6 0.4 0.2 Typical 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-32: IPD BASE, LOW-POWER SLEEP MODE, PIC12F1822 AND PIC16F1823 ONLY 50 Max: 85°C + 3 M 3ı Typical: 25°C 45 Max. 40 IPD (μA) 35 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 375 PIC12(L)F1822/16(L)F1823 FIGURE 31-33: IPD, WATCHDOG TIMER (WDT), PIC12LF1822 AND PIC16LF1823 ONLY 1.2 Max. Max: 85°C + 3ı Typical: 25°C 1.0 IPD (μA (μA) 0.8 Typical 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-34: IPD, WATCHDOG TIMER (WDT), PIC12F1822 AND PIC16F1823 ONLY 50 Max: 85°C + 3 M 3ı Typical: 25°C 45 Max. 40 IPD (μA A) 35 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 376  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12LF1822 AND PIC16LF1823 ONLY 30 Max. 25 IPD (μA A) 20 Typical 15 10 Max: 85°C + 3ı Typical: 25°C 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 31-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12F1822 AND PIC16F1823 ONLY 120 Max. Max: 85°C + 3ı Typical: 25°C 100 80 IPD (μA) Typical 60 40 20 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 377 PIC12(L)F1822/16(L)F1823 FIGURE 31-37: IPD, BROWN-OUT RESET (BOR), PIC12F1822 AND PIC16F1823 ONLY 60 Max: 85°C + 3ı Typical: 25°C 50 Max. IPD (μA) 40 Typical 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 378  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-38: IPD, TIMER1 OSCILLATOR (FOSC = 32 kHz), PIC12LF1822 AND PIC16LF1823 ONLY 6.0 Max: 85°C + 3ı Typical: 25°C 5.0 Max. IPD (μA A) 4.0 3.0 Typical 2.0 1.0 0.0 16 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 31-39: IPD, TIMER1 OSCILLATOR (FOSC = 32 kHz), PIC12F1822 AND PIC16F1823 ONLY 50 Max: 85°C + 3ı Typical: 25°C 45 Max. 40 IPD (μA) 35 30 Typical 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 379 PIC12(L)F1822/16(L)F1823 FIGURE 31-40: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12LF1822 AND PIC16LF1823 ONLY 14 Max. 12 IPD (μA) 10 8 Typical 6 4 Max: 85°C + 3ı Typical: 25°C 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12F1822 AND PIC16F1823 ONLY FIGURE 31-41: 60 Max: 85°C + 3ı Typical: 25°C 50 Max. IPD (μA) 40 Typical 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 380  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-42: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC12LF1822 AND PIC16LF1823 ONLY 60 Max: 85°C + 3ı Typical: 25°C 50 IPD (μA A) 40 Max. 30 Typical 20 10 0 16 1.6 1 8 1.8 2 0 2.0 2 2 2.2 2 4 2.4 2 6 2.6 2 8 2.8 3 0 3.0 3 2 3.2 3 4 3.4 3 6 3.6 3 8 3.8 VDD (V) FIGURE 31-43: IPD, COMPARATOR, NORMAL-POWER MODE (CxSP = 1), PIC12F1822 AND PIC16F1823 ONLY 70 Max. 60 50 IPD (μA A) Typical 40 30 20 Max: 85°C + 3ı Typical: 25°C 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 381 PIC12(L)F1822/16(L)F1823 FIGURE 31-44: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 Voltage (V) 1.64 Typical 1.62 Min. 1.60 1.58 1.56 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.54 1.52 1.50 -40 -20 0 20 40 60 80 100 120 100 120 Temperature (°C) FIGURE 31-45: POR REARM VOLTAGE, PIC12F1822 AND PIC16F1823 ONLY 1.54 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.52 1.50 Max. Voltage (V) 1.48 1.46 1.44 Typical 1.42 1.40 Min. 1.38 1.36 1.34 -40 -20 0 20 40 60 80 Temperature (°C) DS40001413E-page 382  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-46: WDT TIME-OUT PERIOD 24 22 Max. Time (mS) 20 18 Typical 16 14 Min. Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Voltage (V) FIGURE 31-47: PWRT PERIOD 110 100 Max. Time (mS) 90 80 Typical 70 Min. 60 Max: Typical + 3ı (-40°C to +125°C) Typical: statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 50 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Voltage (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 383 PIC12(L)F1822/16(L)F1823 FIGURE 31-48: COMPARATOR HYSTERESIS, NORMAL-POWER MODE (CxSP = 1, CxHYS = 1) 80 70 Max. Hysteresis (mV) 60 Typical 50 40 Min. 30 20 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-49: COMPARATOR HYSTERESIS, LOW-POWER MODE (CxSP = 0, CxHYS = 1) 16 14 Max. Hysteresis (mV) 12 Typical 10 8 Min. 6 4 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001413E-page 384  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 FIGURE 31-50: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE (CxSP = 1) 350 300 Time (nS) 250 Max. 200 Typical 150 100 Max: Typical + 3ı Typical: 25°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 31-51: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE (CxSP = 1) 400 Graph represents 3ı Limits 350 Time (nS) 300 250 125°C 200 150 Typical 100 -40°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2010-2015 Microchip Technology Inc. DS40001413E-page 385 PIC12(L)F1822/16(L)F1823 FIGURE 31-52: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE (CxSP = 1), PIC12F1822 AND PIC16F1823 ONLY 50 40 30 Max. Offset Voltage (mV) 20 10 Typical 0 Min. -10 -20 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı -30 -40 -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) DS40001413E-page 386  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 32.0 DEVELOPMENT SUPPORT The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools 32.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2010-2015 Microchip Technology Inc. DS40001413E-page 387 PIC12(L)F1822/16(L)F1823 32.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 32.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 32.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 32.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001413E-page 388  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 32.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 32.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables.  2010-2015 Microchip Technology Inc. 32.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 32.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 32.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001413E-page 389 PIC12(L)F1822/16(L)F1823 32.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 32.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001413E-page 390  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) Example 12LF1822 E/P e3 017 1010 Example 12LF1822 E/SN1010 017 NNN Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2015 Microchip Technology Inc. DS40001413E-page 391 PIC12(L)F1822/16(L)F1823 33.1 Package Marking Information (Continuation) 8-Lead DFN (3x3x0.9 mm) 8-Lead UDFN (3x3x0.5 mm) Example MFLO 1010 017 XXXX YYWW NNN PIN 1 TABLE 33-1: PIN 1 8-LEAD 3x3x0.9 DFN (MF) TOP MARKING Part Number Marking PIC12F1822T-E/MF MFLO PIC12F1822T-I/MF MFMO PIC12LF1822T-E/MF MFPO PIC12LF1822T-I/MF MFNO TABLE 33-2: 8-LEAD 3x3x0.5 UDFN (RF) TOP MARKING Part Number Marking PIC12F1822T-E/RF DABO PIC12F1822T-I/RF DAAO PIC12LF1822T-E/RF DAHO PIC12LF1822T-I/RF DAGO DS40001413E-page 392  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 33.1 Package Marking Information (Continuation) 14-Lead PDIP (300 mil) Example PIC16F1823 -E/P e3 0910017 14-Lead SOIC (3.90 mm) Example PIC16F1823 -E/SL e3 0910017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2015 Microchip Technology Inc. DS40001413E-page 393 PIC12(L)F1822/16(L)F1823 33.1 Package Marking Information (Continuation) 14-Lead TSSOP (4.4 mm) Example XXXXXXXX YYWW NNN F1823EST 0910 017 16-Lead QFN (4x4x0.9 mm) 16-Lead UQFN (4x4x0.5 mm) PIN 1 Example PIN 1 PIC16 F1823 E/ML e 910017 3 Legend: XX...X Y YY WW NNN e3 * Note: DS40001413E-page 394 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 33.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2010-2015 Microchip Technology Inc. DS40001413E-page 395 PIC12(L)F1822/16(L)F1823 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS40001413E-page 396  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001413E-page 397 PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 398  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823      !"#$% &  ! "# $% &"'"" ($)  % *++&&&!  !+$  2010-2015 Microchip Technology Inc. DS40001413E-page 399 PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 400  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001413E-page 401 PIC12(L)F1822/16(L)F1823 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001413E-page 402  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.10 C 1 2X 2 TOP VIEW 0.10 C 0.05 C C SEATING PLANE A1 A 8X (A3) 0.05 C SIDE VIEW 0.10 C A B D2 1 2 L 0.10 C A B E2 NOTE 1 K N e 8X b 0.10 e 2 C A B BOTTOM VIEW Microchip Technology Drawing C04-254A Sheet 1 of 2  2010-2015 Microchip Technology Inc. DS40001413E-page 403 PIC12(L)F1822/16(L)F1823 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 1.40 2.20 0.25 0.35 0.20 MILLIMETERS NOM 8 0.65 BSC 0.50 0.02 0.065 REF 3.00 BSC 1.50 3.00 BSC 2.30 0.30 0.45 - MAX 0.55 0.05 1.60 2.40 0.35 0.55 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-254A Sheet 2 of 2 DS40001413E-page 404  2010-2015 Microchip Technology Inc. PIC12(L)F1822/16(L)F1823 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C X2 E Y2 X1 G1 G2 SILK SCREEN Y1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 Contact Pad to Contact Pad (X6) G1 Contact Pad to Center Pad (X8) G2 MIN MILLIMETERS NOM 0.65 BSC MAX 1.60 2.40 2.90 0.35 0.85 0.20 0.30 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2254A '(  ) #    !" )# %  2010-2015 Microchip Technology Inc. DS40001413E-page 405 PIC12(L)F1822/16(L)F1823 '(  ) #    !" )# % &  ! "# $% &"'"" ($)  % *++&&&!  !+$ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB E" !" J!" G#!7  )(" G;H= G G GK L 1 (   (  N N 1  %%($ $""  11@ 1