PIC16F18313-I/MS

PIC16(L)F18313/18323 Full-Featured, Low Pin Count Microcontrollers with XLP Description PIC16(L)F18313/18323 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP, PWM and communications) to add flexibility to the application design. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture • Only 48 Instructions • Operating Speed: - DC – 32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Up to Four 8-bit Timers • Up to Three 16-bit Timers • Low-Current Power-on Reset (POR) • Power-up Timer (PWRT) • Brown-out Reset (BOR) • Low-Power BOR (LPBOR) Option • Extended Watchdog Timer (WDT) with Dedicated On-Chip Oscillator for Reliable Operation • Programmable Code Protection • Idle mode: ability to put the CPU core to Sleep while internal peripherals continue operating from the system clock • Doze mode: ability to run the CPU core slower than the system clock used by the internal peripherals • Sleep mode: Lowest Power Consumption • Peripheral Module Disable (PMD): peripheral power disable hardware module to minimize power consumption of unused peripherals Memory • • • • 3.5 Kbytes Program Flash Memory 256B Data SRAM Memory 256B of EEPROM Direct, Indirect and Relative Addressing Modes Operating Characteristics • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF18313/18323) - 2.3V to 5.5V (PIC16F18313/18323) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C eXtreme Low-Power (XLP) Features • • • • Sleep mode: 40 nA @ 1.8V, typical Watchdog Timer: 250 nA @ 1.8V, typical Secondary Oscillator: 300 nA @ 32 kHz Operating Current: - 8 A @ 32 kHz, 1.8V, typical - 37 A/MHz @ 1.8V, typical  2015-2019 Microchip Technology Inc. Digital Peripherals • Configurable Logic Cell (CLC): - Two CLCs - Integrated combinational and sequential logic • Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources • Capture/Compare/PWM (CCP) modules: - Two CCPs - 16-bit resolution for Capture/Compare modes - 10-bit resolution for PWM mode • Pulse-Width Modulators (PWM) - Two 10-bit PWMs • Numerically Controlled Oscillator (NCO): - Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock - Input Clock: 0 Hz < FNCO < 32 MHz - Resolution: FNCO/220 • Serial Communications: - EUSART - RS-232, RS-485, LIN compatible - Auto-Baud Detect, auto-wake-up on start - Master Synchronous Serial Port (MSSP) - SPI - I2C, SMBus, PMBus™ compatible • Data Signal Modulator (DSM): - Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms DS40001799F-page 1 PIC16(L)F18313/18323 • Up to 12 I/O Pins: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select - Input level selection control (ST or TTL) - Digital open-drain enable • Peripheral Pin Select (PPS): - I/O pin remapping of digital peripherals • Timer modules: - Timer0: - 8/16-bit timer/counter - Synchronous or asynchronous operation - Programmable prescaler/postscaler - Time base for capture/compare function - Timer1 with gate control: - 16-bit timer/counter - Programmable internal or external clock sources - Multiple gate sources - Multiple gate modes - Time base for capture/compare function - Timer2: - 8-bit timers - Programmable prescaler/postscaler - Time base for PWM function Flexible Oscillator Structure • High-Precision Internal Oscillator: - Software-selectable frequency range up to 32 MHz - ±2% at nominal 4 MHz calibration point • 4x PLL with External Sources • Low-Power Internal 31 kHz Oscillator (LFINTOSC) • External Low-Power 32 kHz Crystal Oscillator (SOSC) • External Oscillator Block with: - Three Crystal/Resonator modes up to 20 MHz - Three External Clock modes up to 32 MHz - Fail-Safe Clock Monitor - Detects clock source failure - Oscillator Start-up Timer (OST) - Ensures stability of crystal oscillator sources Analog Peripherals • 10-bit Analog-to-Digital Converter (ADC): - Up to 11 external channels - Conversion available during Sleep • Comparator: - Up to two comparators - Fixed Voltage Reference at non-inverting input(s) - Comparator outputs externally accessible • 5-bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive Reference Selection - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels  2015-2019 Microchip Technology Inc. DS40001799F-page 2 PIC16(L)F18313/18323 1 1/1 2 1 Y Y Y Y I 1 1/1 2 1 Y Y Y Y I PIC16(L)F18324 (2) 4096 7 256 512 12 11 1 2 2 1 4/3 4 2 1 1 1/1 4 1 Y Y Y Y I PIC16(L)F18325 (3) 8192 14 256 1024 12 11 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I PIC16(L)F18326 (4) 16384 28 256 2048 12 15 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I Debug(1) 1 1 Idle and Doze 2 2 XLP 2 2 PMD 2/1 2/1 PPS 1 1 CLC 1 1 DSM 1 2 I2C/SPI 1 1 EUSART 5 12 11 NCO 6 256 10-bit PWM 10-bit ADC (ch) 256 256 CCP I/Os(2) 256 3.5 Timers (8/16-bit) Data SRAM (bytes) 3.5 2048 Clock Ref Data Memory (bytes) 2048 (1) CWG Program Flash Memory (Kbytes) (1) PIC16(L)F18323 5-bit DAC Program Flash Memory (Words) PIC16(L)F18313 High-Speed/ Comparators Device Data Sheet Index PIC16(L)F183XX Family Types PIC16(L)F18344 (2) 4096 7 256 512 18 17 1 2 2 1 4/3 4 2 1 1 1/1 4 1 Y Y Y Y I PIC16(L)F18345 (3) 8192 14 256 1024 18 17 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I PIC16(L)F18346 (4) 16384 28 256 2048 18 21 1 2 2 1 4/3 4 2 1 1 2/2 4 1 Y Y Y Y I Note 1: Debugging Methods: (I) – Integrated on Chip; 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001799 PIC16(L)F18313/18323 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP 2: DS40001800 PIC16(L)F18324/18344 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP 3: DS40001795 PIC16(L)F18325/18345 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP 4: DS40001839 PIC16(L)F18326/18346 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office.  2015-2019 Microchip Technology Inc. DS40001799F-page 3 PIC16(L)F18313/18323 Pin Diagrams 1 RA5 2 RA4 3 VPP/MCLR/RA3 4 8 VSS 7 RA0/ICSPDAT 6 RA1/ICSPCLK 5 RA2 14-PIN PDIP, SOIC, TSSOP VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 16-PIN UQFN 16 15 14 13 VDD NC FIGURE 3: PIC16(L)F18313 VDD PIC16(L)F18323 FIGURE 2: 8-PIN PDIP, SOIC, UDFN NC VSS FIGURE 1: 1 2 PIC16(L)F18323 3 4 12 11 10 9 RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC4 RC3 RC2 RC1 5 6 7 8 RA5 RA4 RA3/MCLR/VPP RC5 Note 1: It is recommended that the exposed bottom pad be connected to VSS, but must not be the main VSS connection to the device.  2015-2019 Microchip Technology Inc. DS40001799F-page 4 ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic RA0 8-PIN ALLOCATION TABLE (PIC16(L)F18313) PDIP/SOIC/UDFN I/O(2)  2015-2019 Microchip Technology Inc. TABLE 1: 7 ANA0 — C1IN0+ — DAC1OUT MDCIN1(1) — — — — — — CLCIN3(1) — IOC Y ICDDAT/ ICSPDAT ANA1 VREF+ C1IN0- — DAC1REF+ MDMIN(1) — — — — SCK1(1) SCL1(1,3,4) RX(1) CLCIN2(1) — IOC Y ICDCLK/ ICSPCLK RA1 5 ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1IN(1) SDA1(1,3,4) SDI1(1) — — — INT(1) IOC Y — RA3 4 — — — — — — — — — — SS1(1) — CLCIN0(1) — IOC Y MCLR VPP RA4 3 ANA4 — C1IN1- — — — T1G(1) SOSCO — — — — — — — IOC Y CLKOUT OSC2 RA5 2 ANA5 — — — — MDCIN2(1) T1CKI(1) SOSCIN SOSCI CCP1(1) CCP2(1) — — — — CLCIN1(1) — IOC Y CLKIN OSC1 VDD 1 — — — — — — — — — — — — — — — — VDD VSS 8 — — — — — — — — — — — — — — — — VSS — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A SDA1(3) CK CLC1OUT CLKR — — — PWM6 CWG1B SCL1(3) DT CLC2OUT OUT(2) Note 1: 2: 3: 4: — — — — — — — — CCP2 — — — — — — — — — — — — — — CWG1C SDO1 TX — — — — — — — — — — — — — — — CWG1D SCK1 — — — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels as described in Section 13.3 “Bidirectional Pins”; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. DS40001799F-page 5 PIC16(L)F18313/18323 RA2 PDIP/SOIC/TSSOP UQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic  2015-2019 Microchip Technology Inc. I/O(2) 14/16-PIN ALLOCATION TABLE (PIC16(L)F18323) RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — — — — — — — — — IOC Y ICDDAT/ ICSPDAT RA1 12 11 ANA1 VREF+ C1IN0C2IN0- — DAC1REF+ — — — — — — — — — IOC Y ICDCLK/ ICSPCLK RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) — — CWG1IN(1) — — — — INT(1) IOC Y — RA3 4 3 — — — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOC Y CLKOUT OSC2 RA5 2 1 ANA5 — — — — — T1CKI(1) SOSCIN SOSCI — — — — — CLCIN3(1) — IOC Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — — — — — SCK1(1) SCL1(1,3,4) — — — IOC Y — RC1 9 8 ANC1 — C1IN1C2IN1- — — — — — — — SDI1(1) SDA1(1,3,4) — CLCIN2(1) — IOC Y — RC2 8 7 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOC Y — RC3 7 6 ANC3 — C1IN3C2IN3- — — MDMIN(1) — CCP2(1) — — SS1(1) — CLCIN0(1) — IOC Y — RC4 6 5 ANC4 — — — — — — — — — — — CLCIN1(1) — IOC Y — — CCP1(1) — — — RX(1) — — IOC Y — — — — — — — — — — — VDD RC5 5 4 ANC5 — — — — MDCIN2(1) VDD 1 16 — — — — — — VSS 14 13 — — — — — — — — — — — — — — — — VSS — — — — C1OUT NCO — DSM TMR0 CCP1 PWM5 CWG1A SDA1(3) CK CLC1OUT CLKR — — — — — — — C2OUT — — — — CCP2 PWM6 CWG1B SCL1(3) DT CLC2OUT — — — — — — — — — — — — — OUT(2) Note 1: 2: 3: 4: — — — — — — — — — — — CWG1C SDO1 TX — — — — — — — — — — — CWG1D SCK1 — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels as described in Section 13.3 “Bidirectional Pins”; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F18313/18323 DS40001799F-page 6 TABLE 2: PIC16(L)F18313/18323 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started With PIC16(L)F183XX Microcontrollers ..................................................................................... 16 3.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 21 5.0 Device Configuration .................................................................................................................................................................. 51 6.0 Resets ........................................................................................................................................................................................ 58 7.0 Oscillator Module........................................................................................................................................................................ 66 8.0 Interrupts .................................................................................................................................................................................... 85 9.0 Power-Saving Operation Modes .............................................................................................................................................. 101 10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 107 11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 111 12.0 I/O Ports ................................................................................................................................................................................... 128 13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 142 14.0 Peripheral Module Disable ....................................................................................................................................................... 148 15.0 Interrupt-on-Change ................................................................................................................................................................. 154 16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 160 17.0 Temperature Indicator Module ................................................................................................................................................. 163 18.0 Comparator Module.................................................................................................................................................................. 165 19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 174 20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 180 21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 202 22.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 217 23.0 Numerically Controlled Oscillator (NCO1) Module ................................................................................................................... 231 24.0 5-bit Digital-to-Analog Converter (DAC1) Module .................................................................................................................... 242 25.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 246 26.0 Timer0 Module ......................................................................................................................................................................... 257 27.0 Timer1 Module with Gate Control............................................................................................................................................. 264 28.0 Timer2 Module ......................................................................................................................................................................... 277 29.0 Capture/Compare/PWM Modules ............................................................................................................................................ 282 30.0 Master Synchronous Serial Port (MSSP1) Module .................................................................................................................. 293 31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1) ............................................................. 346 32.0 Reference Clock Output Module .............................................................................................................................................. 371 33.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 374 34.0 Instruction Set Summary .......................................................................................................................................................... 376 35.0 Electrical Specifications............................................................................................................................................................ 390 36.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 420 37.0 Development Support............................................................................................................................................................... 441 38.0 Packaging Information.............................................................................................................................................................. 445 Appendix A: Data Sheet Revision History ........................................................................................................................................ 467 The Microchip WebSite ..................................................................................................................................................................... 468 Customer Change Notification Service ............................................................................................................................................. 468 Customer Support ............................................................................................................................................................................. 468 Product Identification System ........................................................................................................................................................... 469  2015-2019 Microchip Technology Inc. DS40001799F-page 7 PIC16(L)F18313/18323 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products.  2015-2019 Microchip Technology Inc. DS40001799F-page 8 PIC16(L)F18313/18323 DEVICE OVERVIEW Figure 1-1 shows a block diagram of the PIC16(L)F18313/18323 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral PIC16(L)F18323 The PIC16(L)F18313/18323 are described within this data sheet. The PIC16(L)F18313 is available in 8-pin PDIP, SOIC and UDFN packages, and the PIC16(L)F18323 is available in 14-pin PDIP, SOIC and TSSOP packages and 16-pin UQFN packages. PIC16(L)F18313 1.0 Analog-to-Digital Converter (ADC) ● ● Temperature Indicator ● ● DAC1 ● ● ADCFVR ● ● CDAFVR ● ● DSM1 ● ● NCO1 ● ● CCP1 ● ● CCP2 ● ● C1 ● ● Digital-to-Analog Converter (DAC) Fixed Voltage Reference (FVR) Digital Signal Modulator (DSM) Numerically Controlled Oscillator (NCO) Capture/Compare/PWM Modules (CCP) Comparators C2 ● Complementary Waveform Generator (CWG) CWG1 ● ● CLC1 ● ● CLC2 ● ● Configurable Logic Cell (CLC) Enhanced Universal Synchronous/Asynchronous Receiver/ Transmitter (EUSART) EUSART1 ● ● MSSP1 ● ● PWM5 ● ● PWM6 ● ● TMR0 ● ● TMR1 ● ● TMR2 ● ● Master Synchronous Serial Port (MSSP) Pulse-Width Modulator (PWM) Timers (TMR)  2015-2019 Microchip Technology Inc. DS40001799F-page 9  2015-2019 Microchip Technology Inc. FIGURE 1-1: PIC16(L)F18313/18323 BLOCK DIAGRAM Program Flash Memory Rev. 10-000039Z 5/25/2017 RAM Timing Generation CLKOUT/OSC2 PORTA EXTOSC Oscillator CLKIN/OSC1 CPU PORTC(2) (Note 3) Secondary Oscillator (SOSC) SOSCI SOSCO MCLR EUSART1 NCO1 PWM5 Temp Indicator Timer2 CWG2 Timer1 CWG1 DS40001799F-page 10 Note 1: See available chapters for more information on peripherals. 2: Available on PIC16(L)F18323 only. 3: See Figure 4-1. Timer0 CLC2 C2(2) ADC 10-bit C1 CLC1 WDT MSSP1 DAC1 CCP2 FVR CCP1 PIC16(L)F18313/18323 PWM6 PIC16(L)F18313/18323 TABLE 1-2: PIC16(L)F18313 PINOUT DESCRIPTION Name RA0/ANA0/C1IN0+/ DAC1OUT/CLCIN3(1)/MDCIN1(1)/ ICSPDAT/ICDDAT Function Input Type Output Type Description RA0 TTL/ST CMOS ANA0 AN — General purpose I/O. C1IN0+ AN — Comparator C1 positive input. DAC1OUT — AN Digital-to-Analog Converter output. ADC Channel A0 input. CLCIN3 TTL/ST — Configurable Logic Cell source input. MDCIN1 TTL/ST — Modular Carrier input 1. ICSPDAT TTL/ST — ICSP™ Data I/O. ICDDAT TTL/ST — RA1 TTL/ST CMOS ANA1 AN — RA1/ANA1/VREF+/C1IN0-/ MDMIN(1)/CLCIN2(1)/SCK1(3)/ SCL1(3)/RX(1)/DAC1REF+/ ICSPCLK/ICDCLK In-Circuit Debug Data I/O. General purpose I/O. ADC Channel A1 input. VREF+ AN — ADC Voltage Reference Positive input. C1IN0- AN — Comparator C1 negative input. MDMIN TTL/ST — Modulator Source Input. CLCIN2 TTL/ST — Configurable Logic Cell source input. SCK1 TTL/ST — SPI clock. SCL1 I2C OD I2C clock input/output. RX TTL/ST — EUSART asynchronous input. DAC1REF+ AN — Digital-to-Analog Converter positive reference voltage input. ICSPCLK — CMOS Serial Programming Clock. ICDCLK — CMOS In-Circuit Debug Clock. General purpose I/O. RA2/ANA2/VREF-/DAC1REF-/ SDI1(1,3)/SDA1(1,3)/T0CKI(1)/ CWG1IN(1)/INT(1) RA2 TTL/ST CMOS ANA2 AN — VREF- AN — ADC Voltage Reference Negative input. DAC1REF- AN — Digital-to-Analog Converter negative reference voltage input. ADC Channel A3 input. SDI1 TTL/ST — SPI Data Input. SDA1 I2C OD I2C clock input/output. TMR0 clock input. T0CKI TTL/ST — CWG1IN TTL/ST — Complementary Waveform Generator input. INT TTL/ST — External interrupt. RA3 TTL/ST CMOS MCLR TTL/ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA3/MCLR/VPP/SS1(1)/CLCIN0(1) General purpose I/O. SS1 TTL/ST — Slave Select input. CLCIN0 TTL/ST — Configurable Logic Cell source input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2019 Microchip Technology Inc. DS40001799F-page 11 PIC16(L)F18313/18323 TABLE 1-2: PIC16(L)F18313 PINOUT DESCRIPTION (CONTINUED) Name Function Input Type Output Type RA4 TTL/ST CMOS RA4/ANA4/C1IN1-/T1G(1)/ SOSCO/OSC2/CLKOUT RA5/ANA5/MDCIN2(1)/T1CKI(1)/ SOSCIN/SOSCI/CLCIN1(1)/ CCP1(1)/CCP2(2)/OSC1/CLKIN OUT(2) Description General purpose I/O. ANA4 AN — ADC Channel A4 input. C1IN1- AN — Comparator C1 negative input. T1G TTL/ST — SOSCO — XTAL TMR1 gate input. Secondary Oscillator Connection. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. RA5 TTL/ST CMOS General purpose I/O. ANA5 AN — ADC Channel A5 input. MDCIN2 TTL/ST — Modular Carrier input 2. T1CKI TTL/ST — TMR1 clock input. SOSCIN TTL/ST — Secondary Oscillator Input Connection. SOSCI XTAL — Secondary Oscillator Connection. CLCIN1 TTL/ST — Configurable Logic Cell source input. CCP1 TTL/ST — Capture/Compare/PWM1 input. CCP2 TTL/ST — Capture/Compare/PWM2 input. OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). External clock input. CLKIN TTL/ST — C1OUT — CMOS Comparator output. NCO1 — CMOS NCO output. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. PWM5 — CMOS PWM5 output. PWM6 — CMOS PWM6 output. CWG1A — CMOS Complementary Waveform Generator Output A. CWG1B — CMOS Complementary Waveform Generator Output B. CWG1C — CMOS Complementary Waveform Generator Output C. CWG1D — CMOS Complementary Waveform Generator Output D. SDA1(3) — OD I2C data input/output. SDO1 — CMOS SPI data output. SCK1 — CMOS SPI clock output. SCL1(3) — OD I2C clock output. TX/CK — CMOS EUSART asynchronous TX data/synchronous clock output. DT — CMOS EUSART synchronous data output. CLC1OUT — CMOS Configurable Logic Cell 1 source output. CLC2OUT — CMOS Configurable Logic Cell 2 source output. DSM — CMOS Modulator output. TMR0 — CMOS TMR0 output. CLKR — CMOS Clock reference output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2019 Microchip Technology Inc. DS40001799F-page 12 PIC16(L)F18313/18323 TABLE 1-3: PIC16(L)F18323 PINOUT DESCRIPTION Name RA0/ANA0/C1IN0+/ DAC1OUT/ICSPDAT/ICDDAT RA1/ANA1/VREF+/C1IN0-/ C2IN0-/DAC1REF+/ICSPCLK/ ICDCLK RA2/ANA2/VREF-/DAC1REF-/ T0CKI(1)/CWG1IN(1)/INT(1) RA3/MCLR/VPP RA4/ANA4/T1G(1)/SOSCO/ OSC2/CLKOUT RA5/ANA5/T1CKI(1)/CLCIN3(1)/ SOSCI/SOSCIN/OSC1/CLKIN Function Input Type Output Type Description RA0 TTL/ST CMOS ANA0 AN — ADC Channel A0 input. General purpose I/O. C1IN0+ AN — Comparator C1 positive input. DAC1OUT — AN Digital-to-Analog Converter output. ICSPDAT TTL/ST — ICSP™ Data I/O. ICDDAT TTL/ST — In-Circuit Debug Data I/O. RA1 TTL/ST CMOS ANA1 AN — General purpose I/O. VREF+ AN — ADC Voltage Reference input. C1IN0- AN — Comparator C1 negative input. Comparator C2 negative input. ADC Channel A1 input. C2IN0- AN — DAC1REF+ AN — Digital-to-Analog Converter positive reference voltage input. ICSPCLK TTL/ST — Serial Programming Clock. ICDCLK TTL/ST — In-Circuit Debug Clock. RA2 TTL/ST CMOS ANA2 AN — ADC Channel A2 input. General purpose I/O. VREF- AN — ADC Negative Voltage Reference input. DAC1REF- AN — Digital-to-Analog Converter negative reference voltage input. T0CKI TTL/ST — TMR0 clock input. CWG1IN TTL/ST — Complementary Waveform Generator input. INT TTL/ST — RA3 TTL/ST CMOS MCLR TTL/ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4 TTL/ST CMOS ANA4 AN — External interrupt. General purpose I/O. General purpose I/O. ADC Channel A4 input. T1G TTL/ST — SOSCO — XTAL Secondary Oscillator Connection. TMR1 gate input. Crystal/Resonator (LP, XT, HS modes). OSC2 — XTAL CLKOUT — CMOS FOSC/4 output. RA5 TTL/ST CMOS General purpose I/O. ANA5 AN — ADC Channel A5 input. T1CKI TTL/ST — TMR1 clock input. CLCIN3 TTL/ST — Configurable Logic Cell source input. SOSCI XTAL — Secondary Oscillator Connection. SOSCIN TTL/ST — Secondary Oscillator Input Connection. OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). CLKIN TTL/ST — External clock input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2019 Microchip Technology Inc. DS40001799F-page 13 PIC16(L)F18313/18323 TABLE 1-3: PIC16(L)F18323 PINOUT DESCRIPTION (CONTINUED) Name RC0/ANC0/C2IN0+/SCL1(1)/ SCK1(1) RC1/ANC1/C1IN1-/C2IN1-/ SDA1(1)/SDI1(1)/CLCIN2(1) RC2/ANC2/C1IN2-/C2IN2-/ MDCIN1(1) RC3/ANC3/C1IN3-/C2IN3-/ MDMIN(1)/CCP2(1)/CLCIN0(1)/ SS1(1) RC4/ANC4/CLCIN1 (1) RC5/ANC5/MDCIN2(1)/CCP1(1)/ RX(1) Function Input Type Output Type RC0 TTL/ST CMOS Description General purpose I/O. ANC0 AN — ADC Channel C0 input. C2IN0+ AN — Comparator positive input. SCL1 I 2C OD I2C clock. SCK1 TTL/ST — SPI clock. RC1 TTL/ST CMOS ANC1 AN — ADC Channel C1 input. General purpose I/O. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. SDA1 2 OD I2C data. I C SDI1 TTL/ST — SPI data input. CLCIN2 TTL/ST — Configurable Logic Cell source input. RC2 TTL/ST CMOS General purpose I/O. ANC2 AN — ADC Channel C2 input. C1IN2- AN — Comparator C1 negative input. C2IN2- AN — Comparator C2 negative input. MDCIN1 TTL/ST — Modular Carrier input 1. RC3 TTL/ST CMOS ANC3 AN — ADC Channel C3 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. MDMIN TTL/ST — Modular Source input. CCP2 TTL/ST — Capture/Compare/PWM2. CLCIN0 TTL/ST — Configurable Logic Cell source input. SS1 TTL/ST — Slave Select input. RC4 TTL/ST CMOS ANC4 AN — ADC Channel C4 input. Configurable Logic Cell source input. CLCIN1 TTL/ST — RC5 TTL/ST CMOS General purpose I/O. General purpose I/O. General purpose I/O. ANC5 AN — ADC Channel C5 input. MDCIN2 TTL/ST — Modular Carrier input 2. CCP1 TTL/ST — Capture/Compare/PWM1. RX TTL/ST — EUSART asynchronous input. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2019 Microchip Technology Inc. DS40001799F-page 14 PIC16(L)F18313/18323 TABLE 1-3: PIC16(L)F18323 PINOUT DESCRIPTION (CONTINUED) Name OUT(2) Function Input Type Output Type C1OUT — CMOS Comparator output. C2OUT — CMOS Comparator output. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. PWM5 — CMOS PWM5 output. Description PWM6 — CMOS PWM6 output. CWG1A — CMOS Complementary Waveform Generator Output A. CWG1B — CMOS Complementary Waveform Generator Output B. CWG1C — CMOS Complementary Waveform Generator Output C. CWG1D — CMOS SDA1(3) — OD SDO1 — CMOS SPI data output. SCK1 — CMOS SPI clock output. — OD I2C clock output. SCL1 (3) Complementary Waveform Generator Output D. I2C data input/output. TX/CK — CMOS EUSART asynchronous TX data/synchronous clock output. DT — CMOS EUSART synchronous data output. CLC1OUT — CMOS Configurable Logic Cell 1 source output. CLC2OUT — CMOS Configurable Logic Cell 2 source output. NCO1 — CMOS Numerically controlled oscillator output. DSM — CMOS Data Signal Modulator output. TMR0 — CMOS TMR0 clock output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2015-2019 Microchip Technology Inc. DS40001799F-page 15 PIC16(L)F18313/18323 2.0 GUIDELINES FOR GETTING STARTED WITH PIC16(L)F183XX MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC16(L)F183XX family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • MCLR pin (when configured for external operation) (see Section 2.3 “Master Clear (MCLR) Pin”) These pins must also be connected if they are being used in the end application: • ICSPCLK/ICSPDAT pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.4 “ICSP™ Pins”) • OSC1 and OSC2 pins when an external oscillator source is used (see Section 2.5 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented The minimum mandatory connections are shown in Figure 2-1. FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS (Note 1) C2 R1 VSS VDD VDD R2 MCLR/VPP C1 PIC16(L)F1xxx VSS Key (all values are recommendations): C1 and C2: 0.1 PF, 20V ceramic R1: 10 kȍ R2: 100ȍ to 470ȍ Note1: Only when MCLRE configuration bit is 1 and the MCLR pin does not have a weak pull-up.  2015-2019 Microchip Technology Inc. 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required. All VDD and VSS pins must be connected. None can be left floating. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 µF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 µF in parallel with 0.001 µF). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. DS40001799F-page 16 PIC16(L)F18313/18323 2.3 Master Clear (MCLR) Pin The MCLR pin provides three specific device functions: • Device Reset (when MCLRE = 1) • Digital input pin (when MCLRE = 0) • Device Programming and Debugging If programming and debugging are not required in the end application then either set the MCLRE configuration bit to ‘1’ and use the pin as a digital input or clear the MCLRE Configuration bit and leave the pin open to use the internal weak pull-up. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, the programmer MCLR/VPP output should be connected directly to the pin so that R1 isolates the capacitor, C1 from the MCLR pin during programming and debugging operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. 2.4 ICSP™ Pins The ICSPCLK and ICSPDAT pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω. Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be isolated from the programmer by resistors between the application and the device pins or removed from the circuit during programming. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/ emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 37.0 “Development Support”.  2015-2019 Microchip Technology Inc. DS40001799F-page 17 PIC16(L)F18313/18323 2.5 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 7.0 “Oscillator Module” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-2. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. 2.6 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins and drive the output logic low. FIGURE 2-2: Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 ` OSC2 GND C2 ` SOSCO SOSCI Secondary Oscillator (SOSC) Crystal In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). ` SOSC: C1 For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate website (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT SOSC: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS  2015-2019 Microchip Technology Inc. DS40001799F-page 18 PIC16(L)F18313/18323 3.0 ENHANCED MID-RANGE CPU The hardware stack is 16-levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 48 instructions. Interrupt capability includes automatic context saving. FIGURE 3-1: CORE DATA PATH BLOCK DIAGRAM Rev. 10-000055B 8/23/2016 15 Configuration 15 MUX Flash Program Memory Data Bus 16-Level Stack (15-bit) RAM 14 Program Bus 8 Program Counter 12 Program Memory Read (PMR) RAM Addr Addr MUX Instruction Reg Direct Addr 7 5 Indirect Addr 12 12 BSR Reg 15 FSR0 Reg 15 FSR1 Reg STATUS Reg 8 Instruction Decode and Control OSC1/CLKIN OSC2/CLKOUT SOSCI Timing Generation Power-up Timer Power-on Reset Watchdog Timer Brown-out Reset 3 8 MUX ALU W Reg SOSCO VDD VSS Internal Oscillator Block  2015-2019 Microchip Technology Inc. DS40001799F-page 19 PIC16(L)F18313/18323 3.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 “Automatic Context Saving” for more information. 3.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON0 register, and if enabled, will cause a software Reset. See Section 4.4 “Stack” for more details. 3.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers, program memory, and data EEPROM, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. See Section 4.5 “Indirect Addressing” for more details. 3.4 Instruction Set There are 48 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 34.0 “Instruction Set Summary” for more details.  2015-2019 Microchip Technology Inc. DS40001799F-page 20 PIC16(L)F18313/18323 4.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - Revision ID - User ID - Program Flash Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • Data EEPROM 4.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 4-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 4-1). TABLE 4-1: DEVICE SIZES AND ADDRESSES Device PIC16(L)F18313/18323  2015-2019 Microchip Technology Inc. Program Memory Size (Words) Last Program Memory Address 2048 07FFh DS40001799F-page 21 PIC16(L)F18313/18323 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F18313/18323 PC[14:0] CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 Stack Level 0 Stack Level 1 Interrupt Vector On-chip Program Memory 0000h 0004h 0005h 07FFh 0800h Wraps to Page 0  2015-2019 Microchip Technology Inc. EXAMPLE 4-1: constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W Wraps to Page 0 Rollover to Page 0 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 4-1. Page 0-3 Rollover to Page 0 Wraps to Page 0 READING PROGRAM MEMORY AS DATA There are three methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. The third method is to use the NVMCON registers to access the program memory. 4.1.1.1 Stack Level 15 Reset Vector 4.1.1 The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, computed GOTO method must be used because the BRW instruction is not available in some devices, such as the PIC16F6XX, PIC16F7XX, PIC16F8XX, and PIC16F9XX devices. 7FFFh DS40001799F-page 22 PIC16(L)F18313/18323 4.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of an FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that read the program memory via the FSR require one extra instruction cycle to complete. Example 4-2 demonstrates reading the program memory via an FSR. Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. FIGURE 4-2: 00h ACCESSING PROGRAM MEMORY VIA FSR Special Function Registers 1Fh 4.2 Data Memory Organization The data memory is partitioned into 32 memory banks with 128 bytes in each bank. Each bank consists of (Figure 4-2): • • • • 12 core registers Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM 4.2.1 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) NVMREG Access The NVMREG interface allows read/write access to all locations accessible by the FSRs, User ID locations, and EEPROM. The NVMREG interface also provides read-only access to Device ID, Revision ID, and Configuration data. See Section 11.4 “NVMREG Access” for more information. BANK SELECTION The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 4.5 “Indirect Addressing”” for more information.  2015-2019 Microchip Technology Inc. Core Registers (12 bytes) 0Bh 0Ch constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 4.1.1.3 Memory Region 7-bit Bank Offset The HIGH directive will set bit 7 if a label points to a location in the program memory. EXAMPLE 4-2: BANKED MEMORY PARTITIONING 7Fh 4.2.2 CORE REGISTERS The core registers contain the registers that directly affect basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x80h through x0Bh/x8Bh). These registers are listed below in Table 4-2. For detailed information, see Table 4-4. TABLE 4-2: CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON DS40001799F-page 23 PIC16(L)F18313/18323 4.2.2.1 STATUS Register The STATUS register, shown in Register 4-1, contains: • The arithmetic status of the ALU • The Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 4-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 34.0 “Instruction Set Summary”). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 — For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). U-0 — R-1/q — TO R-1/q PD R/W-0/u R/W-0/u R/W-0/u Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2015-2019 Microchip Technology Inc. DS40001799F-page 24 PIC16(L)F18313/18323 4.2.3 SPECIAL FUNCTION REGISTERS 4.2.5 The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh), with the exception of banks 27, 28, and 29 (PPS and CLC registers). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 4.2.4 COMMON RAM There are 16 bytes of common RAM accessible from all banks. 4.2.6 DEVICE MEMORY MAPS The memory maps for PIC16(L)F18313/18323 are as shown in Table 4-4. GENERAL PURPOSE RAM There are up to 80 bytes of GPR in each data memory bank. The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 4.5.2 “Linear Data Memory” for more information. TABLE 4-3: Bank Offset Name SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (ALL BANKS) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets All Banks 000h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h PCL 003h STATUS 004h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h FSR1H Indirect Data Memory Address 1 High Pointer 008h BSR 009h WREG 00Ah PCLATH Program Counter (PC) Least Significant Byte — — — — — TO 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 — BSR4 BSR3 — — — BSR2 BSR1 BSR0 Working Register — — ---1 1000 ---q quuu ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper three bits ---- -000 ---- -000 of the Program Counter 00Bh Legend: Note 1: INTCON GIE PEIE — — — — — INTEDG 00-- ---1 00-- ---1 x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. These Registers can be accessed from any bank  2015-2019 Microchip Technology Inc. DS40001799F-page 25 Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets RA1 RA0 --xx xxxx --uu uuuu Bank 0 CPU CORE REGISTERS; see Table 4-2 for specifics 00Ch PORTA 00Dh 00Eh ― ― PORTC X 010h RA5 RA4 ― ― 00Fh ― ― ― X ― ― RC5 RA3 ― ― Unimplemented ― ― --xx xxxx --uu uuuu RC4 ― RA2 Unimplemented RC3 RC2 RC1 RC0 Unimplemented PIR0 ― ― TMR0IF TMR1GIF ADIF ― ― ― ― INTF --00 ---0 --00 ---0 IOCIF ― ― ― RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 0000 0000 0000 0000 C1IF NVMIF ― ― ― NCO1IF 0000 0000 0000 0000 PIR1 012h PIR2 ― C2IF C1IF NVMIF ― ― ― NCO1IF 0000 0000 0000 0000 013h PIR3 OSFIF CSWIF ― ― ― ― CLC2IF CLC1IF 0000 0000 0000 0000 014h PIR4 ― CWG1IF ― ― ― ― CCP2IF CCP1IF 0000 0000 0000 0000 015h TMR0L TMR0[7:0] 0000 0000 0000 0000 016h TMR0H TMR0[15:8] 1111 1111 1111 1111 017h T0CON0 0-00 0000 018h T0CON1 019h TMR1L 01Ah TMR1H 01Bh T1CON 01Ch T1GCON 01Dh TMR2 01Eh PR2 X ― ― X T0EN ― T0OUT T0CS[2:0] T016BIT T0OUTPS[3:0] 0-00 0000 T0ASYNC T0CKPS[3:0] 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1L[7:0] TMR1H[7:0] TMR1CS[1:0] TMR1GE T1GPOL T1CKPS[1:0] T1GTM T1GSPM T1SOSC T1SYNC T1GGO/ DONE T1GVAL ― TMR1ON T1GSS[1:0] uuuu uxuu DS40001799F-page 26 0000 0000 0000 0000 PR2[7:0] 1111 1111 1111 1111 -000 0000 -000 0000 T2CON Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. T2OUTPS[3:0] uuuu uu-u 0000 0x00 TMR2[7:0] 01Fh ― 0000 00-0 TMR2ON T2CKPS[1:0] PIC16(L)F18313/18323 011h PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets TRISA1 TRISA0 Bank 1 CPU CORE REGISTERS; see Table 4-2 for specifics 08Ch TRISA 08Dh 08Eh ― ― TRISC 08Fh X ― ― X ― 090h PIE0 091h PIE1 092h PIE2 093h PIE3 094h PIE4 ― TRISA5 TRISA4 ― TRISA2 --11 -111 --11 -111 ― ― Unimplemented ― ― --11 1111 ― ― TRISC5 TRISC4 ― ― TMR0IE IOCIE ― ― Unimplemented TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 ― ― ― ― ― INTE --00 ---0 --00 ---0 Unimplemented TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 0000 0000 0000 0000 X ― ― ― C1IE NVMIE ― ― ― NCO1IE 0000 0000 0000 0000 ― X ― C2IE C1IE NVMIE ― ― ― NCO1IE 0000 0000 0000 0000 OSFIE CSWIE ― ― ― ― CLC2IE CLC1IE 0000 0000 0000 0000 ― CWG1IE ― ― ― ― CCP2IE CCP1IE 0000 0000 0000 0000 095h ― ― Unimplemented ― ― 096h ― ― Unimplemented ― ― --01 0110 --01 0110 097h WDTCON ― ― WDTPS[4:0] SWDTEN 098h ― ― Unimplemented ― ― 099h ― ― Unimplemented ― ― 09Ah ― ― Unimplemented ― ― 09Bh ADRESL ADRESL[7:0] xxxx xxxx uuuu uuuu  2015-2019 Microchip Technology Inc. 09Ch ADRESH 09Dh ADCON0 ADRESH[7:0] 09Eh ADCON1 09Fh ADACT Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. CHS[5:0] ADFM ― GO/DONE ADCS[2:0] ― ― ― ― ADNREF ADON ADPREF[1:0] ADACT[3:0] xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 -000 0000 -000 ---- 0000 ---- 0000 PIC16(L)F18313/18323 DS40001799F-page 27 TABLE 4-4: Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets LATA1 LATA0 Bank 2 CPU CORE REGISTERS; see Table 4-2 for specifics 10Ch LATA 10Dh 10Eh ― ― LATC ― LATA5 ― X ― ― X ― ― LATC5 LATA4 ― LATA2 --xx -xxx --uu -uuu Unimplemented ― ― Unimplemented ― ― --xx xxxx --uu uuuu ― LATC4 LATC3 LATC2 LATC1 LATC0 10Fh ― ― Unimplemented ― 110h ― ― Unimplemented ― ― 00-0 -100 00-0 -100 0000 0000 0000 0000 111h CM1CON0 112h CM1CON1 113h CM2CON0 115h CM2CON1 CMOUT ― ― X C1OUT C1INTP C1INTN ― C1POL ― C1SP C1PCH[2:0] C1NCH[2:0] C2ON C2OUT ― C2POL ― C2SP C2SYNC ― 00-0 -100 00-0 -100 X ― X C2INTP C2INTN X ― ― ― ― ― ― ― ― MC1OUT ---- ---0 ---- ---0 ― X ― ― ― ― ― ― MC2OUT MC1OUT ---- --00 ---- --00 ― ― ― BORRDY 1--- ---q u--- ---u 0q00 0000 0q00 0000 0-0- 00-0 0-0- 00-0 ---0 0000 ---0 0000 ― ― Unimplemented C2PCH[2:0] C2NCH[2:0] BORCON SBOREN Reserved ― ― FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR[1:0] 118h DACCON0 DAC1EN ― DAC1OE ― DAC1PSS[1:0] 119h DACCON1 ― ― ― Legend: Note 1: C2HYS ― ― 117h ― C1SYNC Unimplemented 116h 11Ah-11Fh C1HYS ― ADFVR[1:0] ― DAC1NSS DAC1R[4:0] Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. ― ― 0000 0000 0000 0000 DS40001799F-page 28 PIC16(L)F18313/18323 114h X C1ON PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets ANSA1 ANSA0 Bank 3 CPU CORE REGISTERS; see Table 4-2 for specifics 18Ch ANSELA 18Dh ― 18Eh ANSELC ― ― ANSA5 ― X ― ― X ― ― ANSC5 ANSA4 ― ANSA2 --11 -111 --11 -111 Unimplemented ― ― Unimplemented ― ― --11 1111 --11 1111 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 18Fh ― ― Unimplemented ― ― 190h ― ― Unimplemented ― ― 191h ― ― Unimplemented ― ― 192h ― ― Unimplemented ― ― 193h ― ― Unimplemented ― ― 194h ― ― Unimplemented ― ― 195h ― ― Unimplemented ― ― 196h ― ― Unimplemented ― ― 197h VREGCON(1) ---- --01 ---- --01 198h ― 199h RC1REG ― ― ― ― ― ― ― VREGPM Reserved Unimplemented ― ― RC1REG[7:0] 0000 0000 0000 0000 0000 0000  2015-2019 Microchip Technology Inc. 19Ah TX1REG TX1REG[7:0] 0000 0000 19Bh SP1BRGL SP1BRG[7:0] 0000 0000 0000 0000 19Ch SP1BRGH SP1BRG[15:8] 0000 0000 0000 0000 19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUD1CON ABDOVF RCIDL ― SCKP BRG16 ― WUE ABDEN 01-0 0-00 01-0 0-00 Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. PIC16(L)F18313/18323 DS40001799F-page 29 TABLE 4-4: Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets WPUA1 WPUA0 Bit 2 Bank 4 CPU CORE REGISTERS; see Table 4-2 for specifics 20Ch WPUA 20Dh 20Eh ― ― WPUC ― WPUA5 WPUA4 ― X ― ― X ― ― WPUC5 WPUA3 WPUA2 --00 0000 --00 0000 Unimplemented ― ― Unimplemented ― ― --00 0000 --00 0000 ― WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 20Fh ― ― Unimplemented ― 210h ― ― Unimplemented ― ― SSP1BUF[7:0] xxxx xxxx uuuu uuuu SSP1BUF 212h SSP1ADD SSP1ADD[7:0] 0000 0000 0000 0000 213h SSP1MSK SSP1MSK[7:0] 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 ― ― 218h-21Fh Legend: Note 1: ― ― S R/W UA BF SSPM[3:0] Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. DS40001799F-page 30 PIC16(L)F18313/18323 211h PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets ODCA1 ODCA0 Bank 5 CPU CORE REGISTERS; see Table 4-2 for specifics 28Ch ODCONA 28Dh ― 28Eh ODCONC ― ― ODCA5 ― X ― ― X ― ― ODCC5 ODCA4 ― ODCA2 --00 -000 --00 -000 Unimplemented ― ― Unimplemented ― ― --00 0000 --00 0000 ― ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 28Fh ― ― Unimplemented ― 290h ― ― Unimplemented ― ― 291h CCPR1L CCPR1[7:0] xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0-x0 0000 0-x0 0000 ---- 0000 ---- xxxx 292h CCPR1H 293h CCP1CON CCP1EN ― CCP1OUT CCP1FMT CCPR1[15:8] 294h CCP1CAP ― ― ― ― 295h CCPR2L CCPR2[7:0] xxxx xxxx xxxx xxxx 296h CCPR2H CCPR2[15:8] xxxx xxxx xxxx xxxx 297h CCP2CON CCP2EN ― CCP2OUT CCP2FMT 0-x0 0000 0-x0 0000 298h CCP2CAP ― ― ― ― ---- -000 ---- -xxx CCP1MODE[3:0] ― CCP1CTS[2:0] CCP2MODE[3:0] ― CCP2CTS[2:0]  2015-2019 Microchip Technology Inc. 299h ― ― Unimplemented ― ― 29Ah ― ― Unimplemented ― ― 29Bh ― ― Unimplemented ― ― 29Ch ― ― Unimplemented ― ― 29Dh ― ― Unimplemented ― ― 29Eh ― ― Unimplemented ― ― 29Fh ― ― Unimplemented ― ― Bank 6 30Ch 30Dh 30Eh 30Fh-31Fh Legend: Note 1: SLRCONA — — SLRCONC — — SLRA5 — X — — X — — — SLRC5 SLRA4 — SLRA2 SLRA1 SLRA0 --11 -111 --11 -111 Unimplemented — — Unimplemented — — --11 1111 --11 1111 — — SLRC4 SLRC3 SLRC2 SLRC1 Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. SLRC0 PIC16(L)F18313/18323 DS40001799F-page 31 TABLE 4-4: Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets INLVLA1 INLVLA0 Bit 2 Bank 7 CPU CORE REGISTERS; see Table 4-2 for specifics 38Ch INLVLA 38Dh 38Eh ― ― INLVLC ― INLVLA5 ― X ― ― X ― ― INLVLC5 INLVLA4 INLVLA3 INLVLA2 --11 1111 --11 1111 Unimplemented ― ― Unimplemented ― ― --11 1111 --11 1111 ― INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 38Fh ― ― Unimplemented ― 390h ― ― Unimplemented ― ― --00 0000 --00 0000 391h IOCAP ― ― IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 392h IOCAN ― ― IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF ― ― IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 ― ― Unimplemented ― ― 395h ― ― Unimplemented ― ― 396h ― ― Unimplemented ― ― Unimplemented ― ― --00 0000 397h 398h 399h 39Ah 39Bh 39Ch IOCCP IOCCN IOCCF X ― ― X X ― ― X X ― ― X CLKRCON ― ― ― IOCCP5 IOCCP4 ― ― IOCCN5 IOCCN4 ― ― IOCCF5 IOCCF4 CLKREN ― ― IOCCP3 IOCCP2 IOCCP1 IOCCP0 --00 0000 ― ― IOCCN2 IOCCN1 IOCCN0 --00 0000 --00 0000 ― ― IOCCF2 IOCCF1 IOCCF0 --00 0000 --00 0000 0--1 0000 0--1 0000 Unimplemented IOCCN3 Unimplemented ― IOCCF3 CLKRDC[1:0] CLKRDIV[2:0] Unimplemented MDCON MDEN ― ― MDOPOL MDOUT ― ― MDBIT ― ― 0--0 0--0 0--0 0--0 DS40001799F-page 32 39Dh MDSRC ― ― ― ― MDMS[3:0] ---- xxxx ---- uuuu 39Eh MDCARH ― MDCHPOL MDCHSYNC ― MDCH[3:0] -xx- xxxx -uu- uuuu 39Fh MDCARL ― MDCLPOL MDCLSYNC ― MDCL[3:0] -xx- xxxx -uu- uuuu Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. PIC16(L)F18313/18323 394h PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets — — Bank 8 CPU CORE REGISTERS; see Table 4-2 for specifics 40Ch-41Fh — — Unimplemented — — Unimplemented — — NCO1ACC[7:0] 0000 0000 0000 0000 Bank 9 48Ch-497h 498h NCO1ACCL 499h NCO1ACCH 49Ah NCO1ACCU NCO1ACC[15:8] 49Bh NCO1INCL 49Ch NCO1INCH 49Dh NCO1INCU ― 49Eh NCO1CON N1EN 49Fh NCO1CLK Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. ― ― ― 0000 0000 0000 0000 ---- 0000 ---- 0000 NCO1INC[7:0] 0000 0001 0000 0001 NCO1INC[15:8] 0000 0000 0000 0000 ---- 0000 ---- 0000 ― NCO1ACC[19:16] ― ― ― ― N1OUT N1POL ― ― ― ― ― N1PWS[2:0] NCO1INC[19:16] ― N1PFM N1CKS[1:0] 0-00 ---0 0-00 ---0 000- --00 000- --00 PIC16(L)F18313/18323 DS40001799F-page 33 TABLE 4-4:  2015-2019 Microchip Technology Inc. Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 10-11 CPU CORE REGISTERS; see Table 4-2 for specifics 50Ch-51Fh — — Unimplemented — — 58Ch-59Fh — — Unimplemented — — 60Ch ― ― Unimplemented ― ― 60Dh ― ― Unimplemented ― ― 60Eh ― ― Unimplemented ― ― 60Fh ― ― Unimplemented ― ― 610h ― ― Unimplemented ― ― 611h ― ― Unimplemented ― ― 612h ― ― Unimplemented ― ― 613h ― ― Unimplemented ― ― 614h ― ― Unimplemented ― ― 615h ― ― Unimplemented ― ― 616h ― ― Unimplemented ― ― xx-- ---- uu-- ---- Bank 12 PWM5DCL 618h PWM5DCH 619h PWM5CON 61Ah PWM6DCL 61Bh PWM6DCH 61Ch PWM6CON 61Dh-61Fh Legend: Note 1: ― PWM5DC[1:0] ― ― ― PWM5OUT PWM5POL ― ― ― ― ― xxxx xxxx uuuu uuuu ― ― ― ― 0-00 ---- 0-00 ---- ― ― ― ― xx-- ---- uu-- ---- xxxx xxxx uuuu uuuu 0-00 ---- 0-00 ---- ― ― PWM5DC[9:2] PWM5EN ― PWM6DC[1:0] PWM6DC[9:2] PWM6EN ― ― PWM6OUT PWM6POL ― ― ― Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. ― DS40001799F-page 34 PIC16(L)F18313/18323 617h PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 13 CPU CORE REGISTERS; see Table 4-2 for specifics 68Ch ― ― Unimplemented ― ― 68Dh ― ― Unimplemented ― ― 68Eh ― ― Unimplemented ― ― 68Fh ― ― Unimplemented ― ― 690h ― ― Unimplemented ― ― 691h CWG1CLKCON ― ― ― ― ---- ---0 ---- ---0 692h CWG1DAT ― ― ― ― 693h CWG1DBR ― ― ― ― ― CS DAT[3:0] DBR[5:0] 694h CWG1DBF ― ― 695h CWG1CON0 EN LD ― ― ― 696h CWG1CON1 ― ― IN ― POLD DBF[5:0] POLC POLB --00 0000 --00 0000 00-- -000 00-- -000 POLA --x- 0000 --x- 0000 697h CWG1AS0 SHUTDOWN REN ― ― 0001 01-- 0001 01-- CWG1AS1 ― ― ― ― AS3E AS2E(1) AS1E AS0E ---0 0000 ---0 0000 699h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000 ― ― Legend: Note 1: ― ― LSAC[1:0] ---- 0000 --00 0000 698h 69Ah-69Fh LSBD[1:0] MODE[2:0] ---- 0000 --00 0000 Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. PIC16(L)F18313/18323 DS40001799F-page 35 TABLE 4-4:  2015-2019 Microchip Technology Inc. Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Banks 14-16 CPU CORE REGISTERS; see Table 4-2 for specifics 70Ch-71Fh — — Unimplemented — — 78Ch-79Fh — — Unimplemented — — 80Ch-81Fh — — Unimplemented — — 88Ch ― ― Unimplemented ― ― 88Dh ― ― Unimplemented ― ― 88Eh ― ― Unimplemented ― ― 88Fh ― ― Unimplemented ― ― 890h ― ― Unimplemented ― ― NVMADR[7:0] 0000 0000 0000 0000 1000 0000 1000 0000 Bank 17 891h NVMADRL NVMADRH NVMDATL 894h NVMDATH ― ― 895h NVMCON1 ― NVMREGS 896h NVMCON2 ― NVMADR[14:8] NVMDAT[7:0] NVMDAT[13:8] LWLO FREE WRERR WREN WR RD 0000 0000 0000 0000 --00 0000 --00 0000 -000 x000 -000 q000 NVMCON2[7:0] 0000 0000 0000 0000 897h ― ― Unimplemented ― ― 898h ― ― Unimplemented ― ― 899h ― ― Unimplemented ― ― 89Ah ― ― Unimplemented ― ― 00-1 110q qq-q qquu ― ― 89Bh 89Ch-89Fh Legend: Note 1: PCON0 ― STKOVF ― STKUNF ― RWDT RMCLR RI POR Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. BOR DS40001799F-page 36 PIC16(L)F18313/18323 892h 893h PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 18 CPU CORE REGISTERS; see Table 4-2 for specifics 90Ch ― ― Unimplemented ― ― 90Dh ― ― Unimplemented ― ― 90Eh ― ― Unimplemented ― ― 90Fh ― ― Unimplemented ― ― 910h ― ― Unimplemented ― ― 00-- -000 00-- -000 911h PMD0 912h PMD1 913h PMD2 914h PMD3 915h PMD4 916h PMD5 917h 918h SYSCMD ― FVRMD ― ― ― NVMMD CLKRMD IOCMD NCOMD ― ― ― ― TMR2MD TMR1MD TMR0MD 0--- -000 0--- -000 X ― ― DACMD ADCMD ― ― ― CMP1MD ― -00- --0- -00- --0- ― X ― DACMD ADCMD ― ― CMP2MD CMP1MD ― -00- -00- -00- -00- ― CWG1MD PWM6MD PWM5MD ― ― CCP2MD CCP1MD -000 --00 -000 --00 ― ― UART1MD ― ― ― MSSP1MD ― --0- --0- --0- --0- ― ― ― ― ― CLC2MD CLC1MD DSMMD ---- -000 ---- -000 ― Unimplemented CPUDOZE IDLEN DOZEN ROI DOE ― DOZE[2:0] ― ― 000- -000 000- -000 -qqq 0000  2015-2019 Microchip Technology Inc. 919h OSCCON1 ― NOSC[2:0] NDIV[3:0] -qqq 0000 91Ah OSCCON2 ― COSC[2:0] CDIV[3:0] -qqq 0000 -qqq 0000 91Bh OSCCON3 CSWHOLD 0000 0--- 0000 0--- 91Ch OSCSTAT1 91Dh OSCEN 91Eh 91Fh Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. SOSCPWR SOSCBE ORDY NOSCR ― ― ― EXTOR HFOR ― LFOR SOR ADOR ― PLLR qq-q qq-q qq-q qq-q EXTOEN HFOEN ― LFOEN SOSCEN ADOEN ― ― 00-0 00-- 00-0 00-- OSCTUNE ― ― --10 0000 --10 0000 OSCFRQ ― ― ― ― ---- 0110 ---- 0110 HFTUN[5:0] HFFRQ[3:0] PIC16(L)F18313/18323 DS40001799F-page 37 TABLE 4-4: Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Banks 19-27 CPU CORE REGISTERS; see Table 4-2 for specifics 98Ch-9EFh — — Unimplemented — — A0Ch-A6Fh — — Unimplemented — — A8Ch-AEFh — — Unimplemented — — B0Ch-B6Fh — — Unimplemented — — B8Ch-BEFh — — Unimplemented — — C0Ch-C1Fh — — Unimplemented — — C8Ch-CEFh — — Unimplemented — — D0Ch-D6Fh — — Unimplemented — — D8Ch-D6Fh — — Unimplemented — — x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. DS40001799F-page 38 PIC16(L)F18313/18323 Legend: Note 1: PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Banks 28 CPU CORE REGISTERS; see Table 4-2 for specifics E0Ch — — Unimplemented — — E0Dh — — Unimplemented — — E0Eh — — Unimplemented — — ---- ---0 ---- ---0 E0Fh E10h PPSLOCK — — — INTPPS — — — INTPPS[4:0] ---0 0010 ---u uuuu E11h T0CKIPPS — — — T0CKIPPS[4:0] ---0 0010 ---u uuuu E12h T1CKIPPS — — — T1CKIPPS[4:0] ---0 0101 ---u uuuu E13h T1GPPS — — — T1GPPS[4:0] ---0 0100 ---u uuuu ---u uuuu E14h E15h CCP1PPS CCP2PPS — — — — PPSLOCKED X — — — — CCP1PPS[4:0] ---0 0101 — X — — — CCP1PPS[4:0] ---1 0101 ---u uuuu X — — — — CCP2PPS[4:0] ---0 0101 ---u uuuu — X — — — CCP2PPS[4:0] ---1 0011 ---u uuuu — E16h — — Unimplemented — E17h — — Unimplemented — — CWG1PPS[4:0] ---0 0010 ---u uuuu E18h E19h E1Ah  2015-2019 Microchip Technology Inc. E1Bh E1Ch — — — — — — — — — MDCIN1PPS[4:0] ---0 0000 ---u uuuu — X — — — MDCIN1PPS[4:0] ---1 0010 ---u uuuu X — — — — MDCIN2PPS[4:0] ---0 0101 ---u uuuu — X — — — MDCIN2PPS[4:0] ---1 0101 ---u uuuu X — — — — MDMINPPS[4:0] ---0 0001 ---u uuuu — X — — — MDMINPPS[4:0] ---1 0011 ---u uuuu CWG1PPS — MDCIN1PPS MDCIN2PPS MDMINPPS — X Unimplemented E1Dh — — Unimplemented — — E1Eh — — Unimplemented — — E1Fh — — Unimplemented — — ---u uuuu ---u uuuu E20h Legend: Note 1: SSP1CLKPPS X — — — — SSP1CLKPPS[4:0] ---0 0001 — X — — — SSP1CLKPPS[4:0] ---1 0000 x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. PIC16(L)F18313/18323 DS40001799F-page 39 TABLE 4-4: E21h E22h E23h E24h E25h Name SSP1DATPPS SSP1SSPPS PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 X — — — — SSP1DATPPS[4:0] ---0 0010 ---u uuuu — X — — — SSP1DATPPS[4:0] ---1 0001 ---u uuuu X — — — — SSP1SSPPS[4:0] ---0 0011 ---u uuuu — X — — — SSP1SSPPS[4:0] ---1 0011 ---u uuuu — RXPPS TXPPS Bit 6 Bit 5 — X Bit 4 Bit 3 Bit 2 Bit 1 Unimplemented Bit 0 Value on: POR, BOR Value on all other Resets — — — — — — RXPPS[4:0] ---0 0001 ---u uuuu — X — — — RXPPS[4:0] ---0 0101 ---u uuuu X — — — — TXPPS[4:0] ---0 0000 ---u uuuu — X — — — TXPPS[4:0] ---1 0100 ---u uuuu — E26h — — Unimplemented — E27h — — Unimplemented — — E28h E29h Legend: Note 1: CLCIN1PPS — — — — — CLCIN0PPS[4:0] ---0 0011 ---u uuuu — X — — — CLCIN0PPS[4:0] ---1 0011 ---u uuuu X — — — — CLCIN1PPS[4:0] ---0 0101 ---u uuuu — X — — — CLCIN1PPS[4:0] ---1 0100 ---u uuuu — — — Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. DS40001799F-page 40 PIC16(L)F18313/18323 E2Ah-E6Fh CLCIN0PPS X PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 29 CPU CORE REGISTERS; see Table 4-2 for specifics E8Ch-E8Fh — — — RA0PPS — — — RA0PPS[4:0] ---0 0000 ---u uuuu RA1PPS — — — RA1PPS[4:0] ---0 0000 ---u uuuu — — — RA2PPS[4:0] ---0 0000 ---u uuuu E90h E91h E92h RA2PPS E93h — E94h RA4PPS E95h RA5PPS E96h-E9Fh EA0h EA1h — — Unimplemented — Unimplemented — — — — — — — RA4PPS[4:0] RA5PPS[4:0] Unimplemented — — ---0 0000 ---u uuuu ---0 0000 ---u uuuu ---0 0000 ---u uuuu RC0PPS — — — RC0PPS[4:0] ---0 0000 ---u uuuu RC1PPS — — — RC1PPS[4:0] ---0 0000 ---u uuuu EA2h RC2PPS — — — RC2PPS[4:0] ---0 0000 ---u uuuu EA3h RC3PPS — — — RC3PPS[4:0] ---0 0000 ---u uuuu EA4h RC4PPS — — — RC4PPS[4:0] ---0 0000 ---u uuuu EA5h RC5PPS — — — RC5PPS[4:0] ---0 0000 ---u uuuu E97h — ---0 0000 ---u uuuu Legend: Note 1: — Unimplemented x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. PIC16(L)F18313/18323 DS40001799F-page 41 TABLE 4-4:  2015-2019 Microchip Technology Inc. Name PIC16(L)F18323 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18313  2015-2019 Microchip Technology Inc. TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 30 CPU CORE REGISTERS; see Table 4-2 for specifics F0Ch — — Unimplemented — — F0Dh — — Unimplemented — — F0Eh — — Unimplemented — — ---- --00 ---- --00 0-00 0000 0-00 0000 0--- xxxx 0--- uuuu F0Fh CLCDATA — — — — — — MLC2OUT MLC1OUT CLC1CON LC1EN — LC1OUT LC1INPT LC1INTN CLC1POL LC1POL — — — LC1G4POL F12h CLC1SEL0 — — — LC1D1S[4:0] ---x xxxx ---u uuuu F13h CLC1SEL1 — — — LC1D2S[4:0] ---x xxxx ---u uuuu F14h CLC1SEL2 — — — LC1D3S[4:0] ---x xxxx ---u uuuu F15h CLC1SEL3 — — — LC1D4S[4:0] ---x xxxx ---u uuuu F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu F1Ah CLC2CON LC2EN — LC2OUT LC2INPT LC2INTN 0-00 0000 0-00 0000 F1Bh CLC2POL LC2POL — — — LC2G4POL 0--- xxxx 0--- uuuu F1Ch CLC2SEL0 — — — LC2D1S[4:0] ---x xxxx ---u uuuu F1Dh CLC2SEL1 — — — LC2D2S[4:0] ---x xxxx ---u uuuu F1Eh CLC2SEL2 — — — LC2D3S[4:0] ---x xxxx ---u uuuu F1Fh CLC2SEL3 — — — LC2D4S[4:0] ---x xxxx ---u uuuu F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. LC1MODE[2:0] LC1G3POL LC1G2POL LC1G1POL LC2MODE[2:0] LC2G3POL LC2G2POL LC2G1POL PIC16(L)F18313/18323 DS40001799F-page 42 F10h F11h PIC16(L)F18323 Name PIC16(L)F18313 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets — — DC C ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu ---x -xxx ---- -uuu Bank 31 — only accessible from Debug Executive, unless otherwise specified CPU CORE REGISTERS; see Table 4-2 for specifics F8Ch-FE3h — FE4h(2) STATUS_SHAD FE5h(2) WREG_SHAD FE6h(2) — Unimplemented — — — BSR_SHAD — — — FE7h(2) PCLATH_SHAD — FE8h(2) FSR0L_SHAD FE9h(2) FEAh(2) FEBh(2) — — Z Working Register Normal (Non-ICD) Shadow Bank Select Register Normal (Non-ICD) Shadow Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx -uuu uuuu Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu Unimplemented — — ---x xxxx ---1 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FECh — — FEDh(2) STKPTR FEEh(2) TOSL FEFh(2) TOSH Legend: Note 1: x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18313/18323. — — — Current Stack Pointer Top of Stack Low Byte — Top of Stack Low Byte PIC16(L)F18313/18323 DS40001799F-page 43 TABLE 4-4:  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 4.3 PCL and PCLATH 4.3.2 The Program Counter (PC) is 15-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC[14:8]) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 4-3 shows the five situations for the loading of the PC. FIGURE 4-3: 14 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 0 PC 6 7 8 0 PCLATH Instruction with PCL as Destination ALU Result 14 PCH PCL 0 PC 6 4 0 PCLATH GOTO, CALL 11 OPCODE 14 PCH PCL 0 PC 6 7 0 PCLATH CALLW W 14 PCH PCL 0 PC BRW 15 PC + W 14 PCH PCL PC 0 BRA 15 PC + OPCODE 4.3.1 A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556). 4.3.3 MODIFYING PCL COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). If using the CALL instruction, the PCH[2:0] and PCL registers are loaded with the operand of the CALL instruction. PCH[6:3] is loaded with PCLATH[6:3]. The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 4.3.4 8 COMPUTED GOTO BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the signed 9-bit literal value ('k') of the operand of the BRA instruction is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC[14:8] bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.  2015-2019 Microchip Technology Inc. DS40001799F-page 44 PIC16(L)F18313/18323 4.4 Stack All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 4-4 through Figure 4-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer and does not cause a Reset when either a Stack Overflow or Underflow occur if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be Reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 4.4.1 ACCESSING THE STACK The stack is accessible through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be read to see how many levels remain available on the stack. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will write the PC and then decrement the STKPTR. Reference Figure 4-4 through Figure 4-7 for examples of accessing the stack. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.  2015-2019 Microchip Technology Inc. DS40001799F-page 45 PIC16(L)F18313/18323 FIGURE 4-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F - 1. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL FIGURE 4-5: 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL  2015-2019 Microchip Technology Inc. 0x00 Return Address STKPTR = 0x00 DS40001799F-page 46 PIC16(L)F18313/18323 FIGURE 4-6: ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL FIGURE 4-7: 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06 ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL  2015-2019 Microchip Technology Inc. 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 DS40001799F-page 47 PIC16(L)F18313/18323 4.5 Indirect Addressing 4.5.1 The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. TRADITIONAL/BANKED DATA MEMORY The banked data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into four memory regions: • • • • Traditional/Banked Data Memory Linear Data Memory Program Flash Memory EEPROM FIGURE 4-8: INDIRECT ADDRESSING Rev. 10-000044F 1/13/2017 0x0000 0x0000 Traditional Data Memory 0x1FFF 0x2000 Linear Data Memory 0X2FEF 0X2FF0 Reserved FSR Address Range 0x7FFF 0x8000 PC value = 0x000 Program Flash Memory 0x87FF  2015-2019 Microchip Technology Inc. PC value = 0x7FF DS40001799F-page 48 PIC16(L)F18313/18323 FIGURE 4-9: TRADITIONAL/BANKED DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select 0x00 FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x7F  2015-2019 Microchip Technology Inc. DS40001799F-page 49 PIC16(L)F18313/18323 4.5.2 4.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 4-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 4-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF 0xFFFF 0xF6F 4.5.4 0x7FFF DATA EEPROM MEMORY The EEPROM memory can be read or written through the NVMCON register interface (see Section 11.2 “Data EEPROM”). However, to make access to the EEPROM easier, read-only access to the EEPROM contents are also available through indirect addressing via an FSR. When the MSB of the FSR (ex: FSRxH) is set to 0x70, the lower 8-bit address value (in FSRxL) determines the EEPROM location that may be read (via the INDF register). In other words, the EEPROM address range 0x00-0xFF is mapped into the FSR address space between 0x7000 and 0x70FF. Writing to the EEPROM cannot be accomplished via the FSR/INDF interface. Reads from the EEPROM through the FSR/INDF interface will require one additional instruction cycle to complete.  2015-2019 Microchip Technology Inc. DS40001799F-page 50 PIC16(L)F18313/18323 5.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 5.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h, Configuration Word 2 at 8008h, Configuration Word 3 at 8009h, and Configuration Word 4 at 800Ah. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2015-2019 Microchip Technology Inc. DS40001799F-page 51 PIC16(L)F18313/18323 5.2 Register Definitions: Configuration Words REGISTER 5-1: CONFIGURATION WORD 1: OSCILLATORS R/P-1 U-1 R/P-1 U-1 U-1 R/P-1 FCMEN — CSWEN — — CLKOUTEN bit 13 U-1 R/P-1 — R/P-1 bit 8 R/P-1 U-1 RSTOSC[2:0] R/P-1 — R/P-1 R/P-1 FEXTOSC[2:0] bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = ON FSCM timer enabled 0 = OFF FSCM timer disabled bit 12 Unimplemented: Read as ‘1’ bit 11 CSWEN: Clock Switch Enable bit 1 = ON Writing to NOSC and NDIV is allowed 0 = OFF The NOSC and NDIV bits cannot be changed by user software bit 10-9 Unimplemented: Read as ‘1’ bit 8 CLKOUTEN: Clock Out Enable bit If FEXTOSC = EC, HS, HT or LP, then this bit is ignored; otherwise: 1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2 0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2 bit 7 Unimplemented: Read as ‘1’ bit 6-4 RSTOSC[2:0]: Power-up Default Value for COSC bits This value is the Reset default value for COSC, and selects the oscillator first used by user software 111 = EXT1X EXTOSC operating per FEXTOSC[2:0] bits 110 = HFINT1 HFINTOSC (1 MHz) 101 = Reserved 100 = LFINT LFINTOSC 011 = SOSC SOSC (32.768 kHz) 010 = Reserved 001 = EXT4X EXTOSC with 4x PLL; EXTOSC operating per FEXTOSC[2:0] bits 000 = HFINT32 HFINTOSC (32 MHz) bit 3 Unimplemented: Read as ‘1’ bit 2-0 FEXTOSC[2:0]: FEXTOSC External Oscillator Mode Selection bits 111 = ECH EC(External Clock) above 8 MHz 110 = ECM EC(External Clock) for 500 kHz to 8 MHz 101 = ECL EC(External Clock) below 500 kHz 100 = OFF Oscillator not enabled 011 = Unimplemented 010 = HS HS(Crystal oscillator) above 4 MHz 001 = XT HT(Crystal oscillator) above 100 kHz, below 4 MHz 000 = LP LP(Crystal oscillator) optimized for 32.768 kHz  2015-2019 Microchip Technology Inc. DS40001799F-page 52 PIC16(L)F18313/18323 REGISTER 5-2: CONFIGURATION WORD 2: SUPERVISORS R/P-1 R/P-1 R/P-1 U-1 R/P-1 U-1 DEBUG STVREN PPS1WAY — BORV — bit 13 R/P-1 R/P-1 BOREN[1:0] bit 8 R/P-1 LPBOREN U-1 (3) R/P-1 — R/P-1 WDTE[1:0] R/P-1 R/P-1 PWRTE MCLRE bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank bit 13 DEBUG: Debugger Enable bit(1) 1 = OFF Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins 0 = ON Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = ON Stack Overflow or Underflow will cause a Reset 0 = OFF Stack Overflow or Underflow will not cause a Reset bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit 1 = ON The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle 0 = OFF The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence) bit 10 Unimplemented: Read as ‘1’ bit 9 BORV: Brown-out Reset Voltage Selection bit(2) 1 = LOW Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices 0 = HIGH Brown-out Reset voltage (VBOR) set to 2.7V The higher voltage setting is recommended for operation at or above 16 MHz. bit 8 Unimplemented: Read as ‘1’ bit 7-6 BOREN[1:0]: Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit 11 = ON Brown-out Reset is enabled; SBOREN bit is ignored 10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = SBOREN Brown-out Reset is enabled according to SBOREN 00 = OFF Brown-out Reset is disabled bit 5 LPBOREN: Low-Power BOR Enable bit(3) 1 = OFF ULPBOR is disabled 0 = ON ULPBOR is enabled bit 4 Unimplemented: Read as ‘1’ bit 3-2 WDTE[1:0]: Watchdog Timer Enable bit 11 = ON WDT is enabled; SWDTEN is ignored 10 = SLEEP WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored 01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT is disabled; SWDTEN is ignored bit 1 PWRTE: Power-up Timer Enable bit 1 = OFF PWRT is disabled 0 = ON PWRT is enabled bit 0 MCLRE: Master Clear (MCLR) Enable bit If LVP = 1: RA3 pin function is MCLR. If LVP = 0: 1 = ON MCLR pin is MCLR. 0 = OFF MCLR pin function is port-defined function. Note 1: 2: 3: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. See VBOR parameter for specific trip point voltages. PIC16LF18313/18323 devices only.  2015-2019 Microchip Technology Inc. DS40001799F-page 53 PIC16(L)F18313/18323 REGISTER 5-3: CONFIGURATION WORD 3: MEMORY R/P-1 (1) LVP U-1 U-1 U-1 U-1 U-1 — — — — — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — R/P-1 R/P-1 WRT[1:0] bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = ON Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. 0 = OFF HV on MCLR/VPP must be used for programming. bit 12-2 Unimplemented: Read as ‘1’ bit 1-0 WRT[1:0]: User NVM Self-Write Protection bits 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write-protected, 0200h to 07FFh may be modified 01 = HALF 0000h to 03FFh write-protected, 0400h to 07FFh may be modified 00 = ALL 0000h to 07FFh write-protected, no addresses may be modified WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected. Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.  2015-2019 Microchip Technology Inc. DS40001799F-page 54 PIC16(L)F18313/18323 REGISTER 5-4: CONFIGURATION WORD 4: CODE PROTECTION U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — CPD CP bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13-2 Unimplemented: Read as ‘1’ bit 1 CPD: Data EEPROM Memory Code Protection bit 1 = OFF Data EEPROM code protection disabled 0 = ON Data EEPROM code protection enabled bit 0 CP: Program Memory Code Protection bit 1 = OFF Program Memory code protection disabled 0 = ON Program Memory code protection enabled  2015-2019 Microchip Technology Inc. DS40001799F-page 55 PIC16(L)F18313/18323 5.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data memory are controlled independently. Internal access to the program memory is unaffected by any code protection setting. 5.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Self-write writing the program memory is dependent upon the write protection setting. See Section 5.4 “Write Protection” for more information. 5.3.2 DATA MEMORY PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit in the Configuration Words. When CPD = 0, external reads and writes of EEPROM memory are inhibited and a read will return all ‘0’s. The CPU can continue to read and write EEPROM memory, regardless of the protection bit settings. 5.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT[1:0> bits in Configuration Words define the size of the program memory block that is protected. 5.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 11.4.7 “NVMREG EEPROM, User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F183XX Memory Programming Specification” (DS40001738). 5.6 Device ID and Revision ID The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See Section 11.4.7 “NVMREG EEPROM, User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.  2015-2019 Microchip Technology Inc. DS40001799F-page 56 PIC16(L)F18313/18323 5.7 Register Definitions: Device and Revision REGISTER 5-5: DEVID: DEVICE ID REGISTER R R R R R R DEV[13:8] bit 13 R R bit 8 R R R R R R DEV[7:0] bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared DEV[13:0]: Device ID bits Device DEVID[13:0] Values PIC16F18313 11 0000 0110 0110 (3066h) PIC16LF18313 11 0000 0110 1000 (3068h) PIC16F18323 11 0000 0110 0111 (3067h) PIC16LF18323 11 0000 0110 1001 (3069h) REGISTER 5-6: REVID: REVISION ID REGISTER R-1 R-0 R R R R REV[13:8] bit 13 R R bit 8 R R R R R R REV[7:0] bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 Note: ‘0’ = Bit is cleared REV[13:0]: Revision ID bits The upper two bits of the Revision ID Register will always read ‘10’.  2015-2019 Microchip Technology Inc. DS40001799F-page 57 PIC16(L)F18313/18323 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the on-chip Reset circuit is shown in Figure 6-1. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000006A 8/14/2013 ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE VPP/MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD BOR Active(1) Brown-out Reset LPBOR Reset Note 1: R LFINTOSC Power-up Timer PWRTE See Table 6-1 for BOR active conditions.  2015-2019 Microchip Technology Inc. DS40001799F-page 58 PIC16(L)F18313/18323 6.1 Power-on Reset (POR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. 6.2 Brown-out Reset (BOR) The BOR circuit holds the device in Reset while VDD is below a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The Brown-out Reset module has four operating modes controlled by the BOREN[1:0] bits in Configuration Words. The four operating modes are: • • • • BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 6-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset, and the BOR bit of the PCON0 register will be cleared, indicating that a Brown-out Reset condition occurred. See Figure 6-2 for more information. TABLE 6-1: BOR OPERATING MODES Instruction Execution upon: Release of POR or Wake-up from Sleep BOREN[1:0] SBOREN Device Mode BOR Mode 11 X X Active In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN[1:0] bits. 10 X Awake Active Waits for release of BOR (BORRDY = 1) Sleep Disabled Active 1 X 01 00 0 X Disabled X X Disabled  2015-2019 Microchip Technology Inc. BOR ignored when asleep In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN[1:0] bits. Begins immediately (BORRDY = x) DS40001799F-page 59 PIC16(L)F18313/18323 6.2.1 BOR IS ALWAYS ON 6.2.3 When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device wake from Sleep is not delayed by the BOR Ready condition or the VDD level only when the SBOREN bit is cleared in software and the device is starting up from a non POR/BOR Reset event. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 6.2.2 BOR CONTROLLED BY SOFTWARE BOR IS OFF IN SLEEP BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is unchanged by Sleep. BOR protection is not active during Sleep, but device wake-up will be delayed until the BOR can determine that VDD is higher than the BOR threshold. The device wake-up will be delayed until the BOR is ready. FIGURE 6-2: BROWN-OUT SITUATIONS VDD Internal Reset VBOR TPWRT(1) VDD Internal Reset VBOR < TPWRT TPWRT(1) VDD Internal Reset Note 1: 6.2.4 VBOR TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. BOR ALWAYS OFF When the BOREN bits of Configuration Word 2 are programmed to ‘00’, the BOR is always disable. In the configuration, setting the SWBOREN bit will have no affect on BOR operation.  2015-2019 Microchip Technology Inc. DS40001799F-page 60 PIC16(L)F18313/18323 6.3 Low-Power Brown-out Reset (LPBOR)(PIC16LF18313/18323 Devices Only) The Low-Power Brown-Out Reset (LPBOR) circuit provides alternative protection against Brown-out conditions for the PIC16LF18313/18323 devices only. When VDD falls below the LPBOR threshold, the device is held in Reset. When this occurs, the BOR bit of the PCON0 register is cleared to indicate that a Brown-out Reset occurred. The BOR bit will be cleared when either the BOR or the LPBOR circuitry detects a BOR condition. The LPBOR feature can be used with or without BOR enabled. When used while BOR is enabled, the LPBOR can be used as a secondary protection circuit in case the BOR circuit fails to detect the BOR condition. Additionally, when BOR is enabled except while in Sleep (BOREN[1:0] = 10), the LPBOR circuit will hold the device in Reset while VDD is lower than the LPBOR threshold, and will also re-arm the POR. (See Table 35-11 for LPBOR Reset voltage levels). The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 6.4.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.2 “PORTA Registers” for more information. 6.5 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register as well as the RWDT bit in the PCON0 register, are changed to indicate the WDT Reset. See Section 10.0 “Watchdog Timer (WDT)” for more information. 6.6 RESET Instruction When used without BOR enabled, the LPBOR circuit provides a single Reset trip point with the benefit of reduced current consumption. A RESET instruction will cause a device Reset. The RI bit in the PCON0 register will be set to ‘0’. See Table 6-4 for default conditions after a RESET instruction has occurred. 6.3.1 6.7 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 6.3.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON0 register and to the power control block. 6.4 MCLR The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2). TABLE 6-2: MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 6.4.1 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON0 register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 4.4 “Stack” for more information. 6.8 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a device Reset had just occurred. 6.9 Power-up Timer The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up.  2015-2019 Microchip Technology Inc. DS40001799F-page 61 PIC16(L)F18313/18323 6.10 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). MCLR must be released (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. The total time-out will vary based on oscillator configuration and Power-up Timer Configuration. See Section 7.0 “Oscillator Module” for more information. FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2015-2019 Microchip Technology Inc. DS40001799F-page 62 PIC16(L)F18313/18323 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON0 register are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during Normal Operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON0 Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during Normal Operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-0 uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu Brown-out Reset 0000h ---1 1000 00-1 11u0 ---1 0uuu uu-u uuuu Condition Interrupt Wake-up from Sleep PC + 1(1) RESET Instruction Executed 0000h ---u uuuu uu-u u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.  2015-2019 Microchip Technology Inc. DS40001799F-page 63 PIC16(L)F18313/18323 REGISTER 6-1: R/W-1/u SBOREN (1) BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-0-0 U-0 U-0 U-0 U-0 U-0 R-q/u Reserved — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit(1) If BOREN [1:0] in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN [1:0] in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 Reserved. Bit must be maintained as ‘0’. bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: 6.12 BOREN[1:0] bits are located in Configuration Words. Power Control (PCON0) Register The Power Control (PCON0) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON0 register bits are shown in Register 6-2. Hardware will change the corresponding register bit during the Reset process; if the Reset was not caused by the condition, the bit remains unchanged (Table 6-4). Software should reset the bit to the inactive state after the restart (hardware will not reset the bit). Software may also set any PCON0 bit to the active state, so that user code may be tested, but no Reset action will be generated.  2015-2019 Microchip Technology Inc. DS40001799F-page 64 PIC16(L)F18313/18323 6.13 Register Definitions: Power Control REGISTER 6-2: PCON0: POWER CONTROL REGISTER 0 R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF — R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or has been cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or has been cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) TABLE 6-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN Reserved — — — — — BORRDY 64 PCON0 STKOVF STKUNF — RWDT RMCLR RI POR BOR 65 STATUS — — — TO PD Z DC C 24 WDTCON — — SWDTEN 109 WDTPS[4:0] Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.  2015-2019 Microchip Technology Inc. DS40001799F-page 65 PIC16(L)F18313/18323 7.0 OSCILLATOR MODULE 7.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 7-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic resonators. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. The RSTOSC bits of Configuration Word 1 determine the type of oscillator that will be used when the device is reset, including when it is first powered-up. The internal clock modes, LFINTOSC, HFINTOSC (set at 1 MHz), or HFINTOSC (set at 32 MHz) can be set through the RSTOSC bits.  2015-2019 Microchip Technology Inc. If an external clock source is selected, the FEXTOSC bits of Configuration Word 1 must be used in conjunction with the RSTOSC bits to select the External Clock mode. The external oscillator module can be configured in one of the following clock modes by setting the FEXTOSC[2:0] bits of Configuration Word 1: 1. 2. 3. 4. 5. 6. ECL – External Clock Low-Power mode (500 kHz) ECM – External Clock Medium-Power mode ( 8 MHz) ECH – External Clock High-Power mode ( 32 MHz) LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (between 100 kHz and 4 MHz) HS – High Gain Crystal or Ceramic Resonator mode (above 4 MHz) The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source. The LP, XT, and HS Clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The INTOSC internal oscillator block produces low and high-frequency clock sources, designated LFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 7-1). DS40001799F-page 66 CLKIN/ OSC1 Rev. 10-000208L 3/13/2017 External Oscillator (EXTOSC) CLKOUT/ OSC2 CDIV 4x PLL Mode SOSCIN/SOSCI Secondary Oscillator (SOSC) SOSCO LFINTOSC PLL Block 2x PLL Mode 512 1001 111 256 1000 001 128 0111 64 0110 000 011 100 110 010 101 HFINTOSC Sleep System Clock 32 0101 16 0100 8 0011 4 0010 Sleep 2 0001 Idle 1 0000 SYSCMD HFFRQ 1 – 32 MHz Oscillator FSCM To Peripherals DS40001799F-page 67 To Peripherals To Peripherals Peripheral Clock PIC16(L)F18313/18323 31kHz Oscillator COSC 9-bit Postscaler Divider  2015-2019 Microchip Technology Inc. SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 7-1: PIC16(L)F18313/18323 7.2 Clock Source Types 7.2.1.1 Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes). There is also a secondary oscillator block which is optimized for a 32.768 kHz external clock source, which can be used as an alternate clock source. There are two internal oscillator blocks: - HFINTOSC - LFINTOSC The HFINTOSC can produce clock frequencies from 1-16 MHz. The LFINTOSC generates a 31 kHz clock frequency. There is a PLL that can be used by the external oscillator. See 7.2.1.4 “4x PLL” for more details. Additionally, there is a PLL that can be used by the HFINTOSC at certain frequencies. See Section 7.2.2.2 “2x PLL” for more details. 7.2.1 EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: • Program the RSTOSC[2:0] bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. • Write the NOSC[2:0] and NDIV[3:0] bits in the OSCCON1 register to switch the system clock source. See Section 7.3 information. “Clock Switching”  2015-2019 Microchip Technology Inc. for EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 7-2 shows the pin connections for EC mode. EC mode has three power modes to select from through Configuration Words: • ECH – High power,  32 MHz • ECM – Medium power,  8 MHz • ECL – Low power,  0.5 MHz The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 7-2: Clock from Ext. System FOSC/4 or I/O(1) Note 1: EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN PIC® MCU OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Words. more DS40001799F-page 68 PIC16(L)F18313/18323 7.2.1.2 LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 7-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive 32.768 kHz tuning-fork type crystals (watch crystals), but can operate up to 100 kHz. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive crystals and resonators with a frequency range up to 4 MHz. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require operating frequencies up to 20 MHz. FIGURE 7-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) Figure 7-3 and Figure 7-4 show typical circuits for quartz crystal and ceramic resonators, respectively. FIGURE 7-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) PIC® MCU OSC1/CLKIN C1 PIC® MCU RP(3) OSC1/CLKIN C1 RF(2) Sleep To Internal Logic Quartz Crystal RF(2) Sleep C2 Ceramic RS(1) Resonator Note 1: C2 To Internal Logic RS(1) OSC2/CLKOUT Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.  2015-2019 Microchip Technology Inc. OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. DS40001799F-page 69 PIC16(L)F18313/18323 7.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR), Brown-out Reset (BOR), or a wake-up from Sleep. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. 7.2.1.4 4x PLL The oscillator module contains a PLL that can be used with external clock sources to provide a system clock source. The input frequency for the PLL must fall within specifications. See the PLL Clock Timing Specifications in Table 35-9. The PLL may be enabled for use by one of two methods: 1. 2. Program the RSTOSC bits in the Configuration Word 1 to enable the EXTOSC with 4x PLL. Write the NOSC[2:0] bits in the OSCCON1 register to enable the EXTOSC with 4x PLL. 7.2.1.5 Secondary Oscillator The secondary oscillator is a separate oscillator block that can be used as an alternate system clock source. The secondary oscillator is optimized for 32.768 kHz, and can be used with an external crystal oscillator connected to the SOSCI and SOSCO device pins, or an external clock source connected to the SOSCIN pin. The secondary oscillator can be selected during run-time using clock switching. Refer to Section 7.3 “Clock Switching” for more information. FIGURE 7-5: Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PICmicro® Oscillator Design” (DS00849) • AN943, “Practical PICmicro® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) PIC® MCU SOSCI C1 To Internal Logic 32.768 kHz Quartz Crystal C2 SOSCO  2015-2019 Microchip Technology Inc. DS40001799F-page 70 PIC16(L)F18313/18323 7.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the RSTOSC[2:0] bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the NOSC[2:0] bits in the OSCCON1 register to switch the system clock source to the internal oscillator during run-time. See Section 7.3 “Clock Switching” for more information. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. The internal oscillator block has two independent oscillators that can produce two internal system clock sources. 1. 2. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates up to 32 MHz. The LFINTOSC (Low-Frequency Internal Oscillator) is factory calibrated and operates at 31 kHz. 7.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a precision digitally-controlled internal clock source that produces a stable clock up to 32 MHz. The HFINTOSC can be enabled through one of the following methods: • Programming the RSTOSC[2:0] bits in Configuration Word 1 to ‘110’ (1 MHz) or ‘000’ (32 MHz) to set the oscillator upon device Power-up or Reset • Write to the NOSC[2:0] bits of the OSCCON1 register during run-time The HFINTOSC frequency can be selected by setting the HFFRQ[2:0] bits of the OSCFRQ register. The NDIV[3:0] bits of the OSCCON1 register allow for division of the output of the selected clock source by a range between 1:1 and 1:512. 7.2.2.2 2x PLL The oscillator module contains a PLL that can be used with the HFINTOSC clock source to provide a system clock source. The input frequency to the PLL is limited to 8, 12, or 16 MHz, which will yield a system clock source of 16, 24, or 32 MHz, respectively. The PLL may be enabled for use by one of two methods: 1. 2.  2015-2019 Microchip Technology Inc. Program the RSTOSC bits in the Configuration Word 1 to ‘000’ to enable the HFINTOSC (32 MHz). This setting configures the HFFRQ[2:0] bits to ‘110’ (16 MHz) and activates the 2x PLL. Write ‘000’ the NOSC[2:0] bits in the OSCCON1 register to enable the 2x PLL, and write the correct value into the HFFRQ[3:0] bits of the OSCFRQ register to select the desired system clock frequency. See Register 6-6 for more information. DS40001799F-page 71 PIC16(L)F18313/18323 7.2.2.3 Internal Oscillator Frequency Adjustment The HFINTOSC and LFINTOSC internal oscillators are both factory-calibrated. The HFINTOSC oscillator can be adjusted in software by writing to the OSCTUNE register (Register 7-3). OSCTUNE does not affect the LFINTOSC frequency. The default value of the OSCTUNE register is 00h. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the HFINTOSC oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. 7.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is a factory calibrated 31 kHz internal clock source. The LFINTOSC is the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC can also be used as the system clock, or as a clock or input source to certain peripherals. The LFINTOSC is selected as the clock source through one of the following methods: • Programming the RSTOSC[2:0] bits of Configuration Word 1 to enable LFINTOSC. • Write to the NOSC[2:0] bits of the OSCCON1 register. 7.2.2.5 Oscillator Status and Manual Enable The ‘ready’ status of each oscillator is displayed in the OSCSTAT1 register (Register 7-4). The oscillators can also be manually enabled through the OSCEN register (Register 7-5). Manual enables make it possible to verify the operation of the EXTOSC or SOSC crystal oscillators. This can be achieved by enabling the selected oscillator, then watching the corresponding ‘ready’ state of the oscillator in the OSCSTAT1 register.  2015-2019 Microchip Technology Inc. DS40001799F-page 72 PIC16(L)F18313/18323 7.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits of the OSCCON1 register. The following clock sources can be selected: • • • • • • External Oscillator (EXTOSC) High-Frequency Internal Oscillator (HFINTOSC) Low-Frequency Internal Oscillator (LFINTOSC) Secondary Oscillator (SOSC) EXTOSC with 4x PLL HFINTOSC with 2x PLL 7.3.1 NEW OSCILLATOR SOURCE (NOSC) AND NEW DIVIDER SELECTION REQUEST (NDIV) BITS The New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits of the OSCCON1 register select the system clock source and frequencies that are used for the CPU and peripherals. When the new values of NOSC[2:0] and NDIV[3:0] are written to OSCCON1, the current oscillator selection will continue to operate as the system clock while waiting for the new source to indicate that it is stable and ready. In some cases, the newly requested source may already be in use, and is ready immediately. In the case of a divider-only change, the new and old sources are the same and are ready immediately. The device may enter Sleep while waiting for the switch as described in Section 7.3.3 “Clock Switch and Sleep”. When the new oscillator is ready, the New Oscillator is Ready (NOSCR) bit of OSCCON3 and the Clock Switch Interrupt Flag (CSWIF) bit of PIR3 become set (CSWIF = 1). If Clock Switch Interrupts are enabled (CSWIE = 1), an interrupt will be generated at that time. The Oscillator Ready (ORDY) bit of OSCCON3 can also be polled to determine when the oscillator is ready in lieu of an interrupt. If the Clock Switch Hold (CSWHOLD) bit of OSCCON3 is clear, the oscillator switch will occur when the New Oscillator Ready bit (NOSCR) is set and the interrupt (if enabled) will be serviced at the new oscillator setting. If CSWHOLD is set, the oscillator switch is suspended, while execution continues using the current (old) clock source. When the NOSCR bit is set, software should: • set CSWHOLD = 0 so the switch can complete, or • copy COSC into NOSC[2:0] to abandon the switch.  2015-2019 Microchip Technology Inc. If Doze is in effect, the switch occurs on the next clock cycle, whether or not the CPU is operating during that cycle. Changing the clock post-divider without changing the clock source (i.e., changing FOSC from 1 MHz to 2 MHz) is handled in the same manner as a clock source change, as described previously. The clock source will already be active, so the switch is relatively quick. CSWHOLD must be clear (CSWHOLD = 0) for the switch to complete. The current COSC and CDIV are indicated in the OSCCON2 register up to the moment when the switch actually occurs, at which time OSCCON2 is updated and ORDY is set. NOSCR is cleared by hardware to indicate that the switch is complete. 7.3.2 PLL INPUT SWITCH Switching between the PLL and any non-PLL source is managed as described above. The input to the PLL is established when NOSC[2:0] selects the PLL, and maintained by the COSC setting. When NOSC[2:0] and COSC select the PLL with different input sources, the system continues to run using the COSC setting, and the new source is enabled per NOSC[2:0]. When the new oscillator is ready (and CSWHOLD = 0), system operation is suspended while the PLL input is switched and the PLL acquires lock. 7.3.3 CLOCK SWITCH AND SLEEP If OSCCON1 is written with a new value and the device is put to Sleep before the switch completes, the switch will not take place and the device will enter Sleep mode. When the device wakes from Sleep and the CSWHOLD bit is clear, the device will wake with the ‘new’ clock active, and the Clock Switch Interrupt Flag bit (CSWIF) will be set. When the device wakes from Sleep and the CSWHOLD bit is set, the device will wake with the ‘old’ clock active and the new clock will be requested again. DS40001799F-page 73 PIC16(L)F18313/18323 FIGURE 7-6: CLOCK SWITCH (CSWHOLD = 0) OSCCON1 WRITTEN OSC #2 OSC #1 ORDY Note 2 NOSCR Note 1 CSWIF CSWHOLD USER CLEAR Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed. 2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch. FIGURE 7-7: CLOCK SWITCH (CSWHOLD = 1) OSCCON1 WRITTEN OSC #1 OSC #2 ORDY NOSCR CSWIF CSWHOLD Note 1 USER CLEAR Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.  2015-2019 Microchip Technology Inc. DS40001799F-page 74 PIC16(L)F18313/18323 FIGURE 7-8: CLOCK SWITCH ABANDONED OSCCON1 WRITTEN OSCCON1 WRITTEN OSC #1 ORDY Note 2 NOSCR CSWIF Note 1 CSWHOLD Note 1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared. 2: ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.  2015-2019 Microchip Technology Inc. DS40001799F-page 75 PIC16(L)F18313/18323 7.4 Fail-Safe Clock Monitor 7.4.2 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, ECL, ECM, ECH, and Secondary Oscillator). FIGURE 7-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock S Q When the external clock fails, the FSCM switches the device clock to the HFINTOSC at 1 MHz clock frequency and sets the bit flag OSFIF of the PIR3 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE3 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation, by writing to the NOSC[2:0] and NDIV[3:0]bits of the OSCCON1 register. 7.4.3 LFINTOSC Oscillator ÷ 64 31 kHz (~32 s) 488 Hz (~2 ms) R Q Sample Clock 7.4.1 Clock Failure Detected FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 7-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.  2015-2019 Microchip Technology Inc. FAIL-SAFE OPERATION FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the NOSC[2:0] and NDIV[3:0] bits of the OSCCON1 register. When switching to the external oscillator or external oscillator with PLL, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON1. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again be set by hardware. DS40001799F-page 76 PIC16(L)F18313/18323 7.4.4 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC Clock modes so that the external clock signal can be stopped if required. Therefore, the device will always be executing code while the OST is operating when using one of the EC modes. FIGURE 7-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.  2015-2019 Microchip Technology Inc. DS40001799F-page 77 PIC16(L)F18313/18323 7.5 Register Definitions: Oscillator Control REGISTER 7-1: OSCCON1: OSCILLATOR CONTROL REGISTER 1 R/W-f/f(1) U-0 R/W-f/f(1) R/W-f/f(1) R/W-q/q(4) NOSC[2:0](2,3) — R/W-q/q(4) R/W-q/q(4) R/W-q/q(4) NDIV[3:0](2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting q = Reset value is determined by hardware bit 7 Unimplemented: Read as ‘0’ bit 6-4 NOSC[2:0]: New Oscillator Source Request bits The setting requests a source oscillator and PLL combination per Table 7-1. POR value = RSTOSC (Register 5.2). bit 3-0 NDIV[3:0]: New Divider Selection Request bits The setting determines the new postscaler division ratio per Table 7-2. Note 1: 2: 3: 4: The default value (f/f) is set equal to the RSTOSC Configuration bits. If NOSC is written with a reserved value (Table 7-1), the HFINTOSC will be automatically selected as the clock source. When CSWEN = 0, this register is read-only and cannot be changed from the POR value. When RSTOSC = 110 (HFINTOSC 1 MHz) the NDIV bits will default to '0010' upon Reset; for all other NOSC settings the NVID bits will default to '0000' upon Reset. REGISTER 7-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-q/q(1) U-0 — R-q/q(1) R-q/q(1) R-q/q(1) COSC[2:0] R-q/q(1) R-q/q(1) R-q/q(1) CDIV[3:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting q = Reset value is determined by hardware bit 7 Unimplemented: Read as ‘0’ bit 6-4 COSC[2:0]: Current Oscillator Source Select bits (read-only) Indicates the current source oscillator and PLL combination per Table 7-1. bit 3-0 CDIV[3:0]: Current Divider Select bits (read-only) Indicates the current postscaler division ratio per Table 7-2. Note 1: The Reset value (q/q) will match the NOSC[2:0]/NDIV[3:0] bits.  2015-2019 Microchip Technology Inc. DS40001799F-page 78 PIC16(L)F18313/18323 TABLE 7-1: NOSC/COSC BIT SETTINGS TABLE 7-2: NDIV/CDIV BIT SETTINGS NOSC[2:0] COSC[2:0] Clock Source NDIV[3:0] CDIV[3:0] Clock Divider 111 EXTOSC(1) 1111–1010 Reserved 110 HFINTOSC (1 MHz) 1001 512 101 Reserved 1000 256 100 LFINTOSC 0111 128 011 SOSC 0110 64 010 Reserved 0101 32 001 EXTOSC with 4xPLL(1) 0100 16 000 HFINTOSC with 2x PLL (32 MHz) 0011 8 0010 4 0001 2 0000 1 Note 1: EXTOSC configured by the FEXTOSC bits of Configuration Word 1 (Register 5-1). REGISTER 7-3: OSCCON3: OSCILLATOR CONTROL REGISTER 3 R/W/HC-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 U-0 U-0 U-0 CSWHOLD SOSCPWR SOSCBE ORDY NOSCR — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Reset value is determined by hardware f = determined by fuse setting HC = Hardware clear bit 7 CSWHOLD: Clock Switch Hold bit 1 = Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready 0 = Clock switch may proceed when the oscillator selected by NOSC is ready; if this bit is set at the time that NOSCR becomes ‘1’, the switch and interrupt will occur. bit 6 SOSCPWR: Secondary Oscillator Power Mode Select bit If SOSCBE = 0 1 = Secondary oscillator operating in High-Power mode 0 = Secondary oscillator operating in Low-Power mode If SOSCBE = 1 x = Bit is ignored bit 5 SOSCBE: Secondary Oscillator Bypass Enable bit 1 = Secondary oscillator SOSCI is configured as an external clock input (ST-buffer); SOSCO is not used. 0 = Secondary oscillator is configured as a crystal oscillator using SOSCO and SOSCI pins. bit 4 ORDY: Oscillator Ready bit (read-only) 1 = OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC 0 = A clock switch is in progress bit 3 NOSCR: New Oscillator is Ready bit (read-only) 1 = A clock switch is in progress and the oscillator selected by NOSC indicates a Ready condition 0 = A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready bit 2-0 Unimplemented: Read as ‘0’.  2015-2019 Microchip Technology Inc. DS40001799F-page 79 PIC16(L)F18313/18323 REGISTER 7-4: OSCSTAT1: OSCILLATOR STATUS REGISTER 1 R-q/q R-q/q U-0 R-q/q R-q/q R-q/q U-0 R-q/q EXTOR HFOR — LFOR SOR ADOR — PLLR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Reset value is determined by hardware bit 7 EXTOR: EXTOSC (external) Oscillator Ready 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used. bit 6 HFOR: HFINTOSC Oscillator Ready 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used. bit 5 Unimplemented: Read as ‘0’ bit 4 LFOR: LFINTOSC Oscillator Ready 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used. bit 3 SOR: Secondary Oscillator Ready 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used. bit 2 ADOR: ADCRC Oscillator Ready 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used bit 1 Unimplemented: Read as ‘0’ bit 0 PLLR: PLL is ready 1 = The PLL is ready to be used 0 = The PLL is not enabled, the required input source is not ready, or the PLL is not ready.  2015-2019 Microchip Technology Inc. DS40001799F-page 80 PIC16(L)F18313/18323 REGISTER 7-5: OSCEN: OSCILLATOR MANUAL ENABLE REGISTER R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 EXTOEN HFOEN — LFOEN SOSCEN ADOEN — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EXTOEN: External Oscillator Manual Request Enable bit 1 = EXTOSC is explicitly enabled, operating as specified by FEXTOSC 0 = EXTOSC could be enabled by another module bit 6 HFOEN: HFINTOSC Oscillator Manual Request Enable bit 1 = HFINTOSC is explicitly enabled, operating as specified by OSCFRQ (Register 7-6) 0 = HFINTOSC could be enabled by another module bit 5 Unimplemented: Read as ‘0’ bit 4 LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit 1 = LFINTOSC is explicitly enabled 0 = LFINTOSC could be enabled by another module bit 3 SOSCEN: Secondary Oscillator Manual Request Enable bit 1 = Secondary Oscillator is explicitly enabled 0 = Secondary Oscillator could be enabled by another module bit 2 ADOEN: ADOSC (600 kHz) Oscillator Manual Request Enable bit 1 = ADOSC is explicitly enabled 0 = ADOSC could be enabled by another module bit 1 Unimplemented: Read as ‘0’ bit 0 Unimplemented: Read as ‘0’  2015-2019 Microchip Technology Inc. DS40001799F-page 81 PIC16(L)F18313/18323 REGISTER 7-6: OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 HFFRQ[3:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’. bit 3-0 HFFRQ[3:0]: HFINTOSC Frequency Selection bits HFFRQ[3:0] Nominal Freq. (MHz) (NOSC = 110) 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 1 2 Reserved 4 8 12 16 32 32  2015-2019 Microchip Technology Inc. 2xPLL Freq. (MHz) (NOSC = 000) Reserved 16 24 32 Reserved DS40001799F-page 82 PIC16(L)F18313/18323 REGISTER 7-7: OSCTUNE: HFINTOSC TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 HFTUN[5:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting q = Reset value is determined by hardware bit 7-6 Unimplemented: Read as ‘0’. bit 5-0 HFTUN[5:0]: HFINTOSC Frequency Tuning bits 01 1111 = Maximum frequency 01 1110 • • • 00 0001 00 0000 = Center frequency. Oscillator module is running at the calibrated frequency (default value). 11 1111 • • • 10 0000 = Minimum frequency.  2015-2019 Microchip Technology Inc. DS40001799F-page 83 PIC16(L)F18313/18323 TABLE 7-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 OSCCON1 — NOSC[2:0] NDIV[3:0] 78 OSCCON2 — COSC[2:0] CDIV[3:0] 78 OSCCON3 Bit 6 Bit 5 Bit 4 CWSHOLD SOSCPWR SOSCBE OSCSTAT1 EXTOR HFOR — EXTOEN HFOEN — OSCFRQ — — — OSCTUNE — — OSCEN Bit 3 ORDY NOSCR LFOR SOR Bit 2 LFOEN SOSCEN Bit 1 Bit 0 Register on Page Name — — — 79 ADOR — PLLR 80 ADOEN — — 81 HFFRQ[3:0] — 82 HFTUN[5:0] 83 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 7-4: Name CONFIG1 Legend: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bits Bit -/7 13:8 — 7:0 — Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 — FCMEN — CSWEN — — CLKOUTEN RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0 Register on Page 52 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.  2015-2019 Microchip Technology Inc. DS40001799F-page 84 PIC16(L)F18313/18323 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 8-1. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1 (TMR1IE) PIE1 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn PIEn  2015-2019 Microchip Technology Inc. GIE DS40001799F-page 85 PIC16(L)F18313/18323 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) (PIEx bits) for the specific interrupt event(s) • PEIE bit of the INTCON register 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The interrupt is sampled during Q1 of the instruction cycle. The actual interrupt latency then depends on the instruction that is executing at the time the interrupt is detected. See Figure 8-2 and Figure 8-3 for more details. The PIR1, PIR2, PIR3 and PIR4 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section 8.5 “Automatic Context Saving”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2015-2019 Microchip Technology Inc. DS40001799F-page 86 PIC16(L)F18313/18323 FIGURE 8-2: INTERRUPT LATENCY Rev. 10-000269E 8/31/2016 OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT INT pin Valid Interrupt window(1) Fetch PC - 1 Execute PC - 2 1 Cycle Instruction at PC PC = 0x0004 PC + 1 PC PC - 1 123 PC Indeterminate Latency(2) 123 PC = 0x0005 PC = 0x0006 PC = 0x0004 PC = 0x0005 Latency Note 1: An interrupt may occur at any time during the interrupt window. 2: Since an interrupt may occur any time during the interrupt window, the actual latency can vary. FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF (5) Interrupt Latency (2) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 35.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2015-2019 Microchip Technology Inc. DS40001799F-page 87 PIC16(L)F18313/18323 8.3 Interrupts During Sleep All interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 9.0 “Power-Saving Operation Modes” for more details. 8.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the PIE0 register. The INTEDG bit of the INTCON register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the PIR0 register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • • • • • W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.  2015-2019 Microchip Technology Inc. DS40001799F-page 88 PIC16(L)F18313/18323 8.6 Register Definitions: Interrupt Control REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W/HS/HC-0/0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 R-1/1 GIE PEIE — — — — — INTEDG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = hardware set HC = Hardware clear bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5-1 Unimplemented: Read as ‘0’. bit 0 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 89 PIC16(L)F18313/18323 REGISTER 8-2: PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0 U-0 U-0 R/W/HS-0/0 R/W-0/0 U-0 U-0 U-0 R/W/HS-0/0 — — TMR0IE IOCIE — — — INTE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set bit 7-6 Unimplemented: Read as ‘0’. bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 IOCIE: Interrupt-on-Change Interrupt Enable bit 1 = Enables the IOC change interrupt 0 = Disables the IOC change interrupt bit 3-1 Unimplemented: Read as ‘0’. bit 0 INTE: INT External Interrupt Flag bit(1) 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt Note 1: Note: The external interrupt INT pin is selected by INTPPS (Register 13-1). Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 90 PIC16(L)F18313/18323 REGISTER 8-3: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = MSSP bus collision interrupt enabled 0 = MSSP bus collision interrupt not enabled bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 91 PIC16(L)F18313/18323 REGISTER 8-4: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 — C2IE(1) C1IE NVMIE — — — NCO1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’. bit 6 C2IE: Comparator C2 Interrupt Enable bit(1) 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 NVMIE: NVM Interrupt Enable Bit 1 = NVM task complete interrupt enabled 0 = NVM interrupt not enabled bit 3-1 Unimplemented: Read as ‘0’. bit 0 NCO1IE: NCO Interrupt Enable bit 1 = NCO rollover interrupt enabled 0 = NCO rollover interrupt not enabled Note 1: Note: Comparator C2 not available on PIC16(L)F18313 devices. Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 92 PIC16(L)F18313/18323 REGISTER 8-5: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 OSFIE CSWIE — — — — CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit. 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 CSWIE: Clock Switch Complete Interrupt Enable bit 1 = The clock switch module interrupt is enabled 0 = The clock switch module interrupt is not enabled bit 5-2 Unimplemented: Read as ‘0’. bit 1 CLC2IE: CLC2 Interrupt Enable bit 1 = CLC2 interrupt enabled 0 = CLC2 interrupt disabled bit 0 CLC1IE: CLC1 Interrupt Enable bit 1 = CLC1 interrupt enabled 0 = CLC1 interrupt disabled Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 93 PIC16(L)F18313/18323 REGISTER 8-6: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — CWG1IE — — — — CCP2IE CCP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set bit 7 Unimplemented: Read as ‘0’. bit 6 CWG1IE: CWG 1 Interrupt Enable bit 1 = CWG1 interrupt enabled 0 = CWG1 interrupt not enabled bit 5-2 Unimplemented: Read as ‘0’. bit 1 CCP2IE: CCP2 Interrupt Enable bit 1 = CCP2 interrupt is enabled 0 = CCP2 interrupt is not enabled bit 0 CCP1IE: CCP1 Interrupt Enable bit 1 = CCP1 interrupt is enabled 0 = CCP1 interrupt is not enabled Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 94 PIC16(L)F18313/18323 REGISTER 8-7: U-0 PIR0: PERIPHERAL INTERRUPT REQUEST REGISTER 0 U-0 — — R/W/HS-0/0 TMR0IF R-0 IOCIF (1) U-0 U-0 U-0 R/W/HS-0/0 — — — INTF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS= Hardware Set bit 7-6 Unimplemented: Read as ‘0’ bit 5 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 4 IOCIF: Interrupt-on-Change Interrupt Flag bit (read-only) 1 = An enabled edge was detected by the IOC module. One of the IOCF bits is set. 0 = No enabled edge is was detected by the IOC module. None of the IOCF bits is set. Pins are individually masked via IOCxP and IOCxN. bit 3-1 Unimplemented: Read as ‘0’ bit 0 INTF: INT External Interrupt Flag bit(1) 1 = The INT external interrupt occurred (must be cleared in software) 0 = The INT external interrupt did not occur Note 1: Note: The IOCIF bit is the logical OR of all the IOCAF-IOCCF flags. Therefore, to clear the IOCIF flag, application firmware must clear all of the IOCAF-IOCCF register bits. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 95 PIC16(L)F18313/18323 REGISTER 8-8: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W/HS-0/0 R/W/HS-0/0 R-0 R-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = The Timer1 gate has gone inactive (the gate is closed). 0 = The Timer1 gate has not gone inactive. bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit 1 = The A/D conversion completed 0 = The A/D conversion is not completed bit 5 RCIF: EUSART Receive Interrupt Flag bit (read-only) 1 = The EUSART1 receive buffer is not empty 0 = The EUSART1 receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit (read-only) 1 = The EUSART1 transmit buffer is empty 0 = The EUSART1 transmit buffer is not empty bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software) 0 = Waiting for the Transmission/Reception/Bus Condition in progress bit 2 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = A bus collision was detected (must be cleared in software) 0 = No bus collision was detected bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = TMR1 overflow occurred (must be cleared in software) 0 = No TMR1 overflow occurred Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 96 PIC16(L)F18313/18323 REGISTER 8-9: U-0 PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W/HS-0/0 — (1) C2IF R/W/HS-0/0 R/W/HS-0/0 C1IF NVMIF U-0 U-0 U-0 R/W/HS-0/0 — — — NCO1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set bit 7 Unimplemented: Read as ‘0’ bit 6 C2IF: Comparator C2 Interrupt Flag bit(1) 1 = Comparator 2 interrupt asserted 0 = Comparator 2 interrupt not asserted bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator 1 interrupt asserted 0 = Comparator 1 interrupt not asserted bit 4 NVMIF: NVM Interrupt Flag bit 1 = The NVM has completed a programming task 0 = NVM interrupt not asserted bit 3-1 Unimplemented: Read as ‘0’ bit 0 NCO1IF: NCO Interrupt Flag bit 1 = The NCO has rolled over. 0 = No NCO interrupt is asserted. Note 1: Note: Comparator C2 not available on PIC16(L)F18313 devices. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 97 PIC16(L)F18313/18323 REGISTER 8-10: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 OSFIF CSWIF — — — — CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set bit 7 OSFIF: Oscillator Fail-Safe Interrupt Flag bit 1 = Fail-Safe Clock Monitor module has detected a failed oscillator 0 = External oscillator operating normally. bit 6 CSWIF: Clock Switch Complete Interrupt Flag bit 1 = The clock switch module has completed the clock switch; new oscillator is ready 0 = The clock switch module has not completed clock switch. bit 5-2 Unimplemented: Read as ‘0’ bit 1 CLC2IF: CLC2 Interrupt Flag bit 1 = The CLC2OUT interrupt condition has been met 0 = No CLC2 interrupt bit 0 CLC1IF: CLC1 Interrupt Flag bit 1 = The CLC1OUT interrupt condition has been met 0 = No CLC1 interrupt Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 98 PIC16(L)F18313/18323 REGISTER 8-11: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 U-0 R/W/HS-0/0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 — CWG1IF — — — — CCP2IF CCP1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware set bit 7 Unimplemented: Read as ‘0’ bit 6 CWG1IF: CWG1 Interrupt Flag bit 1 = CWG1 has gone into shutdown 0 = CWG1 is operating normally, or interrupt cleared bit 5-2 Unimplemented: Read as ‘0’ bit 1 CCP2IF: CCP2 Interrupt Flag bit Value 1 0 bit 0 CCPM Mode Capture Capture occurred Compare match occurred (must be cleared in software) (must be cleared in software) Compare match did not Capture did not occur occur PWM Output trailing edge occurred (must be cleared in software) Output trailing edge did not occur CCP1IF: CCP1 Interrupt Flag bit CCPM Mode Value 1 0 Note: Compare Capture Compare Capture occurred Compare match occurred (must be cleared in software) (must be cleared in software) Compare match did not Capture did not occur occur PWM Output trailing edge occurred (must be cleared in software) Output trailing edge did not occur Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2015-2019 Microchip Technology Inc. DS40001799F-page 99 PIC16(L)F18313/18323 TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE — — — — — INTEDG 89 PIE0 — — TMR0IE IOCIE — — — INTE 90 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 91 C1IE NVMIE — — — NCO1IE 92 (1) PIE2 — C2IE PIE3 OSFIE CSWIE — — — — CLC2IE CLC1IE 93 PIE4 — CWG1IE — — — — CCP2IE CCP1IE 94 PIR0 — — TMR0IF IOCIF — — — INTF 95 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96 PIR2 — C2IF(1) C1IF NVMIF — — — NCO1IF 97 PIR3 OSFIF CSWIF — — — — CLC2IF CLC1IF 98 PIR4 — CWG1IF — — — — CCP2IF CCP1IF 99 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. Note 1: Comparator C2 not available on PIC16(L)F18313 devices.  2015-2019 Microchip Technology Inc. DS40001799F-page 100 PIC16(L)F18313/18323 9.0 POWER-SAVING OPERATION MODES 9.1.1 The Doze operation is illustrated in Figure 9-1. For this example: The purpose of the Power-Down modes is to reduce power consumption. There are three Power-Down modes: Doze mode, Idle mode, and Sleep mode. 9.1 • Doze enable (DOZEN) bit set (DOZEN = 1) • DOZE[2:0] = 001 (1:4) ratio • Recover-on-Interrupt (ROI) bit set (ROI = 1) Doze Mode As with normal operation, the program memory fetches for the next instruction cycle. The instruction clocks to the peripherals continue throughout. Doze mode allows for power savings by reducing CPU operation and program memory access, without affecting peripheral operation. Doze mode differs from Sleep mode because the system oscillators continue to operate, while only the CPU and program memory are affected. The reduced execution saves power by eliminating unnecessary operations within the CPU and memory. 9.1.2 INTERRUPTS DURING DOZE If an interrupt occurs and the Recover-on-Interrupt (ROI) bit is clear (ROI = 0) at the time of the interrupt, the Interrupt Service Routine (ISR) continues to execute at the rate selected by DOZE[2:0]. Interrupt latency is extended by the DOZE[2:0] ratio. When the Doze Enable (DOZEN) bit is set (DOZEN = 1), the CPU executes only one instruction cycle out of every N cycles as defined by the DOZE[2:0] bits of the CPUDOZE register. For example, if DOZE[2:0] = 100, the instruction cycle ratio is 1:32. The CPU and memory execute for one instruction cycle and then lay idle for 31 instruction cycles. During the unused cycles, the peripherals continue to operate at the system clock speed. FIGURE 9-1: DOZE OPERATION If an interrupt occurs and the ROI bit is set (ROI = 1) at the time of the interrupt, the DOZEN bit is cleared and the CPU executes at full speed. The prefetched instruction is executed and then the interrupt vector sequence is executed. In Figure 9-1, the interrupt occurs during the 2nd instruction cycle of the Doze period, and immediately brings the CPU out of Doze. If the Doze-on-Exit (DOE) bit is set (DOE = 1) when the RETFIE operation is executed, DOZEN is set, and the CPU executes at the reduced rate based on the DOZE[2:0] ratio. DOZE MODE OPERATION EXAMPLE System Clock 1 1 2 /ŶƐƚƌƵĐƚŝŽŶ WĞƌŝŽĚƐ 1 2 3 1 2 3 4 1 2 3 4 2 3 4 1 2 3 4 1 1 2 3 4 2 3 4 1 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2 3 4 4 1 2 3 4 1 2 3 4 PFM Op’s Fetch Fetch Push 0004h Fetch Fetch CPU Op’s Exec Exec Exec(1,2) NOP Exec Exec CPU Clock 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Exec Interrupt Here (ROI = 1)  2015-2019 Microchip Technology Inc. DS40001799F-page 101 PIC16(L)F18313/18323 9.2 Idle Mode When the Idle Enable (IDLEN) bit is clear (IDLEN = 0), the SLEEP instruction will put the device into full Sleep mode (see Section 9.3 “Sleep Mode”). When IDLEN is set (IDLEN = 1), the SLEEP instruction will put the device into Idle mode. In Idle mode, the CPU and memory operations are halted, but the peripheral clocks continue to run. This mode is similar to Doze mode, except that in Idle, both the CPU and program memory are shut off. Note: Note: 9.2.1 Peripherals using FOSC will continue running while in Idle (but not in Sleep). Peripherals using HFINTOSC, LFINTOSC, or SOSC will continue operation in both Idle and Sleep. If CLKOUT is enabled (CLKOUT = 0, Configuration Word 1), the output will continue operating while in Idle. 9.3 Sleep mode is entered by executing the SLEEP instruction, while the Idle Enable (IDLEN) bit of the CPUDOZE register is clear (IDLEN = 0). If the SLEEP instruction is executed while the IDLEN bit is set (IDLEN = 1), the CPU will enter the Idle mode (Section 9.3.3 “Low-Power Sleep Mode”). Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. IDLE AND INTERRUPTS Idle mode ends when an interrupt occurs (even if GIE = 0), but IDLEN is not changed. The device can re-enter Idle by executing the SLEEP instruction. If Recover-on-Interrupt is enabled (ROI = 1), the interrupt that brings the device out of Idle also restores full-speed CPU execution when Doze is also enabled. 9.2.2 IDLE AND WDT When in Idle, the WDT Reset is blocked and will instead wake the device. The WDT wake-up is not an interrupt, therefore ROI does not apply. Note: The WDT can bring the device out of Idle, in the same way it brings the device out of Sleep. The DOZEN bit is not affected. Sleep Mode 7. Resets other than WDT are not affected by Sleep mode; WDT will be cleared but keeps running if enabled for operation during Sleep. The PD bit of the STATUS register is cleared. The TO bit of the STATUS register is set. The CPU and System clocks are disabled. 31 kHz LFINTOSC, HFINTOSC and SOSC will remain enabled if any peripheral has requested them as a clock source or if the HFOEN, LFOEN, or SOSCEN bits of the OSCEN register are set. ADC is unaffected if the dedicated ADCRC oscillator is selected. When the ADC clock source is something other than ADCRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. I/O ports maintain the status they had before Sleep was executed (driving high, low, or high-impedance) only if no peripheral connected to the I/O port is active. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: - I/O pins should not be floating - External circuitry sinking current from I/O pins - Internal circuitry sourcing current from I/O pins - Current draw from pins with internal weak pull-ups - Modules using any oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 24.0 “5-bit Digital-to-Analog Converter (DAC1) Module” and Section 16.0 “Fixed Voltage Reference (FVR)” for more information on these modules.  2015-2019 Microchip Technology Inc. DS40001799F-page 102 PIC16(L)F18313/18323 9.3.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. 4. 5. External Reset input on MCLR pin, if enabled BOR Reset, if enabled. POR Reset. Watchdog Timer, if enabled Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information). The first three events will cause a device Reset. The last two events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 6.11 “Determining the Cause of a Reset”. The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up. 9.3.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.  2015-2019 Microchip Technology Inc. DS40001799F-page 103 PIC16(L)F18313/18323 FIGURE 9-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt Latency (4) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 9.3.3 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. LOW-POWER SLEEP MODE The PIC16F18313/18323 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F18313/18323 allows the user to optimize the operating current in Sleep, depending on the application requirements. Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. Depending on the configuration of this bit, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 9.3.3.1 PC + 2 Sleep Current vs. Wake-up Time In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking-up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.  2015-2019 Microchip Technology Inc. 9.3.3.2 Peripheral Usage in Sleep Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The Low-Power Sleep mode is intended for use with these peripherals: • • • • Brown-out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer 1 (with external clock source) It is the responsibility of the end user to determine what is acceptable for their application when setting the VREGPM settings in order to ensure operation in Sleep. Note: The PIC16LF18313/18323 does not have a configurable Low-Power Sleep mode. PIC16LF18313/18323 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum VDD and I/O voltage than the PIC16F18313/18323. See Section 35.0 “Electrical Specifications” for more information. DS40001799F-page 104 PIC16(L)F18313/18323 9.4 Register Definitions: Voltage Regulator Control VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 9-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2); Draws lowest current in Sleep, slower wake-up 0 = Normal-Power Sleep mode enabled in Sleep(2); Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: 2: PIC16F18313/18323 only. See Section 35.0 “Electrical Specifications”. REGISTER 9-2: R/W-0/u CPUDOZE: DOZE AND IDLE REGISTER R/W/HC/HS-0/0 IDLEN DOZEN (1,2) R/W-0/0 R/W-0/0 U-0 ROI DOE — R/W-0/0 R/W-0/0 R/W-0/0 DOZE[2:0] bit 7 bit 0 HS = Hardware Set Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Hardware clear bit 7 IDLEN: Idle Enable bit 1 = A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s) 0 = A SLEEP instruction places the device into Full-Sleep mode bit 6 DOZEN: Doze Enable bit(1,2) 1 = The CPU executes instruction cycles according to DOZE setting. 0 = The CPU executes all instruction cycles (fastest, highest power operation). bit 5 ROI: Recover-on-Interrupt bit 1 = Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed operation. 0 = Interrupt entry does not change DOZEN bit 4 DOE: Doze-on-Exit bit 1 = Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation. 0 = RETFIE does not change DOZEN bit 3 Unimplemented: Read as ‘0’. bit 2-0 DOZE[2:0]: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles 111 = 1:256 110 = 1:128 101 = 1:64 100 = 1:32 011 = 1:16 010 = 1:8 001 = 1:4 000 = 1:2 Note 1: 2: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit. Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.  2015-2019 Microchip Technology Inc. DS40001799F-page 105 PIC16(L)F18313/18323 TABLE 9-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Bit 7 Bit 6 GIE PEIE — — — PIE0 — — TMR0IE IOCIE — INTCON Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 Register on Page — — INTEDG 89 — — INTE 90 Bit 2 PIE1 TMR1GIE ADIE RCIE TXIE TMR2IE TMR1IE 91 PIE2 — C2IE(1) C1IE NVMIE — — — NCO1IE 92 PIE3 OSFIE CSWIE — — — — CLC2IE CLC1IE 93 PIE4 — CWG1IE — — — — CCP2IE CCP1IE 94 PIR0 — — TMR0IF IOCIF — — — INTF 95 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 96 — C2IF(1) C1IF NVMIF — — — NCO1IF 97 — — — CLC2IF CLC1IF 98 — — — CCP2IF CCP1IF 99 PIR2 SSP1IE BCL1IE PIR3 OSFIF CSWIF — PIR4 — CWG1IF — IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 156 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 156 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 157 (1) — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 158 (1) IOCCN — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 158 IOCCF(1) — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 159 — — — TO PD Z DC C 24 VREGCON — — — — — — VREGPM — 105 CPUDOZE IDLEN DOZEN ROI DOE WDTCON — — IOCCP STATUS (2) Legend: Note 1: 2: — WDTPS[4:0] DOZE[2:0] 105 SWDTEN 109 — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. PIC16(L)F18323 only. PIC16F18313/18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 106 PIC16(L)F18313/18323 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple WDT clearing conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE[1:0] = 01 SWDTEN WDTE[1:0] = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE[1:0] = 10 Sleep  2015-2019 Microchip Technology Inc. WDTPS[4:0] DS40001799F-page 107 PIC16(L)F18313/18323 10.1 Independent Clock Source 10.3 Time-out Period The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Table 35-8 for the LFINTOSC specification. The WDTPS[4:0] bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds. 10.2 10.4 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE[1:0] bits in Configuration Words. See Table 10-1. 10.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. WDT protection is active during Sleep. 10.2.2 WDT IS OFF IN SLEEP Clearing the WDT The WDT is cleared when any of the following conditions occur: • • • • • • • Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep due to an interrupt Oscillator fail WDT is disabled Oscillator Start-up Timer (OST) is running When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep. See Table 10-2 for more information. WDT protection is not active during Sleep. 10.5 10.2.3 WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged Table 10-1 for more details. 10.2.4 by Sleep. See WDT IS ALWAYS OFF When the WDTE bits are set to '00', the WDT is disabled, and the SWDTEN bit of the WDTCON is ignored. TABLE 10-1: WDT OPERATING MODES WDTE[1:0] SWDTEN 11 X X 10 X Active Active Sleep Disabled 0 X 00 X X When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 7.0 “Oscillator Module” for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See STATUS Register (Register 4-1) for more information. WDT Mode Awake 1 01 TABLE 10-2: Device Mode Operation During Sleep Active Disabled Disabled WDT CLEARING CONDITIONS Conditions WDTE = 00 WDTE = 01 and SWDTEN = 0 Exit Sleep due to a Reset + System Clock = XT, HS, LP Exit Sleep due to a Reset + System Clock = HFINTOSC, LFINTOSC, EC, SOSC WDT Cleared and Disabled Cleared until the end of OST Exit Sleep due to an interrupt Enter Sleep CLRWDT Command Cleared Oscillator Failure (see Section 7.4 “Fail-Safe Clock Monitor”) System Reset Any clock switch or divider change (see Section 7.3 “Clock Switching”)  2015-2019 Microchip Technology Inc. Unaffected DS40001799F-page 108 PIC16(L)F18313/18323 10.6 Register Definitions: Watchdog Control REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 WDTPS[4:0](1) bit 7 R/W-0/0 SWDTEN bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS[4:0]: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 Note 1: = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE[1:0] = 1x: This bit is ignored. If WDTE[1:0] = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE[1:0] = 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC.  2015-2019 Microchip Technology Inc. DS40001799F-page 109 PIC16(L)F18313/18323 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page STATUS — — — TO PD Z DC C 24 WDTCON — — SWDTEN 109 Name WDTPS[4:0] Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 10-4: Name CONFIG2 SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — DEBUG STVREN PPS1WAY — BORV — — WDTE1 7:0 BOREN1 BOREN0 LPBOREN WDTE0 PWRTE MCLRE Register on Page 53 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.  2015-2019 Microchip Technology Inc. DS40001799F-page 110 PIC16(L)F18313/18323 11.0 NONVOLATILE MEMORY (NVM) CONTROL TABLE 11-1: NVM is separated into two types: Program Flash Memory and Data EEPROM. NVM is accessible by using both the FSR and INDF registers, or through the NVMREG register interface. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. NVM can be protected in two ways; by either code protection or write protection. Code protection (CP and CPD bits in Configuration Word 4) disables access, reading and writing, to both the program Flash memory and EEPROM via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be Reset by a device programmer performing a Bulk Erase to the device, clearing all nonvolatile memory, Configuration bits, and user IDs. Write protection prohibits self-write and erase to a portion or all of the program Flash memory, as defined by the WRT[1:0] bits of Configuration Word 3. Write protection does not affect a device programmer’s ability to read, write, or erase the device. 11.1 Device PIC16(L)F18325 PIC16(L)F18345 FLASH MEMORY ORGANIZATION BY DEVICE Row Erase (words) Write Latches (words) 32 32 It is important to understand the program Flash memory structure for erase and programming operations. Program Flash memory is arranged in rows. A row consists of 32 14-bit program memory words. A row is the minimum size that can be erased by user software. All or a portion of a row can be programmed. Data to be written into the program memory row is written to 14-bit wide data write latches. These latches are not directly accessible to the user, but may be loaded via sequential writes to the NVMDATH:NVMDATL register pair. Note: Program Flash Memory Program Flash memory consists of 8192 14-bit words as user memory, with additional words for user ID information, Configuration Words, and interrupt vectors. Program Flash memory provides storage locations for: To modify only a portion of a previously programmed row, the contents of the entire row must be read and saved in either RAM or the row’s write latches prior to the erase. Then, the new data and retained data can be written into the write latches to reprogram the row of program Flash memory. Any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations • User program instructions • User defined data 11.1.1 Program Flash memory data can be read and/or written to through: The program Flash memory is readable and writable during normal operation over the full VDD range. • CPU instruction fetch (read-only) • FSR/INDF indirect access (read-only) (Section 11.3 “FSR and INDF Access”) • NVMREG access (Section 11.4 “NVMREG Access” • External device programmer Read operations return a single word of memory. When write and erase operations are done on a row basis, the row size is defined in Table 11-1. Program Flash memory will erase to a logic ‘1’ and program to a logic ‘0’.  2015-2019 Microchip Technology Inc. 11.1.1.1 PROGRAM MEMORY VOLTAGES Programming Externally The program memory cell and control logic support write and Bulk Erase operations down to the minimum device operating voltage. 11.1.1.2 Self-Programming The program memory cell and control logic will support write and row erase operations across the entire VDD range. Bulk Erase is not available when self-programming. DS40001799F-page 111 PIC16(L)F18313/18323 11.2 Data EEPROM Data EEPROM consists of 256 bytes of user data memory. The EEPROM provides storage locations for 8-bit user defined data. EEPROM can be read and/or written through: • FSR/INDF indirect access (Section 11.3 “FSR and INDF Access”) • NVMREG access (Section 11.4 “NVMREG Access”) • External device programmer Unlike program Flash memory, which must be written to by row, EEPROM can be written to byte by byte. 11.3 FSR and INDF Access The FSR and INDF registers allow indirect access to the program Flash memory or EEPROM. 11.3.1 FSR READ With the intended address loaded into an FSR register, a MOVIW instruction or read of INDF will read data from the Program Flash Memory or EEPROM. The CPU operation is suspended during the read, and resumes immediately after. Read operations return a single word of memory. When the MSB of the FSR (ex: FSRxH) is set to 0x70, the lower 8-bit address value (in FSRxL) determines the EEPROM location that may be read from (through the INDF register). In other words, the EEPROM address range 0x00-0xFF is mapped into the FSR address space between 0x7000-0x70FF. Writing to the EEPROM cannot be accomplished via the FSR/INDF interface. 11.3.2 FSR WRITE Writing/erasing the NVM through the FSR registers (ex. MOVWI instruction) is not supported in the PIC16(L)F18313/18323 devices.  2015-2019 Microchip Technology Inc. DS40001799F-page 112 PIC16(L)F18313/18323 11.4 NVMREG Access FIGURE 11-1: The NVMREG interface allows read/write access to all the locations accessible by FSRs, and also read/write access to the user ID locations and EEPROM, and read-only access to the device identification, revision, and Configuration data. Reading, writing, or erasing of NVM via the NVMREG interface is prevented when the device is code-protected. 11.4.1 Start Read Operation Select Memory: Program Flash Memory, EEPROM, Config. Words, User ID (NVMREGS) NVMREG READ OPERATION To read a NVM location using the NVMREG interface, the user must: 1. 2. 3. PROGRAM FLASH MEMORY READ FLOWCHART Clear the NVMREGS bit of the NVMCON1 register if the user intends to access program Flash memory locations, or set NVMREGS if the user intends to access user ID, Configuration, or EEPROM locations. Write the desired address into the NVMADRH:NVMADRL register pair (Table 11-2). Set the RD bit of the NVMCON1 register to initiate the read. Select Word Address (NVMADRH:NVMADRL) Initiate Read Operation (RD = 1) Data read now in NVMDATH:NVMDATL End Read Operation Once the read control bit is set, the CPU operation is suspended during the read, and resumes immediately after. The data is available in the very next cycle, in the NVMDATH:NVMDATL register pair; therefore, it can be read as two bytes in the following instructions. NVMDATH:NVMDATL register pair will hold this value until another read or until it is written to by the user. Upon completion, the RD bit is cleared by hardware. EXAMPLE 11-1: PROGRAM FLASH MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWF NVMADRL PROG_ADDR_LO NVMADRL PROG_ADDR_HI NVMADRH ; Select Bank for NVMCON registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF NVMCON1,NVMREGS NVMCON1,RD ; Do not select Configuration Space ; Initiate read MOVF MOVWF MOVF MOVWF NVMDATL,W PROG_DATA_LO NVMDATH,W PROG_DATA_HI ; ; ; ;  2015-2019 Microchip Technology Inc. Get LSB of word Store in user location Get MSB of word Store in user location DS40001799F-page 113 PIC16(L)F18313/18323 11.4.2 NVM UNLOCK SEQUENCE FIGURE 11-2: The unlock sequence is a mechanism that protects the NVM from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: Start Unlock Sequence • Program Flash Memory Row Erase • Load of Program Flash Memory write latches • Write of Program Flash Memory write latches to Program Flash Memory memory • Write of Program Flash Memory write latches to user IDs • Write to EEPROM Write 55h to NVMCON2 The unlock sequence consists of the following steps and must be completed in order: Write AAh to NVMCON2 • Write 55h to NVMCON2 • Write AAh to NMVCON2 • Set the WR bit of NVMCON1 Initiate Write or Erase Operation (WR = 1) Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume with the next instruction. Note: NVM UNLOCK SEQUENCE FLOWCHART NOP Instruction (not required for PIC16(L)F18313/18323 devices) The two NOP instructions after setting the WR bit, which were required in previous devices, are not required for PIC16(L)F18313/18323 devices. See Figure 11-2. NOP Instruction (not required for PIC16(L)F18313/18323 devices) Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. End Unlock Operation EXAMPLE 11-2: NVM UNLOCK SEQUENCE BANKSEL BSF MOVLW BCF NVMCON1 NVMCON1,WREN 55h INTCON,GIE ; Enable write/erase ; Load 55h ; Recommended so sequence is not interrupted MOVWF MOVLW MOVWF BSF NVMCON2 AAh NVMCON2 NVMCON1,WR ; ; ; ; BSF INTCON,GIE ; Re-enable interrupts Step Step Step Step 1: 2: 3: 4: Load 55h into NVMCON2 Load W with AAh Load AAh into NVMCON2 Set WR bit to begin write/erase Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown. 2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.  2015-2019 Microchip Technology Inc. DS40001799F-page 114 PIC16(L)F18313/18323 11.4.3 NVMREG WRITE TO EEPROM Writing to the EEPROM is accomplished by the following steps: 1. 2. 3. Set the NVMREGS and WREN bits of the NVMCON1 register. Write the desired address (address +7000h) into the NVMADRH:NVMADRL register pair (Table 11-2). Perform the unlock sequence as described in Section 11.4.2 “NVM Unlock Sequence”. A single EEPROM byte is written with NVMDATA. The operation includes an implicit erase cycle for that byte (it is not necessary to set the FREE bit), and requires many instruction cycles to finish. CPU execution continues in parallel and, when complete, WR is cleared by hardware, NVMIF is set, and an interrupt will occur if NVMIE is also set. Software must poll the WR bit to determine when writing is complete, or wait for the interrupt to occur. WREN will remain unchanged. Once the EEPROM write operation begins, clearing the WR bit will have no effect; the operation will run to completion. 11.4.4 NVMREG ERASE OF PROGRAM FLASH MEMORY Program Flash memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write to program Flash memory. To erase a program Flash memory row: 1. 2. 3. 4. Clear the NVMREGS bit of the NVMCON1 register to erase program Flash memory locations, or set the NVMREGS bit to erase user ID locations. Write the desired address into the NVMADRH:NVMADRL register pair (Table 11-2). Set the FREE and WREN bits of the NVMCON1 register. Perform the unlock sequence as described in Section 11.4.2 “NVM Unlock Sequence”. FIGURE 11-3: NVM ERASE FLOWCHART Start Erase Operation Select Memory: Program Flash Memory, Config. Words, User ID (NVMREGS) Select Word Address (NVMADRH:NVMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Disable Interrupts (GIE = 0) Unlock Sequence (Figure 11-2) CPU stalls while Erase operation completes (2 ms typical) Enable Interrupts (GIE = 1) Disable Write/Erase Operation (WREN = 0) End Erase Operation If the program Flash memory address is write-protected, the WR bit will be cleared and the erase operation will not take place. While erasing program Flash memory, CPU operation is suspended, and resumes when the operation is complete. Upon completion, the NVMIF is set, and an interrupt will occur if the NVMIE bit is also set. Write latch data is not affected by erase operations, and WREN will remain unchanged.  2015-2019 Microchip Technology Inc. DS40001799F-page 115 PIC16(L)F18313/18323 EXAMPLE 11-3: ERASING ONE ROW OF PROGRAM FLASH MEMORY ; This sample row erase routine assumes the following: ; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL ; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F) BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF BCF NVMADRL ADDRL,W NVMADRL ADDRH,W NVMADRH NVMCON1,NVMREGS NVMCON1,FREE NVMCON1,WREN INTCON,GIE ; Load lower 8 bits of erase address boundary ; ; ; ; ; Load upper 6 bits of erase address boundary Choose Program Flash Memory area Specify an erase operation Enable writes Disable interrupts during unlock sequence ; -------------------------------REQUIRED UNLOCK SEQUENCE:-----------------------------MOVLW MOVWF MOVLW MOVWF BSF 55h NVMCON2 AAh NVMCON2 NVMCON1,WR ; ; ; ; ; Load 55h to get ready for unlock sequence First step is to load 55h into NVMCON2 Second step is to load AAh into W Third step is to load AAh into NVMCON2 Final step is to set WR bit ; -------------------------------------------------------------------------------------BSF BCF TABLE 11-2: INTCON,GIE NVMCON1,WREN ; Re-enable interrupts, erase is complete ; Disable writes NVM ORGANIZATION AND ACCESS INFORMATION Master Values Memory Function Program Counter (PC), ICSP™ Address NVMREG Access Memory Type FSR Access NVMREGS NVMADR Allowed bit [14:0] Operations (NVMCON1) FSR Address Reset Vector 0000h 0 0000h 8000h User Memory 0001h 0 0001h 8001h 0 0004h 0003h INT Vector User Memory 0004h Program Flash Memory 0005h 0003h 0 17FFh User ID Reserved Program Flash Memory 1 — 0005h 8005h FFFFh 0003h READ — 0004h 1 0005h Device ID Program Flash Memory 1 0006h 1 0007h 1 0008h 1 0009h EEPROM 1 CONFIG2 CONFIG3 CONFIG4 User Memory  2015-2019 Microchip Technology Inc. READ-ONLY 0000h — No PC Address 8003h 8004h 17FFh Rev ID CONFIG1 READ WRITE FSR Programming Address No Access READ 000Ah F000h READ 7000h F0FFh WRITE 70FFh READ-ONLY DS40001799F-page 116 PIC16(L)F18313/18323 11.4.5 NVMREG WRITE TO PROGRAM FLASH MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address of the row to be programmed into NVMADRH:NVMADRL. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 11-4 (row writes to program memory with 32 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper ten bits of NVMADRH:NVMADRL, (NVMADRH[6:0]:NVMADRL[7:5]) with the lower five bits of NVMADRL, (NVMADRL[4:0]) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the NVMDATH:NVMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated.  2015-2019 Microchip Technology Inc. 1. 2. Set the WREN bit of the NVMCON1 register. Clear the NVMREGS bit of the NVMCON1 register. 3. Set the LWLO bit of the NVMCON1 register. When the LWLO bit of the NVMCON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the NVMADRH:NVMADRL register pair with the address of the location to be written. 5. Load the NVMDATH:NVMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 11.4.2 “NVM Unlock Sequence”). The write latch is now loaded. 7. Increment the NVMADRH:NVMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the NVMCON1 register. When the LWLO bit of the NVMCON1 register is ‘0’, the write sequence will initiate the write to Flash program memory. 10. Load the NVMDATH:NVMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 11.4.2 “NVM Unlock Sequence”). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 11-4. The initial address is loaded into the NVMADRH:NVMADRL register pair; the data is loaded using indirect addressing. DS40001799F-page 117  2015-2019 Microchip Technology Inc. FIGURE 11-4: 7 6 - r9 BLOCK WRITES TO PROGRAM FLASH MEMORY WITH 32 WRITE LATCHES 0 7 5 4 NVMADRH r8 r7 r6 r5 r4 0 7 NVMADRL r3 r2 r1 r0 c4 c3 - c2 c1 5 - 0 7 NVMDATH 0 NVMDATL 6 c0 8 14 Program Memory Write Latches 5 10 14 NVMADRL Write Latch #0 00h 14 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0020h 0021h 003Eh 003Fh 002h 0040h 0041h 005Eh 005Fh 3FEh 7FC0h 7FC1h 7FDEh 7FDFh 3FFh 7FE0h 7FE1h 7FFEh 7FFFh Program Flash Memory DS40001799F-page 118 400h NVMREGS = 1 14 Write Latch #31 1Fh 8000h - 8003h 8004h USER ID 0 - 3 reserved 8005h -8006h DEVICE ID Dev / Rev 8007h – 800Ah 800Bh - 801Fh Configuration Words reserved Configuration Memory PIC16(L)F18313/18323 NVMADRH NVMADRL Row Address Decode 14 Write Latch #30 1Eh Write Latch #1 01h 14 NVMREGS = 0 14 PIC16(L)F18313/18323 FIGURE 11-5: PROGRAM FLASH MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into PFM or Configuration Memory. The number of words cannot exceed the number of words per row (word_cnt) Load the value to write (NVMDATH:NVMDATL) Update the word counter (word_cnt--) Write Latches to PFM (LWLO = 0) Select PFM or Config. Memory (NVMREGS) Last word to write? No Select Row Address (NVMADRH:NVMADRL) Select Write Operation (FREE = 0) Disable Interrupts (GIE = 0) Yes Disable Interrupts (GIE = 0) Unlock Sequence (Figure 11-2) Unlock Sequence (Figure 11-2) CPU stalls while Write operation completes (2 ms typical) Load Write Latches Only (LWLO = 1) No delay when writing to PFM Latches Enable Write/Erase Operation (WREN = 1) Re-enable Interrupts (GIE = 1) Re-enable Interrupts (GIE = 1) Increment Address (NVMADRH:NVMADRL++)  2015-2019 Microchip Technology Inc. Disable Write/Erase Operation (WREN = 0) End Write Operation DS40001799F-page 119 PIC16(L)F18313/18323 EXAMPLE 11-4: ; ; ; ; ; ; ; WRITING TO PROGRAM FLASH MEMORY This write routine assumes the following: 1. 32 words of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F) 5. NVM interrupts are not taken into account BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF NVMADRH ADDRH,W NVMADRH ADDRL,W NVMADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H NVMCON1,NVMREGS NVMCON1,WREN NVMCON1,LWLO MOVIW MOVWF MOVIW MOVWF FSR0++ NVMDATL FSR0++ NVMDATH MOVF XORLW ANDLW BTFSC GOTO NVMADRL,W 0x1F 0x1F STATUS,Z START_WRITE CALL INCF GOTO UNLOCK_SEQ NVMADRL,F LOOP ; If not, go load latch ; Increment address NVMCON1,LWLO UNLOCK_SEQ NVMCON1,LWLO ; Latch writes complete, now write memory ; Perform required unlock sequence ; Disable writes ; Load initial address ; Load initial data address ; Set Program Flash Memory as write location ; Enable writes ; Load only write latches LOOP START_WRITE BCF CALL BCF UNLOCK_SEQ MOVLW BCF MOVWF MOVLW MOVWF BSF BSF return 55h INTCON,GIE NVMCON2 AAh NVMCON2 NVMCON1,WR INTCON,GIE  2015-2019 Microchip Technology Inc. ; Load first data byte ; Load second data byte ; ; ; ; Check if lower bits of address are 00000 and if on last of 32 addresses Last of 32 words? If so, go write latches into memory ; Disable interrupts ; Begin unlock sequence ; Unlock sequence complete, re-enable interrupts DS40001799F-page 120 PIC16(L)F18313/18323 11.4.6 MODIFYING PROGRAM FLASH MEMORY When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FIGURE 11-6: PROGRAM FLASH MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure11-1 x.x) Figure An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (Figure11-3 x.x) Figure Write Operation use RAM image (Figure11-5 x.x) Figure End Modify Operation  2015-2019 Microchip Technology Inc. DS40001799F-page 121 PIC16(L)F18313/18323 11.4.7 NVMREG EEPROM, USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS Instead of accessing program Flash memory, the EEPROM, the user ID’s, Device ID/Revision ID and Configuration Words can be accessed when NVMREGS = 1 in the NVMCON1 register. This is the region that would be pointed to by PC[15] = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-3. When read access is initiated on an address outside the parameters listed in Table 11-3, the NVMDATH: NVMDATL register pair is cleared, reading back ‘0’s. TABLE 11-3: EEPROM, USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS (NVMREGS = 1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8005h-8006h Device ID/Revision ID Yes No 8007h-800Ah Configuration Words 1-4 Yes No F000h-F0FFh EEPROM Yes Yes  2015-2019 Microchip Technology Inc. DS40001799F-page 122 PIC16(L)F18313/18323 11.4.8 WRITE VERIFY It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full row, then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 11-7: PROGRAM FLASH MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation Figure 11-1 No NVMDAT = RAM image? Yes No Fail Verify Operation Last Word? Yes End Verify Operation  2015-2019 Microchip Technology Inc. DS40001799F-page 123 PIC16(L)F18313/18323 11.4.9 WRERR BIT The WRERR bit can be used to determine if a write error occurred. WRERR will be set if one of the following conditions occurs: • If WR is set while the NVMADRH:NMVADRL points to a write-protected address • A Reset occurs while a self-write operation was in progress • An unlock sequence was interrupted The WRERR bit is normally set by hardware, but can be set by the user for test purposes. Once set, WRERR must be cleared in software. TABLE 11-4: ACTIONS FOR PROGRAM FLASH MEMORY WHEN WR = 1 Free LWLO Actions for Program Flash Memory when WR = 1 0 0 Write the write latch data to program Flash memory • If WP is enabled, WR is cleared row. See Section 11.4.4 “NVMREG Erase of Proand WRERR is set gram Flash Memory” • Write latches are reset to 3FFh • NVMDATH:NVMDATL is ignored 0 1 Copy NVMDATH:NVMDATL to the write latch corre- • Write protection is ignored sponding to NVMADR LSBs. See Section 11.4.4 • No memory access occurs “NVMREG Erase of Program Flash Memory” 1 x Erase the 32-word row of NVMADRH:NVMADRL location. See Section 11.4.3 “NVMREG Write to EEPROM”  2015-2019 Microchip Technology Inc. Comments • If WP is enabled, WR is cleared and WRERR is set • All 32 words are erased • NVMDATH:NVMDATL is ignored DS40001799F-page 124 PIC16(L)F18313/18323 11.5 Register Definitions: Program Flash Memory Control REGISTER 11-1: R/W-0/0 NVMDATL: NONVOLATILE MEMORY DATA LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NVMDAT[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NVMDAT[7:0]: Read/write value for Least Significant bits of program memory REGISTER 11-2: NVMDATH: NONVOLATILE MEMORY DATA HIGH BYTE REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NVMDAT[13:8] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 NVMDAT[13:8]: Read/write value for Most Significant bits of program memory(1) Note 1: This byte is ignored when writing to EEPROM. REGISTER 11-3: R/W-0/0 NVMADRL: NONVOLATILE MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NVMADR[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NVMADR[7:0]: Specifies the Least Significant bits for program memory address REGISTER 11-4: U-1 NVMADRH: NONVOLATILE MEMORY ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NVMADR[14:8] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 NVMADR[14:8]: Specifies the Most Significant bits for program memory address  2015-2019 Microchip Technology Inc. DS40001799F-page 125 PIC16(L)F18313/18323 REGISTER 11-5: NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER U-0 R/W-0/0 R/W-0/0 — NVMREGS LWLO R/W/HC-0/0 R/W/HS-x/q FREE WRERR R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 WREN WR RD bit 7 bit 0 Legend: q = Reset value is determined by hardware HS = Hardware set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘0’ bit 6 NVMREGS: Configuration Select bit 1 = Access EEPROM, Configuration, user ID and device ID registers 0 = Access program Flash memory bit 5 LWLO: Load Write Latches Only bit When FREE = 0: 1 = The next WR command updates the write latch for this word within the row; no memory operation is initiated. 0 = The next WR command writes data or erases. Otherwise: The bit is ignored. bit 4 FREE: Program Flash Memory Erase Enable bit When NVMREGS:NVMADR points to a program Flash memory location: 1 = Performs an erase operation with the next WR command; the row containing the indicated address is erased (to all 1s) to prepare for writing. 0 = All erase operations have completed normally bit 3 WRERR: Program/Erase Error Flag bit (1,2,3) 1 = A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one while NVMADR points to a write-protected address. 0 = The program or erase operation completed normally bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit(4,5,6) When NVMREG:NVMADR points to a EEPROM location: 1 = Initiates an erase/program cycle at the corresponding EEPROM location 0 = NVM program/erase operation is complete and inactive When NVMREG:NVMADR points to a program Flash memory location: 1 = Initiates the operation indicated by Table 11-5 0 = NVM program/erase operation is complete and inactive bit 0 RD: Read Control bit(7) 1 = Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle and the bit is cleared when the operation is complete. The bit can only be set (not cleared) in software. 0 = NVM read operation is complete and inactive. Note 1: 2: 3: 4: 5: 6: 7: Bit may change while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’). Bit must be cleared by software; hardware will not clear this bit. Bit may be written to ‘1’ by software in order to implement test sequences. This bit can only be set by following the unlock sequence of Section 11.4.2 “NVM Unlock Sequence”. Operations are self-timed, and the WR bit is cleared by hardware when complete. Once a write operation is initiated, setting this bit to zero will have no effect. Reading from EEPROM loads only NVMDATL[7:0] (Register 11-1).  2015-2019 Microchip Technology Inc. DS40001799F-page 126 PIC16(L)F18313/18323 REGISTER 11-6: W-0/0 NVMCON2: NONVOLATILE MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 NVMCON2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NVMCON2[7:0]: Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the NVMCON1 register. The value written to this register is used to unlock the writes. TABLE 11-5: SUMMARY OF REGISTERS ASSOCIATED WITH NONVOLATILE MEMORY (NVM) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE — — — — — INTEDG 89 — C2IF(2) C1IF NVMIF — — — NCO1IF 97 PIE2 — C2IE(2) C1IE NVMIE — — — NCO1IE 92 NVMCON1 — NVMREGS LWLO FREE WRERR WREN WR RD 126 PIR2 NVMCON2 NVMADRL —(1) NVMADRH NVMCON2 127 NVMADR[7:0] 125 NVMADR[14:8] NVMDATL 125 NVMDAT[7:0] — NVMDATH — 125 NVMDAT[13:8] 125 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM. Note 1: Unimplemented, read as ‘1’. 2: PIC16(L)F18345 only. TABLE 11-6: Name CONFIG3 CONFIG4 SUMMARY OF CONFIGURATION WORD WITH NONVOLATILE MEMORY (NVM) Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — LVP — — — — — 7:0 — — — — — — 13:8 — — — — — — — — 7:0 — — — — — — CPD CP WRT[1:0] Register on Page 54 55 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.  2015-2019 Microchip Technology Inc. DS40001799F-page 127 PIC16(L)F18313/18323 I/O PORTS GENERIC I/O PORT OPERATION PORT AVAILABILITY PER DEVICE Device PORTA TABLE 12-1: FIGURE 12-1: PIC16(L)F18313 ● PIC16(L)F18323 ● PORTC 12.0 ● Each port has ten standard registers for its operation. These registers are: • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) • TRISx registers (data direction) • ANSELx registers (analog select) • WPUx registers (weak pull-up) • INLVLx (input level control) • SLRCONx registers (slew rate) • ODCONx registers (open-drain) Most port pins share functions with device peripherals, both analog and digital. In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output; however, the pin can still be read. The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Read LATx D Write LATx Write PORTx TRISx Q CK VDD Data Register Data Bus I/O pin Read PORTx To digital peripherals To analog peripherals 12.1 ANSELx VSS I/O Priorities Each pin defaults to the PORT data latch after Reset. Other functions are selected with the peripheral pin select logic. See Section 13.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital output functions may continue to control the pin when it is in Analog mode. Analog outputs, when enabled, take priority over the digital outputs and force the digital output driver to the high-impedance state. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1.  2015-2019 Microchip Technology Inc. DS40001799F-page 128 PIC16(L)F18313/18323 12.2 PORTA Registers 12.2.1 DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input-only and its TRIS bit will always read as ‘1’. Example 12-1 shows how to initialize PORTA. Reading the PORTA register (Register 12-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 12.2.3 OPEN-DRAIN CONTROL The ODCONA register (Register 12-6) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONA bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONA bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. Note: 12.2.4 It is not necessary to set open-drain control when using the pin for I2C; the I2C module controls the pin and makes the pin open-drain. SLEW RATE CONTROL The PORT data latch LATA (Register 12-3) holds the output port data, and contains the latest value of a LATA or PORTA write. The SLRCONA register (Register 12-7) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONA bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum rate available. EXAMPLE 12-1: 12.2.5 ; ; ; ; INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF 12.2.2 PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Clear PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA[5:3] as inputs ;and set RA[2:0] as ;outputs DIRECTION CONTROL The TRISA register (Register 12-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’.  2015-2019 Microchip Technology Inc. INPUT THRESHOLD CONTROL The INLVLA register (Register 12-8) controls the input voltage threshold for each of the available PORTA input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 35-4 for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. DS40001799F-page 129 PIC16(L)F18313/18323 12.2.6 ANALOG CONTROL The ANSELA register (Register 12-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 12.2.7 The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. WEAK PULL-UP CONTROL The WPUA register (Register 12-5) controls the individual weak pull-ups for each PORT pin. PORTA pin RA3 includes the MCLR/VPP input. The MCLR input allows the device to be reset, and can be disabled by the MCLRE bit of Configuration Word 2. A weak pull-up is present on the RA3 port pin. This weak pull-up is enabled when MCLR is enabled (MCLRE = 1) or the WPUA3 bit is set. The weak pull-up is disabled when is disabled and the WPUA3 bit is clear. 12.2.8 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. Each pin defaults to the PORT latch data after Reset. Other output functions are selected with the peripheral pin select logic. See Section 13.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC and comparator inputs are not shown in the peripheral pin select lists. Digital output functions may continue to control the pin when it is in Analog mode.  2015-2019 Microchip Technology Inc. DS40001799F-page 130 PIC16(L)F18313/18323 12.3 Register Definitions: PORTA REGISTER 12-1: U-0 PORTA: PORTA REGISTER U-0 — — R/W-x/u R/W-x/u RA5 RA4 R-x/u (2) RA3 R/W-x/u R/W-x/u R/W-x/u RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA[5:0]: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: 2: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. Bit RA3 is read-only, and will read ‘1’ when MCLRE = 1 (master clear enabled). REGISTER 12-2: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 TRISA[5:4]: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 Unimplemented: Read as ‘1’ bit 2-0 TRISA[2:0]: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output  2015-2019 Microchip Technology Inc. DS40001799F-page 131 PIC16(L)F18313/18323 REGISTER 12-3: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA[5:4]: RA[5:4] Output Latch Value bits(1) bit 3 Unimplemented: Read as ‘0’ bit 2-0 LATA[2:0]: RA[2:0] Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ANSA[5:4]: Analog Select between Analog or Digital Function on pins RA[5:4], respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3 Unimplemented: Read as ‘0’ bit 2-0 ANSA[2:0]: Analog Select between Analog or Digital Function on pins RA[2:0], respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.  2015-2019 Microchip Technology Inc. DS40001799F-page 132 PIC16(L)F18313/18323 REGISTER 12-5: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — WPUA5 WPUA4 WPUA3(1) WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA[5:0]: Weak Pull-up Register bits(2) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: If MCLRE = 1, the weak pull-up in RA3 is always enabled; bit WPUA3 is not affected. The weak pull-up device is disabled if the pin is configured as an output except when the pin is also configured as open-drain. When configured as open-drain, the pull-up is enabled when the output value is high, and disabled when the output value is low. REGISTER 12-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — ODCA5 ODCA4 — ODCA2 ODCA1 ODCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ODCA[5:4]: PORTA Open-Drain Enable bits For RA[5:4] pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3 Unimplemented: Read as ‘0’ bit 2-0 ODCA[2:0]: PORTA Open-Drain Enable bits For RA[2:0] pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current)  2015-2019 Microchip Technology Inc. DS40001799F-page 133 PIC16(L)F18313/18323 REGISTER 12-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 SLRA[5:4]: PORTA Slew Rate Enable bits For RA[5:4] pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3 Unimplemented: Read as ‘0’ bit 2-0 SLRA[2:0]: PORTA Slew Rate Enable bits For RA[2:0] pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 12-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INLVLA[5:0]: PORTA Input Level Select bits For RA[5:0] pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change  2015-2019 Microchip Technology Inc. DS40001799F-page 134 PIC16(L)F18313/18323 TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 131 TRISA — — TRISA5 TRISA4 — TRISA2 TRISA1 TRISA0 131 LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 132 ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 132 WPUA0 133 Name WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 ODCONA — — ODCA5 ODCA4 — ODCA2 ODCA1 ODCA0 133 SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 134 INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 134 Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. TABLE 12-3: Name CONFIG2 Legend: SUMMARY OF CONFIGURATION WORD WITH PORTA Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — DEBUG STVREN PPS1WAY — BORV — 7:0 BOREN1 — WDTE1 WDTE0 PWRTE MCLRE BOREN0 LPBOREN Register on Page 53 — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.  2015-2019 Microchip Technology Inc. DS40001799F-page 135 PIC16(L)F18313/18323 12.4 12.4.1 PORTC Registers DATA REGISTER PORTC is a bidirectional port that is 6-bits wide. The corresponding data direction register is TRISC (Register 12-10). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-1 shows how to initialize an I/O port. Reading the PORTC register (Register 12-9) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). The PORT data latch LATC (Register 12-11) holds the output port data, and contains the latest value of a LATC or PORTC write. 12.4.2 DIRECTION CONTROL 12.4.4 OPEN-DRAIN CONTROL The ODCONC register (Register 12-14) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONC bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONC bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. Note: 12.4.5 It is not necessary to set open-drain control when using the pin for I2C; the I2C module controls the pin and makes the pin open-drain. SLEW RATE CONTROL The SLRCONC register (Register 12-15) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONC bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONC bit is cleared, The corresponding port pin drive slews at the maximum rate available. The TRISC register (Register 12-10) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 12.4.6 12.4.3 The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. INPUT THRESHOLD CONTROL The INLVLC register (Register 12-16) controls the input voltage threshold for each of the available PORTC input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTC register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 35-4 for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELC register (Register 12-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. Note: 12.4.7 The ANSELC bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. WEAK PULL-UP CONTROL The WPUC register (Register 12-13) controls the individual weak pull-ups for each PORT pin. 12.4.8 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 13.0 “Peripheral Pin Select (PPS) Module” for more information. Analog output functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. Digital output functions may continue to control the pin when it is in Analog mode.  2015-2019 Microchip Technology Inc. DS40001799F-page 136 PIC16(L)F18313/18323 12.5 Register Definitions: PORTC REGISTER 12-9: PORTC: PORTC REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RC[5:0]: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.  2015-2019 Microchip Technology Inc. DS40001799F-page 137 PIC16(L)F18313/18323 REGISTER 12-10: TRISC: PORTC TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISC[5:0]: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 12-11: LATC: PORTC DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LATC[5:0]: PORTC Output Latch Value bits  2015-2019 Microchip Technology Inc. DS40001799F-page 138 PIC16(L)F18313/18323 REGISTER 12-12: ANSELC: PORTC ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSC[5:0]: Analog Select between Analog or Digital Function on pins RC[5:0], respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 12-13: WPUC: WEAK PULL-UP PORTC REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUC[5:0]: Weak Pull-up Register bits(1) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: The weak pull-up is disabled if the pin is configured as an output except when the pin is also configured as open-drain. When configured as open-drain, the pull-up is enabled when the output value is high, and disabled when the output value is low.  2015-2019 Microchip Technology Inc. DS40001799F-page 139 PIC16(L)F18313/18323 REGISTER 12-14: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ODCC[5:0]: PORTC Open-Drain Enable bits For RC[5:0] pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 12-15: SLRCONC: PORTC SLEW RATE CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SLRC[5:0]: PORTC Slew Rate Enable bits For RC[5:0] pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate  2015-2019 Microchip Technology Inc. DS40001799F-page 140 PIC16(L)F18313/18323 REGISTER 12-16: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INLVLC[5:0]: PORTC Input Level Select bits For RC[5:0] pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change TABLE 12-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page Bit 7 Bit 6 PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 137 TRISC — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138 LATC — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 138 ANSELC — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139 WPUC — — WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 139 ODCONC — — ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 140 SLRCONC — — SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 140 INLVLC — — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 141 Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.  2015-2019 Microchip Technology Inc. DS40001799F-page 141 PIC16(L)F18313/18323 13.0 PERIPHERAL PIN SELECT (PPS) MODULE The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as shown in the simplified block diagram Figure 13-1. 13.1 PPS Inputs Each peripheral has a PPS register with which the inputs to the peripheral are selected. Inputs include the device pins. 13.2 Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals are: • EUSART1 (synchronous operation) • MSSP (I2C) Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown in Register 13-2. Although every peripheral has its own PPS input selection register, the selections are identical for every peripheral as shown in Register 13-1. Note: PPS Outputs Note: The notation “Rxy” is a place holder for the pin identifier. For example, RA0PPS. The notation “xxx” in the register name is a place holder for the peripheral identifier. For example, CLC1PPS. FIGURE 13-1: SIMPLIFIED PPS BLOCK DIAGRAM PPS Outputs RA0PPS PPS Inputs abcPPS RA0 RA0 Peripheral abc RxyPPS Rxy Peripheral xyz RC7(1) RC7PPS(1) xyzPPS RC7(1) Note 1: RB[7:4] and RC[7:6] are available on PIC16(L)F18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 142 PIC16(L)F18313/18323 13.3 Bidirectional Pins PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. Peripherals that have bidirectional signals are: • EUSART1 (synchronous operation) • MSSP (I2C) Note: 13.4 The I2C default input pins are I2C and SMBus compatible and are the only pins on the PIC16(L)F18313/18323 with this compatibility. Clock and data signals can be routed to any pin, however pins without I2C compatibility will operate at standard TTL/ST logic levels as selected by the INVLV register. PPSLOCKED Bit The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the PPSLOCKED bit are shown in Example 13-1. EXAMPLE 13-1: PPS LOCK/UNLOCK SEQUENCE 13.5 PPS1WAY Bit The PPS can be locked by setting the PPS1WAY bit of Configuration Word 2. When the PPS1WAY bit is set, the PPSLOCKED bit of the PPSLOCK register can be cleared and set only one time after a device Reset. Once the PPS registers are configured, user software sets the PPSLOCKED bit, preventing any further writes to the PPS registers. The PPS registers can be read at any time, regardless of the PPS1WAY or PPSLOCKED settings. When the PPS1WAY bit is clear, the PPSLOCKED bit of the PPSLOCK register can be cleared and set multiple times during code execution, but requires the PPS lock/unlock sequence to be performed each time modifications to the PPS registers are made. 13.6 Operation During Sleep PPS input and output selections are unaffected by Sleep. 13.7 Effects of a Reset A device Power-On-Reset (POR) clears all PPS input and output selections to their default values, and clears the PPSLOCKED bit of the PPSLOCK register. All other Resets leave the selections unchanged. Default input selections are shown in pin allocation Table 1 and Table 2. ; suspend interrupts bcf INTCON,GIE ; BANKSEL PPSLOCK ; set bank ; required sequence, next 5 instructions movlw 0x55 movwf PPSLOCK movlw 0xAA movwf PPSLOCK ; Set PPSLOCKED bit to disable writes or ; Clear PPSLOCKED bit to enable writes bsf PPSLOCK,PPSLOCKED ; restore interrupts bsf INTCON,GIE  2015-2019 Microchip Technology Inc. DS40001799F-page 143 PIC16(L)F18313/18323 13.8 Register Definitions: PPS Input Selection REGISTER 13-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION U-0 U-0 U-0 — — — R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u xxxPPS[4:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 xxxPPS[4:0]: Peripheral xxx Input Selection bits 11xxx = Reserved. Do not use. 10111 = Reserved. Do not use. 10110 = Reserved. Do not use. 10101 = Peripheral input is RC5(1) 10100 = Peripheral input is RC4(1) 10011 = Peripheral input is RC3(1) 10010 = Peripheral input is RC2(1) 10001 = Peripheral input is RC1(1) 10000 = Peripheral input is RC0(1) ... 01xxx = Reserved. Do not use. ... 0011x = Reserved. Do not use. 00101 = Peripheral input is RA5 00100 = Peripheral input is RA4 00011 = Peripheral input is RA3 00010 = Peripheral input is RA2 00001 = Peripheral input is RA1 00000 = Peripheral input is RA0 Note 1: PIC16(L)F18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 144 PIC16(L)F18313/18323 REGISTER 13-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER U-0 U-0 U-0 — — — R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u RxyPPS[4:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RxyPPS[4:0]: Pin Rxy Output Source Selection bits 11111 = Rxy source is DSM 11110 = Rxy source is CLKR 11101 = Rxy source is NCO1 11100 = Rxy source is TMR0 11011 = Reserved 11010 = Reserved 11001 = Rxy source is SDO1/SDA1 11000 = Rxy source is SCK1/SCL1(1) 10111 = Rxy source is C2(2) 10110 = Rxy source is C1 10101 = Rxy source is DT(1) 10100 = Rxy source is EUSART TC/CK 10011 = Reserved 10010 = Reserved 10001 = Reserved 10000 = Reserved 01111 = Reserved 01110 = Reserved 01101 = Rxy source is CCP2 01100 = Rxy source is CCP1 01011 = Rxy source is CWG1D(1) 01010 = Rxy source is CWG1C(1) 01001 = Rxy source is CWG1B(1) 01000 = Rxy source is CWG1A(1) 00111 = Reserved 00110 = Reserved 00101 = Rxy source is CLC2OUT 00100 = Rxy source is CLC1OUT 00011 = Rxy source is PWM6 00010 = Rxy source is PWM5 00001 = Reserved 00000 = Rxy source is LATxy Note 1: 2: TRIS control is overridden by the peripheral as required. PIC16(L)F18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 145 PIC16(L)F18313/18323 REGISTER 13-3: PPSLOCK: PPS LOCK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — PPSLOCKED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 PPSLOCKED: PPS Locked bit 1= PPS is locked. PPS selections can not be changed. 0= PPS is not locked. PPS selections can be changed. TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page PPSLOCK — — — — — — — PPSLOCKED 146 INTPPS — — — INTPPS[4:0] 144 T0CKIPPS — — — T0CKIPPS[4:0] 144 T1CKIPPS — — — T1CKIPPS[4:0] 144 T1GPPS — — — T1GPPS[4:0] 144 CCP1PPS — — — CCP1PPS[4:0] 144 CCP2PPS — — — CCP2PPS[4:0] 144 CWG1PPS — — — CWG1PPS[4:0] 144 MDCIN1PPS — — — MDCIN1PPS[4:0] 144 MDCIN2PPS — — — MDCIN2PPS[4:0] 144 MDMINPPS — — — MDMINPPS[4:0] 144 SSP1CLKPPS — — — SSP1CLKPPS[4:0] 144 SSP1DATPPS — — — SSP1DATPPS[4:0] 144 SSP1SSPPS — — — SSP1SSPPS[4:0] 144 RXPPS — — — RXPPS[4:0] 144 CLCIN0PPS — — — CLCIN0PPS[4:0] 144 CLCIN1PPS — — — CLCIN1PPS[4:0] 144 CLCIN2PPS — — — CLCIN2PPS[4:0] 144 CLCIN3PPS — — — CLCIN3PPS[4:0] 144 RA0PPS — — — RA0PPS[4:0] 145 RA1PPS — — — RA1PPS[4:0] 145 RA2PPS — — — RA2PPS[4:0] 145 RA4PPS — — — RA4PPS[4:0] 145 RA5PPS — — — RA5PPS[4:0] 145 Name Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module. Note 1: PIC16(L)F18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 146 PIC16(L)F18313/18323 TABLE 13-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page Bit 7 Bit 6 Bit 5 RC0PPS(1) — — — RC0PPS[4:0] 145 RC1PPS(1) — — — RC1PPS[4:0] 145 RC2PPS(1) — — — RC2PPS[4:0] 145 RC3PPS(1) — — — RC3PPS[4:0] 145 RC4PPS(1) — — — RC4PPS[4:0] 145 RC5PPS(1) — — — RC5PPS[4:0] 145 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module. Note 1: PIC16(L)F18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 147 PIC16(L)F18313/18323 14.0 PERIPHERAL MODULE DISABLE 14.2 When the register bit is cleared, the module is reenabled and will be in its Reset state; SFR data will reflect the POR Reset values. The PIC16(L)F18313/18323 provides the ability to disable selected modules, placing them into the lowest possible power mode. Depending on the module, it may take up to one full instruction cycle for the module to become active. There should be no interaction with the module (e.g., writing to registers) for at least one instruction after it has been re-enabled. For legacy reasons, all modules are ON by default following any Reset. 14.1 Enabling a Module Disabling a Module Disabling a module has the following effects: 14.3 • All clock and control inputs to the module are suspended; there are no logic transitions, and the module will not function. • The module is held in Reset. - Writing to the SFRs is disabled - Reads return 00h • Analog outputs are disabled; Digital outputs read ‘0’ Setting SYSCMD (PMD0, Register 14-1) disables the system clock (FOSC) distribution network to the peripherals. Not all peripherals make use of SYSCLK, so not all peripherals are affected. Refer to the specific peripheral description to see if it will be affected by this bit. REGISTER 14-1: System Clock Disable PMD0: PMD CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 SYSCMD FVRMD — — — NVMMD CLKRMD IOCMD 7 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SYSCMD: Disable Peripheral System Clock Network bit See description in Section 14.3 “System Clock Disable”. 1 = System Clock network disabled (a.k.a. FOSC) 0 = System Clock network enabled bit 6 FVRMD: Disable Fixed Voltage Reference FVR bit 1 = FVR module disabled 0 = FVR module enabled bit 5-3 Unimplemented: Read as ‘0’ bit 2 NVMMD: NVM Module Disable bit(1) 1 = Data EEPROM reading and writing is disabled; NVMCON registers cannot be written; FSR access to EEPROM returns zero. 0 = NVM module enabled bit 1 CLKRMD: Disable Clock Reference CLKR bit 1 = CLKR module disabled 0 = CLKR module enabled bit 0 IOCMD: Disable Interrupt-on-Change bit, All Ports 1 = IOC module(s) disabled 0 = IOC module(s) enabled Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.  2015-2019 Microchip Technology Inc. DS40001799F-page 148 PIC16(L)F18313/18323 REGISTER 14-2: PMD1: PMD CONTROL REGISTER 1 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 NCOMD — — — — TMR2MD TMR1MD TMR0MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 NCOMD: Disable Numerically Control Oscillator bit 1 = NCO1 module disabled 0 = NCO1 module enabled bit 6-3 Unimplemented: Read as ‘0’ bit 2 TMR2MD: Disable Timer TMR2 bit 1 = TMR2 module disabled 0 = TMR2 module enabled bit 1 TMR1MD: Disable Timer TMR1 bit 1 = TMR1 module disabled 0 = TMR1 module enabled bit 0 TMR0MD: Disable Timer TMR0 bit 1 = TMR0 module disabled 0 = TMR0 module enabled  2015-2019 Microchip Technology Inc. DS40001799F-page 149 PIC16(L)F18313/18323 REGISTER 14-3: U-0 PMD2: PMD CONTROL REGISTER 2 R/W-0/0 — DACMD R/W-0/0 ADCMD U-0 — U-0 R/W-0/0 R/W-0/0 U-0 — CMP2MD(1) CMP1MD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6 DACMD: Disable DAC bit 1 = DAC module disabled 0 = DAC module enabled bit 5 ADCMD: Disable ADC bit 1 = ADC module disabled 0 = ADC module enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 CMP2MD: Disable Comparator C2 bit(1) 1 = Comparator C2 module disabled 0 = Comparator C2 module enabled bit 1 CMP1MD: Disable Comparator C1 bit 1 = Comparator C1 module disabled 0 = Comparator C1 module enabled bit 0 Unimplemented: Read as ‘0’ Note 1: U = Unimplemented bit, read as ‘0’ PIC16(L)F18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 150 PIC16(L)F18313/18323 REGISTER 14-4: PMD3: PMD CONTROL REGISTER 3 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — CWG1MD PWM6MD PWM5MD — — CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6 CWG1MD: Disable CWG1 bit 1 = CWG1 module disabled 0 = CWG1 module enabled bit 5 PWM6MD: Disable PWM6 bit 1 = PWM6 module disabled 0 = PWM6 module enabled bit 4 PWM5MD: Disable PWM5 bit 1 = PWM5 module disabled 0 = PWM5 module enabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 CCP2MD: Disable CCP2 bit 1 = CCP2 module disabled 0 = CCP2 module enabled bit 0 CCP1MD: Disable CCP1 bit 1 = CCP1 module disabled 0 = CCP1 module enabled  2015-2019 Microchip Technology Inc. U = Unimplemented bit, read as ‘0’ DS40001799F-page 151 PIC16(L)F18313/18323 REGISTER 14-5: PMD4: PMD CONTROL REGISTER 4 U-0 U-0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 U-0 — — UART1MD — — — MSSP1MD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5 UART1MD: Disable EUSART1 bit 1 = EUSART1 module disabled 0 = EUSART1 module enabled bit 4-2 Unimplemented: Read as ‘0’ bit 1 MSSP1MD: Disable MSSP1 bit 1 = MSSP1 module disabled 0 = MSSP1 module enabled bit 0 Unimplemented: Read as ‘0’  2015-2019 Microchip Technology Inc. DS40001799F-page 152 PIC16(L)F18313/18323 REGISTER 14-6: PMD5: PMD CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — CLC2MD CLC1MD DSMMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as ‘0’ bit 2 CLC2MD: Disable CLC2 bit 1 = CLC2 module disabled 0 = CLC2 module enabled bit 1 CLC1MD: Disable CLC1 bit 1 = CLC1 module disabled 0 = CLC1 module enabled bit 0 DSMMD: Disable Data Signal Modulator bit 1 = DSM module disabled 0 = DSM module enabled  2015-2019 Microchip Technology Inc. U = Unimplemented bit, read as ‘0’ DS40001799F-page 153 PIC16(L)F18313/18323 15.0 INTERRUPT-ON-CHANGE All pins on all ports can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual pin, or combination of pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: • Interrupt-on-Change enable - Rising and falling edge detection • Individual pin configuration • Individual pin interrupt flags Figure 15-1 is a block diagram of the IOC module. 15.1 Enabling the Module To allow individual pins to generate an interrupt, the IOCIE bit of the PIE0 register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 15.2 Individual Pin Configuration 15.3 The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the PIR0 register reflects the status of all IOCxF bits. 15.3.1 CLEARING INTERRUPT FLAGS The individual status flags, (IOCxF register bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 15-1: For each pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in both of the IOCxP and IOCxN registers. Interrupt Flags MOVLW XORWF ANDWF 15.4 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt event will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the affected IOCxF register will be updated prior to the first instruction executed out of Sleep.  2015-2019 Microchip Technology Inc. DS40001799F-page 154 PIC16(L)F18313/18323 FIGURE 15-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D Q R data bus = 0 or 1 D S to data bus IOCAFx Q write IOCAFx IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors  2015-2019 Microchip Technology Inc. DS40001799F-page 155 PIC16(L)F18313/18323 15.5 Register Definitions: Interrupt-on-Change Control REGISTER 15-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP[5:0]]: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin REGISTER 15-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAN[5:0]: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin  2015-2019 Microchip Technology Inc. DS40001799F-page 156 PIC16(L)F18313/18323 REGISTER 15-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 — — R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF5 IOCAF4 IOCAF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF[5:0]: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change.  2015-2019 Microchip Technology Inc. DS40001799F-page 157 PIC16(L)F18313/18323 REGISTER 15-4: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER(1) U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCCP[5:0]: Interrupt-on-Change PORTC Positive Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin Note 1: PIC16(L)F18323 only. REGISTER 15-5: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER(1) U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCCN[5:0]: Interrupt-on-Change PORTC Negative Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin Note 1: PIC16(L)F18323 only.  2015-2019 Microchip Technology Inc. DS40001799F-page 158 PIC16(L)F18313/18323 REGISTER 15-6: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER(1) U-0 U-0 — — R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCCF5 IOCCF4 IOCCF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCCF2 IOCCF1 IOCCF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCCF[5:0]: Interrupt-on-Change PORTC Flag bits(1) 1 = An enabled change was detected on the associated pin. Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was detected on RCx. 0 = No change was detected, or the user cleared the detected change. Note 1: PIC16(L)F18323 only. TABLE 15-1: Name ANSELA (1) ANSELC SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSA4 ANSA4 — ANSA2 ANSA1 ANSA0 132 — — ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 139 TRISA — — TRISA5 TRISA4 —(2) TRISA2 TRISA1 TRISA0 131 TRISC(1) — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 138 INTCON GIE PEIE — — — — — INTEDG 89 PIE0 — — TMR0IE IOCIE — — — INTE 90 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 156 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 156 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 157 (1) — — IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 158 (1) IOCCN — — IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 158 IOCCF(1) — — IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 159 IOCCP Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. Note 1: PIC16(L)F18323 only. 2: Unimplemented, read as ‘1’.  2015-2019 Microchip Technology Inc. DS40001799F-page 159 PIC16(L)F18313/18323 16.0 FIXED VOLTAGE REFERENCE (FVR) 16.1 The output of the FVR, which is supplied to the ADC, Comparators and DAC, is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR subsystem can be configured to supply a reference voltage to the following: • • • • The ADFVR[1:0] bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 22.0 “Analog-to-Digital Converter (ADC) Module” for additional information. ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The CDAFVR[1:0] bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator module. Reference Section 24.0 “5-bit Digital-to-Analog Converter (DAC1) Module” and Section 18.0 “Comparator Module” for additional information. The FVR can be enabled by setting the FVREN bit of the FVRCON register. Note: Independent Gain Amplifiers Fixed Voltage Reference output cannot exceed VDD. 16.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. See Table 35-16 for FVR start-up times. FIGURE 16-1: VOLTAGE REFERENCE BLOCK DIAGRAM Rev. 10-000 053C 12/9/201 3 ADFVR CDAFVR FVREN 1x 2x 4x FVR_buffer1 (To ADC Module) 1x 2x 4x FVR_buffer2 (To Comparators and DAC) 2 + _ Note 1 Note: 2 FVRRDY Any peripheral requiring the fixed reference (see Table 16-1).  2015-2019 Microchip Technology Inc. DS40001799F-page 160 PIC16(L)F18313/18323 16.3 Register Definitions: FVR Control REGISTER 16-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q FVREN FVRRDY(1) R/W-0/0 (3) TSEN R/W-0/0 R/W-0/0 (3) TSRNG R/W-0/0 R/W-0/0 CDAFVR[1:0] bit 7 R/W-0/0 ADFVR[1:0] bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR[1:0]: Comparator FVR Buffer Gain Selection bits 11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2) 10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2) 01 = Comparator FVR Buffer Gain is 1x, (1.024V) 00 = Comparator FVR Buffer is off bit 1-0 ADFVR[1:0]: ADC FVR Buffer Gain Selection bit 11 = ADC FVR Buffer Gain is 4x, (4.096V)(2) 10 = ADC FVR Buffer Gain is 2x, (2.048V)(2) 01 = ADC FVR Buffer Gain is 1x, (1.024V) 00 = ADC FVR Buffer is off Note 1: 2: 3: FVRRDY is always ‘1’. Fixed Voltage Reference output cannot exceed VDD. See Section 17.0 “Temperature Indicator Module” for additional information.  2015-2019 Microchip Technology Inc. DS40001799F-page 161 PIC16(L)F18313/18323 TABLE 16-1: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG ADCON0 ADCON1 Bit 3 Bit 2 CDAFVR[1:0] CHS[5:0] ADFM ADCS[2:0] CMxCON1 CxINTP CxINTN DAC1CON0 DAC1EN — ADNREF — Bit 0 ADFVR[1:0] GO/DONE — CxPCH[2:0] DAC1OE Bit 1 ADON ADPREF[1:0] CxNCH[2:0] DAC1PPS[1:0] — Register on page 161 225 226 172 DAC1NSS 244 Legend: Shaded cells are not used with the Fixed Voltage Reference.  2015-2019 Microchip Technology Inc. DS40001799F-page 162 PIC16(L)F18313/18323 17.0 TEMPERATURE INDICATOR MODULE FIGURE 17-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN2092, “Using the Temperature Indicator Module” (DS00002092) for more details regarding the calibration process. 17.1 Circuit Operation Figure 17-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 17-1 describes the output characteristics of the temperature indicator. EQUATION 17-1: VOUT RANGES TEMPERATURE CIRCUIT DIAGRAM VOUT Temp. Indicator 17.2 To ADC Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 17-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT Low Range: VOUT = VDD - 2VT The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 16.0 “Fixed Voltage Reference (FVR)” for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. TABLE 17-1: RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 17.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is provided for the temperature circuit output. Refer to Section 22.0 “Analog-to-Digital Converter (ADC) Module” for detailed information. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower VDD voltage is needed to operate the circuit. The low range is provided for low voltage operation.  2015-2019 Microchip Technology Inc. DS40001799F-page 163 PIC16(L)F18313/18323 17.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. TABLE 17-2: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR[1:0] Bit 1 Bit 0 ADFVR[1:0] Register on page 161 Legend: Shaded cells are unused by the temperature indicator module.  2015-2019 Microchip Technology Inc. DS40001799F-page 164 PIC16(L)F18313/18323 18.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • Programmable input selection - Selectable voltage reference • Programmable output polarity • Rising/falling output edge interrupts • Wake-up from Sleep • CWG Auto-shutdown source 18.1 Comparator Overview A single comparator is shown in Figure 18-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparators available for this device are located in Table 18-1. TABLE 18-1: AVAILABLE COMPARATORS Device C1 PIC16(L)F18313 ● PIC16(L)F18323 ● FIGURE 18-1: C2 ● SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.  2015-2019 Microchip Technology Inc. DS40001799F-page 165 PIC16(L)F18313/18323 FIGURE 18-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM Rev. 10-000027M 9/20/2016 CxNCH 3 CxON(1) CxIN0- 000 CxIN1- 001 CxIN2- 010 CxIN3- 011 Reserved 100 Reserved 101 FVR_buffer2 110 CxON(1) CxVN Interrupt Rising Edge CxINTP Interrupt Falling Edge CxINTN set bit CxIF - D CxOUT Q MCxOUT Cx CxVP 111 + Q1 CxSP CxHYS CxPOL CxOUT_sync CxSYNC 000 CxIN0+ Reserved 001 Reserved 010 Reserved 011 Reserved 100 DAC_output 101 FVR_buffer2 110 to peripherals TRIS bit 0 PPS D (From Timer1 Module) T1CLK Q CxOUT 1 RxyPPS 111 CxPCH Note 1: 2 CxON(1) When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.  2015-2019 Microchip Technology Inc. DS40001799F-page 166 PIC16(L)F18313/18323 18.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 register (see Register 18-1) contains Control and Status bits for the following: • • • • • Enable Output Output polarity Hysteresis enable Timer1 output synchronization The CMxCON1 register (see Register 18-2) contains Control bits for the following: • Interrupt on positive/negative edge enables • Positive input channel selection • Negative input channel selection 18.2.1 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 18-2 shows the output state versus input conditions, including polarity control. TABLE 18-2: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 18.2.2 18.2.3 COMPARATOR OUTPUT The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. The comparator output can also be routed to an external pin through the RxyPPS register (Register 13-2). The corresponding TRIS bit must be clear to enable the pin as an output. Note 1: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 18.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. See Comparator Specifications in Table 35-14 for more information. 18.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 27.5 “Timer1 Gate” for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 18.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from a comparator can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. This allows the timer/counter to synchronize with the CxOUT bit so that the software sees no ambiguity due to timing. See the Comparator Block Diagram (Figure 18-2) and the Timer1 Block Diagram (Figure 27-1) for more information.  2015-2019 Microchip Technology Inc. DS40001799F-page 167 PIC16(L)F18313/18323 18.5 Comparator Interrupt An interrupt can be generated when either the rising edge or falling edge detector detects a change in the output value of each comparator. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. To enable the interrupt, you must set the following bits: • CxON bit of the CMxCON0 register • CxIE bit of the PIE2 register • CxINTP bit of the CMxCON1 register (for a rising edge detection) • CxINTN bit of the CMxCON1 register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: 18.6 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. 18.7 Comparator Negative Input Selection The CxNCH CxVN 0 = CxVP < CxVN bit 5 Unimplemented: Read as ‘0’ bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in Normal-Power, High-Speed mode 0 = Reserved. (do not use) bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous  2015-2019 Microchip Technology Inc. DS40001799F-page 171 PIC16(L)F18313/18323 REGISTER 18-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CxPCH 16 MHz D002 VDD 2.3 2.5 — — 5.5 5.5 V V FOSC  16 MHz: FOSC > 16 MHz RAM Data Retention(1) D003 VDR 1.5 — — V Device in Sleep mode D003 VDR 1.7 — — V Device in Sleep mode Power-on Reset Release Voltage(2) D004 VPOR — 1.6 — V BOR and LPBOR disabled(3) D004 VPOR — 1.6 — V BOR and LPBOR disabled(3) Power-on Reset ReARM Voltage(2) D005 VPORR — 0.8 — V BOR and LPBOR disabled(3) D005 VPORR — 1.5 — V BOR and LPBOR disabled(3) VDD Rise Rate to ensure Internal Power-on Reset Signal(2) D006 SVDD 0.05 — — V/ms BOR and LPBOR disabled(3) D006 SVDD 0.05 — — V/ms BOR and LPBOR disabled(3) † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode or during a device Reset, without losing RAM data. 2: See Figure 35-3. 3: Please see Table 35-11 for BOR and LPBOR trip point information.  2015-2019 Microchip Technology Inc. DS40001799F-page 393 PIC16(L)F18313/18323 FIGURE 35-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.  2015-2019 Microchip Technology Inc. DS40001799F-page 394 PIC16(L)F18313/18323 TABLE 35-2: SUPPLY CURRENT (IDD)(1,2) PIC16LF18313/18323 Standard Operating Conditions (unless otherwise stated) PIC16F18313/18323 Param. No. Symbol Standard Operating Conditions (unless otherwise stated) Device Characteristics Min. Typ.† Max. Units Conditions VDD D100 IDDXT4 XT = 4 MHz — 292 390 uA 3.0V D100 IDDXT4 XT = 4 MHz — 302 410 uA 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz — 1.2 1.5 mA 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz — 1.3 1.6 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.0 2.6 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 2.1 2.6 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.0 2.4 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.1 2.5 mA 3.0V D104 IDDIDLE Idle Mode, HFINTOSC = 16 MHz — 733 1100 uA 3.0V D104 IDDIDLE Idle Mode, HFINTOSC = 16 MHz — 743 1100 uA 3.0V D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, DOZE Ratio = 16 — 786 — uA 3.0V D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, DOZE Ratio = 16 — 796 — uA 3.0V Note † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see Register 9-2).  2015-2019 Microchip Technology Inc. DS40001799F-page 395 PIC16(L)F18313/18323 TABLE 35-3: POWER-DOWN CURRENTS (IPD)(1,2,3) PIC16LF18313/18323 Standard Operating Conditions (unless otherwise stated) PIC16F18313/18323 Standard Operating Conditions (unless otherwise stated) VREGPM = 1 Param. No. Symbol Device Characteristics Conditions Max. Max. Units +85°C +125°C VDD Note Min. Typ.† 0.03 2 5.2 A 3.0V D200 IPD IPD Base — D200 IPD IPD Base — 0.3 2.4 5.6 A 3.0V — 12.8 22 27 A 3.0V VREGPM = 0 D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — 0.4 2.9 6 A 3.0V D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — 0.5 3.3 6.6 A 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) — 1.3 2.8 6 A 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) — 1.5 3.2 6.4 A 3.0V D203 IPD_FVR FVR — 45 74 76 A 3.0V D203 IPD_FVR FVR — 40 70 75 A 3.0V D204 IPD_BOR Brown-out Reset (BOR) — 10.6 16 19 A 3.0V D204 IPD_BOR Brown-out Reset (BOR) — 10.5 16.4 19.4 A 3.0V D205 IPD_LPBOR Low Power Brown-out Reset (LPBOR) — 0.3 2.5 5.5 A 3.0V D207 IPD_ADCA ADC - Non-converting — 0.3 2 5.2 A 3.0V ADC not converting(4) D207 IPD_ADCA ADC - Non-converting — 0.3 2.4 5.6 A 3.0V ADC not converting(4) D208 IPD_CMP Comparator — 30 45 50 A 3.0V D208 IPD_CMP Comparator — 30 44 49 A 3.0V * These parameters are characterized but not tested. † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4: ADC clock source is ADCRC.  2015-2019 Microchip Technology Inc. DS40001799F-page 396 PIC16(L)F18313/18323 TABLE 35-4: I/O PORTS DC CHARACTERISTICS Param. Sym. No. VIL Standard Operating Conditions (unless otherwise stated) Characteristic Min. Typ.† Max. Units Conditions — — 0.8 V 4.5V  VDD  5.5V — — 0.15 VDD V 1.8V  VDD  4.5V — — 0.2 VDD V 2.0V  VDD  5.5V — — 0.3 VDD V Input Low Voltage I/O PORT: D300 with TTL buffer D301 D302 with Schmitt Trigger buffer I2C levels D303 with D304 with SMBus levels — — 0.8 V D305 MCLR — — 0.2 VDD V 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V 0.8 VDD — — V 2.0V  VDD  5.5V 0.7 VDD — — V 2.1 — — V 0.7 VDD — — V — ±5 ± 125 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C — ±5 ± 1000 nA VSS  VPIN  VDD, Pin at high-impedance, 125°C — ± 50 ± 200 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C 25 120 200 A VDD = 3.0V, VPIN = VSS — — 0.6 V IOL = 10.0 mA, VDD = 3.0V VDD - 0.7 — — V IOH = 6.0 mA, VDD = 3.0V — 5 50 pF VIH 2.7V  VDD  5.5V Input High Voltage I/O PORT: D320 with TTL buffer D321 D322 with Schmitt Trigger buffer I2C D323 with D324 with SMBus levels D325 MCLR IIL D340 levels Input Leakage Current(2) I/O Ports D341 MCLR(2) D342 IPUR Weak Pull-up Current VOL Voltage(4) D350 D360 I/O ports VOH D370 D380 Output Low Output High Voltage(4) I/O ports CIO 2.7V  VDD  5.5V All I/O pins * These parameters are characterized but not tested. † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.  2015-2019 Microchip Technology Inc. DS40001799F-page 397 PIC16(L)F18313/18323 TABLE 35-5: MEMORY SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units — 9 V Note 2 — — — uA Note 2 High Voltage Entry Programming Mode Specifications Voltage on MCLR/VPP pin to MEM01 VIHH 7.9 enter Programming mode MEM02 IPPGM Current on MCLR/VPP pin during Programming mode Conditions Programming Mode Specifications MEM10 VBE VDD for Bulk Erase — 2.7 — V MEM11 Supply Current during Programming Operation — — 5 mA IDDPGM Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance 100k — — E/W -40°C  TA 85°C MEM21 TD_RET Characteristic Retention — 40 — Year MEM22 ND_REF Total Erase/Write Cycles before Refresh — — 100k E/W MEM23 VD_RW VDD for Read or Erase/Write Operation VDDMIN — VDDMAX V — 4.0 5.0 ms 10k — — E/W -40°C  Ta  85°C (Note 1) Provided no other specifications are violated MEM24 TD_BEW Byte Erase and Write Cycle Time Provided no other specifications are violated Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance MEM32 TP_RET Characteristic Retention — 40 — Year MEM33 VP_RD VDD for Read Operation VDDMIN — VDDMAX V VDDMIN — VDDMAX V — 2.0 2.5 ms VDD for Row Erase or Write MEM34 VP_REW Operation MEM35 TP_REW Self-Timed Row Erase or Self-Timed Write † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. 2: Required only if CONFIG3.LVP is disabled.  2015-2019 Microchip Technology Inc. DS40001799F-page 398 PIC16(L)F18313/18323 TABLE 35-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 Sym. JA JC Characteristic Thermal Resistance Junction-to-Ambient Thermal Resistance Junction-to-Case TH03 TJMAX Maximum Junction Temperature TH04 PD Power Dissipation TH05 Typ. Units Conditions 46.2 C/W 8-pin PDIP package 112.4 C/W 8-pin SOIC package 52.2 C/W 8-pin UDFN package 70.0 C/W 14-pin PDIP package 95.3 C/W 14-pin SOIC package 100.0 C/W 14-pin TSSOP package 51.5 C/W 16-pin UQFN 4x4mm package 62.2 C/W 20-pin PDIP package 87.3 C/W 20-pin SSOP package 77.7 C/W 20-pin SOIC package 43.0 C/W 20-pin UQFN 4x4mm package 33.3 C/W 8-pin PDIP package 50.0 C/W 8-pin SOIC package 4.0 C/W 8-pin UDFN package 32.75 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 24.4 C/W 14-pin TSSOP package 5.4 C/W 16-pin UQFN 4x4mm package 27.5 C/W 20-pin PDIP package 31.1 C/W 20-pin SSOP package 23.1 C/W 20-pin SOIC package 5.3 C/W 20-pin UQFN 4x4mm package 150 C 0.800 W PD = PINTERNAL + PI/O PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature  2015-2019 Microchip Technology Inc. DS40001799F-page 399 PIC16(L)F18313/18323 35.4 AC Characteristics FIGURE 35-4: LOAD CONDITIONS Load Condition Pin CL VSS Note: CL = 50 pF for all pins FIGURE 35-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS1 OS2 OS2 OS20 CLKOUT (CLKOUT Mode) Note: See Table 35-10.  2015-2019 Microchip Technology Inc. DS40001799F-page 400 PIC16(L)F18313/18323 TABLE 35-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency — — 500 kHz OS2 TECL_DC Clock Duty Cycle 40 — 60 % ECM Oscillator OS3 FECM Clock Frequency — — 8 MHz OS4 TECM_DC Clock Duty Cycle 40 — 60 % Note 4 ECH Oscillator OS5 FECH Clock Frequency — — 32 MHz OS6 TECH_DC Clock Duty Cycle 40 — 60 % Clock Frequency — — 100 kHz Note 4 Clock Frequency — — 4 MHz Note 4 Clock Frequency — — 20 MHz Note 4 — — 32 MHz Note 2, Note 3 — FOSC/4 — MHz 125 1/FCY — ns LP Oscillator OS7 FLP XT Oscillator OS8 FXT HS Oscillator OS9 FHS System Clock OS20 FOSC System Clock Frequency OS21 FCY Instruction Frequency OS22 TCY Instruction Period * † Note 1: 2: 3: 4: These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 7.3 “Clock Switching”. The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 35.2 “Standard Operating Conditions”. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with an external square wave, one of the EC mode selections must be used.  2015-2019 Microchip Technology Inc. DS40001799F-page 401 PIC16(L)F18313/18323 TABLE 35-8: INTERNAL OSCILLATOR PARAMETERS(1) Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions OS20 FHFOSC Precision Calibrated HFINTOSC Frequency — 4 8 12 16 32 — MHz -40°C to +125°C (2) OS21 FHFOSCLP Low-Power Optimized HFINTOSC Frequency 0.93 1.86 0.88 1.76 1 2 1 2 1.07 2.14 1.12 2.24 MHz -40°C to +85°C -40°C to +85°C -40°C to +125°C -40°C to +125°C OS23 FLFOSC Internal LFINTOSC Frequency — 31 — kHz OS24 THFOSCST HFINTOSC Wake-up from Sleep Start-up Time — 11 50 20 — s s OS26 TLFOSCST LFINTOSC Wake-up from Sleep Start-up Time — 0.2 — ms VREGPM = 0 VREGPM = 1 * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 35-6. FIGURE 35-6: PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 0 ± 5% -40 1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2015-2019 Microchip Technology Inc. DS40001799F-page 402 PIC16(L)F18313/18323 TABLE 35-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic PLL Input Frequency Range Min. Typ.† Max. Units 4 — 8 MHz PLL01 FPLLIN PLL02 FPLLOUT PLL Output Frequency Range 16 — 32 MHz PLL03 TPLLST PLL Lock Time from Start-up — 200 — s PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) -0.25 — 0.25 % Conditions * These parameters are characterized but not tested. † Data in “Typ.” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 35-7: Cycle CLKOUT AND I/O TIMING Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 IO12 CLKOUT IO8 IO4 IO7 IO5 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO7, IO8  2015-2019 Microchip Technology Inc. DS40001799F-page 403 PIC16(L)F18313/18323 TABLE 35-10: CLKOUT AND I/O TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions IO1 TCLKOUTH CLKOUT rising edge delay (rising edge FOSC (Q1 cycle) to falling edge CLKOUT — — 70 ns IO2 TCLKOUTL CLKOUT falling edge delay (rising edge FOSC (Q3 cycle) to rising edge CLKOUT — — 72 ns IO3 TIO_VALID Port output valid time (rising edge FOSC (Q1 cycle) to port valid) — 50 70 ns IO4 TIO_SETUP Port input setup time (Setup time before rising edge FOSC - Q2 cycle) 20 — — ns IO5 TIO_HOLD Port input hold time (Hold time after rising edge FOSC - Q2 cycle) 50 — — ns IO6 TIOR_SLREN Port I/O rise time, slew rate enabled — 25 — ns VDD = 3.0V IO7 TIOR_SLRDIS Port I/O rise time, slew rate disabled — 5 — ns VDD = 3.0V IO8 TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD = 3.0V IO9 TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD = 3.0V IO10 TINT INT pin high or low time to trigger an interrupt 25 — — ns IO11 TIOC Interrupt-on-Change minimum 25 high or low time to trigger interrupt — — ns * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25C unless otherwise stated.  2015-2019 Microchip Technology Inc. DS40001799F-page 404 PIC16(L)F18313/18323 FIGURE 35-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST03 RST02 RST02 I/O pins Note 1: Asserted low. FIGURE 35-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device not in Brown-out Reset) (Device in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms delay if PWRTE = 0.  2015-2019 Microchip Technology Inc. DS40001799F-page 405 PIC16(L)F18313/18323 TABLE 35-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT RESET AND LOW POWER BROWN-OUT RESET SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units RST01 TMCLR MCLR Pulse Width Low to ensure Reset 2 — — s RST02 TIOZ I/O high-impedance from Reset detection — — 2 s RST03 TWDT Watchdog Timer Time-out Period 10 16 27 ms RST04* TPWRT Power-up Timer Period 40 65 140 ms RST05 TOST Oscillator Start-up Timer Period(1,2) — 1024 — RST06 VBOR Brown-out Reset Voltage(4) 2.55 2.30 1.80 2.70 2.45 1.90 2.85 2.60 2.10 V V V RST07 VBORHYS Brown-out Reset Hysteresis 0 25 75 mV RST08 TBORDC Brown-out Reset Response Time 1 3 35 s RST09 VLPBOR Low-Power Brown-out Reset Voltage 1.8 2.1 2.5 V * † Note 1: 2: 3: 4: Conditions 16 ms Nominal Reset Time TOSC (Note3) BORV = 0 BORV = 1 (PIC16F18313/18323) BORV = 1 (PIC16LF18313/18323) PIC16LF18313/18323 These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.  2015-2019 Microchip Technology Inc. DS40001799F-page 406 PIC16(L)F18313/18323 TABLE 35-12: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2) Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD03 EDL Differential Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD04 EOFF Offset Error — 0.5 ±2.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD05 EGN Gain Error — ±0.2 ±2.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD06 VADREF ADC Reference Voltage (ADREF+) 1.8 — VDD V AD07 VAIN Full-Scale Range VSS — ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source — 10 — k AD09 RVREF ADC Voltage Reference Ladder Impedance — 50 — k * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors. 2: The ADC conversion result never decreases with an increase in the input and has no missing codes.  2015-2019 Microchip Technology Inc. DS40001799F-page 407 PIC16(L)F18313/18323 TABLE 35-13: ANALOG-TO DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS(1,2) Standard Operating Conditions (unless otherwise stated) Param. No. AD20 Sym. TAD Characteristic ADC Clock Period AD21 Min. Typ.† Max. Units Conditions 1 — 9 us Using FOSC as the ADC clock source; ADCS ! = x11 1 2 6 us Using ADCRC as the ADC clock source; ADCS = x11 — 11 — TAD AD22 TCNV Conversion Time AD23 TACQ THCD Acquisition Time — 2 — us Sample and Hold Capacitor Disconnect Time 0.5 — — TAD FOSC based clock source 0.5 — — TAD ADCRC based clock source AD24 * † Set of GO/DONE bit to Clear of GO/DONE bit These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 35-10: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD132  2015-2019 Microchip Technology Inc. Sampling Stopped DS40001799F-page 408 PIC16(L)F18313/18323 FIGURE 35-11: ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample Note: AD132 Sampling Stopped If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.  2015-2019 Microchip Technology Inc. DS40001799F-page 409 PIC16(L)F18313/18323 TABLE 35-14: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C See Section 36.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. Param No. CM01 Sym. VIOFF Characteristics Min. Typ. Max. Units — — ±50 mV Input Offset Voltage Comments VICM = VDD/2 CM02 VICM Input Common Mode Voltage GND — VDD V CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB CM04 CHYST Comparator Hysteresis 15 25 35 mV CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns Response Time, Falling Edge — 220 500 ns CM06* TMCV2VO(2) Mode Change to Valid Output — — 10 us * Note 1: These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. A mode change includes changing any of the control register values, including module enable. 2: TABLE 35-15: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristics Min. Typ.† Max. Units DSB01 VLSB Step Size — VDD/32 — V DSB01 VACC Absolute Accuracy — —  0.5 LSb DSB03* RUNIT Unit Resistor Value — 6000 —  — — 10 s DSB04* TST Settling Time(1) Comments * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while DACR[4:0] transitions from ‘00000’ to ‘01111’. TABLE 35-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions FVR01 VFVR1 1x Gain (1.024V nominal) -4 — 4 % VDD  2.5V, -40°C to 85°C FVR02 VFVR2 2x Gain (2.048V nominal) -4 — 4 % VDD  2.5V, -40°C to 85°C FVR03 VFVR4 4x Gain (4.096V nominal) -5 — 5 % VDD  4.75V, -40°C to 85°C FVR04 TFVRST FVR Start-up Time — 35 — s  2015-2019 Microchip Technology Inc. DS40001799F-page 410 PIC16(L)F18313/18323 FIGURE 35-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 35-17: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Time Synchronous, No Prescaler 46* TT1L T1CKI Low Time Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous Greater of: 30 or TCY + 40 N — — ns 47* TT1P T1CKI Input Period 48 F T1 Secondary Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * † Typ.† 60 — — ns 32.4 32.768 33.1 kHz 2 TOSC — 7 TOSC — Conditions N = prescale value N = prescale value Timers in Sync mode These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2015-2019 Microchip Technology Inc. DS40001799F-page 411 PIC16(L)F18313/18323 FIGURE 35-13: CAPTURE/COMPARE/PWM (CCP) TIMINGS CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 35-4 for Load conditions. TABLE 35-18: CAPTURE/COMPARE/PWM (CCP) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. Characteristic CC01* TccL CCPx Input Low Time No Prescaler CC02* TccH CCPx Input High Time CC03* TccP CCPx Input Period With Prescaler No Prescaler With Prescaler * † Min. Typ.† Max. Units 0.5TCY + 20 — — ns 20 — — ns 0.5TCY + 20 — — ns 20 — — ns 3TCY + 40 N — — ns Conditions N = prescale value These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2015-2019 Microchip Technology Inc. DS40001799F-page 412 PIC16(L)F18313/18323 FIGURE 35-14: CLC PROPAGATION TIMING CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC01 CLC02 CLC03 Note 1: See Figure 21-1, "CLCx Simplified Block Diagram" to identify specific CLC signals. TABLE 35-19: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions CLC01* TCLCIN CLC input time — 7 OS17 ns (Note 1) CLC02* TCLC CLC module input to output progagation time — — 24 12 — — ns ns VDD = 1.8V VDD > 3.6V CLC03* TCLCOUT CLC output time — OS18 — — (Note 1) — OS19 — — (Note 1) — 32 FOSC MHz Rise Time Fall Time CLC04* FCLCMAX CLC maximum switching frequency * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Table 35-10 for OS17, OS18 and OS19 rise and fall times.  2015-2019 Microchip Technology Inc. DS40001799F-page 413 PIC16(L)F18313/18323 FIGURE 35-15: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 35-4 for Load conditions. TABLE 35-20: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Max. Units Conditions US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid — 80 ns 3.0V  VDD  5.5V — 100 ns 1.8V  VDD  5.5V US121 TCKRF Clock out rise time and fall time (Master mode) — 45 ns 3.0V  VDD  5.5V — 50 ns 1.8V  VDD  5.5V US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V — 50 ns 1.8V  VDD  5.5V FIGURE 35-16: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 35-4 for Load conditions. TABLE 35-21: EUSART SYNCHRONOUS RECEIVE CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-setup before CK  (DT hold time) US126 TCKL2DTL Data-hold after CK  (DT hold time)  2015-2019 Microchip Technology Inc. Min. Max. Units 10 — ns 15 — ns Conditions DS40001799F-page 414 PIC16(L)F18313/18323 FIGURE 35-17: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 35-4 for Load conditions. FIGURE 35-18: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 SP78 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 35-4 for Load conditions.  2015-2019 Microchip Technology Inc. DS40001799F-page 415 PIC16(L)F18313/18323 FIGURE 35-19: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: SP73 Refer to Figure 35-4 for Load conditions. FIGURE 35-20: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 35-4 for Load conditions.  2015-2019 Microchip Technology Inc. DS40001799F-page 416 PIC16(L)F18313/18323 TABLE 35-22: SPI MODE CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ.† Max. Units Conditions SP70* TSSL2SCH, TSSL2SCL SS to SCK or SCK input 2.25*TCY — — ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 — — ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 — — ns SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  VDD  5.5V — 25 50 ns 1.8V  VDD  5.5V SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) — 10 25 ns 3.0V  VDD  5.5V — 25 50 ns 1.8V  VDD  5.5V SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge — — 50 ns 3.0V  VDD  5.5V 1.8V  VDD  5.5V SP81* TDOV2SCH, SDO data output setup to SCK TDOV2SCL edge SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, TSCL2SSH SS after SCK edge — — 145 ns 1 Tcy — — ns — — 50 ns 1.5 TCY + 40 — — ns * These parameters are characterized but not tested. † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2015-2019 Microchip Technology Inc. DS40001799F-page 417 PIC16(L)F18313/18323 FIGURE 35-21: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 35-4 for Load conditions. TABLE 35-23: I2C BUS START/STOP BITS CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Start condition 100 kHz mode Setup time Start condition Typ. Max. Units SP90* TSU:STA SP91* THD:STA Hold time 400 kHz mode 600 — — SP92* TSU:STO Stop condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — SP93 THD:STO Stop condition 100 kHz mode 4000 — — 400 kHz mode 600 — — Hold time * 4700 — — 400 kHz mode 600 — — 100 kHz mode 4000 — — Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 35-22: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 35-4 for Load conditions.  2015-2019 Microchip Technology Inc. DS40001799F-page 418 PIC16(L)F18313/18323 TABLE 35-24: I2C BUS DATA CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. SP100* Symbol THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module SP102* SP103* SP106* SP107* TR TF THD:DAT TSU:DAT SP109* TAA SP110* TBUF 1.5TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode — 250 ns 400 kHz mode 20 + 0.1CB 250 ns Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start SP111 CB * Note 1: These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 2:  2015-2019 Microchip Technology Inc. DS40001799F-page 419 PIC16(L)F18313/18323 36.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range.  2015-2019 Microchip Technology Inc. DS40001799F-page 420 PIC16(L)F18313/18323 500 500 450 450 400 400 350 350 Typical IDD (µA) Max 300 IDD (µA) Max 250 Typical 300 250 200 200 150 150 100 100 Max: 85°C + 3ı Typical: 25°C 50 Max: 85°C + 3ı Typical: 25°C 50 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-1: IDD, XT Oscillator, 4 MHz, PIC16LF18313/18323 Only FIGURE 36-2: IDD, XT Oscillator, 4 MHz, PIC16F18313/18323 Only 3.0 3.0 2.5 2.5 Max Max 2.0 2.0 IDD (mA) IDD (mA) Typical Typical 1.5 1.0 1.5 1.0 Max: 85°C + 3ı Typical: 25°C 0.5 Max: 85°C + 3ı Typical: 25°C 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-3: IDD, HS Oscillator, 32 MHz, PIC16LF18313/18323 Only FIGURE 36-4: IDD, HS Oscillator, 32 MHz, PIC16F18313/18323 Only 3.0 3.0 Max Max 2.5 2.5 2.0 2.0 Typical IDD (mA) IDD (mA) Typical 1.5 1.5 1.0 1.0 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 0.5 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-5: IDD, HFINTOSC Mode, FOSC = 32 MHz, PIC16LF18313/18323 Only DS40001799F-page 421 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-6: IDD, HFINTOSC Mode, FOSC = 32 MHz, PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 1.8 1.8 1.6 1.6 Max Max 1.4 1.4 1.2 Typical Typical 1.0 IDD (mA) IDD (mA) 1.2 0.8 0.6 1.0 0.8 0.6 0.4 Max: 85°C + 3ı Typical: 25°C 0.4 0.2 Max: 85°C + 3ı Typical: 25°C 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0.0 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-7: IDD, HFINTOSC Mode, FOSC = 16 MHz, PIC16LF18313/18323 Only FIGURE 36-8: IDD, HFINTOSC Mode, FOSC = 16 MHz, PIC16F18313/18323 Only 1,200 1,200 1,000 1,000 Max Max 600 800 IDD (µA) IDD (µA) 800 Typical Typical 600 400 400 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 200 200 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 36-9: IDD, HFINTOSC Idle Mode, FOSC = 16 MHz, PIC16LF18313/18323 Only FIGURE 36-10: IDD, HFINTOSC Idle Mode, FOSC = 16 MHz, PIC16F18313/18323 Only 1,200 1,200 1,000 1,000 Max Max 800 Typical 600 IDD (µA) IDD (µA) 800 Typical 400 600 400 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 200 200 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VDD (V) FIGURE 36-11: IDD, HFINTOSC DOZE Mode, FOSC = 16 MHz, PIC16LF18313/18323 Only  2015-2019 Microchip Technology Inc. 3.4 3.6 3.8 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-12: IDD, HFINTOSC DOZE Mode, FOSC = 16 MHz, PIC16F18313/18323 Only DS40001799F-page 422 PIC16(L)F18313/18323 1.0 Max: 85°C + 3ı Typical: 25°C 0.9 0.8 IPD (µA) A) 0.7 0.6 Max. 0.5 0.4 Typical 0.3 0.2 0.1 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 3.6 3.8 VDD (V) FIGURE 36-13: IPD BASE, Low-Power Sleep Mode, PIC16LF18313/18323 Only FIGURE 36-14: IPD, Watchdog Timer (WDT), PIC16LF18313/18323 Only 60 1.2 Max: 85°C + 3 M 3ı Typical: 25°C 55 1.0 Max. 50 45 Typical IPD (µA) A) IPD (µA) µA) 0.8 0.6 Max. 40 Typical 35 0.4 30 Max: 85°C + 3ı Typical: 25°C 0.2 25 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 20 6.0 1.6 1.8 2.0 2.2 2.4 VDD (V) 2.6 2.8 3.0 3.2 3.4 VDD (V) FIGURE 36-15: IPD, Watchdog Timer (WDT), PIC16F18313/18323 Only FIGURE 36-16: IPD, Fixed Voltage Reference (FVR), PIC16LF18313/18323 Only 14 60 Max: 85°C + 3ı Typical: 25°C 55 13 50 Max. IPD D (µA) IPD (µA) µA) 12 Max. 45 40 11 Typical 35 10 Typical 30 Max: 85°C + 3ı Typical: 25°C 25 9 20 8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 36-17: IPD, Fixed Voltage Reference (FVR), PIC16F18313/18323 Only DS40001799F-page 423 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-18: IPD, Brown-out Reset (BOR), BORV = 1, PIC16LF18313/18323 Only  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 0.5 16 Max: 85°C + 3ı Typical: 25°C 14 0.4 Max. Max. 12 IPD (µA) µA) IPD (µA) A) 0.3 Typical 10 0.2 8 Typical Max: 85 85°C C + 3ı Typical: 25°C 0.1 6 0 4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 36-19: IPD, Brown-out Reset (BOR), BORV = 1, PIC16F18313/18323 Only FIGURE 36-20: IPD, Low-Power Brown-out Reset (LPBOR = 0), PIC16LF18313/18323 Only 40 0.8 38 0.7 Max. Max. 36 0.6 34 IPD (µA) µA) IPD (µA) µA) 0.5 Typical 0.4 32 Typical 30 28 0.3 26 Max: 85 85°C C + 3ı Typical: 25°C 0.2 24 0.1 01 Max: 85°C + 3ı Typical: 25°C 22 20 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 36-21: IPD, Low-Power Brown-out Reset (LPBOR = 0), PIC16F18313/18323 Only FIGURE 36-22: IPD, Comparator, PIC16LF18313/18323 Only 30 40 Max Max. Max: 85°C + 3ı Typical: 25°C 35 25 Max. 30 Typical 20 IPD (µA) µA) IPD (µA) µA) 25 20 15 Typical 15 10 10 5 Max: 85°C + 3ı Typical: 25°C 5 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) FIGURE 36-23: IPD, Comparator, PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. 5.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-24: IPD BASE, 01, PIC16F18313/18323 Only DS40001799F-page 424 PIC16(L)F18313/18323 1 0.8 2.0% 0.7 1.0% 0.6 Max. 0.5 0.4 Max. 0.0% Error (%) IPD (µA) µA) 3.0% Max: 85°C + 3ı Typical: 25°C 0.9 Typical Typical -1.0% -2.0% Min. 0.3 -3.0% 0.2 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C -4.0% 0.1 Min: Typical - 3ı (-40°C to 125°C) -5.0% 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 36-25: IPD BASE, 11, PIC16F18313/18323 Only FIGURE 36-26: HFINTOSC Typical Frequency Error, PIC16LF18313/18323 Only 1.5% 2.0% Max. 1.0% 1.0% Max. Typical 0.5% 0.0% Error (%) Error (%) Typical -1.0% Min. -2.0% 0.0% -0.5% Min. -3.0% -1.0% Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) -4.0% -5.0% -2.0% 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 -50 VDD (V) 50 100 150 FIGURE 36-28: HFINTOSC Frequency Error VDD = 3V, All devices 36,000 36,000 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) Max: Typical + 3ı (-40°C to 125°C) 35,000 Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) 34,000 34,000 33,000 33,000 Max. Frequency (Hz) Frequency (Hz) 0 Temperature (°C) FIGURE 36-27: HFINTOSC Typical Frequency Error, PIC16F18313/18323 Only 35,000 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) -1.5% 32,000 Typical 31,000 30,000 Max. 32,000 31,000 Typical 30,000 Min. Min. 29,000 29,000 28,000 28,000 1.7 2.0 2.3 2.6 2.9 3.2 3.5 VDD (V) FIGURE 36-29: LFINTOSC Frequency, PIC16LF18313/18323 Only DS40001799F-page 425 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) FIGURE 36-30: LFINTOSC Frequency, PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 180 300 Max. 160 250 Max. Min. Pull-Up Current ent (µA) (µA Pull-Up ull-Up C Current (µA) Typical 200 Min. 150 100 120 100 80 60 Max: Typical + 3ı (-40°C to 125°C) 40 Max: Typical + 3ı (-40°C to 125°C) 50 Typical 140 Typical: Statistical mean @ 25°C Typical: Statistical mean @ 25°C 20 Min: Typical - 3ı (-40°C to 125°C) Min: Typical - 3ı (-40°C to 125°C) 0 0 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 VDD (V) VDD (V) FIGURE 36-31: Weak Pull-Up Current, PIC16F18313/18323 Only FIGURE 36-32: Weak Pull-Up Current, PIC16LF18313/18323 Only 6 3 Graph represents 3ı Limits Graph represents 3ı Limits 5 -40°C 4 2 VOL (V) VOH (V) Typical 3 125°C 125°C 2 1 Typical 1 -40°C 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 0 10 20 30 IOL (mA) IOH (mA) FIGURE 36-33: VOH vs. IOH Over Temperature, VDD = 5.5V, PIC16F18313/18323 Only 40 50 60 FIGURE 36-34: VOL vs. IOL Over Temperature, VDD = 5.5V, PIC16F18313/18323 Only 3.0 3.5 Graph represents 3ı Limits Graph represents 3ı Limits 3.0 2.5 -40°C 125°C 2.5 Typical 2.0 VOL (V) VOH (V) 2.0 Typical 1.5 1.5 125°C 1.0 1.0 -40°C 0.5 0.5 0.0 0.0 -30 -25 -20 -15 -10 IOH (mA) FIGURE 36-35: VOH vs. IOH Over Temperature, VDD = 3.0V, All devices  2015-2019 Microchip Technology Inc. -5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 IOL (mA) FIGURE 36-36: VOL vs. IOL Over Temperature, VDD = 3.0V, All devices DS40001799F-page 426 PIC16(L)F18313/18323 2.0 1.8 Graph represents 3ı Limits 1.8 Graph represents 3ı Limits 1.6 1.6 1.4 1.4 1.2 Typical 125°C VOL (V) VOH (V) -40°C 1.2 125°C 1.0 Typical -40°C 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0 1 2 3 4 5 6 7 8 FIGURE 36-38: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF18313/18323 Only 70.0 3.00 Max: Typical + 3ı Typical: Statistical mean Min: Typical - 3ı 2.95 60.0 2.90 2.85 50.0 Max. 2.75 Max. Voltage (mV) 2.80 Voltage (V) 10 11 12 13 14 15 16 17 18 19 20 IOL (mA) IOH (mA) FIGURE 36-37: VOH vs. IOH Over Temperature, VDD = 1.8V, PIC16LF18313/18323 Only Typical 2.70 2.65 Min. 2.60 40.0 Typical 30.0 20.0 2.55 2.50 Max: Typical + 3ı Typical: Statistical mean Min: Typical - 3ı 2.45 Min. 10.0 0.0 2.40 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 Temperature (°C) 20 40 60 80 100 120 140 Temperature (°C) FIGURE 36-39: Brown-out Reset Voltage, High Trip Point, (BORV = 0), All devices FIGURE 36-40: Brown-out Reset Hysteresis, Low Trip Point, (BORV = 0), All devices 2.00 40.0 Max. 35.0 1.95 30.0 Voltage (mV) Typical Voltage (V) 9 1.90 Min. 1.85 Max. 25.0 Typical 20.0 Min. 15.0 10.0 Max: Typical + 3ı Typical: Statistical mean Min: Typical - 3ı Max: Typical yp + 3ı Typical: Statistical mean Min: Typical - 3ı 5.0 1.80 00 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 36-41: Brown-out Reset Voltage, Trip Point, (BORV = 1), PIC16LF18313/18323 Only DS40001799F-page 427 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 36-42: Brown-out Reset Hysteresis, Trip Point, (BORV = 1), PIC16LF18313/18323 Only  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 2.70 50.0 2.65 45.0 Max: Typical + 3ı Typical: Statistical mean Min: Typical - 3ı 2.60 2.50 Max. 35.0 Typical Voltage (mV) Voltage (V) 40.0 Max. 2.55 2.45 Min. 2.40 30.0 Typical 25.0 2.35 Min. 20.0 2.30 Max: Typical + 3ı Typical: Statistical mean Min: Typical - 3ı 2.25 15.0 2.20 -60 -40 -20 0 20 40 60 80 100 120 10.0 140 -60 -40 -20 0 20 Temperature (°C) 40 FIGURE 36-43: Brown-out Reset Voltage, Trip Point, (BORV = 1), PIC16F18313/18323 Only 80 100 120 140 FIGURE 36-44: Brown-out Reset Hysteresis, Trip Point, (BORV = 1), PIC16F18313/18323 Only 2.60 50 Max: Typical + 3ı Typical: Statistical mean Min: Typical - 3ı 2.50 Max: Typical + 3ı Typical: Statistical mean Min: Typical - 3ı 45 40 2.40 Max. 35 2.30 Max. 30 Voltage (mV) Voltage (V) 60 Temperature (°C) 2.20 Typical 2.10 2.00 Typical 25 20 Min. 15 Min. 10 1.90 5 1.80 0 -60 1.70 -60 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 Temperature (°C) 60 80 100 120 140 Temperature (°C) FIGURE 36-45: LPBOR Reset Voltage, PIC16LF18313/18323 Only FIGURE 36-46: LPBOR Reset Hysteresis, PIC16LF18313/18323 Only 7 5.0 4.5 6 Max. 4.0 5 3.5 3.0 Time (µs) Time (µs) 40 140 Typical 2.5 2.0 1.5 Max. 4 Typical 3 2 1.0 Max: Typical + 3ı @ 125°C 0.5 Max: Typical + 3ı @ 125°C 1 Typical: Statistical mean @ 25°C Typical: Statistical mean @ 25°C 0.0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) FIGURE 36-47: BOR Response Time, PIC16LF18313/18323 Only  2015-2019 Microchip Technology Inc. 3.7 0 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) FIGURE 36-48: BOR Response Time, PIC16F18313/18323 Only DS40001799F-page 428 1.0 1.0 0.5 0.5 DNL (LSb) DNL (LSb) PIC16(L)F18313/18323 0.0 0.0 -0.5 -0.5 -1.0 -1.0 0 128 256 384 512 640 768 896 0 1024 128 256 384 1.0 1.0 0.5 0.5 0.0 768 896 1024 0.0 -0.5 -0.5 -1.0 -1.0 0 128 256 384 512 640 768 896 0 1024 128 256 384 512 640 768 896 1024 Output Code Output Code FIGURE 36-51: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 8 µs, 25°C, All devices FIGURE 36-52: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 1 µs, 25°C, All devices 2.0 1.0 2.0 1.0 1.5 1.5 1.0 1.0 0.5 0.5 0.5 0.5 INL (LSb) DNL (LSb) INL (LSb) DNL (LSb) 640 FIGURE 36-50: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 4 µs, 25°C, All devices INL (LSb) DNL (LSb) FIGURE 36-49: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 1 µs, 25°C, All devices 0.0 -0.5 0.0 -1.0 0.0 -0.5 0.0 -1.0 -1.5 -1.5 -2.0 -0.5 512 Output Code Output Code 0 512 1024 1536 2048 2560 3072 3584 4096 -2.0 -0.5 0 512 1024 1536 2048 2560 3072 3584 4096 640 768 896 1024 Output Code Output Code -1.0 -1.0 0 128 256 384 512 640 768 896 Output Code FIGURE 36-53: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 4 µs, 25°C, All devices DS40001799F-page 429 1024 0 128 256 384 512 Output Code FIGURE 36-54: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 8 µs, 25°C, All devices  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 1.0 1.0 0.5 Max 25°C Max 25°C Min 25°C Min 25°C Max -40°C 0.0 Min -40°C Max 85°C INL (LSb) DNL (LSb) 0.5 Max -40°C 0.0 Min -40°C Max 85°C Min 85°C Min 85°C -0.5 -0.5 -1.0 -1.0 0.5 05 0.8 08 1.0 2.0 0 0 TAD (µs) 4.0 0 0.5 8.0 80 0.8 1.0 2.0 4.0 8.0 TAD (µs) FIGURE 36-55: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, All devices FIGURE 36-56: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, All devices 1.0 2.0 1.5 0.5 1.0 Max 85°C 0.5 Max 25°C Max -40°C 0.0 Min 85°C Min 25°C INL(LSb) DNL(LSb) Max 85°C Max 25°C Max -40°C 0.0 Min 85°C -0.5 Min -40°C Min 25°C Min -40°C -1.0 -0.5 -1.5 -2.0 -1.0 1.8 1.8 8 2.3 3 2.5 5 2.3 3.0 30 2.5 3.0 VREF (V) VREF (V) FIGURE 36-57: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 µs, All devices FIGURE 36-58: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 µs, All devices g 6 3.0 5 2.5 4 2.0 Max 85°C 1.5 2 Max 25°C 1.0 1 Max -40°C 0 Min 85°C -1 Min 25°C -2 Min -40°C Max 85°C Offset Error (LSb) Gain Error (LSb) 3 Max -40°C 0.0 Min 85°C -0.5 Min 25°C -1.0 -3 -1.5 -4 -2.0 -5 Max 25°C 0.5 Min -40°C -2.5 -6 1.8 2.3 2.5 3.0 VREF (V) FIGURE 36-59: ADC 10-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, TAD = 1 µs, All devices  2015-2019 Microchip Technology Inc. -3.0 1.8 2.3 2.5 3.0 VREF (V) FIGURE 36-60: ADC 10-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, TAD = 1 µs, All devices DS40001799F-page 430 PIC16(L)F18313/18323 , te g , μ , 1.0 1.0 0.5 0.5 Max 85°C Max 25°C Max -40°C 0.0 INL(LSb) DNL(LSb) Max 85°C Max 25°C Max -40°C 0.0 Min 85°C Min 85°C Min 25°C Min 25°C -0.5 Min -40°C Min -40°C -0.5 -1.0 1.8 2.3 2.5 3.0 VREF (V) -1.0 1.8 2.3 2.5 3.0 VREF ((V)) FIGURE 36-61: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 4 µs, All devices FIGURE 36-62: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 4 µs, All devices 1.0 6 5 3 Max 85°C 2 Max 25°C 1 0.5 Offset Error (LSb) Gain Error (LSb) 4 Max -40°C 0 Min 85°C -1 -2 Min 25°C -3 Min -40°C Max 85°C Max 25°C Max -40°C 0.0 Min 85°C Min 25°C Min -40°C -4 -0.5 -5 -6 1.8 2.3 2.5 3.0 VREF (V) -1.0 1.8 2.3 2.5 3.0 VREF (V) FIGURE 36-63: ADC 10-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, TAD = 4 µs, All devices FIGURE 36-64: ADC 10-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, TAD = 4 µs, All devices g 2.0 2.0 1.5 1.5 1.0 Max. Offset Error (LSb) Gain Error (LSb) 1.0 0.5 Typical 0.0 -0.5 Min. -1.0 Max. 0.5 0.0 Typical -0.5 -1.0 Min. -1.5 -1.5 -2.0 0.5 0.8 1.0 2.0 4.0 TAD (µs) 8.0 -2.0 0.5 FIGURE 36-65: ADC 10-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, VREF = 3.0V, -40°C to 85°C, All devices DS40001799F-page 431 0.8 1.0 2.0 4.0 8.0 TAD (µs) FIGURE 36-66: ADC 10-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, VREF = 3.0V, -40°C to 85°C, All devices  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 4.0 5.0 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) 4.5 3.5 Max. 4.0 3.0 Max. 2.5 3.0 Time (µs) Time (µs) 3.5 2.5 Typical Typical 2.0 2.0 1.5 Min. Min. 1.5 1.0 Max: Typical + 3ı (-40°C to 125°C) 1.0 0.5 Typical: Statistical mean @ 25°C 0.5 Min: Typical - 3ı (-40°C to 125°C) 0.0 0.0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 2.2 3.7 2.4 2.6 2.8 3.0 3.2 3.4 3.6 FIGURE 36-67: ADC RC Oscillator period, PIC16LF18313/18323 Only 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) VDD (V) FIGURE 36-68: ADC RC Oscillator period, PIC16F18313/18323 Only 0.00 0.025 -40°C 0.020 -0.05 25°C 85°C 0.015 -0.10 125°C -0.15 INL (LSb) DNL (LSb) 0.010 0.005 0.000 -0.20 -0.25 -0.005 -0.30 -0.010 -0.35 -0.015 -0.40 -0.020 -0.45 -40°C 25°C 85°C 125°C 0 16 32 48 64 80 96 0 112 128 144 160 176 192 208 224 240 16 32 48 64 80 FIGURE 36-69: Typical DAC DNL Error, VDD = 3.0V, VREF = External 3V, All devices 96 112 128 144 160 176 192 208 224 240 Output Code Output Code FIGURE 36-70: Typical DAC INL Error, VDD = 3.0V, VREF = External 3V, All devices 0.020 0.00 0.015 -40°C 25°C -0.05 85°C 125°C -0.10 0.010 INL (LSb) DNL (LSb) -0.15 0.005 0.000 -0.20 -0.25 -0.30 -0.005 -40°C -0.35 25°C -0.010 85°C -0.40 125°C -0.015 -0.45 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 36-71: Typical DAC DNL Error, VDD = 5.0V, VREF = External 5V, PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 36-72: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V, PIC16F18313/18323 Only DS40001799F-page 432 PIC16(L)F18313/18323 0.4 0.45 VREF = INT. VDD 0.4 VREF = EXT. 1.8V DNL (LSb) AbsoluteAbsolute DNL (LSb) 0.35 VREF = EXT. 2.0V 0.3 0.3 VREF = EXT. 3.0V 0.25 Vref = Int. Vdd Vref = Ext. 1.8V 0.2 Vref = Ext. 2.0V 0.15 0.2 Vref = Ext. 3.0V 0.1 0.05 0 0.1 -50 0 50 Temperature (°C) 100 150 0.0 -60 FIGURE 36-73: DAC INL Error, VDD = 3.0V, PIC16LF18313/18323 Only -20 0 40 60 80 100 120 140 FIGURE 36-74: Absolute Value of DAC DNL Error, VDD = 3.0V, VREF = VDD, All devices VREF = INT. VDD VREF = Int. VDD VREF = EXT. 1.8V -2.3 0.88 0.25 -2.5 AbsoluteAbsolute DNL (LSb) DNL (LSb) VREF = EXT. 2.0V VREF = EXT. 3.0V -40 -2.7 0.86 25 -2.9 85 0.84 -3.1 125 -3.3 0.82 -3.5 0.0 VREF = Ext. 1.8V 0.26 0.2 VREF = Ext. 2.0V VREF = Ext. 3.0V -40 VREF = Ext. 5.0V 0.15 0.22 25 85 0.1 125 0.05 0.18 0 1.0 2.0 3.0 Temperature (°C) 0.80 4.0 5.0 0.0 1.0 2.0 0.14 0.78 3.0 4.0 Temperature (°C) 5.0 6.0 0.10 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 FIGURE 36-75: Absolute Value of DAC INL Error, VDD = 3.0V, VREF = VDD, All devices 0.90 -2.1 80 100 120 41 VREF = Ext. 5.0V -40 -2.7 0.86 25 -2.9 85 0.84 -3.1 125 Hysteresis (mV) VREF = Ext. 3.0V 39 37 35 33 31 1.0 2.0 0.80 3.0 4.0 Temperature (°C) 140 43 VREF = Ext. 2.0V -3.3 0.82 -3.5 0.0 60 45 VREF = Ext. 1.8V -2.5 40 FIGURE 36-76: Absolute Value of DAC DNL Error, VDD = 5.0V, VREF = VDD, PIC16F18313/18323 Only VREF = Int. VDD -2.3 0.88 20 Temperature (°C) ( C) Temperature (°C) ( C) AbsoluteAbsolute INL (LSb)INL (LSb) 20 Temperature p (°C) ( ) 0.30 0.3 0.90 -2.1 AbsoluteAbsolute INL (LSb)INL (LSb) -40 5.0 6.0 -40°C 25°C 29 125° 125 27 85°C 25 0.0 0.78 -60 -40 -20 0 20 40 60 80 100 120 FIGURE 36-77: Absolute Value of DAC INL Error, VDD = 5.0V, VREF = VDD, PIC16F18313/18323 Only DS40001799F-page 433 0.5 1.0 1.5 2.0 2.5 3.0 3.5 140 Temperature (°C) Common Mode Voltage (V) FIGURE 36-78: Comparator Hysteresis, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values, All devices  2015-2019 Microchip Technology Inc. 30 30 25 25 20 20 15 15 Offset Voltage (mV) Offset Voltage (mV) PIC16(L)F18313/18323 10 Max. 5 0 10 Max. 5 0 -5 -5 Min. Min. -10 -10 -15 -15 -20 -20 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 36-79: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25°C, All devices FIGURE 36-80: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values from -40°C to 125°C, All devices 50 30 25 20 40 Hysteresis (mV) Hysteresis (mV) 45 35 30 10 Max. 5 0 -5 -40°C Min. 25°C 25 15 -10 125° -15 85° 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 Common Mode Voltage (V) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Voltage (V) FIGURE 36-82: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values at 25°C, PIC16F18313/18323 Only FIGURE 36-81: Comparator Hysteresis, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values, PIC16F18313/18323 Only 140 40 Max: Typical + 3ı (-40°C to +125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 120 30 Time (ns) Offset Voltage (mV) 100 20 10 Max. 80 Max. 60 Typical 0 40 Min. Min. -10 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Voltage (V) FIGURE 36-83: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values from -40°C to 125°C, PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. 0 1.7 2.0 2.3 2.6 2.9 3.2 3.5 VDD (V) FIGURE 36-84: Comparator Response Time Over Voltage, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values PIC16LF18313/18323 Only DS40001799F-page 434 PIC16(L)F18313/18323 90 300 Max: Typical + 3ı (-40°C to +125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 80 250 70 Max. Max. 200 50 Time (ns) Time (ns) 60 Typical 40 30 150 Typical 100 Min. 20 50 Max: Typical + 3ı @ 125°C 10 Typical: Statistical mean @ 25°C 0 0 2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 1.7 1.9 2.1 2.3 2.5 FIGURE 36-85: Comparator Response Time Over Voltage, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values PIC16F18313/18323 Only 2.7 2.9 3.1 3.3 3.5 3.7 VDD (V) VDD (V) FIGURE 36-86: Comparator Response Time Falling edge, PIC16LF18313/18323 Only 250 700 600 200 Max. Max. Typical 100 Time (ns) Time (ns) 500 150 400 Typical 300 200 50 100 Max: Typical + 3ı @ 125°C Typical: Statistical mean @ 25°C Max: Typical + 3ı @ 125°C Typical: Statistical mean @ 25°C 0 0 1.7 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 1.9 2.1 2.3 2.5 FIGURE 36-87: Comparator Response Time Falling edge, PIC16F18313/18323 Only 2.7 2.9 3.1 3.3 3.5 3.7 VDD (V) VDD (V) FIGURE 36-88: Comparator Response Time Rising edge, PIC16LF18313/18323 Only 900 70 800 60 700 Max. Max. 50 Time (µs) Time (ns) 600 500 400 40 Typical 300 Typical 30 200 100 20 Max: Typical + 3ı @ 125°C Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Typical: Statistical mean @ 25°C 0 10 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) FIGURE 36-89: Comparator Response Time Rising edge, PIC16F18313/18323 Only DS40001799F-page 435 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-90: Bandgap Ready Time, PIC16LF18313/18323 Only  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 1.1% 1.0% Typical 125°C 0.9% 0.8% Typical 85°C Error (%) 0.7% 0.6% Typical 25°C 0.5% 0.4% 0.3% Typical -40°C 0.2% 0.1% 0.0% 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 VDD (V) FIGURE 36-91: FVR Stabilization Period, PIC16LF18313/18323 Only FIGURE 36-92: Typical FVR Voltage (1x), PIC16LF18313/18323 Only 1.2% 1.0% Typical 125°C Typical 125°C 1.0% 0.8% 0.6% Error (%) Error (%) 0.6% Typical 85°C 0.8% Typical 25°C Typical 85°C 0.4% Typical 25°C 0.2% Typical -40°C 0.4% 0.0% Typical -40°C 0.2% -0.2% 0.0% -0.4% 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 VDD (V) VDD (V) FIGURE 36-93: FVR Voltage Error (1x), PIC16F18313/18323 Only FIGURE 36-94: FVR Voltage Error (2x), PIC16LF18313/18323 Only 1.0% 1.0% Typical 125°C 0.8% 0.8% Typical 125°C Error (%) Typical 85°C 0.6% Error (%) 0.6% Typical 25°C 0.4% Typical 85°C 0.4% 0.2% Typical 25°C 0.2% Typical -40°C 0.0% Typical -40°C 0.0% -0.2% -0.2% 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 VDD (V) FIGURE 36-95: FVR Voltage Error (2x), PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. 5.6 -0.4% 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 VDD (V) FIGURE 36-96: FVR Voltage Error (4x), PIC16F18313/18323 Only DS40001799F-page 436 PIC16(L)F18313/18323 gg 2.5 4.0 Max. 3.5 2.0 Typical Max. Min. Voltage oltage (V) Voltage (V) 3.0 Typical 2.5 2.0 1.5 Min. 10 1.0 1.5 Max: Typical + 3ı (-40°C to 125°C) 0.5 1.0 Typical: Statistical mean @ 25°C Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) 0.5 Min: Typical - 3ı (-40°C to 125°C) 0.0 1.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 6.0 3.5 4.0 4.5 5.0 5.5 VDD (V) VDD (V) FIGURE 36-97: All devices Schmitt Trigger High Values, FIGURE 36-98: All devices Schmitt Trigger Low Values, p 1.8 50 1.6 1.2 Max. 45 Max: Typical + 3ı (-40°C to 125°C) Typical yp 40 Typical: y Statistical mean @ 25°C 35 1.0 0.8 Time (ns) Voltage age (V) 1.4 Min. 0.6 0.4 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 25 C Min: Typical - 3ı (-40°C to 125°C) 0.2 0.0 30 Max. 25 20 15 Typical 10 15 1.5 2.0 20 2.5 25 3.0 30 3.5 35 4.0 40 4.5 45 5.0 50 5.5 55 5 VDD (V) 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-99: devices TTL Trip Thresholds, All FIGURE 36-100: Rise Time, Slew Rate Control Enabled, All devices 60 30 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 50 40 20 Time me (ns) Time me (ns) (ns Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 25 Max. 30 20 15 Max. 10 Typical 10 5 0 0 Typical 1 5 1.5 20 2.0 25 2.5 30 3.0 35 3.5 40 4.0 45 4.5 50 5.0 55 5.5 60 6.0 VDD (V) FIGURE 36-101: Fall Time, Slew Rate Control Enabled, All devices DS40001799F-page 437 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-102: Rise Time, Slew Rate Control Disabled, All devices  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 , 4.00% Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 20 3.00% Max: Typical + 3ı (-40°C to 125°C) 18 Typical: Statistical mean @ 25°C 2.00% 16 1 00% 1.00% Error (%) Time me (ns) 14 12 10 8 Max 0.00% Min Average -1.00% Max. 6 -2.00% 4 Typical yp 2 -3.00% 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -4.00% -32 VDD (V) Min -24 -16 -8 0 8 Center 16 24 32 Max OSCTUNE Setting FIGURE 36-103: Fall Time, Slew Rate Control Disabled, All devices FIGURE 36-104: OSCTUNE Center Frequency, PIC16LF18313/18323 Only 1.64 1.80 1.60 Max: Typical + 3ı 1.55 Min: Typical - 3ı Max. 1.45 Typical 1.40 Typical: Statistical mean Min: Typical - 3ı 1.62 Voltage (V) Voltage (V) 1.50 Voltage (V) Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı Max: Typical + 3ı 1.63 1.75 Typical: Statistical mean 1.35 1.70 1.61 Max. 1.6 1.65 Typical 1.59 1.60 1.30 Min. 1.58 Min. -40 -20 0 20 1.55 1.25 1.20 40 60 80 100 120 Temperature (°C) 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 Temperature (°C) FIGURE 36-105: All devices 40 60 80 100 120 140 Temperature (°C) POR Release Voltage, FIGURE 36-106: POR Rearm Voltage, Normal Power Mode, PIC16F18313/18323 Only 75 74 73 Max. 72 71 Max. 69 Time (ms) Time (ms) 70 68 Typical 66 67 Typical 65 Min. 63 Min. 64 61 62 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) 59 60 57 2.0 2.5 3.0 3.5 4.0 4.5 VDD (V) FIGURE 36-107: PWRT Period, PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-108: PWRT Period, PIC16LF18313/18323 Only DS40001799F-page 438 PIC16(L)F18313/18323 120 18 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 110 17 100 90 Max. 15 Max. 80 Time (µs) Time (µs) 16 70 Typical 60 14 50 Typical 40 13 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 30 20 12 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 36-109: Wake From Sleep, VREGPM = 0, HFINTOSC = 4 MHz, PIC16F18313/18323 Only FIGURE 36-110: ULP Wake From Sleep, VREGPM = 1, HFINTOSC = 4 MHz, PIC16F18313/18323 Only 120 28 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 27 110 100 26 Max. 24 Typical 80 23 70 22 60 21 50 20 40 1.5 2.0 2.5 3.0 3.5 Max. 90 Time (µs) Time (µs) 25 4.0 4.5 5.0 5.5 Typical Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 1.5 6.0 2.0 2.5 3.0 FIGURE 36-111: Wake From Sleep, VREGPM = 1, HFINTOSC = 16 MHz, PIC16F18313/18323 Only 4.0 4.5 5.0 5.5 6.0 FIGURE 36-112: ULP Wake From Sleep, VREGPM = 1, HFINTOSC = 16 MHz, PIC16F18313/18323 Only 700 700 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 650 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C 650 600 600 Max. 550 550 Max. 500 450 Time (µs) Time (µs) 3.5 VDD (V) VDD (V) 500 450 Typical 400 350 Typical 400 350 300 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) FIGURE 36-113: Wake From Sleep, VREGPM = 1, LFINTOSC, PIC16F18313/18323 Only DS40001799F-page 439 300 1.7 2.2 2.7 3.2 3.7 VDD (V) FIGURE 36-114: Wake From Sleep, LFINTOSC, PIC16LF18313/18323 Only  2015-2019 Microchip Technology Inc. PIC16(L)F18313/18323 4.2 4.2 Max. Max. 4.1 4.1 Typical Time (ms) Time (ms) Typical 4.0 4.0 Min. Min. 3.9 3.9 Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) Max: Typical + 3ı (-40°C to 125°C) Typical: Statistical mean @ 25°C Min: Typical - 3ı (-40°C to 125°C) 3.8 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 36-115: WDT Time-out Period, PIC16F18313/18323 Only  2015-2019 Microchip Technology Inc. 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-116: WDT Time-out Period, PIC16LF18313/18323 Only DS40001799F-page 440 PIC16(L)F18313/18323 37.0 DEVELOPMENT SUPPORT The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software - MPLAB Xpress IDE Software - Microchip Code Configurator (MCC) • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools 37.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2015-2019 Microchip Technology Inc. DS40001799F-page 441 PIC16(L)F18313/18323 37.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 37.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 37.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 37.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2015-2019 Microchip Technology Inc. DS40001799F-page 442 PIC16(L)F18313/18323 37.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 37.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables.  2015-2019 Microchip Technology Inc. 37.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 37.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 37.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001799F-page 443 PIC16(L)F18313/18323 37.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 37.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2015-2019 Microchip Technology Inc. DS40001799F-page 444 PIC16(L)F18313/18323 38.0 PACKAGING INFORMATION 38.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN 16F18313 P e3 017 YYWW 1110 8-Lead SOIC (3.90 mm) Example 16F18313I PIC16F18313 -I/SO e3 SN e3 1110 NNN Legend: XX...X Y YY WW NNN e3 * Note: 1304017 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2015-2019 Microchip Technology Inc. DS40001799F-page 445 PIC16(L)F18313/18323 Package Marking Information (Continued) 8-Lead UDFN (3x3x0.9 mm) XXXX YYWW NNN PIN 1 14-Lead PDIP (300 mil) Example MGR0 1110 017 PIN 1 Example PIC16F18323 P e3 1304017 14-Lead SOIC (3.90 mm) Example PIC16F18323 SO e3 1304017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX YYWW NNN 16F18323  2015-2019 Microchip Technology Inc. 1304 017 DS40001799F-page 446 PIC16(L)F18313/18323 Package Marking Information (Continued) 16-Lead UQFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F18323 MV 130417 e3  2015-2019 Microchip Technology Inc. DS40001799F-page 447 PIC16(L)F18313/18323 TABLE 38-1: 8-LEAD 3x3 UDFN (RF) TOP MARKING Part Number Marking PIC16F18313 RF MGG0 PIC16LF18313 RF MGH0  2015-2019 Microchip Technology Inc. DS40001799F-page 448 PIC16(L)F18313/18323 38.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2  2015-2019 Microchip Technology Inc. DS40001799F-page 449 PIC16(L)F18313/18323 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2  2015-2019 Microchip Technology Inc. DS40001799F-page 450 PIC16(L)F18313/18323 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2019 Microchip Technology Inc. DS40001799F-page 451 PIC16(L)F18313/18323 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2019 Microchip Technology Inc. DS40001799F-page 452 PIC16(L)F18313/18323     !"#$%& '  ! "# $% &"'"" *$;  % ?@@&&&!  !@$  2015-2019 Microchip Technology Inc. DS40001799F-page 453 PIC16(L)F18313/18323 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.10 C 1 2X 2 TOP VIEW 0.10 C 0.05 C C SEATING PLANE A1 A 8X (A3) 0.05 C SIDE VIEW 0.10 C A B D2 1 2 L 0.10 C A B E2 NOTE 1 K N e 8X b 0.10 e 2 C A B BOTTOM VIEW Microchip Technology Drawing C04-254A Sheet 1 of 2  2015-2019 Microchip Technology Inc. DS40001799F-page 454 PIC16(L)F18313/18323 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 1.40 2.20 0.25 0.35 0.20 MILLIMETERS NOM 8 0.65 BSC 0.50 0.02 0.065 REF 3.00 BSC 1.50 3.00 BSC 2.30 0.30 0.45 - MAX 0.55 0.05 1.60 2.40 0.35 0.55 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-254A Sheet 2 of 2  2015-2019 Microchip Technology Inc. DS40001799F-page 455 PIC16(L)F18313/18323 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C X2 E Y2 X1 G1 G2 SILK SCREEN Y1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 Contact Pad to Contact Pad (X6) G1 Contact Pad to Center Pad (X8) G2 MIN MILLIMETERS NOM 0.65 BSC MAX 1.60 2.40 2.90 0.35 0.85 0.20 0.30 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2254A  2015-2019 Microchip Technology Inc. DS40001799F-page 456 PIC16(L)F18313/18323 *+  , $   !"# ,$ & '  ! "# $% &"'"" *$;  % ?@@&&&!  !@$ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB }" !" !" ~#!Y  ;*" ~\^ ~ ~ ~‚ ƒ G *   *  „ „ G  %%*$ $""  GG{ G] G{ |" * G G{ „ „  #%   #% †% ^  ]G ]{  %%*$†% ^G  {  ‚J   ]{ { {  *  GG{ G] G{ % $""   G G{ YG { ‡  Y G G  | „ „ } %†%  & %†% ‚J  &[ G|\ ] ' G *GJ"#%X;# !J 'Y#!#"Y %&%   [;\  " ] !" "%^G%  #%! %;"   #" " %;"   #" "" X%G` "%  !" %   ^jG{ |\?|"!"   XJ#" && #  "       & \{|  2015-2019 Microchip Technology Inc. DS40001799F-page 457 PIC16(L)F18313/18323 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2019 Microchip Technology Inc. DS40001799F-page 458 PIC16(L)F18313/18323 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2019 Microchip Technology Inc. DS40001799F-page 459 PIC16(L)F18313/18323 '  ! "# $% &"'"" *$;  % ?@@&&&!  !@$  2015-2019 Microchip Technology Inc. DS40001799F-page 460 PIC16(L)F18313/18323 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2019 Microchip Technology Inc. DS40001799F-page 461 PIC16(L)F18313/18323 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2019 Microchip Technology Inc. DS40001799F-page 462 PIC16(L)F18313/18323 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2015-2019 Microchip Technology Inc. DS40001799F-page 463 PIC16(L)F18313/18323 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C SEATING PLANE A1 0.10 C C A 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N 16X b 0.10 L e C A B BOTTOM VIEW Microchip Technology Drawing C04-257A Sheet 1 of 2  2015-2019 Microchip Technology Inc. DS40001799F-page 464 PIC16(L)F18313/18323 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.50 2.50 0.25 0.30 0.20 MILLIMETERS NOM 16 0.65 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.60 4.00 BSC 2.60 0.30 0.40 - MAX 0.55 0.05 2.70 2.70 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-257A Sheet 2 of 2  2015-2019 Microchip Technology Inc. DS40001799F-page 465 PIC16(L)F18313/18323 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 16 1 2 C2 Y2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X16) X1 Contact Pad Length (X16) Y1 MIN MILLIMETERS NOM 0.65 BSC MAX 2.70 2.70 4.00 4.00 0.35 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2257A  2015-2019 Microchip Technology Inc. DS40001799F-page 466 PIC16(L)F18313/18323 APPENDIX A: DATA SHEET REVISION HISTORY Revision F (09/2019) Updated Register 5-5 and Table 35-6. Revision E (10/2018) Updated Table 35-8 (Internal Oscillator Parameters). Other minor corrections. Revision D (10/2017) Updated Register 30-4; Section 30.6; and Tables 6-5, 11-2, and 35-2. Revision C (07/2017) Minor electrical specs updated, Char Graphs updated for IDD Revision B (12/2016) Minor updates brought to Table 1-1; Table 1-2; Table 1-3; Added new Chapter 2 “Guidelines for Getting Started with PIC16(L)F183XX Microcontrollers”; Updated Figure 3-1; Added Section 4.1.1.3 “NVMREG Access”, Section 4.2.1 “BANK SELECTION”; Updated Table 6-1; Updated Figure 7-1; Updated Register 7-6; Updated Figure 8-2; Updated Register 9-1; Added Section 10.2.4 “WDT IS ALWAYS OFF”; Updated Table 11-2; Updated Example 11-4; Removed Example 11-5; Updated Figure 15-1; Updated Figure 18-2; Updated Figure 22-1; Updated Figure 29-1; Updated Figure 31-1. Revision A (07/2015) Initial release of the document.  2015-2019 Microchip Technology Inc. DS40001799F-page 467 PIC16(L)F18313/18323 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2015-2019 Microchip Technology Inc. DS40001799F-page 468 PIC16(L)F18313/18323 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F18313, PIC16LF18313, PIC16F18323, PIC16LF18323 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) JQ P ST SL SN RF = = = = = = Pattern: (Industrial) (Extended) UQFN PDIP TSSOP SOIC-14 SOIC-8 UDFN QTP, SQTP, Code or Special Requirements (blank otherwise)  2015-2019 Microchip Technology Inc. PIC16LF18313- I/P Industrial temperature PDIP package PIC16F18313- E/SS Extended temperature, SSOP package Note 1: 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. DS40001799F-page 469 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015-2019, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  2015-2019 Microchip Technology Inc. ISBN: 978-1-5224-5093-1 DS40001799F-page 470 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 Israel - Ra’anana Tel: 972-9-744-7705 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078  2015-2019 Microchip Technology Inc. Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7288-4388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 DS40001799F-page 471 05/14/19