PIC16F18326-I/SL

PIC16(L)F18326/18346 Full-Featured, 14/20 Low Pin Count Microcontrollers with XLP Description PIC16(L)F18326/18346 microcontrollers feature analog, core independent peripherals and communication peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP, PWM and communications) to add flexibility to the application design. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture • Operating Speed: - DC – 32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Up to Four 8-bit Timers • Up to Three 16-bit Timers • Low-Current Power-on Reset (POR) • Power-up Timer (PWRTE) • Brown-out Reset (BOR) Option • Low-Power BOR (LPBOR) Option • Extended Watchdog Timer (WDT) with Dedicated On-Chip Oscillator for Reliable Operation • Programmable Code Protection • Idle Mode: Ability to Put the CPU Core to Sleep While Internal Peripherals Continue Operating from the System Clock • Doze Mode: Ability to Run the CPU Core Slower Than the System Clock Used by the Internal Peripherals • Sleep Mode: Lowest Power Consumption • Peripheral Module Disable (PMD): Peripheral Power Disable Hardware Module to Minimize Power Consumption of Unused Peripherals Memory • • • • 28 Kbytes Program Flash Memory 2 KB Data SRAM Memory 256B of EEPROM Direct, Indirect, and Relative Addressing Modes Operating Characteristics • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF18326/18346) - 2.3V to 5.5V (PIC16F18326/18346) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C eXtreme Low-Power (XLP) Features • • • • Sleep Mode: 40 nA @ 1.8V, typical Watchdog Timer: 250 nA @ 1.8V, typical Secondary Oscillator: 300 nA @ 32 kHz Operating Current: - 8 A @ 32 kHz, 1.8V, typical - 37 A/MHz @ 1.8V, typical  2016-2022 Microchip Technology Inc. and its subsidiaries Digital Peripherals • Configurable Logic Cell (CLC): - Four CLCs - Integrated combinational and sequential logic • Complementary Waveform Generator (CWG): - Two CWGs - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources • Capture/Compare/PWM (CCP) Modules: - Four CCPs - 16-bit resolution for Capture/Compare modes - 10-bit resolution for PWM mode • Pulse-Width Modulators (PWM): - Two 10-bit PWMs • Numerically Controlled Oscillator (NCO): - Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock - Input Clock: 0 Hz < FNCO < 32 MHz - Resolution: FNCO/220 • Serial Communications: - EUSART - RS-232, RS-485, LIN compatible - Auto-Baud Detect, auto-wake-up on start - Host Synchronous Serial Port (MSSP) - SPI - I2C, SMBus, PMBus™ compatible • Data Signal Modulator (DSM): - Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms DS40001839F-page 1 PIC16(L)F18326/18346 • Up to 18 I/O Pins: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select - Input level selection control (ST or TTL) - Digital open-drain enable • Peripheral Pin Select (PPS): - I/O pin remapping of digital peripherals • Timer Modules: - Timer0: - 8/16-bit timer/counter - Synchronous or asynchronous operation - Programmable prescaler/postscaler - Time base for capture/compare function - Timer1/3/5 with gate control: - 16-bit timer/counter - Programmable internal or external clock sources - Multiple gate sources - Multiple gate modes - Time base for capture/compare function - Timer2/4/6: - 8-bit timers - Programmable prescaler/postscaler - Time base for PWM function  2016-2022 Microchip Technology Inc. and its subsidiaries Analog Peripherals • 10-Bit Analog-to-Digital Converter (ADC): - 17 external channels - Conversion available during Sleep • Comparator: - Two comparators - Fixed Voltage Reference at non-inverting input(s) - Comparator outputs externally accessible • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive Reference Selection - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels Flexible Oscillator Structure • High-Precision Internal Oscillator: - Software-selectable frequency range up to 32 MHz - ±1% at nominal 4 MHz calibration point • 4x PLL with External Sources • Low-Power Internal 31 kHz Oscillator (LFINTOSC) • External Low-Power 32 kHz Crystal Oscillator (SOSC) • External Oscillator Block with: - Three Crystal/Resonator modes up to 20 MHz - Three External Clock modes up to 20 MHz - Fail-Safe Clock Monitor - Detects clock source failure - Oscillator Start-up Timer (OST) - Ensures stability of crystal oscillator sources DS40001839F-page 2 1 1 1 2 1 Y I 1 1 1 1 2 1 Y I PIC16(L)F18324 (B) 7 4 256 512 12 11 2 1 1/3/3 4/2 2 1 1 1 4 1 Y I I ICD(2) 1 2/2 PPS 2/2 1/1/1 NCO 1/1/1 1 CLC 1 2 I2 C 1 11 SPI 5 12 EUSART 6 256 CWG 256 256 CCP/PWM 256 2 Timers 0/1/2 2 3.5 5-bit DAC RAM (B) 3.5 Comparators EEPROM (B) (A) (A) 10-bit ADCs Program Memory (KW) PIC16(L)F18313 PIC16(L)F18323 Device I/Os(1) Program Memory (KB) PIC16(L)F183XX FAMILY TYPES Data Sheet Index  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 1: PIC16(L)F18325 (C) 14 8 256 1K 12 11 2 1 1/3/3 4/2 2 1 2 2 4 1 Y PIC16(L)F18326 (D) 28 16 256 2K 12 11 2 1 1/3/3 4/2 2 1 2 2 4 1 Y I PIC16(L)F18344 (B) 7 4 256 512 18 17 2 1 1/3/3 4/2 2 1 1 1 4 1 Y I PIC16(L)F18345 (C) 14 8 256 1K 18 17 2 1 1/3/3 4/2 2 1 2 2 4 1 Y I PIC16(L)F18346 (D) 28 16 256 2K 18 17 2 1 1/3/3 4/2 2 1 2 2 4 1 Y I One pin is input-only. Debugging Methods: (I) – Integrated on Chip; E – using Emulation Header. Data Sheet Index: (Unshaded devices are described in this document.) Note A: DS40001799 PIC16(L)F18313/18323 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP B: DS40001800 PIC16(L)F18324/18344 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP C: DS40001795 PIC16(L)F18325/18345 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP D: DS40001839 PIC16(L)F18326/18346 Data Sheet,Full-Featured, Low Pin Count Microcontrollers with XLP Note: For other small form-factor package availability and marking information, visit http://www.microchip.com/packaging or contact the local sales office. DS40001839F-page 3 PIC16(L)F18326/18346 Note 1: 2: PIC16(L)F18326/18346 Pin Diagrams 14-PIN PDIP, SOIC, TSSOP 1 2 3 4 5 6 7 VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 Note: 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 See Table 2 for location of all peripheral functions. 16-PIN UQFN/QFN/VQFN (4x4) 16 15 14 13 VDD NC NC VSS FIGURE 2: PIC16(L)F18326 FIGURE 1: 1 12 RA0/ICSPDAT 2 11 RA1/ICSPCLK PIC16(L)F18326 3 10 RA2 4 9 RC0 RC4 RC3 RC2 RC1 5 6 7 8 RA5 RA4 RA3/MCLR/VPP RC5 2: FIGURE 3: Note: See Table 2 for location of all peripheral functions. It is recommended that the exposed bottom pad be connected to VSS, but must not be the main VSS connection to the device. 20-PIN PDIP, SOIC, SSOP VDD 1 20 VSS RA5 2 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK MCLR/VPP/RA3 4 17 RA2 RC5 5 16 RC4 6 RC3 RC6 7 13 RC0 RC1 RC2 RB4 RC7 RB7 9 12 RB5 10 11 RB6 8 PIC16(L)F18346 Note 1: 15 14 See Table 3 for location of all peripheral functions.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 4 PIC16(L)F18326/18346 20-PIN UQFN, QFN (also called VQFN) (4x4) 20 19 18 17 16 RA4 RA5 VDD VSS RA0/ICSPDAT FIGURE 4: 1 15 2 14 3 PIC16(L)F18346 13 4 12 5 11 RA1/ICSPCLK RA2 RC0 RC1 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 MCLR/VPP/RA3 RC5 RC4 RC3 RC6 Note 1: See Table 3 for location of all peripheral functions. 2: It is recommended that the exposed bottom pad be connected to VSS, but must not be the main VSS connection to the device.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 5 16-Pin UQFN/QFN/VQFN ADC Reference Comparator NCO DAC DSM Timers CCP PWM CWG MSSP EUSART CLC CLKR Interrupt Pull-up Basic  2016-2022 Microchip Technology Inc. and its subsidiaries 14-Pin PDIP/SOIC/TSSOP 14/16-PIN ALLOCATION TABLE (PIC16(L)F18326) I/O(2) TABLE 2: RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — — — — — SS2(1) — — — IOC Y ICDDAT/ ICSPDAT RA1 12 11 ANA1 VREF+ C1IN0C2IN0- — DAC1REF+ — — — — — — — — — IOC Y ICDCLK/ ICSPCLK RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) CCP3(1) — CWG1IN(1) CWG2IN(1) — — — — INT(1) IOC Y — RA3 4 3 — — — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOC Y CLKOUT OSC2 RA5 2 1 ANA5 — — — — — T1CKI(1) SOSCIN SOSCI — — — — — CLCIN3(1) — IOC Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — T5CKI(1) — — — SCK1(1) SCL1(1,3,4) — — — IOC Y — — CLCIN2(1) — IOC Y — RC1 9 8 ANC1 — C1IN1C2IN1- — — — — CCP4(1) — — SDI1(1) SDA1(1,3,4) RC2 8 7 ANC2 — C1IN2C2IN2- — — MDCIN1(1) — — — — — — — — IOC Y — RC3 7 6 ANC3 — C1IN3C2IN3- — — MDMIN(1) T5G(1) CCP2(1) — — SS1(1) — CLCIN0(1) — IOC Y — RC4 6 5 ANC4 — — — — — T3G(1) — — — SCK2(1) SCL2(1,3,4) — CLCIN1(1) — IOC Y — RX(1) — — IOC Y — — — — — — VDD RC5 5 VDD Note 1 1: 2: 3: 4: 4 ANC5 — — — — MDCIN2(1) T3CKI(1) CCP1(1) — — SDI2(1) SDA2(1,3,4) 16 — — — — — — — — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ ST as selected by the INLVL register. PIC16(L)F18326/18346 DS40001839F-page 6 Pin Allocation Tables Timers CCP PWM — — — — — — — — — — — VSS SDA1(3) SDA2(3) CK CLC1OUT CLKR — — — — — — — C1OUT NCO1 — DSM TMR0 CCP1 PWM5 — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCL1(3) SCL2(3) DT CLC2OUT — — — — — — — — — — — — — CCP3 — CWG1C CWG2C SDO1 SDO2 TX CLC3OUT — — — — — — — — — — — — — CCP4 — CWG1D CWG2D SCK1 SCK2 — CLC4OUT — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ ST as selected by the INLVL register. DS40001839F-page 7 PIC16(L)F18326/18346 1: 2: 3: 4: — CWG1A CWG2A OUT(2) Note Basic DSM — Pull-up DAC — Interrupt NCO — CLKR Comparator — CLC Reference 13 EUSART ADC 14 MSSP 16-Pin UQFN/QFN/VQFN VSS CWG 14-Pin PDIP/SOIC/TSSOP 14/16-PIN ALLOCATION TABLE (PIC16(L)F18326) (CONTINUED) I/O(2)  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 2: — RA4 3 20 ANA4  2016-2022 Microchip Technology Inc. and its subsidiaries Basic 1 Pull-up 4 Interrupt RA3 CLKR ANA2 CLC 14 EUSART 17 MSSP RA2 CWG ANA1 VREF+ PWM 15 CCP 18 Timers RA1 DSM ANA0 DAC ADC 16 NCO 20-Pin UQFN/QFN/VQFN 19 Comparator 20-Pin PDIP/SOIC/SSOP RA0 Reference I/O(2) 20-PIN ALLOCATION TABLE (PIC16(L)F18346) — C1IN0+ — DAC1OUT — — — — — — — — — IOC Y ICDDAT ICSPDAT C1IN0C2IN0- — DAC1REF+ — — — — — SS2 — — — IOC Y ICDCLK ICSPCLK VREF- — — DAC1REF- — T0CKI(1) CCP3(1) — CWG1IN(1) CWG2IN(1) — — CLCIN0(1) — IOC INT(1) Y — — — — — — — — — — — — — — IOC Y MCLR VPP — T1G(1) T3G(1) T5G(1) SOSCO CCP4(1) — — — — — — IOC Y CLKOUT OSC2 — — — — — — — IOC Y CLKIN OSC1 — — — SDI1(1) SDA1(1,3,4) — CLCIN2(1) — IOC Y — — SDI2(1) (1,3,4) RX(1) CLCIN3(1) — IOC Y — SCK1(1) (1,3,4) — — — IOC Y — SCK2(1) (1,3,4) — — — IOC Y — — — — — RA5 2 19 ANA5 — — — — — T1CKI(1) T3CKI(1) T5CKI(1) SOSCIN SOSCI RB4 13 10 ANB4 — — — — — — RB5 12 RB6 11 9 8 ANB5 ANB6 — — — — — — — — — — — — — — — — — SDA2 SCL1 RB7 10 7 ANB7 — — — — — — — — — RC0 16 13 ANC0 — C2IN0+ — — — — — — — — — — — IOC Y — — — — — — — — — — — — IOC Y — — — MDCIN1(1) — — — — — — — — IOC Y — RC1 15 12 ANC1 — C1IN1C2IN1- RC2 14 11 ANC2 — C1IN2C2IN2- Note 1: 2: 3: 4: SCL2 Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. PIC16(L)F18326/18346 DS40001839F-page 8 TABLE 3: ANC4 — — — 2 ANC5 — — — RC6 8 5 ANC6 — — — RC7 9 6 ANC7 — — VDD 1 18 — — VSS 20 17 — — — IOC Y — — — — IOC Y — — — — IOC Y — — — — IOC Y — — — — — IOC Y — — — — — — — VDD — — — — — — — VSS SDO1 SDO2 DT CLC1OUT CLKR — — — — — — — — — — CCP1(1) — — — — — — — — SS1(1) — — — — — — — — — — — — — — — — — — — DSM — DAC — — — — MDCIN2(1) — — — — — — — — C1OUT NCO1 — DSM TMR0 CCP1 PWM5 — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCK1 SCK2 CK CLC2OUT — — — — — — — — — — — — — CCP3 — CWG1C CWG2C SCL1(3) SCL2(3) TX CLC3OUT — — — — CWG1D CWG2D SDA1(3) SDA2(3) — CLC4OUT — — — — (2) 1: 2: 3: 4: CLCIN1(1) CCP2(1) MDMIN(1) CWG1A CWG2A — Note — — — — — — — — — — — CCP4 — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. DS40001839F-page 9 PIC16(L)F18326/18346 OUT Basic 3 5 Pull-up 6 RC5 Interrupt RC4 CLKR — CLC C1IN3C2IN3- EUSART NCO — MSSP Comparator ANC3 CWG Reference 4 PWM ADC 7 CCP 20-Pin UQFN/QFN/VQFN RC3 Timers 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F18346) (CONTINUED) I/O(2)  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 3: PIC16(L)F18326/18346 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 12 2.0 Guidelines for Getting Started With PIC16(L)F183XX Microcontrollers ..................................................................................... 22 3.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 25 4.0 Memory Organization ................................................................................................................................................................. 27 5.0 Device Configuration .................................................................................................................................................................. 63 6.0 Resets ........................................................................................................................................................................................ 70 7.0 Oscillator Module........................................................................................................................................................................ 78 8.0 Interrupts .................................................................................................................................................................................... 96 9.0 Power-Saving Operation Modes .............................................................................................................................................. 112 10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 119 11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 123 12.0 I/O Ports ................................................................................................................................................................................... 140 13.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 160 14.0 Peripheral Module Disable ....................................................................................................................................................... 166 15.0 Interrupt-on-Change ................................................................................................................................................................. 172 16.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 179 17.0 Temperature Indicator Module ................................................................................................................................................. 182 18.0 Comparator Module.................................................................................................................................................................. 184 19.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 193 20.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 199 21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 221 22.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 236 23.0 Numerically Controlled Oscillator (NCO1) Module ................................................................................................................... 250 24.0 5-bit Digital-to-Analog Converter (DAC1) Module .................................................................................................................... 261 25.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 265 26.0 Timer0 Module ......................................................................................................................................................................... 276 27.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 283 28.0 Timer2/4/6 Module ................................................................................................................................................................... 297 29.0 Capture/Compare/PWM Modules ............................................................................................................................................ 302 30.0 Host Synchronous Serial Port (MSSPx) Module ...................................................................................................................... 314 31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1) ............................................................. 367 32.0 Reference Clock Output Module .............................................................................................................................................. 392 33.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 395 34.0 Instruction Set Summary .......................................................................................................................................................... 397 35.0 Electrical Specifications............................................................................................................................................................ 411 36.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 442 37.0 Development Support............................................................................................................................................................... 463 38.0 Packaging Information.............................................................................................................................................................. 467 Appendix A: Data Sheet Revision History.......................................................................................................................................... 496 The Microchip WebSite ...................................................................................................................................................................... 497 Customer Change Notification Service .............................................................................................................................................. 497 Customer Support .............................................................................................................................................................................. 497 Product Identification System ............................................................................................................................................................ 498  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 10 PIC16(L)F18326/18346 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 11 PIC16(L)F18326/18346 The PIC16(L)F18326/18346 devices are described within this data sheet. PIC16(L)F18326 are available in 14-pin PDIP, SOIC, TSSOP and 16-pin UQFN/QFN/ VQFN packages. PIC16(L)F18346 are available in 20pin PDIP, SOIC, SSOP, UQFN and QFN/VQFN packages. See Section 38.0 “Packaging Information” for further packaging information. Figure 1-1 shows a block diagram of the PIC16(L)F18326/18346 devices. Table 1-2 shows the pinout descriptions. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral PIC16(L)F18346 DEVICE OVERVIEW PIC16(L)F18326 1.0 Analog-to-Digital Converter (ADC) ● ● Temperature Indicator ● ● DAC1 ● ● ADCFVR ● ● CDAFVR ● ● DSM1 ● ● NCO1 ● ● CCP1 ● ● CCP2 ● ● CCP3 ● ● CCP4 ● ● C1 ● ● C2 ● ● CWG1 ● ● CWG2 ● ● CLC1 ● ● CLC2 ● ● CLC3 ● ● CLC4 ● ● Digital-to-Analog Converter (DAC) Reference Table 1-1 for peripherals available per device. Fixed Voltage Reference (FVR) Digital Signal Modulator (DSM) Numerically Controlled Oscillator (NCO) Capture/Compare/PWM (CCP) Modules Comparators Complementary Waveform Generator (CWG) Configurable Logic Cell (CLC) Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) EUSART1 ● ● MSSP1 ● ● MSSP2 ● ● PWM5 ● ● PWM6 ● ● TMR0 ● ● TMR1 ● ● TMR2 ● ● TMR3 ● ● TMR4 ● ● TMR5 ● ● TMR6 ● ● Host Synchronous Serial Port (MSSP) Pulse-Width Modulator (PWM) Timers (TMR)  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 12 PIC16(L)F18326/18346 FIGURE 1-1: PIC16(L)F18326/18346 BLOCK DIAGRAM Program Flash Memory RAM CLKOUT PORTA PORTB(1) Timing Generation HFINTOSC/ LFINTOSC Oscillator CLKIN CPU PORTC See Figure 3-1 MCLR DSM NCO1 PWMs Timer0 Timer1/3/5 Timer2/4/6 MSSP1/2 Comparators CWG1/2 Temp. Indicator Note 1: ADC 10-bit FVR DAC CCPs EUSART1 CLCs PIC16(L)F18346 only.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 13 PIC16(L)F18326/18346 TABLE 1-2: PIC16(L)F18326 PINOUT DESCRIPTION Name Function Input Type Output Type RA0/ANA0/C1IN0+/DAC1OUT/ SS2(1)/ ICDDAT/ICSPDAT RA0 TTL/ST CMOS ANA0 AN ― ADC Channel A0 input. C1IN0+ AN ― Comparator C1 positive input. DAC1OUT ― AN Digital-to-Analog Converter output. SS2 TTL/ST ― Client Select 2 input. ICDDAT TTL/ST CMOS In-Circuit Debug Data I/O. ICSPDAT TTL/ST CMOS ICSP™ Data I/O. General purpose I/O. RA1/ANA1/VREF+/C1IN0-/ C2IN0-/DAC1REF+/ ICDCLK/ ICSPCLK RA2/ANA2/VREF-/ DAC1REF-/ T0CKI(1)/ CCP3(1)/CWG1IN(1)/ CWG2IN(1)/INT(1) RA3/MCLR/VPP (1) RA4/ANA4/T1G / SOSCO/ CLKOUT/OSC2 Description General purpose I/O. RA1 TTL/ST CMOS ANA1 AN ― ADC Channel A1 input. VREF+ AN ― ADC positive voltage reference input. C1IN0- AN — Comparator C1 negative input. C2IN0- AN ― Comparator C2 negative input. DAC1REF+ ― AN Digital-to-Analog Converter positive reference input. ICDCLK TTL/ST CMOS ICSPCLK TTL/ST CMOS In-Circuit Debug Clock I/O. ICSP Clock I/O. RA2 TTL/ST CMOS General purpose I/O. ANA2 AN ― ADC Channel A2 input. VREF- AN ― ADC negative voltage reference input. DAC1REF- ― AN Digital-to-Analog Converter negative reference input. T0CKI TTL/ST ― CCP3 TTL/ST CMOS TMR0 Clock input. CWG1IN TTL/ST ― Complementary Waveform Generator 1 input. CWG2IN TTL/ST ― Complementary Waveform Generator 2 input. Capture/Compare/PWM 3 input. INT TTL/ST ― RA3 TTL/ST CMOS External interrupt input. MCLR TTL/ST ― Master Clear with internal pull-up. VPP HV ― Programming voltage. General purpose I/O. General purpose I/O. RA4 TTL/ST CMOS ANA4 AN ― ADC Channel A4 input. T1G ST ― TMR1 gate input. SOSCO ― XTAL CLKOUT ― CMOS Secondary Oscillator connection. FOSC/4 output. OSC2 ― XTAL Crystal/Resonator (LP, XT, HS modes). Legend: AN = Analog input or output CMOS =CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST =Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL =Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 14 PIC16(L)F18326/18346 TABLE 1-2: PIC16(L)F18326 PINOUT DESCRIPTION (CONTINUED) Name RA5/ANA5/T1CKI(1)/ SOSCIN/ SOSCI/ CLCIN3(1)/CLKIN/ OSC1 RC0/ANC0/C2IN0+/ T5CKI(1)/ SCK1(1)/ SCL1(1,3) RC1/ANC1/C1IN1-/C2IN1-/ CCP4(1)/SDI1(1)/ SDA1(1,3)/ CLCIN2(1) RC2/ANC2/C1IN2-/C2IN2-/ MDCIN1(1) RC3/ANC3/C1IN3-/C2IN3-/ MDMIN(1)/T5G(1)/ CCP2(1)/ SS1(1)/CLCIN0(1) Function Input Type Output Type RA5 TTL/ST CMOS Description General purpose I/O. ANA5 AN ― ADC Channel A5 input. T1CKI TTL/ST ― TMR1 Clock input. SOSCIN TTL/ST ― Secondary Oscillator input connection. SOSCI XTAL ― Secondary Oscillator connection. CLCIN3 TTL/ST ― Configurable Logic Cell 3 input. CLKIN TTL/ST ― External clock input. OSC1 XTAL ― RC0 TTL/ST CMOS ANC0 AN ― ADC Channel C0 input. C2IN0+ AN ― Comparator C2 positive input. TMR5 Clock input. Crystal/Resonator (LP, XT, HS modes). General purpose I/O. T5CKI TTL/ST ― SCK1 TTL/ST CMOS SPI Clock 1. SCL1 2C OD I2C Clock 1. I RC1 TTL/ST CMOS ANC1 AN ― ADC Channel C1 input. C1IN1- AN ― Comparator C1 negative input. C2IN1- AN ― CCP4 TTL/ST CMOS Capture/Compare/PWM 4 input. SDI1 TTL/ST CMOS SPI Data input 1. SDA1 2 OD I C General purpose I/O. Comparator C2 negative input. I2C Data 1. CLCIN2 TTL/ST ― RC2 TTL/ST CMOS Configurable Logic Cell 2 input. ANC2 AN ― ADC Channel C2 input. C1IN2- AN ― Comparator C1 negative input. C2IN2- AN ― Comparator C2 negative input. MDCIN1 TTL/ST ― RC3 TTL/ST CMOS General purpose I/O. Modular Carrier input 1. General purpose I/O. ANC3 AN ― ADC Channel C3 input. C1IN3- AN ― Comparator C1 negative input. C2IN3- AN ― Comparator C2 negative input. MDMIN TTL/ST ― Modular Source input. T5G TTL/ST ― CCP2 TTL/ST CMOS TMR5 gate input. SS1 TTL/ST ― Client Select 1 input. CLCIN0 TTL/ST ― Configurable Logic Cell 0 input. Capture/Compare/PWM 2 input. Legend: AN = Analog input or output CMOS =CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST =Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL =Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 15 PIC16(L)F18326/18346 TABLE 1-2: PIC16(L)F18326 PINOUT DESCRIPTION (CONTINUED) Name RC4/ANC4/T3G(1)/ SCK2(1)/ SCL2(1,3)/ CLCIN1(1) RC5/ANC5/MDCIN2(1)/ T3CKI(1)/CCP1(1)/SDI2(1)/ SDA2(1,3)/RX(1)/DT Function Input Type Output Type RC4 TTL/ST CMOS ANC4 AN ― ADC Channel C4 input. T3G TTL/ST ― TMR3 gate input. SCK2 TTL/ST CMOS SPI Clock 2. SCL2 I2 C OD I2C Clock 2. Description General purpose I/O. CLCIN1 TTL/ST ― RC5 TTL/ST CMOS Configurable Logic Cell 1 input. ANC5 AN ― ADC Channel C5 input. MDCIN2 TTL/ST ― Modular Carrier input 2. General purpose I/O. T3CKI TTL/ST ― CCP1 TTL/ST CMOS Capture/Compare/PWM 1 input. TMR3 Clock input. SDI2 TTL/ST CMOS SPI Data 2. SDA2 I2 C OD I2C Data 2. RX TTL/ST CMOS EUSART asynchronous input. DT TTL/ST CMOS EUSART synchronous data output. VDD VDD Power ― Positive supply. VSS VSS Power ― Ground reference. Legend: AN = Analog input or output CMOS =CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST =Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL =Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 16 PIC16(L)F18326/18346 TABLE 1-2: Name OUT(2) PIC16(L)F18326 PINOUT DESCRIPTION (CONTINUED) Function Input Type Output Type C1 ― CMOS Comparator C1 output. Comparator C2 output. Description C2 ― CMOS NCO1 ― CMOS Numerically Controlled Oscillator output. DSM ― CMOS Digital Signal Modulator output. TMR0 ― CMOS TMR0 clock output. CCP1 ― CMOS Capture/Compare/PWM 1 output. CCP2 ― CMOS Capture/Compare/PWM 2 output. CCP3 ― CMOS Capture/Compare/PWM 3 output. CCP4 ― CMOS Capture/Compare/PWM 4 output. PWM5 ― CMOS Pulse-Width Modulator 5 output. PWM6 ― CMOS Pulse-Width Modulator 6 output. CWG1A ― CMOS Complementary Waveform Generator 1 output A. CWG2A ― CMOS Complementary Waveform Generator 2 output A. CWG1B ― CMOS Complementary Waveform Generator 1 output B. CWG2B ― CMOS Complementary Waveform Generator 2 output B. CWG1C ― CMOS Complementary Waveform Generator 1 output C. CWG2C ― CMOS Complementary Waveform Generator 2 output C. CWG1D ― CMOS Complementary Waveform Generator 1 output D. CWG2D ― CMOS Complementary Waveform Generator 2 output D. SDA1(3) I2 C OD I2C data output. SDA2(3) I2 C OD I2C data output. (3) 2 I C OD I2C clock output. SCL2(3) I2 C OD I2C clock output. SDO1 ― CMOS SPI1 data output. SD02 ― CMOS SPI2 data output. SCK1 ― CMOS SPI1 clock output. SCL1 SCK2 ― CMOS SPI2 clock output. TX/CK ― CMOS Asynchronous TX data/synchronous clock output. DT ― CMOS EUSART synchronous data output. CLC1OUT ― CMOS Configurable Logic Cell 1 source output. CLC2OUT ― CMOS Configurable Logic Cell 2 source output. CLC3OUT ― CMOS Configurable Logic Cell 3 source output. CLC4OUT ― CMOS Configurable Logic Cell 4 source output. CLKR ― CMOS Clock Reference output. Legend: AN = Analog input or output CMOS =CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST =Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL =Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 17 PIC16(L)F18326/18346 TABLE 1-3: PIC16(L)F18346 PINOUT DESCRIPTION Name RA0/ANA0/C1IN0+/DAC1OUT/ ICDDAT/ICSPDAT RA1/ANA1/VREF+/C1IN0-/ C2IN0-/ DAC1REF+/SS2(1))/ ICDCLK/ ICSPCLK RA2/ANA2/VREF-/ DAC1REF-/ T0CKI(1)/ CCP3(1)/CWG1IN(1)/ CWG2IN(1)/CLCIN0(1)/ INT(1) RA3/MCLR/VPP RA4/ANA4/T1G(1)/T3G(1)/ T5G(1)/SOSCO/CCP4(1)/ CLKOUT/OSC2 Function Input Type Output Type Description RA0 TTL/ST CMOS ANA0 AN ― General purpose I/O. ADC Channel A0 input. C1IN0+ AN ― Comparator C1 positive input. DAC1OUT ― AN ICDDAT TTL/ST CMOS In-Circuit Debug Data I/O. Digital-to-Analog Converter output. ICSPDAT TTL/ST CMOS ICSP™ Data I/O. General purpose I/O. RA1 TTL/ST CMOS ANA1 AN ― ADC Channel A1 input. VREF+ AN ― ADC positive voltage reference input. C1IN0- AN — Comparator C1 negative input. Comparator C2 negative input. C2IN0- AN ― DAC1REF+ AN ― Digital-to-Analog Converter positive reference input. SS2 TTL/ST ― Client Select 2 input. ICDCLK TTL/ST CMOS ICSPCLK TTL/ST CMOS In-Circuit Debug Clock I/O. ICSP Clock I/O. RA2 TTL/ST CMOS General purpose I/O. ANA2 AN ― ADC Channel A2 input. VREF- AN ― ADC negative voltage reference input. DAC1REF- AN ― Digital-to-Analog Converter negative reference input. T0CKI TTL/ST ― CCP3 TTL/ST CMOS TMR0 Clock input. CWG1IN TTL/ST ― Complementary Waveform Generator 1 input. CWG2IN TTL/ST ― Complementary Waveform Generator 2 input. CLCIN0 TTL/ST ― Configurable Logic Cell 0 input. INT TTL/ST ― RA3 TTL/ST CMOS MCLR TTL/ST ― Capture/Compare/PWM 3 input. External interrupt input. General purpose I/O. Master Clear with internal pull-up. VPP HV ― Programming voltage. RA4 TTL/ST CMOS General purpose I/O. ANA4 AN ― ADC Channel A4 input. T1G TTL/ST ― TMR1 gate input. T3G TTL/ST ― TMR3 gate input. T5G TTL/ST ― SOSCO ― XTAL Secondary Oscillator connection. TMR5 gate input. Capture/Compare/PWM 4 input. CCP4 TTL/ST CMOS CLKOUT ― CMOS FOSC/4 output. OSC2 ― XTAL Crystal/Resonator (LP, XT, HS modes). Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 18 PIC16(L)F18326/18346 TABLE 1-3: PIC16(L)F18346 PINOUT DESCRIPTION (CONTINUED) Name RA5/ANA5/T1CKI(1)/ T3CKI(1)/ T5CKI(1)/ SOSCIN/SOSCI/ CLKIN/OSC1 (1) (1,3) RB4/ANB4/SDI1 / SDA1 CLCIN2(1) / RB5/ANB5/SDI2(1)/ SDA2(1,3)/ RX(1)/DT/CLCIN3(1) RB6/ANB6/SCK1(1)/ SCL1(1,3) (1) RB7/ANB7/SCK2 / SCL2 (1,3) RC0/ANC0/C2IN0+ RC1/ANC1/C1IN1-/C2IN1- RC2/ANC2/C1IN2-/C2IN2-/ MDCIN1(1) Function Input Type Output Type RA5 TTL/ST CMOS Description General purpose I/O. ANA5 AN ― ADC Channel A5 input. T1CKI TTL/ST ― TMR1 Clock input. T3CKI TTL/ST ― TMR3 Clock input. T5CKI TTL/ST ― TMR5 Clock input. SOSCIN TTL/ST ― Secondary Oscillator input connection. SOSCI XTAL ― Secondary Oscillator connection. CLKIN TTL/ST ― External clock input. OSC1 XTAL ― Crystal/Resonator (LP, XT, HS modes). RB4 TTL/ST CMOS ANB4 AN ― SDI1 TTL/ST CMOS SDA1 I2C OD CLCIN2 TTL/ST ― RB5 TTL/ST CMOS ANB5 AN ― General purpose I/O. ADC Channel B4 input. SPI Data input 1. I2C Data 1. Configurable Logic Cell 2 input. General purpose I/O. ADC Channel B5 input. SDI2 TTL/ST CMOS SDA2 I2C OD RX TTL/ST CMOS EUSART asynchronous input. DT TTL/ST CMOS EUSART synchronous data output. CLCIN3 TTL/ST ― RB6 TTL/ST CMOS SPI Data input 2. I2C Data 2. Configurable Logic Cell 3 input. General purpose I/O. ANB6 AN ― SCK1 TTL/ST CMOS ADC Channel B6 input. SPI Clock 1. SCL1 2 I C OD I2C Clock 1. RB7 TTL/ST CMOS ANB7 AN ― SCK2 TTL/ST CMOS SPI Clock 2. SCL2 I 2C OD I2C Clock 2. RC0 TTL/ST CMOS ANC0 AN ― C2IN0+ AN ― RC1 TTL/ST CMOS ANC1 AN ― General purpose I/O. ADC Channel B7 input. General purpose I/O. ADC Channel C0 input. Comparator C2 positive input. General purpose I/O. ADC Channel C1 input. C1IN1- AN ― Comparator C1 negative input. C2IN1- AN ― Comparator C2 negative input. RC2 TTL/ST CMOS ANC2 AN ― General purpose I/O. ADC Channel C2 input. C1IN2- AN ― Comparator C1 negative input. C2IN2- AN ― Comparator C2 negative input. MDCIN1 TTL/ST ― Modular Carrier input 1. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 19 PIC16(L)F18326/18346 TABLE 1-3: PIC16(L)F18346 PINOUT DESCRIPTION (CONTINUED) Name RC3/ANC3/C1IN3-/C2IN3-/ MDMIN(1)/ CCP2(1)/CLCIN1(1)/ RC4/ANC4 (1) RC5/ANC5/MDCIN2 / CCP1 RC6/ANC6/SS1(1) RC7/ANC7 (1) Function Input Type Output Type RC3 TTL/ST CMOS ANC3 AN ― ADC Channel C3 input. C1IN3- AN ― Comparator C1 negative input. Description General purpose I/O. C2IN3- AN ― Comparator C2 negative input. MDMIN TTL/ST ― Modular Source input. CCP2 TTL/ST CMOS CLCIN1 TTL/ST ― RC4 TTL/ST CMOS ANC4 AN ― Capture/Compare/PWM 2 input. Configurable Logic Cell 1 input. General purpose I/O. ADC Channel C4 input. RC5 TTL/ST CMOS ANC5 AN ― General purpose I/O. MDCIN2 TTL/ST ― CCP1 TTL/ST CMOS Capture/Compare/PWM 1 input. General purpose I/O. ADC Channel C5 input. Modular Carrier input 2. RC6 TTL/ST CMOS ANC6 AN ― ADC Channel C6 input. SS1 TTL/ST ― Client Select 1 input. RC7 TTL/ST CMOS General purpose I/O. ANC7 AN ― ADC Channel C7 input. VDD VDD Power ― Positive supply. VSS VSS Power ― Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 20 PIC16(L)F18326/18346 TABLE 1-3: PIC16(L)F18346 PINOUT DESCRIPTION (CONTINUED) Name OUT(2) Function Input Type Output Type C1 ― CMOS Comparator C1 output. Comparator C2 output. Description C2 ― CMOS NCO1 ― CMOS Numerically Controlled Oscillator output. DSM ― CMOS Digital Signal Modulator output. TMR0 ― CMOS Timer0 clock output. CCP1 ― CMOS Capture/Compare/PWM 1 output. CCP2 ― CMOS Capture/Compare/PWM 2 output. CCP3 ― CMOS Capture/Compare/PWM 3 output. CCP4 ― CMOS Capture/Compare/PWM 4 output. PWM5 ― CMOS Pulse-Width Modulator 5 output. PWM6 ― CMOS Pulse-Width Modulator 6 output. CWG1A ― CMOS Complementary Waveform Generator 1 output A. CWG2A ― CMOS Complementary Waveform Generator 2 output A. CWG1B ― CMOS Complementary Waveform Generator 1 output B. CWG2B ― CMOS Complementary Waveform Generator 2 output B. CWG1C ― CMOS Complementary Waveform Generator 1 output C. CWG2C ― CMOS Complementary Waveform Generator 2 output C. CWG1D ― CMOS Complementary Waveform Generator 1 output D. CWG2D ― CMOS Complementary Waveform Generator 2 output D. SDA1(3) I2 C OD I2C data output. SDA2(3) I2 C OD I2C data output. (3) 2 I C OD I2C clock output. SCL2(3) I2 C OD I2C clock output. SDO1 ― CMOS SPI1 data output. SD02 ― CMOS SPI2 data output. SCK1 ― CMOS SPI1 clock output. SCL1 SCK2 ― CMOS SPI2 clock output. TX/CK ― CMOS Asynchronous TX data/synchronous clock output. DT ― CMOS EUSART synchronous data output. CLC1OUT ― CMOS Configurable Logic Cell 1 source output. CLC2OUT ― CMOS Configurable Logic Cell 2 source output. CLC3OUT ― CMOS Configurable Logic Cell 3 source output. CLC4OUT ― CMOS Configurable Logic Cell 4 source output. CLKR ― CMOS Clock Reference output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 13-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 13-2. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 21 PIC16(L)F18326/18346 2.0 GUIDELINES FOR GETTING STARTED WITH PIC16(L)F183XX MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC16(L)F183XX family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • MCLR pin (when configured for external operation) (see Section 2.3 “Master Clear (MCLR) Pin”) These pins must also be connected if they are being used in the end application: • ICSPCLK/ICSPDAT pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.4 “ICSP™ Pins”) • OSC1 and OSC2 pins when an external oscillator source is used (see Section 2.5 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented The minimum mandatory connections are shown in Figure 2-1. FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS (Note 1) C2 R1 VSS VDD VDD R2 MCLR/VPP C1 PIC16(L)F1xxx VSS Key (all values are recommendations): 16 ceramic C1 and C2: 0.1 PF, 20V R1: 10 kȍ R2: 100ȍ to 470ȍ Note1: Only when MCLRE configuration bit is 1 and the MCLR pin does not have a weak pull-up.  2016-2022 Microchip Technology Inc. and its subsidiaries 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required. All VDD and VSS pins must be connected. None can be left floating. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 µF (100 nF), 10-25V capacitor is recommended. The capacitor must be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors need to be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 µF in parallel with 0.001 µF). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor may be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. DS40001839F-page 22 PIC16(L)F18326/18346 2.3 Master Clear (MCLR) Pin The MCLR pin provides three specific device functions: • Device Reset (when MCLRE = 1) • Digital input pin (when MCLRE = 0) • Device Programming and Debugging If programming and debugging are not required in the end application then either set the MCLRE Configuration bit to ‘1’ and use the pin as a digital input or clear the MCLRE Configuration bit and leave the pin open to use the internal weak pull-up. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, the programmer MCLR/VPP output will need to be connected directly to the pin so that R1 isolates the capacitor, C1 from the MCLR pin during programming and debugging operations. Any components associated with the MCLR pin must be placed within 0.25 inch (6 mm) of the pin.  2016-2022 Microchip Technology Inc. and its subsidiaries 2.4 ICSP™ Pins The ICSPCLK and ICSPDAT pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω. Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they must be isolated from the programmer by resistors between the application and the device pins or removed from the circuit during programming. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/ emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 37.0 “Development Support”. DS40001839F-page 23 PIC16(L)F18326/18346 2.5 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 7.0 “Oscillator Module” for details). The oscillator circuit must be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors must be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour must be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-2. In-line s may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch s, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. 2.6 Unused I/Os Unused I/O pins may be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins and drive the output logic low. FIGURE 2-2: Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 ` OSC2 GND C2 ` SOSCO SOSCI Secondary Oscillator (SOSC) Crystal In planning the application’s routing and I/O assignments, ensure that adjacent PORT pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). ` SOSC: C1 SOSC: C2 Fine-Pitch (Dual-Sided) Layouts: For additional information and design guidance on oscillator circuits, refer to these Microchip Application Notes, available at the corporate website (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 24 PIC16(L)F18326/18346 3.0 ENHANCED MID-RANGE CPU Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 48 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16-levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and FIGURE 3-1: • • • • Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set CORE BLOCK DIAGRAM 5HY%   &RQILJXUDWLRQ  08; )ODVK 3URJUDP 0HPRU\ 'DWD%XV /HYHO6WDFN ELW 5$0  3URJUDP %XV  3URJUDP&RXQWHU  3URJUDP0HPRU\ 5HDG305 5$0$GGU $GGU08; ,QVWUXFWLRQ5HJ 'LUHFW$GGU   ,QGLUHFW $GGU   %655HJ  )655HJ  )655HJ 67$7865HJ  ,QVWUXFWLRQ 'HFRGHDQG &RQWURO 26&&/.,1 26&&/.287 626&, 7LPLQJ *HQHUDWLRQ 3RZHUXS 7LPHU 3RZHURQ 5HVHW :DWFKGRJ 7LPHU %URZQRXW 5HVHW   08; $/8 :5HJ 626&2 9'' 966 ,QWHUQDO 2VFLOODWRU %ORFN  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 25 PIC16(L)F18326/18346 3.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 “Automatic Context Saving” for more information. 3.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See Section 4.4 “Stack” for more details. 3.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers, program memory, and data EEPROM, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 4.5 “Indirect Addressing” for more details. 3.4 Instruction Set There are 48 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 34.0 “Instruction Set Summary” for more details.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 26 PIC16(L)F18326/18346 4.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - Revision ID - User ID - Program Flash Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • Data EEPROM The following features are associated with access and control of program memory and data memory: • • • • PCL and PCLATH Stack Indirect Addressing NVMREG Access 4.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 4-1 shows the memory sizes implemented. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 4-1). TABLE 4-1: DEVICE SIZES AND ADDRESSES Device Program Memory Size (Words) Last Program Memory Address 16384 3FFFh PIC16(L)F18326/18346  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 27 PIC16(L)F18326/18346 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F18326/18346 PC CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 Stack Level 0 Stack Level 1 Interrupt Vector On-chip Program Memory 0000h 0004h 0005h 3FFFh 4000h EXAMPLE 4-1: constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W Wraps to Page 0 Wraps to Page 0 Rollover to Page 0 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 4-1. Page 0-3 Rollover to Page 0 Wraps to Page 0 READING PROGRAM MEMORY AS DATA There are three methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. The third method is to use the NVMCON registers to access the program memory. 4.1.1.1 Stack Level 15 Reset Vector 4.1.1 The BRW instruction makes this type of table very simple to implement. If the code must remain portable with previous generations of microcontrollers, the computed GOTO method must be used because the BRW instruction is not available in some devices, such as the PIC16F6XX, PIC16F7XX, PIC16F8XX, and PIC16F9XX devices. 7FFFh  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 28 PIC16(L)F18326/18346 4.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of an FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that read the program memory via the FSR require one extra instruction cycle to complete. Example 4-2 demonstrates accessing the program memory via an FSR. Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. FIGURE 4-2: 00h ACCESSING PROGRAM MEMORY VIA FSR Special Function Registers 1Fh 4.2 Data Memory Organization The data memory is partitioned into 32 memory banks with 128 bytes in each bank. Each bank consists of (Figure 4-2): • • • • 12 core registers Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM 4.2.1 20h General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) NVMREG Access The NVMREG interface allows read/write access to all locations accessible by the FSRs, User ID locations, and EEPROM. The NVMREG interface also provides read-only access to Device ID, Revision ID, and Configuration data. See Section 11.4 “NVMREG Access” for more information. BANK SELECTION The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 4.5 “Indirect Addressing” for more information.  2016-2022 Microchip Technology Inc. and its subsidiaries Core Registers (12 bytes) 0Bh 0Ch constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 4.1.1.3 Memory Region 7-bit Bank Offset The HIGH directive will set bit 7 if a label points to a location in the program memory. EXAMPLE 4-2: BANKED-MEMORY PARTITIONING 7Fh 4.2.2 CORE REGISTERS The core registers contain the registers that directly affect basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x80h through x0Bh/x8Bh). These registers are listed below in Table 4-2. For detailed information, see Table 4-4. TABLE 4-2: CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON DS40001839F-page 29 PIC16(L)F18326/18346 4.2.2.1 STATUS Register The STATUS register, shown in Register 4-1, contains: • The arithmetic status of the ALU • The Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 4-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 4.0 “Memory Organization”). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 — For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). — U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 30 PIC16(L)F18326/18346 4.2.3 SPECIAL FUNCTION REGISTERS 4.2.4 The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh), with the exception of banks 27, 28, and 29 (PPS and CLC registers). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. GENERAL PURPOSE RAM There are up to 80 bytes of GPR in each data memory bank. The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 4.5.2 “Linear Data Memory” for more information. 4.2.5 COMMON RAM There are 16 bytes of common RAM accessible from all banks. 4.2.6 DEVICE MEMORY MAPS The memory maps for PIC16(L)F18326/18346 are as shown in Table 4-4. TABLE 4-3: Bank Offset Name SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (ALL BANKS)(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets All Banks 000h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h PCL Program Counter (PC) Least Significant Byte 003h STATUS 004h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h FSR1H Indirect Data Memory Address 1 High Pointer 008h BSR 009h WREG 00Ah PCLATH — 00Bh INTCON GIE Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. These registers can be accessed from any bank. Note 1: — — — — — — TO BSR4 0000 0000 0000 0000 PD Z DC C 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 Working Register ---0 0000 ---0 0000 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE ---1 1000 ---q quuu — —  2016-2022 Microchip Technology Inc. and its subsidiaries — — -000 0000 -000 0000 — INTEDG 00-- ---1 00-- ---1 DS40001839F-page 31 Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on all other Resets Bit 1 Bit 0 Value on: POR, BOR RA1 RA0 --xx xxxx --uu uuuu Bank 0 CPU CORE REGISTERS; see Table 4-2 for specifics 00Ch PORTA 00Dh PORTB 00Eh PORTC — — RA5 RA4 X — RA3 RA2 Unimplemented — — — X RB7 RB6 RB5 RB4 — — — — X — — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu — X RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu IOCIF — — — INTF --00 ---0 --00 ---0 — PIR0 — — TMR0IF 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 TMR6IF C2IF C1IF NVMIF SSP2IF BCL2IF TMR4IF NCO1IF 0000 0000 0000 0000 013h PIR3 OSFIF CSWIF TMR3GIF TMR3IF CLC4IF CLC3IF CLC2IF CLC1IF 0000 0000 0000 0000 014h PIR4 CWG2IF CWG1IF TMR5GIF TMR5IF CCP4IF CCP3IF CCP2IF CCP1IF 0000 0000 0000 0000 015h TMR0L TMR0L 016h TMR0H TMR0H 017h T0CON0 018h T0CON1 019h TMR1L TMR1L 01Ah TMR1H TMR1H 01Bh T1CON 01Ch T1GCON DS40001839F-page 32 TMR2 01Eh PR2 01Fh T2CON Legend: Note 1: 2: Unimplemented T0EN — T0OUT T0CS TMR1CS TMR1GE T1GPOL xxxx xxxx xxxx xxxx 1111 1111 1111 1111 T0OUTPS 0-00 0000 0-00 0000 T0ASYNC T0CKPS 0000 0000 0000 0000 T1GSPM xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu T1SOSC T1SYNC T1GGO/ DONE T1GVAL — TMR1ON T1GSS TMR2 T2OUTPS 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 PR2 — — T016BIT T1CKPS T1GTM — 1111 1111 1111 1111 TMR2ON T2CKPS x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. -000 0000 -000 0000 PIC16(L)F18326/18346 00Fh 010h 01Dh — xxxx ---- uuuu ---- PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on: POR, BOR Value on all other Resets Bit 1 Bit 0 TRISA2 TRISA1 TRISA0 --11 -111 --11 -111 Bank 1 CPU CORE REGISTERS; see Table 4-2 for specifics 08Ch TRISA 08Dh TRISB — — TRISA5 TRISA4 X — — Unimplemented — — — X TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- X — — — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111 — X TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 — — INTE --00 ---0 --00 ---0  2016-2022 Microchip Technology Inc. and its subsidiaries 08Eh TRISC 08Fh — 090h PIE0 — ― TMR0IE 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 TMR6IE C2IE C1IE NVMIE SSP2IE BCL2IE TMR4IE NCO1IE 0000 0000 0000 0000 093h PIE3 OSFIE CSWIE TMR3GIE TMR3IE CLC4IE CLC3IE CLC2IE CLC1IE 0000 0000 0000 0000 094h PIE4 CWG2IE CWG1IE TMR5GIE TMR5IE CCP4IE CCP3IE CCP2IE CCP1IE 0000 0000 0000 0000 095h — — 096h — — 097h WDTCON — Unimplemented IOCIE — — Unimplemented Unimplemented — — WDTPS SWDTEN — — — — — --01 0110 --01 0110 098h — — Unimplemented — — 099h — — Unimplemented — — 09Ah — — Unimplemented — — 09Bh ADRESL 09Ch ADRESH 09Dh ADCON0 09Eh ADCON1 09Fh ADACT Legend: Note 1: 2: ADRES xxxx xxxx uuuu uuuu ADRES xxxx xxxx uuuu uuuu CHS ADFM — ADCS — — GO/DONE — ADNREF ADON ADPREF ADACT x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. 0000 0000 0000 0000 0000 -000 0000 -000 ---0 0000 ---0 0000 PIC16(L)F18326/18346 DS40001839F-page 33 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on: POR, BOR Value on all other Resets Bit 1 Bit 0 LATA2 LATA1 LATA0 --xx -xxx --uu -uuu — — — xxxx ---- uuuu ---- Bank 2 CPU CORE REGISTERS; see Table 4-2 for specifics 10Ch LATA 10Dh LATB — — X 10Eh LATC — LATA5 X — LATA4 — Unimplemented LATB7 LATB6 LATB5 LATB4 — — — X — — — LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 --xx xxxx --uu uuuu — X LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu 10Fh — — Unimplemented — — 110h — — Unimplemented — — 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT 114h CM2CON1 C2INTP C2INTN 115h CMOUT — — 116h BORCON SBOREN — 117h FVRCON FVREN FVRRDY 118h DACCON0 DAC1EN — DAC1OE 119h DACCON1 — — — 11Ah to 11Fh — C1POL — C1SP — C2SP C1PCH — C2POL C1SYNC C1NCH C2PCH — C1HYS C2HYS 00-0 -100 00-0 -100 0000 0000 0000 0000 C2SYNC 00-0 -100 00-0 -100 C2NCH 0000 0000 0000 0000 — — — MC2OUT MC1OUT ---- --00 ---- --00 — — — — — BORRDY 1--- ---q u--- ---u TSEN TSRNG CDAFVR — DAC1PSS ADFVR — DAC1NSS DAC1R Unimplemented x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. 0q00 0000 0q00 0000 0-0- 00-0 0-0- 00-0 ---0 0000 ---0 0000 — — DS40001839F-page 34 PIC16(L)F18326/18346 Legend: Note 1: 2: — — PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on: POR, BOR Value on all other Resets Bit 1 Bit 0 ANSA2 ANSA1 ANSA0 --xx -xxx --uu -uuu Bank 3 CPU CORE REGISTERS; see Table 4-2 for specifics 18Ch ANSELA 18Dh ANSELB ― ― ANSA5 X ― ― X X ANSA4 ― Unimplemented — — ANSB7 ANSB6 ANSB5 ANSB4 ― ― ― ― xxxx ---- uuuu ---- ― ― ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 --xx xxxx --uu uuuu ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 xxxx xxxx uuuu uuuu 18Eh ANSELC 18Fh ― ― Unimplemented — — 190h ― ― Unimplemented — — 191h ― ― Unimplemented — — 192h ― ― Unimplemented — — 193h ― ― Unimplemented — — 194h ― ― Unimplemented — — 195h ― ― Unimplemented — — 196h ― ― — — 197h VREGCON(1) ― X  2016-2022 Microchip Technology Inc. and its subsidiaries 198h ― 199h RC1REG 19Ah 19Bh Unimplemented ― ― ― ― ― ― ― VREGPM Reserved Unimplemented ---- --01 ---- --01 — — RC1REG 0000 0000 0000 0000 TX1REG TX1REG 0000 0000 0000 0000 SP1BRGL SP1BRG 0000 0000 0000 0000 19Ch SP1BRGH SP1BRG 0000 0000 0000 0000 19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TMRT TX9D 0000 0010 0000 0010 19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: Note 1: 2: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. PIC16(L)F18326/18346 DS40001839F-page 35 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on: POR, BOR Value on all other Resets Bit 1 Bit 0 WPUA2 WPUA1 WPUA0 --00 0000 --00 0000 ― ― ― 0000 ---- 0000 ---- Bank 4 CPU CORE REGISTERS; see Table 4-2 for specifics 20Ch WPUA 20Dh WPUB ― ― X 20Eh WPUC ― WPUA5 X ― WPUA4 WPUA3 Unimplemented WPUB7 ― WPUB6 WPUB5 WPUB4 ― ― X ― ― ― WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 --00 0000 --00 0000 ― X WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 0000 0000 0000 0000 ― ― Unimplemented ― ― 210h ― ― Unimplemented ― ― 211h SSP1BUF 212h 213h 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT 218h ― 219h SSP2BUF 21Ah 21Bh 21Ch SSP2STAT SMP CKE D/A P 21Dh SSP2CON1 WCOL SSPOV SSPEN CKP 21Eh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN 21Fh SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT Legend: Note 1: 2: SSP1BUF xxxx xxxx uuuu uuuu SSP1ADD SSP1ADD 0000 0000 0000 0000 SSP1MSK SSP1MSK ― S 1111 1111 1111 1111 R/W UA BF PEN RSEN SEN 0000 0000 0000 0000 SBCDE AHEN DHEN 0000 0000 0000 0000 SSPM 0000 0000 0000 0000 0000 0000 0000 0000 Unimplemented ― ― SSP2BUF xxxx xxxx uuuu uuuu SSP2ADD SSP2ADD 0000 0000 0000 0000 SSP2MSK SSP2MSK S 1111 1111 1111 1111 R/W UA BF PEN RSEN SEN 0000 0000 0000 0000 SBCDE AHEN DHEN 0000 0000 0000 0000 SSPM 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. PIC16(L)F18326/18346 DS40001839F-page 36 20Fh PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on: POR, BOR Value on all other Resets Bit 1 Bit 0 ODCA2 ODCA1 ODCA0 --00 -000 --00 -000 Bank 5 CPU CORE REGISTERS; see Table 4-2 for specifics 28Ch ODCONA 28Dh ODCONB ― ― ODCA5 ODCA4 X ― ― Unimplemented ― ― ― X ODCB7 ODCB6 ODCB5 ODCB4 ― ― ― ― 0000 ---- 0000 ---- X ― ― ― ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 --00 0000 --00 0000 ― X ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0000 0000 0000 0000  2016-2022 Microchip Technology Inc. and its subsidiaries 28Eh ODCONC 28Fh ― — Unimplemented ― ― 290h ― ― Unimplemented ― ― 291h CCPR1L 292h CCPR1H 293h CCP1CON CCP1EN 294h CCP1CAP ― 295h CCPR2L 296h CCPR2H 297h CCP2CON CCP2EN ― CCP2OUT CCP2FMT CCP2MODE 0-x0 0000 0-x0 0000 298h CCP2CAP ― ― ― ― CCP2CTS ---- 0000 ---- xxxx 299h ― ― Unimplemented ― ― 29Ah ― ― Unimplemented ― ― 29Bh ― ― Unimplemented ― ― 29Ch ― ― Unimplemented ― ― 29Dh ― ― Unimplemented ― ― 29Eh ― ― ― ― 29Fh CCPTMRS Legend: Note 1: 2: CCPR1 xxxx xxxx xxxx xxxx CCPR1 ― xxxx xxxx xxxx xxxx CCP1OUT CCP1FMT CCP1MODE 0-x0 0000 0-x0 0000 ― ― CCP1CTS ---- 0000 ---- xxxx CCPR2 xxxx xxxx xxxx xxxx CCPR2 xxxx xxxx xxxx xxxx Unimplemented C4TSEL C3TSEL C2TSEL C1TSEL x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. 0101 0101 0101 0101 PIC16(L)F18326/18346 DS40001839F-page 37 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on: POR, BOR Value on all other Resets Bit 1 Bit 0 SLRA2 SLRA1 SLRA0 --11 -111 --11 -111 ― ― ― 1111 ---- 1111 ---- Bank 6 CPU CORE REGISTERS; see Table 4-2 for specifics 30Ch SLRCONA 30Dh SLRCONB ― ― X 30Eh SLRCONC ― SLRA5 X ― SLRA4 ― Unimplemented SLRB7 SLRB6 SLRB5 SLRB4 ― ― ― X ― ― ― SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 --11 1111 --11 1111 ― X SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111 30Fh ― ― Unimplemented ― ― 310h ― ― Unimplemented ― ― 311h CCPR3L 312h CCPR3H 313h CCP3CON CCP3EN ― CCP3OUT CCP3FMT CCP3MODE 0-x0 0000 0-x0 0000 314h CCP3CAP ― ― ― ― CCP3CTS ---- 0000 ---- xxxx 315h CCPR4L CCPR4 316h CCPR4H CCPR4 317h CCP4CON CCP4EN ― CCP4OUT CCP4FMT CCP4MODE 0-x0 0000 0-x0 0000 318h CCP4CAP ― ― ― ― CCP4CTS ---- 0000 ---- xxxx 319h to 31Fh ― xxxx xxxx xxxx xxxx CCPR3 ― xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Unimplemented x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. ― ― DS40001839F-page 38 PIC16(L)F18326/18346 Legend: Note 1: 2: CCPR3 PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Value on: POR, BOR Value on all other Resets Bit 1 Bit 0 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111 Bank 7 CPU CORE REGISTERS; see Table 4-2 for specifics 38Ch INLVLA 38Dh INLVLB ― ― INLVLA5 X ― INLVLA4 INLVLA3 Unimplemented ― ― ― X INLVLB7 INLVLB6 INLVLB5 INLVLB4 ― ― ― ― 1111 ---- 1111 ---- X ― ― ― INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 --11 1111 --11 1111 ― X INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111  2016-2022 Microchip Technology Inc. and its subsidiaries 38Eh INLVLC 38Fh ― ― Unimplemented ― ― 390h ― ― Unimplemented ― ― 391h IOCAP ― ― IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN ― ― IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF ― ― IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h IOCBP ― ― ― 0000 ---- 0000 ---- ― ― ― 0000 ---- 0000 ---- ― ― ― 0000 ---- 0000 ---- X ― ― X 395h IOCBN IOCBF 398h 399h Legend: Note 1: 2: IOCCP IOCCN IOCCF IOCBP6 IOCBP5 IOCBP4 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBF7 IOCBF6 IOCBF5 IOCBF4 ― ― Unimplemented X ― ― X 397h IOCBP7 X ― ― X 396h Unimplemented ― ― Unimplemented ― ― ― ― ― X ― ― ― IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 --00 0000 --00 0000 ― X IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000 X ― ― ― IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 --00 0000 --00 0000 ― X IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000 X ― ― ― IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 --00 0000 --00 0000 ― X IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000 x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. PIC16(L)F18326/18346 DS40001839F-page 39 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 7 CPU CORE REGISTERS; see Table 4-2 for specifics 39Ah CLKRCON 39Bh ― 39Ch MDCON MDEN 39Dh MDSRC ― 39Eh MDCARH ― 39Fh MDCARL ― MDCLPOL Legend: Note 1: 2: CLKREN ― ― ― CLKRDC CLKRDIV 0--1 0000 0--1 0001 Unimplemented ― MDOUT ― ― ― MDBIT ― ― MDOPOL ― ― ― MDMS MDCHPOL MDCHSYNC ― MDCH -xx- xxxx -uu- uuuu MDCLSYNC ― MDCL -xx- xxxx -uu- uuuu 0--0 0--0 0--0 0--0 ---- xxxx 0--- uuuu x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. PIC16(L)F18326/18346 DS40001839F-page 40 PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets ― ― Bank 8 CPU CORE REGISTERS; see Table 4-2 for specifics 40Ch to 410h ― ― Unimplemented 411h TMR3L TMR3L 412h TMR3H TMR3H 413h T3CON 414h TMR3CS T3GCON TMR3GE T3GPOL T3CKPS T3GTM T3GSPM T3SYNC T3GGO/ DONE T3GVAL  2016-2022 Microchip Technology Inc. and its subsidiaries TMR4 416h PR4 417h T4CON 418h TMR5L TMR5L 419h TMR5H TMR5H 41Ah T5CON 41Bh T5GCON TMR6 41Dh PR6 41Eh T6CON 41Fh ― Legend: Note 1: 2: xxxx xxxx uuuu uuuu T3SOSC 415h 41Ch xxxx xxxx uuuu uuuu ― TMR3ON T3GSS TMR4 T4OUTPS TMR5CS TMR5GE ― ― T5GPOL T5GTM 1111 1111 1111 1111 TMR4ON T5CKPS T5GSPM 0000 0x00 uuuu uxuu 0000 0000 0000 0000 PR4 ― 0000 00-0 uuuu uu-u T4CKPS -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu T5SOSC T5SYNC T5GGO/ DONE T5GVAL ― TMR5ON T5GSS 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu TMR6 0000 0000 0000 0000 PR6 1111 1111 1111 1111 T6OUTPS TMR6ON T6CKPS Unimplemented x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. -000 0000 -000 0000 ― ― PIC16(L)F18326/18346 DS40001839F-page 41 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets ― ― Bank 9 CPU CORE REGISTERS; see Table 4-2 for specifics 48Ch to 497h ― 498h NCO1ACCL NCO1ACC 499h NCO1ACCH NCO1ACC 49Ah NCO1ACCU 49Bh NCO1INCL ― Unimplemented — ― ― ― 0000 0000 0000 0000 0000 0000 0000 0000 NCO1ACC 0000 0001 0000 0001 49Ch NCO1INCH 49Dh NCO1INCU ― ― ― ― 49Eh NCO1CON N1EN ― N1OUT N1POL ― ― 49Fh NCO1CLK ― ― ― NCO1INC N1PWS 0000 0000 0000 0000 NCO1INC ― ---- 0000 ---- 0000 N1PFM N1CKS x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. 0-00 ---0 0-00 ---0 000- --00 000- --00 DS40001839F-page 42 PIC16(L)F18326/18346 Legend: Note 1: 2: ---- 0000 ---- 0000 NCO1INC PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 10-11 CPU CORE REGISTERS; see Table 4-2 for specifics 50Ch to 51Fh ― ― Unimplemented ― ― 58Ch to 59Fh ― ― Unimplemented ― ― 60Ch ― ― Unimplemented ― ― 60Dh ― ― Unimplemented ― ― 60Eh ― ― Unimplemented ― ― 60Fh ― ― Unimplemented ― ― 610h ― ― Unimplemented ― ― 611h ― ― Unimplemented ― ― 612h ― ― Unimplemented ― ― 613h ― ― Unimplemented ― ― 614h ― ― Unimplemented ― ― 615h ― ― Unimplemented ― ― 616h ― ― Unimplemented ― ― 617h PWM5DCL 618h PWM5DCH 619h PWM5CON 61Ah PWM6DCL 61Bh PWM6DCH 61Ch PWM6CON 61Dh to 61Eh ― 61Fh PWMTMRS Bank 12  2016-2022 Microchip Technology Inc. and its subsidiaries Legend: Note 1: 2: ― PWM5DC ― ― ― ― ― PWM5DC PWM5EN ― PWM6DC xxxx xxxx uuuu uuuu PWM5OUT PWM5POL ― ― ― ― 0-00 ---- 0-00 ---- ― ― ― ― ― ― xx-- ---- uu-- ---- ― ― ― PWM6DC PWM6EN ― PWM6OUT ― PWM6POL xxxx xxxx uuuu uuuu ― Unimplemented ― ― xx-- ---- uu-- ---- ― ― 0-00 ---- 0-00 ---― P6TSEL P5TSEL x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. ― ---- 0101 ---- 0101 PIC16(L)F18326/18346 DS40001839F-page 43 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 13 CPU CORE REGISTERS; see Table 4-2 for specifics 68Ch ― ― Unimplemented ― ― 68Dh ― ― Unimplemented ― ― 68Eh ― ― Unimplemented ― ― 68Fh ― ― Unimplemented ― ― 690h ― ― Unimplemented ― ― 691h CWG1CLKCON ― ― ― ― ― ― ― ― CWG1DAT ― ― CWG1DBR ― ― 694h CWG1DBF ― ― 695h CWG1CON0 EN LD ― ― ― 696h CWG1CON1 ― ― IN ― POLD CS DAT ---- 0000 ---- 0000 DBR --00 0000 --00 0000 DBF --00 0000 --00 0000 MODE POLC 00-- -000 00-- -000 POLA --x- 0000 --x- 0000 CWG1AS0 SHUTDOWN REN ― ― 0001 01-- 0001 01-- 698h CWG1AS1 ― ― ― AS4E AS3E AS2E AS1E AS0E ---0 0000 ---0 0000 699h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000 69Ah to 69Fh ― Legend: Note 1: 2: LSAC POLB 697h ― LSBD ---- ---0 ---- ---0 Unimplemented x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. ― ― DS40001839F-page 44 PIC16(L)F18326/18346 692h 693h ― PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 14 CPU CORE REGISTERS; see Table 4-2 for specifics 70Ch ― ― Unimplemented ― ― 70Dh ― ― Unimplemented ― ― 70Eh ― ― Unimplemented ― ― 70Fh ― ― Unimplemented ― ― 710h ― ― ― ― 711h CWG2CLKCON ― ― ― ― ― ― Unimplemented ― ―  2016-2022 Microchip Technology Inc. and its subsidiaries 712h CWG2DAT ― ― 713h CWG2DBR ― ― DBR 714h CWG2DBF ― ― DBF 715h CWG2CON0 EN LD ― ― ― 716h CWG2CON1 ― ― IN ― POLD 717h CWG2AS0 SHUTDOWN REN ― CS DAT LSBD ---- ---0 ---- ---0 ---- 0000 ---- 0000 --00 0000 --00 0000 --00 0000 --00 0000 MODE POLC LSAC 00-- -000 00-- -000 POLB POLA --x- 0000 --x- 0000 ― ― 0001 01-- 0001 01-- 718h CWG2AS1 ― ― ― AS4E AS3E AS2E AS1E AS0E ---0 0000 ---0 0000 719h CWG2STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 0000 0000 0000 0000 71Ah to 71Fh ― Legend: Note 1: 2: ― Unimplemented x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. ― ― PIC16(L)F18326/18346 DS40001839F-page 45 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Banks 15-16 CPU CORE REGISTERS; see Table 4-2 for specifics 78Ch to 79FH ― ― Unimplemented ― ― 80Ch to 81Fh ― ― Unimplemented ― ― 88Ch ― ― Unimplemented ― ― 88Dh ― ― Unimplemented ― ― 88Eh ― ― Unimplemented ― ― 88Fh ― ― Unimplemented ― ― 890h ― ― Unimplemented ― ― 891h NVMADRL 892h NVMADRH Bank 17 ― 0000 0000 0000 0000 NVMADR 1000 0000 1000 0000 DS40001839F-page 46 893h NVMDATL 894h NVMDATH ― ― 895h NVMCON1 ― NVMREGS 896h NVMCON2 897h ― ― Unimplemented ― ― 898h ― ― Unimplemented ― ― 899h ― ― Unimplemented ― ― 89Ah ― ― Unimplemented ― ― 89Bh PCON0 89Ch to 89Fh ― Legend: Note 1: 2: NVMDAT 0000 0000 NVMDAT LWLO FREE WRERR WREN WR RD NVMCON2 STKOVF ― STKUNF ― RWDT RMCLR 0000 0000 --00 0000 --00 0000 -000 x000 -000 q000 0000 0000 0000 0000 RI POR BOR Unimplemented x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. 00-1 110q qq-q qquu ― ― PIC16(L)F18326/18346 NVMADR PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 18 CPU CORE REGISTERS; see Table 4-2 for specifics  2016-2022 Microchip Technology Inc. and its subsidiaries 90Ch ― ― Unimplemented ― ― 90Dh ― ― Unimplemented ― ― 90Eh ― ― Unimplemented ― ― 90Fh ― ― Unimplemented ― ― 910h ― ― ― ― 911h PMD0 SYSCMD FVRMD ― ― ― 912h PMD1 NCOMD TMR6MD TMR5MD TMR4MD TMR3MD 913h PMD2 ― DACMD ADCMD ― ― 914h PMD3 CWG2MD CWG1MD PWM6MD PWM5MD CCP4MD 915h PMD4 ― ― UART1MD ― 916h PMD5 ― ― ― CLC4MD 917h ― Unimplemented ― NVMMD CLKRMD IOCMD 00-- -000 00-- -000 TMR2MD TMR1MD TMR0MD 0--- -000 0--- -000 CMP2MD CMP1MD ― -00- --0- -00- --0- CCP3MD CCP2MD CCP1MD -000 --00 -000 --00 ― MSSP2MD MSSP1MD ― --0- --0- --0- --0- CLC3MD CLC2MD CLC1MD DSMMD ---- -000 ---- -000 Unimplemented ROI DOE ― DOZE ― 918h CPUDOZE IDLEN 919h OSCCON1 ― NOSC NDIV 91Ah OSCCON2 ― COSC CDIV 91Bh OSCCON3 CSWHOLD SOSCPWR SOSCBE ORDY NOSCR ― ― ― 0000 0--- 0000 0--- 91Ch OSCSTAT1 EXTOR HFOR ― LFOR SOR ADOR ― PLLR qq-q qq-q qq-q qq-q 91Dh OSCEN EXTOEN HFOEN ― LFOEN SOSCEN ADOEN ― ― 00-0 00-- 00-0 00-- 91Eh OSCTUNE ― ― 91Fh OSCFRQ ― ― Legend: Note 1: 2: DOZEN ― 000- -000 000- -000 -qqq 0000 -qqq 0000 -qqq 0000 -qqq 0000 HFTUN ― ― --10 0000 --10 0000 HFFRQ x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. ---- -qqq ---- -qqq PIC16(L)F18326/18346 DS40001839F-page 47 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Banks 19-27 CPU CORE REGISTERS; see Table 4-2 for specifics — — Unimplemented — — A0Ch to A6Fh — — Unimplemented — — A8Ch to AEFh — — Unimplemented — — B0Ch to B6Fh — — Unimplemented — — B8Ch to BEFh — — Unimplemented — — C0Ch to C6Fh — — Unimplemented — — C8Ch to CEFh — — Unimplemented — — D0Ch to D6Fh — — Unimplemented — — D8Ch to DEFh — — Unimplemented — — Legend: Note 1: 2: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. DS40001839F-page 48 PIC16(L)F18326/18346 98Ch to 9EFh PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 28 CPU CORE REGISTERS; see Table 4-2 for specifics E0Ch ― ― Unimplemented ― ― E0Dh ― ― Unimplemented ― ― E0Eh ― ― ― ― E0Fh PPSLOCK ― ― ― Unimplemented ― ― ― ― PPSLOCKED ---- ---0 ---- ---0 E10h INTPPS ― ― ― INTPPS ---0 0010 ---u uuuu E11h T0CKIPPS ― ― ― T0CKIPPS ---0 0010 ---u uuuu E12h T1CKIPPS ― ― ― T1CKIPPS ---0 0101 ---u uuuu E13h T1GPPS ― ― ― T1GPPS ---0 0100 ---u uuuu E14h CCP1PPS ― ― ― CCP1PPS ---1 0011 ---u uuuu E15h CCP2PPS ― ― ― CCP2PPS ---1 0101 ---u uuuu E16h CCP3PPS E17h CCP4PPS  2016-2022 Microchip Technology Inc. and its subsidiaries ― ― ― CCP3PPS ---0 0010 ---u uuuu X ― ― ― ― CCP4PPS ---1 0001 ---u uuuu ― X ― ― ― CCP4PPS ---0 0100 ---u uuuu E18h CWG1PPS ― ― ― CWG1PPS ---0 0010 ---u uuuu E19h CWG2PPS ― ― ― CWG2PPS ---0 0010 ---u uuuu E1Ah MDCIN1PPS ― ― ― MDCIN1PPS ---1 0010 ---u uuuu E1Bh MDCIN2PPS ― ― ― MDCIN2PPS ---1 0101 ---u uuuu E1Ch MDMINPPS ― ― ― MDMINPPS ---1 0011 ---u uuuu E1Dh SSP2CLKPPS E1Eh E1Fh E20h Legend: Note 1: 2: SSP2DATPPS SSP2SSPPS SSP1CLKPPS X ― ― ― ― SSP2CLKPPS ---1 0100 ---u uuuu ― X ― ― ― SSP2CLKPPS ---0 1111 ---u uuuu X ― ― ― ― SSP2DATPPS ---1 0101 ---u uuuu ― X ― ― ― SSP2DATPPS ---0 1101 ---u uuuu X ― ― ― ― SSP2SSPPS ---0 0000 ---u uuuu ― X ― ― ― SSP2SSPPS ---0 0001 ---u uuuu X ― ― ― ― SSP1CLKPPS ---1 0000 ---u uuuu ― X ― ― ― SSP1CLKPPS ---0 1110 ---u uuuu x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. PIC16(L)F18326/18346 DS40001839F-page 49 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 28 CPU CORE REGISTERS; see Table 4-2 for specifics E21h E22h SSP1DATPPS SSP1SSPPS E23h ― E24h RXPPS E25h TXPPS X ― ― ― ― SSP1DATPPS ---1 0001 ---u uuuu ― X ― ― ― SSP1DATPPS ---0 1100 ---u uuuu X ― ― ― ― SSP1SSPPS ---1 0011 ---u uuuu ― X ― ― ― SSP1SSPPS ---1 0100 ---u uuuu ― Unimplemented ― ― X ― ― ― ― RXPPS ---1 0101 ---u uuuu ― X ― ― ― RXPPS ---0 1101 ---u uuuu X ― ― ― ― TXPPS ---1 0100 ---u uuuu ― X ― ― ― TXPPS ---0 1111 ---u uuuu ― ― Unimplemented ― ― E27h ― ― Unimplemented ― ― E28h CLCIN0PPS E29h CLCIN1PPS E2Ah CLCIN2PPS E2Bh E2Ch CLCIN3PPS T3CKIPPS DS40001839F-page 50 E2Dh T3GPPS E2Eh T5CKIPPS E2Fh Legend: Note 1: 2: T5GPPS X ― ― ― ― CLCIN0PPS ---1 0011 ---u uuuu ― X ― ― ― CLCIN0PPS ---0 0010 ---u uuuu X ― ― ― ― CLCIN1PPS ---0 0100 ---u uuuu ― X ― ― ― CLCIN1PPS ---1 0011 ---u uuuu X ― ― ― ― CLCIN2PPS ---1 0001 ---u uuuu ― X ― ― ― CLCIN2PPS ---0 1100 ---u uuuu X ― ― ― ― CLCIN3PPS ---0 0101 ---u uuuu ― X ― ― ― CLCIN3PPS ---0 1101 ---u uuuu X ― ― ― ― T3CKIPPS ---1 0001 ---u uuuu ― X ― ― ― T3CKIPPS ---0 0101 ---u uuuu X ― ― ― ― T3GPPS ---1 0001 ---u uuuu ― X ― ― ― T3GPPS ---1 0100 ---u uuuu X ― ― ― ― T5CKIPPS ---1 0001 ---u uuuu ― X ― ― ― T5CKIPPS ---0 0101 ---u uuuu X ― ― ― ― T5GPPS ---1 0001 ---u uuuu ― X ― ― ― T5GPPS ---1 0100 ---u uuuu x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. PIC16(L)F18326/18346 E26h PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 29 CPU CORE REGISTERS; see Table 4-2 for specifics  2016-2022 Microchip Technology Inc. and its subsidiaries E8Dh ― ― Unimplemented ― ― E8Eh ― ― Unimplemented ― ― E8Fh ― ― Unimplemented ― ― E90h RA0PPS ― ― ― RA0PPS ---0 0000 ---u uuuu E91h RA1PPS ― ― ― RA1PPS ---0 0000 ---u uuuu E92h RA2PPS ― ― ― RA2PPS ---0 0000 ---u uuuu E93h ― E94h RA4PPS RA4PPS ---0 0000 ---u uuuu E95h RA5PPS RA5PPS ---0 0000 ---u uuuu E96h ― ― Unimplemented ― ― E97h ― ― Unimplemented ― ― E98h ― ― Unimplemented ― ― E99h ― ― Unimplemented ― ― E9Ah ― ― Unimplemented ― ― E9Bh ― ― Unimplemented ― ― E9Ch RB4PPS X ― Unimplemented ― ― ― ― X E9Dh RB5PPS RB6PPS E9Fh RB7PPS ― ― ― ― ― ― ― ― ― ― ― ― ― ― ---0 0000 ---u uuuu RB5PPS ---0 0000 ---u uuuu ― ― ― ― ― ― RB6PPS ---0 0000 ---u uuuu RB7PPS ---0 0000 ---u uuuu Unimplemented ― ― RB4PPS Unimplemented X ― ― X ― Unimplemented X ― ― X Legend: Note 1: 2: ― X ― ― X E9Eh Unimplemented ― x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. ― PIC16(L)F18326/18346 DS40001839F-page 51 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 29 CPU CORE REGISTERS; see Table 4-2 for specifics EA0h RC0PPS ― ― ― RC0PPS ---0 0000 ---u uuuu EA1h RC1PPS ― ― ― RC1PPS ---0 0000 ---u uuuu EA2h RC2PPS ― ― ― RC2PPS ---0 0000 ---u uuuu EA3h RC3PPS ― ― ― RC3PPS ---0 0000 ---u uuuu EA4h RC4PPS ― ― ― RC4PPS ---0 0000 ---u uuuu EA5h RC5PPS ― ― ― RC5PPS ---0 0000 ---u uuuu EA6h RC6PPS RC6PPS ---0 0000 ---u uuuu RC7PPS ---0 0000 ---u uuuu X ― ― X EA7h RC7PPS ― ― ― ― ― ― Unimplemented ― x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. ― ― DS40001839F-page 52 PIC16(L)F18326/18346 ― X ― ― X Legend: Note 1: 2: Unimplemented PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 30 CPU CORE REGISTERS; see Table 4-2 for specifics F0Ch ― ― Unimplemented ― ― F0Dh ― ― Unimplemented ― ― F0Eh ― ― Unimplemented ― ― F0Fh CLCDATA ― ― ― ― MLC4OUT MLC3OUT MLC2OUT MLC1OUT  2016-2022 Microchip Technology Inc. and its subsidiaries F10h CLC1CON LC1EN ― LC1OUT LC1INTP LC1INTN F11h CLC1POL LC1POL ― ― ― LC1G4POL F12h CLC1SEL0 ― ― LC1D1S --xx xxxx --uu uuuu F13h CLC1SEL1 ― ― LC1D2S --xx xxxx --uu uuuu F14h CLC1SEL2 ― ― LC1D3S --xx xxxx --uu uuuu F15h CLC1SEL3 ― ― LC1D4S F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu F1Ah CLC2CON LC2EN ― LC2OUT LC2INTP LC2INTN F1Bh CLC2POL LC2POL ― ― ― LC2G4POL F1Ch CLC2SEL0 ― ― LC2D1S --xx xxxx --uu uuuu F1Dh CLC2SEL1 ― ― LC2D2S --xx xxxx --uu uuuu F1Eh CLC2SEL2 ― ― LC2D3S --xx xxxx --uu uuuu F1Fh CLC2SEL3 ― ― LC2D4S --xx xxxx --uu uuuu Legend: Note 1: 2: LC1MODE ---- 0000 ---- 0000 LC1G3POL LC1G2POL 0-00 0000 0-00 0000 LC1G1POL --xx xxxx --uu uuuu LC2MODE LC2G3POL 0--- xxxx 0--- uuuu LC2G2POL 0-00 0000 0-00 0000 LC2G1POL x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. 0--- xxxx 0--- uuuu PIC16(L)F18326/18346 DS40001839F-page 53 TABLE 4-4: Name PIC16(L)F18346 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) PIC16(L)F18326  2016-2022 Microchip Technology Inc. and its subsidiaries TABLE 4-4: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets Bank 30 CPU CORE REGISTERS; see Table 4-2 for specifics F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu F24h CLC3CON LC3EN ― LC3OUT LC3INTP LC3INTN F25h CLC3POL LC3POL ― ― ― LC3G4POL F26h CLC3SEL0 ― ― LC3D1S --xx xxxx --uu uuuu F27h CLC3SEL1 ― ― LC3D2S --xx xxxx --uu uuuu F28h CLC3SEL2 ― ― LC3D3S --xx xxxx --uu uuuu F29h CLC3SEL3 ― ― LC3D4S F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu F2Eh CLC4CON LC4EN ― LC4OUT LC4INTP LC4INTN F2Fh CLC4POL LC4POL ― ― ― LC4G4POL LC3MODE LC3G3POL LC3G2POL 0-00 0000 0-00 0000 LC3G1POL LC4G2POL 0-00 0000 0-00 0000 LC4G1POL 0--- xxxx 0--- uuuu DS40001839F-page 54 F30h CLC4SEL0 ― ― LC4D1S --xx xxxx --uu uuuu F31h CLC4SEL1 ― ― LC4D2S --xx xxxx --uu uuuu F32h CLC4SEL2 ― ― LC4D3S --xx xxxx --uu uuuu F33h CLC4SEL3 ― ― LC4D4S F34h CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N xxxx xxxx uuuu uuuu F35h CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N xxxx xxxx uuuu uuuu F36h CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N xxxx xxxx uuuu uuuu F37h CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N xxxx xxxx uuuu uuuu Legend: Note 1: 2: --xx xxxx --uu uuuu x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. PIC16(L)F18326/18346 --xx xxxx --uu uuuu LC4MODE LC4G3POL 0--- xxxx 0--- uuuu PIC16(L)F18346 Name PIC16(L)F18326 Address SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets — — Bank 31 — only accessible from Debug Executive, unless otherwise specified CPU CORE REGISTERS; see Table 4-2 for specifics F8Ch to FE3h — FE4h(2) STATUS_SHAD FE5h(2) WREG_SHAD FE6h(2) BSR_SHAD — FE7h(2) PCLATH_SHAD — FE8h(2) FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FE9h(2) FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FEAh(2) FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu FEBh(2) FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu  2016-2022 Microchip Technology Inc. and its subsidiaries FECh — FEDh(2) STKPTR FEEh(2) TOSL FEFh(2) TOSH Legend: Note 1: 2: — — Unimplemented — — — — — Z DC C Working Register Normal (Non-ICD) Shadow — — Bank Select Register Normal (Non-ICD) Shadow Program Counter Latch High Register Normal (Non-ICD) Shadow — Unimplemented — — — ---x xxxx ---u uuuu -xxx xxxx -uuu uuuu — Current Stack pointer Top of Stack Low byte — ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu Top of Stack High byte x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Only on PIC16F18326/18346. Register accessible from both User and ICD Debugger. — ---x xxxx ---1 1111 xxxx xxxx xxxx xxxx -xxx xxxx -xxx xxxx PIC16(L)F18326/18346 DS40001839F-page 55 TABLE 4-4: PIC16(L)F18326/18346 4.3 PCL and PCLATH 4.3.2 The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 4-3 shows the five situations for the loading of the PC. FIGURE 4-3: 14 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 0 PC 6 7 8 0 PCLATH Instruction with PCL as Destination ALU Result 14 PCH PCL 0 PC 6 4 0 PCLATH GOTO, CALL 11 OPCODE 14 PCH PCL 0 PC 6 7 0 PCLATH CALLW W 14 PCH PCL 0 PC BRW 15 PC + W 14 PCH PCL PC 0 BRA 15 PC + OPCODE 4.3.1 A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care must be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, Implementing a Table Read (DS00556). 4.3.3 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care must be exercised if the table location crosses a PCL memory boundary (each 256-byte block). If using the CALL instruction, the PCH and PCL registers are loaded with the operand of the CALL instruction. PCH is loaded with PCLATH. The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 4.3.4 8 COMPUTED GOTO BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 + the signed value of the operand of the BRA instruction. MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 56 PIC16(L)F18326/18346 4.4 Stack 4.4.1 ACCESSING THE STACK The stack is accessible through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of Overflow and Underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 4-4 through Figure 4-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer and does not cause a Reset when either a Stack Overflow or Underflow occur if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Care must be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be read to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be Reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. Reference Figure 4-4 through Figure 4-7 for examples of accessing the stack. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 4-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL 0x1F  2016-2022 Microchip Technology Inc. and its subsidiaries 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) DS40001839F-page 57 PIC16(L)F18326/18346 FIGURE 4-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 4-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address  2016-2022 Microchip Technology Inc. and its subsidiaries STKPTR = 0x06 DS40001839F-page 58 PIC16(L)F18326/18346 FIGURE 4-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address  2016-2022 Microchip Technology Inc. and its subsidiaries When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 DS40001839F-page 59 PIC16(L)F18326/18346 4.5 Indirect Addressing 4.5.1 The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. TRADITIONAL/BANKED DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into four memory regions: • • • • Traditional/Banked Data Memory Linear Data Memory Program Flash Memory EEPROM FIGURE 4-8: INDIRECT ADDRESSING PIC16(L)F18326/18346 5HY$  [ [ 7UDGLWLRQDO 'DWD0HPRU\ [))) [ [))) 5HVHUYHG [))) [ /LQHDU 'DWD0HPRU\ [$) [% 5HVHUYHG )65 $GGUHVV 5DQJH [))) [ [ 3URJUDP )ODVK0HPRU\  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 60 PIC16(L)F18326/18346 FIGURE 4-9: TRADITIONAL/BANKED DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select 0x00 FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x7F  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 61 PIC16(L)F18326/18346 4.5.2 LINEAR DATA MEMORY 4.5.4 The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 4-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire Program Flash Memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location are accessible via INDF. Writing to the Program Flash Memory cannot be accomplished via the FSR/INDF interface. All instructions that access Program Flash Memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 4-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF 4.5.3 0xF6F 0xFFFF 0x7FFF DATA EEPROM MEMORY The EEPROM memory can be read or written through the NVMCON register interface (see Section 11.2 “Data EEPROM”). However, to make access to the EEPROM easier, read-only access to the EEPROM contents are also available through indirect addressing via an FSR. When the MSP of the FSR (ex: FSRxH) is set to 0x70, the lower 8-bit address value (in FSRxL) determines the EEPROM location that may be read via the INDF register). In other words, the EEPROM address range 0x00-0xFF is mapped into the FSR address space between 0x7000 and 0x70FF. Writing to the EEPROM cannot be accomplished via the FSR/INDF interface. Reads from the EEPROM through the FSR/INDF interface will require one additional instruction cycle to complete.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 62 PIC16(L)F18326/18346 5.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 5.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h, Configuration Word 2 at 8008h, Configuration Word 3 at 8009h, and Configuration Word 4 at 800Ah. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit must be maintained as a ‘1’.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 63 PIC16(L)F18326/18346 5.2 Register Definitions: Configuration Words REGISTER 5-1: CONFIGURATION WORD 1: OSCILLATORS R/P-1 U-1 R/P-1 U-1 U-1 R/P-1 FCMEN — CSWEN — — CLKOUTEN bit 13 bit 8 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 — RSTOSC2 RSTOSC1 RSTOSC0 — FEXTOSC2 FEXTOSC1 FEXTOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = ON FSCM timer enabled 0 = OFF FSCM timer disabled bit 12 Unimplemented: Read as ‘1’ bit 11 CSWEN: Clock Switch Enable bit 1 = ON Writing to NOSC and NDIV is allowed 0 = OFF The NOSC and NDIV bits cannot be changed by user software bit 10-9 Unimplemented: Read as ‘1’ bit 8 CLKOUTEN: Clock Out Enable bit If FEXTOSC = EC, HS, HT or LP, then this bit is ignored; otherwise: 1 = OFF CLKOUT function is disabled; I/O or oscillator function on OSC2 0 = ON CLKOUT function is enabled; FOSC/4 clock appears at OSC2 bit 7 Unimplemented: Read as ‘1’ bit 6-4 RSTOSC: Power-up Default Value for COSC bits This value is the Reset default value for COSC, and selects the oscillator first used by user software 111 = EXT1X EXTOSC operating per FEXTOSC bits 110 = HFINT1 HFINTOSC (1 MHz) 101 = Reserved 100 = LFINT LFINTOSC 011 = SOSC SOSC (32.768 kHz) 010 = Reserved 001 = EXT4X EXTOSC with 4x PLL; EXTOSC operating per FEXTOSC bits 000 = HFINT32 HFINTOSC (32 MHz) bit 3 Unimplemented: Read as ‘1’ bit 2-0 FEXTOSC: FEXTOSC External Oscillator Mode Selection bits 111 = ECH EC(External Clock) above 8 MHz 110 = ECM EC(External Clock) for 100 kHz to 8 MHz 101 = ECL EC(External Clock) below 100 kHz 100 = OFF Oscillator not enabled 011 = Unimplemented 010 = HS HS(Crystal oscillator) above 8 MHz 001 = XT HT(Crystal oscillator) above 100 kHz, below 8 MHz 000 = LP LP(Crystal oscillator) optimized for 32.768 kHz  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 64 PIC16(L)F18326/18346 REGISTER 5-2: CONFIGURATION WORD 2: SUPERVISORS R/P-1 R/P-1 R/P-1 U-1 R/P-1 U-1 DEBUG STVREN PPS1WAY — BORV — bit 13 bit 8 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 BOREN1 BOREN0 LPBOREN — WDTE1 WDTE0 PWRTE MCLRE bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 DEBUG: Debugger Enable bit(1) 1 = OFF Background debugger disabled; ICSPCLK and ICSPDAT are general purpose I/O pins 0 = ON Background debugger enabled; ICSPCLK and ICSPDAT are dedicated to the debugger bit 12 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = ON Stack Overflow or Underflow will cause a Reset 0 = OFF Stack Overflow or Underflow will not cause a Reset bit 11 PPS1WAY: PPSLOCK One-Way Set Enable bit 1 = ON The PPSLOCKED bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle 0 = OFF The PPSLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence) bit 10 Unimplemented: Read as ‘1’ bit 9 BORV: Brown-out Reset Voltage Selection bit(2) 1 = LOW Brown-out Reset voltage (VBOR) set to 1.9V on LF, and 2.45V on F devices 0 = HIGH Brown-out Reset voltage (VBOR) set to 2.7V The higher voltage setting is recommended for operation at or above 16 MHz. bit 8 Unimplemented: Read as ‘1’ bit 7-6 BOREN: Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit 11 = ON Brown-out Reset is enabled; SBOREN bit is ignored 10 = SLEEP Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored 01 = SBOREN Brown-out Reset is enabled according to SBOREN 00 = OFF Brown-out Reset is disabled bit 5 LPBOREN: Low-Power BOR Enable bit 1 = OFF ULPBOR is disabled 0 = ON ULPBOR is enabled bit 4 Unimplemented: Read as ‘1’ bit 3-2 WDTE: Watchdog Timer Enable bit 11 = ON WDT is enabled; SWDTEN is ignored 10 = SLEEP WDT is enabled while running and disabled in Sleep/Idle; SWDTEN is ignored 01 = SWDTEN WDT is controlled by the SWDTEN bit in the WDTCON register 00 = OFF WDT is disabled; SWDTEN is ignored bit 1 PWRTE: Power-up Timer Enable bit 1 = OFF PWRT is disabled 0 = ON PWRT is enabled bit 0 MCLRE: Master Clear (MCLR) Enable bit If LVP = 1: RA3 pin function is MCLR. If LVP = 0: 1 = ON MCLR pin is MCLR. 0 = OFF MCLR pin function is port-defined function. Note 1: 2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit must be maintained as a ‘1’. See VBOR parameter for specific trip point voltages.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 65 PIC16(L)F18326/18346 REGISTER 5-3: CONFIGURATION WORD 3: MEMORY R/P-1 (1) LVP U-1 U-1 U-1 U-1 U-1 — — — — — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = ON Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. 0 = OFF HV on MCLR/VPP must be used for programming. bit 12-2 Unimplemented: Read as ‘1’ bit 1-0 WRT: User NVM Self-Write Protection bits 11 = OFF Write protection off 10 = BOOT 0000h to 01FFh write-protected, 0200h to 3FFFh may be modified 01 = HALF 0000h to 1FFFh write-protected, 2000h to 3FFFh may be modified 00 = ALL 0000h to 3FFFh write-protected, no addresses may be modified WRT applies only to the self-write feature of the device; writing through ICSP™ is never protected. Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 66 PIC16(L)F18326/18346 REGISTER 5-4: CONFIGURATION WORD 4: CODE PROTECTION U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — CPD CP bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after Bulk Erase bit 13-2 Unimplemented: Read as ‘1’ bit 1 CPD: Data EEPROM Memory Code Protection bit 1 = OFF Data EEPROM code protection disabled 0 = ON Data EEPROM code protection enabled bit 0 CP: Program Memory Code Protection bit 1 = OFF Program Memory code protection disabled 0 = ON Program Memory code protection enabled  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 67 PIC16(L)F18326/18346 5.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data memory are controlled independently. Internal access to the program memory is unaffected by any code protection setting. 5.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Self-write writing the program memory is dependent upon the write protection setting. See Section 5.4 “Write Protection” for more information. 5.3.2 5.6 Device ID and Revision ID The 14-bit Device ID word is located at 8006h and the 14-bit Revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See Section 11.4 “NVMREG Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. DATA MEMORY PROTECTION The entire data EEPROM are protected from external reads and writes by the CPD bit in the Configuration Words. When CPD = 0, external reads and writes of EEPROM memory are inhibited and a read will return all ‘0’s. The CPU can continue to read and write EEPROM memory, regardless of the protection bit settings. 5.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT bits in Configuration Words define the size of the program memory block that is protected. 5.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 11.4.7 “NVMREG EEPROM, User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F183XX Memory Programming Specification” (DS40001738).  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 68 PIC16(L)F18326/18346 5.7 Register Definitions: Device and Revision REGISTER 5-5: DEVID: DEVICE ID REGISTER R R R R R R DEV bit 13 R R bit 8 R R R R R R DEV bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared DEV: Device ID bits Device DEVID Values PIC16F18326 11 0000 1010 0100 (30A4) PIC16LF18326 11 0000 1010 0110 (30A6) PIC16F18346 11 0000 1010 0101 (30A5) PIC16LF18346 11 0000 1010 0111 (30A7) REGISTER 5-6: REVID: REVISION ID REGISTER R-1 R-0 R R R R REV bit 13 R R bit 8 R R R R R R REV bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 Note: ‘0’ = Bit is cleared REV: Revision ID bits The upper two bits of the Revision ID Register will always read ‘10’.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 69 PIC16(L)F18326/18346 6.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the on-chip Reset circuit is shown in Figure 6-1. FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000006A 8/14/2013 ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE VPP/MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD BOR Active(1) Brown-out Reset LPBOR Reset Note 1: R LFINTOSC Power-up Timer PWRTE See Table 6-1 for BOR active conditions.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 70 PIC16(L)F18326/18346 6.1 Power-on Reset (POR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. 6.2 Brown-out Reset (BOR) The BOR circuit holds the device in Reset while VDD is below a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The Brown-out Reset module has four operating modes controlled by the BOREN bits in Configuration Words. The four operating modes are: • • • • BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 6-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset, and the BOR bit of the PCON0 register will be cleared, indicating that a Brown-out Reset condition occurred. See Figure 6-2 for more information. TABLE 6-1: BOR OPERATING MODES Instruction Execution upon: Release of POR or Wake-up from Sleep BOREN SBOREN Device Mode BOR Mode 11 X X Active In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN bits. 10 X Awake Active Waits for release of BOR (BORRDY = 1) Sleep Disabled X Active 1 01 00 0 X Disabled X X Disabled  2016-2022 Microchip Technology Inc. and its subsidiaries BOR ignored when asleep In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR Ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN bits Begins immediately (BORRDY = x) DS40001839F-page 71 PIC16(L)F18326/18346 6.2.1 BOR IS ALWAYS ON 6.2.3 When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device wake from Sleep is not delayed by the BOR Ready condition or the VDD level only when the SBOREN bit is cleared in software and the device is starting up from a non POR/BOR Reset event. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 6.2.2 BOR CONTROLLED BY SOFTWARE BOR IS OFF IN SLEEP BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR Protection is unchanged by Sleep When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep, but device wake-up will be delayed until the BOR can determine that VDD is higher than the BOR threshold. The device wake-up will be delayed until the BOR is ready. FIGURE 6-2: BROWN-OUT SITUATIONS VDD Internal Reset VBOR TPWRT(1) VDD Internal Reset VBOR < TPWRT TPWRT(1) VDD Internal Reset Note 1: 6.2.4 VBOR TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. BOR ALWAYS OFF When the BOREN bits of Configuration Word 2 are programmed to ‘00’, the BOR is always disabled. In the configuration, setting the SWBOREN bit will have no affect on BOR operation.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 72 PIC16(L)F18326/18346 6.3 Low-Power Brown-out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) circuit provides alternative protection against Brown-out conditions. When VDD falls below the LPBOR threshold, the device is held in Reset. When this occurs, the BOR bit of the PCON0 register is cleared to indicate that a Brown-out Reset occurred. The BOR bit will be cleared when either the BOR or the LPBOR circuitry detects a BOR condition. The LPBOR feature can be used with or without BOR enabled. When used while BOR is enabled, the LPBOR can be used as a secondary protection circuit in case the BOR circuit fails to detect the BOR condition. Additionally, when BOR is enabled except while in Sleep (BOREN = 10), the LPBOR circuit will hold the device in Reset while VDD is lower than the LPBOR threshold, and will also re-arm the POR. (see Figure 35-11 for LPBOR Reset voltage levels). When used without BOR enabled, the LPBOR circuit provides a single Reset trip point with the benefit of reduced current consumption. 6.3.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 6.3.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON register and to the power control block. 6.4 The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 6-2). MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 6.4.1 Note: 6.4.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.2 “PORTA Registers” for more information. 6.5 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register as well as the RWDT bit in the PCON register, are changed to indicate the WDT Reset. See Section 10.0 “Watchdog Timer (WDT)” for more information. 6.6 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table 6-4 for default conditions after a RESET instruction has occurred. 6.7 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 4.4 “Stack” for more information. 6.8 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a device Reset had just occurred. MCLR TABLE 6-2: The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. MCLR ENABLED 6.9 Power-up Timer The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, Power-up Trouble Shooting (DS00607). When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 73 PIC16(L)F18326/18346 6.10 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). MCLR must be released (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will expire. Upon bringing MCLR high, the device will begin execution after ten FOSC cycles (see Figure 6-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. The total time out will vary based on oscillator configuration and Power-up Timer Configuration. See Section 7.0, Oscillator Module for more information. FIGURE 6-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 74 PIC16(L)F18326/18346 6.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 6-3 and Table 6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during Normal Operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON0 Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during Normal Operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-0 uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu Brown-out Reset 0000h ---1 1000 00-1 11u0 Condition Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-u uuuu RESET Instruction Executed 0000h ---u uuuu uu-u u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 75 PIC16(L)F18326/18346 REGISTER 6-1: R/W-1/u SBOREN (1) BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-0-0 U-0 U-0 U-0 U-0 U-0 R-q/u Reserved — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit(1) If BOREN in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 Reserved: Bit must be maintained as ‘0’ bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: 6.12 BOREN bits are located in Configuration Words. Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) RESET Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON0 register bits are shown in Register 6-2. Hardware will change the corresponding register bit during the Reset process; if the Reset was not caused by the condition, the bit remains unchanged (Table 6-4). Software can reset the bit to the Inactive state after the restart (hardware will not reset the bit). Software may also set any PCON bit to the Active state, so that user code may be tested, but no Reset action will be generated.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 76 PIC16(L)F18326/18346 6.13 Register Definitions: Power Control REGISTER 6-2: PCON0: POWER CONTROL REGISTER 0 R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF — R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit U = Unimplemented bit, read as ‘0’ W = Writable bit u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or has been cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or has been cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) TABLE 6-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Bit 7 BORCON SBOREN Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — — — — BORRDY 76 PCON0 STKOVF STKUNF — RWDT RMCLR RI POR BOR 77 STATUS — — — TO PD Z DC C 30 WDTCON — — SWDTEN 121 WDTPS Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 77 PIC16(L)F18326/18346 7.0 OSCILLATOR MODULE 7.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 7-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic resonators. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. The RSTOSC bits of Configuration Word 1 determine the type of oscillator that will be used when the device is reset, including when it is first powered-up. The internal clock modes, LFINTOSC, HFINTOSC (set at 1 MHz), or HFINTOSC (set at 32 MHz) can be set through the RSTOSC bits.  2016-2022 Microchip Technology Inc. and its subsidiaries If an external clock source is selected, the FEXTOSC bits of Configuration Word 1 must be used in conjunction with the RSTOSC bits to select the External Clock mode. The external oscillator module can be configured in one of the following clock modes by setting the FEXTOSC bits of Configuration Word 1: 1. 2. 3. 4. 5. 6. ECL – External Clock Low-Power mode ( CxVN If CxPOL = 0 (noninverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 Unimplemented: Read as ‘0’ bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in Normal-Power, High-Speed mode 0 = Reserved. (do not use) bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 196 PIC16(L)F18326/18346 REGISTER 19-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CxPCH R/W-0/0 R/W-0/0 CxNCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-3 CxPCH: Comparator Positive Input Channel Select bits 111 = CxVP connects to VSS 110 = CxVP connects to FVR Buffer 2 101 = CxVP connects to DAC output 100 = CxVP unconnected 011 = CxVP unconnected 010 = CxVP unconnected 001 = CxVN unconnected 000 = CxVP connects to CxIN0+ pin bit 2-0 CxNCH: Comparator Negative Input Channel Select bits 111 = CxVN connects to VSS 110 = CxVN connects to FVR Buffer 2 101 = CxVN unconnected 100 = CxVN unconnected 011 = CxVN connects to CxIN3- pin 010 = CxVN connects to CxIN2- pin 001 = CxVN connects to CxIN1- pin 000 = CxVN connects to CxIN0- pin  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 197 PIC16(L)F18326/18346 REGISTER 19-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 — — — — — — MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit TABLE 19-3: Name ANSELA ANSELB(1) SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ― ― ANSA5 ANSA4 ― ANSA2 ANSA1 ANSA0 144 ANSB7 ANSB6 ANSB5 ANSB4 ― ― ― ― 150 ANSC7(1) ANSELC TRISA TRISB(1) ― ― TRISB7 TRISB6 TRISC7(1) TRISC ANSC6 (1) TRISC6 (1) CMxCON0 CxON CxOUT CMxCON1 CxINTP CxINTN ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 157 TRISA5 TRISA4 ― TRISA2 TRISA1 TRISA0 143 TRISB5 TRISB4 ― ― ― ― 149 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 155 ― CxPOL ― CxSP CxHYS CxSYNC 196 CxPCH CxNCH 197 CMOUT ― ― ― ― FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR DACCON0 DAC1EN ― DAC1OE ― DAC1PSS DACCON1 ― ― ― GIE PEIE ― ― ― ― ― INTEDG TMR6IE C2IE C1IE NVMIE SSP2IE BLC2IE TMR4IE NCO1IE 103 C1IF NVMIF TMR4IF NCO1IF 108 INTCON PIE2 PIR2 ― ― MC2OUT MC1OUT ADFVR ― DAC1NSS DAC1R 198 180 263 264 100 TMR6IF C2IF CLCINxPPS ― ― ― CLCINxPPS 162 MDMINPPS ― ― ― MDMINPPS 162 T1GPPS ― ― ― T1GPPS 162 ― ― ― CWGxAS1 Legend: Note 1: AS4E SSP2IF AS3E BLC2IF AS2E AS1E AS0E 218 — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. PIC16(L)F18346 only.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 198 PIC16(L)F18326/18346 20.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWGx) produces complementary waveforms with dead-band delay from a selection of input sources. The CWGx module has the following features: • • • • • Selectable dead-band clock source control Selectable input sources Output enable control Output polarity control Dead-band control with independent 6-bit rising and falling edge dead-band counters • Auto-shutdown control with: - Selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control 20.1 Fundamental Operation 20.2 Operating Modes The CWGx module can operate in six different modes, as specified by the MODE bits of the CWGxCON0 register: • • • • • • Half-Bridge mode Push-Pull mode Asynchronous Steering mode Synchronous Steering mode Full-Bridge mode, Forward Full-Bridge mode, Reverse All modes accept a single pulse data input, and provide up to four outputs as described in the following sections. All modes include auto-shutdown control as described in Section 20.11 “Register Definitions: CWG Control” Note: The CWG generates two output waveforms from the selected input source. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in Section 20.6 “Dead-Band Control”. It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in Section 20.7 “Auto-Shutdown Control”. FIGURE 20-1: 20.2.1 Except as noted for Full-bridge mode (Section 20.2.4 “Full-Bridge Modes”), mode changes may only be performed while EN = 0 (Register 20-1). HALF-BRIDGE MODE In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 20-1. A nonoverlap (dead-band) time is inserted between the two outputs as described in Section 20.6 “Dead-Band Control”. Steering modes are not used in Half-Bridge mode. The unused outputs, CWGxC and CWGxD, drive similar signals with polarity independently controlled by POLC and POLD, respectively. CWGx HALF-BRIDGE MODE OPERATION CWG[ clock Input source CWG[A CWG[B Falling Event Dead Band Rising Event Dead Band Rising Event Dead Band Rising Event Dead Band Falling Event Dead Band  2016-2022 Microchip Technology Inc. and its subsidiaries Falling Event Dead Band DS40001839F-page 199 PIC16(L)F18326/18346 20.2.2 PUSH-PULL MODE In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 20-2. This alternation creates the push-pull effect required for driving some transformer based power supply designs. Dead-band control is not used in Push-Pull mode. Steering modes are not used in Push-Pull mode. The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWGxA. The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with polarity controlled by POLC and POLD. FIGURE 20-2: CWGx PUSH-PULL MODE OPERATION CWG[ clock Input source CWG[A CWG[B 20.2.3 STEERING MODES In both Synchronous and Asynchronous Steering modes, the modulated input signal can be steered to any combination of four CWG outputs and a fixed-value will be presented on all the outputs not used for the PWM output. Each output has independent polarity, steering, and shutdown options. Dead-band control is not used in either Steering mode. When STRy = 0 (Register 20-5), the corresponding pin is held at the level defined by SDATy (Register 20-5). When STRy = 1, the pin is driven by the modulated input signal. The POLy bits (Register 20-2) control the signal polarity only when STRy = 1. The CWG auto-shutdown operation also applies to Steering modes as described in Section 20.11 “Register Definitions: CWG Control”. Note: Only the WGSTRy bits are synchronized; the WGSDATy (data) bits are not synchronized.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 200 PIC16(L)F18326/18346 20.2.3.1 Synchronous Steering Mode In Synchronous Steering mode (MODE bits = 001, Register 20-1), changes to steering selection registers take effect on the next rising edge of the modulated data input (Figure 20-3). In Synchronous Steering mode, the output will always produce a complete waveform. FIGURE 20-3: EXAMPLE OF SYNCHRONOUS STEERING (MODE = 001) Rising edge of input Rising edge of input CWG[ INPUT WGSTRA CWG[A CWG[A follows CWG[ input 20.2.3.2 Asynchronous Steering Mode In Asynchronous mode (MODE bits = 000, Register 20-1), steering takes effect at the end of the instruction cycle that writes to WGxSTR. In Asynchronous Steering mode, the output signal may be an incomplete waveform (Register 20-4). This operation may be useful when the user firmware needs to immediately remove a signal from the output pin. FIGURE 20-4: EXAMPLE OF ASYNCHRONOUS STEERING (MODE = 000) CWG[ INPUT End of Instruction Cycle End of Instruction Cycle WGSTRA CWG[A CWG[A follows CWG[ input 20.2.3.3 Start-up Considerations The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG output pins. This is required because all I/O pins are forced to high-impedance at Reset. The POLy bits (Register 20-2) allow the user to choose whether the output signals are active-high or activelow.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 201 PIC16(L)F18326/18346 20.2.4 FULL-BRIDGE MODES In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the data input. Dead-band control is described in Section 20.2.3 “Steering Modes” and Section 20.6 “Dead-Band Control”. Steering modes are not used with either of the Full-Bridge modes. The mode selection may be toggled between forward and reverse (changing MODE) without clearing EN. When connected as shown in Figure 20-5, the outputs are appropriate for a full-bridge motor driver. Each CWG output signal has independent polarity control, so the circuit can be adapted to high-active and low-active drivers. FIGURE 20-5: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QA QC FET Driver CWG[A CWG[B Load CWG[C FET Driver FET Driver CWG[D QB QD V-  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 202 PIC16(L)F18326/18346 20.2.4.1 Full-Bridge Forward Mode 20.2.4.2 In Full-Bridge Forward mode (MODE = 010), CWGxA is driven to its Active state and CWGxD is modulated while CWGxB and CWGxC are driven to their Inactive state, as illustrated at the top of Figure 20-6. FIGURE 20-6: Full-Bridge Reverse Mode In Full-Bridge Reverse mode (MODE = 011), CWGxC is driven to its Active state and CWGxB is modulated while CWGxA and CWGxD are driven to their Inactive state, as illustrated at the bottom of Figure 20-6. EXAMPLE OF FULL-BRIDGE OUTPUT Forward Mode Period CWG1A(2) CWG1B(2) CWG1C(2) Pulse Width CWG1D(2) (1) Reverse Mode (1) Period CWG1A(2) Pulse Width CWG1B(2) CWG1C(2) CWG1D(2) (1) Note 1: 2: 20.2.4.3 (1) A rising CWG1 data input creates a rising event on the modulated output. Output signals shown as active-high; all WGPOLy bits are clear. Direction Change in Full-Bridge Mode In Full-Bridge mode, changing MODE controls the forward/reverse direction. Changes to MODE change to the new direction on the next rising edge of the modulated input. A direction change is initiated in software by changing the MODE bits of the WGxCON0 register. The sequence is illustrated in Figure 20-7.  2016-2022 Microchip Technology Inc. and its subsidiaries • The associated active output CWGxA and the inactive output CWGxC are switched to drive in the opposite direction. • The previously modulated output CWGxD is switched to the inactive state, and the previously inactive output CWGxB begins to modulate. • CWG modulation resumes after the direction-switch dead band has elapsed. DS40001839F-page 203 PIC16(L)F18326/18346 20.2.4.4 Dead-Band Delay in Full-Bridge Mode Dead-band delay is important when either of the following conditions is true: 1. 2. The direction of the CWG output changes when the duty cycle of the data input is at or near 100%, or The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. The dead-band delay is inserted only when changing directions, and only the modulated output is affected. The statically-configured outputs (CWGxA and CWGxC) are not afforded dead band, and switch essentially simultaneously. FIGURE 20-7: Figure 20-7 shows an example of the CWG outputs changing directions from forward to reverse, at near 100% duty cycle. In this example, at time t1, the output of CWGxA and CWGxD become inactive, while output CWGxC becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shootthrough current will flow through power devices QC and QD for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for the CWG direction change from reverse to forward. If changing the CWG direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce the CWG duty cycle for one period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period CWG1A CWG1B Pulse Width CWG1C CWG1D Pulse Width TON External Switch C TOFF External Switch D Potential ShootThrough Current  2016-2022 Microchip Technology Inc. and its subsidiaries T = TOFF - TON DS40001839F-page 204 PIC16(L)F18326/18346 FIGURE 20-8: SIMPLIFIED CWGx BLOCK DIAGRAM (HALF-BRIDGE MODE, MODE = 100) 5HY$  /6$&! µ¶  µ¶  +LJK=   5LVLQJ'HDG%DQG%ORFN &:*&/2&. FZJGDWD FORFN GDWDLQ  FZJGDWD$ GDWDRXW  &:*[$ 32/$ /6%'! µ¶  µ¶  +LJK=   )DOOLQJ'HDG%DQG%ORFN FORFN  FZJGDWD% GDWDRXW GDWDLQ  &:*[% 32/% /6$&! FZJGDWD &:*'$7$ ,1387 ' 4 ( µ¶  µ¶  +LJK=   (1   &:*[& 32/& $6( &:*[336 $6( &287 $6( &287 /6%'! $XWR VKXWGRZQ VRXUFH $6( &/& µ¶  µ¶  +LJK= $6( &/& 6+87'2:1    6 4  5 32/'  &:*[' 5(1 6+87'2:1  6+87'2:1 )5((=( ' 4 FZJGDWD  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 205 PIC16(L)F18326/18346 FIGURE 20-9: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE, MODE = 101) 5HY$  /6$&! µ¶  µ¶  +LJK=    FZJGDWD$ FZJGDWD  &:*[$ 32/$ /6%'! ' 4 µ¶  4 µ¶  +LJK=    FZJGDWD%  &:*[% 32/% /6$&! FZJGDWD &:*'$7$ ,1387 ' 4 ( µ¶  µ¶  +LJK=   (1   &:*[& 32/& /6%'! $6( &:*[336 $6( &287 $6( &287 $XWR VKXWGRZQ VRXUFH $6( &/& µ¶  µ¶  +LJK=   $6( &/& 6 6+87'2:1  4  5 32/' 5(1  &:*[' 6+87'2:1  6+87'2:1 )5((=( ' 4 FZJGDWD  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 206 PIC16(L)F18326/18346 FIGURE 20-10: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES) 5HY$  02'(! $V\QFKURQRXV /6$&! 02'(! 6\QFKURQRXV µ¶  µ¶  +LJK=   FZJGDWD$   32/$ '$7$  &:*[$  675$ /6%'! µ¶  µ¶  +LJK=   FZJGDWD% '$7% FZJGDWD &:*'$7$ ,1387 '   32/%  &:*[%  675% /6$&! 4 ( µ¶  µ¶  +LJK=   (1 FZJGDWD& '$7& $6( &287  &:*[&  675& $6( &:*[336 $6( &287   32/& /6%'! $XWR VKXWGRZQ VRXUFH $6( &/& µ¶  µ¶  +LJK=   $6( &/& 6 6+87'2:1  4 5 FZJGDWD'  32/' 5(1 '$7' 6+87'2:1  6+87'2:1    &:*[' 675' )5((=( ' 4 FZJGDWD  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 207 PIC16(L)F18326/18346 FIGURE 20-11: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES) 5HY$  02'(! )RUZDUG /6$&! 02'(! 5HYHUVH 5LVLQJ'HDG%DQG%ORFN &:*&/2&. FORFN µ¶  µ¶  +LJK= VLJQDORXW VLJQDOLQ    FZJGDWD$  &:*[$ 32/$ FZJGDWD 02'(! ' /6%'! 4 4 FZJGDWD FZJGDWD µ¶  µ¶  +LJK=   &:*&/2&. VLJQDOLQ VLJQDORXW FORFN /6$&! FZJGDWD '  &:*[% 32/% )DOOLQJ'HDG%DQG%ORFN &:*['$7$ ,1387  FZJGDWD% 4 ( µ¶  µ¶  +LJK=   (1  FZJGDWD&  &:*[& 32/& /6%'! $6( &:*[336 $6( &287 $6( &287 $XWR VKXWGRZQ VRXUFH $6( &/& µ¶  µ¶  +LJK=   $6( &/& 6 6+87'2:1  4 5 FZJGDWD' 32/' 5(1   &:*[' 6+87'2:1  6+87'2:1 )5((=( ' 4 FZJGDWD  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 208 PIC16(L)F18326/18346 20.3 Clock Source 20.5.2 The clock source is used to drive the dead-band timing circuits. The CWGx module allows the following clock sources to be selected: • FOSC (system clock) • HFINTOSC (16 MHz only) When the HFINTOSC is selected the HFINTOSC will be kept running during Sleep. Therefore, CWG modes requiring dead band can operate in Sleep provided that the CWG data input is also active during Sleep. The clock sources are selected using the CS bit of the CWGxCLKCON register (Register 20-3). 20.4 Selectable Input Sources The CWG generates the output waveforms from the input sources in Table 20-1. TABLE 20-1: Source Peripheral SELECTABLE INPUT SOURCES Signal Name CWGxPPS CWG PPS input connection C1OUT Comparator 1 output C2OUT Comparator 2 output CCP1 Capture/Compare/PWM output CCP2 Capture/Compare/PWM output CCP3 Capture/Compare/PWM output CCP4 Capture/Compare/PWM output PWM5 PWM5 output PWM6 PWM6 output NCO1 Numerically Controlled Oscillator (NCO) output CLC1 Configurable Logic Cell 1 output CLC2 Configurable Logic Cell 2 output CLC3 Configurable Logic Cell 3 output CLC4 Configurable Logic Cell 4 output The input sources are selected using the DAT bits in the CWGxDAT register (Register 20-4). 20.5 Output Control Immediately after the CWG module is enabled, the complementary drive is configured with all output drives cleared. 20.5.1 CWGx OUTPUTS Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register (see Section 13.0 “Peripheral Pin Select (PPS) Module”).  2016-2022 Microchip Technology Inc. and its subsidiaries POLARITY CONTROL The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-low. Clearing the output polarity bit configures the corresponding output as active-high. However, polarity does not affect the override levels. Output polarity is selected with the POLy bits of the CWGxCON1 register. 20.6 Dead-Band Control Dead-band control provides for nonoverlapping output signals to prevent current shoot-through in power switches. The CWGx modules contain two 6-bit dead-band counters. These counters can be loaded with values that will determine the length of the dead band initiated on either the rising or falling edges of the input source. Dead-band control is used in either HalfBridge or Full-Bridge modes. The rising-edge dead-band delay is determined by the rising dead-band count register (Register 20-8, CWGxDBR) and the falling-edge dead-band delay is determined by the falling dead-band count register (Register 20-9, CWGxDBF). Dead-band duration is established by counting the CWG clock periods from zero up to the value loaded into either the rising or falling dead-band counter registers. The dead-band counters are incremented on every rising edge of the CWG clock source. 20.6.1 RISING EDGE AND REVERSE DEAD BAND In Half-Bridge mode, the rising edge dead band delays the turn-on of the CWGxA output after the rising edge of the CWG data input. In Full-Bridge mode, the reverse dead-band delay is only inserted when changing directions from Forward mode to Reverse mode, and only the modulated output CWGxB is affected. The CWGxDBR register determines the duration of the dead-band interval on the rising edge of the input source signal. This duration is from 0 to 64 periods of the CWG clock. Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed then no output will be seen on the respective output. The CWGxDBR register value is double-buffered. If EN = 0 (Register 20-1), the buffer is loaded when CWGxDBR is written. If EN = 1, then the buffer will be loaded at the rising edge, following the first falling edge of the data input after the LD bit (Register 20-1) is set. DS40001839F-page 209 PIC16(L)F18326/18346 20.6.2 FALLING EDGE AND FORWARD DEAD BAND In Half-Bridge mode, the falling edge dead band delays the turn-on of the CWGxB output at the falling edge of the CWGx data input. In Full-Bridge mode, the forward dead-band delay is only inserted when changing directions from Reverse mode to Forward mode, and only the modulated output CWGxD is affected. The CWGxDBF register determines the duration of the dead-band interval on the falling edge of the input source signal. This duration is from zero to 64 periods of the CWG clock. Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no output will be seen on the respective output. The CWGxDBF register value is double-buffered. When EN = 0 (Register 20-1), the buffer is loaded when CWGxDBF is written. If EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input after the LD (Register 20-1) is set. 20.6.3 DEAD-BAND JITTER The CWG input data signal may be asynchronous to the CWG input clock, so some jitter may occur in the observed dead band in each cycle. The maximum jitter is equal to one CWG clock period. See Equation 20-1 for details and an example. EQUATION 20-1: DEAD-BAND DELAY TIME CALCULATION 1 T DEAD – BAND_MIN = ---------------------------------  DBx  4:0> F CWG_CLOCK 1 T DEAD – BAND_MAX = ---------------------------------  DBx  4:0> + 1 F CWG_CLOCK T JITTER = T DEAD – BAND_MAX – T DEAD – BAND_MIN 1 T JITTER = --------------------------------F CWG_CLOCK T DEAD – BAND_MAX = T DEAD – BAND_MIN + T JITTER Example: DBR  4:0> = 0x0A = 10 F CWG_CLOCK = 8 MHz 1 T JITTER = ---------------8 MHz T DEAD – BAND_MIN = 125 ns  10 = 1.25  s T DEAD – BAND_MAX = 1.25  s + 0.125  s = 1.37  s  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 210 PIC16(L)F18326/18346 20.7 Auto-Shutdown Control Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. 20.7.1 SHUTDOWN The shutdown state can be entered by either of the following two methods: • Software generated • External input 20.7.1.3 Pin Override Levels The levels driven to the CWG outputs during an autoshutdown event are controlled by the LSBD and LSAC bits of the CWGxAS0 register (Register 20-6). The LSBD bits control CWGxB/D output levels, while the LSAC bits control the CWGxA/C output levels. 20.7.1.4 Auto-Shutdown Interrupts When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWGxIF flag bit of the PIR4 register is set (Register 8-11). The SHUTDOWN bit indicates when a Shutdown condition exists. The bit may be set or cleared in software or by hardware. 20.8 20.7.1.1 • Software controlled • Auto-restart Software-Generated Shutdown Setting the SHUTDOWN bit of the CWGxAS0 register will force the CWG into the Shutdown state. When auto-restart is disabled, the Shutdown state will persist as long as the SHUTDOWN bit is set. When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. 20.7.1.2 External Input Source Shutdown Any of the auto-shutdown external inputs can be selected to suspend the CWG operation. These sources are individually enabled by the ASxE bits of the CWGxAS1 register (Register 20-7). When any of the selected inputs goes active (pins are active-low), the CWG outputs will immediately switch to the override levels selected by the LSBD and LSAC bits without any software delay (Section 20.7.1.3 “Pin Override Levels”). Any of the following external input sources can be selected to cause a Shutdown condition: • • • • Comparator C1 Comparator C2 CLC2 CWGxPPS Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level persists. After an auto-shutdown event has occurred, there are two ways to resume operation: In either case, the shutdown source must be cleared before the restart can take place. That is, either the Shutdown condition must be removed, or the corresponding WGASxE bit must be cleared. 20.8.1 SOFTWARE-CONTROLLED RESTART If the REN bit of the CWGxASD0 register is clear (REN = 0), the CWGx module must be restarted after an auto-shutdown event through software. Once all auto-shutdown conditions are removed, the software must clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Note: 20.8.2 SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. AUTO-RESTART If the REN bit of the CWGxASD0 register is set (REN = 1), the CWGx module will restart from the shutdown state automatically. Once all auto-shutdown conditions are removed, the hardware will automatically clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Note:  2016-2022 Microchip Technology Inc. and its subsidiaries Auto-Shutdown Restart SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. DS40001839F-page 211 PIC16(L)F18326/18346 20.9 Operation During Sleep The CWGx module will operate during Sleep, provided that the input sources remain active. If the HFINTOSC is selected as the module clock source, dead-band generation will remain active. This will have a direct effect on the Sleep mode current. 20.10 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Configuring the CWG Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured as inputs, ensuring that the outputs are inactive during setup. External hardware may ensure that pin levels are held to safe levels. Clear the EN bit, if not already cleared. Configure the MODE bits of the CWGxCON0 register to set the output operating mode. Configure the POLy bits of the CWGxCON1 register to set the output polarities. Configure the DAT bits of the CWGxDAT register to select the data input source. If a Steering mode is selected, configure the STRy bits to select the desired output on the CWG outputs. Configure the LSBD and LSAC bits of the CWGxAS0 register to select the autoshutdown output override states (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). If auto-restart is desired, set the REN bit of CWGxAS0. If auto-shutdown is desired, configure the ASxE bits of the CWGxAS1 register to select the shutdown source. Set the desired rising and falling dead-band times with the CWGxDBR and CWGxDBF registers. Select the clock source in the CWGxCLKCON register. Set the EN bit to enable the module. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit in software to start the CWG.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 212 PIC16(L)F18326/18346 20.11 Register Definitions: CWG Control REGISTER 20-1: CWGxCON0: CWGx CONTROL REGISTER 0 R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 EN LD(1) — — — R/W-0/0 R/W-0/0 R/W-0/0 MODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Bit is set/cleared by hardware bit 7 EN: CWGx Enable bit 1 = CWGx is enabled 0 = CWGx is disabled bit 6 LD: CWG Load Buffers bit(1) 1 = Dead-band count buffers to be loaded on CWG data rising edge following first falling edge after this bit is set. 0 = Buffers remain unchanged bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 MODE: CWGx Mode bits 111 = Reserved 110 = Reserved 101 = CWG outputs operate in Push-Pull mode 100 = CWG outputs operate in Half-Bridge mode 011 = CWG outputs operate in Reverse Full-Bridge mode 010 = CWG outputs operate in Forward Full-Bridge mode 001 = CWG outputs operate in Synchronous Steering mode 000 = CWG outputs operate in Asynchronous Steering mode Note 1: This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 213 PIC16(L)F18326/18346 REGISTER 20-2: CWGxCON1: CWGx CONTROL REGISTER 1 U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IN — POLD POLC POLB POLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5 IN: CWGx Data Input Signal (read-only) bit 4 Unimplemented: Read as ‘0’ bit 3 POLD: WGxD Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 2 POLC: WGxC Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 1 POLB: WGxB Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 0 POLA: WGxA Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity REGISTER 20-3: CWGxCLKCON: CWGx CLOCK INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as ‘0’ bit 0 CS: CWG Clock Source Selection Select bits WGCLK Clock Source 0 1 FOSC HFINTOSC (remains operating during Sleep)  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 214 PIC16(L)F18326/18346 REGISTER 20-4: CWGxDAT: CWGx DATA INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 DAT: CWG Data Input Selection bits DAT Data Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CWGxPPS C1OUT C2OUT CCP1 CCP2 CCP3 CCP4 PWM5 PWM6 NCO1 CLC1 CLC2 CLC3 CLC4 Reserved Reserved  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 215 PIC16(L)F18326/18346 CWGxSTR(1): CWG STEERING CONTROL REGISTER REGISTER 20-5: R/W-0/0 R/W-0/0 OVRD OVRC R/W-0/0 R/W-0/0 OVRB OVRA R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 (2) (2) (2) STRA(2) STRD STRC STRB bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 OVRD: Steering Data D bit bit 6 OVRC: Steering Data C bit bit 5 OVRB: Steering Data B bit bit 4 OVRA: Steering Data A bit bit 3 STRD: Steering Enable bit D(2) 1 = CWGxD output has the CWGx data input waveform with polarity control from POLD bit 0 = CWGxD output is assigned to value of OVRD bit bit 2 STRC: Steering Enable bit C(2) 1 = CWGxC output has the CWGx data input waveform with polarity control from POLC bit 0 = CWGxC output is assigned to value of OVRC bit bit 1 STRB: Steering Enable bit B(2) 1 = CWGxB output has the CWGx data input waveform with polarity control from POLB bit 0 = CWGxB output is assigned to value of OVRB bit bit 0 STRA: Steering Enable bit A(2) 1 = CWGxA output has the CWGx data input waveform with polarity control from POLA bit 0 = CWGxA output is assigned to value of OVRA bit Note 1: 2: The bits in this register apply only when MODE = 00x (Register 20-1, steering modes). This bit is double-buffered when MODE = 001.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 216 PIC16(L)F18326/18346 REGISTER 20-6: CWGxAS0: CWG AUTO-SHUTDOWN CONTROL REGISTER 0 R/W/HS/SC-0/0 R/W-0/0 SHUTDOWN REN R/W-0/0 R/W-1/1 R/W-0/0 LSBD R/W-1/1 LSAC bit 7 U-0 U-0 — — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1,2) 1 = An auto-shutdown state is in effect 0 = No auto-shutdown event has occurred bit 6 REN: Auto-Restart Enable bit 1 = Auto-restart is enabled 0 = Auto-restart is disabled bit 5-4 LSBD: CWGxB and CWGxD Auto-Shutdown State Control bits 11 = A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event occurs. 10 = A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event occurs. 01 = Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs. 00 = The inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band interval when an auto-shutdown event occurs. bit 3-2 LSAC: CWGxA and CWGxC Auto-Shutdown State Control bits 11 = A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event occurs. 10 = A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event occurs. 01 = Pin is tri-stated on CWG1A/C when an auto-shutdown event occurs. 00 = The inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band interval when an auto-shutdown event occurs. bit 1-0 Unimplemented: Read as ‘0’ Note 1: 2: This bit may be written while EN = 0 (Register 20-1), to place the outputs into the shutdown configuration. The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this bit is cleared.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 217 PIC16(L)F18326/18346 REGISTER 20-7: CWGxAS1: CWG AUTO-SHUTDOWN CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — AS4E AS3E AS2E AS1E AS0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 AS4E: CWG Auto-Shutdown Source 4 (CLC4) Enable bit 1 = Auto-shutdown for CLC4 is enabled 0 = Auto-shutdown for CLC4 is disabled bit 3 AS3E: CWG Auto-Shutdown Source 3 (CLC2) Enable bit 1 = Auto-shutdown from CLC2 is enabled 0 = Auto-shutdown from CLC2 is disabled bit 2 AS2E: CWG Auto-Shutdown Source 2 (C2) Enable bit 1 = Auto-shutdown from Comparator 2 is enabled 0 = Auto-shutdown from Comparator 2 is disabled bit 1 AS1E: CWG Auto-Shutdown Source 1 (C1) Enable bit 1 = Auto-shutdown from Comparator 1 is enabled 0 = Auto-shutdown from Comparator 1 is disabled bit 0 AS0E: CWG Auto-Shutdown Source 0 (CWGxPPS) Enable bit 1 = Auto-shutdown from CWGxPPS is enabled 0 = Auto-shutdown from CWGxPPS is disabled REGISTER 20-8: CWGxDBR: CWGx RISING DEAD-BAND COUNT REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DBR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 DBR: CWG Rising Edge Triggered Dead-Band Count bits 11 1111 = 63-64 CWG clock periods 11 1110 = 62-63 CWG clock periods . . . 00 0010 = 2-3 CWG clock periods 00 0001 = 1-2 CWG clock periods 00 0000 = 0 CWG clock periods. Dead-band generation is bypassed.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 218 PIC16(L)F18326/18346 REGISTER 20-9: CWGxDBF: CWGx FALLING DEAD-BAND COUNT REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DBF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 DBF: CWG Falling Edge Triggered Dead-Band Count bits 11 1111 = 63-64 CWG clock periods 11 1110 = 62-63 CWG clock periods . . . 00 0010 = 2-3 CWG clock periods 00 0001 = 1-2 CWG clock periods 00 0000 = 0 CWG clock periods. Dead-band generation is bypassed.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 219 PIC16(L)F18326/18346 TABLE 20-2: Name TRISA SUMMARY OF REGISTERS ASSOCIATED WITH CWGx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 143 ANSELA ― ― ANSA5 ANSA4 ― ANSA2 ANSA1 ANSA0 144 TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 ― ― ― ― 149 ANSELB(1) ANSB7 ― ― ― ― 150 ANSB6 ANSB5 ANSB4 TRISC (1) TRISC7 TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 155 ANSELC ANSC7(1) ANSC6(1) ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 157 PIR4 CWG2IF CWG1IF TMR5GIF TMR5IF CCP4IF CCP3IF CCP2IF CCP1IF 110 PIE4 TMR5GIE TMR5IE CCP4IE CCP3IE CCP2IE CCP1IE CWG2IE CWG1IE CWG1CON0 EN LD ― ― ― CWG1CON1 ― ― IN ― POLD POLC POLB POLA 214 CWG1CLKCON ― ― ― ― ― ― ― CS 214 CWG1DAT ― ― ― ― CWG1STR OVRD OVRC OVRB OVRA CWG1AS0 SHUTDOWN REN CWG1AS1 ― ― CWG1DBR ― ― DBR 218 CWG1DBF ― ― DBF 219 LSBD ― AS4E MODE DAT STRD STRC AS2E 215 STRB STRA 216 ― ― 217 AS1E AS0E 218 LSAC AS3E 105 213 CWG1PPS ― ― ― CWG2CON0 EN LD ― ― ― CWG2CON1 ― ― IN ― POLD POLC POLB POLA 214 ― ― ― CS 214 CWG1PPS 162 MODE 213 CWG2CLKCON ― ― ― ― CWG2DAT ― ― ― ― CWG2STR OVRD OVRC OVRB OVRA CWG2AS0 SHUTDOWN REN CWG2AS1 ― ― CWG2DBR ― ― DBR 218 CWG2DBF ― ― DBF 219 CWG2PPS ― ― Note 1: 2: LSBD ― ― AS4E DAT STRD STRC STRB LSAC AS3E AS2E 215 STRA 216 ― ― 217 AS1E AS0E 218 CWG2PPS 162 PIC16(L)F18346 only. Unimplemented, read as ‘0’.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 220 PIC16(L)F18326/18346 21.0 CONFIGURABLE LOGIC CELL (CLC) Refer to Figure 21-1 for a simplified diagram showing signal flow through the CLCx. Possible configurations include: The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 36 input signals and, through the use of configurable gates, reduces the 36 inputs to four logic lines that drive one of eight selectable single-output logic functions. • Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR • Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset Input sources are a combination of the following: • • • • I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. FIGURE 21-1: CLCx SIMPLIFIED BLOCK DIAGRAM Rev. 10-000025C 3/6/2014 D Q LCxOUT MLCxOUT Q1 . . . LCx_in[29] LCx_in[30] LCx_in[35] to Peripherals Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] LCxEN lcxg1 lcxg2 lcxg3 Logic lcxq Function LCx_out (2) PPS Module CLCx lcxg4 LCxPOL LCxMODE Interrupt det LCXINTP LCXINTN set bit CLCxIF Interrupt det Note 1: 2: See Figure 21-2. See Figure 21-3.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 221 PIC16(L)F18326/18346 21.1 CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: • • • • Data selection Data gating Logic function selection Output polarity TABLE 21-1: CLCx DATA INPUT SELECTION LCxDyS Value CLCx Input Source 100011 [35] TMR6/PR6 match 100010 [34] TMR5 overflow 100001 [33] TMR4/PR4 match 100000 [32] TMR3 overflow Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 11111 [31] FOSC 11100 [28] ADCRC 21.1.1 11011 [27] IOCIF int flag bit There are 36 signals available as inputs to the configurable logic. 11010 [26] TMR2/PR2 match 11001 [25] TMR1 overflow Data selection is through four multiplexers as indicated on the left side of Figure 21-2. Data inputs in the figure are identified by ‘LCx_in’ signal name. 11000 [24] TMR0 overflow 10111 [23] EUSART1 (DT) output Table 21-1 correlates the input number to the actual signal for each CLC module. The column labeled ‘LCxDyS Value’ indicates the MUX selection code for the selected data input. LCxDyS is an abbreviation for the MUX select input codes: LCxD1S through LCxD4S. 10110 [22] EUSART1 (TX/CK) output 10101 [21] SDA2/SDO2 10100 [20] SCL2/SCK2 DATA SELECTION Data inputs are selected with CLCxSEL0 through CLCxSEL3 registers (Register 21-3 through Register 21-6).  2016-2022 Microchip Technology Inc. and its subsidiaries 11110 [30] HFINTOSC 11101 [29] LFINTOSC 10011 [19] SDA1/SDO1 10010 [18] SCL1/SCK1 10001 [17] PWM6 output 10000 [16] PWM5 output 01111 [15] CCP4 output 01110 [14] CCP3 output 01101 [13] CCP2 output 01100 [12] CCP1 output 01011 [11] CLKR output 01010 [10] DSM output 01001 [9] C2 output 01000 [8] C1 output 00111 [7] CLC4 output 00110 [6] CLC3 output 00101 [5] CLC2 output 00100 [4] CLC1 output 00011 [3] CLCIN3PPS 00010 [2] CLCIN2PPS 00001 [1] CLCIN1PPS 00000 [0] CLCIN0PPS DS40001839F-page 222 PIC16(L)F18326/18346 21.1.2 INPUT DATA SELECTION GATES Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. The gate can be configured to direct each input signal as inverted or noninverted data. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND of all enabled inputs. Table 21-2 summarizes the basic logic that can be obtained in gate 1 by using the Gate Logic Select bits and Gate Polarity bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the Gate Output Polarity bit. TABLE 21-2: DATA GATING LOGIC CLCxGLSy LCxGyPOL Gate Logic 0x55 1 4-input AND 0x55 0 4-input NAND 0xAA 1 4-input NOR 0xAA 0 4-input OR 0x00 0 Logic 0 0x00 1 Logic 1 21.1.3 LOGIC FUNCTION There are eight available logic functions, including: • • • • • • • • AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 21-3. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. 21.1.4 OUTPUT POLARITY The last stage in the configurable logic cell is the output polarity. Setting the LCxPOL bit of the CLCxPOL register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the Gate Polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: • • • • Gate 1: CLCxGLS0 (Register 21-7) Gate 2: CLCxGLS1 (Register 21-8) Gate 3: CLCxGLS2 (Register 21-9) Gate 4: CLCxGLS3 (Register 21-10) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. Data gating is indicated in the right side of Figure 21-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 223 PIC16(L)F18326/18346 21.2 CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR3 register will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP bit enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: • The CLCxIE bit of the PIE3 register • The LCxINTP bit of the CLCxCON register (for a rising edge detection) • The LCxINTN bit of the CLCxCON register (for a falling edge detection) • The PEIE and GIE bits of the INTCON register The CLCxIF bit of the PIR3 register, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 21.3 Output Mirror Copies Mirror copies of all LCxCON output bits are contained in the CLCDATA register. Reading this register samples the outputs of all CLCs simultaneously. This prevents any timing skew introduced by testing or reading the LCxOUT bits in the individual CLCxCON registers. 21.4 21.6 CLCx Setup Steps Follow these steps when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 through CLCxSEL3 registers (See Table 21-1). • Clear any associated ANSEL bits. • Set all TRIS bits associated with external CLC inputs. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. • Select the gate output polarities with the LCxGyPOL bits of the CLCxPOL register. • Select the desired logic function with the LCxMODE bits of the CLCxCON register. • Select the desired polarity of the logic output with the LCxPOL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). • If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. • If interrupts are desired, configure the following bits: - Set the LCxINTP bit in the CLCxCON register for rising event. - Set the LCxINTN bit in the CLCxCON register for falling event. - Set the CLCxIE bit of the PIE3 register. - Set the GIE and PEIE bits of the INTCON register. • Enable the CLCx by setting the LCxEN bit of the CLCxCON register. Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 21.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go Idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 224 PIC16(L)F18326/18346 FIGURE 21-2: LCx_in[0] INPUT DATA SELECTION AND GATING Data Selection 000000 Data GATE 1 LCx_in[35] lcxd1T LCxD1G1T lcxd1N LCxD1G1N 100011 LCxD2G1T LCxD1S LCxD2G1N LCx_in[0] lcxg1 000000 LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCx_in[35] LCxD4G1T 100011 LCxD2S LCx_in[0] LCxD4G1N 000000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N LCx_in[35] Data GATE 3 100011 lcxg3 LCxD3S LCx_in[0] (Same as Data GATE 1) Data GATE 4 000000 lcxg4 lcxd4T (Same as Data GATE 1) lcxd4N LCx_in[35] 100011 LCxD4S Note: All controls are undefined at power-up.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 225 PIC16(L)F18326/18346 FIGURE 21-3: PROGRAMMABLE LOGIC FUNCTIONS Rev. 10-000122A 7/30/2013 AND-OR OR-XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxq lcxg3 lcxg3 lcxg4 lcxg4 LCxMODE = 000 LCxMODE = 001 4-input AND S-R Latch lcxg1 lcxg1 S Q lcxq Q lcxq lcxg2 lcxg2 lcxq lcxg3 lcxg3 R lcxg4 lcxg4 LCxMODE = 010 LCxMODE = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 R R lcxg3 lcxg3 LCxMODE = 100 LCxMODE = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 J Q lcxq lcxg2 D lcxg3 LE S Q lcxq lcxg1 lcxg4 K R lcxg3 R lcxg1 LCxMODE = 110  2016-2022 Microchip Technology Inc. and its subsidiaries LCxMODE = 111 DS40001839F-page 226 PIC16(L)F18326/18346 21.7 Register Definitions: CLC Control REGISTER 21-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 LCxEN — LCxOUT LCxINTP LCxINTN R/W-0/0 R/W-0/0 R/W-0/0 LCxMODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxEN: Configurable Logic Cell Enable bit 1 = Configurable logic cell is enabled and mixing input signals 0 = Configurable logic cell is disabled and has logic zero output bit 6 Unimplemented: Read as ‘0’ bit 5 LCxOUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT. bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on CLCxOUT 0 = CLCxIF will not be set bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on CLCxOUT 0 = CLCxIF will not be set bit 2-0 LCxMODE: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K flip-flop with R 101 = Cell is 2-input D flip-flop with R 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 227 PIC16(L)F18326/18346 REGISTER 21-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: CLCxOUT Output Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as ‘0’ bit 3 LCxG4POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 2 LCxG3POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 1 LCxG2POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted bit 0 LCxG1POL: Gate 0 Output Polarity Control bit 1 = The output of gate 0 is inverted when applied to the logic cell 0 = The output of gate 0 is not inverted  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 228 PIC16(L)F18326/18346 REGISTER 21-3: CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD1S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD1S: CLCx Data 1 Input Selection bits See Table 21-1. REGISTER 21-4: CLCxSEL1: GENERIC CLCx DATA 1 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD2S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD2S: CLCx Data 2 Input Selection bits See Table 21-1. REGISTER 21-5: CLCxSEL2: GENERIC CLCx DATA 2 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD3S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD3S: CLCx Data 3 Input Selection bits See Table 21-1.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 229 PIC16(L)F18326/18346 REGISTER 21-6: CLCxSEL3: GENERIC CLCx DATA 3 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD4S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD4S: CLCx Data 4 Input Selection bits See Table 21-1. REGISTER 21-7: CLCxGLS0: GATE 0 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 0 Data 4 True (noninverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 0 0 = CLCIN3 (true) is not gated into CLCx Gate 0 bit 6 LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 0 0 = CLCIN3 (inverted) is not gated into CLCx Gate 0 bit 5 LCxG1D3T: Gate 0 Data 3 True (noninverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 0 0 = CLCIN2 (true) is not gated into CLCx Gate 0 bit 4 LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 0 0 = CLCIN2 (inverted) is not gated into CLCx Gate 0 bit 3 LCxG1D2T: Gate 0 Data 2 True (noninverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 0 0 = CLCIN1 (true) is not gated into CLCx Gate 0 bit 2 LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 0 0 = CLCIN1 (inverted) is not gated into CLCx Gate 0 bit 1 LCxG1D1T: Gate 0 Data 1 True (noninverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 0 0 = CLCIN0 (true) is not gated into CLCx Gate 0 bit 0 LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 0 0 = CLCIN0 (inverted) is not gated into CLCx Gate 0  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 230 PIC16(L)F18326/18346 REGISTER 21-8: CLCxGLS1: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 1 Data 4 True (noninverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 1 0 = CLCIN3 (true) is not gated into CLCx Gate 1 bit 6 LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 1 0 = CLCIN3 (inverted) is not gated into CLCx Gate 1 bit 5 LCxG2D3T: Gate 1 Data 3 True (noninverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 1 0 = CLCIN2 (true) is not gated into CLCx Gate 1 bit 4 LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 1 0 = CLCIN2 (inverted) is not gated into CLCx Gate 1 bit 3 LCxG2D2T: Gate 1 Data 2 True (noninverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 1 0 = CLCIN1 (true) is not gated into CLCx Gate 1 bit 2 LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 1 0 = CLCIN1 (inverted) is not gated into CLCx Gate 1 bit 1 LCxG2D1T: Gate 1 Data 1 True (noninverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 1 0 = CLCIN0 (true) is not gated into CLCx Gate 1 bit 0 LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 1 0 = CLCIN0 (inverted) is not gated into CLCx Gate 1  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 231 PIC16(L)F18326/18346 REGISTER 21-9: CLCxGLS2: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 2 Data 4 True (noninverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 2 0 = CLCIN3 (true) is not gated into CLCx Gate 2 bit 6 LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 2 0 = CLCIN3 (inverted) is not gated into CLCx Gate 2 bit 5 LCxG3D3T: Gate 2 Data 3 True (noninverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 2 0 = CLCIN2 (true) is not gated into CLCx Gate 2 bit 4 LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 2 0 = CLCIN2 (inverted) is not gated into CLCx Gate 2 bit 3 LCxG3D2T: Gate 2 Data 2 True (noninverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 2 0 = CLCIN1 (true) is not gated into CLCx Gate 2 bit 2 LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 2 0 = CLCIN1 (inverted) is not gated into CLCx Gate 2 bit 1 LCxG3D1T: Gate 2 Data 1 True (noninverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 2 0 = CLCIN0 (true) is not gated into CLCx Gate 2 bit 0 LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 2 0 = CLCIN0 (inverted) is not gated into CLCx Gate 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 232 PIC16(L)F18326/18346 REGISTER 21-10: CLCxGLS3: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 3 Data 4 True (noninverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 3 0 = CLCIN3 (true) is not gated into CLCx Gate 3 bit 6 LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 3 0 = CLCIN3 (inverted) is not gated into CLCx Gate 3 bit 5 LCxG4D3T: Gate 3 Data 3 True (noninverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 3 0 = CLCIN2 (true) is not gated into CLCx Gate 3 bit 4 LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 3 0 = CLCIN2 (inverted) is not gated into CLCx Gate 3 bit 3 LCxG4D2T: Gate 3 Data 2 True (noninverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 3 0 = CLCIN1 (true) is not gated into CLCx Gate 3 bit 2 LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 3 0 = CLCIN1 (inverted) is not gated into CLCx Gate 3 bit 1 LCxG4D1T: Gate 3 Data 1 True (noninverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 3 0 = CLCIN0 (true) is not gated into CLCx Gate 3 bit 0 LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 3 0 = CLCIN0 (inverted) is not gated into CLCx Gate 3  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 233 PIC16(L)F18326/18346 REGISTER 21-11: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit TABLE 21-3: Name ANSELA SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page ― ― ANSA5 ANSA4 ― ANSA2 ANSA1 ANSA0 144 ― ― TRISA5 TRISA4 ―(2) TRISA2 TRISA1 TRISA0 143 ANSELB(1) ANSB7 ANSB6 ANSB5 ANSB4 ― ― ― ― 150 TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 ― ― ― ― 149 ANSELC ANSC7(1) ANSC6(1) ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 157 TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 155 GIE PEIE ― ― ― ― ― INTEDG 100 OSFIF CSWIF TMR3GIF TMR3IF CLC4IF CLC3IF CLC2IF CLC1IF 109 PIE3 OSFIE CSWIE TMR3GIE TMR3IE CLC4IE CLC3IE CLC2IE CLC1IE CLC1CON LC1EN ― LC1OUT LC1INTP LC1INTN CLC1POL LC1POL ― ― ― TRISA INTCON PIR3 LC1MODE LC1G4POL LC1G3POL LC1G2POL LC1G1POL 104 227 228 CLC1SEL0 ― ― LC1D1S 229 CLC1SEL1 ― ― LC1D2S 229 CLC1SEL2 ― ― LC1D3S 229 CLC1SEL3 ― ― LC1D4S 230 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 230 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 231 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 232 CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N LC2EN ― LC2OUT LC2INTP CLC2POL LC2POL ― ― ― CLC2SEL0 ― ― LC2D1S 229 CLC2SEL1 ― ― LC2D2S 229 CLC2SEL2 ― ― LC2D3S 229 CLC2SEL3 ― ― LC2D4S 230  2016-2022 Microchip Technology Inc. and its subsidiaries LC2INTN LC2MODE 233 CLC2CON LC2G4POL LC2G3POL LC2G2POL LC2G1POL 227 228 DS40001839F-page 234 PIC16(L)F18326/18346 TABLE 21-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (CONTINUED) Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 230 CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 231 CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 232 CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 233 CLC3CON LC3EN ― LC3OUT LC3INTP CLC3POL LC3POL ― ― ― CLC3SEL0 ― ― LC3D1S 229 CLC3SEL1 ― ― LC3D2S 229 CLC3SEL2 ― ― LC3D3S 229 CLC3SEL3 ― ― LC3D4S LC3INTN LC3MODE LC3G4POL LC3G3POL LC3G2POL 227 LC3G1POL 228 230 CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 230 CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 231 CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 232 CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N CLC4CON LC4EN ― LC4OUT LC4INTP ― ― LC4INTN LC4MODE LC4G4POL LC4G3POL LC4G2POL 233 227 CLC4POL LC4POL ― CLC4SEL0 ― ― LC4D1S LC4G1POL 229 CLC4SEL1 ― ― LC4D2S 229 CLC4SEL2 ― ― LC4D3S 229 CLC4SEL3 ― ― LC4D4S 230 228 CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N 230 CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 231 CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 232 CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 233 MLC4OUT MLC3OUT MLC2OUT MLC1OUT 234 CLCDATA ― ― ― CLCIN0PPS ― ― ― CLCIN0PPS 162 CLCIN1PPS ― ― ― CLCIN1PPS 162 CLCIN2PPS ― ― ― CLCIN2PPS 162 CLCIN3PPS ― ― ― CLCIN3PPS 162 CLC1OUTPPS ― ― ― CLC1OUTPPS 162 CLC2OUTPPS ― ― ― CLC2OUTPPS 162 CLC3OUTPPS ― ― ― CLC3OUTPPS 162 CLC4OUTPPS ― ― ― CLC4OUTPPS 162 Legend: ― — = unimplemented, read as ‘0’. Shaded cells are unused by the CLC module.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 235 PIC16(L)F18326/18346 22.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 22-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 22-1: ADC BLOCK DIAGRAM 9'' $'35()! 3RVLWLYH 5HIHUHQFH 6HOHFW 9'' 5(6(59(' 95()SLQ $'15() )95%8))(5 95()SLQ $'&6! $1D 951(* 95326 $1E $'&BFON VDPSOHG LQSXW $1] ,QWHUQDO &KDQQHO ,QSXWV 1HJDWLYH 5HIHUHQFH 6HOHFW 966 $1 ([WHUQDO &KDQQHO ,QSXWV 5HY(  $'& &ORFN 6HOHFW )26&Q )RVF 'LYLGHU )5& )26& )5& 7HPS,QGLFDWRU '$&[BRXWSXW $'&&/2&.6285&( )95BEXIIHU $'& 6DPSOH&LUFXLW &+6! $')0 VHWELW$',) :ULWHWRELW *2'21( 4 ELW5HVXOW *2'21( 4  VWDUW 4 75,*6(/!  FRPSOHWH (QDEOH $'5(6+ $'5(6/ 7ULJJHU6HOHFW $'21  966 7ULJJHU6RXUFHV $872&219(56,21 75,**(5  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 236 PIC16(L)F18326/18346 22.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 22.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin will be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.0 “I/O Ports” for more information. Note: 22.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION There are several channel selections available: • Five PORTA pins (RA0-RA2, RA4-RA5) • Four PORTB pins (RB4-RB7, PIC16(L)F18346 only) • Six PORTC pins (RC0-RC5, PIC16(L)F18326) • Eight PORTC pins (RC0-RC7, PIC16(L)F18346 only) • Temperature Indicator • DAC output • Fixed Voltage Reference (FVR) • VSS (ground) The CHS bits of the ADCON0 register (Register 22-1) determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 22.2 “ADC Operation” for more information. Note: 22.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • • • • VREF+ pin VDD FVR 2.048V FVR 4.096V (Not available on LF devices) The ADNREF bit of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: • VREF- pin • VSS See Section 22.0 “Analog-to-Digital Converter (ADC) Module” for more details on the Fixed Voltage Reference. 22.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • • • • • • • FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 ADCRC (dedicated RC oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 22-2. For correct conversion, the appropriate TAD specification must be met. Refer to Table 35-13 for more information. Table 22-1 gives examples of appropriate ADC clock selections. Note: Unless using the ADCRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. It is recommended that when switching from an ADC channel of a higher voltage to a channel of a lower voltage, that the user selects the VSS channel before connecting to the channel with the lower voltage. If the ADC does not have a dedicated VSS input channel, the VSS selection (DAC1R = b'00000') through the DAC output channel can be used. If the DAC is in use, a free input channel can be connected to VSS, and can be used in place of the DAC.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 237 PIC16(L)F18326/18346 TABLE 22-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 (2) 125 ns 200 ns (2) (2) (2) FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 800 ns 1.0 s FOSC/32 010 1.0 s FOSC/64 110 2.0 s ADCRC Legend: Note 1: 2: 3: 4: x11 250 ns 1.6 s 2.0 s 3.2 s (1,4) 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 2.0 s 4.0 s 16.0 s(3) 4.0 s 8.0 s 8.0 s(3) 4.0 s (1,4) 1.0 s 500 ns (1,4) 1.0-6.0 s (3) 32.0 s(2) 16.0 s(2) (1,4) 1.0-6.0 s 64.0 s(2) (1,4) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. See TAD parameter for ADCRC source typical TAD value. These values violate the required TAD time. Outside the recommended TAD time. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 22-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 THCD Conversion Starts TACQ Holding capacitor disconnected from analog input (THCD). Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. Enable ADC (ADON bit) and Select channel (ACS bits)  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 238 PIC16(L)F18326/18346 22.1.5 INTERRUPTS 22.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 22-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the ADCRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the ADIE bit of the PIE1 register and the PEIE bit of the INTCON register must both be set and the GIE bit of the INTCON register must be cleared. If all three of these bits are set, the execution will switch to the Interrupt Service Routine (ISR). FIGURE 22-3: 10-BIT ADC CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit ADC Result (ADFM = 1) bit 0 Unimplemented: Read as ‘0’ MSB bit 7 Unimplemented: Read as ‘0’  2016-2022 Microchip Technology Inc. and its subsidiaries LSB bit 0 bit 7 bit 0 10-bit ADC Result DS40001839F-page 239 PIC16(L)F18326/18346 22.2 22.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 22.2.2 The GO/DONE bit will not be set in the same instruction that turns on the ADC. Refer to Section 22.2.5 “ADC Conversion Procedure”. COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit • Update the ADRESH and ADRESL registers with new conversion result Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 22.2.3 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the ADCRC option. When the ADCRC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than ADCRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. Note: 22.2.4 The auto-conversion feature is not available while the device is in Sleep mode. AUTO-CONVERSION TRIGGER The Auto-conversion Trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the GO/DONE bit is set by hardware. The Auto-conversion Trigger source is selected with the ADACT bits of the ADACT register. See Table 22-2 for auto-conversion sources. TABLE 22-2: Source Peripheral  2016-2022 Microchip Technology Inc. and its subsidiaries ADC AUTO-CONVERSION TABLE Description TMR0 Timer0 Overflow condition TMR1 Timer1 Overflow condition TMR3 Timer3 Overflow condition TMR5 Timer5 Overflow condition TMR2 Match between Timer2 and PR2 TMR4 Match between Timer4 and PR4 TMR6 Match between Timer6 and PR6 C1 Comparator C1 output C2 Comparator C2 output CLC1 CLC1 output CLC2 CLC2 output CLC3 CLC3 output CLC4 CLC4 output CCP1 CCP1 output CCP2 CCP2 output CCP3 CCP3 output CCP4 CCP4 output DS40001839F-page 240 PIC16(L)F18326/18346 22.2.5 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: • Select ADC conversion clock • Select voltage reference • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 22-1: ADC CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, ADCRC ;oscillator and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, ADCRC ;oscillator MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSELA ; BSF ANSELA,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 22.3 “ADC Acquisition Requirements”.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 241 PIC16(L)F18326/18346 22.3 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 22-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 22-4. The maximum recommended impedance for analog sources is 10 k. EQUATION 22-1: Assumptions: As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 22-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k  5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2µs + T C +   Temperature - 25°C   0.05µs/°C   The value for TC can be approximated with the following equations: 1 V APPLIED  1 – -------------------------- = V CHOLD n+1 2 –1 ;[1] VCHOLD charged to within 1/2 lsb –T C ----------  RC V APPLIED  1 – e  = V CHOLD   ;[2] VCHOLD charge response to VAPPLIED – Tc ---------  RC 1  ;combining [1] and [2] V APPLIED  1 – e  = V APPLIED  1 – -------------------------  n+1   2 –1 Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD  R IC + R SS + R S  ln(1/2047) = – 10pF  1k  + 7k  + 10k   ln(0.0004885) = 1.37 µs Therefore: T ACQ = 2µs + 892ns +   50°C- 25°C   0.05 µs/°C   = 4.62µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 242 PIC16(L)F18326/18346 FIGURE 22-4: ANALOG INPUT MODEL Analog Input pin Rs VDD VT  0.6V CPIN 5 pF VA RIC  1k Sampling Switch SS Rss I LEAKAGE(1) VT  0.6V CHOLD = 10 pF Ref- Legend: CHOLD CPIN 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance RSS I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC = Resistance of Sampling Switch RSS SS = Sampling Switch VT Rs = Threshold Voltage = External series resistance Note 1: FIGURE 22-5: 5 6 7 8 9 10 11 Sampling Switch (k) Refer to Table 35-4 (parameter D060). ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB Ref- Zero-Scale Transition  2016-2022 Microchip Technology Inc. and its subsidiaries 1.5 LSB Full-Scale Transition Ref+ DS40001839F-page 243 PIC16(L)F18326/18346 22.4 Register Definitions: ADC Control REGISTER 22-1: R/W-0/0 ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CHS R/W-0/0 R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 CHS: Analog Channel Select bits 111111 = FVR (Fixed Voltage Reference)(2) 111110 = DAC1 output(1) 111101 = Temperature Indicator(3) 111100 = VSS 111011 = Reserved. No channel connected. • • • 010111 = ANC7(4) 010110 = ANC6(4) 010101 = ANC5 010100 = ANC4 010011 = ANC3 010010 = ANC2 010001 = ANC1 010000 = ANC0 001111 = ANB7(4) 001110 = ANB6(4) 001101 = ANB5(4) 001100 = ANB4(4) 001011 = Reserved. No channel connected. • • • 000101 = ANA5 000100 = ANA4 000011 = Reserved. No channel connected. 000010 = ANA2 000001 = ANA1 000000 = ANA0 bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: 4: See Section 24.0 “5-bit Digital-to-Analog Converter (DAC1) Module” for more information. See Section 16.0 “Fixed Voltage Reference (FVR)” for more information. See Section 17.0 “Temperature Indicator Module” for more information. PIC16(L)F18346 only.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 244 PIC16(L)F18326/18346 REGISTER 22-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS U-0 R/W-0/0 — ADNREF R/W-0/0 bit 7 R/W-0/0 ADPREF bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS: ADC Conversion Clock Select bits 111 = ADCRC (dedicated RC oscillator) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = ADCRC (dedicated RC oscillator) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: A/D Negative Voltage Reference Configuration bit When ADON = 0, all multiplexer inputs are disconnected. 0 = VREF- is connected to AVSS 1 = VREF- is connected to external VREF- bit 1-0 ADPREF: ADC Positive Voltage Reference Configuration bits 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1) 10 = VREF+ is connected to external VREF+ pin(1) 01 = Reserved 00 = VREF+ is connected to VDD Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Table 35-13 for details.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 245 PIC16(L)F18326/18346 REGISTER 22-3: ADACT: A/D AUTO-CONVERSION TRIGGER U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADACT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 ADACT: Auto-Conversion Trigger Selection bits(1) 1111 = CCP4 1110 = CCP3 1101 = CCP2 1100 = CCP1 1011 = CLC4 1010 = CLC3 1001 = CLC2 1000 = CLC1 0111 = Comparator C2 0110 = Comparator C1 0101 = Timer2-PR2 match 0100 = Timer1 overflow(2) 0011 = Timer0 overflow(2) 0010 = Timer6-PR6 match 0001 = Timer4-PR4 match 0000 = No auto-conversion trigger selected 10000 = Timer3 overflow(2) 10001 = Timer5 overflow(2) Note 1: 2: This is a rising edge sensitive input for all sources. Trigger corresponds to when the peripheral’s interrupt flag is set.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 246 PIC16(L)F18326/18346 REGISTER 22-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 22-5: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u ADRES R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 247 PIC16(L)F18326/18346 REGISTER 22-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 22-7: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES: ADC Result Register bits Lower eight bits of 10-bit conversion result  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 248 PIC16(L)F18326/18346 TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE — — — — — INTEDG 100 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE BCL1IE TMR2IE TMR1IE 102 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF BCL1IF TMR2IF TMR1IF 107 Name INTCON TRISA TRISB(1) TRISC ANSELA ANSELB(1) ANSELC — — TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 143 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 149 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 155 ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 144 TRISC7(1) TRISC6(1) — — ADACT — ANSB7 ANSB6 ANSB5 ANSB4 — — — — 150 ANSC7(1) ANSC6(1) ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 157 GO/DONE ADON 244 ADCON0 ADCON1 (2) CHS ADFM — ADCS — — ADRESH ADRESL ADRESL FVREN FVRRDY TSEN DAC1CON1 — — — OSCSTAT1 EXTOR HFOR — ADPREF ADACT — ADRESH FVRCON ADNREF TSRNG 246 247 247 CDAFVR ADFVR DAC1R LFOR SOR 245 ADOR 180 264 — PLLR 91 Legend: — = unimplemented read as ‘0’. Shaded cells are not used for the ADC module. Note 1: PIC16(L)F18346 only. 2: Unimplemented, read as ‘1’.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 249 PIC16(L)F18326/18346 23.0 NUMERICALLY CONTROLLED OSCILLATOR (NCO1) MODULE The Numerically Controlled Oscillator (NCO1) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. The advantage of the addition method over simple counter-driven timer is that the output frequency resolution does not vary with the divider value. The NCO1 is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle. Features of the NCO1 include: • • • • • • • 20-bit increment function Fixed Duty Cycle (FDC) mode Pulse Frequency (PF) mode Output pulse-width control Multiple clock input sources Output polarity control Interrupt capability Figure 23-1 is a simplified block diagram of the NCO1 module.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 250  2016-2022 Microchip Technology Inc. and its subsidiaries FIGURE 23-1: NUMERICALLY CONTROLLED OSCILLATOR MODULE SIMPLIFIED BLOCK DIAGRAM 5HY''6%/2&.  ''6,1&8 ''6,1&+ ''6,1&/ ,1&%8)8 ,1&%8)+ ,1&%8)/ ''6,) ,QWHUUXSWHYHQW $GGHU  )26&  &/&287  1RFORFN  ' ''6$&&8 ''6$&&+ 3HULSKHUDOV 4 2YHUIORZ ''6$&&/ 4 ''6(1 ''6287ELW   ''6&.6! ''6&ORFN 2YHUIORZ 6 4 ''6336 ''632/ ''60' ''6&ORFN 5LSSOH&RXQWHU         5 4 ''63:6! 5HVHW DS40001839F-page 251 Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO1 module. They are shown for reference only and are not user accessible. PIC16(L)F18326/18346 +),1726& PIC16(L)F18326/18346 23.1 NCO1 Operation The NCO1 operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate. The accumulator will overflow with a carry periodically, which is the raw NCO1 output (NCO_overflow). This effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. See Equation 23-1. The NCO1 output can be further modified by stretching the pulse or toggling a flip-flop. The modified NCO1 output is then distributed internally to other peripherals and can optionally be output to a pin. The accumulator overflow also generates an interrupt (NCO_interrupt). The NCO1 period changes in discrete steps to create an average frequency. EQUATION 23-1: NCO1 OPERATION NCO1 Clock Frequency  Increment Value F OVERFLOW = ------------------------------------------------------------------------------------------------------------------20 2 23.1.1 NCO1 CLOCK SOURCES Clock sources available to the NCO1 include: • HFINTOSC • FOSC • LC1_out The NCO1 clock source is selected by configuring the N1CKS bits in the NCO1CLK register. 23.1.4 INCREMENT REGISTERS The increment value is stored in three registers making up a 20-bit increment. In order of LSB to MSB they are: • NCO1INCL • NCO1INCH • NCO1INCU The accumulator is a 20-bit register. Read and write access to the accumulator is available through three registers: When the NCO1 module is enabled, the NCO1INCU and NCO1INCH registers must be written first, then the NCO1INCL register. Writing to the NCO1INCL register initiates the increment buffer registers to be loaded simultaneously on the second rising edge of the NCO_clk signal. • NCO1ACCL • NCO1ACCH • NCO1ACCU The registers are readable and writable. The increment registers are double-buffered to allow value changes to be made without first disabling the NCO1 module. 23.1.3 When the NCO1 module is disabled, the increment buffers are loaded immediately after a write to the increment registers. 23.1.2 ACCUMULATOR ADDER The NCO1 adder is a full adder, which operates independently from the system clock. The addition of the previous result and the increment value replaces the accumulator value on the rising edge of each input clock.  2016-2022 Microchip Technology Inc. and its subsidiaries Note: The increment buffer registers are not user-accessible. DS40001839F-page 252 PIC16(L)F18326/18346 23.2 Fixed Duty Cycle (FDC) Mode 23.4 Output Polarity Control In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows (NCO_overflow), the output is toggled. This provides a 50% duty cycle with a constant frequency, provided that the increment value remains constant. The last stage in the NCO1 module is the output polarity. The N1POL bit in the NCO1CON register selects the output polarity. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. The FDC frequency can be calculated using Equation 23-2.The FDC frequency is half of the overflow frequency since it takes two overflow events to generate one FDC clock period. For more information, see Figure 23-2. The NCO1 output can be used internally by source code or other peripherals. Accomplish this by reading the N1OUT (read-only) bit of the NCO1CON register. EQUATION 23-2: • CWG FDC FREQUENCY The NCO1 output signal is available to the following peripherals: F fdc = F overflow  2 The FDC mode is selected by clearing the N1PFM bit in the NCO1CON register. 23.3 Pulse Frequency (PF) Mode In Pulse Frequency (PF) mode, every time the accumulator overflows (NCO_overflow), the output becomes active for one or more clock periods. Once the clock period expires, the output returns to an inactive state. This provides a pulsed output. The output becomes active on the rising clock edge immediately following the overflow event. For more information, see Figure 23-2. The value of the active and inactive states depends on the polarity bit, N1POL, in the NCO1CON register. The PF mode is selected by setting the N1PFM bit in the NCO1CON register. 23.3.1 OUTPUT PULSE-WIDTH CONTROL When operating in PF mode, the active state of the output can vary in width by multiple clock periods. Various pulse widths are selected with the N1PWS bits in the NCO1CLK register. When the selected pulse width is greater than the accumulator overflow time frame, the output of the NCO1 does not toggle.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 253 FDC OUTPUT MODE OPERATION DIAGRAM Rev. 10-000029A 11/7/2013 NCOx Clock Source NCOx Increment Value NCOx Accumulator Value NCO_overflow  2016-2022 Microchip Technology Inc. and its subsidiaries NCO_interrupt NCOx Output FDC Mode NCOx Output PF Mode NCOxPWS = 000 NCOx Output PF Mode NCOxPWS = 001 4000h 00000h 04000h 08000h 4000h FC000h 00000h 04000h 08000h 4000h FC000h 00000h 04000h 08000h PIC16(L)F18326/18346 DS40001839F-page 254 FIGURE 23-2: PIC16(L)F18326/18346 23.5 Interrupts When the accumulator overflows (NCO_overflow), the NCO1 Interrupt Flag bit, NCO1IF, of the PIR2 register is set. To enable the interrupt event (NCO_interrupt), the following bits must be set: • • • • The N1EN bit of the NCO1CON register The NCO1IE bit of the PIE2 register The PEIE bit of the INTCON register The GIE bit of the INTCON register The interrupt must be cleared by software by clearing the NCO1IF bit in the Interrupt Service Routine. 23.6 Effects of a Reset All of the NCO1 registers are cleared to zero as the result of a Reset. 23.7 Operation in Sleep The NCO1 module operates independently from the system clock and will continue to run during Sleep, provided that the clock source selected remains active. The HFINTOSC remains active during Sleep when the NCO1 module is enabled and the HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the NCO1 clock source, when the NCO1 is enabled, the CPU will go Idle during Sleep, but the NCO1 will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 255 PIC16(L)F18326/18346 23.8 NCO1 Control Registers REGISTER 23-1: NCO1CON: NCO1 CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 N1EN — N1OUT N1POL — — — N1PFM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 N1EN: NCO1 Enable bit 1 = NCO1 module is enabled 0 = NCO1 module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 N1OUT: NCO1 Output bit Displays the current output value of the NCO1 module bit 4 N1POL: NCO1 Polarity bit 1 = NCO1 output signal is inverted 0 = NCO1 output signal is not inverted bit 3-1 Unimplemented: Read as ‘0’ bit 0 N1PFM: NCO1 Output Divider mode bit 1 = NCO1 operates in Pulse Frequency mode 0 = NCO1 operates in Fixed Duty Cycle mode, divide by 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 256 PIC16(L)F18326/18346 REGISTER 23-2: R/W-0/0 NCO1CLK: NCO1 INPUT CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 N1PWS U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 N1CKS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 N1PWS: NCO1 Output Pulse Width Select bits(1, 2) 111 = NCO1 output is active for 128 input clock periods 110 = NCO1 output is active for 64 input clock periods 101 = NCO1 output is active for 32 input clock periods 100 = NCO1 output is active for 16 input clock periods 011 = NCO1 output is active for 8 input clock periods 010 = NCO1 output is active for 4 input clock periods 001 = NCO1 output is active for 2 input clock periods 000 = NCO1 output is active for 1 input clock period bit 4-2 Unimplemented: Read as ‘0’ bit 1-0 N1CKS: NCO1 Clock Source Select bits 11 =Reserved 10 = CLC1OUT 01 = FOSC 00 = HFINTOSC (16 MHz) Note 1: 2: N1PWS applies only when operating in Pulse Frequency mode. If NCO1 pulse width is greater than NCO1 overflow period, the NCO1 output does not toggle. REGISTER 23-3: R/W-0/0 NCO1ACCL: NCO1 ACCUMULATOR REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCO1ACC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCO1ACC: NCO1 Accumulator, low byte  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 257 PIC16(L)F18326/18346 REGISTER 23-4: R/W-0/0 NCO1ACCH: NCO1 ACCUMULATOR REGISTER – HIGH BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCO1ACC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 NCO1ACC: NCO1 Accumulator, high byte NCO1ACCU: NCO1 ACCUMULATOR REGISTER – UPPER BYTE(1) REGISTER 23-5: U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCO1ACC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 NCO1ACC: NCO1 Accumulator, upper byte Note 1: The accumulator spans registers NCO1ACCU:NCO1ACCH:NCO1ACCL. The 24 bits are reserved but not all are used.This register updates in real-time, asynchronously to the CPU; there is no provision to ensure atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is operating will produce undefined results. REGISTER 23-6: R/W-0/0 NCO1INCL(1,2): NCO1 INCREMENT REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 NCO1INC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: NCO1INC: NCO1 Increment, low byte The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL. NCO1INC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after writing to NCO1INCL;NCO1INCU and NCO1INCH must be written prior to writing NCO1INCL.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 258 PIC16(L)F18326/18346 NCO1INCH(1): NCO1 INCREMENT REGISTER – HIGH BYTE REGISTER 23-7: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCO1INC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: NCO1INC: NCO1 Increment, high byte The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL. NCO1INCU(1): NCO1 INCREMENT REGISTER – UPPER BYTE REGISTER 23-8: U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NCO1INC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 bit 3-0 Note 1: Unimplemented: Read as ‘0’ NCO1INC: NCO1 Increment, upper byte The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 259 PIC16(L)F18326/18346 TABLE 23-1: Name TRISA SUMMARY OF REGISTERS ASSOCIATED WITH NCO1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — TRISA5 TRISA4 —(2) Bit 0 Register on Page TRISA2 TRISA1 TRISA0 143 Bit 2 Bit 1 ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 144 TRISB(1) TRISB7 TRISB6 TRISB5 TRISB4 — — — — 149 ANSELB(1) ANSB7 ANSB6 — — — — 150 TRISC3 TRISC2 TRISC1 TRISC0 155 TRISC TRISC7 (1) (1) ANSB5 ANSB4 (1) TRISC5 TRISC4 (1) TRISC6 ANSC5 ANSC4 ANSC3 ANSC0 157 PIR2 TMR6IF C2IF C1IF NVMIF SSP2IF BCL2IF TMR4IF NCO1IF 108 PIE2 TMR6IE C2IE C1IE NVMIE SSP2IE BCL2IE TMR4IE NCO1IE 103 GIE PEIE — — — — — INTEDG 100 — N1OUT N1POL — — — N1PFM — — — N1CKS ANSELC INTCON NCO1CON ANSC7 N1EN NCO1CLK ANSC6 N1PWS ANSC2 ANSC1 256 257 NCO1ACCL NCO1ACC 257 NCO1ACCH NCO1ACC 258 NCO1ACCU — — — — NCO1ACC 258 NCO1INCL NCO1INC 258 NCO1INCH NCO1INC 259 NCO1INCU — — — — CWG1DAT — — — MDSRC — — — MDCARH — MDCARL — CCPxCAP — NCO1INC 259 — DAT 215 — MDMS 272 MDCHPOL MDCHSYNC — MDCH 273 MDCLPOL — MDCL 274 — CCPxCTS 310 — MDCLSYNC — Legend: — = unimplemented read as ‘0’. Shaded cells are not used for NCO1 module. Note 1: PIC16(L)F18346 only. 2: Unimplemented, read as ‘1’.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 260 PIC16(L)F18326/18346 24.0 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC1) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. 24.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DAC1R bits of the DAC1CON1 register. The DAC output voltage is determined by Equation 24-1: The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • ADC input channel • DAC1OUT pin The Digital-to-Analog Converter (DAC) is enabled by setting the DAC1EN bit of the DAC1CON0 register. EQUATION 24-1: DAC OUTPUT VOLTAGE  DAC1R  4:0  V OUT =   V SOURCE+ – V SOURCE-   ---------------------------------- +  V SOURCE-  5   2 V SOURCE+ = V DD or V REF+ or FVR V SOURCE- = V SS or V REF- 24.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Table 35-15. 24.3 DAC Voltage Reference Output The DAC voltage can be output to the DAC1OUT pin by setting the DAC1OE bit of the DAC1CON0 register. Selecting the DAC reference voltage for output on the DAC1OUT pin automatically overrides the digital output buffer and digital input threshold detector functions, it disables the weak pull-up and the constant-current drive function of that pin. Reading the DAC1OUT pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to the DAC1OUT pin. Figure 24-2 shows an example buffering technique.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 261 PIC16(L)F18326/18346 FIGURE 24-1: VDD DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM 00 01 VREF+ FVR_buffer2 10 Reserved 11 VSOURCE+ DAC1R 5 R DAC1PSS R DAC1EN R 32-to-1 MUX R 32 Steps DAC1_output To Peripherals R DAC1OUT R (1) DAC1OE R DAC1NSS VREF- 1 VSS VSOURCE- 0 Note 1: The unbuffered DAC1_output is provided on the DAC1OUT pin(s). FIGURE 24-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DAC1OUT  2016-2022 Microchip Technology Inc. and its subsidiaries + – Buffered DAC Output DS40001839F-page 262 PIC16(L)F18326/18346 24.4 Operation During Sleep 24.5 The DAC continues to function during Sleep. When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DAC1CON0 register are not affected. 24.6 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DAC1OUT pin. • The DAC1R range select bits are cleared. Register Definitions: DAC Control REGISTER 24-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 U-0 DAC1EN — DAC1OE — R/W-0/0 R/W-0/0 U-0 R/W-0/0 — DAC1NSS DAC1PSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DAC1EN: DAC1 Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DAC1OE: DAC1 Voltage Output 1 Enable bit 1 = DAC voltage level is output on the DAC1OUT pin 0 = DAC voltage level is disconnected from the DAC1OUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DAC1PSS: DAC1 Positive Source Select bits 11 = Reserved, do not use 10 = FVR output 01 = VREF+ pin 00 = VDD bit 1 Unimplemented: Read as ‘0’ bit 0 DAC1NSS: DAC1 Negative Source Select bits 1 = VREF- pin 0 = VSS  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 263 PIC16(L)F18326/18346 REGISTER 24-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DAC1R bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DAC1R: DAC1 Voltage Output Select bits VOUT = (VSRC+ - VSRC-)*(DAC1R/32) + VSRC TABLE 24-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE Bit 7 Bit 6 Bit 5 Bit 4 DACCON0 DAC1EN — DAC1OE — DACCON1 — — — CMxCON1 CxINTP CxINTN ADCON0 Legend: Bit 3 Bit 2 DAC1PSS Bit 1 Bit 0 — DAC1NSS DAC1R CxPCH CHS 263 264 CxNCH GO/DONE Register on page 197 ADON 244 — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 264 PIC16(L)F18326/18346 25.0 DATA SIGNAL MODULATOR (DSM) MODULE The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical “AND” operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Using this method, the DSM can generate the following types of key modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • • • • • • • Carrier Synchronization Carrier Source Polarity Select Carrier Source Pin Disable Programmable Modulator Data Modulator Source Pin Disable Modulated Output Polarity Select Slew Rate Control Figure 25-1 shows a simplified block diagram of the Data Signal Modulator peripheral.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 265 PIC16(L)F18326/18346 FIGURE 25-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR 5HY'60%/2&.  0'&+! 966 0'&,1 0'&,1 &/.5 &&3 &&3 3:0 3:0 ''6 5(6(59(' )26& +),1726& &/& &/& &/& &/&                 'DWD6LJQDO0RGXODWRU &$5+ 0'&+32/ ' 6 16 MHz D002 VDD 2.3 2.5 — — 5.5 5.5 V V FOSC  16 MHz FOSC > 16 MHz RAM Data Retention(1) D003 VDR 1.5 — — V Device in Sleep mode D003 VDR 1.7 — — V Device in Sleep mode Power-on Reset Release Voltage(2) D004 VPOR — 1.6 — V BOR and LPBOR disabled(3) D004 VPOR — 1.6 — V BOR and LPBOR disabled(3) Power-on Reset ReARM Voltage(2) D005 VPORR — 0.8 — V BOR and LPBOR disabled(3) D005 VPORR — 1.5 — V BOR and LPBOR disabled(3) VDD Rise Rate to ensure Internal Power-on Reset Signal(2) D006 SVDD 0.05 — — V/ms BOR and LPBOR disabled(3) D006 SVDD 0.05 — — V/ms BOR and LPBOR disabled(3) † Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode or during a device Reset, without losing RAM data. 2: See Figure 35-3, POR and POR ReARM with Slow Rising VDD. 3: See Table 35-11 for BOR and LPBOR trip point information.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 414 PIC16(L)F18326/18346 FIGURE 35-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 415 PIC16(L)F18326/18346 TABLE 35-2: SUPPLY CURRENT (IDD)(1,2) PIC16LF18326/18346 Standard Operating Conditions (unless otherwise stated) PIC16F18326/18346 Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Device Characteristics Min Typ. Max Units . † . Conditions VDD D100 IDDXT4 XT = 4 MHz — 321 455 uA 3.0V D100 IDDXT4 XT = 4 MHz — 332 479 uA 3.0V D101 IDDHFO16 HFO = 16 MHz — 1.3 1.8 mA 3.0V D101 IDDHFO16 HFO = 16 MHz — 1.4 1.9 mA 3.0V D102 IDDHFOPLL HFO = 32 MHz — 2.2 2.8 mA 3.0V D102 IDDHFOPLL HFO = 32 MHz — 2.3 2.9 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.2 2.8 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 2.3 2.9 mA 3.0V D104 IDDIDLE Idle Mode, HFINTOSC = 16 MHz — 804 128 3 uA 3.0V D104 IDDIDLE Idle Mode, HFINTOSC = 16 MHz — 816 128 4 uA 3.0V D105 IDDDOZE(3) Doze mode, HFO = 16 MHz, DOZE Ratio = 16 — 863 — uA 3.0V D105 IDDDOZE(3) Doze mode, HFO = 16 MHz, DOZE Ratio = 16 — 875 — uA 3.0V † Note 1: 2: 3: 4: Note 32 MHz PIC16 Typical value only, no maximum value required. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ration (see Register 9-2). PMD bits are all in the default state, no modules are disabled.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 416 PIC16(L)F18326/18346 TABLE 35-3: POWER-DOWN CURRENTS (IPD)(1,2,3) PIC16LF18326/18346 Standard Operating Conditions (unless otherwise stated) PIC16F18326/18346 Standard Operating Conditions (unless otherwise stated) VREGPM = 1 Param. No. Symbol Device Characteristics Min. Typ.† Max. Max. Units +85°C +125°C VDD Conditions Note 5.5 A 3.0V 2.5 6 A 3.0V 22 27 A 3.0V VREGPM = 0 0.9 2.9 6 A 3.0V — 1.1 3.3 6.6 A 3.0V Secondary Oscillator (SOSC) — 2.7 4 9.6 A 3.0V IPD_SOSC Secondary Oscillator (SOSC) — 3.0 6.8 10 A 3.0V IPD_FVR FVR — 40 76 76 A 3.0V 76 76 A 3.0V 17 19 A 3.0V 21 23 A 3.0V 5 13 A 3.0V 5 13 A 3.0V 0.9 5.0 13 A 3.0V 0.9 5.0 13 A 3.0V — 0.9 5 13 A 3.0V ADC is converting(4) ADC - Active — 0.9 5 13 A 3.0V ADC is converting(4) IPD_CMP Comparator — 35 45 50 A 3.0V High-Power Mode IPD_CMP Comparator — 36 44 50 A 3.0V High-Power Mode D200 IPD IPD Base — 0.05 2 D200 D200A IPD IPD Base — 0.4 — 13 D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — D201 IPD_WDT Low-Frequency Internal Oscillator/WDT D202 IPD_SOSC D202 D203 D203 IPD_FVR FVR — 33 D204 IPD_BOR Brown-out Reset (BOR) — 12 D204 IPD_BOR Brown-out Reset (BOR) — 12 D205 IPD_LPBOR Low Power Brown-out Reset (LPBOR) — 1.0 D205 IPD_LPBOR Low Power Brown-out Reset (LPBOR) — 1.2 D206 IPD_ADCA ADC - Non converting — D206 IPD_ADCA ADC - Non converting — D207 IPD_ADCA ADC - Active D207 IPD_ADCA D208 D208 † Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values may be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4: ADC clock source is ADCRC.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 417 PIC16(L)F18326/18346 TABLE 35-4: I/O PORTS(1) DC CHARACTERISTICS Param. Sym. No. VIL Standard Operating Conditions (unless otherwise stated) Characteristic Min. Typ.† Max. Units Conditions — — 0.8 V 4.5V  VDD  5.5V — — 0.15 VDD V 1.8V  VDD  4.5V — — 0.2 VDD V 2.0V  VDD  5.5V — — 0.3 VDD V Input Low Voltage I/O PORT: D300 with TTL buffer D301 D302 with Schmitt Trigger buffer I2C levels D303 with D304 with SMBus levels — — 0.8 V D305 MCLR — — 0.2 VDD V 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V 0.8 VDD — — V 2.0V  VDD  5.5V 0.7 VDD — — V 2.1 — — V 0.7 VDD — — V — ±5 ± 125 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C — ±5 ± 1000 nA VSS  VPIN  VDD, Pin at high-impedance, 125°C — ± 50 ± 200 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C 25 120 200 A VDD = 3.0V, VPIN = VSS — — 0.6 V IOL = 10.0 mA, VDD = 3.0V VDD - 0.7 — — V IOH = 6.0 mA, VDD = 3.0V — 5 50 pF VIH 2.7V  VDD  5.5V Input High Voltage I/O PORT: D320 with TTL buffer D321 D322 with Schmitt Trigger buffer I2C D323 with D324 with SMBus levels D325 MCLR IIL D340 levels Input Leakage Current(2) I/O Ports D341 MCLR(2) D342 IPUR Weak Pull-up Current VOL Voltage(3) D350 D360 I/O ports VOH D370 D380 Output Low Output High I/O ports CIO All I/O pins 2.7V  VDD  5.5V Voltage(3) † Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 418 PIC16(L)F18326/18346 TABLE 35-5: I/O AND CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units — 9 V (2) — — 600 uA (2) High Voltage Entry Programming Mode Specifications Voltage on MCLR/VPP pin to MEM01 VIHH 8 enter Programming mode MEM02 IPPGM Current on MCLR/VPP pin during Programming mode Conditions Programming Mode Specifications MEM10 VBE VDD for Bulk Erase — 2.7 — V MEM11 Supply Current during Programming Operation — — 3 mA 100k — — E/W -40°C  TA  85°C — 40 — Year VDDMIN — VDDMAX V — 4.0 5.0 ms IDDPGM Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance MEM22 TD_REF Total Erase/Write Cycles before Refresh MEM23 VD_RW VDD for Read or Erase/Write Operation MEM24 TD_BEW Byte Erase and Write Cycle Time Provided no other specifications are violated Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance 10k — — -40°C  TA  85°C E/W (1) MEM31 EPHEF High-Endurance Flash Memory Cell Endurance 100k — — E/W TBD MEM32 TP_RET Characteristic Retention — 40 — Year MEM33 VP_RD VDD for Read Operation VDDMIN — VDDMAX V VDDMIN — VDDMAX V — 2.0 2.5 ms VDD for Row Erase or Write MEM34 VP_REW Operation MEM35 TP_REW Self-Timed Row Erase or Self-Timed Write Provided no other specifications are violated † Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. 2: Required only if CONFIG3.LVP is disabled.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 419 PIC16(L)F18326/18346 TABLE 35-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 Sym. JA JC Characteristic Typ. Units Thermal Resistance Junction to Ambient 70.0 C/W 14-pin PDIP package Thermal Resistance Junction to Case TH03 TJMAX Maximum Junction Temperature TH04 PD Power Dissipation TH05 PINTERNAL Internal Power Dissipation Conditions 95.3 C/W 14-pin SOIC package 100.0 C/W 14-pin TSSOP package 51.5 C/W 16-pin UQFN/QFN/VQFN 4x4 mm package 62.2 C/W 20-pin PDIP package 87.3 C/W 20-pin SSOP package 77.7 C/W 20-pin SOIC package 43.0 C/W 20-pin UQFN 4x4 mm package 40.0 C/W 20-pin QFN/VQFN 4x4 mm package 32.75 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 24.4 C/W 14-pin TSSOP package 5.4 C/W 16-pin UQFN/QFN/VQFN 4x4 mm package 27.5 C/W 20-pin PDIP package 31.1 C/W 20-pin SSOP package 23.1 C/W 20-pin SOIC package 5.3 C/W 20-pin UQFN 4x4 mm package 21.7 C/W 20-pin QFN/VQFN 4x4 mm package 150 C 0.800 W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 420 PIC16(L)F18326/18346 35.4 AC Characteristics FIGURE 35-4: LOAD CONDITIONS Load Condition Pin CL VSS Note: CL = 50 pF for all pins. FIGURE 35-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS1 OS2 OS2 OS20 CLKOUT (CLKOUT Mode) Note: See Table 35-10.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 421 PIC16(L)F18326/18346 TABLE 35-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS(1) Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency — — 500 kHz OS2 TECL_DC Clock Duty Cycle 40 — 60 % ECM Oscillator OS3 FECM Clock Frequency — — 4 MHz OS4 TECM_DC Clock Duty Cycle 40 — 60 % ECH Oscillator OS5 FECH Clock Frequency — — 32 MHz OS6 TECH_DC Clock Duty Cycle 40 — 60 % Clock Frequency — — 100 kHz Note 4 Clock Frequency — — 4 MHz Note 4 Clock Frequency — — 20 MHz — — 32 MHz — FOSC/4 — MHz 125 1/FCY — ns LP Oscillator OS7 FLP XT Oscillator OS8 FXT HS Oscillator OS9 FHS System Clock OS20 FOSC System Clock Frequency OS21 FCY Instruction Frequency OS22 TCY Instruction Period * † Note 1: 2: 3: 4: Note 2, Note 3 These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 7.3 “Clock Switching”. The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 35.2 “Standard Operating Conditions”. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with an external square wave, one of the EC mode selections must be used.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 422 PIC16(L)F18326/18346 TABLE 35-8: OSCILLATOR PARAMETERS(1) Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions OS50 FHFOSC Precision Calibrated HFINTOSC Frequency — 4 8 12 16 32 — MHz (2) OS50 FHFOSC Precision Calibrated HFINTOSC Frequency 3.92 4 4.08 MHz 25°C OS51 FHFOSCLP Low-Power Optimized HFINTOSC Frequency 0.93 1.86 1 2 1.07 2.14 MHz MHz OS52 FMFOSC Internal Calibrated MFINTOSC Frequency — 500 — kHz OS53 FLFOSC Internal LFINTOSC Frequency — 31 — kHz OS54 THFOSCST HFINTOSC Wake-up from Sleep Start-up Time — 11 50 20 — s s OS56 TLFOSCST LFINTOSC Wake-up from Sleep Start-up Time — 0.2 — ms (3) VREGPM = 0 VREGPM = 1 * † These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 35-6: Precision Calibrated HFINTOSC/MFINTOSC Frequency Accuracy Over Device VDD and Temperature.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 423 PIC16(L)F18326/18346 FIGURE 35-6: PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 0 ± 5% -40 1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 424 PIC16(L)F18326/18346 TABLE 35-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Typ.† Max. Units Conditions 4 — 8 MHz PIC16 (Note 1) PIC16 PLL01 FPLLIN PLL02 FPLLOUT PLL Output Frequency Range 16 — 32 MHz PLL03 TPLLST PLL Lock -Time from Start-up — 200 — s PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) -0.25 — 0.25 % Note 1: PLL Input Frequency Range Min. The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002. FIGURE 35-7: Cycle CLKOUT AND I/O TIMING Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 IO12 CLKOUT IO8 IO4 IO7 IO5 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO7, IO8  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 425 PIC16(L)F18326/18346 TABLE 35-10: CLKOUT AND I/O TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions IO1* TCLKOUTH CLKOUT rising edge delay (rising edge FOSC (Q1 cycle) to falling edge CLKOUT — — 70 ns IO2* TCLKOUTL CLKOUT falling edge delay (rising edge FOSC (Q3 cycle) to rising edge CLKOUT — — 72 ns IO3* TIO_VALID Port output valid time (rising edge FOSC (Q1 cycle) to port valid) — 50 70 ns IO4* TIO_SETUP Port input setup time (Setup time before rising edge FOSC - Q2 cycle) 20 — — ns IO5* TIO_HOLD Port input hold time (Hold time after rising edge FOSC - Q2 cycle) 50 — — ns IO6* TIOR_SLREN Port I/O rise time, slew rate enabled — 25 — ns VDD = 3.0V IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled — 5 — ns VDD = 3.0V IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD = 3.0V IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD = 3.0V IO10* TINT INT pin high or low time to trigger an interrupt 25 — — ns IO11* TIOC Interrupt-on-Change minimum 25 high or low time to trigger interrupt — — ns * † These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25C unless otherwise stated.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 426 PIC16(L)F18326/18346 FIGURE 35-8: RESET, WATCHDOG TIMER, OSCILLATOR, START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST02 RST03 RST02 I/O pins Note 1: Asserted low. FIGURE 35-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device not in Brown-out Reset) (Device in Brown-out Reset) (RST08)(1) Reset (due to BOR) (RST04)(1) Note 1: 64 ms delay only if the PWRTE bit in the Configuration Word register is programmed to ‘0’.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 427 PIC16(L)F18326/18346 TABLE 35-11: RESET, WATCHDOG TIMER, OSCILLATOR, START-UP TIMER, POWER-UP TIMER, BROWN-OUT RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units RST01 TMCLR MCLR Pulse Width Low to ensure Reset 2 — — s RST02 TIOZ I/O high-impedance from Reset detection — — 2 s RST03 TWDT Watchdog Timer Time-out Period — 16 — ms RST04* TPWRT Power-up Timer Period — 65 — ms RST05 TOST Oscillator Start-up Timer Period(1,2) — 1024 — TOSC RST06 VBOR Brown-out Reset Voltage(4) 2.55 2.30 1.80 2.70 2.45 1.90 2.85 2.60 2.05 V V V RST07 VBORHYS Brown-out Reset Hysteresis — 40 — mV RST08 TBORDC Brown-out Reset Response Time — 3 — s RST09 VLPBOR Low-Power Brown-out Reset Voltage 2.3 2.45 2.7 V Conditions 16 ms Nominal Reset Time BORV = 0 BORV = 1 (PIC16F18326/18346) BORV = 1 (PIC16LF18326/18346) PIC16LF18326/18346 * † These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the Oscillator start-up timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF values in parallel are recommended.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 428 PIC16(L)F18326/18346 TABLE 35-12: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2) Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD03 EDL Differential Error — ±0.1 ±1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V AD04 EOFF Offset Error — 0.5 2 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD05 EGN Gain Error — ±0.2 ±1.0 LSb ADCREF+ = 3.0V, ADCREF- = 0V AD06 VADREF ADC Reference Voltage (ADREF+)(3) 1.8 — VDD V AD07 VAIN Full-Scale Range ADREF- — ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source — 10 — k AD09 RVREF ADC Voltage Reference Ladder Impedance — 50 — k Note 3 * † These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error is the sum of the offset, gain and integral nonlinearity (INL) errors. 2: The ADC conversion result never decreases with an increase in the input and has no missing codes. 3: This is impedance seen by the VREF pads when the external reference pads are selected.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 429 PIC16(L)F18326/18346 TABLE 35-13: ANALOG-TO DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. AD20 Sym. TAD Characteristic ADC Clock Period AD21 Min. Typ.† Max. Units Conditions 1 — 9 s This requirement is to set ADCCS correctly to produce this period/frequency 1 2 6 s Using FRC as the ADC clock source; ADOSC = 1 — 11 — TAD AD22 TCNV Conversion Time AD23 TACQ Acquisition Time — 2 — s AD24 THCD Sample and Hold Capacitor Disconnect Time — — — s FOSC based clock source — — — s FRC based clock source * † Set of GO/DONE bit to Clear of GO/DONE bit These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 35-10: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD24 1 TCY AD22 Q4 9 ADC Data 8 7 6 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD23  2016-2022 Microchip Technology Inc. and its subsidiaries Sampling Stopped DS40001839F-page 430 PIC16(L)F18326/18346 FIGURE 35-11: ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC) BSF ADCON0, GO AD24 1 TCY AD22 Q4 AD20 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD23 Sampling Stopped  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 431 PIC16(L)F18326/18346 TABLE 35-14: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C See Section 36.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. Param No. CM01 Sym. VIOFF Characteristics Input Offset Voltage Min. Typ. Max. Units — — ±50 mV Comments VICM = VDD/2 CM02 VICM Input Common Mode Range GND — VDD V CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB CM04 CHYST Comparator Hysteresis 15 25 35 mV CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns Response Time, Falling Edge — 220 500 ns CM06* TMCV2VO(2) Mode Change to Valid Output — — 10 s * Note 1: These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. A mode change includes changing any of the control register values, including module enable. 2: TABLE 35-15: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. D5B01 Sym. VLSB Characteristics Step Size Min. — Typ.† Max. Units (VDA- — V LSb Comments CREF+/-VDACREF-)/32 D5B02 VACC Absolute Accuracy — —  0.5 D5B03* RUNIT Unit Resistor Value — 5000 —  D5B04* TST Settling Time(1) — — 10 s * † These parameters are characterized but not tested. Data in “Typ” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while DACR transitions from ‘00000’ to ‘01111’. TABLE 35-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions FVR01 VFVR1 1x Gain (1.024V) -4 — +4 % VDD  2.5V, -40°C to 85°C FVR02 VFVR2 2x Gain (2.048V) -4 — +4 % VDD  2.5V, -40°C to 85°C FVR03 VFVR4 4x Gain (4.096V) -5 — +5 % VDD  4.75V, -40°C to 85°C FVR04 TFVRST FVR Start-up Time — 25 — s Note 1: Available only on PIC16F153xx.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 432 PIC16(L)F18326/18346 FIGURE 35-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 35-17: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Time Synchronous, No Prescaler 46* TT1L T1CKI Low Time Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or (TCY + 40)* N — — ns ns 0.5 TCY + 20 — — Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous Greater of: 30 or (TCY + 40)* N — — ns 47* TT1P T1CKI Input Period 48 F T1 Secondary Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * † Typ.† 60 — — ns 32.4 32.768 33.1 kHz 2 TOSC — 7 TOSC — Conditions N = prescale value (2, 4, ..., 256) Timers in Sync mode These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 433 PIC16(L)F18326/18346 FIGURE 35-13: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 35-4 for Load conditions. TABLE 35-18: CAPTURE/COMPARE/PWM CHARACTERISTICS (CCP) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. Sym. No. Characteristic CC01* TccL CCPx Input Low Time No Prescaler CC02* TccH CCPx Input High Time With Prescaler No Prescaler With Prescaler CC03* * † TccP CCPx Input Period Min. 0.5 TCY + 20 Typ.† Max. Units — — Conditions ns 20 — — ns 0.5 TCY + 20 — — ns 20 — — ns (3 TCY + 40)* N — — ns N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 434 PIC16(L)F18326/18346 FIGURE 35-14: CLC PROPAGATION TIMING CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC01 CLC02 CLC03 Note 1: See Figure 21-1, "CLCx Simplified Block Diagram" to identify specific CLC signals. TABLE 35-19: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions CLC01* TCLCIN CLC input time (CKCxIN[n]) to CKC module Input select (LCx_in[n]) propagation time — 7 IO5 ns (Note 1) CLC02* TCLC CLC module input to output propagation delay — — 24 12 — — ns ns VDD = 1.8V VDD > 3.6V CLC03* TCLCOUT CLC output time Rise Time — IO7 — — Rise Time (Note 1) Fall Time — IO8 — — Fall Time (Note 1) — 32 FOSC MHz CLC04* FCLCMAX CLC maximum switching frequency * † These parameters are characterized but not tested. Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Table 35-10 for rise and fall times. FIGURE 35-15: EUSART SYNCHRONOUS TRANSMISSION (HOST/CLIENT) TIMING CK US121 US121 DT US120 Note: US122 Refer to Figure 35-4 for Load conditions.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 435 PIC16(L)F18326/18346 TABLE 35-20: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. No. US120 Symbol Characteristic TCKH2DTV Min. Max. Units Conditions SYNC XMIT (Host and Client) Clock high to data-out valid — 80 ns 3.0V 5.5V — 100 ns 1.8V  5.5V 45 ns 3.0V  5.5V US121 TCKRF Clock out rise time and fall time (Host mode) — — 50 ns 1.8V  5.5V US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  5.5V — 50 ns 1.8V  5.5V FIGURE 35-16: EUSART SYNCHRONOUS RECEIVE (HOST/CLIENT) TIMING CK US125 DT US126 Note: Refer to Figure 35-4 for Load conditions. TABLE 35-21: EUSART SYNCHRONOUS RECEIVE CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param. No. Symbol Characteristic Min. Max. Units US125 TDTV2CKL SYNC RCV (Host and Client) Data-hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns  2016-2022 Microchip Technology Inc. and its subsidiaries Conditions DS40001839F-page 436 PIC16(L)F18326/18346 FIGURE 35-17: SPI HOST MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 35-4 for Load conditions. FIGURE 35-18: SPI HOST MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 SP78 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 35-4 for Load conditions.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 437 PIC16(L)F18326/18346 FIGURE 35-19: SPI CLIENT MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 35-4 for Load conditions. FIGURE 35-20: SS SPI CLIENT MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 35-4 for Load conditions.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 438 PIC16(L)F18326/18346 TABLE 35-22: SPI MODE CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ.† Max. Units Conditions SP70* TSSL2SCH, TSSL2SCL SS to SCK or SCK 2.25*TCY — — ns SP71* TSCH SCK input high time (Client mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Client mode) TCY + 20 — — ns SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 — — ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 — — ns SP75* TDOR SDO data output rise time — 10 25 ns 3.0V  5.5V — 25 50 ns 1.8V  5.5V SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Host mode) — 10 25 ns 3.0V  5.5V — 25 50 ns 1.8V  5.5V SP79* TSCF SCK output fall time (Host mode) — 10 25 ns SP80* TSCH2DOV, SDO data output valid after SCK TSCL2DOV edge — — 50 ns 3.0V  5.5V 1.8V  5.5V SP81* TDOV2SCH, SDO data output setup to SCK TDOV2SCL edge SP82* TSSL2DOV SP83* TSCH2SSH, SS after SCK edge TSCL2SSH SDO data output valid after SS edge — — 145 ns 1 Tcy — — ns — — 50 ns 1.5 TCY + 40 — — ns * These parameters are characterized but not tested. † Data in “Typ.” column are at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 439 PIC16(L)F18326/18346 FIGURE 35-21: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 35-4 for Load conditions. TABLE 35-23: I2C BUS START/STOP BITS CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition 100 kHz mode Typ. Max. Units 4700 — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — 100 kHz mode 4000 — — 400 kHz mode 600 — — Hold time * Min. Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 35-22: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 35-4 for Load conditions.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 440 PIC16(L)F18326/18346 TABLE 35-24: I2C BUS DATA CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5 TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module SP102* TR SP103* TF SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* TBUF SP111 * Note 1: 2: CB 1.5 TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns SDA and SCL fall time 100 kHz mode — 250 ns 400 kHz mode 20 + 0.1 CB 250 ns Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 441 PIC16(L)F18326/18346 36.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 442 PIC16(L)F18326/18346 4.2 4.2 4.1 4.1 Time (ms) Time (ms) Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 4.0 4.0 3.9 3.9 Typical 25°C Typical 25°C ı-40°C to +125°C) ı-40°C to +125°C) -ı-40°C to +125°C) -ı-40°C to +125°C) 3.8 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 36-1: WDT Time-Out Period (PIC16F18326/46 only) FIGURE 36-2: WDT Time-Out Period (PIC16LF18326/46 only) 1.0 600 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 0.9 Max. 500 Max. 0.8 0.7 0.6 IPD (µA) IPD (nA) 400 300 Typical 0.5 0.4 200 0.3 0.2 Typical 100 0.1 0.0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.6 3.8 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 36-3: IPD Base, Low-Power Sleep Mode (PIC16LF18326/46 only) FIGURE 36-4: IPD, Watchdog Timer (WDT) (PIC16LF18326/46 only) 1.4 60 Max: 85°C + 3ı Typical: 25°C 1.2 Max: 85°C + 3ı Typical: 25°C 55 Max. 50 1.0 IPD (µA) IPD (µA) 45 Typical 0.8 40 35 Max. 0.6 30 0.4 Typical 25 0.2 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-5: IPD, Watchdog Timer (WDT) (PIC16F18326/46 only) DS40001839F-page 443 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-6: IPD, Fixed Voltage Reference (FVR) (PIC16LF18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 60 14 Max: 85°C + 3ı Typical: 25°C 55 Max: 85°C + 3ı Typical: 25°C 13 50 45 IPD (µA) 12 Idd (µA) 40 Max. 35 11 30 Typical 25 10 Typical 20 9 15 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 8 6.0 1.6 1.8 2.0 2.2 2.4 2.6 FIGURE 36-7: IPD, Fixed Voltage Reference (FVR) (PIC16F18326/46 only) 3.0 3.2 3.4 3.6 3.8 FIGURE 36-8: IPD, Brown-Out Reset (BOR), BORV = 1 (PIC16LF18326/46 only) 1.2 16 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 14 1 12 0.8 IPD (nA) IPD (µA) 2.8 VDD (V) VDD (V) Typical 10 Max. 0.6 8 0.4 6 0.2 4 0 Typical 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 VDD (V) 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-9: IPD, Brown-Out Reset (BOR), BORV = 1 (PIC16F18326/46 only) FIGURE 36-10: IPD, Low-Power Brown-Out Reset (LPBOR = 1)(PIC16LF18326/46 only) 1.4 40 Max: 85°C + 3ı Typical: 25°C Max. Max: 85°C + 3ı Typical: 25°C 38 1.2 36 1.0 Max. 0.8 IPD (µA) IPD (µA) 34 0.6 Typical 32 Typical 30 0.4 28 0.2 26 0.0 24 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-11: IPD, Low-Power Brown-Out Reset (LPBOR = 0)(PIC16F18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-12: IPD, Comparator (PIC16LF18326/46 only) DS40001839F-page 444 PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 40 30 Max: 85°C + 3ı Typical: 25°C 39 Max: 85°C + 3ı Typical: 25°C 38 37 Max. 20 IPD (µA) 36 IPD (µA) Max. 25 35 34 Typical Typical 15 10 33 32 5 31 0 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 6.0 2.5 3.0 3.5 VDD (V) FIGURE 36-13: IPD, Comparator (PIC16F18326/46 only) 1 5.0 5.5 6.0 500 Max. Max: 85°C + 3ı Typical: 25°C 450 0.8 400 0.7 350 Max 0.6 300 IDD (µA) IPD (µA) 4.5 FIGURE 36-14: IPD Base, VREGPM = 0, (PIC16F18326/46 only) Max: 85°C + 3ı Typical: 25°C 0.9 4.0 VDD (V) Typical 0.5 0.4 Typical 250 200 0.3 150 0.2 100 0.1 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 1.6 VDD (V) FIGURE 36-15: IPD Base, VREGPM = 1, (PIC16F18326/46 only) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 36-16: IDD, XT Oscillator 4 MHz (PIC16LF18326/46 only) 4.0 500 450 1.8 Max: 85°C + 3ı Typical: 25°C 3.5 Max 400 Max: 85°C + 3ı Typical: 25°C 3.0 Typical 350 2.5 IDD (MA) IDD (µA) 300 250 200 Max 2.0 Typical 1.5 150 1.0 100 0.5 50 0.0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FIGURE 36-17: IDD, XT Oscillator 4 MHz (PIC16F18326/46 only) DS40001839F-page 445 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 36-18: IDD, HS Oscillator 32 MHz (PIC16LF18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 4.0 4.0 Max: 85°C + 3ı Typical: 25°C 3.5 Max: 85°C + 3ı Typical: 25°C 3.5 3.0 3.0 Max Max 2.5 IDD (MA) IDD (MA) 2.5 2.0 Typical 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0.0 Typical 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FIGURE 36-19: IDD, HS Oscillator 32 MHz (PIC16F18326/46 only) 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 36-20: IDD, HFINTOSC Mode, FOSC = 32 MHz (PIC16LF18326/46 only) 4.0 2.0 Max: 85°C + 3ı Typical: 25°C 3.5 Max: 85°C + 3ı Typical: 25°C 1.8 1.6 Max 3.0 1.4 Max 1.2 IDD (MA) IDD (MA) 2.5 Typical 2.0 1.0 Typical 0.8 1.5 0.6 1.0 0.4 0.5 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 5.5 FIGURE 36-21: IDD, HFINTOSC Mode, FOSC = 32 MHz (PIC16F18326/46 only) 1.6 2.0 2.2 2.4 2.8 3.0 3.2 3.4 3.6 3.8 1,200 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C Max 1,000 1.6 1.4 Max 800 TypicalIDD (µA) 1.2 IDD (MA) 2.6 FIGURE 36-22: IDD, HFINTOSC Mode, FOSC = 16 MHz (PIC16LF18326/46 only) 2.0 1.8 1.8 1.0 600 Typical 0.8 400 0.6 0.4 200 0.2 0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FIGURE 36-23: IDD, HFINTOSC Mode, FOSC = 16 MHz (PIC16F18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 36-24: IDD, HFINTOSC Idle Mode, FOSC = 16 MHz (PIC16LF18326/46 only) DS40001839F-page 446 PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 1,200 1,200 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C Max 1,000 1,000 Max 800 800 IDD (µA) IDD (µA) Typical 600 Typical 600 400 400 200 200 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.6 5.5 FIGURE 36-25: IDD, HFINTOSC Idle Mode, FOSC = 16 MHz (PIC16F18326/46 only) 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 36-26: IDD, HFINTOSC Doze Mode, FOSC = 16 MHz (PIC16LF18326/46 only) 36,000 1,200 Typical 25°C Max: 85°C + 3ı Typical: 25°C 35,000 Max +3 Sigma (-40°C to 125°C) 1,000 -3 Sigma (-40°C to 125°C) 34,000 33,000 Typical Frequency (Hz) IDD (µA) 800 600 400 32,000 31,000 30,000 29,000 200 28,000 1.7 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.3 2.6 FIGURE 36-27: IDD, HFINTOSC Doze Mode, FOSC = 16 MHz (PIC16F18326/46 only) 2.9 3.2 3.5 VDD (V) 5.5 FIGURE 36-28: LFINTOSC Frequency (PIC16LF18326/46 only) 36,000 3.0% Typical 25°C 35,000 +3 Sigma (-40°C to 125°C) 2.0% -3 Sigma (-40°C to 125°C) 34,000 1.0% 0.0% Error (%) Frequency (Hz) 33,000 32,000 31,000 -1.0% -2.0% 30,000 -3.0% 29,000 -4.0% 28,000 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 VDD (V) FIGURE 36-29: LFINTOSC Frequency (PIC16F18326/46 only) DS40001839F-page 447 Typical 25°C ı-40°C to +125°C) -ı-40°C to +125°C) -5.0% 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-30: HFINTOSC Typical Frequency Error (PIC16LF18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 1.5% 2.0% 1.5% 1.0% 1.0% +3 Sigma 0.0% Typical 25°C -0.5% ı-40°C to +125°C) -1.0% Error (%) Error (%) Typical 0.5% 0.5% -3 Sigma 0.0% -0.5% -ı-40°C to +125°C) -1.5% -1.0% -2.0% -1.5% -2.5% -3.0% 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 -2.0% -50 0 50 100 150 VDD (V) Temperature (°C) FIGURE 36-31: HFINTOSC Typical Frequency Error (PIC16F18326/46 only) FIGURE 36-32: HFINTOSC Frequency Error VDD = 3V (All devices) 300.0 180.0 Typical 25°C ı-40°C to +125°C) - ı-40°C to +125°C) Typical 25°C 160.0 Pull-Up Current (uA) Pull-Up Current (uA) 250.0 200.0 150.0 100.0 140.0 ı-40°C to +125°C) - ı-40°C to +125°C) 120.0 100.0 80.0 60.0 40.0 50.0 20.0 0.0 0.0 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 1.6 5.7 1.8 2.0 2.2 2.4 VDD (V) 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 36-33: Weak Pull-Up Current (PIC16F18326/46 only) FIGURE 36-34: Weak Pull-Up Current (PIC16LF18326/46 only) 6 3 Graph represents 3ı Limits Graph represents 3ı Limits 5 -40°C Typical 2 125°C VOL (V) VOH (V) 4 3 125°C 2 1 Typical 1 -40°C 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH (mA) FIGURE 36-35: VOH vs. IOH Overtemperature, VDD = 5.5V (PIC16LF18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries 0 0 10 20 30 IOL (mA) 40 50 60 FIGURE 36-36: VOL vs. IOL Overtemperature, VDD = 5.5V (PIC16F18326/46 only) DS40001839F-page 448 PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 3.5 3.0 Graph represents 3ı Limits 3.0 Graph represents 3ı Limits 2.5 2.5 Typical 2.0 Typical VOL (V) VOH (V) 2.0 -40°C 125°C 1.5 1.5 125°C 1.0 -40°C 1.0 0.5 0.5 0.0 0.0 -30 -25 -20 -15 -10 -5 0 0 5 10 15 20 25 IOH (mA) 30 35 40 45 50 55 60 IOL (mA) FIGURE 36-37: VOH vs. IOH Overtemperature, VDD = 3.0V (All devices) FIGURE 36-38: VOL vs. IOL Overtemperature, VDD = 3.0V (All devices) 2.0 1.8 Graph represents 3ı Limits 1.8 Graph represents 3ı Limits 1.6 1.6 1.4 1.4 1.2 125°C 1.2 Typical 125°C VOL (V) VOH (V) -40°C 1.0 Typical -40°C 1 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0 -8 -7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0 1 2 3 4 5 6 7 8 IOH (mA) 9 10 11 12 13 14 15 16 17 18 19 20 IOL (mA) FIGURE 36-39: VOH vs. IOH Overtemperature, VDD = 1.8V (PIC16LF18326/46 only) FIGURE 36-40: VOL vs. IOL Overtemperature, VDD = 1.8V (PIC16LF18326/46 only) 70.0 3.00 +3 Sigma -3 Sigma Typical 2.95 2.90 Typical +3 Sigma -3 Sigma 60.0 2.85 50.0 Voltage (mV) Voltage (V) 2.80 2.75 2.70 2.65 2.60 40.0 30.0 20.0 2.55 2.50 10.0 2.45 0.0 2.40 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 36-41: Brown-Out Reset Voltage, Trip Point (BORV = 0) (All devices) DS40001839F-page 449 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 36-42: Brown-Out Reset Hysteresis, Trip Point (BORV = 0) (All devices)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 40.0 2.00 Typical +3 Sigma -3 Sigma 35.0 1.95 30.0 Voltage (mV) Voltage (V) 25.0 1.90 1.85 20.0 15.0 10.0 +3 Sigma -3 Sigma Typical 5.0 1.80 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 FIGURE 36-43: Brown-Out Reset Voltage, Trip Point (BORV = 1) (PIC16LF18326/46 only) 40 60 80 100 120 140 100 120 140 100 120 140 FIGURE 36-44: Brown-Out Reset Hysteresis, Trip Point (BORV = 1) (PIC16LF18326/46 only) 2.70 50.0 +3 Sigma -3 Sigma Typical 2.65 2.60 Typical +3 Sigma -3 Sigma 45.0 40.0 2.55 2.50 35.0 Voltage (mV) Voltage (V) 20 Temperature (°C) Temperature (°C) 2.45 2.40 2.35 30.0 25.0 20.0 2.30 2.25 15.0 2.20 -60 -40 -20 0 20 40 60 80 100 120 140 10.0 -60 -40 -20 0 Temperature (°C) 20 40 60 80 Temperature (°C) FIGURE 36-45: Brown-Out Reset Voltage, Trip Point (BORV = 1) (PIC16F18326/46 only) FIGURE 36-46: Brown-Out Reset Hysteresis, Trip Point (BORV = 1) (PIC16F18326/46 only) 2.60 50 +3 Sigma Typical -3 Sigma 2.50 Typical +3 Sigma -3 Sigma 45 40 2.40 35 30 Voltage (mV) Voltage (V) 2.30 2.20 2.10 2.00 25 20 15 10 1.90 5 1.80 0 -60 1.70 -60 -40 -20 0 20 40 60 80 100 120 -40 -20 20 40 60 80 Temperature (°C) Temperature (°C) FIGURE 36-47: devices) 0 140 LPBOR Reset Voltage (All  2016-2022 Microchip Technology Inc. and its subsidiaries FIGURE 36-48: (All devices) LPBOR Reset Hysteresis DS40001839F-page 450 PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 7 5.0 Typical 25°C Typical 25°C 4.5 +3 Sigma 125°C +3 Sigma 125°C 6 4.0 5 3.0 Time (us) Time (us) 3.5 2.5 2.0 4 3 1.5 2 1.0 1 0.5 0.0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 0 3.7 2.6 VDD (V) 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 VDD (V) FIGURE 36-50: BOR Response Time (PIC16F18326/46 only) 1.0 1.0 0.5 0.5 DNL (LSb) DNL (LSb) FIGURE 36-49: BOR Response Time (PIC16LF18326/46 only) 0.0 0.0 -0.5 -0.5 -1.0 -1.0 0 128 256 384 512 640 768 896 0 1024 128 256 384 FIGURE 36-51: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 1 s, 25C (All devices) 640 768 896 1024 FIGURE 36-52: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 4 s, 25C (All devices) 1.0 1.0 0.5 0.5 INL (LSb) DNL (LSb) 512 Output Code Output Code 0.0 -0.5 0.0 -0.5 -1.0 -1.0 0 128 256 384 512 640 768 896 1024 Output Code FIGURE 36-53: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 8 s, 25C (All devices) DS40001839F-page 451 0 128 256 384 512 640 768 896 1024 Output Code FIGURE 36-54: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 1 s, 25C (All devices)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 2.0 1.0 2.0 1.0 1.5 1.5 1.0 1.0 0.5 0.5 0.5 0.5 INL (LSb) DNL (LSb) INL (LSb) DNL (LSb) Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 0.0 -0.5 0.0 -1.0 -1.5 -2.0 -0.5 0.0 -0.5 0.0 -1.0 -1.5 0 512 1024 1536 2048 2560 3072 3584 4096 -2.0 -0.5 0 512 1024 1536 2048 2560 3072 3584 4096 640 768 896 1024 Output Code Output Code -1.0 -1.0 0 128 256 384 512 640 768 896 0 1024 128 256 384 512 Output Code Output Code FIGURE 36-55: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 4 s, 25C (All devices) FIGURE 36-56: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 8 s, 25C (All devices) 0.5 0.5 INL (LSB) 1 DNL (LSB) 1 0 0 -0.5 -0.5 Max 25°C Min 25°C Max -40°C Min -40°C Max 85°C Min 85°C -1 0.5 0.8 1 2 4 Max 25°C Min 25°C Max -40°C Min -40°C Max 85°C Min 85°C -1 0.5 8 0.8 1 2 4 8 TADs TADs FIGURE 36-57: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V (All devices) FIGURE 36-58: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V (All devices) 2 1 1.5 1 0.5 INL(LSB) DNL(LSB) 0.5 0 0 -0.5 -1 -0.5 Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C -1 1.8 2.3 2.5 Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C -1.5 -2 3 VREF FIGURE 36-59: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 s (All devices)  2016-2022 Microchip Technology Inc. and its subsidiaries 1.8 2.3 2.5 3 VREF FIGURE 36-60: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 s (All devices) DS40001839F-page 452 PIC16(L)F18326/18346 6 3 5 2.5 4 2 3 1.5 2 1 1 0.5 (LSB) (LSB) Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 0 -1 0 -0.5 -2 -1 -3 -1.5 Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C -4 -5 -6 1.8 2.3 Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C -2 -2.5 -3 2.5 3 1.8 2.3 VREF 1 1 0.5 0.5 0 -0.5 -1 2.5 0 -0.5 Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C 2.3 3 FIGURE 36-62: ADC 10-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, TAD = 1 s (All devices) INL(LSB) DNL(LSB) FIGURE 36-61: ADC 10-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, TAD = 1 s (All devices) 1.8 2.5 VREF Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C -1 3 1.8 2.3 VREF 2.5 3 VREF FIGURE 36-63: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 4 s (All devices) FIGURE 36-64: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 4 s (All devices) 1 6 5 4 0.5 3 2 (LSB) (LSB) 1 0 0 -1 -2 -3 -0.5 Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C -4 -5 -6 1.8 2.3 2.5 -1 3 VREF FIGURE 36-65: ADC 10-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, TAD = 4 s (All devices) DS40001839F-page 453 Max 85°C Max 25°C Max -40°C Min 85°C Min 25°C Min -40°C 1.8 2.3 2.5 3 VREF FIGURE 36-66: ADC 10-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, TAD = 4 s (All devices)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 1.5 1.5 1 1 0.5 0.5 (LSB) 2 (LSB) 2 0 -0.5 0 -0.5 -1 -1 Max -1.5 Max -1.5 Typical Typical Min Min -2 -2 0.5 0.8 1 2 4 8 0.5 0.8 1 TADs 2 4 8 TADs FIGURE 36-67: ADC 10-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, VREF = 3.0V, -40°C to 85°C(All devices) FIGURE 36-68: ADC 10-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, VREF = 3.0V, -40°C to 85°C(All devices) 5.0 4.0 4.5 3.5 4.0 3.0 3.5 Time (us) Time (us) 2.5 3.0 2.5 2.0 2.0 1.5 1.5 1.0 1.0 Typical 25°C ı-40°C to +125°C) -ı-40°C to +125°C) 0.5 0.0 0.0 1.7 1.9 2.1 2.3 2.5 2.7 VDD (V) 2.9 3.1 3.3 3.5 2.2 3.7 0.00 0.015 -0.10 0.01 -0.15 -40°C 25°C INL (LSb) 0.02 -0.05 0 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 -0.20 5.2 5.4 5.6 -40°C 25°C -0.25 85°C 85°C 125°C -0.005 5 FIGURE 36-70: ADC RC Oscillator Period (PIC16F18326/46 only) 0.025 0.005 2.4 VDD (V) FIGURE 36-69: ADC RC Oscillator Period (PIC16LF18326/46 only) DNL (LSb) Typical 25°C ı-40°C to +125°C) -ı-40°C to +125°C) 0.5 125°C -0.30 -0.01 -0.35 -0.015 -0.40 -0.45 -0.02 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 36-71: Typical DAC DNL Error, VDD = 3.0V, VREF = External 3V (All devices)  2016-2022 Microchip Technology Inc. and its subsidiaries 0 14 28 42 56 70 84 98 112 126 140 154 168 182 196 210 224 238 252 Output Code FIGURE 36-72: Typical DAC INL Error, VDD = 3.0V, VREF = External 3V (All devices) DS40001839F-page 454 PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 0.020 0.00 -0.05 0.015 -0.10 0.010 INL (LSb) DNL (LSb) -0.15 0.005 -40°C 25°C 0.000 85°C 125°C -0.20 -40°C 25°C -0.25 85°C 125°C -0.30 -0.005 -0.35 -0.010 -0.40 -0.45 -0.015 0 14 28 42 56 70 84 98 112 126 140 154 168 182 196 210 224 238 252 Output Code 0 14 28 42 56 70 84 98 112126140154168182196210224238252 Output Code FIGURE 36-73: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V (PIC16F18326/46 only) FIGURE 36-74: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V (PIC16F18326/46 only) 0.45 0.4 24 Vref = Int. Vdd 0.4 22 AbsoluteAbsolute DNL (LSb) DNL (LSb) 20 DNL (LSb) Vref = Ext. 1.8V Vref = Ext. 2.0V 0.35 Max. 18 Typical 16 14 Min. 0.25 Vref = Int. Vdd Vref = Ext. 1.8V 0.2 Vref = Ext. 2.0V 0.15 0.2 Vref = Ext. 3.0V 0.1 0.05 0 0.1 -50 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 Vref = Ext. 3.0V 0.3 0.3 0 50 Temperature (°C) 100 150 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0.0 -60 -40 -20 0 Output Code FIGURE 36-75: DAC INL Error, VDD = 3.0V (PIC16LF18326/46 only) 0.90 -2.1 120 140 Vref = Int. Vdd Vref = Ext. 1.8V Vref = Ext. 2.0V Vref = Ext. 3.0V Vref = Ext. 5.0V 0.25 Vref = Ext. 2.0V Vref = Ext. 3.0V -40 -2.7 0.86 25 -2.9 85 0.84 -3.1 125 -3.3 0.82 -3.5 0.0 0.26 0.2 -40 0.15 0.22 25 85 0.1 125 0.05 0.18 0 1.0 2.0 3.0 Temperature (°C) 0.80 0.78 -60.0 100 0.30 0.3 Vref = Int. Vdd AbsoluteAbsolute DNL (LSb) DNL (LSb) AbsoluteAbsolute INL (LSb)INL (LSb) -2.5 80 FIGURE 36-76: Absolute Value of DAC DNL Error, VDD = 3.0V, VREF = VDD (All devices) Vref = Ext. 1.8V -2.3 0.88 20 40 60 Temperature (°C) -40.0 -20.0 0.0 20.0 40.0 60.0 Temperature (°C) 4.0 0.0 5.0 80.0 100.0 120.0 140.0 FIGURE 36-77: Absolute Value of DAC INL Error, VDD = 3.0V, VREF = VDD (All devices) DS40001839F-page 455 1.0 2.0 0.14 0.10 -60.0 -40.0 -20.0 0.0 3.0 4.0 Temperature (°C) 20.0 40.0 60.0 Temperature (°C) 5.0 80.0 6.0 100.0 120.0 140.0 FIGURE 36-78: Absolute Value of DAC DNL Error, VDD = 5.0V, VDD = 5.0V, VREF = VDD (PIC16F18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 0.9 -2.1 43 -40°C 41 -2.5 -40 -2.7 0.86 25 -2.9 85 0.84 -3.1 125 Hysteresis (mV) AbsoluteAbsolute INL (LSb)INL (LSb) -2.3 0.88 45 Vref = Int. Vdd Vref = Ext. 1.8V Vref = Ext. 2.0V Vref = Ext. 3.0V Vref = Ext. 5.0V 39 25°C 37 35 125° 33 85°C -3.3 0.82 -3.5 0.0 31 1.0 2.0 3.0 4.0 Temperature (°C) 0.8 5.0 6.0 29 27 25 0.78 -60.0 0.0 -40.0 -20.0 0.0 20.0 40.0 60.0 Temperature (°C) 80.0 100.0 120.0 1.5 2.0 2.5 3.0 3.5 FIGURE 36-80: Comparator Hysteresis, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values 30 30 25 25 20 20 15 15 Offset Voltage (mV) Offset Voltage (mV) 1.0 Common Mode Voltage (V) FIGURE 36-79: Absolute Value of DAC INL Error, VDD = 5.0V, VREF = VDD (PIC16F18326/46 only) 10 0.5 140.0 MAX 5 0 MAX 10 5 0 -5 -5 MIN MIN -10 -10 -15 -15 -20 -20 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 36-81: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25°C FIGURE 36-82: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values from -40°C to 125°C 30 50 25 20 40 25°C 125° 35 85° 30 Hysteresis (mV) Hysteresis (mV) 45 15 MAX 10 5 0 -5 -40°C -10 25 MIN -15 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Voltage (V) FIGURE 36-83: Comparator Hysteresis, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values  2016-2022 Microchip Technology Inc. and its subsidiaries 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Voltage (V) FIGURE 36-84: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values at 25°C DS40001839F-page 456 PIC16(L)F18326/18346 40 140 30 120 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 100 20 125°C Time (nS) Offset Voltage (mV) Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. MAX 10 80 25°C 60 0 40 -10 -40°C MIN 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1.7 2.0 2.3 2.6 2.9 3.2 3.5 Common Mode Voltage (V) VDD (V) FIGURE 36-85: Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values from -40°C to 125°C FIGURE 36-86: Comparator Response Time Overvoltage, Normal Power Mode (CxSP = 1), Typical Measured Values 0 90 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 80 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 0 70 Time (nS) Time (nS) 0 125°C 60 50 25°C 40 0 125°C 0 30 25°C 0 20 -40°C 0 10 -40°C 0 0 2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 1.8 2 2.2 2.4 2.6 VDD (V) 2.8 3 3.2 3.4 3.6 VDD (V) FIGURE 36-87: Comparator Response Time Overvoltage, Normal Power Mode (CxSP = 1), Typical Measured Values FIGURE 36-88: Comparator Output Filter Delay Time Overtemperature, Normal Power Mode (CxSP), Typical Measured Values 0 300 Typical 25°C +3 Sigma 125°C Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 0 250 200 0 Time (ns) Time (nS) 0 125°C 0 150 0 100 25°C 0 50 0 -40°C 0 0 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VDD (V) VDD (V) FIGURE 36-89: Comparator Output Filter Delay Time Overtemperature, Normal Power Mode (CxSP), Typical Measured Values DS40001839F-page 457 FIGURE 36-90: Comparator Response Time Falling Edge (PIC16LF18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 250 700 Typical 25°C Typical 25°C +3 Sigma 125°C +3 Sigma 125°C 600 200 150 Time (ns) Time (ns) 500 100 400 300 200 50 100 0 0 1.7 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VDD (V) VDD (V) FIGURE 36-91: Comparator Response Time Falling Edge (PIC16F18326/46 only) FIGURE 36-92: Comparator Response Time Rising Edge (PIC16LF18326/46 only) 70 900 Typical 25°C +3 Sigma 125°C 800 Typical 25°C ı-40°C to +125°C) 60 700 50 Time (us) Time (ns) 600 500 40 400 30 300 200 20 100 10 0 1.6 1.8 2 2.2 2.4 2.6 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 2.8 3 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 36-93: Comparator Response Time Rising Edge (PIC16F18326/46 only) FIGURE 36-94: Band Gap Ready Time (PIC16LF18326/46 only) 70 1.1% Typical -40°C Typical 25°C Typical 85°C Typical 125°C Typical 25°C 1.0% ı-40°C to +125°C) 60 0.9% 0.8% 50 Error (%) Time (us) 0.7% 40 30 0.6% 0.5% 0.4% 20 0.3% 0.2% 10 Note: The FVR Stabiliztion Period applies when coming out of RESET or exiting sleep mode. 0.1% 0.0% 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.4 2.5 2.6 2.7 FIGURE 36-95: FVR Stabilization Period  2016-2022 Microchip Technology Inc. and its subsidiaries 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 VDD (V) VDD (MV) FIGURE 36-96: Typical FVR Voltage 1x DS40001839F-page 458 PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 1.0% 1.2% Typical -40°C Typical 25°C Typical 85°C Typical 125°C 1.0% 0.8% 0.6% Error (%) Error (%) 0.8% 0.6% 0.4% 0.2% 0.4% 0.0% 0.2% Typical -40°C Typical 25°C Typical 85°C Typical 125°C -0.2% -0.4% 0.0% 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 2.4 5.6 2.5 2.6 2.7 2.8 2.9 FIGURE 36-97: FVR Voltage Error 1x FIGURE 36-98: 1.0% 1.0% 0.8% 0.8% 3.1 3.2 3.3 3.4 3.5 3.6 3.7 FVR Voltage Error 2x 0.6% Error (%) 0.6% Error (%) 3.0 VDD (V) VDD (V) 0.4% 0.4% 0.2% 0.2% 0.0% Typical -40°C Typical 25°C Typical 85°C Typical 125°C 0.0% Typical -40°C Typical 25°C Typical 85°C Typical 125°C -0.2% -0.2% 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 -0.4% 4.7 VDD (V) 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 VDD (V) FIGURE 36-99: FVR Voltage Error 2x FIGURE 36-100: FVR Voltage Error 4x (PIC16F18326/46 only) 4 2.5 Typical 25°C 3.5 ı-40°C to +125°C) -ı-40°C to +125°C) 3 2 2.5 Voltage (V) Voltage (V) Typical 25°C ı-40°C to +125°C) 2 1.5 1 -ı-40°C to +125°C) 1.5 1 0.5 0.5 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) VDD (V) FIGURE 36-101: DS40001839F-page 459 Schmitt Trigger High Values FIGURE 36-102: Schmitt Trigger Low Values  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 1.8 1.8 Typical 25°C 1.6 -ı-40°C to +125°C) 1.2 1 1 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 1.5 2.0 2.5 FIGURE 36-103: 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Input Level TTL 1.5 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Rise Time, Slew Rate 30 Typical 25°C 50 2.0 FIGURE 36-104: Control Enabled 60 Typical 25°C +3 Sigma (-40°C to 125°C) 25 40 +3 Sigma (-40°C to 125°C) 20 Time (ns) Time (ns) -ı-40°C to +125°C) 1.2 0.8 0 30 15 20 10 10 5 0 1.5 2.5 FIGURE 36-105: Enabled 3.5 VDD (V) 4.5 0 5.5 Fall Time, Slew Rate Control 1.5 2.5 3.5 VDD (V) FIGURE 36-106: Control Disabled 20 4.5 5.5 Rise Time, Slew Rate 4.00% Typical 25°C 18 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 3.00% +3 Sigma (-40°C to 125°C) 16 2.00% 14 12 1.00% Error (%) Time (ns) ı-40°C to +125°C) 1.4 Voltage (V) 1.4 Voltage (V) Typical 25°C 1.6 ı-40°C to +125°C) 10 8 Max 0.00% Min Average -1.00% 6 -2.00% 4 2 -3.00% 0 1.5 2.5 3.5 VDD (V) 4.5 5.5 -4.00% -32 Min -24 -16 -8 0 Center 8 16 24 32 Max OSCTUNE Setting FIGURE 36-107: Control Disabled Rise Time, Slew Rate  2016-2022 Microchip Technology Inc. and its subsidiaries FIGURE 36-108: Frequency OSCTUNE Center DS40001839F-page 460 PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 1.6 1.64 1.8 1.55 1.63 1.75 +3 Sigma 1.62 Voltage Voltage (V) (V) Voltage (V) 1.5 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.45 Typical 1.4 +3 Sigma 1.7 1.61 Typical 1.6 1.65 1.59 1.6 1.35 1.58 -3 Sigma 1.3 -40 -20 0 20 1.55 -3 Sigma 60 40 80 100 120 Temperature (°C) 1.25 1.5 1.2 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 20 FIGURE 36-109: 40 60 80 100 120 140 Temperature (°C) Temperature (°C) POR Release Voltage FIGURE 36-110: POR Rearm Voltage, Normal Power Mode 75.0 74.0 73.0 72.0 71.0 69.0 Time (ms) Time (ms) 70.0 68.0 66.0 67.0 65.0 63.0 64.0 61.0 Typical 25°C ı-40°C to +125°C) - ı-40°C to +125°C) 62.0 57.0 60.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Typical 25°C ı-40°C to +125°C) - ı-40°C to +125°C) 59.0 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 36-111: PWRT Period (PIC16F18326/46 only) FIGURE 36-112: PWRT Period (PIC16LF18326/46 only) 18 120 Typical 25°C Typical 25°C 110 ı-40°C to +125°C) ı-40°C to +125°C) 17 100 90 Time (us) Time (us) 16 15 14 80 70 60 50 40 13 30 20 12 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (V) FIGURE 36-113: Wake From Sleep, VREGPM = 0, HFINTOSC = 4 MHz (PIC16F18326/46 only) DS40001839F-page 461 5.5 6.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 36-114: Wake From Sleep, VREGPM = 1, HFINTOSC = 4 MHz (PIC16F18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries PIC16(L)F18326/18346 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 120 28 Typical 25°C 26 100 25 90 Time (us) Time (us) Typical 25°C 110 ı-40°C to +125°C) 27 24 ı-40°C to +125°C) 80 70 23 60 22 50 21 40 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 6.0 2.0 2.5 3.0 FIGURE 36-115: Wake From Sleep, VREGPM = 1, HFINTOSC = 16 MHz (PIC16F18326/46 only) 4.5 5.0 5.5 6.0 700 Typical 25°C Typical 25°C ı-40°C to +125°C) 650 ı-40°C to +125°C) 600 600 550 550 Time (us) Time (us) 4.0 FIGURE 36-116: Wake From Sleep, VREGPM = 1, HFINTOSC = 16 MHz (PIC16F18326/46 only) 700 650 3.5 VDD (V) VDD (V) 500 500 450 450 400 400 350 350 300 300 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) FIGURE 36-117: Wake From Sleep, VREGPM = 1 (PIC16F18326/46 only)  2016-2022 Microchip Technology Inc. and its subsidiaries 1.7 2.2 2.7 3.2 3.7 VDD (V) FIGURE 36-118: Wake From Sleep (PIC16LF18326/46 only) DS40001839F-page 462 PIC16(L)F18326/18346 37.0 DEVELOPMENT SUPPORT Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs) in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools. Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application, while our line of third party tools round out our comprehensive development tool solutions. Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which support multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows. Go to the following website for more information and details: https://www.microchip.com/development-tools/  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 463 PIC16(L)F18326/18346 38.0 PACKAGING INFORMATION 38.1 Marking Information 14-Lead PDIP (300 mil) Example PIC16LF18326 P e3 1519017 14-Lead SOIC (3.90 mm) Example PIC16F18326 SL e3 1519017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX YYWW NNN F18326ST 1519 017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this . ) e3 In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 464 PIC16(L)F18326/18346 Marking Information (Continued) Example 16-Lead UQFN (4x4x0.5mm) PIN 1 PIN 1 PIC16 F18326 JQ e3 519017 Example 16-Lead QFN (4x4x0.9mm)/VQFN (4x4x1mm) PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: PIC16 F18326 7N e3 519017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this . ) e3 In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 465 PIC16(L)F18326/18346 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC16LF18346 P e3 1519017 20-Lead SOIC (7.50 mm) Example PIC16LF18346 SO e3 1519017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this . ) e3 In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 466 PIC16(L)F18326/18346 Marking Information (Continued) 20-Lead SSOP (5.30 mm) Example 16F18346 SS e3 1405017 20-Lead UQFN (4x4x0.5 mm) PIN 1 Example PIN 1 PIC16 F18346 GZ e 519017 3 20-Lead QFN/VQFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F18346 ML e 519017 3 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this . ) e3 In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 467 PIC16(L)F18326/18346 38.2 Details The following sections give the technical details of the packages.                ! ] &' !&" &^# ?!*!!& ^%&  &#& &&\``???'  '`^ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB j&! '! |'&! q"';  %! qG{Q q q q} ~  &  & &      ##^ ^!!  Z J Z [!& &  Z    "# &  "# #& Q  J JZ  ##^#& Q  Z ‚ } |&  JZ Z Z & & | Z J Z |# ^!!  ‚  Z ; Z ƒ  ;  ‚  [   j |##& | ? |##& }  ?@ [G J  !  !"#$%&" ' *;"&'"!&; &#?&&&#   @%&G & !& J '! !#Q#  &"#' #%!  & "! ! #%!  & "! !! &$#X !#  '! #&   QYZ [G\[!'!   &$&"! ??& "&&  !       ? GZ[  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 468 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 469 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 470 PIC16(L)F18326/18346  ! ] &' !&" &^# ?!*!!& ^%&  &#& &&\``???'  '`^  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 471 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 472 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 473 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 474 PIC16(L)F18326/18346 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C SEATING PLANE A1 0.10 C C A 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N 16X b 0.10 L e C A B BOTTOM VIEW Microchip Technology Drawing C04-257A Sheet 1 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 475 PIC16(L)F18326/18346 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.50 2.50 0.25 0.30 0.20 MILLIMETERS NOM 16 0.65 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.60 4.00 BSC 2.60 0.30 0.40 - MAX 0.55 0.05 2.70 2.70 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-257A Sheet 2 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 476 PIC16(L)F18326/18346 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 16 1 2 C2 Y2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X16) X1 Contact Pad Length (X16) Y1 MIN MILLIMETERS NOM 0.65 BSC MAX 2.70 2.70 4.00 4.00 0.35 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2257A  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 477 PIC16(L)F18326/18346 16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.15 C 2X TOP VIEW 0.15 C 0.10 C C A1 A SEATING PLANE 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N 0.40 16X b 0.10 e C A B BOTTOM VIEW Microchip Technology Drawing C04-127D Sheet 1 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 478 PIC16(L)F18326/18346 16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Pins e Pitch A Overall Height Standoff A1 A3 Contact Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Contact Width Contact Length L Contact-to-Exposed Pad K MIN 0.80 0.00 2.50 2.50 0.25 0.30 0.20 MILLIMETERS NOM 16 0.65 BSC 0.90 0.02 0.20 REF 4.00 BSC 2.65 4.00 BSC 2.65 0.30 0.40 - MAX 1.00 0.05 2.80 2.80 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-127D Sheet 2 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 479 PIC16(L)F18326/18346 16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 480 PIC16(L)F18326/18346 16-Lead Plastic Quad Flat, No Lead Package (7N) - 4x4x1.0 mm Body [VQFN] Wettable Flanks (Stepped), 0.40 mm Terminal Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D NOTE 1 A B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C SEE DETAIL A C SEATING PLANE SIDE VIEW L 0.10 C A B D2 0.10 C A B E2 e 2 2 K 1 NOTE 1 N 16X b 0.10 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-403C Sheet 1 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 481 PIC16(L)F18326/18346 16-Lead Plastic Quad Flat, No Lead Package (7N) - 4x4x1.0 mm Body [VQFN] Wettable Flanks (Stepped), 0.40 mm Terminal Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.10 C C A4 A SEATING PLANE (A3) L1 A1 16X 0.08 C DETAIL A Units Dimension Limits N Number of Terminals e Pitch Overall Height A Standoff A1 A3 Terminal Thickness A4 Step Height Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 b Terminal Width Terminal Length L L1 Step Length Terminal-to-Exposed Pad K MILLIMETERS NOM MAX 16 0.65 BSC 0.80 0.90 1.00 0.02 0.05 0.00 0.20 REF 0.05 0.12 0.19 4.00 BSC 2.50 2.60 2.70 4.00 BSC 2.50 2.60 2.70 0.25 0.30 0.35 0.30 0.40 0.50 0.035 0.060 0.085 0.30 MIN Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-403C Sheet 2 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 482 PIC16(L)F18326/18346 16-Lead Plastic Quad Flat, No Lead Package (7N) - 4x4x1.0 mm Body [VQFN] Wettable Flanks (Stepped), 0.40 mm Terminal Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 16 ØV 1 G2 2 C2 Y2 EV G1 Y1 X1 SILK SCREEN E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X16) X1 Contact Pad Length (X16) Y1 Contact Pad to Center Pad (X16) G1 Contact Pad to Contact Pad (X12) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.65 BSC MAX 2.70 2.70 4.00 4.00 0.30 0.80 0.20 0.35 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2403B  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 483 PIC16(L)F18326/18346 "               ! ] &' !&" &^# ?!*!!& ^%&  &#& &&\``???'  '`^  N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 eB e b j&! '! |'&! q"';  %! qG{Q q q q} ~  &  & &      ##^ ^!!  Z J Z [!& &  Z    "# &  "# #& Q J J JZ  ##^#& Q  Z ‚ } |&  ‚ J ƒ & & | Z J Z |# ^!!  ‚  Z ; Z ƒ  ;  ‚  [   j |##& | ? |##& }  ?@ [G J  !  !"#$%&" ' *;"&'"!&; &#?&&&#   @%&G & !& J '! !#Q#  &"#' #%!  & "! ! #%!  & "! !! &$#X !#  '! #&   QYZ [G\ [!'!   &$&"! ??& "&&  !       ? G[  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 484 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 485 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 486 PIC16(L)F18326/18346 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 487 PIC16(L)F18326/18346 "   #$%& # '  ##  *+   ##'   ! ] &' !&" &^# ?!*!!& ^%&  &#& &&\``???'  '`^ D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 j&! '! |'&! q"';  %! L ||Q Q q q q} ~  &  } {&   ƒZ[G    ##^ ^!!  ƒZ Z ‚Z &# %%  Z   } #& Q  ‚ ‚  ##^#& Q Z ZJ Zƒ } |&  ƒ  Z ] &|& | ZZ Z Z ] & & | ZQ] |# ^!!    ] &  „ „ Z ‚„ |##& ;   J‚  !  !"#$%&" ' *;"&'"!&; &#?&&&#   '! !#Q#  &"#' #%!  & "! ! #%!  & "! !! &$#'' !# J '! #&   QYZ [G\ [!'!   &$&"! ??& "&&  ! Q]\ % '! *"!"?& "&&  *% % '& "  !!        ? G[  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 488 PIC16(L)F18326/18346 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.65 0.45 SILK SCREEN c Y1 G X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.65 BSC 7.20 MAX 0.45 1.75 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2072B  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 489 PIC16(L)F18326/18346 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C C SEATING PLANE A1 A 20X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 L 0.10 C A B E2 2 K 1 NOTE 1 N 20X b 0.10 e C A B BOTTOM VIEW Microchip Technology Drawing C04-255A Sheet 1 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 490 PIC16(L)F18326/18346 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Terminals e Pitch A Overall Height Standoff A1 A3 Terminal Thickness E Overall Width E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width L Terminal Length K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.60 2.60 0.20 0.30 0.20 MILLIMETERS NOM 20 0.50 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.70 4.00 BSC 2.70 0.25 0.40 - MAX 0.55 0.05 2.80 2.80 0.30 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-255A Sheet 2 of 2  2016-2022 Microchip Technology Inc. and its subsidiaries DS40001839F-page 491 PIC16(L)F18326/18346 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 20 1 2 C2 Y2 G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 MIN MILLIMETERS NOM 0.50 BSC MAX 2.80 2.80 4.00 4.00 0.30 0.80 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 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