PIC16F18446-I/SO

PIC16(L)F18426/46 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP Description PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general purpose and lowpower applications. Features such as a 12-bit Analog-to-Digital Converter with Computation (ADC2), Memory Access Partitioning (MAP), the Device Information Area (DIA), Power-Saving operating modes, and Peripheral Pin Select (PPS), offer flexible solutions for a wide variety of custom applications. Core Features • • • • • • • • • • • • C Compiler Optimized RISC Architecture Operating Speed: – DC – 32 MHz clock input – 125 ns minimum instruction cycle Interrupt Capability 16-Level Deep Hardware Stack Up to Four 8-Bit Timers Up to Four 16-Bit Timers Low-Current Power-on Reset (POR) Configurable Power-up Timer (PWRT) Brown-out Reset (BOR) Low-Power BOR (LPBOR) Option Windowed Watchdog Timer (WWDT): – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software Programmable Code Protection Memory • • • • • • • Up to 28 Kbytes Program Flash Memory Up to 2 KB Data SRAM Memory 256B Data EEPROM Direct, Indirect and Relative Addressing Modes Memory Access Partition (MAP): – Write-protect – Customizable partition Device Information Area (DIA) Device Characteristics Information (DCI) © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 1 PIC16(L)F18426/46 Operating Characteristics • • Operating Voltage Range: – 1.8V to 3.6V (PIC16LF184XX) – 2.3V to 5.5V (PIC16F184XX) Temperature Range: – Industrial: -40°C to 85°C – Extended: -40°C to 125°C eXtreme Low-Power (XLP) Features • • • • • Doze: CPU and Peripherals Running at Different Cycle Rates (Typically CPU is Lower) Idle: CPU Halted While Peripherals Operate Sleep: Lowest Power Consumption Peripheral Module Disable (PMD): – Ability to selectively disable hardware module to minimize active power consumption of unused peripherals Extreme Low-Power Mode (XLP) – Sleep: 500 nA typical @ 1.8V – Sleep and Watchdog Timer: 900 nA typical @ 1.8V Power-Saving Operation Modes • • • • Sleep Mode: 50 nA @ 1.8V, Typical Watchdog Timer: 500 nA @ 1.8V, Typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: – 8 uA @ 32 kHz, 1.8V, typical – 32 uA/MHz @ 1.8V, typical Digital Peripherals • • • • • Configurable Logic Cell (CLC): – Four CLCs – Integrated combinational and sequential logic Complementary Waveform Generator (CWG): – Two CWGs – Rising and falling edge dead-band control – Full-bridge, half-bridge, 1-channel drive – Multiple signal sources Capture/Compare/PWM (CCP) Modules: – Four CCPs – 16-bit resolution for Capture/Compare modes – 10-bit resolution for PWM mode Pulse-Width Modulators (PWM): – Two 10-bit PWMs Numerically Controlled Oscillator (NCO): – Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock – Input Clock: 0 Hz < fNCO < 32 MHz – Resolution: fNCO/220 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 2 PIC16(L)F18426/46 • • • • • Serial Communications: – EUSART • One EUSART(s) • RS-232, RS-485, LIN compatible • Auto-Baud Detect, Auto-wake-up on Start. – Master Synchronous Serial Port (MSSP) • Two MSSP(s) • SPI • I2C, SMBus and PMBus™ compatible Data Signal Modulator (DSM): – Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms Up to 18 I/O Pins: – Individually programmable pull-ups – Slew rate control – Interrupt-on-change with edge-select – Input level selection control (ST or TTL) – Digital open-drain enable Peripheral Pin Select (PPS): – I/O pin remapping of digital peripherals Timer Modules: – Timer0: • 8/16-bit timer/counter • Synchronous or asynchronous operation • Programmable prescaler/postscaler • Time base for capture/compare function – Timer1/3/5 with gate control: • 16-bit timer/counter • Programmable internal or external clock sources • Multiple gate sources • Multiple gate modes • Time base for capture/compare function – Timer2/4/6 with Hardware Limit Timer: • 8-bit timers • Programmable prescaler/postscaler • Time base for PWM function • Hardware Limit (HLT) and one-shot extensions • Selectable clock sources – Signal Measurement Timer (SMT): • One SMT(s) • 24-bit timer/counter with programmable prescaler Analog Peripherals • 12-bit Analog-to-Digital Converter with Computation (ADC2): – up to 140 ksps – up to 17 external channels – Conversion available during Sleep – Automated post-processing – Automated math functions on input signals: © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 3 PIC16(L)F18426/46 • • • • • • Averaging, filter calculations, oversampling and threshold comparison – Integrated charge pump for low-voltage operation – CVD support Zero-Cross Detect (ZCD): – AC high voltage zero-crossing detection – Synchronized switching control and timing Temperature Sensor Circuit Comparator: – Two Comparators – Fixed Voltage Reference at (non)inverting input(s) – Comparator outputs externally accessible Digital-to-Analog Converter (DAC): – 5-bit resolution, rail-to-rail – Positive Reference Selection – Unbuffered I/O pin output – Internal connections to ADC2 and comparators Fixed Voltage Reference with 1.024V, 2.048V and 4.096V Output Levels Flexible Oscillator Structure • • • • • • • • High-Precision Internal Oscillator: – Software-selectable frequency range up to 32 MHz – ±2% at calibration (nominal) 4x PLL for use with External Sources: – up to 32 MHz (4-8 MHz input) 2x PLL for use with the HFINTOSC: – up to 32 MHz Low-Power Internal 31 kHz Oscillator (LFINTOSC) External 32.768 kHz Crystal Oscillator (SOCS) External Oscillator Block with: – Three crystal/resonator modes up to 20 MHz – Three external clock modes up to 32 MHz Fail-Safe Clock Monitor: – Detects clock source failure Oscillator Start-up Timer (OST): – Ensures stability of crystal oscillator sources © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 4 PIC16(L)F18426/46 PIC16(L)F184XX Family Types NCO EUSART MSSP (I2C/SPI) CLC DSM PPS XLP PMD WWDT MAP DIA ICD(2) Clock Ref 4/4 4/4 PWM CWG 1 1 CCP Comparators 2 2 Timers (8/16-bit) 5-bit DAC 2 2 I/O’s(1) 1 1 RAM (B) 16 28 256 2048 12 11 16 28 256 2048 18 17 EEPROM (B) 12-bit ADC2 (ch) PIC16(L)F18426 PIC16(L)F18446 Program Flash Memory (Kbytes) Device Program Flash Memory (KW) Table 1. Devices Included In This Data Sheet 4 4 2 2 1 1 1 1 2 2 4 4 1 1 Y Y Y Y Y Y Y Y Y Y Y Y I I Note:  1. One pin is input-only. 2. Debugging Methods: (I) - Integrated on Chip; (E) - using Emulation Header. DSM PPS XLP PMD WWDT MAP DIA ICD(2) 4/4 4/4 4/4 4/4 4/4 4/4 CLC 1 1 1 1 1 1 MSSP (I2C/SPI) 2 2 2 2 3 3 EUSART 2 2 2 2 2 2 NCO 1 1 1 1 1 1 PWM Clock Ref 11 11 17 17 24 24 CCP CWG 12 12 18 18 26 26 Timers (8/16-bit) Comparators 512 1024 512 1024 1024 2048 5-bit DAC 256 256 256 256 256 256 12-bit ADC2 (ch) 7 14 7 14 14 28 I/O’s(1) EEPROM (B) 4 8 4 8 8 16 RAM (B) Program Flash Memory (Kbytes) PIC16(L)F18424 PIC16(L)F18425 PIC16(L)F18444 PIC16(L)F18445 PIC16(L)F18455 PIC16(L)F18456 Program Flash Memory (Words) Device Table 2. Devices Not Included In This Data Sheet 4 4 4 4 5 5 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 2 2 2 4 4 4 4 4 4 1 1 1 1 1 1 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y I I I I I I Data Sheet Index: 1. 2. 3. DS40002000A, PIC16(L)F18424/44 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP DS40002002A, PIC16(L)F18425/45 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP DS40002038B, PIC16(L)F18455/56 Data Sheet, 28-Pin Full-Featured, Low Pin Count Microcontrollers with XLP © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 5 PIC16(L)F18426/46 Packages Packages PDIP SOIC SSOP ● ● ● ● ● PIC16(L)F18426 PIC16(L)F18446 TSSOP ● UQFN (4x4) ● ● Note:  Pin details are subject to change. Important:  For other small form-factor package availability and marking information, visit www.microchip.com/ packaging or contact your local sales office. Pin Diagrams 14/16-Pin Diagrams Figure 1. 14-Pin PDIP, SOIC, TSSOP Rev. 00-000014A 6/21/2017 VDD 1 RA5 2 14 13 RA4 3 12 RA1/ICSPCLK VSS RA0/ICSPDAT MCLR/VPP/RA3 4 11 RA2 RC5 5 10 RC0 RC4 6 9 RC1 RC3 7 8 RC2 Figure 2. 16-Pin UQFN (4x4) VSS NC NC VDD Rev. 00-000016A 6/21/2017 16 15 14 13 RA5 1 12 RA0/ICSPDAT RA4 2 11 RA1/ICSPCLK 5 6 7 8 RC1 9 RC0 RC2 RC5 4 RC3 10 RA2 RC4 MCLR/VPP/RA3 3 Note:  It is recommended that the exposed bottom pad be connected to VSS. See Table 3 for more information. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 6 PIC16(L)F18426/46 20-Pin Diagrams Figure 3. 20-Pin PDIP, SOIC, SSOP Rev. 00-000020A 6/21/2017 VDD 1 RA5 2 20 VSS 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK MCLR/VPP/RA3 4 17 RA2 RC5 5 16 RC0 RC4 6 15 RC1 RC3 7 14 RC2 RC6 8 13 RB4 RC7 9 12 RB5 RB7 10 11 RB6 Figure 4. 20-Pin UQFN (4x4) RA0/ICSPDAT VSS VDD RA5 RA4 Rev. 00-000020B 6/21/2016 20 19 18 17 16 15 RA1/ICSPCLK MCLR/VPP/RA3 1 RC4 3 13 RC0 RC3 4 12 RC1 RC6 5 11 RC2 RB6 8 9 10 RB4 7 RB5 6 RB7 14 RA2 RC7 RC5 2 Note:  It is recommended that the exposed bottom pad be connected to VSS. See Table 4 for more information. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 7 PIC16(L)F18426/46 Pin Allocation Tables Interrupts Pull-up Basic — DAC1OUT1 MDSRC(1) — — — — SS2(1) — — — — IOCA0 Y ICDDAT ICSPDAT RA1 12 11 ANA1 ADCVREF+ C1IN0 C2IN0- — DAC1VREF+ — — — — — — — — — — IOCA1 Y ICDCLK ICSPCLK RA2 11 10 ANA2 ADCVREF- — — DAC1VREF- — T0CKI(1) CCP3IN(1) — CWG1IN(1) CWG2IN(1) — ZCD1 — — — IOCA2 Y INT(1) RA3 4 3 — — — — — — T6IN(1) — — — — — — — — IOCA3 Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) SMT1WIN(1) — — — — — — — — IOCA4 Y CLKOUT SOSCO OSC2 RA5 2 1 ANA5 — — — — — T1CKI(1) T2IN(1) SMT1SIG(1) — — — — — — CLCIN3(1) — IOCA5 Y CLKIN SOSCI OSC1 RC0 10 9 ANC0 — C2IN0+ — — — T5CKI(1) — — — SCK1(1) SCL1(1,3,4) — — — — IOCC0 Y — RC1 9 8 ANC1 — C1IN1C2IN1- — — — T4IN(1) CCP4IN(1) — — SDI1(1) SDA1(1,3,4) — — CLCIN2(1) — IOCC1 Y — RC2 8 7 ANC2 ADACT(1) — C1IN2C2IN2- — — MDCARL(1) — — — — — — — — — IOCC2 Y — RC3 7 6 ANC3 — C1IN3C2IN3- — — — T5G(1) CCP2IN(1) — — SS1(1) — — CLCIN0(1) — IOCC3 Y — RC4 6 5 ANC4 — — — — — T3G(1) — — — SCK2(1,5) SCL2(1,3,4,5) — CK1(1,3) CLCIN1(1) — IOCC4 Y — RC5 5 4 ANC5 — — — — MDCARH(1) T3CKI(1) CCP1IN(1) — — SDI2(1,5) SDA2(1,3,4,5) — RX1(1) DT1(1,3) — — IOCC5 Y — VDD 1 16 — — — — — — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — — — — — — VSS SDO1 SDO2 — DT1(3) CLC1OUT CLKR — — — CLC ZCD CWG CCP NCO Reference ADC CLKR C1IN0+ EUSART — MSSP ANA0 PWM DSM 12 Timers DAC 13 Comparator 16-pin UQFN RA0 I/O 14-pin PDIP/SOIC/TSSOP Table 3. 14/16-Pin Allocation Table — — ADCGRDA — C1OUT NCO1OUT — DSM1OUT TMR0OUT CCP1OUT PWM6OUT CWG1A CWG2A — — ADCGRDB — C2OUT — — — — CCP2OUT PWM7OUT CWG1B CWG2B SCK1 SCK2 — CK1(3) CLC2OUT — — — — — — — — — — — — — CCP3OUT — CWG1C CWG2C SCL1(3) SCL2(3) — TX1 CLC3OUT — — — — — — — — — — — — — CCP4OUT — CWG1D CWG2D SDA1(3) SDA2(3) — — CLC4OUT — — — — OUT(2) Interrupts Pull-up Basic — DAC1OUT1 — — — — — — — — — — IOCA0 Y ICDDAT/ ICSPDAT RA1 18 15 ANA1 ADCVREF+ C1IN0C2IN0- — DAC1VREF+ MDSRC(1) — — — — SS2(1) — — — — IOCA1 Y ICDCLK/ ICSPCLK RA2 17 14 ANA2 ADCVREF- — — DAC1VREF- — T0CKI(1) — — CWG1IN(1) CWG2IN(1) — ZCD1 — CLCIN0(1) — IOCA2 Y INT(1) RA3 4 1 — — — — — — — — — — — — — — — IOCA3 Y MCLR VPP Datasheet CLC ZCD CWG CCP DSM DAC NCO Reference ADC © 2019 Microchip Technology Inc. CLKR C1IN0+ EUSART — MSSP ANA0 PWM 16 Timers 19 Comparator 20-pin UQFN RA0 I/O 20-pin PDIP/SOIC/TSSOP Table 4. 20-Pin Allocation Table DS40001985B-page 8 PIC16(L)F18426/46 Interrupts Pull-up Basic — — — T1G(1) SMT1WIN(1) CCP4IN(1) — — — — — — — IOCA4 Y CLKOUT SOSCO OSC2 RA5 2 19 ANA5 — — — — — T1CKI(1) T2IN(1) SMT1SIG(1) — — — — — — — — IOCA5 Y CLKIN SOSCI OSC1 RB4 13 10 ANB4 — — — — — T5G(1) — — — SDI1(1) SDA1(1,3,4) — — CLCIN2(1) — IOCB4 Y — — RX1(1) DT1(1,3) CLCIN3(1) — IOCB5 Y — CLC ZCD CWG DAC NCO Reference ADC CLKR — EUSART — MSSP CCP ANA4 PWM Timers 20 DSM 3 Comparator 20-pin UQFN RA4 I/O 20-pin PDIP/SOIC/TSSOP ...........continued RB5 12 9 ANB5 — — — — — — CCP3IN(1) — — SDI2(1,5) SDA2(1,3,4,5) RB6 11 8 ANB6 — — — — — — — — — SCK1(1) SCL1(1,3,4) — — — — IOCB6 Y — RB7 10 7 ANB7 — — — — — T6IN(1) — — — SCK2(1,5) SCL2(1,3,4,5) — CK1(1,3) — — IOCB7 Y — RC0 16 13 ANC0 — C2IN0+ — — — T3CKI(1) T3G(1) — — — — — — — — IOCC0 Y — RC1 15 12 ANC1 — C1IN1C2IN1- — — — — — — — — — — — — IOCC1 Y — RC2 14 11 ANC2 ADACT(1) — C1IN2C2IN2- — — MDCARL(1) T5CKI(1) — — — — — — — — IOCC2 Y — RC3 7 4 ANC3 — C1IN3C2IN3- — — — — CCP2IN(1) — — — — — CLCIN1(1) — IOCC3 Y — RC4 6 3 ANC4 — — — — — — — — — — — — — — IOCC4 Y — RC5 5 2 ANC5 — — — — MDCARH(1) T4IN(1) CCP1IN(1) — — — — — — — IOCC5 Y — RC6 8 5 ANC6 — — — — — — — — — SS1(1) — — — — IOCC6 Y — RC7 9 6 ANC7 — — — — — — — — — — — — — — IOCC7 Y — VDD 1 18 — — — — — — — — — — — — — — — — — VDD VSS 20 17 — — — — — — — — — — — — — — — — — VSS SDO1 SDO2 — DT1(3) CLC1OUT CLKR — — — — — ADCGRDA — C1OUT NCO1OUT — DSM1OUT TMR0OUT CCP1OUT PWM6OUT CWG1A CWG2A — — ADCGRDB — C2OUT — — — — CCP2OUT PWM7OUT CWG1B CWG2B SCK1 SCK2 — CK1(3) CLC2OUT — — — — — — — — — — — — — CCP3OUT — CWG1C CWG2C SCL1(3) SCL2(3) — TX1 CLC3OUT — — — — CWG1D CWG2D SDA1(3) SDA2(3) — — CLC4OUT — — — — OUT(2) — — — — — — — — — CCP4OUT — Note:  1. Default peripheral input. Input can be moved to any other pin with the PPS input selections registers. 2. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripherals output with the PPS output selection registers. 3. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 4. These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected y the INLVL register. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 9 PIC16(L)F18426/46 Table of Contents Description..................................................................................................................................................... 1 Core Features................................................................................................................................................ 1 Memory.......................................................................................................................................................... 1 Operating Characteristics...............................................................................................................................2 eXtreme Low-Power (XLP) Features............................................................................................................. 2 Power-Saving Operation Modes.................................................................................................................... 2 Digital Peripherals.......................................................................................................................................... 2 Analog Peripherals......................................................................................................................................... 3 Flexible Oscillator Structure........................................................................................................................... 4 PIC16(L)F184XX Family Types......................................................................................................................5 Packages........................................................................................................................................................6 Pin Diagrams..................................................................................................................................................6 Pin Allocation Tables...................................................................................................................................... 8 1. Device Overview................................................................................................................................... 13 2. Guidelines for Getting Started with PIC16(L)F18426/46 Microcontrollers............................................ 19 3. Enhanced Mid-Range CPU...................................................................................................................24 4. Device Configuration.............................................................................................................................26 5. Memory Organization............................................................................................................................39 6. NVM - Nonvolatile Memory Control ......................................................................................................76 7. Interrupts............................................................................................................................................... 98 8. OSC - Oscillator Module..................................................................................................................... 122 9. REFCLK - Reference Clock Output Module........................................................................................143 10. Resets................................................................................................................................................. 148 11. WWDT - Windowed Watchdog Timer .................................................................................................161 12. Power-Saving Operation Modes......................................................................................................... 172 13. PMD - Peripheral Module Disable.......................................................................................................181 14. I/O Ports.............................................................................................................................................. 191 15. IOC - Interrupt-On-Change................................................................................................................. 221 16. PPS - Peripheral Pin Select Module .................................................................................................. 233 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 10 PIC16(L)F18426/46 17. CLC - Configurable Logic Cell.............................................................................................................244 18. TMR0 - Timer0 Module....................................................................................................................... 267 19. TMR1 - Timer1 Module with Gate Control...........................................................................................275 20. TMR2 - Timer2 Module....................................................................................................................... 293 21. SMT - Signal Measurement Timer...................................................................................................... 315 22. Capture/Compare/PWM Module......................................................................................................... 338 23. CCP/PWM Timer Resource Selection.................................................................................................351 24. PWM - Pulse-Width Modulation.......................................................................................................... 355 25. CWG - Complementary Waveform Generator.................................................................................... 363 26. NCO - Numerically Controlled Oscillator.............................................................................................390 27. DSM - Data Signal Modulator Module.................................................................................................400 28. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter...........................411 29. MSSP - Master Synchronous Serial Port Module............................................................................... 441 30. FVR - Fixed Voltage Reference.......................................................................................................... 500 31. Temperature Indicator Module............................................................................................................ 504 32. ADC2 - Analog-to-Digital Converter.....................................................................................................507 33. DAC - 5-Bit Digital-to-Analog Converter..............................................................................................552 34. CMP - Comparator Module................................................................................................................. 558 35. ZCD - Zero-Cross Detection Module...................................................................................................570 36. Register Summary.............................................................................................................................. 577 37. Instruction Set Summary.....................................................................................................................602 38. ICSP™ - In-Circuit Serial Programming™........................................................................................... 622 39. Development Support......................................................................................................................... 625 40. Electrical Specifications...................................................................................................................... 629 41. DC and AC Characteristics Graphs and Tables.................................................................................. 661 42. Packaging Information........................................................................................................................ 682 43. Revision History.................................................................................................................................. 704 The Microchip Website...............................................................................................................................705 Product Change Notification Service..........................................................................................................705 Customer Support...................................................................................................................................... 705 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 11 PIC16(L)F18426/46 Product Identification System.....................................................................................................................706 Microchip Devices Code Protection Feature.............................................................................................. 706 Legal Notice............................................................................................................................................... 707 Trademarks................................................................................................................................................ 707 Quality Management System..................................................................................................................... 707 Worldwide Sales and Service.....................................................................................................................708 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 12 PIC16(L)F18426/46 Device Overview 1. Device Overview This document contains device-specific information for the following devices: • PIC16F18426 • PIC16LF18426 • PIC16F18446 • PIC16LF18446 1.1 New Core Features 1.1.1 XLP Technology All of the devices in the PIC16(L)F184XX family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • • • • 1.1.2 Alternate Run Modes: By clocking the controller from the secondary oscillator or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. Peripheral Module Disable: Modules that are not being used in the code can be selectively disabled using the PMD module. This further reduces the power consumption. Multiple Oscillator Options and Features All of the devices in the PIC16(L)F184XX family offer several different oscillator options. The PIC16(L)F184XX family can be clocked from several different sources: • • • • • • 1.2 HFINTOSC – 1-32 MHz precision digitally controlled internal oscillator LFINTOSC – 31 kHz internal oscillator EXTOSC – External clock (EC) – Low-power oscillator (LP) – Medium-power oscillator (XT) – High-power oscillator (HS) SOSC – Secondary oscillator circuit optimized for 32 kHz clock crystals A Phase Lock Loop (PLL) frequency multiplier (2x/4x) is available to the External Oscillator modes enabling clock speeds of up to 32 MHz Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. Other Special Features • 12-bit A/D Converter with Computation: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. It has a new module called ADC2 with computation features, which provides a digital filter and threshold interrupt functions. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 13 PIC16(L)F18426/46 Device Overview • • • • 1.3 Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a boot loader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Windowed Watchdog Timer (WWDT): – Timer monitoring of overflow and underflow events – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software Details on Individual Family Members The devices of the PIC16(L)F184XX family described in the current datasheet are available in 14/20-pin packages. The block diagram for this device is shown in Figure 1-1. The devices have the following differences: 1. 2. 3. 4. 5. 6. 7. Program Flash Memory Data Memory SRAM Data Memory EEPROM A/D channels I/O ports Enhanced USART Input Voltage Range/Power Consumption All other features for devices in this family are identical. These are summarized in the following Device Features table. The pinouts for all devices are listed in the pin summary tables. Table 1-1. Device Features Features PIC16(L)F18426 PIC16(L)F18446 28 28 Program Memory (Instructions) 16384 16384 Data Memory (Bytes) 2048 2048 Data EEPROM Memory (Bytes) 256 256 14 - PDIP 20 - PDIP 14 - SOIC (3.9 mm) 20 - SOIC (7.5 mm) 14 - TSSOP 20 - SSOP 16 - uQFN (4x4) 20 - uQFN (4x4) A, C A, B, C Capture/Compare/PWM Modules (CCP) 4 4 Configurable Logic Cell (CLC) 4 4 10-Bit Pulse-Width Modulator (PWM) 2 2 Program Memory (KBytes) Packages I/O Ports © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 14 PIC16(L)F18426/46 Device Overview ...........continued Features PIC16(L)F18426 PIC16(L)F18446 11 channels 17 channels 5-Bit Digital-to-Analog Module (DAC) 1 1 Comparators 2 2 Numerical Contolled Oscillator (NCO) 1 1 Interrupt Sources 40 40 Timers (16-/8-bit) 4 4 2 MSSP 2 MSSP 1 EUSART 1 EUSART Complementary Waveform Generator (CWG) 2 2 Zero-Cross Detect (ZCD) 1 1 Data Signal Modulator (DSM) 1 1 Reference Clock Output Module 1 1 Peripheral Pin Select (PPS) YES YES Peripheral Module Disable (PMD) YES YES Programmable Brown-out Reset (BOR) YES YES POR, BOR, RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT POR, BOR, RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT 50 instructions 50 instructions 16-levels hardware stack 16-levels hardware stack DC – 32 MHz DC – 32 MHz 12-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator Serial Communications Resets (and Delays) Instruction Set Operating Frequency © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 15 Filename: 10-000039V.vsd Title: PIC16(L)F184xx Block Diagram Last Edit: 7/7/2017 First Used: PIC16(L)F184xx Notes: 1. See applicable chapters for more information on peripherals. 2. See Table 1-1 for peripherals available on specific devices. 3. See Figure 2-1 4. PORTB available on PIC16(L)F18444/5/6 PIC16(L)F18426/46 Device Overview Figure 1-1. PIC16(L)F18426/46 Device Block Diagram Program Flash Memory Rev. 10-000039V 7/7/2017 RAM PORTA Timing Generation CLKOUT/OSC2 PORTB(2) EXTOSC Oscillator CLKIN/OSC1 PORTC CPU Secondary Oscillator (SOSC) SOSCI SOSCO MCLR NCO1 CWG2 CWG1 PWM7 WDT PWM6 Timer6 Temp Indicator Timer5 EUSART1 MSSP2 Timer4 Timer3 MSSP1 CLC4 Timer2 CLC3 Timer1 CLC2 Timer0 CLC1 C2 ADC2 12-bit C1 SMU1 CCP4 CCP3 DAC1 CCP2 FVR CCP1 Note:  1. See applicable chapters for more information on peripherals. 2. PORTB available only on 20-pin or higher pin-count devices. 1.4 Register and Bit Naming Conventions 1.4.1 Register Names When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.4.2 Bit Names There are two variants for bit names: • • 1.4.2.1 Short name: Bit function abbreviation Long name: Peripheral abbreviation + short name Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the CM1CON0 register can be set in C programs with the instruction CM1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 16 PIC16(L)F18426/46 Device Overview 1.4.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Important:  The COG1 peripheral is used as an example. Not all devices have the COG peripheral. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction. 1.4.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the Mode Control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1UTH 101 Interrupt if ERR≤UTH 100 Interrupt if ERRUTH 011 Interrupt if ERR>LTH and ERR CxVN CxVP < CxVN CxVP < CxVN CxVP > CxVN Bit 4 – POL Comparator Output Polarity Select bit Value Description 1 Comparator output is inverted 0 Comparator output is not inverted Bit 1 – HYS Comparator Hysteresis Enable bit Value Description 1 Comparator hysteresis enabled 0 Comparator hysteresis disabled Bit 0 – SYNC Comparator Output Synchronous Mode bit Output updated on the falling edge of prescaled Timer1 clock. Value Description 1 Comparator output to Timer1 and I/O pin is synchronous to changes on the prescaled Timer1 clock. 0 Comparator output to Timer1 and I/O pin is asynchronous © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 566 PIC16(L)F18426/46 CMP - Comparator Module 34.15.3 CMxCON1 Name:  Address:  CMxCON1 0x991,0x995 Comparator x Control Register 1 Bit 7 6 5 4 3 2 Access Reset 1 INTP R/W 0 0 INTN R/W 0 Bit 1 – INTP Comparator Interrupt on Positive-Going Edge Enable bit Value Description 1 The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit 0 No interrupt flag will be set on a positive-going edge of the CxOUT bit Bit 0 – INTN Comparator Interrupt on Negative-Going Edge Enable bit Value Description 1 The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit 0 No interrupt flag will be set on a negative-going edge of the CxOUT bit © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 567 PIC16(L)F18426/46 CMP - Comparator Module 34.15.4 CMxNCH Name:  Address:  CMxNCH 0x992,0x996 Comparator x Inverting Channel Select Register Bit 7 6 5 4 3 Access Reset 2 R/W 0 1 NCH[2:0] R/W 0 0 R/W 0 Bits 2:0 – NCH[2:0] Comparator Inverting Input Channel Select bits NCH Negative Input Sources 111 CxVN connects to AVSS 110 CxVN connects to FVR Buffer 2 101 CxVN not connected 100 CxVN not connected 011 CxVN connects to CxIN3- pin 010 CxVN connects to CxIN2- pin 001 CxVN connects to CxIN1- pin 000 CxVN connects to CxIN0- pin © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 568 PIC16(L)F18426/46 CMP - Comparator Module 34.15.5 CMxPCH Name:  Address:  CMxPCH 0x993,0x997 Comparator x Non-Inverting Channel Select Register Bit 7 6 5 4 3 Access Reset 2 R/W 0 1 PCH[2:0] R/W 0 0 R/W 0 Bits 2:0 – PCH[2:0] Comparator Non-Inverting Input Channel Select bits PCH Positive Input Source 111 CxVP connects to VSS 110 CxVP connects to FVR Buffer 2 101 CxVP connects to DAC1 output 100 CxVP not connected 011 CxVP not connected 010 CxVP not connected 001 CxVP not connected 000 CxVP connects to CxIN0+ pin © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 569 PIC16(L)F18426/46 ZCD - Zero-Cross Detection Module 35. ZCD - Zero-Cross Detection Module The Zero-Cross Detection (ZCD) module detects when an A/C signal crosses through the ground potential. The actual zero crossing threshold is the zero crossing reference voltage, ZCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current-limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from Filename: 10-000194B.vsd forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the Title: ZERO CROSS DETECT BLOCK DIAGRAM module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The Last Edit: 5/14/2014 currentFirst source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD Used: PIC16(L)F1615 module is shown in the following simplified block diagram. Notes: Figure 35-1. Simplified ZCD Block Diagram VPULLUP Rev. 10-000194B 5/14/2014 optional VDD RPULLUP - Zcpinv ZCDxIN RSERIES RPULLDOWN + External voltage source optional ZCDx_output D ZCDxPOL Q ZCDxOUT bit Q1 Interrupt det ZCDxINTP ZCDxINTN Set ZCDIF flag Interrupt det The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: • • • • A/C period measurement Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 570 PIC16(L)F18426/46 ZCD - Zero-Cross Detection Module 35.1 External Resistor Selection The ZCD module requires a current-limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 μA. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. Equation 35-1. External Resistor ����� ������� = 3 × 10−4 Figure 35-2. External Voltage Source Rev. 30-000001A 7/18/2017 VMAXPEAK VMINPEAK VPEAK Z CPINV 35.2 ZCD Logic Output The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The OUT bit is set when the current sink is active, and cleared when the current source is active. The OUT bit is affected by the polarity bit. The OUT signal can also be used as input to other modules. This is controlled by the registers of the corresponding module. OUT can be used as follows: • • • 35.3 Gate source for TMR1/3/5 Clock source for TMR2/4/6 Reset source for TMR2/4/6 ZCD Logic Polarity The POL bit inverts the OUT bit relative to the current source and sink output. When the POL bit is set, a OUT high indicates that the current source is active, and a low output indicates that the current sink is active. The POL bit affects the ZCD interrupts. 35.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIR2 register will be set when either edge detector is triggered and its associated enable bit is set. The INTP bit in the ZCDxCON register enables rising edge interrupts and the INTN bit in the ZCDxCON register enables falling edge interrupts. To fully enable the interrupt, the following bits must be set: • • • ZCDIE bit of the PIE2 register INTP bit for rising edge detection INTN bit for falling edge detection © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 571 PIC16(L)F18426/46 ZCD - Zero-Cross Detection Module • PEIE and GIE bits of the INTCON register Changing the POL bit will cause an interrupt, regardless of the level of the SEN bit. The ZCDIF bit of the PIR2 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Related Links 5.8.10 INTCON 7.7.13 PIR2 35.5 Correction for ZCPINV Offset The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. 35.5.1 Correction by AC Coupling When the external voltage source is sinusoidal, the effects of the ZCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a capacitor, in addition to the voltage reducing resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual zero crossing event. The phase shift will be the same for both rising and falling zero crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift is negligible. To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to obtain a peak current of 300 μA. Next, arbitrarily select a suitably large non-polar capacitor and compute its reactance, XC, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage, and phase shift by the formulas shown below. When this technique is used and the input signal is not present, the ZCD will tend to oscillate. To avoid this oscillation, connect the ZCD pin to VDD or GND with a high-impedance resistor such as 200K. Equation 35-2. R-C Equations VPEAK = external voltage source peak voltage f = external voltage source frequency C = series capacitor R = series resistor VC = Peak capacitor voltage Φ = Capacitor induced zero crossing phase advance in radians TΦ = Time ZC event occurs before actual zero crossing �= ����� 3 × 10−4 �� = �= 1 2��� �2 − ��2 �� = �� 3 × 10−4 Φ = tan −1� �Φ = Φ 2�� �� � © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 572 PIC16(L)F18426/46 ZCD - Zero-Cross Detection Module Equation 35-3. R-C Calcuation Example ���� = 120 ����� = ���� × 2 = 169.7 � = 60 �� � = 0.1 �� �= ����� −4 3 × 10 �� = �= = 169.7 3 × 10−4 = 565.7 �Ω 1 1 = 26.53 �Ω = 2��� 2� × 60 × 10−7 �2 − ��2 = 565.1 �Ω �������� �� = 560 �Ω ���� �� = ��2 + ��2 = 560.6 �Ω ����� = ����� = 302.7 × 10−6� �� �� = �� × ����� = 8.0 � Φ = tan −1� �Φ = 35.5.2 �� = 0.047������� � Φ = 125.6�� 2�� Correction By Offset Current When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown below. Equation 35-4. ZCD Event Offset When External Voltage source is relative to VSS ������ sin−1 � ���� ������� = 2�� When External Voltage source is relative to VDD ������� = sin−1 ��� − ������ ����� 2�� This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the ZCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown below. Equation 35-5. ZCD Pull-up/Pull-down Resistor When External Voltage source is relative to VSS © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 573 PIC16(L)F18426/46 ZCD - Zero-Cross Detection Module ������� = ������� ������� − ������ ������ When External Voltage source is relative to VDD ��������� = 35.6 ������� ������ ��� − ������ Handling VPEAK Variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of ± 600 μA and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed ± 600 μA and the minimum is at least ± 100 μA, compute the series resistance as shown in Equation 35-6. The compensating pull-up for this series resistance can be determined with the equations shown in Equation 35-5 because the pull-up value is independent from the peak voltage. Equation 35-6. Series R for V range ����_���� + ����_���� ������� = 7 × 10−4 35.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 35.8 Effects of a Reset The ZCD circuit can be configured to default to the Active or Inactive state on Power-on Reset (POR). When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the SEN bit must be set to enable the ZCD module. 35.9 Disabling the ZCD Module The ZCD module can be disabled in two ways: 1. 2. The ZCD Configuration bit disables the ZCD module when set. When this is the case then the ZCD module will be enabled by setting the SEN bit. When the ZCD bit is cleared, the ZCD is always enabled and the SEN bit has no effect. The ZCD can also be disabled using the ZCDMD bit of the PMD3 register. This is subject to the status of the ZCD bit. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 574 PIC16(L)F18426/46 ZCD - Zero-Cross Detection Module 35.10 Address 0x00 ... 0x091E 0x091F 35.11 Register Summary: ZCD Control Name Bit Pos. Reserved ZCDCON 7:0 SEN OUT POL INTP INTN Register Definitions: ZCD Control © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 575 PIC16(L)F18426/46 ZCD - Zero-Cross Detection Module 35.11.1 ZCDCON Name:  Address:  ZCDCON 0x91F Zero-Cross Detect Control Register Bit Access Reset 7 SEN R/W 0 6 5 OUT RO x 4 POL R/W 0 3 2 1 INTP R/W 0 0 INTN R/W 0 Bit 7 – SEN Zero-Cross Detect Software Enable bit This bit is ignored when ZCD fuse is cleared. Value Condition Description X ZCD Config fuse = 0 Zero-cross detect is always enabled. This bit is ignored. 1 ZCD Config fuse = 1 Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 ZCD Config fuse = 1 Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. Bit 5 – OUT Zero-Cross Detect Data Output bit Value Condition Description 1 POL = 0 ZCD pin is sinking current 0 POL = 0 ZCD pin is sourcing current 1 POL = 1 ZCD pin is sourcing current 0 POL = 1 ZCD pin is sinking current Bit 4 – POL Zero-Cross Detect Polarity bit Value Description 1 ZCD logic output is inverted 0 ZCD logic output is not inverted Bit 1 – INTP Zero-Cross Detect Positive-Going Edge Interrupt Enable bit Value Description 1 ZCDIF bit is set on low-to-high ZCD_output transition 0 ZCDIF bit is unaffected by low-to-high ZCD_output transition Bit 0 – INTN Zero-Cross Detect Negative-Going Edge Interrupt Enable bit Value Description 1 ZCDIF bit is set on high-to-low ZCD_output transition 0 ZCDIF bit is unaffected by high-to-low ZCD_output transition © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 576 PIC16(L)F18426/46 Register Summary 36. Register Summary Address Name Bit Pos. 0x00 0x01 0x02 0x03 INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 RB7 RC7 7:0 7:0 7:0 7:0 7:0 7:0 0x04 FSR0 0x06 FSR1 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F ... 0x11 0x12 0x13 0x14 0x15 ... 0x17 0x18 0x19 0x1A 0x1B ... 0x7F 0x80 0x81 0x82 0x83 BSR WREG PCLATH INTCON PORTA PORTB PORTC INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C RA3 RA2 RA1 INTEDG RA0 RC3 RC2 RC1 RC0 TRISA2 TRISA1 TRISA0 TRISC2 TRISC1 TRISC0 LATA2 LATA1 LATA0 LATC2 LATC1 LATC0 Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE RB6 RC6 RA5 RB5 RC5 RA4 RB4 RC4 TRISB7 TRISC7 TRISB6 TRISC6 TRISA5 TRISB5 TRISC5 TRISA4 TRISB4 TRISC4 LATB7 LATC7 LATB6 LATC6 LATA5 LATB5 LATC5 LATA4 LATB4 LATC4 Reserved TRISA TRISB TRISC TRISC3 Reserved LATA LATB LATC LATC3 Reserved INDF0 INDF1 PCL STATUS 0x84 FSR0 0x86 FSR1 0x88 0x89 0x8A 0x8B BSR WREG PCLATH INTCON 0x8C ADLTH 0x8E ADUTH 0x90 ADERR 0x92 ADSTPT 0x94 ADFLTR 0x96 ADACC 0x99 ADCNT 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 7:0 15:8 23:16 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE © 2019 Microchip Technology Inc. PEIE INTEDG LTH[7:0] LTH[15:8] UTH[7:0] UTH[15:8] ERR[7:0] ERR[15:8] STPT[7:0] STPT[15:8] FLTR[7:0] FLTR[15:8] ACC[7:0] ACC[15:8] ACC[17:16] CNT[7:0] Datasheet DS40001985B-page 577 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 7:0 7:0 RPT[7:0] PREV[7:0] 15:8 7:0 15:8 7:0 PREV[15:8] RES[7:0] RES[15:8] 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] 0x9A ADRPT 0x9B ADPREV 0x9D ADRES 0x9F 0xA0 ... 0xFF 0x0100 0x0101 0x0102 0x0103 ADPCH PCH[5:0] Reserved INDF0 INDF1 PCL STATUS 0x0104 FSR0 0x0106 FSR1 0x0108 0x0109 0x010A 0x010B BSR WREG PCLATH INTCON 0x010C ADACQ 0x010E ADCAP 0x010F ADPRE 0x0111 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118 0x0119 0x011A ADCON0 ADCON1 ADCON2 ADCON3 ADSTAT ADREF ADACT ADCLK RC1REG TX1REG 0x011B SP1BRG 0x011D 0x011E 0x011F 0x0120 ... 0x017F 0x0180 0x0181 0x0182 0x0183 RC1STA TX1STA BAUD1CON TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG ACQ[7:0] ACQ[12:8] CAP[4:0] PRE[7:0] ON PPOL PSIS CONT IPEN OV UTHR PRE[12:8] FRM CS GPOL CRS[2:0] CALC[2:0] LTHR ACLR SOI GO DSEN MD[2:0] TMD[2:0] STAT[2:0] PREF[1:0] MATH NREF ACT[4:0] CS[5:0] SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN RCREG[7:0] TXREG[7:0] SPBRG[7:0] SPBRG[15:8] CREN ADDEN SYNC SENDB SCKP BRG16 BRGH FERR OERR TRMT WUE RX9D TX9D ABDEN Z DC C Reserved INDF0 INDF1 PCL STATUS 0x0184 FSR0 0x0186 FSR1 0x0188 0x0189 0x018A 0x018B 0x018C 0x018D 0x018E BSR WREG PCLATH INTCON SSP1BUF SSP1ADD SSP1MSK 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE © 2019 Microchip Technology Inc. PEIE INTEDG BUF[7:0] ADD[7:0] MSK[6:0] Datasheet MSK0 DS40001985B-page 578 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x018F 0x0190 SSP1STAT SSP1CON1 7:0 7:0 SMP WCOL CKE SSPOV D/A SSPEN P CKP S 0x0191 0x0192 0x0193 ... 0x0195 0x0196 0x0197 0x0198 0x0199 0x019A 0x019B 0x019C 0x019D ... 0x01FF 0x0200 0x0201 0x0202 0x0203 SSP1CON2 SSP1CON3 7:0 7:0 GCEN ACKTIM ACKSTAT PCIE ACKDT SCIE ACKEN BOEN RCEN SDAHT 0x0204 FSR0 0x0206 FSR1 0x0208 0x0209 0x020A 0x020B BSR WREG PCLATH INTCON 0x020C TMR1 0x020E 0x020F 0x0210 0x0211 T1CON T1GCON TMR1GATE TMR1CLK 0x0212 TMR3 0x0214 0x0215 0x0216 0x0217 T3CON T3GCON TMR3GATE TMR3CLK 0x0218 TMR5 0x021A 0x021B 0x021C 0x021D 0x021E 0x021F 0x0220 ... 0x027F 0x0280 0x0281 0x0282 0x0283 T5CON T5GCON TMR5GATE TMR5CLK CCPTMRS0 CCPTMRS1 0x0284 R/W UA SSPM[3:0] PEN SBCDE RSEN AHEN BF SEN DHEN Reserved SSP2BUF SSP2ADD SSP2MSK SSP2STAT SSP2CON1 SSP2CON2 SSP2CON3 7:0 7:0 7:0 7:0 7:0 7:0 7:0 SMP WCOL GCEN ACKTIM CKE SSPOV ACKSTAT PCIE D/A SSPEN ACKDT SCIE BUF[7:0] ADD[7:0] MSK[6:0] P S CKP ACKEN RCEN BOEN SDAHT R/W UA SSPM[3:0] PEN RSEN SBCDE AHEN MSK0 BF SEN DHEN Reserved INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG TMRx[7:0] TMRx[15:8] GE GPOL CKPS[1:0] GTM GSPM SYNC GVAL GSS[4:0] CS[4:0] RD16 ON SYNC GVAL GSS[4:0] CS[4:0] RD16 ON SYNC GVAL GSS[4:0] CS[4:0] C2TSEL[1:0] P6TSEL[1:0] RD16 ON GGO/DONE TMRx[7:0] TMRx[15:8] GE GPOL CKPS[1:0] GTM GSPM GGO/DONE TMRx[7:0] TMRx[15:8] GE GPOL C4TSEL[1:0] CKPS[1:0] GTM GSPM GGO/DONE C3TSEL[1:0] P7TSEL[1:0] C1TSEL[1:0] Reserved INDF0 INDF1 PCL STATUS FSR0 7:0 7:0 7:0 7:0 7:0 15:8 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] Datasheet DS40001985B-page 579 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0286 FSR1 7:0 15:8 FSR1[7:0] FSR1[15:8] 0x0288 0x0289 0x028A 0x028B 0x028C 0x028D 0x028E 0x028F 0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297 0x0298 0x0299 0x029A 0x029B 0x029C 0x029D 0x029E 0x029F 0x02A0 ... 0x02FF 0x0300 0x0301 0x0302 0x0303 BSR WREG PCLATH INTCON T2TMR T2PR T2CON T2HLT T2CLKCON T2RST T4TMR T4PR T4CON T4HLT T4CLKCON T4RST T6TMR T6PR T6CON T6HLT T6CLKCON T6RST Reserved ADCPCON0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] 7:0 GIE PEIE INTEDG TxTMR[7:0] TxPR[7:0] ON PSYNC CPOL CKPS[2:0] CSYNC OUTPS[3:0] MODE[4:0] CS[3:0] RSEL[3:0] TxTMR[7:0] TxPR[7:0] ON PSYNC CPOL CKPS[2:0] CSYNC OUTPS[3:0] MODE[4:0] CS[3:0] RSEL[3:0] TxTMR[7:0] TxPR[7:0] ON PSYNC CPOL CKPS[2:0] CSYNC OUTPS[3:0] MODE[4:0] CS[3:0] RSEL[3:0] CPON CPRDY Reserved INDF0 INDF1 PCL STATUS 0x0304 FSR0 0x0306 FSR1 0x0308 0x0309 0x030A 0x030B BSR WREG PCLATH INTCON 0x030C CCPR1 0x030E 0x030F CCP1CON CCP1CAP 0x0310 CCPR2 0x0312 0x0313 CCP2CON CCP2CAP 0x0314 CCPR3 0x0316 0x0317 CCP3CON CCP3CAP 0x0318 CCPR4 0x031A 0x031B CCP4CON CCP4CAP 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 7:0 15:8 7:0 7:0 7:0 15:8 7:0 7:0 7:0 15:8 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE EN EN EN EN © 2019 Microchip Technology Inc. PEIE INTEDG OUT CCPR[7:0] CCPR[15:8] FMT OUT CCPR[7:0] CCPR[15:8] FMT OUT CCPR[7:0] CCPR[15:8] FMT OUT CCPR[7:0] CCPR[15:8] FMT Datasheet MODE[3:0] CTS[2:0] MODE[3:0] CTS[2:0] MODE[3:0] CTS[2:0] MODE[3:0] CTS[2:0] DS40001985B-page 580 PIC16(L)F18426/46 Register Summary ...........continued Address 0x031C ... 0x037F 0x0380 0x0381 0x0382 0x0383 Name Bit Pos. Reserved INDF0 INDF1 PCL STATUS 0x0384 FSR0 0x0386 FSR1 0x0388 0x0389 0x038A 0x038B BSR WREG PCLATH INTCON 0x038C PWM6DC 0x038E 0x038F PWM6CON Reserved 0x0390 PWM7DC 0x0392 0x0393 ... 0x03FF 0x0400 0x0401 0x0402 0x0403 PWM7CON 0x0404 FSR0 0x0406 FSR1 0x0408 0x0409 0x040A 0x040B 0x040C ... 0x047F 0x0480 0x0481 0x0482 0x0483 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 7:0 7:0 15:8 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG DCL[1:0] DCH[7:0] EN OUT POL OUT POL DCL[1:0] DCH[7:0] EN Reserved INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0484 FSR0 0x0486 FSR1 0x0488 0x0489 0x048A 0x048B BSR WREG PCLATH INTCON 0x048C SMT1TMR 0x048F SMT1CPR 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 23:16 7:0 15:8 23:16 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE © 2019 Microchip Technology Inc. PEIE INTEDG TMR[7:0] TMR[15:8] TMR[23:16] CPR[7:0] CPR[15:8] CPR[23:16] Datasheet DS40001985B-page 581 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0492 SMT1CPW 7:0 15:8 CPW[7:0] CPW[15:8] 23:16 7:0 15:8 23:16 7:0 7:0 7:0 7:0 7:0 7:0 CPW[23:16] PR[7:0] PR[15:8] PR[23:16] WPOL SPOL 0x0495 SMT1PR 0x0498 0x0499 0x049A 0x049B 0x049C 0x049D 0x049E ... 0x04FF 0x0500 0x0501 0x0502 0x0503 SMT1CON0 SMT1CON1 SMT1STAT SMT1CLK SMT1SIG SMT1WIN 0x0504 FSR0 0x0506 FSR1 0x0508 0x0509 0x050A 0x050B 0x050C ... 0x057F 0x0580 0x0581 0x0582 0x0583 BSR WREG PCLATH INTCON EN GO CPRUP STP REPEAT CPWUP RST CPOL PS[1:0] MODE[3:0] TS WS AS CSEL[2:0] SSEL[4:0] WSEL[4:0] Reserved INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0584 FSR0 0x0586 FSR1 0x0588 0x0589 0x058A 0x058B WREG PCLATH INTCON BSR 0x058C NCO1ACC 0x058F NCO1INC 0x0592 0x0593 0x0594 ... 0x059B 0x059C 0x059D 0x059E 0x059F NCO1CON NCO1CLK 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 15:8 23:16 7:0 15:8 23:16 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG ACC[7:0] ACC[15:8] ACC[23:16] INC[7:0] INC[15:8] INC[19:16] EN OUT POL PWS[2:0] PFM CKS[3:0] Reserved TMR0L TMR0H T0CON0 T0CON1 7:0 7:0 7:0 7:0 T0EN © 2019 Microchip Technology Inc. T0OUT T0CS[2:0] TMR0L[7:0] TMR0H[7:0] T016BIT T0ASYNC Datasheet T0OUTPS[3:0] T0CKPS[3:0] DS40001985B-page 582 PIC16(L)F18426/46 Register Summary ...........continued Address 0x05A0 ... 0x05FF 0x0600 0x0601 0x0602 0x0603 Name Reserved INDF0 INDF1 PCL STATUS 0x0604 FSR0 0x0606 FSR1 0x0608 0x0609 0x060A 0x060B 0x060C 0x060D 0x060E 0x060F 0x0610 0x0611 0x0612 0x0613 0x0614 0x0615 0x0616 0x0617 0x0618 0x0619 0x061A 0x061B 0x061C 0x061D 0x061E 0x061F ... 0x067F 0x0680 0x0681 0x0682 0x0683 BSR WREG PCLATH INTCON CWG1CLK CWG1ISM CWG1DBR CWG1DBF CWG1CON0 CWG1CON1 CWG1AS0 CWG1AS1 CWG1STR Reserved CWG2CLK CWG2ISM CWG2DBR CWG2DBF CWG2CON0 CWG2CON1 CWG2AS0 CWG2AS1 CWG2STR 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD IN SHUTDOWN REN OVRD OVRC LSBD[1:0] AS5E AS4E OVRB OVRA POLD POLC LSAC[1:0] AS3E AS2E STRD STRC MODE[2:0] POLB POLA AS1E STRB AS0E STRA CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD IN SHUTDOWN REN OVRD OVRC LSBD[1:0] AS5E AS4E OVRB OVRA POLD POLC LSAC[1:0] AS3E AS2E STRD STRC MODE[2:0] POLB POLA AS1E STRB AS0E STRA DC C Reserved INDF0 INDF1 PCL STATUS 0x0684 FSR0 0x0686 FSR1 0x0688 0x0689 0x068A 0x068B 0x068C ... 0x06FF 0x0700 0x0701 0x0702 0x0703 BSR WREG PCLATH INTCON 0x0704 Bit Pos. 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS FSR0 7:0 7:0 7:0 7:0 7:0 15:8 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] Datasheet DS40001985B-page 583 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0706 FSR1 7:0 15:8 FSR1[7:0] FSR1[15:8] 0x0708 0x0709 0x070A 0x070B 0x070C 0x070D 0x070E 0x070F 0x0710 0x0711 0x0712 0x0713 0x0714 0x0715 0x0716 0x0717 0x0718 0x0719 0x071A 0x071B 0x071C 0x071D 0x071E 0x071F ... 0x077F 0x0780 0x0781 0x0782 0x0783 BSR WREG PCLATH INTCON PIR0 PIR1 PIR2 PIR3 PIR4 PIR5 PIR6 PIR7 PIR8 Reserved PIE0 PIE1 PIE2 PIE3 PIE4 PIE5 PIE6 PIE7 PIE8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 GIE PEIE TMR0IF OSFIF CLC4IF CSWIF ZCDIF CLC3IF RC1IF TMR6IF CL24IF TX1IF TMR5IF CLC1IF NVMIF NCO1IF TMR0IE IOCIE BCL2IF TMR4IF CCP4IF OSFIE CLC4IE CSWIE ZCDIE CLC3IE ADTIF C2IF SSP2IF BCL1IF TMR3IF TMR2IF TMR5GIF TMR3GIF CCP3IF CCP2IF CWG2IF SMT1PWAIF SMT1PRAIF INTEDG INTF ADIF C1IF SSP1IF TMR1IF TMR1GIF CCP1IF CWG1IF SMT1IF ADTIE C2IE SSP2IE BCL1IE TMR3IE TMR2IE TMR5GIE TMR3GIE CCP3IE CCP2IE CWG2IE SMT1PWAIE SMT1PRAIE INTE ADIE C1IE SSP1IE TMR1IE TMR1GIE CCP1IE CWG1IE SMT1IE IOCIF RC1IE TMR6IE CLC2IE TX1IE TMR5IE CLC1IE NVMIE NCO1IE BCL2IE TMR4IE CCP4IE Reserved INDF0 INDF1 PCL STATUS 0x0784 FSR0 0x0786 FSR1 0x0788 0x0789 0x078A 0x078B 0x078C ... 0x0795 0x0796 0x0797 0x0798 0x0799 0x079A 0x079B 0x079C 0x079D 0x079E ... 0x07FF 0x0800 0x0801 0x0802 0x0803 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG SYSCMD FVRMD TMR6MD TMR5MD DAC1MD PWM7MD CWG2MD ADCMD PWM6MD CWG1MD Reserved PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 TMR4MD TMR3MD NVMMD TMR2MD CLKRMD TMR1MD IOCMD TMR0MD CCP4MD C2MD CCP3MD C1MD CCP2MD ZCDMD CCP1MD CLC3MD CLC2MD MSSP2MD CLC1MD MSSP1MD DSM1MD Z DC C NCO1MD SMT1MD UART1MD CLC4MD Reserved INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO Datasheet PD DS40001985B-page 584 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0804 FSR0 7:0 15:8 FSR0[7:0] FSR0[15:8] 0x0806 FSR1 FSR1[7:0] FSR1[15:8] 0x0808 0x0809 0x080A 0x080B 0x080C 0x080D 0x080E 0x080F 0x0810 0x0811 0x0812 0x0813 0x0814 0x0815 ... 0x0819 BSR WREG PCLATH INTCON WDTCON0 WDTCON1 WDTPSL WDTPSH WDTTMR BORCON VREGCON PCON0 PCON1 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 0x081A NVMADR 0x081C NVMDAT 0x081E 0x081F 0x0820 ... 0x087F 0x0880 0x0881 0x0882 0x0883 NVMCON1 NVMCON2 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG SEN WDTPS[4:0] WDTCS[2:0] WINDOW[2:0] PSCNTL[7:0] PSCNTH[7:0] WDTTMR[4:0] STATE SBOREN STKOVF STKUNF WDTWV RWDT RMCLR RI PSCNT[1:0] BORRDY VREGPM POR BOR MEMV Reserved 7:0 15:8 7:0 15:8 7:0 7:0 NVMREGS NVMADR[7:0] NVMADR[14:8] NVMDAT[7:0] NVMDAT[13:8] FREE WRERR WREN NVMCON2[7:0] LWLO WR RD DC C Reserved INDF0 INDF1 PCL STATUS 0x0884 FSR0 0x0886 FSR1 0x0888 0x0889 0x088A 0x088B 0x088C 0x088D 0x088E 0x088F 0x0890 0x0891 0x0892 0x0893 0x0894 0x0895 0x0896 0x0897 0x0898 0x0899 0x089A 0x089B BSR WREG PCLATH INTCON CPUDOZE OSCCON1 OSCCON2 OSCCON3 OSCSTAT OSCEN OSCTUNE OSCFRQ Reserved CLKRCON CLKRCLK MD1CON0 MD1CON1 MD1SRC MD1CARL MD1CARH 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE IDLEN PEIE DOZEN CSWHOLD EXTOR EXTOEN SOSCPWR HFOR HFOEN INTEDG ROI NOSC[2:0] COSC[2:0] MFOR MFOEN DOE DOZE[2:0] NDIV[3:0] CDIV[3:0] ORDY LFOR LFOEN NOSCR SOR ADOR SOSCEN ADOEN HFTUN[5:0] PLLR HFFRQ[2:0] EN EN © 2019 Microchip Technology Inc. DC[1:0] OUT CHPOL OPOL CHSYNC DIV[2:0] CLK[3:0] CLPOL BIT CLSYNC SRCS[4:0] CLS[3:0] CHS[3:0] Datasheet DS40001985B-page 585 PIC16(L)F18426/46 Register Summary ...........continued Address 0x089C ... 0x08FF 0x0900 0x0901 0x0902 0x0903 Name Reserved INDF0 INDF1 PCL STATUS 0x0904 FSR0 0x0906 FSR1 0x0908 0x0909 0x090A 0x090B 0x090C 0x090D 0x090E 0x090F 0x0910 ... 0x091E 0x091F 0x0920 ... 0x097F 0x0980 0x0981 0x0982 0x0983 BSR WREG PCLATH INTCON FVRCON Reserved DAC1CON0 DAC1CON1 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE FVREN PEIE FVRRDY TSEN 7:0 7:0 EN OE1 7:0 SEN OUT TSRNG CDAFVR[1:0] INTEDG ADFVR[1:0] PSS[1:0] DAC1R[4:0] NSS Reserved ZCDCON POL INTP INTN DC C Reserved INDF0 INDF1 PCL STATUS 0x0984 FSR0 0x0986 FSR1 0x0988 0x0989 0x098A 0x098B 0x098C ... 0x098E 0x098F 0x0990 0x0991 0x0992 0x0993 0x0994 0x0995 0x0996 0x0997 0x0998 ... 0x09FF 0x0A00 0x0A01 0x0A02 0x0A03 BSR WREG PCLATH INTCON 0x0A04 Bit Pos. 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG EN OUT POL EN OUT POL Reserved CMOUT CM1CON0 CM1CON1 CM1NCH CM1PCH CM2CON0 CM2CON1 CM2NCH CM2PCH 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 MC2OUT HYS INTP NCH[2:0] PCH[2:0] HYS INTP NCH[2:0] PCH[2:0] MC1OUT SYNC INTN DC C SYNC INTN Reserved INDF0 INDF1 PCL STATUS FSR0 7:0 7:0 7:0 7:0 7:0 15:8 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z FSR0[7:0] FSR0[15:8] Datasheet DS40001985B-page 586 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0A06 FSR1 7:0 15:8 FSR1[7:0] FSR1[15:8] 0x0A08 0x0A09 0x0A0A 0x0A0B 0x0A0C ... 0x0A7F 0x0A80 0x0A81 0x0A82 0x0A83 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0A84 FSR0 0x0A86 FSR1 0x0A88 0x0A89 0x0A8A 0x0A8B 0x0A8C ... 0x0AFF 0x0B00 0x0B01 0x0B02 0x0B03 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0B04 FSR0 0x0B06 FSR1 0x0B08 0x0B09 0x0B0A 0x0B0B 0x0B0C ... 0x0B7F 0x0B80 0x0B81 0x0B82 0x0B83 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0B84 FSR0 0x0B86 FSR1 0x0B88 0x0B89 0x0B8A 0x0B8B 0x0B8C ... 0x0BFF 0x0C00 0x0C01 0x0C02 0x0C03 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO Datasheet PD Z DC C DS40001985B-page 587 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0C04 FSR0 7:0 15:8 FSR0[7:0] FSR0[15:8] 0x0C06 FSR1 FSR1[7:0] FSR1[15:8] 0x0C08 0x0C09 0x0C0A 0x0C0B 0x0C0C ... 0x0C7F 0x0C80 0x0C81 0x0C82 0x0C83 BSR WREG PCLATH INTCON 7:0 15:8 7:0 7:0 7:0 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0C84 FSR0 0x0C86 FSR1 0x0C88 0x0C89 0x0C8A 0x0C8B 0x0C8C ... 0x0CFF 0x0D00 0x0D01 0x0D02 0x0D03 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0D04 FSR0 0x0D06 FSR1 0x0D08 0x0D09 0x0D0A 0x0D0B 0x0D0C ... 0x0D7F 0x0D80 0x0D81 0x0D82 0x0D83 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0D84 FSR0 0x0D86 FSR1 0x0D88 0x0D89 0x0D8A 0x0D8B 0x0D8C ... 0x0DFF 0x0E00 0x0E01 0x0E02 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL 7:0 7:0 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] Datasheet DS40001985B-page 588 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0E03 STATUS 0x0E04 FSR0 7:0 7:0 0x0E06 FSR1 0x0E08 0x0E09 0x0E0A 0x0E0B 0x0E0C ... 0x0E7F 0x0E80 0x0E81 0x0E82 0x0E83 BSR WREG PCLATH INTCON 15:8 7:0 15:8 7:0 7:0 7:0 7:0 TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0E84 FSR0 0x0E86 FSR1 0x0E88 0x0E89 0x0E8A 0x0E8B 0x0E8C ... 0x0EFF 0x0F00 0x0F01 0x0F02 0x0F03 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0F04 FSR0 0x0F06 FSR1 0x0F08 0x0F09 0x0F0A 0x0F0B 0x0F0C ... 0x0F7F 0x0F80 0x0F81 0x0F82 0x0F83 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x0F84 FSR0 0x0F86 FSR1 0x0F88 0x0F89 0x0F8A 0x0F8B 0x0F8C ... 0x0FEC 0x0FED BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved STKPTR 7:0 © 2019 Microchip Technology Inc. STKPTR[4:0] Datasheet DS40001985B-page 589 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x0FEE TOS 7:0 15:8 TOS[7:0] TOS[15:8] 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] 0x0FF0 ... 0x0FFF 0x1000 0x1001 0x1002 0x1003 Reserved INDF0 INDF1 PCL STATUS 0x1004 FSR0 0x1006 FSR1 0x1008 0x1009 0x100A 0x100B 0x100C ... 0x107F 0x1080 0x1081 0x1082 0x1083 BSR WREG PCLATH INTCON TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1084 FSR0 0x1086 FSR1 0x1088 0x1089 0x108A 0x108B 0x108C ... 0x10FF 0x1100 0x1101 0x1102 0x1103 BSR WREG PCLATH INTCON Reserved 0x1104 FSR0 0x1106 FSR1 0x1108 0x1109 0x110A 0x110B 0x110C ... 0x117F 0x1180 0x1181 0x1182 0x1183 BSR WREG PCLATH INTCON INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1184 FSR0 0x1186 FSR1 0x1188 BSR 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] Datasheet DS40001985B-page 590 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1189 0x118A WREG PCLATH 7:0 7:0 0x118B 0x118C ... 0x11FF 0x1200 0x1201 0x1202 0x1203 INTCON 7:0 WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1204 FSR0 0x1206 FSR1 0x1208 0x1209 0x120A 0x120B 0x120C ... 0x127F 0x1280 0x1281 0x1282 0x1283 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1284 FSR0 0x1286 FSR1 0x1288 0x1289 0x128A 0x128B 0x128C ... 0x12FF 0x1300 0x1301 0x1302 0x1303 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1304 FSR0 0x1306 FSR1 0x1308 0x1309 0x130A 0x130B 0x130C ... 0x137F 0x1380 0x1381 0x1382 0x1383 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1384 FSR0 0x1386 FSR1 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] Datasheet DS40001985B-page 591 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1388 0x1389 BSR WREG 7:0 7:0 0x138A 0x138B 0x138C ... 0x13FF 0x1400 0x1401 0x1402 0x1403 PCLATH INTCON 7:0 7:0 PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1404 FSR0 0x1406 FSR1 0x1408 0x1409 0x140A 0x140B 0x140C ... 0x147F 0x1480 0x1481 0x1482 0x1483 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1484 FSR0 0x1486 FSR1 0x1488 0x1489 0x148A 0x148B 0x148C ... 0x14FF 0x1500 0x1501 0x1502 0x1503 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1504 FSR0 0x1506 FSR1 0x1508 0x1509 0x150A 0x150B 0x150C ... 0x157F 0x1580 0x1581 0x1582 0x1583 BSR WREG PCLATH INTCON 0x1584 BSR[5:0] WREG[7:0] 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS FSR0 7:0 7:0 7:0 7:0 7:0 15:8 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] Datasheet DS40001985B-page 592 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1586 FSR1 7:0 15:8 FSR1[7:0] FSR1[15:8] 0x1588 0x1589 0x158A 0x158B 0x158C ... 0x15FF 0x1600 0x1601 0x1602 0x1603 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1604 FSR0 0x1606 FSR1 0x1608 0x1609 0x160A 0x160B 0x160C ... 0x167F 0x1680 0x1681 0x1682 0x1683 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1684 FSR0 0x1686 FSR1 0x1688 0x1689 0x168A 0x168B 0x168C ... 0x16FF 0x1700 0x1701 0x1702 0x1703 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1704 FSR0 0x1706 FSR1 0x1708 0x1709 0x170A 0x170B 0x170C ... 0x177F 0x1780 0x1781 0x1782 0x1783 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] TO Datasheet PD Z DC C DS40001985B-page 593 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1784 FSR0 7:0 15:8 FSR0[7:0] FSR0[15:8] 0x1786 FSR1 FSR1[7:0] FSR1[15:8] 0x1788 0x1789 0x178A 0x178B 0x178C ... 0x17FF 0x1800 0x1801 0x1802 0x1803 BSR WREG PCLATH INTCON 7:0 15:8 7:0 7:0 7:0 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1804 FSR0 0x1806 FSR1 0x1808 0x1809 0x180A 0x180B 0x180C ... 0x187F 0x1880 0x1881 0x1882 0x1883 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1884 FSR0 0x1886 FSR1 0x1888 0x1889 0x188A 0x188B 0x188C ... 0x18FF 0x1900 0x1901 0x1902 0x1903 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1904 FSR0 0x1906 FSR1 0x1908 0x1909 0x190A 0x190B 0x190C ... 0x197F 0x1980 0x1981 0x1982 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL 7:0 7:0 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] PCL[7:0] Datasheet DS40001985B-page 594 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1983 STATUS 0x1984 FSR0 7:0 7:0 0x1986 FSR1 0x1988 0x1989 0x198A 0x198B 0x198C ... 0x19FF 0x1A00 0x1A01 0x1A02 0x1A03 BSR WREG PCLATH INTCON 15:8 7:0 15:8 7:0 7:0 7:0 7:0 TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1A04 FSR0 0x1A06 FSR1 0x1A08 0x1A09 0x1A0A 0x1A0B 0x1A0C ... 0x1A7F 0x1A80 0x1A81 0x1A82 0x1A83 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1A84 FSR0 0x1A86 FSR1 0x1A88 0x1A89 0x1A8A 0x1A8B 0x1A8C ... 0x1AFF 0x1B00 0x1B01 0x1B02 0x1B03 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1B04 FSR0 0x1B06 FSR1 0x1B08 0x1B09 0x1B0A 0x1B0B 0x1B0C ... 0x1B7F 0x1B80 0x1B81 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 7:0 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] INDF1[7:0] Datasheet DS40001985B-page 595 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1B82 0x1B83 PCL STATUS 7:0 7:0 0x1B84 FSR0 0x1B86 FSR1 0x1B88 0x1B89 0x1B8A 0x1B8B 0x1B8C ... 0x1BFF 0x1C00 0x1C01 0x1C02 0x1C03 BSR WREG PCLATH INTCON 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1C04 FSR0 0x1C06 FSR1 0x1C08 0x1C09 0x1C0A 0x1C0B 0x1C0C ... 0x1C7F 0x1C80 0x1C81 0x1C82 0x1C83 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1C84 FSR0 0x1C86 FSR1 0x1C88 0x1C89 0x1C8A 0x1C8B 0x1C8C ... 0x1CFF 0x1D00 0x1D01 0x1D02 0x1D03 BSR WREG PCLATH INTCON Reserved 0x1D04 FSR0 0x1D06 FSR1 0x1D08 0x1D09 0x1D0A 0x1D0B 0x1D0C ... 0x1D7F 0x1D80 BSR WREG PCLATH INTCON INDF0 INDF1 PCL STATUS 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 7:0 © 2019 Microchip Technology Inc. INDF0[7:0] Datasheet DS40001985B-page 596 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1D81 0x1D82 INDF1 PCL 7:0 7:0 0x1D83 STATUS 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 0x1D84 FSR0 0x1D86 FSR1 0x1D88 0x1D89 0x1D8A 0x1D8B 0x1D8C ... 0x1DFF 0x1E00 0x1E01 0x1E02 0x1E03 BSR WREG PCLATH INTCON INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved INDF0 INDF1 PCL STATUS 0x1E04 FSR0 0x1E06 FSR1 0x1E08 0x1E09 0x1E0A 0x1E0B 0x1E0C ... 0x1E0E 0x1E0F 0x1E10 0x1E11 0x1E12 0x1E13 0x1E14 0x1E15 0x1E16 0x1E17 0x1E18 0x1E19 0x1E1A 0x1E1B 0x1E1C 0x1E1D 0x1E1E 0x1E1F 0x1E20 0x1E21 0x1E22 0x1E23 0x1E24 0x1E25 0x1E26 0x1E27 0x1E28 0x1E29 0x1E2A 0x1E2B 0x1E2C BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1SEL2 CLC1SEL3 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2SEL2 CLC2SEL3 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3SEL2 CLC3SEL3 CLC3GLS0 CLC3GLS1 CLC3GLS2 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 EN POL OUT G1D4T G2D4T G3D4T G4D4T EN POL G1D4N G2D4N G3D4N G4D4N G1D4T G2D4T G3D4T G4D4T EN POL G1D4N G2D4N G3D4N G4D4N G1D4T G2D4T G3D4T G1D4N G2D4N G3D4N © 2019 Microchip Technology Inc. G1D3T G2D3T G3D3T G4D3T OUT G1D3T G2D3T G3D3T G4D3T OUT G1D3T G2D3T G3D3T INTP G1D3N G2D3N G3D3N G4D3N INTP G1D3N G2D3N G3D3N G4D3N INTP G1D3N G2D3N G3D3N Datasheet MLC4OUT MLC3OUT INTN G4POL G3POL D1S[5:0] D2S[5:0] D3S[5:0] D4S[5:0] G1D2T G1D2N G2D2T G2D2N G3D2T G3D2N G4D2T G4D2N INTN G4POL G3POL D1S[5:0] D2S[5:0] D3S[5:0] D4S[5:0] G1D2T G1D2N G2D2T G2D2N G3D2T G3D2N G4D2T G4D2N INTN G4POL G3POL D1S[5:0] D2S[5:0] D3S[5:0] D4S[5:0] G1D2T G1D2N G2D2T G2D2N G3D2T G3D2N MLC2OUT MODE[2:0] G2POL MLC1OUT G1D1T G2D1T G3D1T G4D1T MODE[2:0] G2POL G1D1N G2D1N G3D1N G4D1N G1POL G1POL G1D1T G2D1T G3D1T G4D1T MODE[2:0] G2POL G1D1N G2D1N G3D1N G4D1N G1POL G1D1T G2D1T G3D1T G1D1N G2D1N G3D1N DS40001985B-page 597 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1E2D 0x1E2E CLC3GLS3 CLC4CON 7:0 7:0 G4D4T EN 0x1E2F 0x1E30 0x1E31 0x1E32 0x1E33 0x1E34 0x1E35 0x1E36 0x1E37 0x1E38 ... 0x1E7F 0x1E80 0x1E81 0x1E82 0x1E83 CLC4POL CLC4SEL0 CLC4SEL1 CLC4SEL2 CLC4SEL3 CLC4GLS0 CLC4GLS1 CLC4GLS2 CLC4GLS3 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 POL G1D4T G2D4T G3D4T G4D4T G4D4N G1D4N G2D4N G3D4N G4D4N G4D3T OUT G1D3T G2D3T G3D3T G4D3T G4D3N INTP G4D2T INTN G4D2N G1D3N G2D3N G3D3N G4D3N G4POL G3POL D1S[5:0] D2S[5:0] D3S[5:0] D4S[5:0] G1D2T G1D2N G2D2T G2D2N G3D2T G3D2N G4D2T G4D2N G4D1T MODE[2:0] G4D1N G2POL G1POL G1D1T G2D1T G3D1T G4D1T G1D1N G2D1N G3D1N G4D1N DC C Reserved INDF0 INDF1 PCL STATUS 0x1E84 FSR0 0x1E86 FSR1 0x1E88 0x1E89 0x1E8A 0x1E8B 0x1E8C ... 0x1E8E 0x1E8F 0x1E90 0x1E91 0x1E92 0x1E93 0x1E94 0x1E95 0x1E96 0x1E97 0x1E98 ... 0x1E9B 0x1E9C 0x1E9D 0x1E9E 0x1E9F ... 0x1EA0 0x1EA1 0x1EA2 0x1EA3 0x1EA4 0x1EA5 ... 0x1EA8 0x1EA9 0x1EAA 0x1EAB ... 0x1EB0 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD Z FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved PPSLOCK INTPPS T0CKIPPS T1CKIPPS T1GPPS T3CKIPPS T3GPPS T5CKIPPS T5GPPS 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PPSLOCKED 7:0 7:0 7:0 PORT[1:0] PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] Reserved T2INPPS T4INPPS T6INPPS Reserved CCP1PPS CCP2PPS CCP3PPS CCP4PPS Reserved SMT1WINPPS SMT1SIGPPS Reserved © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 598 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1EB1 0x1EB2 CWG1PPS CWG2PPS 7:0 7:0 PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 PORT[1:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PORT[1:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] PIN[2:0] 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] 0x1EB3 ... 0x1EB7 0x1EB8 0x1EB9 0x1EBA 0x1EBB 0x1EBC 0x1EBD 0x1EBE 0x1EBF ... 0x1EC2 0x1EC3 0x1EC4 0x1EC5 0x1EC6 0x1EC7 0x1EC8 0x1EC9 0x1ECA 0x1ECB 0x1ECC 0x1ECD ... 0x1EFF 0x1F00 0x1F01 0x1F02 0x1F03 Reserved MDCARLPPS MDCARHPPS MDSRCPPS CLCIN1PPS CLCIN2PPS CLCIN3PPS CLCIN4PPS Reserved ADACTPPS Reserved SSP1CLKPPS SSP1DATPPS SSP1SSPPS SSP2CLKPPS SSP2DATPPS SSP2SSPPS RX1PPS CK1PPS Reserved INDF0 INDF1 PCL STATUS 0x1F04 FSR0 0x1F06 FSR1 0x1F08 0x1F09 0x1F0A 0x1F0B 0x1F0C ... 0x1F0F 0x1F10 0x1F11 0x1F12 0x1F13 0x1F14 0x1F15 0x1F16 ... 0x1F1B 0x1F1C 0x1F1D 0x1F1E 0x1F1F 0x1F20 0x1F21 0x1F22 BSR WREG PCLATH INTCON TO PD Z DC C FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved RA0PPS RA1PPS RA2PPS Reserved RA4PPS RA5PPS 7:0 7:0 7:0 PPS[5:0] PPS[5:0] PPS[5:0] 7:0 7:0 PPS[5:0] PPS[5:0] 7:0 7:0 7:0 7:0 7:0 7:0 7:0 PPS[5:0] PPS[5:0] PPS[5:0] PPS[5:0] PPS[5:0] PPS[5:0] PPS[5:0] Reserved RB4PPS RB5PPS RB6PPS RB7PPS RC0PPS RC1PPS RC2PPS © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 599 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1F23 0x1F24 RC3PPS RC4PPS 7:0 7:0 PPS[5:0] PPS[5:0] 0x1F25 0x1F26 0x1F27 0x1F28 ... 0x1F37 0x1F38 0x1F39 0x1F3A 0x1F3B 0x1F3C 0x1F3D 0x1F3E 0x1F3F 0x1F40 ... 0x1F42 0x1F43 0x1F44 0x1F45 0x1F46 0x1F47 0x1F48 0x1F49 0x1F4A 0x1F4B ... 0x1F4D 0x1F4E 0x1F4F 0x1F50 0x1F51 0x1F52 0x1F53 0x1F54 0x1F55 0x1F56 ... 0x1F7F 0x1F80 0x1F81 0x1F82 0x1F83 RC5PPS RC6PPS RC7PPS 7:0 7:0 7:0 PPS[5:0] PPS[5:0] PPS[5:0] Reserved ANSELA WPUA ODCONA SLRCONA INLVLA IOCAP IOCAN IOCAF 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 ANSELA5 WPUA5 ODCA5 SLRA5 INLVLA5 IOCAP5 IOCAN5 IOCAF5 ANSELA4 WPUA4 ODCA4 SLRA4 INLVLA4 IOCAP4 IOCAN4 IOCAF4 INLVLA3 IOCAP3 IOCAN3 IOCAF3 ANSELA2 WPUA2 ODCA2 SLRA2 INLVLA2 IOCAP2 IOCAN2 IOCAF2 ANSELA1 WPUA1 ODCA1 SLRA1 INLVLA1 IOCAP1 IOCAN1 IOCAF1 ANSELA0 WPUA0 ODCA0 SLRA0 INLVLA0 IOCAP0 IOCAN0 IOCAF0 ANSELC3 WPUC3 ODCC3 SLRC3 INLVLC3 IOCCP3 IOCCN3 IOCCF3 ANSELC2 WPUC2 ODCC2 SLRC2 INLVLC2 IOCCP2 IOCCN2 IOCCF2 ANSELC1 WPUC1 ODCC1 SLRC1 INLVLC1 IOCCP1 IOCCN1 IOCCF1 ANSELC0 WPUC0 ODCC0 SLRC0 INLVLC0 IOCCP0 IOCCN0 IOCCF0 Z DC C WPUA3 Reserved ANSELB WPUB ODCONB SLRCONB INLVLB IOCBP IOCBN IOCBF 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 ANSELB7 WPUB7 ODCB7 SLRB7 INLVLB7 IOCBP7 IOCBN7 IOCBF7 ANSELB6 WPUB6 ODCB6 SLRB6 INLVLB6 IOCBP6 IOCBN6 IOCBF6 ANSELB5 WPUB5 ODCB5 SLRB5 INLVLB5 IOCBP5 IOCBN5 IOCBF5 ANSELB4 WPUB4 ODCB4 SLRB4 INLVLB4 IOCBP4 IOCBN4 IOCBF4 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 ANSELC7 WPUC7 ODCC7 SLRC7 INLVLC7 IOCCP7 IOCCN7 IOCCF7 ANSELC6 WPUC6 ODCC6 SLRC6 INLVLC6 IOCCP6 IOCCN6 IOCCF6 ANSELC5 WPUC5 ODCC5 SLRC5 INLVLC5 IOCCP5 IOCCN5 IOCCF5 ANSELC4 WPUC4 ODCC4 SLRC4 INLVLC4 IOCCP4 IOCCN4 IOCCF4 Reserved ANSELC WPUC ODCONC SLRCONC INLVLC IOCCP IOCCN IOCCF Reserved INDF0 INDF1 PCL STATUS 0x1F84 FSR0 0x1F86 FSR1 0x1F88 0x1F89 0x1F8A 0x1F8B 0x1F8C ... 0x1FE3 0x1FE4 0x1FE5 0x1FE6 BSR WREG PCLATH INTCON 7:0 7:0 7:0 7:0 7:0 15:8 7:0 15:8 7:0 7:0 7:0 7:0 INDF0[7:0] INDF1[7:0] PCL[7:0] TO PD FSR0[7:0] FSR0[15:8] FSR1[7:0] FSR1[15:8] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved STATUS_SHAD WREG_SHAD BSR_SHAD 7:0 7:0 7:0 © 2019 Microchip Technology Inc. TO PD Z DC C WREG[7:0] BSR[5:0] Datasheet DS40001985B-page 600 PIC16(L)F18426/46 Register Summary ...........continued Address Name Bit Pos. 0x1FE7 PCLATH_SHAD 0x1FE8 FSR0_SHAD 0x1FEA FSR1_SHAD 7:0 7:0 15:8 7:0 15:8 © 2019 Microchip Technology Inc. PCLATH[6:0] FSR0_SHAD[7:0] FSR1_SHAD[7:0] Datasheet DS40001985B-page 601 PIC16(L)F18426/46 Instruction Set Summary 37. Instruction Set Summary PIC16(L)F18426/46 devices incorporate the standard set of 50 PIC16 core instructions. Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories: • Byte Oriented • Bit Oriented • Literal and Control The literal and control category contains the most varied instruction word format. The Instruction Set table lists the instructions recognized by the MPASM™ assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine entry takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. 37.1 Read-Modify-Write Operations Any WRITE instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the working (W) register, or the originating file register, depending on the state of the destination designator 'd' (see the table below for more information). A read operation is performed on a register even if the instruction writes to that register. Table 37-1. Opcode Field Descriptions Field Description f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. n FSR or INDF number. (0-1) mm Prepost increment-decrement mode selection Table 37-2. Abbreviation Descriptions Field Description PC Program Counter © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 602 PIC16(L)F18426/46 Instruction Set Summary ...........continued 37.2 Field Description TO Time-Out bit C Carry bit DC Digit Carry bit Z Zero bit PD Power-Down bit Standard Instruction Set Table 37-3. Instruction Set Mnemonic, Operands ADDWF f, d ADDWFC f, d Description Cycles BYTE-ORIENTED OPERATIONS Add WREG and f 1 Add WREG and CARRY bit to f 1 ANDWF f, d AND WREG with f 1 ASRF f, d Arithmetic Right Shift 1 LSLF f, d Logical Left Shift 1 LSRF f, d Logical Right Shift 1 CLRF f Clear f 1 CLRW – Clear WREG 1 COMF f, d Complement f 1 DECF f, d Decrement f 1 INCF f, d Increment f 1 IORWF f, d Inclusive OR WREG with f 1 MOVF f, d Move f 1 MOVWF f Move WREG to f 1 RLF f, d Rotate Left f through Carry 1 RRF f, d Rotate Right f through Carry 1 © 2019 Microchip Technology Inc. Datasheet 14-Bit Opcode MSb LSb 00 0111 dfff ffff 11 1101 dfff ffff 00 0101 dfff ffff 11 0111 dfff ffff 11 0101 dfff ffff 11 0110 dfff ffff 00 0001 lfff ffff 00 0001 0000 00xx 00 1001 dfff ffff 00 0011 dfff ffff 00 1010 dfff ffff 00 0100 dfff ffff 00 1000 dfff ffff 00 0000 1fff ffff 00 1101 dfff ffff 00 1100 dfff ffff Status Affected Notes C, DC, Z 2 C, DC, Z 2 Z 2 C, Z 2 C, Z 2 C, Z 2 Z 2 Z Z 2 Z 2 Z 2 Z 2 Z 2 None 2 C 2 C 2 DS40001985B-page 603 PIC16(L)F18426/46 Instruction Set Summary ...........continued Mnemonic, Operands Description Cycles SUBWF f, d Subtract WREG from f 1 SUBWFB f, d Subtract WREG from f with borrow 1 SWAPF f, d Swap nibbles in f 1 XORWF f, d Exclusive OR WREG with f 1 DECFSZ INCFSZ 14-Bit Opcode MSb LSb 00 0010 dfff ffff 11 1011 dfff ffff 00 1110 dfff ffff 00 0110 dfff ffff f, d BYTE ORIENTED SKIP OPERATIONS Decrement f, Skip if 0 1(2) 00 1011 dfff ffff f, d Increment f, Skip if 0 1111 dfff ffff 00bb bfff ffff 01 01bb bfff ffff BIT-ORIENTED SKIP OPERATIONS Bit Test f, Skip if Clear 1(2) 01 10bb bfff ffff 1010 11bb bfff ffff 11 1110 kkkk kkkk 11 1001 kkkk kkkk 11 1000 kkkk kkkk 00 000 0k kkkk 11 0001 1kkk kkkk 11 0000 kkkk kkkk 11 1100 kkkk kkkk 11 1010 kkkk kkkk BCF f, b BSF f, b 1(2) 00 BIT-ORIENTED FILE REGISTER OPERATIONS Bit Clear f 1 01 Bit Set f 1 BTFSC f, b BTFSS f, b ADDLW k LITERAL OPERATIONS Add literal and WREG 1 ANDLW k AND literal with WREG 1 IORLW k Inclusive OR literal with WREG 1 MOVLB k Move literal to BSR 1 MOVLP k Move literal to PCLATH 1 MOVLW k Move literal to W 1 SUBLW k Subtract W from literal 1 XORLW k Exclusive OR literal with W 1 Bit Test f, Skip if Set 1(2) Status Affected Notes C, DC, Z 2 C, DC, Z 2 None 2 Z 2 None 1, 2 None 1, 2 None 2 None 2 None 1, 2 None 1, 2 C, DC, Z Z Z None None None C, DC, Z Z CONTROL OPERATIONS © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 604 PIC16(L)F18426/46 Instruction Set Summary ...........continued Mnemonic, Operands Description Cycles BRA k Relative Branch 2 BRW — Relative Branch with WREG 2 CALL k Call Subroutine 2 CALLW — Call Subroutine with WREG 2 GOTO k Go to address 2 RETFIE k Return from interrupt 2 RETLW k Return with literal in WREG 2 RETURN — Return from Subroutine 2 14-Bit Opcode MSb LSb 11 001k kkkk kkkk 00 0000 0000 1011 10 0kkk kkkk kkkk 00 0000 0000 1010 10 1kkk kkkk kkkk 00 0000 0000 1001 11 0100 kkkk kkkk 00 0000 0000 1000 00 0000 0110 0100 00 0000 0000 0000 00 0000 0000 0001 00 0000 0110 0011 00 0000 0110 0fff 11 0001 0nkk kkkk 00 0000 0001 0nmm 11 1111 0nkk kkkk 00 0000 0001 1nmm 11 1111 1nkk kkkk Status Affected Notes None None None None None None None None INHERENT OPERATIONS CLRWDT — Clear Watchdog Timer 1 NOP — No Operation 1 RESET — Software device Reset 1 SLEEP — Go into Standby or Idle mode 1 TRIS f Load TRIS register with WREG 1 ADDFSR n, k MOVIW MOVWI C-COMPILER OPTIMIZED Add Literal k to FSRn 1 n, mm Move Indirect FSRn to WREG with pre/post inc/dec modifier, mm 1 k[n] Move INDFn to WREG, Indexed Indirect. 1 n, mm Move WREG to Indirect FSRn with pre/post inc/dec modifier, mm 1 k[n] Move WREG to INDFn, Indexed Indirect. 1 TO, PD None None TO, PD None None Z Z 3. 2, 3 None 2 If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. Details on MOVIW and MOVWI instruction descriptions are available in the next section. © 2019 Microchip Technology Inc. Datasheet 2 None Note:  1. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2. 2, 3 DS40001985B-page 605 PIC16(L)F18426/46 Instruction Set Summary 37.2.1 Standard Instruction Set ADDFSR Add Literal to FSRn Syntax: [ label ] ADDFSR FSRn, k Operands: -32 ≤ k ≤ 31; n ∈ [ 0, 1] Operation: FSR(n) + k → FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW ADD literal to W Syntax: [ label ] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W. ADDWF ADD W to f Syntax: [ label ] ADDWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) → dest Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC f {,d} Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) + (C) → dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. k → (W) © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 606 PIC16(L)F18426/46 Instruction Set Summary ...........continued ANDLW AND literal with W Status Affected: Z Description: The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed in W. ANDWF AND W with f Syntax: [ label ] ANDWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → dest Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift Syntax: [ label ] ASRF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] (f[7]) → dest[7] Operation: (f[7:1]) → dest[6:0] (f[0]) → C Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Register f → C BCF Bit Clear f Syntax: [ label ] BCF f, b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → f[b] Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BRA Relative Branch Syntax: [ label ] BRA label [ label ] BRA $+k Operands: -256 ≤ label - PC + ≤ 255 -256 ≤ k ≤ 255 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 607 PIC16(L)F18426/46 Instruction Set Summary ...........continued BRA Relative Branch Operation: (PC) + 1 + k → PC Status Affected: None Description: Add the signed 9-bit literal ‘k’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a 2-cycle instruction. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) → PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a 2-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF f, b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 1 → (f[b]) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. BTFSC Bit Test File, Skip if Clear Syntax: [ label ] BTFSC f, b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: skip if (f[b]) = 0 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSS f, b Operands: 0 ≤ f ≤ 127 0≤b k Description C = 1, W ≤ k DC = 0, W[3:0] > k[3:0] DC = 1, W[3:0] ≤ k[3:0] SUBWF Subtract W from f Syntax: [ label ] SUBWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (dest) Status Affected: C, DC, Z Description Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f. C =0, W > f C = 1, W ≤ f DC = 0, W[3:0] > f[3:0] DC = 1, W[3:0] ≤ f[3:0] SUBFWB Subtract W from f with Borrow Syntax: [ label ] SUBFWB f {,d} Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) – (f) – (B) → dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f[3:0]) → dest[7:4], (f[7:4]) → dest[3:0] Status Affected: None © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 620 PIC16(L)F18426/46 Instruction Set Summary ...........continued SWAPF Swap Nibbles in f Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). TRIS Load TRIS Register with W Syntax: [ label ] TRIS f Operands: 5≤f≤7 Operation: (W) → TRIS register ‘f’ Status Affected: None Description: Move data from W register to TRIS register. When ‘f’ = 5, TRISA is loaded. When ‘f’ = 6, TRISB is loaded. When ‘f’ = 7, TRISC is loaded. XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W. XORWF Exclusive OR W with f Syntax: [ label ] XORWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 621 PIC16(L)F18426/46 ICSP™ 38. - In-Circuit Serial Programming™ ICSP™ - In-Circuit Serial Programming™ ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • • • • • ICSPCLK ICSPDAT MCLR/VPP VDD VSS In Program/Verify mode the program memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to “Memory Programming Specification” (DS40001970). 38.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 38.2 Low-Voltage Programming Entry Mode ® The Low-Voltage Programming Entry mode allows the PIC Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 4 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See the MCLR Section for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. Related Links 10.4 MCLR Reset 38.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 38-1. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 622 PIC16(L)F18426/46 ICSP™ - In-Circuit Serial Programming™ Figure 38-1. ICD RJ-11 Style Connector Interface VDD ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 38-2. For additional interface recommendations, refer to the specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 38-3 for more information. Figure 38-2. PICkit™ Programmer Style Connector Interface Pin 1 Indicator 1 2 3 4 5 6 Pin Description(1) 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Note:  1. Note:  The 6-pin header (0.100" spacing) accepts 0.025" square pins. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 623 PIC16(L)F18426/46 ICSP™ Figure 38-3. Typical Connection for ICSP™ Programming External Programming VDD Signals - In-Circuit Serial Programming™ Device to be Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 624 PIC16(L)F18426/46 Development Support 39. Development Support The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • • • • • • • • 39.1 Integrated Development Environment – MPLAB® X IDE Software Compilers/Assemblers/Linkers – MPLAB XC Compiler – MPASM™ Assembler – MPLINK™ Object Linker/ MPLIB™ Object Librarian – MPLAB Assembler/Linker/Librarian for Various Device Families Simulators – MPLAB X SIM Software Simulator Emulators – MPLAB REAL ICE™ In-Circuit Emulator In-Circuit Debuggers/Programmers – MPLAB ICD 3 – PICkit™ 3 In-Circuit Debugger Device Programmers – MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits Third-party development tools MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware ® ® development tool that runs on Windows , Linux and Mac OS X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for high-performance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • • • • Color syntax highlighting Smart code completion makes suggestions and provides hints as you type Automatic code formatting based on user-defined rules Live parsing User-Friendly, Customizable Interface: • • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. Call graph window Project-Based Workspaces: • • • Multiple projects Multiple tools Multiple configurations © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 625 PIC16(L)F18426/46 Development Support • Simultaneous debugging sessions File History and Bug Tracking: • • 39.2 Local file history feature Built-in support for Bugzilla issue tracker MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • 39.3 Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. ® The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: • • • • 39.4 Integration into MPLAB X IDE projects User-defined macros to streamline assembly code Conditional assembly for multipurpose source files Directives that allow complete control over the assembly process MPLINK Object Linker/MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • • • Efficient linking of single libraries instead of many smaller files Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing, replacement, deletion and extraction © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 626 PIC16(L)F18426/46 Development Support 39.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • 39.6 Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further runtime analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 39.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-touse, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 39.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/ programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 39.9 PICkit 3 In-Circuit Debugger/Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a full-speed USB interface and can be connected to the target via a © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 627 PIC16(L)F18426/46 Development Support Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 39.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. 39.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a ® ® line of evaluation kits and demonstration software for analog filter design, KeeLoq security ICs, CAN, IrDA , ® PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip webpage (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 39.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • • • • • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS Software Tools from companies, such as Gimpel and Trace Systems Protocol Analyzers from companies, such as Saleae and Total Phase ® Demonstration Boards from companies, such as MikroElektronika, Digilent and Olimex ® Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 628 PIC16(L)F18426/46 Electrical Specifications 40. Electrical Specifications 40.1 Absolute Maximum Ratings(†) Parameter Ambient temperature under bias Storage temperature Voltage on pins with respect to VSS • Rating -40°C to +125°C -65°C to +150°C on VDD pin: PIC16LF18426/46 -0.3V to +4.0V PIC16F18426/46 -0.3V to +6.5V • on MCLR pin: -0.3V to +9.0V • on all other pins: -0.3V to (VDD + 0.3V) Maximum current • on VSS pin(1) • on VDD pin(1) • on any standard I/O pin -40°C ≤ TA ≤ +85°C 85°C < TA ≤ +125°C -40°C ≤ TA ≤ +85°C 85°C < TA ≤ +125°C 250 mA 120 mA 250 mA 85 mA ±50 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) Total power dissipation(2) ±20 mA 800 mW Important:  1. Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Thermal Characteristics to calculate device specifications. 2. Power dissipation is calculated as follows: PDIS = VDD x {IDD - Σ IOH} + Σ {(VDD - VOH) x IOH} + Σ (VOI x IOL) 3. Internal Power Dissipation is calculated as follows: PINTERNAL = IDD x VDD where IDD is current to run the chip alone without driving any load on the output pins. 4. I/O Power Dissipation is calculated as follows: PI/O =Σ(IOL*VOL)+Σ(IOH*(VDD-VOH)) 5. Derated Power is calculated as follows: PDER = PDMAX(TJ-TA)/θJA where TA=Ambient Temperature, TJ = Junction Temperature. NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 40.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: © 2019 Microchip Technology Inc. VDDMIN ≤ VDD ≤ VDDMAX Datasheet DS40001985B-page 629 PIC16(L)F18426/46 Electrical Specifications TA_MIN ≤ TA ≤ TA_MAX Operating Temperature: Parameter VDD — Operating Supply Voltage(1) Ratings VDDMIN (FOSC ≤ 16 MHz) VDDMIN (FOSC ≤ 32 MHz) VDDMAX VDDMIN (FOSC ≤ 16 MHz) PIC16F18426/46 VDDMIN (FOSC ≤ 32 MHz) VDDMAX TA — Operating Ambient Temperature Range TA_MIN Industrial Temperature TA_MAX TA_MIN Extended Temperature TA_MAX Note:  1. See Parameter D002, DC Characteristics: Supply Voltage. +1.8V +2.5V +3.6V +2.3V +2.5V +5.5V PIC16LF18426/46 -40°C +85°C -40°C +125°C Figure 40-1. Voltage Frequency Graph, -40°C ≤ TA≤ +125°C, for PIC16F18426/46 only Rev. 30-000069C 10/27/2016 VDD (V) 5.5 2.5 2.3 0 4 10 16 32 Frequency (MHz) Note:  1. The shaded region indicates the permissible combinations of voltage and frequency. 2. Refer to 40.4.1 External Clock/Oscillator Timing Requirements for each Oscillator mode’s supported frequencies. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 630 PIC16(L)F18426/46 Electrical Specifications Figure 40-2. Voltage Frequency Graph, -40°C ≤ TA≤ +125°C, for PIC16LF18426/46 Devices only VDD (V) Rev. 30-000070B 10/27/2017 3.6 2.5 1.8 4 0 10 16 32 Frequency (MHz) Note:  1. The shaded region indicates the permissible combinations of voltage and frequency. 2. Refer to 40.4.1 External Clock/Oscillator Timing Requirements for each Oscillator mode’s supported frequencies. Related Links 40.3.1 Supply Voltage 40.3 40.3.1 DC Characteristics Supply Voltage Table 40-1.  PIC16LF18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions 1.8 — 3.6 V FOSC ≤ 16 MHz 2.5 — 3.6 V FOSC > 16 MHz 1.5 — — V Device in Sleep mode Supply Voltage D002 VDD RAM Data Retention(1) D003 VDR Power-on Reset Release Voltage(2) © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 631 PIC16(L)F18426/46 Electrical Specifications ...........continued PIC16LF18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. D004 VPOR Characteristic Min. Typ.† Max. Units Conditions — 1.6 — V BOR or LPBOR disabled(3) — 0.8 — V BOR or LPBOR disabled(3) — — V/ms BOR or LPBOR disabled(3) Power-on Reset Rearm Voltage(2) D005 VPORR VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD 0.05 † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2. See the following figure, POR and POR REARM with Slow Rising VDD. 3. Please see 40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications for BOR and LPBOR trip point information. PIC16F18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions 2.3 — 5.5 V FOSC ≤ 16 MHz 2.5 — 5.5 V FOSC > 16 MHz 1.7 — — V Device in Sleep mode — 1.6 — V BOR or LPBOR disabled(3) — 1.5 — V BOR or LPBOR disabled(3) — — V/ms BOR or LPBOR disabled(3) Supply Voltage D002 VDD RAM Data Retention(1) D003 VDR Power-on Reset Release Voltage(2) D004 VPOR Power-on Reset Rearm Voltage(2) D005 VPORR VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD © 2019 Microchip Technology Inc. 0.05 Datasheet DS40001985B-page 632 PIC16(L)F18426/46 Electrical Specifications ...........continued PIC16F18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.POR AND POR REARM WITH SLOW RISING VDD.vsdx Filename: Title: Note:  Last Edit: 7/31/2019 First 1. Used: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. Notes: 2. See the following figure, POR and POR REARM with Slow Rising VDD. 3. Please see 40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications for BOR and LPBOR trip point information. Figure 40-3. POR and POR Rearm with Slow Rising VDD VDD VPOR VPORR SVDD VSS NPOR (1) POR REARM VSS Note:  1. When NPOR is low, the device is held in Reset. 40.3.2 Supply Current (IDD)(1,2,4) Table 40-2.  PIC16LF18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D100 IDDXT4 D101 IDDHFO16 Conditions Min. Typ.† Max. Units XT = 4 MHz — 465 670 μA 3.0V HFINTOSC = 16 MHz — 2.1 2.6 mA 3.0V © 2019 Microchip Technology Inc. Datasheet VDD Note DS40001985B-page 633 PIC16(L)F18426/46 Electrical Specifications ...........continued PIC16LF18426/46 only Standard Operating Conditions (unless otherwise stated) Conditions Param. No. Sym. Device Characteristics Min. Typ.† Max. Units D102 IDDHFOPLL HFINTOSC = 32 MHz — 3.9 4.8 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 3.6 4.4 mA 3.0V D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.5 1.9 mA 3.0V DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.5 — mA 3.0V D105 IDDDOZE (3) VDD Note † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. 2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see CPUDOZE register). 4. PMD bits are all in the default state, no modules are disabled. PIC16F18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D100 IDDXT4 D101 Conditions Min. Typ.† Max. Units XT = 4 MHz — 515 710 μA 3.0V IDDHFO16 HFINTOSC = 16 MHz — 2.2 2.7 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 4.0 4.9 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 3.7 4.5 mA 3.0V D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.6 2.0 mA 3.0V DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.6 — mA 3.0V D105 IDDDOZE (3) © 2019 Microchip Technology Inc. Datasheet VDD Note DS40001985B-page 634 PIC16(L)F18426/46 Electrical Specifications ...........continued PIC16F18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. Conditions Units VDD Note † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. 2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see CPUDOZE register). 4. PMD bits are all in the default state, no modules are disabled. Related Links 12.5.2 CPUDOZE 40.3.3 Power-Down Current (IPD)(1,2) Table 40-3.  PIC16LF18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D200 IPD D201 Conditions Min. Typ.† Max. +85°C Max. +125°C Units IPD Base — 0.08 2.0 7 μA 3.0V IPD_WDT Low-Frequency Internal Oscillator/WDT — 0.8 2.8 8 μA 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) — 1.0 3.8 9 μA 3.0V D203 IPD_FVR FVR — 46 76 77 μA 3.0V D204 IPD_BOR Brown-out Reset (BOR) — 10 15 18 μA 3.0V D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.13 2.2 8 μA 3.0V D207 IPD_ADCA ADC - Nonconverting — 0.08 2.0 7.0 μA 3.0V D208 IPD_CMP Comparator — 30 57 58 μA 3.0V © 2019 Microchip Technology Inc. Datasheet VDD Note ADC not converting (4) DS40001985B-page 635 PIC16(L)F18426/46 Electrical Specifications ...........continued PIC16LF18426/46 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. +85°C Max. +125°C Units Conditions VDD Note † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPDcurrent from this limit. Max. values should be used when calculating total current consumption. 2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. 3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4. ADC clock source is FRC. PIC16F18426/46 only Standard Operating Conditions (unless otherwise stated), VREGPM = 1 Param. No. Sym. Device Characteristics IPD IPD Base D201 IPD_WDT D202 Conditions Min. Typ.† Max. +85°C Max. +125°C Units — 0.40 2.5 8 μA 3.0V — 18 25 30 μA 3.0V Low-Frequency Internal Oscillator/WDT — 1.0 2.9 9 μA 3.0V IPD_SOSC Secondary Oscillator (SOSC) — 1.2 4.3 9.2 μA 3.0V D203 IPD_FVR FVR — 40 69 70 μA 3.0V D204 IPD_BOR Brown-out Reset (BOR) — 11 16 19 μA 3.0V D207 IPD_ADCA ADC - Nonconverting — 0.38 2.5 8.0 μA 3.0V D208 IPD_CMP Comparator — 31 58 59 μA 3.0V D200 D200A VDD Note VREGPM = 0 ADC not converting (4) † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPDcurrent from this limit. Max. values should be used when calculating total current consumption. 2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. 3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4. ADC clock source is FRC. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 636 PIC16(L)F18426/46 Electrical Specifications 40.3.4 I/O Ports Table 40-4.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Input Low Voltage VIL I/O PORT: D300 — • with TTL buffer D301 — D302 — • with Schmitt Trigger buffer Typ.† Max. Units — — — 0.8 0.15 VDD 0.2 VDD V V V Conditions 4.5V≤VDD≤5.5V 1.8V≤VDD≤4.5V 2.0V≤VDD≤5.5V D303 • with I2C levels — — 0.3 VDD V D304 • with SMBus levels — — 0.8 V — — 0.2 VDD V — — — — — — V V V 0.7 VDD — — V 2.1 — — V 0.7 VDD — — V — ±5 ±125 nA VSS≤VPIN≤VDD, Pin at high-impedance, 85°C — ±5 ±1000 nA VSS≤VPIN≤VDD, Pin at high-impedance, 125°C — ±50 ±200 nA VSS≤VPIN≤VDD, Pin at high-impedance, 85°C 25 120 200 μA VDD=3.0V, VPIN=VSS Standard I/O PORTS — — 0.6 V IOL = 10 mA, VDD = 3.0V Standard I/O PORTS VDD-0.7 — — V IOH = 6 mA, VDD = 3.0V — 5 50 pF D305 Input High Voltage VIH D320 D321 D322 MCLR I/O PORT: • • 2.0 0.25 VDD+0.8 0.8VDD with Schmitt Trigger buffer with TTL buffer D323 • with I2C levels D324 • with SMBus levels D325 MCLR (1) Input Leakage Current D340 IIL I/O PORTS D341 MCLR(2) D342 Weak Pull-up Current D350 IPUR Output Low Voltage D360 VOL Output High Voltage D370 VOH All I/O Pins D380 CIO 2.7V≤VDD≤5.5V © 2019 Microchip Technology Inc. Datasheet 4.5V≤VDD≤5.5V 1.8V≤VDD≤4.5V 2.0V≤VDD≤5.5V 2.7V≤VDD≤5.5V DS40001985B-page 637 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. Units Conditions † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Negative current is defined as current sourced by the pin. 2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 40.3.5 Memory Programming Specifications Table 40-5.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Device Characteristics Min. Typ† Max. Units Conditions (Note 2, Note 3) High Voltage Entry Programming Mode Specifications MEM01 VIHH Voltage on MCLR/VPP pin to enter programming mode 8 — 9 V MEM02 IPPGM Current on MCLR/VPP pin during programming mode — 1 — mA (Note 2) (Note 4) Programming Mode Specifications MEM10 VBE VDD for Bulk Erase — — — V MEM11 IDDPGM Supply Current during Programming operation — — 10 mA 100k — — E/W -40°C≤TA≤+85°C Year Provided no other specifications are violated Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance MEM21 TD_RET Characteristic Retention MEM22 ND_REF Total Erase/Write Cycles before Refresh MEM23 VD_RW VDD for Read or Erase/Write operation MEM24 TD_BEW Byte Erase and Write Cycle Time — 40 — — — VDDMIN — VDDMAX V — 4.0 5.0 ms 10k — — E/W 100k E/W Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance © 2019 Microchip Technology Inc. Datasheet -40°C≤Ta≤+85°C (Note 1) DS40001985B-page 638 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. MEM32 Sym. TP_RET Device Characteristics Characteristic Retention Min. Typ† Max. Units Conditions Provided no other specifications are violated — 40 — Year MEM33 VP_RD VDD for Read operation VDDMIN — VDDMAX V MEM34 VP_REW VDD for Row Erase or Write operation VDDMIN — VDDMAX V MEM35 TP_REW Self-Timed Row Erase or Self-Timed Write — 2.0 2.8 ms † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one SelfTimed Write. 2. Required only if CONFIG4, bit LVP is disabled. 3. The MPLAB® ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between the ICD2 and target system when programming or debugging with the ICD2. 4. Refer to the “PIC16(L)F184XX Memory Programming Specification” document for description. Related Links 4.7.4 CONFIG4 40.3.6 Thermal Characteristics Table 40-6.  Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Typ. Units Conditions TH01 Thermal Resistance Junction to Ambient 70.0 °C/W 14-pin PDIP package 95.3 °C/W 14-pin SOIC package θJA 100.0 °C/W 14-pin TSSOP package © 2019 Microchip Technology Inc. Datasheet 51.5 °C/W 16-pin UQFN 4x4mm package 62.2 °C/W 20-pin PDIP package 87.3 °C/W 20-pin SSOP package 77.7 °C/W 20-pin SOIC package 43.0 °C/W 20-pin UQFN 4x4mm package DS40001985B-page 639 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Typ. Units Conditions TH02 Thermal Resistance Junction to Case 32.75 °C/W 14-pin PDIP package θJC TH03 TJMAX Maximum Junction Temperature TH04 PD Power Dissipation TH05 31.0 °C/W 14-pin SOIC package 24.4 °C/W 14-pin TSSOP package 5.4 °C/W 16-pin UQFN 4x4mm package 27.5 °C/W 20-pin PDIP package 31.1 °C/W 20-pin SSOP package 23.1 °C/W 20-pin SOIC package 5.3 °C/W 20-pin UQFN 4x4mm package 150 °C — W PD=PINTERNAL+PI/O PINTERNAL Internal Power Dissipation — W PINTERNAL=IDDxVDD(1) TH06 PI/O I/O Power Dissipation — W PI/O=Σ(IOL*VOL)+Σ(IOH*(VDD-VOH)) TH07 PDER Derated Power — W PDER=PDMAX (TJ-TA)/θJA(2) Note:  1. IDD is current to run the chip Filename: alone without driving any load on the output pins. 10-000133A.vsd LOAD CONDITION 2. TA = Ambient Temperature, TTitle: J = Junction Temperature. Last Edit: First Used: Note: 40.4 8/1/2013 PIC16F1508/9 AC Characteristics Figure 40-4. Load Conditions Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 640 Filename: Title: Last Edit: First Used: Notes: 40.4.1 Ext Clock Osc Timing Requirements.vsdx PIC16(L)F18426/46 8/1/2019 Electrical Specifications External Clock/Oscillator Timing Requirements Figure 40-5. Clock Timing Rev. Ext Clock 8/1/2019 OS2, OS4, OS6 Q4 CLKIN Q1 OS1,OS3,OS5 OS7,OS8,OS9 Q2 Q3 Q4 Q1 OS10,OS20 CLKOUT OS21 Note:  See table below. Table 40-7.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency — — 500 kHz OS2 TECL_DC Clock Duty Cycle 40 — 60 % ECM Oscillator OS3 FECM Clock Frequency — — 4 MHz OS4 TECM_DC Clock Duty Cycle 40 — 60 % ECH Oscillator OS5 FECH Clock Frequency — — 32 MHz OS6 TECH_DC Clock Duty Cycle 40 — 60 % Clock Frequency — — 100 kHz Note 4 Clock Frequency — — 4 MHz Note 4 Clock Frequency — — 20 MHz Note 4 Clock Frequency 32.4 32.768 33.1 kHz Note 4 — — 32 MHz (Note 2, Note 3) LP Oscillator OS7 FLP XT Oscillator OS8 FXT HS Oscillator OS9 FHS Secondary Oscillator OS10 FSEC System Oscillator OS20 FOSC System Clock Frequency © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 641 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic OS21 FCY Instruction Frequency OS22 TCY Instruction Period Min. Typ. † Max. Units — FOSC/4 — MHz 125 1/FCY — ns Conditions * These parameters are characterized but not tested. † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in the “Oscillator Module (with Fail-Safe Clock Monitor)” section. 3. The system clock frequency (FOSC) must meet the voltage requirements defined in the “Standard Operating Conditions” section. 4. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used. Related Links 8. OSC - Oscillator Module 40.2 Standard Operating Conditions 40.4.2 Internal Oscillator Parameters(1) Table 40-8.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic OS50 Precision Calibrated HFINTOSC Frequency FHFOSC Min. Typ. † Max. Units Conditions — 4 — MHz (Note 2) 8 12 16 32 OS51 FHFOSCLP Low-Power Optimized HFINTOSC Frequency 0.92 1 1.08 MHz -40°C to 85°C 1.84 2 2.16 MHz -40°C to 85°C 0.88 1 1.12 MHz -40°C to 125 °C 1.76 2 2.24 MHz -40°C to 125°C OS52 FMFOSC Internal Calibrated MFINTOSC Frequency — 500 — kHz OS53 FLFOSC Internal LFINTOSC Frequency — 31 — kHz © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 642 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic OS54 THFOSCST OS56 TLFOSCST Min. Typ. † Max. Units Conditions HFINTOSC Wake-up from Sleep Start-up Time — 11 20 μs VREGPM=0 — 85  — μs VREGPM=1 LFINTOSC Wake-up from Sleep Start-up Time — 0.2 — ms † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:    1. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 2. See the figure below. Figure 40-6. Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 0 ± 5% -40 1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 40.4.3 PLL Specifications Table 40-9.   Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic PLL01 FPLLIN PLL02 FPLLOUT © 2019 Microchip Technology Inc. Min. Typ. † Max. Units PLL Input Frequency Range 4 — 16 MHz PLL Output Frequency Range 16 — 32 MHz Datasheet Conditions (Note 1) DS40001985B-page 643 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic PLL03 FPLLST PLL Lock Time from Start-up PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) Min. Typ. † Max. Units — 200 — μs -0.25 — 0.25 % Conditions * - These parameters are characterized but not tested. CLKOUTis and Timing.vsdx † - Filename: Data in “Typ” column atIO5.0V, 25°C unless otherwise stated. These parameters are for design guidance only Title: andLast areEdit: not tested.8/1/2019 First Used: Note:  Notes: 1. The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002. 40.4.4 I/O and CLKOUT Timing Specifications Figure 40-7. CLKOUT and I/O Timing Rev. CLK OUT and 8/1/2019 Cycle Read Q2 Fetch Q1 Write Q4 Execute Q3 FOSC IO1 IO2 IO5 CLKOUT IO8, IO9 IO4 IO6, IO7 I/O pin (Input) IO3 IO10, IO11 I/O pin (Output) Table 40-10. I/O and CLKOUT Timing Specifications Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic IO1* TCLKOUTH CLKOUT rising edge delay (rising edge FOSC (Q1 cycle) to falling edge CLKOUT — — 70 ns IO2* TCLKOUTL CLKOUT falling edge delay (rising edge FOSC (Q3 cycle) to rising edge CLKOUT — — 72 ns IO3* TIO_VALID Port output valid time (rising edge FOSC (Q1 cycle) to port valid) — 50 70 ns IO4* TIO_SETUP Port input setup time (Setup time before rising edge FOSC – Q2 cycle) 20 — — ns © 2019 Microchip Technology Inc. Min. Typ. † Max. Units Conditions Datasheet DS40001985B-page 644 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions IO5* TIO_HOLD Port input hold time (Hold time after rising edge FOSC – Q2 cycle) IO6* 50 — — ns TIOR_SLREN Port I/O rise time, slew rate enabled — 25 — ns VDD=3.0V IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled — 5 — ns VDD=3.0V IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD=3.0V IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD=3.0V IO10* TINT INT pin high or low time to trigger an interrupt 25 — — ns IO11* TIOC Interrupt-on-Change minimum high or low time to trigger interrupt 25 — — ns * - These parameters are characterized but not tested. 40.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power BrownOut Reset Specifications Figure 40-8. Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Rev. 30-000075A 4/6/2017 VDD MCLR RST01 Internal POR PWRT Time-out RST04 RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST02 RST03 RST02 I/O pins Note:  1. Asserted low. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 645 PIC16(L)F18426/46 Electrical Specifications Figure 40-9. Brown-out Reset Timing and Characteristics Rev. 30-000076A 4/6/2017 VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) RST08 Reset RST04(1) (due to BOR) Note:  1. Only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0. Table 40-11.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. RST01* TMCLR MCLR Pulse Width 2 Low to ensure Reset RST02* TIOZ I/O high-impedance — from Reset detection RST03 TWDT Watchdog Timer — Time-out Period RST04* TPWRT Power-up Timer — Period RST05 TOST Oscillator Start-up — Timer Period(1, 2) RST06 VBOR Brown-out Reset 2.55 Voltage 2.30 1.80 Typ. † — Max. — Units μs — 2 μs 16 — ms 65 — ms 1024 — TOSC 2.7 2.85 2.45 2.60(3) V V 1.90 2.05 V Conditions 1:512 Prescaler BORV=0 BORV=1(F devices only) BORV=1(LF Devices only) RST07 VBORHYS Brown-out Reset — Hysteresis RST08 TBORDC Brown-out Reset — Response Time RST09 VLPBOR Low-Power Brown-out 1.8 Reset Voltage * - These parameters are characterized but not tested. 40 — mV 3 — μs 1.9 2.2 V LF Devices only † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 3. This value corresponds to VBORMAX © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 646 PIC16(L)F18426/46 Electrical Specifications 40.4.6 Temperature Indicator Requirements Table 40-12.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. TS01 TACQMIN Minimum ADC Acquisition Time Delay TS02 Mv Voltage Sensitivity Max. Units Conditions — 25 — μs High Range — -3.684 — mV/°C TSRNG = 1 Low Range — -3.456 — mV/°C TSRNG = 0 * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 40.4.7 Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2) Table 40-13.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, TAD = 1μs Param No. Sym. Characteristic Min. Typ. † Max. AD01 NR AD02 Units Conditions Resolution — — 12 bit EIL Integral Error — ±1.0 ±2.0 LSb ADCREF+=3.0V, ADCREF= 0V AD03 EDL Differential Error — ±1.0 ±1.0 LSb ADCREF+=3.0V, ADCREF= 0V AD04 EOFF Offset Error — 0.5 ±6.0 LSb ADCREF+=3.0V, ADCREF= 0V AD05 EGN Gain Error — ±0.2 ±6.0 LSb ADCREF+=3.0V, ADCREF= 0V AD06 VADREF ADC Reference Voltage (ADREF+ - ADREF-) 1.8 — VDD V AD07 VAIN Full-Scale Range ADREF- — ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source — 10 — kΩ AD09 RVREF ADC Voltage Reference Ladder Impedance — 50 — kΩ * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors. 2. The ADC conversion result never decreases with an increase in the input and has no missing codes. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 647 PIC16(L)F18426/46 Electrical Specifications 40.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications Table 40-14.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic AD20 TAD ADC Clock Period AD21 TCNV Conversion Time(1) AD22 Min. Typ. † Max. Units Conditions 0.5 — 9 μs Using FOSC as the ADC clock source ADCS = 1 — 2 — μs Using FRC as the ADC clock source ADCS = 0 — 14TAD+2TCY — — Using FOSC as the ADC clock source ADCS = 1 — 16TAD+2TCY — — Using FRC as the ADC clock source ADCS = 0 AD23 TACQ Acquisition Time — 2 — μs AD24 THCD Sample and Hold Capacitor Disconnect Time — 2TAD+1TCY — — Using FOSC as the ADC clock source ADCS = 1 — 3TAD+2TCY — — Using FRC as the ADC clock source ADCS = 0 * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Does not apply for the FRC oscillator. Figure 40-10. ADC Conversion Timing (ADC Clock FOSC-Based) Rev. 10-000321B 7/31/2019 BSF ADCON0, GO 1 TCY AD22 AD23 1 TCY 1 TCY AD20 ADC_clk ADRES OLD DATA NEW DATA ADIF GO Sample © 2019 Microchip Technology Inc. DONE Sampling Stopped Datasheet DS40001985B-page 648 PIC16(L)F18426/46 Electrical Specifications Figure 40-11. ADC Conversion Timing (ADC Clock from FRC) Rev. 10-000328B 7/31/2019 BSF ADCON0, GO 1 TCY AD22 AD23 2 TCY(1) AD21 ADC_clk ADRES OLD DATA NEW DATA ADIF GO DONE Sample Sampling Stopped Note:  1. If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. 40.4.9 Comparator Specifications Table 40-15.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions CM01 VIOFF Input Offset Voltage — — ±60 mV VICM = VDD/2 CM02 VICM Input Common Mode Range GND — VDD V CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB CM04 VHYST Comparator Hysteresis 15 25 35 mV CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns Response Time, Falling Edge — 220 500 ns Mode Change to Valid Output — — 10 ns CM06* TMCV2VO(2) * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. 2. A mode change includes changing any of the control register values, including module enable. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 649 PIC16(L)F18426/46 Electrical Specifications 40.4.10 5-Bit DAC Specifications Table 40-16.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic DSB01 VLSB DSB02 DSB03* DSB04* Min. Typ. † Max. Units Step Size — (VDACREF+VDACREF-)/32 — V VACC Absolute Accuracy — — ±0.5 LSb RUNIT Unit Resistor Value — 5000 — Ω — — 10 μs TST Settling Time(1) Conditions * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Settling time measured while DACR[4:0] transitions from ‘00000’ to ‘01111’. 40.4.11 Fixed Voltage Reference (FVR) Specifications Table 40-17.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units FVR01 VFVR1 FVR02 Conditions 1x Gain (1.024V) -4 — +4 % VDD≥2.5V, -40°C to 85°C VFVR2 2x Gain (2.048V) -4 — +4 % VDD≥2.5V, -40°C to 85°C FVR03 VFVR4 4x Gain (4.096V) -5 — +5 % VDD≥4.75V, -40°C to 85°C FVR04 TFVRST FVR Start-up Time — 60 — μs 40.4.12 Zero-Cross Detect (ZCD) Specifications Table 40-18.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units ZC01 VPINZC Voltage on Zero Cross Pin — 0.75 — V ZC02 IZCD_MAX Maximum source or sink current — — 600 μA ZC03 TRESPH Response Time, Rising Edge — 1 — μs TRESPL Response Time, Falling Edge — 1 — μs Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 650 PIC16(L)F18426/46 Electrical Specifications 40.4.13 Timer0 and Timer1 External Clock Requirements Table 40-19.  Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. Sym. Characteristic 40* TT0H 41* TT0L Min. Typ. † Max. T0CKI High No Prescaler Pulse Width With Prescaler 0.5TCY+20 — — ns 10 — — ns T0CKI Low No Prescaler Pulse Width With Prescaler 0.5TCY+20 — — ns 10 — — ns Greater of: 20 or (TCY +40)/N — — ns Synchronous, No Prescaler 0.5TCY+20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous, No Prescaler 0.5TCY+20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Greater of: 30 or (TCY +40)/N — — ns 60 — — ns 2 TOSC — 7 TOSC — 42* TT0P T0CKI Period 45* TT1H T1CKI High Time 46* 47* TT1L TT1P T1CKI Low Time T1CKI Input Synchronous Period Asynchronous 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Units Conditions N = Prescale value N = Prescale value Timers in Sync mode * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 651 PIC16(L)F18426/46 Electrical Specifications Figure 40-12. Timer0 and Timing1 External Clock Timings Rev. 30-000079A 4/6/2017 T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 40.4.14 Capture/Compare/PWM Requirements (CCP) Table 40-20.  Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. Sym. Characteristic CC01* TCCL CCPx Input Low Time CC02* CC03* TCCH TCCP CCPx Input High Time Min. Typ. † Max. No Prescaler 0.5TCY+20 — — ns With Prescaler 20 — — ns No Prescaler 0.5TCY+20 — — ns With Prescaler 20 — — ns (3TCY+40)/N — — ns CCPx Input Period Units Conditions N = Prescale value * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Figure 40-13. Capture/Compare/PWM Timings (CCP) Rev. 30-000080A 4/6/2017 CCPx (Capture mode) CC01 CC02 CC03 Note:  Refer to Figure 40-4 for load conditions. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 652 PIC16(L)F18426/46 Electrical Specifications 40.4.15 Configurable Logic Cell (CLC) Characteristics Table 40-21.  Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions CLC01* TCLCIN CLC input time — 7 OS5 ns (Note1) CLC02* TCLC CLC module input to output propagation time — 24 — ns VDD = 1.8V — 12 — ns VDD > 3.6V CLC output time Rise Time — OS7 — — (Note1) Fall Time — OS8 — — (Note1) — 32 FOSC CLC03* CLC04* TCLCOUT FCLCMAX CLC maximum switching frequency MHz * - These parameters are characterized but not tested. † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. See “I/O and CLKOUT Timing Specifications” for OS5, OS7 and OS8 rise and fall times. Figure 40-14. CLC Propagation Timing Rev. 30-000153A 10/27/2017 CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC01 CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC02 CLC03 Related Links 40.4.4 I/O and CLKOUT Timing Specifications 40.4.16 EUSART Synchronous Transmission Requirements Table 40-22.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic US120 TCKH2DTV © 2019 Microchip Technology Inc. Min. Max. Units SYNC XMIT (Master and Slave) — 80 ns 3.0V≤VDD≤5.5V Clock high to data-out valid — 100 ns 1.8V≤VDD≤5.5V Datasheet Conditions DS40001985B-page 653 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic US121 TCKRF US122 TDTRF Min. Max. Units Conditions Clock out rise time and fall time — 45 ns 3.0V≤VDD≤5.5V (Master mode) — 50 ns 1.8V≤VDD≤5.5V Data-out rise time and fall time — 45 ns 3.0V≤VDD≤5.5V — 50 ns 1.8V≤VDD≤5.5V Figure 40-15. EUSART Synchronous Transmission (Master/Slave) Timing Rev. 30-000081A 4/6/2017 CK US121 US121 DT US122 US120 Note:  Refer to Figure 40-4 for load conditions. 40.4.17 EUSART Synchronous Receive Requirements Table 40-23.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Min. Max. Units 10 — ns 15 — ns Conditions Data-setup before CK ↓ (DT hold time) US126 TCKL2DTL Data-hold after CK ↓ (DT hold time) Figure 40-16. EUSART Synchronous Receive (Master/Slave) Timing Rev. 30-000082A 4/6/2017 CK US125 DT US126 Note:  Refer to Figure 40-4 for load conditions. 40.4.18 SPI Mode Requirements Table 40-24.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic SP70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input TSSL2SCL © 2019 Microchip Technology Inc. Min. Typ. † Max. Units 2.25*TCY — — ns Datasheet Conditions DS40001985B-page 654 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units SP71* TSCH SP72* SP73* SCK input high time (Slave mode) TCY + 20 — — ns TSCL SCK input low time (Slave mode) TCY + 20 — — ns TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns Hold time of SDI data input to SCK edge 100 — — ns SDO data output rise time — 10 25 ns 3.0V≤VDD≤5.5V — 25 50 ns 1.8V≤VDD≤5.5V TDIV2SCL SP74* TSCH2DIL, TSCL2DIL SP75* TDOR Conditions SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS↑ to SDO output highimpedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) — 10 25 ns 3.0V≤VDD≤5.5V — 25 50 ns 1.8V≤VDD≤5.5V SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDO data output valid after SCK edge — — 50 ns 3.0V≤VDD≤5.5V — — 145 ns 1.8V≤VDD≤5.5V 1 TCY — — ns — — 50 ns 1.5 TCY + 40 — — ns TSCL2DOV SP81* TDOV2SCH, TDOV2SCL SDO data output setup to SCK edge SP82* TSSL2DOV SDO data output valid after SS↓ edge SP83* TSCH2SSH, SS ↑after SCK edge TSCL2SSH * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 655 PIC16(L)F18426/46 Electrical Specifications Figure 40-17. SPI Master Mode Timing (CKE = 0, SMP = 0) Rev. 30-000083A 4/6/2017 SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note:  Refer to Figure 40-4 for load conditions. Figure 40-18. SPI Master Mode Timing (CKE = 1, SMP = 1) Rev. 30-000084A 4/6/2017 SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb SP78 LSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note:  Refer to Figure 40-4 for load conditions. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 656 PIC16(L)F18426/46 Electrical Specifications Figure 40-19. SPI Slave Mode Timing (CKE = 0) Rev. 30-000085A 4/6/2017 SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note:  Refer to Figure 40-4 for load conditions. Figure 40-20. SPI Slave Mode Timing (CKE = 1) Rev. 30-000086A 4/6/2017 SS SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note:  Refer to Figure 40-4 for load conditions. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 657 PIC16(L)F18426/46 Electrical Specifications 40.4.19 I2C Bus Start/Stop Bits Requirements Table 40-25.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. SP90* Characteristic TSU:STA Start condition 100 kHz mode 4700 — — 600 — — THD:STA Start condition 100 kHz mode 4000 — — 600 — — TSU:STO Stop condition 100 kHz mode 4700 — — 600 — — THD:STO Stop condition 100 kHz mode 4000 — — — — Setup time SP91* Hold time SP92* Setup time SP93* Min. Typ. † Max. Units Conditions Hold time 400 kHz mode 400 kHz mode 400 kHz mode 400 kHz mode 600 ns Only relevant for Repeated Start Setup time 400 kHz mode 600 condition ns After this period, the first clock Hold time 400 kHz mode 600 — — pulse is generated ns ns * - These parameters are characterized but not tested. Figure 40-21. I2C Bus Start/Stop Bits Timing Rev. 30-000087A 4/6/2017 SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note:  Refer to Figure 40-4 for load conditions. 40.4.20 I2C Bus Data Requirements Table 40-26.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Max. Units SP100* THIGH Clock high time 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1.5TCY — SSP module © 2019 Microchip Technology Inc. Datasheet Conditions DS40001985B-page 658 PIC16(L)F18426/46 Electrical Specifications ...........continued Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Max. Units SP101* TLOW Clock low time 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns — 250 ns 400 kHz mode 20 + 0.1CB 250 ns 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 100 kHz mode 250 — ns 400 kHz mode 100 — ns 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs — 400 pF SSP module SP102* SP103* SP106* SP107* SP109* SP110* SP111 TR TF THD:DAT TSU:DAT TAA TBUF CB SDA and SCL rise time SDA and 100 kHz SCL fall time mode Data input hold time Data input setup time Output valid from clock Bus capacitive loading Conditions CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start * - These parameters are characterized but not tested. Note:  1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT≥250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 659 PIC16(L)F18426/46 Electrical Specifications Figure 40-22. I2C Bus Data Timing Rev. 30-000088A 4/6/2017 SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note:  Refer to Figure 40-4 for load conditions. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 660 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables 41. DC and AC Characteristics Graphs and Tables The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note:  The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Note:  “Typical” represents the mean of the distribution at 25°C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range. 41.1 Graphs Figure 41-1. IPD Base, Low-Power Sleep Mode, PIC16LF18426/46 only © 2019 Microchip Technology Inc. Figure 41-2. IPD Watchdog Timer (WDT), PIC16LF18426/46 only Datasheet DS40001985B-page 661 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-3. IPD Watchdog Timer (WDT), PIC16F18426/46 only Figure 41-4. IPD Fixed Voltage Reference (FVR), PIC16LF18426/46 only Figure 41-5. IPD Fixed Voltage Reference (FVR), PIC16F18426/46 only Figure 41-6. IPD Brown-Out Reset (BOR), BORV = 1, PIC16LF18426/46 only Figure 41-7. IPD Brown-Out Reset (BOR), BORV = 1, PIC16F18426/46 only Figure 41-8. IPD Low-Power Brown-Out Reset, LPBOR = 0, PIC16LF18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 662 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-9. IPD Comparator, PIC16LF18426/46 only Figure 41-10. IPD Comparator, PIC16F18426/46 only Figure 41-11. IPD Base, 01, PIC16F18426/46 only Figure 41-12. IPD Base, 11, PIC16F18426/46 only Figure 41-13. IDD XT Oscillator 4 MHz, PIC16LF18426/46 only Figure 41-14. IDD XT Oscillator 4 MHz, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 663 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-15. IDD HS Oscillator 32 MHz, PIC16LF18426/46 only Figure 41-16. IDD HS Oscillator 32 MHz, PIC16F18426/46 only Figure 41-17. IDD HFINTOSC Mode, FOSC= 32 MHz, PIC16LF18426/46 only Figure 41-18. IDD HFINTOSC Mode, FOSC= 32 MHz, PIC16F18426/46 only Figure 41-19. IDD HFINTOSC Mode, FOSC= 16 MHz, PIC16LF18426/46 only Figure 41-20. IDD HFINTOSC Mode, FOSC= 16 MHz, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 664 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-21. IDD HFINTOSC Idle Mode, FOSC= 16 MHz, PIC16LF18426/46 only Figure 41-22. IDD HFINTOSC Idle Mode, FOSC= 16 MHz, PIC16F18426/46 only Figure 41-23. IDD HFINTOSC Doze Mode, FOSC= 16 MHz, PIC16LF18426/46 only Figure 41-24. IDD HFINTOSC Doze Mode, FOSC= 16 MHz, PIC16F18426/46 only Figure 41-25. LFINTOSC Frequency, PIC16LF18426/46 only Figure 41-26. LFINTOSC Frequency, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 665 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-27. HFINTOSC Typical Frequency Error, PIC16LF18426/46 only Figure 41-28. HFINTOSC Typical Frequency Error, PIC16F18426/46 only Figure 41-29. HFINTOSC Frequency Error VDD = 3V, All devices Figure 41-30. Weak Pull-Up Current, PIC16F18426/46 only Figure 41-31. Weak Pull-Up Current, PIC16LF18426/46 only Figure 41-32. VOH vs. IOH Overtemperature, VDD = 5.5V, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 666 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-33. VOL vs. IOL Overtemperature, VDD = 5.5V, PIC16F18426/46 only Figure 41-34. VOH vs. IOH Overtemperature, VDD = 3.0V, All devices Figure 41-35. VOL vs. IOL Overtemperature, VDD = 3.0V, All devices Figure 41-36. VOH vs. IOH Overtemperature, VDD = 1.8V, PIC16LF18426/46 only Figure 41-37. VOL vs. IOL Overtemperature, VDD = 1.8V, PIC16LF18426/46 only Figure 41-38. Brown-Out Reset Voltage, Trip Point BORV = 00, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 667 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-39. Brown-Out Reset Hysteresis, Low Trip Point BORV = 00, All devices Figure 41-40. Brown-Out Reset Voltage, Trip Point BORV = 01, PIC16LF18426/46 only Figure 41-41. Brown-Out Reset Hysteresis, Trip Point BORV = 01, PIC16LF18426/46 only Figure 41-42. Brown-Out Reset Voltage, Trip Point BORV = 01, PIC16F18426/46 only Figure 41-43. Brown-Out Reset Hysteresis, Trip Point BORV = 01, PIC16F18426/46 only Figure 41-44. LPBOR Reset Voltage, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 668 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-45. LPBOR Reset Hysteresis, All devices Figure 41-46. BOR Response Time, PIC16LF18426/46 only Figure 41-47. BOR Response Time, PIC16F18426/46 only Figure 41-48. ADC 12-Bit Mode, Single-Ended Typical DNL, VDD = 3.0V, VREF = 3.0V, TAD = 0.5 uS, 25ºC, All devices Figure 41-49. ADC 12-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 1 uS, 25ºC, All devices Figure 41-50. ADC 12-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 4 uS, 25ºC, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 669 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-51. ADC 12-Bit Mode, Single-Ended Typical INL, VDD = 3.0V, VREF = 3.0V, TAD = 0.5 uS, 25ºC, All devices Figure 41-52. ADC 12-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 1 uS, 25ºC, All devices Figure 41-53. ADC 12-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 4 uS, 25ºC, All devices Figure 41-54. ADC 12-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, All devices Figure 41-55. ADC 12-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, All devices Figure 41-56. ADC 12-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 uS, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 670 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-57. ADC 12-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 uS, All devices Figure 41-58. ADC 12-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, TAD = 1 uS, All devices Figure 41-59. ADC 12-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, TAD = 1 uS, All devices Figure 41-60. ADC 12-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 4 uS, All devices Figure 41-61. ADC 12-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 4 uS, All devices Figure 41-62. ADC 12-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, TAD = 4 uS, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 671 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-63. ADC 12-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, TAD = 4 uS, All devices Figure 41-64. ADC 12-Bit Mode, Single-Ended Gain Error, VDD = 3.0V, VREF = 3.0V, -40ºC to 85ºC, All devices Figure 41-65. ADC 12-Bit Mode, Single-Ended Offset Error, VDD = 3.0V, VREF = 3.0V, -40ºC to 85ºC, All devices Figure 41-66. ADC RC Oscillator Period, PIC16LF18426/46 only Figure 41-67. ADC RC Oscillator Period, PIC16F18426/46 only Figure 41-68. Typical DAC DNL Error, VDD = 3.0V, VREF = External 3V, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 672 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-69. Typical DAC INL Error, VDD = 3.0V, VREF = External 3V, All devices Figure 41-70. Typical DAC DNL Error, VDD = 5.0V, VREF = External 5V, PIC16F18426/46 only Figure 41-71. Typical DAC INL Error, VDD = 5.0V, VREF = External 5V, PIC16F18426/46 only Figure 41-72. DAC DNL Error, VDD = 3.0V, PIC16LF18426/46 only Figure 41-73. Absolute Value of DAC DNL Error, VDD Figure 41-74. Absolute Value of DAC INL Error, VDD = = 3.0V, VREF = VDD, All devices 3.0V, VREF = VDD, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 673 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-75. Absolute Value of DAC DNL Error, VDD Figure 41-76. Absolute Value of DAC INL Error, VDD = = 5.0V, VREF = VDD, PIC16F18426/46 only 5.0V, VREF = VDD, PIC16F18426/46 only Figure 41-77. Comparator Hysteresis, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values, All devices Figure 41-78. Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25°C, All devices Figure 41-79. Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values from -40°C to 125°C, All devices Figure 41-80. Comparator Hysteresis, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 674 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-81. Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values at 25°C, PIC16F18426/46 only Figure 41-82. Comparator Offset, Normal Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values from -40°C to 125°C, PIC16F18426/46 only Figure 41-83. Comparator Response Time Figure 41-84. Comparator Response Time Overvoltage, Normal Power Mode (CxSP = 1), Typical Overvoltage, Normal Power Mode (CxSP = 1), Typical Measured Values, PIC16LF18426/46 only Measured Values, PIC16F18426/46 only Figure 41-85. Comparator Response Time Falling Edge, PIC16LF18426/46 only © 2019 Microchip Technology Inc. Figure 41-86. Comparator Response Time Falling Edge, PIC16F18426/46 only Datasheet DS40001985B-page 675 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-87. Comparator Response Time Rising Edge, PIC16LF18426/46 only Figure 41-88. Comparator Response Time Rising Edge, PIC16F18426/46 only Figure 41-89. Band Gap Ready Time, PIC16LF18426/46 only Figure 41-90. FVR Stabilization Period, PIC16LF18426/46 only Figure 41-91. Typical FVR Voltage 1x, PIC16LF18426/46 only Figure 41-92. FVR Voltage Error 1x, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 676 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-93. FVR Voltage Error 2x, PIC16LF18426/46 only Figure 41-94. FVR Voltage Error 2x, PIC16F18426/46 only Figure 41-95. FVR Voltage Error 4x, PIC16F18426/46 only Figure 41-96. Schmitt Trigger High Values, All devices Figure 41-97. Schmitt Trigger Low Values, All devices Figure 41-98. Input Level TTL, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 677 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-99. Rise Time, Slew Rate Control Enabled, Figure 41-100. Fall Time, Slew Rate Control Enabled, All devices All devices Figure 41-101. Rise Time, Slew Rate Control Disabled, All devices Figure 41-102. Fall Time, Slew Rate Control Disabled, All devices Figure 41-103. OSCTUNE Center Frequency, PIC16LF18426/46 only Figure 41-104. POR Release Voltage, All devices © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 678 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-105. POR REARM Voltage, Normal Power Mode, PIC16F18426/46 only Figure 41-106. PWRT Period, PIC16F18426/46 only Figure 41-107. PWRT Period, PIC16LF18426/46 only Figure 41-108. Wake from Sleep, VREGPM = 0, HFINTOSC = 4 MHz, PIC16F18426/46 only Figure 41-109. Wake from Sleep, VREGPM = 1, HFINTOSC = 4 MHz, PIC16F18426/46 only Figure 41-110. Wake from Sleep, VREGPM = 0, HFINTOSC = 16 MHz, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 679 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-111. Wake from Sleep, VREGPM = 1, HFINTOSC = 16 MHz, PIC16F18426/46 only Figure 41-112. Wake from Sleep, VREGPM = 1, PIC16F18426/46 only Figure 41-113. Wake from Sleep, PIC16LF18426/46 only Figure 41-114. WDT Time-Out Period, PIC16F18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 680 PIC16(L)F18426/46 DC and AC Characteristics Graphs and Tables Figure 41-115. WDT Time-Out Period, PIC16LF18426/46 only © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 681 PIC16(L)F18426/46 Packaging Information 42. Packaging Information Package Marking Information Rev. 30-009000A 5/17/2017 Legend: XX...X Y YY WW NNN Pe3 * Note: Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code b-free JEDEC ® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Rev. 30-009014A 09/21/2017 14-Lead PDIP (300 mil) Example PIC16F18426 /SO e3 1525017 Rev. 30-009014B 09/21/2017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX YYWW NNN 16F18426 1525 e3 017 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 682 PIC16(L)F18426/46 Packaging Information Rev. 30-009014C 09/21/2017 14-Lead SOIC (3.90 mm) Example PIC16F18426 /SO e3 1525017 Rev. 30-009016A 09/21/2017 16-Lead UQFN (4x4x0.5 mm) Example PIN 1 PIN 1 PIC16 F1842 6 /MV 525017 e3 Rev. 30-009020A 09/21/2017 20-Lead PDIP (300 mil) Example PIC16F18446 /P e3 1525017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Rev. 30-009020B 09/21/2017 20-Lead SSOP (5.30 mm) Example PIC16F18446 /SO e3 1525017 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 683 PIC16(L)F18426/46 Packaging Information Rev. 30-009020C 09/21/2017 20-Lead SOIC (7.50 mm) Example PIC16F18446 /SO e3 1525017 Rev. 30-009020D 09/21/2017 20-Lead UQFN (4x4x0.5 mm) Example PIN 1 PIN 1 PIC16 F1844 6 /MV 525017 e3 42.1 Package Details The following sections give the technical details of the packages. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 684 M PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information 14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .045 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-005B © 2007 Microchip Technology Inc. © 2019 Microchip Technology Inc. DS00049AR-page 47 Datasheet DS40001985B-page 685 PIC16(L)F18426/46 Packaging Information 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A NOTE 5 D N E 2 E2 2 E1 E 2X 0.10 C D NOTE 1 1 2 2X N/2 TIPS 0.20 C 3 e NX b B 0.25 NOTE 5 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 14X 0.10 C SIDE VIEW A1 h h R0.13 H R0.13 c SEE VIEW C L VIEW A–A (L1) VIEW C Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 686 PIC16(L)F18426/46 Packaging Information 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Lead Angle Foot Angle c Lead Thickness Lead Width b Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0° 0.10 0.31 5° 5° MILLIMETERS NOM 14 1.27 BSC 6.00 BSC 3.90 BSC 8.65 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimension D does not include mold flash, protrusions or gate burrs, which shall not exceed 0.15 mm per end. Dimension E1 does not include interlead flash or protrusion, which shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 687 PIC16(L)F18426/46 Packaging Information 14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 14 SILK SCREEN C Y 1 2 X E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X14) X Contact Pad Length (X14) Y MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2065-SL Rev D © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 688 M PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS00049BE-page 240 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 689 M PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. © 2019 Microchip Technology Inc. DS00049BC-page 103 Datasheet DS40001985B-page 690 M Note: PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 96 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 691 PIC16(L)F18426/46 Packaging Information 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging A D B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C SEATING PLANE A1 0.10 C C A 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N 16X b 0.10 L e C A B BOTTOM VIEW Microchip Technology Drawing C04-257A Sheet 1 of 2 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 692 PIC16(L)F18426/46 Packaging Information 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.50 2.50 0.25 0.30 0.20 MILLIMETERS NOM 16 0.65 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.60 4.00 BSC 2.60 0.30 0.40 - MAX 0.55 0.05 2.70 2.70 0.35 0.50 - Notes : 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-257A Sheet 2 of 2 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 693 PIC16(L)F18426/46 Packaging Information 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 16 1 C2 Y2 2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch X2 Optional Center Pad Width Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X16) X1 Contact Pad Length (X16) Y1 MIN MILLIMETERS NOM 0.65 BSC MAX 2.70 2.70 4.00 4.00 0.35 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2257A © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 694 M PIC16(L)F18426/46 Packaging Information Packaging Diagrams and Parameters 20-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 20 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .300 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .980 1.030 1.060 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .045 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-019B © 2007 Microchip Technology Inc. DS00049AR-page 52 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 695 M PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 6.90 7.20 7.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 – Foot Angle φ 0° 4° 0.25 8° Lead Width b 0.22 – 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-072B © 2007 Microchip Technology Inc. DS00049AR-page 114 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 696 PIC16(L)F18426/46 Packaging Information 20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.65 0.45 SILK SCREEN c Y1 G X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.65 BSC 7.20 MAX 0.45 1.75 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2072B © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 697 M Note: PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 102 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 698 M PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 104 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 699 M Note: PIC16(L)F18426/46 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 100 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 700 PIC16(L)F18426/46 Packaging Information 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C C SEATING PLANE A1 A 20X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 L 0.10 C A B E2 2 K 1 NOTE 1 N 20X b 0.10 e C A B BOTTOM VIEW Microchip Technology Drawing C04-255A Sheet 1 of 2 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 701 PIC16(L)F18426/46 Packaging Information 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.60 2.60 0.20 0.30 0.20 MILLIMETERS NOM 20 0.50 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.70 4.00 BSC 2.70 0.25 0.40 - MAX 0.55 0.05 2.80 2.80 0.30 0.50 - Notes : 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-255A Sheet 2 of 2 © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 702 PIC16(L)F18426/46 Packaging Information 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 20 1 2 C2 Y2 G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 MIN MILLIMETERS NOM 0.50 BSC MAX 2.80 2.80 4.00 4.00 0.30 0.80 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2255A © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 703 PIC16(L)F18426/46 Revision History 43. Revision History Doc Rev. Date Comments B 11/2019 Adding Electrical Specifications and DC and AC Characteristics Graphs and Tables. Other minor corrections. A 02/2018 Initial release of this document. © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 704 PIC16(L)F18426/46 The Microchip Website Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files and information easily available to customers. Some of the content available includes: • • • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip design partner program member listing Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Product Change Notification Service Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will receive email notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, go to http://www.microchip.com/pcn and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Embedded Solutions Engineer (ESE) Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: http://www.microchip.com/support © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 705 PIC16(L)F18426/46 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) –X /XX Tape Temperature and Reel Range Device: Tape & Reel Option: Temperature Range: Package: Pattern: Package PIC16F18426, PIC16LF18426, PIC16F18446, PIC16LF18446 Blank = Tube T = Tape & Reel I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) JQ = 16-lead UQFN 4x4x0.5mm P = 14-lead, 20-lead PDIP SL = 14-lead SOIC SO = 20-lead SOIC SS = 20-lead SSOP ST = 14-lead TSSOP GZ = 20-lead UQFN 4x4x0.5mm QTP, SQTP, Code or Special Requirements (blank otherwise) Examples: • PIC16F18426- E/P Extended temperature PDIP package Note:  1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2. Small form-factor packaging options may be available. Please check http://www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: • • • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital © 2019 Microchip Technology Inc. Datasheet DS40001985B-page 706 PIC16(L)F18426/46 Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-5234-8 Quality Management System For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality. © 2019 Microchip Technology Inc. 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