PIC16F19195T-I/PT

PIC16(L)F19195/6/7 Full-Featured 64-Pin Microcontrollers Description PIC16(L)F19195/6/7 microcontrollers offer eXtreme Low-Power (XLP) LCD drive coupled with Core Independent Peripherals (CIPs) and Intelligent Analog. They are especially suited for battery-powered LCD applications due to an integrated charge pump, high current I/O drive for backlighting, and battery backup of the Real-Time Clock/Calendar (RTCC). Active clock tuning of the HFINTOSC provides a highly accurate clock source over voltage and temperature. The family also features a new 12-bit ADC controller which can automate Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and automatic threshold comparison. Other new features include low-power Idle and Doze modes, Device Information Area (DIA), and Memory Access Partition (MAP). These low-power products are available in 64 pins to support the customer in various LCD and general purpose applications. Core Features Operating Characteristics • C Compiler Optimized RISC Architecture • Operating Speed: - DC – 32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Timers: - Two 8-bit (TMR2/4) Timer with Hardware Limit Timer Extension (HLT) - 16-bit (TMR0/1) • Low-Current Power-on Reset (POR) • Configurable Power-up Timer (PWRTE) • Brown-out Reset (BOR) with Fast Recovery • Low-Power BOR (LPBOR) Option • Windowed Watchdog Timer (WWDT): - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software • Programmable Code Protection • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF19195/6/7) - 2.3V to 5.5V (PIC16F19195/6/7) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C Memory • • • • • Up to 56KB Flash Program Memory Up to 4KB Data SRAM Memory 256 bytes DataEE Direct, Indirect and Relative Addressing modes Memory Access Partition (MAP): - Bootloader write-protect - Custom partition • Device Information Area (DIA): - Temp sensor factory calibrated data - Fixed Voltage Reference - Device ID  2017-2021 Microchip Technology Inc. Power-Saving Functionality • Doze mode: Ability to run CPU core slower than the system clock • Idle mode: Ability to halt CPU core while internal peripherals continue operating • Sleep mode: Lowest power consumption • Peripheral Module Disable (PMD): Ability to disable hardware module to minimize power consumption of unused peripherals eXtreme Low-Power (XLP) Features • • • • Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 µA @ 32 kHz, 1.8V, typical - 32 µA/MHz @ 1.8V, typical Digital Peripherals • LCD Controller: - Up to 360 segments - Charge pump for low-voltage operation - Contrast control • Four Configurable Logic Cell Modules (CLC): - Integrated combinational and sequential logic DS40001873E-page 1 PIC16(L)F19195/6/7 • Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources • Two Capture/Compare/PWM (CCP) module • Two 10-Bit PWMs • Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O • Communication: - Two EUSART, RS-232, RS-485, LIN compatible - One SPI/I2C, SMBus, PMBus™ compatible • Up to 59 I/O Pins: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select - Input level selection control (ST or TTL) - Digital open-drain enable Flexible Oscillator Structure • High-Precision Internal Oscillator: - Active Clock Tuning of HFINTOSC over voltage and temperature (ACT) - Selectable frequency range up to 32 MHz ±1% typical • x2/x4 PLL with Internal and External Sources • Low-Power Internal 31 kHz Oscillator (LFINTOSC) • External 32 kHz Crystal Oscillator (SOSC) - Oscillator Start-up Timer (OST) - Ensures stability of crystal oscillator source • External Oscillator Block with: - Three external clock modes up to 32 MHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripherals clock stops Analog Peripherals • Analog-to-Digital Converter with Computation (ADC2): - 12-bit with up to 45 external channels - Automates math functions on input signals: averaging, filter calculations, oversampling and threshold comparison - Conversion available during Sleep • Two Comparators: - (1) Low-Power Clocked Comparator - (1) High-Speed Comparator - Fixed Voltage Reference at (non)inverting input(s) - Comparator outputs externally accessible • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive Reference Selection - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels • Zero-Cross Detect Module: - AC high-voltage zero-crossing detection for simplifying TRIAC control - Synchronized switching control and timing  2017-2021 Microchip Technology Inc. DS40001873E-page 2 Device Program Flash Memory (kW/KB) DataEE (bytes) Data SRAM (bytes) I/O Pins 12-bit ADC (ch) 5-bit DAC Comparator 8-bit/ (with HLT) Timer 16-bit Timer Window Watchdog Timer (WWDT) CCP/10-bit PWM CWG CLC Zero-Cross Detect Temperature Sensor Memory Access Partition Device Information Area EUSART/ I2C/SPI Peripheral Pin Select Peripheral Module Disable Debug(1) LCD Segments (Max) LCD Charge Pump/ Bias Generator PIC16(L)F19195/6/7 FAMILY TYPES Data Sheet Index  2017-2021 Microchip Technology Inc. TABLE 1: PIC16(L)F19155 (A) 8/14 256 1024 24 20 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 96 Y/Y PIC16(L)F19156 (A) 16/28 256 2048 24 20 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 96 Y/Y PIC16(L)F19175 (A) 8/14 256 1024 35 31 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 184 Y/Y PIC16(L)F19176 (A) 16/28 256 2048 35 31 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 184 Y/Y PIC16(L)F19185 (A) 8/14 256 1024 43 39 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 248 Y/Y PIC16(L)F19186 (A) 16/28 256 2048 43 39 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 248 Y/Y PIC16(L)F19195 (B) 8/14 256 1024 59 45 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 360 Y/Y PIC16(L)F19196 (B) 16/28 256 2048 59 45 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 360 Y/Y PIC16(L)F19197 (B) 32/56 256 4096 59 45 1 2 2 2 Y 2/2 1 4 Y Y Y Y 2/1 Y Y I 360 Y/Y Note 1: I – Debugging integrated on chip. Data Sheet Index (Unshaded devices are described in this document): A. B. PIC16(L)F19155/56/75/76/85/86 Data Sheet, 28/40/44/48-Pin PIC16(L)F19195/6/7 Data Sheet, Full-Featured 64-Pin Microcontrollers For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. DS40001873E-page 3 PIC16(L)F19195/6/7 Note: DS40001923 DS40001873 PIC16(L)F19195/6/7 TABLE 2: PACKAGES Device 64-Pin TQFP (10x10) 64-Pin QFN (9x9) 64-Pin QFN/ VQFN (9x9)          PIC16(L)F19195 PIC16(L)F19196 PIC16(L)F19197 Pin details are subject to change. RD6/SEG6 RD7/SEG7 RD5/SEG5 RD4/SEG4 RD3/SEG3 RD2/SEG2 RD1/SEG1 RH3/SEG40/CFLY2 RH2/SEG32/CFLY1 RD0/SEG0 RE6/COM3 RE7/SEG31 RE5/COM2 RE4/COM1 64-PIN TQFP (10X10X1)/QFN (9X9X0.9)/VQFN (9X9X1.0) PIN DIAGRAM FOR PIC16(L)F19195/6/7 VLCD3 FIGURE 1: RE3/COM0 Note: 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/VLCD2 RE0/VLCD1 RG0/SEG42 RG1/SEG43 RG2/SEG44 RG3/SEG45 VPP/MCLR/RG5 RG4/SEG26 VSS VDD RF7/SEG25 RF6/SEG24 RF5/SEG23 RF4/SEG22 RF3/SEG21 RF2/SEG20 1 2 3 48 47 46 45 4 5 6 7 8 9 10 11 12 13 14 44 43 42 PIC16(L)F19195/96/97 41 40 39 38 37 36 35 15 16 34 33 RB0/SEG30 RB1/SEG8 RB2/SEG9 RB3/SEG10 RB4/SEG11 RB5/SEG29 RB6/SEG38/ICSPCLK VSS RA6/SEG36 RA7/SEG37 VDD RB7/SEG39/ICSPDAT RC5/SEG12 RC4/SEG16 RC3/SEG17 RC2/SEG13 RC7/SEG28 RC6/SEG27 RC0/SOSCO VBAT/RA5 RA4/SEG14 RC1/SOSCI RH0/COM4 RH1/COM5 RA0/SEG33 RA1/SEG18 RA2/SEG34 RG6/COM6 RA3/SEG35 RG7/SEG15/COM7 RF0/SEG41 RF1/SEG19 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note 1: QFN/VQFN package orientation is the same. No leads are present on the QFN/VQFN package. 2: See Table 3 for location of all peripheral functions. 3: For QFN/VQFN packages, it is recommended that the exposed bottom pad be connected to VSS. However, it must not be the only VSS connection to the device.  2017-2021 Microchip Technology Inc. DS40001873E-page 4 CWG MSSP EUSART CLC ― ― ― ― ― ― ― CLCIN0(1) RA1 23 ANA1 ― ― ― ― T2IN(1) ― ― ― ― ― CLCIN1(1) RA2 22 ANA2 ― C1IN1+ C2IN1+ ― ― ― ― ― ― ― ― ― RA3 21 ANA3 VREF+ ― ― DAC1REF+ ― ― ― ― ― ― RA4 28 ANA4 ― ― ― ― T0CKI(1) ― ― ― ― ― RA5 27 ― ― ― ― ― ― ― ― ― ― 40 ANA6 ― ― ― ― ― ― ― ― ― RA7 39 ANA7 ― ― ― ― ― ― ― ― ― RB0 48 ANB0 ― ― ZCD ― ― ― ― ― ― RB1 47 ANB1 ― ― ― ― ― ― ― ― SCL, SDA(1,3,4,5,6) RB2 46 ANB2 ― ― ― ― ― ― ― ― SCL, SDA(1,3,4,5,6) RB3 45 ANB3 ― ― ― ― ― ― ― ― RB4 44 ANB4 ― ― ― ― ― ― ― ― RB5 43 ANB5 ― ― ― ― T1G(1) ― ― RB6 42 ANB6 ― ― ― ― ― ― RB7 37 ANB7 ― ― ― DAC1OUT2 ― ― Note 1: 2: 3: 4: 5: 6: ― ― ― Y ― ― ― Y ― ― ― Y ― SEG35 ― ― Y ― SEG14 ― ― Y ― ― ― ― ― Y VBAT ― SEG33 ― SEG18 ― SEG34 ― ― ― ― ― ― ― SEG36 ― ― Y CLKOUT ― ― SEG37 ― ― Y CLKIN ― ― SEG30 INT(1) ― Y ― ― ― SEG8 IOCB1 ― Y ― ― ― ― SEG9 IOCB2 ― Y ― ― ― ― ― SEG10 IOCB3 ― Y ― ― ― ― ― SEG11 IOCB4 ― Y ― ― ― ― ― ― SEG29 IOCB5 ― Y ― ― ― ― ― CLCIN2(1) ― SEG38 IOCB6 ― Y ICDCLK/ ICSPCLK ― ― ― ― CLCIN3(1) ― SEG39 IOCB7 ― Y ICDDAT/ ICSPDAT ― This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. These are alternative I2C logic levels pins. In I2C logic levels configuration, these pins can operate as either SCL or SDA pins. PIC16(L)F19195/6/7 DS40001873E-page 5 RA6 Basic PWM ― Pull-up CCP C1IN4C2IN4- High Current Timers/SMT ― Interrupt-on-Change DAC ANA0 LCD Zero-Cross Detect 24 RTCC Reference RA0 Comparator ADC 64-PIN ALLOCATION TABLE (PIC16(L)F19195/6/7) 64-Pin TQFP/QFN/VQFN TABLE 3: I/O(2)  2017-2021 Microchip Technology Inc. PIN ALLOCATION TABLES 64-Pin TQFP/QFN/VQFN ADC Reference Comparator Zero-Cross Detect DAC Timers/SMT CCP PWM CWG MSSP EUSART CLC RTCC LCD Interrupt-on-Change High Current Pull-up Basic I/O(2) RC0 64-PIN ALLOCATION TABLE (PIC16(L)F19195/6/7) (CONTINUED) 30 ― ― ― ― ― T1CKI(1) ― ― ― ― ― ― ― ― IOCC0 ― Y SOSCO RC1 29 ― ― ― ― ― ― ― ― ― ― ― ― ― ― IOCC1 ― Y RC2 33 ― ― ― ― ― ― ― ― CWG1IN(1) ― ― ― ― SEG13 IOCC2 ― Y SOSCI ― RC3 34 ― ― ― ― ― ― ― ― ― SCK(1) SCL(1,3,4) ― ― ― SEG17 IOCC3 ― Y ― RC4 35 ― ― ― ― ― ― ― ― ― SDI(1) SDA(1,3,4) ― ― ― SEG16 IOCC4 ― Y ― RC5 36 ― ― ― ― ― ― ― ― ― ― ― ― ― SEG12 IOCC5 ― Y ― RC6 31 ― ― ― ― ― ― ― ― ― ― TX1(1) CK1(1) ― ― SEG27 IOCC6 ― Y ― RC7 32 ― ― ― ― ― ― ― ― ― ― RX1(1) DT1 (1) ― ― SEG28 IOCC7 ― Y ― RD0 58 AND0 ― ― ― ― ― ― ― ― ― ― ― ― SEG0 ― ― Y ― RD1 55 AND1 ― ― ― ― ― ― ― ― ― ― ― ― SEG1 ― ― Y ― RD2 54 AND2 ― ― ― ― ― ― ― ― ― ― ― ― SEG2 ― ― Y ― RD3 53 AND3 ― ― ― ― ― ― ― ― ― ― ― ― SEG3 ― ― Y ―  2017-2021 Microchip Technology Inc. RD4 52 AND4 ― ― ― ― ― ― ― ― ― ― ― ― SEG4 ― ― Y ― RD5 51 AND5 ― ― ― ― ― ― ― ― ― ― ― ― SEG5 ― ― Y ― RD6 50 AND6 ― ― ― ― ― ― ― ― ― ― ― ― SEG6 ― ― Y ― RD7 49 AND7 ― ― ― ― ― ― ― ― ― ― ― ― SEG7 ― ― Y ― RE0 2 ANE0 ― ― ― ― ― ― ― ― ― ― ― ― VLCD1 ― ― Y ― RE1 1 ANE1 ― ― ― ― ― ― ― ― ― ― ― ― VLCD2 ― ― Y ― ANE3 ― ― ― ― ― ― ― ― ― ― ― ― COM0 IOCE3 ― Y ― RE3 Note 63 1: 2: 3: 4: 5: 6: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. These are alternative I2C logic levels pins. In I2C logic levels configuration, these pins can operate as either SCL or SDA pins. PIC16(L)F19195/6/7 DS40001873E-page 6 TABLE 3: 64-Pin TQFP/QFN/VQFN ADC Reference Comparator Zero-Cross Detect DAC Timers/SMT CCP PWM CWG MSSP EUSART CLC RTCC LCD Interrupt-on-Change High Current Pull-up Basic 64-PIN ALLOCATION TABLE (PIC16(L)F19195/6/7) (CONTINUED) RE4 62 ANE4 ― ― ― ― T4IN(1) CCP2(1) ― ― ― ― ― ― COM1 IOCE4 ― Y ― RE5 61 ANE5 ― ― ― ― ― CCP1(1) ― ― ― ― ― ― COM2 IOCE5 ― Y ― RE6 60 ANE6 ― ― ― ― SMTWIN1(1) ― ― ― ― ― ― ― COM3 IOCE6 ― Y ― RE7 59 ANE7 ― ― ― ― SMTSIG1(1) ― ― ― ― ― ― ― SEG31 IOCE7 ― Y ― RF0 18 ANF0 ― C1IN0C2IN0- ― ― ― ― ― ― ― ― ― ― SEG41 ― ― Y ― I/O(2)  2017-2021 Microchip Technology Inc. TABLE 3: 17 ANF1 ― ― ― ― ― ― ― ― ― ― ― ― SEG19 ― ― Y ― 16 ANF2 ― ― ― ― ― ― ― ― ― ― ― ― SEG20 ― ― Y ― RF3 15 ANF3 ― C1IN2C2IN2- ― ― ― ― ― ― ― ― ― ― SEG21 ― ― Y ― RF4 14 ANF4 ― C2IN0+ ― ― ― ― ― ― ― ― ― ― SEG22 ― ― Y ― RF5 13 ANF5 ― C1IN1C2IN1- ― DAC1OUT1 ― ― ― ― ― ― ― ― SEG23 ― ― Y ― RF6 12 ANF6 ― C1IN0+ ― ― ― ― ― ― ― ― ― ― SEG24 ― ― Y ― RF7 11 ANF7 ― C1IN3C2IN3- ― ― ― ― ― ― SS(1) ― ― ― SEG25 ― HIDF7 Y ― RG0 3 ANG0 ― ― ― ― ― ― ― ― ― ― ― ― SEG42 ― ― Y ― RG1 4 ANG1 ― ― ― ― ― ― ― ― ― TX2(1) CK2(1) ― ― SEG43 ― ― Y ― RG2 5 ANG2 ― ― ― ― ― ― ― ― ― RX2(1) DT2(1) ― ― SEG44 ― ― Y ― RG3 6 ANG3 ― ― ― ― ― ― ― ― ― ― ― ― SEG45 ― ― Y ― RG4 8 ANG4 ― ― ― ― ― ― ― ― ― ― ― ― SEG26 ― ― Y ― DS40001873E-page 7 Note 1: 2: 3: 4: 5: 6: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. These are alternative I2C logic levels pins. In I2C logic levels configuration, these pins can operate as either SCL or SDA pins. PIC16(L)F19195/6/7 RF1 RF2 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― COM6 ― SEG15 COM7 Basic CLC ― Pull-up EUSART ― High Current MSSP ― Interrupt-on-Change CWG ― LCD PWM ― RTCC CCP ANG7 Timers/SMT ANG6 19 DAC 20 RG7 Zero-Cross Detect RG6 Comparator ― RG5 Reference ADC 7 I/O(2) 64-Pin TQFP/QFN/VQFN 64-PIN ALLOCATION TABLE (PIC16(L)F19195/6/7) (CONTINUED) IOG5 ― Y MCLR VPP ― ― Y ― ― ― Y ― ―  2017-2021 Microchip Technology Inc. RH0 26 ― ― ― ― ― ― ― ― ― ― ― ― ― COM4 ― ― Y RH1 25 ADCACT(1) ― ― ― ― ― ― ― ― ― ― ― ― COM5 ― ― Y ― RH2 57 ― ― ― ― ― ― ― ― ― ― ― ― ― SEG32 CFLY1 ― ― Y ― RH3 56 ― ― ― ― ― ― ― ― ― ― ― ― ― SEG40 CFLY2 ― ― Y ― VLCD3 64 ― ― ― ― ― ― ― ― ― ― ― ― ― VLCD3 ― ― ― ― VDD 10 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD VDD 38 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VDD VSS 9 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS VSS 41 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VSS OUT(2) ― ADGRDA ADGRDB ― C1OUT C2OUT ― ― TMR0 CCP1 CCP2 PWM3 PWM4 CWG1A CWG1B CWG1C CWG1D SDO SCK SCL SDA TX1 DT1 CK1 TX2 DT2 CK2 CLC1OUT RTCC ― ― ― ― ― Note 1: 2: 3: 4: 5: 6: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. These are alternative I2C logic levels pins. In I2C logic levels configuration, these pins can operate as either SCL or SDA pins. PIC16(L)F19195/6/7 DS40001873E-page 8 TABLE 3: PIC16(L)F19195/6/7 Table of Contents Pin Allocation Tables ............................................................................................................................................................................. 5 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started With PIC16(L)F19195/6/7 Microcontrollers................................................................................ 22 3.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 25 4.0 Memory Organization ................................................................................................................................................................. 27 5.0 Device Configuration ................................................................................................................................................................ 102 6.0 RESETS and Vbat.................................................................................................................................................................... 112 7.0 Device Information Area........................................................................................................................................................... 123 8.0 Device Configuration Information ............................................................................................................................................. 125 9.0 Oscillator Module (with Fail-Safe Clock Monitor) ..................................................................................................................... 126 10.0 Interrupts .................................................................................................................................................................................. 143 11.0 Power-Saving Operation Modes .............................................................................................................................................. 167 12.0 Windowed Watchdog Timer (WWDT) ...................................................................................................................................... 175 13.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 183 14.0 I/O Ports ................................................................................................................................................................................... 202 15.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 254 16.0 Peripheral Module Disable (PMD)............................................................................................................................................ 263 17.0 Interrupt-On-Change (IOC) ...................................................................................................................................................... 270 18.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 278 19.0 Analog-to-Digital Converter with Computation (ADC2) Module ............................................................................................... 282 20.0 Temperature Indicator Module (TIM)........................................................................................................................................ 322 21.0 5-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 325 22.0 Comparator Module.................................................................................................................................................................. 330 23.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 340 24.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 346 25.0 Timer0 Module ......................................................................................................................................................................... 361 26.0 Timer1 Module with Gate Control............................................................................................................................................. 367 27.0 Timer2/4 Module With Hardware Limit Timer (HLT)................................................................................................................. 380 28.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 404 29.0 Capture/Compare/PWM Modules ............................................................................................................................................ 447 30.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 459 31.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 466 32.0 Configurable Logic Cell (CLC).................................................................................................................................................. 490 33.0 Host Synchronous Serial Port (MSSP) Modules ...................................................................................................................... 507 34.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1/2) .......................................................... 558 35.0 Liquid Crystal Display (LCD) Controller.................................................................................................................................... 586 36.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 620 37.0 Instruction Set Summary .......................................................................................................................................................... 622 38.0 Register Summary.................................................................................................................................................................... 635 39.0 Electrical Specifications............................................................................................................................................................ 659 40.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 689 41.0 Development Support............................................................................................................................................................... 709 42.0 Packaging Information.............................................................................................................................................................. 711 Appendix A: Data Sheet Revision History.......................................................................................................................................... 725 The Microchip WebSite ...................................................................................................................................................................... 726 Customer Change Notification Service .............................................................................................................................................. 726 Customer Support .............................................................................................................................................................................. 726 Product Identification System ............................................................................................................................................................ 727  2017-2021 Microchip Technology Inc. DS40001873E-page 9 PIC16(L)F19195/6/7 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products.  2017-2021 Microchip Technology Inc. DS40001873E-page 10 PIC16(L)F19195/6/7 DEVICE OVERVIEW The PIC16(L)F19195/6/7 are described within this data sheet. The PIC16(L)F19195/6/7 devices are available in 64-pin TQFP, QFN and VQFN packages. Figure 1-1 shows a block diagram of the PIC16(L)F19195/6/7 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral PIC16(L)F19195/6/7 1.0 Analog-to-Digital Converter with Computation (ADC2) ● Digital-to-Analog Converter (DAC1) ● Fixed Voltage Reference (FVR) ● Enhanced Universal Synchronous/Asynchronous Receiver/ Transmitter (EUSART1 and EUSART2) ● Temperature Indicator Module (TIM) ● Zero-Cross Detect (ZCD1) ● Real-Time Calendar and Clock (RTCC) ● Liquid Crystal Display (LCD) ● Capture/Compare/PWM Modules (CCP) CCP1 ● CCP2 ● C1 ● C2 ● CLC1 ● CLC2 ● CLC3 ● CLC4 ● CWG1 ● MSSP1 ● PWM3 ● PWM4 ● SMT1 ● Timer0 ● Timer1 ● Timer2 ● Timer4 ● Comparator Module (Cx) Configurable Logic Cell (CLC) Complementary Waveform Generator (CWG) Host Synchronous Serial Ports (MSSP) Pulse-Width Modulator (PWM) Signal Measure Timer (SMT) Timers  2017-2021 Microchip Technology Inc. DS40001873E-page 11 PIC16(L)F19195/6/7 1.1 1.1.1 Register and Bit Naming Conventions REGISTER NAMES When there are multiple instances of the same peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.1.2 BIT NAMES There are two variants for bit names: • Short name: Bit function abbreviation • Long name: Peripheral abbreviation + short name 1.1.2.1 Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction COG1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.1.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction.  2017-2021 Microchip Technology Inc. 1.1.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1UTH 101 = Interrupt if ERRUTH 100 = Interrupt if ERRLTH or ERR>UTH 011 = Interrupt if ERR>LTH and ERR CxVN If CxPOL = 0 (noninverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 Unimplemented: Read as ‘0’ bit 4 POL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3-2 Unimplemented: Read as ‘0’ bit 1 HYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 SYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous  2017-2021 Microchip Technology Inc. DS40001873E-page 336 PIC16(L)F19195/6/7 REGISTER 22-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — INTP INTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 INTP: Comparator Interrupt on Positive-Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive-going edge of the CxOUT bit bit 0 INTN: Comparator Interrupt on Negative-Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative-going edge of the CxOUT bit  2017-2021 Microchip Technology Inc. DS40001873E-page 337 PIC16(L)F19195/6/7 REGISTER 22-3: CMxNSEL: COMPARATOR Cx NEGATIVE INPUT SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/0 R/W-0/0 R/W-0/0 NCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 2-0 NCH: Comparator Negative Input Channel Select bits 111 = CxVN connects to AVSS 110 = CxVN connects to FVR Buffer 2 101 = CxVN unconnected 100 = CxVN connects to CxIN4- pin 011 = CxVN connects to CxIN3- pin 010 = CxVN connects to CxIN2- pin 001 = CxVN connects to CxIN1- pin 000 = CxVN connects to CxIN0- pin REGISTER 22-4: CMxPSEL: COMPARATOR Cx POSITIVE INPUT SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/0 R/W-0/0 R/W-0/0 PCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 5-3 PCH: Comparator Positive Input Channel Select bits 111 = CxVP connects to AVSS 110 = CxVP connects to FVR Buffer 2 101 = CxVP connects to DAC output 100 = CxVP LCD VREF(1) 011 = CxVP unconnected 010 = CxVP unconnected 001 = CxVP connects to CxIN1+ pin 000 = CxVP connects to CxIN0+ pin Note 1: Applies to C2 comparator only.  2017-2021 Microchip Technology Inc. DS40001873E-page 338 PIC16(L)F19195/6/7 REGISTER 22-5: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 — — — — — — MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CMxCON0 ON OUT — POL — — HYS SYNC 336 CMxCON1 — — — — — — INTP INTN 337 CMOUT — — — — — — MC2OUT MC1OUT 339 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR DAC1CON0 DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS DAC1CON1 — — — Name INTCON ADFVR — — DAC1R 280 328 328 GIE PEIE — INTEDG 147 PIE2 — ZCDIE — — — — C2IE C1IE 150 PIR2 — ZCDIF — — — — C2IF C1IF 159 CLCINxPPS — — — CLCIN0PPS 259 T1GPPS ― ― ― T1GPPS 259 Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.  2017-2021 Microchip Technology Inc. DS40001873E-page 339 PIC16(L)F19195/6/7 23.0 ZERO-CROSS DETECTION (ZCD) MODULE The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero-crossing threshold is the zero-crossing reference voltage, VCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD module is shown in the simplified block diagram Figure 23-2. The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: • • • • A/C period measurement Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching  2017-2021 Microchip Technology Inc. 23.1 External Resistor Selection The ZCD module requires a current limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 A. Refer to Equation 23-1 and Figure 23-1. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. EQUATION 23-1: EXTERNAL RESISTOR V PEAK R SERIES = -----------------–4 3 10 FIGURE 23-1: VPEAK EXTERNAL VOLTAGE VMAXPEAK VMINPEAK VCPINV DS40001873E-page 340 PIC16(L)F19195/6/7 FIGURE 23-2: SIMPLIFIED ZCD BLOCK DIAGRAM VPULLUP Rev. 10-000194D 11/27/2018 optional VDD - Zcpinv RPULLUP ZCDxIN RSERIES RPULLDOWN + External voltage source optional ZCD Output for other modules POL Interrupt det ZCDxINTP ZCDxINTN Set ZCDxIF flag Interrupt det  2017-2021 Microchip Technology Inc. DS40001873E-page 341 PIC16(L)F19195/6/7 23.2 ZCD Logic Output 23.5 Correcting for VCPINV offset The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The OUT bit of the ZCDxCON register is set when the current sink is active, and cleared when the current source is active. The OUT bit is affected by the polarity even if the module is disabled. The actual voltage at which the ZCD switches is the reference voltage at the noninverting input of the ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. 23.3 23.5.1 ZCD Logic Polarity The POL bit of the ZCDxCON register inverts the ZCDxOUT bit relative to the current source and sink output. When the POL bit is set, a OUT high indicates that the current source is active, and a low output indicates that the current sink is active. The POL bit affects the ZCD interrupts. See Section 23.4 “ZCD Interrupts”. 23.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIR2 register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. Both are located in the ZCDxCON register. CORRECTION BY AC COUPLING When the external voltage source is sinusoidal then the effects of the VCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a capacitor in addition to the voltage reducing resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual zero-crossing event. The phase shift will be the same for both rising and falling zero crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift is negligible. To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to obtain a peak current of 300 uA. Next, arbitrarily select a suitably large non-polar capacitor and compute its reactance, Xc, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage, and phase shift by the formulas shown in Equation 23-2. To fully enable the interrupt, the following bits must be set: • ZCDIE bit of the PIE2 register • INTP bit of the ZCDxCON register (for a rising edge detection) • INTN bit of the ZCDxCON register (for a falling edge detection) • PEIE and GIE bits of the INTCON register Changing the POL bit can cause an interrupt, regardless of the level of the EN bit. The ZCDIF bit of the PIR2 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.  2017-2021 Microchip Technology Inc. DS40001873E-page 342 PIC16(L)F19195/6/7 EQUATION 23-2: R-C CALCULATIONS Vpeak = external voltage source peak voltage f = external voltage source frequency EXAMPLE 23-1: V peak = V rms  2 = 169.7 C = series capacitor R = series resistor f = 60 Hz VC = Peak capacitor voltage C = 0.1 f  = Capacitor induced zero crossing phase advance in radians T = Time ZC event occurs before actual zero crossing V peak 169.7 - = ------------------Z = ------------------= 565.7 kOhms –4 –4 3  10 3  10 1 1 - = 26.53 kOhms X C = ----------------- = ------------------------------------------- 2fC   2  60  1  10 – 7  V PEAK Z = ---------------–4 3x10 R 1 X C = ---------------- 2fC  R = R-C CALCULATIONS EXAMPLE 2 Z – XC –4 V C = X C  3x10  –1 X C  = Tan  ------ R  T  = ----------- 2f  Vrms = 120  2017-2021 Microchip Technology Inc. = 560 kOhms ZR = 2  R + X c 2  = 560.6 kOhm  using actual resistor  V peak –6 I peak = ------------= 302.7  10 ZR V C = X C  I peak = 8.0 V –1 X C  = Tan  ------ = 0.047 radians  R  T  = ------------- = 125.6 s  2f  DS40001873E-page 343 PIC16(L)F19195/6/7 23.5.2 CORRECTION BY OFFSET CURRENT When the waveform is varying relative to VSS, then the zero-cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zerocross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown in Equation 23-3. EQUATION 23-3: ZCD EVENT OFFSET When External Voltage Source is relative to Vss: T OFFSET Vcpinv asin  ------------------ V PEAK = ---------------------------------2  Freq 23.6 If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of ± 600 A and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed ± 600 A and the minimum is at least ± 100 A, compute the series resistance as shown in Equation 23-5. The compensating pull-up for this series resistance can be determined with Equation 23-4 because the pull-up value is not dependent from the peak voltage. EQUATION 23-5: T OFFSET This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the VCPINV switching voltage. The pull-up or pull-down value can be determined with the equation shown in Equation 23-4. EQUATION 23-4: SERIES R FOR V RANGE V MAXPEAK + V MINPEAK R SERIES = --------------------------------------------------------–4 7 10 When External Voltage Source is relative to VDD: V DD – Vcpinv asin  --------------------------------  V PEAK  = ------------------------------------------------2  Freq Handling VPEAK variations 23.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 23.8 Effects of a Reset The ZCD circuit can be configured to default to the active or inactive state on Power-on-Reset (POR). When the ZCDDIS Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the EN bit of the ZCDxCON register must be set to enable the ZCD module. ZCD PULL-UP/DOWN When External Signal is relative to Vss: R SERIES  V PULLUP – V cpinv  R PULLUP = -----------------------------------------------------------------------V cpinv When External Signal is relative to VDD: ꞏ SERIES   Vcpinv  R PULLDOWN = R ------------------------------------------------ V DD – Vcpinv   2017-2021 Microchip Technology Inc. DS40001873E-page 344 PIC16(L)F19195/6/7 23.9 Register Definitions: ZCD Control REGISTER 23-1: ZCDCON: ZERO-CROSS DETECTION CONTROL REGISTER R/W-q/q U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 SEN — OUT POL — — INTP INTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on Configuration bits bit 7 SEN: Zero-Cross Detection Enable bit 1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. bit 6 Unimplemented: Read as ‘0’ bit 5 OUT: Zero-Cross Detection Logic Level bit POL bit = 1: 1 = ZCD pin is sourcing current 0 = ZCD pin is sinking current POL bit = 0: 1 = ZCD pin is sinking current 0 = ZCD pin is sourcing current bit 4 POL: Zero-Cross Detection Logic Output Polarity bit 1 = ZCD logic output is inverted 0 = ZCD logic output is not inverted bit 3-2 Unimplemented: Read as ‘0’ bit 1 INTP: Zero-Cross Positive Edge Interrupt Enable bit 1 = ZCDIF bit is set on low-to-high ZCDx_output transition 0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition bit 0 INTN: Zero-Cross Negative Edge Interrupt Enable bit 1 = ZCDIF bit is set on high-to-low ZCDx_output transition 0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page PIE3 RC2IE TX2IE RC1IE TX1IE — — BCL1IE SSP1IE 151 PIR3 RC2IF TX2IF RC1IF TX1IF — — BCL1IF SSP1IF 160 SEN — OUT POL — — INTP INTN 345 Name ZCDxCON Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module. TABLE 23-2: Name CONFIG2 Legend: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register on Page 13:8 — — DEBUG STVREN PPS1WAY ZCDDIS BORV — 103 7:0 BOREN LPBOREN — — — PWRTE MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.  2017-2021 Microchip Technology Inc. DS40001873E-page 345 PIC16(L)F19195/6/7 24.0 REAL-TIME CLOCK AND CALENDAR (RTCC) • Multiple Clock Sources • Low-Power Optimization Figure 24-1 is a simplified block diagram of the RTCC module. The PIC16(L)F19195/6/7 family of devices is equipped with a Real-Time Clock and Calendar (RTCC) module, designed to maintain accurate time measurement for extended periods, with little or no intervention from the CPU. The module is optimized for low-power operation in order to provide extended battery life. The key features include: • • • • • • • • • Time: Hours, Minutes and Seconds 24-hour Format Calendar: Weekday, Date, Month and Year Year Range: 2000 to 2099 Leap Year Correction Configurable Alarm BCD Format for Compact Firmware Half-second Synchronization and Visibility User Calibration with Auto-Adjust FIGURE 24-1: RTCC BLOCK DIAGRAM Rev. 10-000313A 10/18/2016 RTCC Clock Domain CPU Clock Domain RTCCON Clock Source YEAR RTCC Prescalers ALRMCON MONTH 500ms WEEKDAY Timer Registers DAY RTCC Timer RTCCAL HOURS Alarm Event MINUTES Comparator SECONDS ALRMMNTH ALRMWD ALRMDAY Compare Register with Masks Alarm Registers ALRMHR ALRMMIN ALRMSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic SECONDS RTCC Pin RxyPPS  2017-2021 Microchip Technology Inc. DS40001873E-page 346 PIC16(L)F19195/6/7 24.1 OPERATION The RTCC consists of a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1st, 2000 to 23:59:59 on December 31st, 2099. The hours use the 24-hour time format with no hardware provisions for regular time format (AM/PM). The clock provides a granularity of one second with additional visibility to the half-second. The user has visibility to the half second field of the counter. This value is read-only and can be reset only by writing to the lower half of the SECONDS register. 24.1.1 REGISTER INTERFACE The RTCC register set is divided into the following categories: Control Registers • • • • RTCCON RTCCAL ALRMCON ALRMRPT Clock Value Registers • • • • • • • YEAR MONTH DAY WEEKDAY HOURS MINUTES SECONDS Alarm Value Registers • • • • • • ALRMMNTH ALRMDAY ALRMWD ALRMHR ALRMMIN ALRMSEC Note: The WEEKDAY register is not automatically derived from the date, but it must be correctly set by the user. The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format. This simplifies the firmware when using the module, as each of the digits is contained within its own 4-bit value (see Figure 24-2 and Figure 24-3).  2017-2021 Microchip Technology Inc. All timer registers containing a value of seconds or greater are writable. The user can configure the initial start date and time by writing the year, month, day, hour, minutes and seconds into the clock value registers and the timer will then proceed to count from the newly written values. The RTCC module is enabled by setting the RTCEN bit (RTCCON). Once the RTCC is enabled, the timer will continue incrementing, even while the clock value registers are being re-written. However, any time the SECONDS register is written to, all of the clock value prescalers are reset to ‘0’. This allows lower granularity of timer adjustments. The Timer registers are updated in the same cycle as the write instruction’s execution by the CPU. The user must ensure that when RTCEN = 1, the updated registers will not be incremented at the same time. This can be accomplished in several ways: • By checking the RTCSYNC bit (RTCCON) • By checking the preceding digits from which a carry can occur • By updating the registers immediately following the seconds pulse (or alarm interrupt) 24.1.2 WRITE LOCK To perform a write to any of the RTCC timer registers, the RTCWREN bit must be set. To avoid accidental writes to the timer, it is recommended that the RTCWREN bit is kept clear at any other time. The RTCEN bit can only be written to when RTCWREN = 1. A write attempt to this bit while RTCWREN = 0 will be ignored. The RTCC timer registers can be written with RTCEN = 0 or 1. The RTCEN bit of the RTCCON register is synchronized to the SOSC and will not be set until the external oscillator is available. The first time that the RTCEN bit is set, there could be a delay between when the bit is set in software and when the bit is set in the RTCCON register, if an external crystal is used as the clock source. This potential delay is based upon the start-up time of the crystal, as the RTCEN bit of the RTCCON register will not set until the external oscillator is stable and ready. The start-up time of the specific external crystal must be considered when initializing the RTCC module to ensure that the RTCC module is enabled before the RTCWREN bit is cleared. It is recommended that the RTCEN bit be polled after setting it to ensure that it is truly set before clearing the RTCWREN bit. DS40001873E-page 347 PIC16(L)F19195/6/7 FIGURE 24-2: BINARY CODED DECIMAL (BCD) TIMER DIGIT FORMAT Year 0-9 0-9 0-1 Hours (24-hour format) 0-2 FIGURE 24-3: Day Month 0-9 0-9 0-3 Minutes 0-5 0-9 0-9 0-5 0-6 1/2 Second Bit (binary format) Seconds 0-9 0/1 BINARY CODED DECIMAL (BCD) ALARM DIGIT FORMAT Day Month 0-1 Hours (24-hour format) 0-2 Day of Week 0-9  2017-2021 Microchip Technology Inc. 0-9 0-3 Minutes 0-5 Day of Week 0-9 0-6 Seconds 0-9 0-5 0-9 DS40001873E-page 348 PIC16(L)F19195/6/7 24.1.3 CLOCK SOURCES The RTCC module can be clocked by either an external Real-Time Clock crystal oscillating at 32.768 kHz, MFINTOSC/16 (31.25 kHz) or via the ZCD at 50 Hz or 60 Hz. Each clock selection has a fixed prescaler in order to generate the required half-second clock needed by the RTCC. They are as follows: • • • • SOSC (32.768 kHz) = 1:16384 MFINTOSC/16 (31.25 kHz) = 1:15625 ZCD (50 Hz) = 1:25 ZCD (60 Hz) = 1:30 Calibration of the RTCC can be performed to yield an error of three seconds or less per month (see Section 24.1.7 “Calibration” for more information). FIGURE 24-4: CLOCK SOURCE MULTIPLEXING Rev. 10-000314A 12/5/2016 SOSC (32.768kHz) 1:16384 00 MFINTOSC/16 (31.25kHz) 1:15625 01 ZCD (50Hz) 1:25 10 ZCD (60Hz) 1:30 11 500ms Clock 1/2 Second(1) 1 Second Clock Second Note 1: 24.1.4 Hours Minutes Day Day of Week Month Year Writing to the SECONDS register resets all counters, allowing for fraction of a second synchronization. DIGIT CARRY RULES This section explains which timer values are affected when there is a rollover. • Time of Day: From 23:59:59 to 00:00:00 with a carry to the Day and Weekday field • Month: From 12/31 to 01/01 with a carry to the Year field • Day of Week: From 6 to 0 with no carry (see Table 24-1) • Year Carry: From 99 to 00; this also surpasses the use of the RTCC TABLE 24-1: DAY OF WEEK SCHEDULE Day of Week Sunday 0 Monday 1 Tuesday 2 Wednesday 3 Thursday 4 Friday 5 Saturday 6 For the day to month rollover schedule, see Table 24-2. Because the following values are in BCD format, the carry to the upper BCD digit will occur at a count of 10 and not at 16 (SECONDS, MINUTES, HOURS, WEEKDAY, DAYS and MONTHS).  2017-2021 Microchip Technology Inc. DS40001873E-page 349 PIC16(L)F19195/6/7 TABLE 24-2: DAY TO MONTH ROLLOVER SCHEDULE Month Maximum Day Field 01 (January) 31 02 (February) 28 or 29(1) 03 (March) 31 04 (April) 30 05 (May) 31 06 (June) 30 The Status bit is set a number of clock edges before a rollover is about to occur, as follows: • RTCCLKSEL = 00: 32 SOSC clock cycles • RTCCLKSEL = 01: 32 MFINTOSC/16 clock cycles • RTCCLKSEL = 10: 1 50 Hz clock cycle (ZCD) • RTCCLKSEL = 11: 1 60 Hz clock cycle (ZCD) 07 (July) 31 08 (August) 31 The RTCSYNC bit is cleared at the time the rollover occurs. Assuming that the device uses the 32.768 kHz oscillator as the device clock (RTCCLKSEL = 00), the 32 clock edges allow execution of about six instructions following a read of the RTCSYNC of ‘0’ (a period of time is lost due to bit synchronization). 09 (September) 30 24.1.7 10 (October) 31 11 (November) 30 12 (December) 31 The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than three seconds per month. Note 1: 24.1.5 See Section 24.1.5 “Leap Year”. LEAP YEAR Since the year range on the RTCC module is 2000 to 2099, the leap year calculation is determined by any year divisible by four in the above range. Only February is effected in a leap year. This is accomplished by finding the number of error clock pulses and storing the value into the RTCCAL register. The 8-bit signed value loaded into RTCCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute. Note: February will have 29 days in a leap year and 28 days in any other year. Note: 24.1.6 The corresponding counters are clocked based on their defined intervals (i.e., the DAYS register is clocked once a day, the MONTHS register is only clocked once a month, etc.). This leaves large windows of time during which registers can be safely updated. SAFETY WINDOW FOR REGISTER READS AND WRITES The RTCC 1/2 second clock signal can be brought out to a pin via PPS. See Section 15.0 “Peripheral Pin Select (PPS) Module” and Table 15-3. To calibrate the RTCC module refer to the steps below: 1. 2. The user must first find the error of the timer source being used. Once the error is known, it must be converted to the number of error clock pulses per minute (see Equation 24-1). EQUATION 24-1: CONVERTING ERROR CLOCK PULSES (Ideal Frequency (32,768) – Measured Frequency) * The RTCSYNC bit indicates a time window during which the RTCC Clock Domain registers can be safely read and written without concern about a rollover. When RTCSYNC = 0, the registers can be safely accessed by the CPU. 60 = Error Clocks per Minute Whether RTCSYNC = 1 or 0, the user should employ a firmware solution to ensure that the data read did not fall on a rollover boundary, resulting in an invalid or partial read. This firmware solution would consist of reading each register twice and then comparing the two values. If the two values matched, then, a rollover did not occur. 3.  2017-2021 Microchip Technology Inc. CALIBRATION • If the oscillator is faster than ideal (negative result from Step 2), the RTCCAL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. • If the oscillator is slower than ideal (positive result from Step 2), the RTCCAL register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter, once every minute. Load the RTCCAL register with the correct value. DS40001873E-page 350 PIC16(L)F19195/6/7 24.2.1 Writes to the RTCCAL register should occur only when the timer is turned off, or immediately after the rising edge of the seconds pulse, except when SECONDS = 00, 15, 30 or 45 due to the possibility of the auto-adjust event. Note: 24.2 The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. The bit will not be cleared if the CHIME bit = 1. The interval selection of the alarm is configured through the ALRMCFG (AMASK) bits (see Figure 24-5). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. In determining the crystal’s error value, it is the user’s responsibility to include the crystal’s initial error from drift due to temperature or crystal aging. The number of times this occurs, after the alarm is enabled, is stored in the lower half of the ALRMRPT register. Alarm The alarm features and characteristics are: Note: • Configurable from half a second to one year • Enabled using the ALRMEN bit (ALRMCON, Register 24-10) • Offers one time and repeat alarm options FIGURE 24-5: CONFIGURING THE ALARM While the alarm is enabled (ALRMEN = 1), changing any of the registers, other than the ALRMRPT register, and the CHIME bit, can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALRMRPT register and CHIME bit be changed when RTCSYNC = 0. ALARM MASK SETTINGS Alarm Mask Setting AMASK Day of the Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s m s s m m s s 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week d 1000 – Every month 1001 – Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when configured for February 29.  2017-2021 Microchip Technology Inc. DS40001873E-page 351 PIC16(L)F19195/6/7 When ALRMRPT = 00 and the CHIME bit = 0 (ALRMCON), the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading the ALRMRPT register with FFh with the CHIME bit = 1. After each alarm is issued, the ALRMRPT register is decremented by one. Once the register has reached ‘00’, the alarm will be issued one last time. After the alarm is issued a last time, the ALRMEN bit is cleared automatically and the alarm turned off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the ALRMRPT register reaches ‘00’, it will roll over to FFh and continue counting when CHIME = 1. 24.2.2 ALARM INTERRUPT At every alarm event, an interrupt is generated and the RTCCIF bit is set. Additionally, an alarm pulse output is provided that operates at half the frequency of the alarm. The alarm pulse output is completely synchronous with the RTCC clock and can be used as a trigger clock to other peripherals. 24.3 VBAT Operation This device is equipped with a VBAT pin that allows the user to connect an external battery or Supercap. In the event of the VDD supply failing or dropping below the supply voltage level on the VBAT pin, the power source connected to the VBAT pin will keep the SOSC and RTCC blocks running. VBAT is enabled via the VBATEN bit in Configuration Word 1. 24.4 Sleep Mode The timer and alarm continue to operate while in Sleep mode. The operation of the alarm is not affected by Sleep, as an alarm event can always wake-up the CPU. Idle mode does not affect the operation of the timer or alarm. 24.5 Resets The RTCCON and RTCCAL registers are only reset on a POR or BOR event. Only a POR or BOR event will turn the RTCC module off if VBAT is valid. If the VBAT module is enabled and active during a POR or BOR, the RTCCON and RTCCAL registers will not reset. The RTCC module will continue with normal operation during the reset. The timer prescaler values can only be reset by writing to the SECONDS register. No device reset will affect the prescaler values.  2017-2021 Microchip Technology Inc. DS40001873E-page 352 PIC16(L)F19195/6/7 24.6 RTCC Control Registers REGISTER 24-1: RTCCON: RTC CONTROL REGISTER R/W-0/u U-0 R/W-0/u RTCEN(1) — RTCWREN R-0/u R-0/u RTCSYNC HALFSEC(2) U-0 R/W-0/u R/W-0/u — RTCCLKSEL1 RTCCLKSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared u = Bit is unchanged x = Bit is unknown bit 7 RTCEN: RTCC Enable bit(1) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCC registers can be written to by the user 0 = RTCC registers are locked out from being written to by the user bit 4 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCC registers can change while reading due to a rollover ripple resulting in an invalid data read; if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCC registers can be read without concern over a rollover ripple bit 3 HALFSEC: Half-Second Status bit(2) 1 = Second half period of a second 0 = First half period of a second bit 2 Unimplemented: Read as ‘0’ bit 1-0 RTCCLKSEL: RTC Clock Source Selection bits 00 = SOSC (expected to 32.768 kHz) 01 = MFINTOSC/16 (31.25 kHz) 10 = 50 Hz Powerline Clock (Zero-Cross Detect) 11 = 60 Hz Powerline Clock (Zero-Cross Detect) Note 1: 2: A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to '0' on a write to the SECONDS register.  2017-2021 Microchip Technology Inc. DS40001873E-page 353 PIC16(L)F19195/6/7 RTCCAL: RTC CALIBRATION REGISTER REGISTER 24-2: R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CAL: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 00000001 = Minimum positive adjustment; adds four RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts four RTC clock pulses every one minute . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute YEAR(1): YEAR VALUE REGISTER REGISTER 24-3: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEARH R/W-x R/W-x YEARL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 YEARH: Binary Coded Decimal value of years ‘10’ digit; contains a value from 0 to 9 bit 3-0 YEARL: Binary Coded Decimal value of years ‘1’ digit; contains a value from 0 to 9 Note 1: Writes to the YEAR register is only allowed when RTCWREN = 1. MONTH(1): MONTH VALUE REGISTER REGISTER 24-4: U-0 U-0 U-0 R/W-x — — — MONTHH R/W-x R/W-x R/W-x R/W-x MONTHL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MONTHH: Binary Coded Decimal value of months ‘10’ digit; valid values from 0 to 1 bit 3-0 MONTHL: Binary Coded Decimal value of months ‘1’ digit; valid values from 0 to 9 Note 1: Writes to the MONTH registers are only allowed when RTCWREN = 1.  2017-2021 Microchip Technology Inc. DS40001873E-page 354 PIC16(L)F19195/6/7 WEEKDAY(1): WEEKDAY VALUE REGISTER REGISTER 24-5: U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x WDAY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY: Binary Coded Decimal value of weekdays ‘1’ digit; valid values from 0 to 6 Note 1: Writes to the WDAY registers are only allowed when RTCWREN = 1. DAY(1): DAY VALUE REGISTER REGISTER 24-6: U-0 U-0 — — R/W-x R/W-x R/W-x R/W-x DAYH R/W-x R/W-x DAYL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYH: Binary Coded Decimal value of days ‘10’ digit; valid values from 0 to 3 bit 3-0 DAYL: Binary Coded Decimal value of days ‘1’ digit; valid values from 0 to 9 Note 1: Writes to the DAY registers are only allowed when RTCWREN = 1. HOURS(1): HOUR VALUE REGISTER REGISTER 24-7: U-0 U-0 — — R/W-x R/W-x R/W-x HRH R/W-x R/W-x R/W-x HRL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRH: Binary Coded Decimal value of hours ‘10’ digit; valid values from 0 to 2 bit 3-0 HRL: Binary Coded Decimal value of hours ‘1’ digit; valid values from 0 to 9 Note 1: Writes to the HOURS registers are only allowed when RTCWREN = 1.  2017-2021 Microchip Technology Inc. DS40001873E-page 355 PIC16(L)F19195/6/7 REGISTER 24-8: U-0 MINUTES(1): MINUTE VALUE REGISTER R/W-x — R/W-x R/W-x R/W-x MINH R/W-x R/W-x R/W-x MINL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINH: Binary Coded Decimal value of minutes ‘10’ digit; valid values from 0 to 5 bit 3-0 MINL: Binary Coded Decimal value of minutes ‘1’ digit; valid values from 0 to 9 Note 1: Writes to the MINUTE registers are only allowed when RTCWREN = 1. REGISTER 24-9: U-0 SECONDS(1): SECOND VALUE REGISTER R/W-x — R/W-x R/W-x R/W-x SECH R/W-x R/W-x R/W-x SECL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECH: Binary Coded Decimal value of seconds ‘10’ digit; valid values from 0 to 5 bit 3-0 SECL: Binary Coded Decimal value of seconds ‘1’ digit; valid values from 0 to 9 Note 1: Writes to the SECOND registers are only allowed when RTCWREN = 1.  2017-2021 Microchip Technology Inc. DS40001873E-page 356 PIC16(L)F19195/6/7 REGISTER 24-10: ALRMCON: ALARM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALRMEN: Alarm Enable bit(1) 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 0000 0000 and CHIME = 0) 0 = Alarm is disabled bit 6 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT bits stop once they reach 00h bit 5-2 AMASK: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every four years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 1-0 Note 1: Unimplemented: Read as ‘0’ ALRMEN is cleared automatically any time an alarm event occurs when ARPT = 00 and CHIME = 0 REGISTER 24-11: ALRMRPT: ALARM REPEAT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown ARPT: Alarm Repeat Counter Value bits(1) 00000000 = Alarm will repeat 0 more times . . . 11111111 = Alarm will repeat 255 more times The counter decrements on any alarm event. The counter is prevented from rolling over from ‘255’ to ‘0’ unless CHIME = 1.  2017-2021 Microchip Technology Inc. DS40001873E-page 357 PIC16(L)F19195/6/7 REGISTER 24-12: ALRMMTH: ALARM MONTH CONTROL REGISTER U-0 U-0 U-0 R/W-x — — — ALRMHMONTH R/W-x R/W-x R/W-x R/W-x ALRMLMONTH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 ALRMHMONTH: Binary Coded Decimal value of months ‘10’ digit; valid value from 0 to 1 bit 3-0 ALRMLMONTH: Binary Coded Decimal value of months ‘1’ digit; valid value from 0 to 9 REGISTER 24-13: ALRMWD: ALARM WEEKDAY CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x ALRMLWDAY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ALRMLWDAY: Binary Coded Decimal value of weekdays ‘1’ digit; valid values from 0 to 6. REGISTER 24-14: ALRMDAY: ALARM DAY CONTROL REGISTER U-0 U-0 — — R/W-x R/W-x R/W-x ALRMHDAY R/W-x R/W-x R/W-x ALRMLDAY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ALRMHDAY: Binary Coded Decimal value of days ‘10’ digit; valid value from 0 to 3 bit 3-0 ALRMLDAY: Binary Coded Decimal value of days ‘1’ digit; valid value from 0 to 9  2017-2021 Microchip Technology Inc. DS40001873E-page 358 PIC16(L)F19195/6/7 REGISTER 24-15: ALRMHR: ALARM HOUR CONTROL REGISTER U-0 U-0 — — R/W-x R/W-x R/W-x ALRMHHR R/W-x R/W-x R/W-x ALRMLHR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ALRMHHR: Binary Coded Decimal value of hours ‘10’ digit; valid values from 0 to 2 bit 3-0 ALRMLHR: Binary Coded Decimal value of hours ‘1’ digit; valid values from 0 to 9 REGISTER 24-16: ALRMMIN: ALARM MINUTE CONTROL REGISTER U-0 R/W-x — R/W-x R/W-x R/W-x ALRMHMIN R/W-x R/W-x R/W-x ALRMLMIN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ALRMHMIN: Binary Coded Decimal value of minutes ‘10’ digit; valid values from 0 to 5 bit 3-0 ALRMLMIN: Binary Coded Decimal value of minutes ‘1’ digit; valid values from 0 to 9 REGISTER 24-17: ALRMSEC: ALARM SECONDS CONTROL REGISTER U-0 R/W-x — R/W-x R/W-x R/W-x ALRMHSEC R/W-x R/W-x R/W-x ALRMLSEC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ALRMHSEC: Binary Coded Decimal value of seconds ‘10’ digit; valid values from 0 to 5 bit 3-0 ALRMLSEC: Binary Coded Decimal value of seconds ‘1’ digit; valid values from 0 to 9  2017-2021 Microchip Technology Inc. DS40001873E-page 359 PIC16(L)F19195/6/7 TABLE 24-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE RTCC MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page PIE8 LCDIE RTCCIE — — — SMT1PWAIE SMT1PRAIE SMT1IE 156 PIR8 LCDIF RTCCIF — — — SMT1PWAIF SMT1PRAIF SMT1IF 165 PMD2 RTCCMD DACMD ADCMD — — CMP2MD CMP1MD ZCDMD 266 INTCON GIE PEIE — — — — — INTEDG 147 PCON1 — — — — — — MEMV VBATBOR RTCEN — RTCWREN RTCSYNC HALFSEC — ALRMEN CHIME RTCCON RTCCAL ALRMCON RTCCLKSEL CAL 354 AMASK ALRMRPT — — ARPT YEAR 121 353 357 357 YEARH YEARL 354 MONTH — — — MONTHH WEEKDAY — — — — DAY — — DAYH DAYL HOURS — — HRH HRL 355 MINUTES — MINL 356 SECONDS — SECL 356 ALRMMTH — — — ALRMHMONTH ALRMWD — — — — ALRMDAY — — ALRMHDAY ALRMLDAY ALRMHR — — ALRMHHR ALRMLHR 359 ALRMMIN — ALRMHMIN ALRMLMIN 359 ALRMSEC — ALRMHSEC ALRMLSEC 359 MONTHL — MINH SECH  2017-2021 Microchip Technology Inc. 354 WDAY 355 355 ALRMLMONTH — 358 ALRMLWDAY 358 358 DS40001873E-page 360 PIC16(L)F19195/6/7 25.0 TIMER0 MODULE The Timer0 module is an 8/16-bit timer/counter with the following features: • • • • • • • • • 16-bit timer/counter 8-bit timer/counter with programmable period Synchronous or asynchronous operation Selectable clock sources Programmable prescaler (independent of Watchdog Timer) Programmable postscaler Operation during Sleep mode Interrupt on match or overflow Output on I/O pin (via PPS) or to other peripherals 25.1 Timer0 Operation Timer0 can operate as either an 8-bit timer/counter or a 16-bit timer/counter. The mode is selected with the T016BIT bit of the T0CON register. 25.1.1 16-BIT MODE In normal operation, TMR0 increments on the rising edge of the clock source. A 15-bit prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS in the T0CON1 register). 25.1.1.1 Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode. It is actually a buffered version of the real high byte of Timer0, which is neither directly readable nor writable (see Figure 25-1). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte was valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. 25.1.2 8-BIT MODE In normal operation, TMR0 increments on the rising edge of the clock source. A 15-bit prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS in the T0CON1 register).  2017-2021 Microchip Technology Inc. The value of TMR0L is compared to that of the Period buffer, a copy of TMR0H, on each clock cycle. When the two values match, the following events happen: • TMR0_out goes high for one prescaled clock period • TMR0L is reset • The contents of TMR0H are copied to the period buffer In 8-bit mode, the TMR0L and TMR0H registers are both directly readable and writable. The TMR0L register is cleared on any device Reset, while the TMR0H register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: • A write to the TMR0L register • A write to either the T0CON0 or T0CON1 registers • Any device Reset – Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or • Brown-out Reset (BOR) 25.1.3 COUNTER MODE In Counter mode, the prescaler is normally disabled by setting the T0CKPS bits of the T0CON1 register to ‘0000’. Each rising edge of the clock input (or the output of the prescaler if the prescaler is used) increments the counter by ‘1’. 25.1.4 TIMER MODE In Timer mode, the Timer0 module will increment every instruction cycle as long as there is a valid clock signal and the T0CKPS bits of the T0CON1 register (Register 25-2) are set to ‘0000’. When a prescaler is added, the timer will increment at the rate based on the prescaler value. 25.1.5 ASYNCHRONOUS MODE When the T0ASYNC bit of the T0CON1 register is set (T0ASYNC = ‘1’), the counter increments with each rising edge of the input source (or output of the prescaler, if used). Asynchronous mode allows the counter to continue operation during Sleep mode provided that the clock also continues to operate during Sleep. 25.1.6 SYNCHRONOUS MODE When the T0ASYNC bit of the T0CON1 register is clear (T0ASYNC = 0), the counter clock is synchronized to the system oscillator (FOSC/4). When operating in Synchronous mode, the counter clock frequency cannot exceed FOSC/4. DS40001873E-page 361 PIC16(L)F19195/6/7 25.2 Clock Source Selection The T0CS bits of the T0CON1 register are used to select the clock source for Timer0. Register 25-2 displays the clock source selections. 25.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, Timer0 operates as a timer and will increment on multiples of the clock source, as determined by the Timer0 prescaler. 25.2.2 EXTERNAL CLOCK SOURCE When an external clock source is selected, Timer0 can operate as either a timer or a counter. Timer0 will increment on multiples of the rising edge of the external clock source, as determined by the Timer0 prescaler. 25.3 Programmable Prescaler A software programmable prescaler is available for exclusive use with Timer0. There are 16 prescaler options for Timer0 ranging in powers of two from 1:1 to 1:32768. The prescaler values are selected using the T0CKPS bits of the T0CON1 register. The prescaler is not directly readable or writable. Clearing the prescaler register can be done by writing to the TMR0L register or the T0CON1 register. 25.4 Programmable Postscaler A software programmable postscaler (output divider) is available for exclusive use with Timer0. There are 16 postscaler options for Timer0 ranging from 1:1 to 1:16. The postscaler values are selected using the T0OUTPS bits of the T0CON0 register. The postscaler is not directly readable or writable. Clearing the postscaler register can be done by writing to the TMR0L register or the T0CON0 register.  2017-2021 Microchip Technology Inc. 25.5 Operation during Sleep When operating synchronously, Timer0 will halt. When operating asynchronously, Timer0 will continue to increment and wake the device from Sleep (if Timer0 interrupts are enabled) provided that the input clock source is active. 25.6 Timer0 Interrupts The Timer0 Interrupt Flag bit (TMR0IF) is set when either of the following conditions occur: • 8-bit TMR0L matches the TMR0H value • 16-bit TMR0 rolls over from ‘FFFFh’ When the postscaler bits (T0OUTPS) are set to 1:1 operation (no division), the T0IF flag bit will be set with every TMR0 match or rollover. In general, the TMR0IF flag bit will be set every T0OUTPS +1 matches or rollovers. If Timer0 interrupts are enabled (TMR0IE bit of the PIE0 register = 1), the CPU will be interrupted and the device may wake from sleep (see Section 25.2 “Clock Source Selection” for more details). 25.7 Timer0 Output The Timer0 output can be routed to any I/O pin via the RxyPPS output selection register (see Section 15.0 “Peripheral Pin Select (PPS) Module” for additional information). The Timer0 output can also be used by other peripherals, such as the Auto-conversion Trigger of the Analog-to-Digital Converter. Finally, the Timer0 output can be monitored through software via the Timer0 output bit (T0OUT) of the T0CON0 register (Register 25-1). TMR0_out will be one postscaled clock period when a match occurs between TMR0L and TMR0H in 8-bit mode, or when TMR0 rolls over in 16-bit mode. The Timer0 output is a 50% duty cycle that toggles on each TMR0_out rising clock edge. DS40001873E-page 362 PIC16(L)F19195/6/7 FIGURE 25-1: BLOCK DIAGRAM OF TIMER0 Rev. 10-000017D 4/6/2017 CLC1 111 SOSC 110 MFINTOSC 101 T0CKPS 100 LFINTOSC HFINTOSC 011 FOSC/4 010 PPS 001 Peripherals TMR0 body T0OUTPS T0IF 1 Prescaler SYNC 0 IN OUT TMR0 FOSC/4 T016BIT T0ASYNC 000 T0_out Postscaler Q D T0CKIPPS PPS RxyPPS CK Q 3 T0CS 16-bit TMR0 Body Diagram (T016BIT = 1) 8-bit TMR0 Body Diagram (T016BIT = 0) IN TMR0L R Clear IN TMR0L TMR0 High Byte OUT 8 Read TMR0L COMPARATOR OUT Write TMR0L T0_match 8 8 TMR0H TMR0 High Byte Latch Enable 8 TMR0H 8 Internal Data Bus  2017-2021 Microchip Technology Inc. DS40001873E-page 363 PIC16(L)F19195/6/7 REGISTER 25-1: T0CON0: TIMER0 CONTROL REGISTER 0 R/W-0/0 U-0 R-0 R/W-0/0 T0EN — T0OUT T016BIT R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 T0OUTPS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 T0EN: Timer0 Enable bit 1 = The module is enabled and operating 0 = The module is disabled and in the lowest power mode bit 6 Unimplemented: Read as ‘0’ bit 5 T0OUT: Timer0 Output bit (read-only) Timer0 output bit bit 4 T016BIT: Timer0 Operating as 16-bit Timer Select bit 1 = Timer0 is a 16-bit timer 0 = Timer0 is an 8-bit timer bit 3-0 T0OUTPS: Timer0 output postscaler (divider) select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler  2017-2021 Microchip Technology Inc. DS40001873E-page 364 PIC16(L)F19195/6/7 REGISTER 25-2: R/W-0/0 T0CON1: TIMER0 CONTROL REGISTER 1 R/W-0/0 R/W-0/0 T0CS R/W-0/0 R/W-0/0 T0ASYNC R/W-0/0 R/W-0/0 R/W-0/0 T0CKPS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 T0CS: Timer0 Clock Source select bits 111 = CLC1 110 = SOSC 101 = MFINTOSC (500 kHz) 100 = LFINTOSC 011 = HFINTOSC 010 = FOSC/4 001 = T0CKIPPS (Inverted) 000 = T0CKIPPS (True) bit 4 T0ASYNC: TMR0 Input Asynchronization Enable bit 1 = The input to the TMR0 counter is not synchronized to system clocks 0 = The input to the TMR0 counter is synchronized to FOSC/4 bit 3-0 T0CKPS: Prescaler Rate Select bit 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1  2017-2021 Microchip Technology Inc. DS40001873E-page 365 PIC16(L)F19195/6/7 TABLE 25-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 361* TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 361* T0CON0 T0EN T0CON1 ― T0OUT T0CS T016BIT T0OUTPS 364 T0ASYNC T0CKPS 365 — T0CKIPPS 259 T0CKIPPS ― ― ― TMR0PPS ― ― ― T1GCON GE GPOL GTM GSPM GGO/DONE GVAL — — 376 INTCON GIE PEIE ― ― ― ― ― INTEDG 147 PIR0 ― ― TMR0IF IOCIF ― ― ― INTF 157 PIE0 ― ― TMR0IE IOCIE ― ― ― INTE 148 Legend: * TMR0PPS 259 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. Page with Register information.  2017-2021 Microchip Technology Inc. DS40001873E-page 366 PIC16(L)F19195/6/7 26.0 TIMER1 MODULE WITH GATE CONTROL • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Auto-conversion Trigger (with CCP) • Selectable Gate Source Polarity • Gate Toggle mode • Gate Single-Pulse mode • Gate Value Status • Gate Event Interrupt The Timer1 module is 16-bit timer/counters with the following features: • • • • 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Clock source for optional comparator synchronization • Multiple Timer1 gate (count enable) sources • Interrupt on overflow FIGURE 26-1: Figure 26-1 is a block diagram of the Timer1 module. This device has one instance of Timer1 type modules. TIMER1 BLOCK DIAGRAM TMRxGATE Rev. 10-000018M 9/25/2017 5 TxGPPS TxGSPM 00000 PPS Note 1 0 (5) Single Pulse Acq. Control 1 11111 D D 0 Q TxGVAL Q1 Q TxGGO/DONE TxGPOL CK Q Interrupt TMRxON R set bit TMRxGIF det TxGTM TMRxGE set flag bit TMRxIF TMRxON EN Tx_overflow To Comparators (6) TMRx(2) TMRxH TMRxL Q Synchronized Clock Input 0 D 1 TxCLK TxSYNC TMRxCLK 4 TxCKIPPS (1) 0000 PPS Note (4) Prescaler 1,2,4,8 1111 det 2 TxCKPS Note 1: 2: 3: 4: 5: 6: Synchronize(3) Fosc/2 Internal Clock Sleep Input ST Buffer is high speed type when using TxCKIPPS. TMRx register increments on rising edge. Synchronize does not operate while in Sleep. See Register 26-3 for Clock source selections. See Register 26-4 for GATE source selections. Synchronized comparator output should not be used in conjunction with synchronized input clock.  2017-2021 Microchip Technology Inc. DS40001873E-page 367 PIC16(L)F19195/6/7 26.1 Timer1 Operation 26.2 The Timer1 modules are 16-bit incrementing counters which are accessed through the TMR1H:TMR1L register pairs. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. The timer is enabled by configuring the TMR1ON and GE bits in the T1CON and T1GCON registers, respectively. Table 26-1 displays the Timer1 enable selections. TABLE 26-1: TIMER1 ENABLE SELECTIONS Timer1 Operation TMR1ON TMR1GE 1 1 Count Enabled 1 0 Always On 0 1 Off 0 0 Off Clock Source Selection The T1CLK register is used to select the clock source for the timer. Register 26-3 shows the possible clock sources that may be selected to make the timer increment. 26.2.1 INTERNAL CLOCK SOURCE When the internal clock source FOSC is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the respective Timer1 prescaler. When the FOSC internal clock source is selected, the timer register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the TMR1H:TMR1L value. To utilize the full resolution of the timer in this mode, an asynchronous input signal must be used to gate the timer clock input. Out of the total timer gate signal sources, the following subset of sources can be asynchronous and may be useful for this purpose: • • • • • • • • CLC4 output CLC3 output CLC2 output CLC1 output Zero-Cross Detect output Comparator2 output Comparator1 output TxG PPS remappable input pin 26.2.2 EXTERNAL CLOCK SOURCE When the timer is enabled and the external clock input source (ex: T1CKI PPS remappable input) is selected as the clock source, the timer will increment on the rising edge of the external clock input. When using an external clock source, the timer can be configured to run synchronously or asynchronously, as described in Section 26.5 “Timer Operation in Asynchronous Counter Mode”. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used connected to the SOSCI/SOSCO pins. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • •  2017-2021 Microchip Technology Inc. The timer is first enabled after POR Firmware writes to TMR1H or TMR1L The timer is disabled The timer is re-enabled (e.g., TMR1ON-->1) when the T1CKI signal is currently logic low. DS40001873E-page 368 PIC16(L)F19195/6/7 26.3 Timer Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 26.4 Secondary Oscillator A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is designed to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. The oscillator will continue to run during Sleep. Note: 26.5 The oscillator requires a start-up and stabilization time before use. Thus, SOSCEN should be set and a suitable delay observed prior to using Timer1 with the SOSC source. A suitable delay similar to the OST delay can be implemented in software by clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to FC00h. The TMR1IF flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. Timer Operation in Asynchronous Counter Mode If the control bit SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 26.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: 26.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 26.6 Timer Gate Timer1 can be configured to count freely or the count can be enabled and disabled using the time gate circuitry. This is also referred to as Timer Gate Enable. The timer gate can also be driven by multiple selectable sources. 26.6.1 TIMER GATE ENABLE The Timer Gate Enable mode is enabled by setting the GE bit of the T1GCON register. The polarity of the Timer Gate Enable mode is configured using the GPOL bit of the T1GCON register. When Timer Gate Enable signal is enabled, the timer will increment on the rising edge of the Timer1 clock source. When Timer Gate Enable signal is disabled, the timer always increments, regardless of the GE bit. See Figure 26-3 for timing details. TABLE 26-2: TIMER GATE ENABLE SELECTIONS T1CLK T1GPOL T1G Timer Operation  1 1 Counts  1 0 Holds Count  0 1 Holds Count  0 0 Counts When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.  2017-2021 Microchip Technology Inc. DS40001873E-page 369 PIC16(L)F19195/6/7 26.6.2 TIMER GATE SOURCE SELECTION One of the several different external or internal signal sources may be chosen to gate the timer and allow the timer to increment. The gate input signal source can be selected based on the T1GATE register setting. See the T1GATE register (Register 26-4) description for a complete list of the available gate sources. The polarity for each available source is also selectable. Polarity selection is controlled by the GPOL bit of the T1GCON register. 26.6.2.1 T1G Pin Gate Operation The T1G pin is one source for the timer gate control. It can be used to supply an external source to the time gate circuitry. 26.6.2.2 Timer0 Overflow Gate Operation 26.6.4 TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the GSPM bit in the T1GCON register. Next, the GGO/DONE bit in the T1GCON register must be set. The timer will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment the timer until the GGO/DONE bit is once again set in software. See Figure 26-5 for timing details. If the Single-Pulse Gate mode is disabled by clearing the GSPM bit in the T1GCON register, the GGO/DONE bit should also be cleared. When Timer0 overflows, or a period register match condition occurs (in 8-bit mode), a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the timer gate source to be measured. See Figure 26-6 for timing details. 26.6.2.3 26.6.5 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for the timer gate control. The Comparator 1 output can be synchronized to the timer clock or left asynchronous. For more information see Section 22.5.1 “Comparator Output Synchronization”. 26.6.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for the timer gate control. The Comparator 2 output can be synchronized to the timer clock or left asynchronous. For more information see Section 22.5.1 “Comparator Output Synchronization”. 26.6.3 TIMER1 GATE TOGGLE MODE TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the GVAL bit in the T1GCON register. The GVAL bit is valid even when the timer gate is not enabled (GE bit is cleared). 26.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of GVAL occurs, the TMR1GIF flag bit in the PIR5 register will be set. If the TMR1GIE bit in the PIE5 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the timer gate is not enabled (TMR1GE bit is cleared). When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a timer gate signal, as opposed to the duration of a single level pulse. The timer gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 26-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the GTM bit of the T1GCON register. When the GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation.  2017-2021 Microchip Technology Inc. DS40001873E-page 370 PIC16(L)F19195/6/7 26.7 Timer1 Interrupts The Timer1 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the respective PIR register is set. To enable the interrupt-on-rollover, you must set these bits: • • • • ON bit of the T1CON register TMR1IE bit of the PIE4 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 26.8 To avoid immediate interrupt vectoring, the TMR1H:TMR1L register pair should be preloaded with a value that is not imminently about to rollover, and the TMR1IF flag should be cleared prior to enabling the timer interrupts. Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • ON bit of the T1CON register must be set TMR1IE bit of the PIE4 register must be set PEIE bit of the INTCON register must be set SYNC bit of the T1CON register must be set 26.9 CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. In Compare mode, an event is triggered when the value CCPRxH:CCPRxL register pair matches the value in the TMR1H:TMR1L register pair. This event can be an Auto-conversion Trigger. For more information, see “Capture/Compare/PWM Modules”. Section 29.0 26.10 CCP Special Event Trigger When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine.  2017-2021 Microchip Technology Inc. DS40001873E-page 371 PIC16(L)F19195/6/7 FIGURE 26-2: TIMER1 INCREMENTING EDGE TxCKI = 1 when the timer is enabled TxCKI = 0 when the timer is enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 26-3: TIMER1 GATE ENABLE MODE TMRxGE TxGPOL selected gate input TxCKI TxGVAL TMRxH:TMRxL Count N  2017-2021 Microchip Technology Inc. N+1 N+2 N+3 N+4 DS40001873E-page 372 PIC16(L)F19195/6/7 FIGURE 26-4: TIMER1 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM selected gate input TxCKI TxGVAL TMRxH:TMRxL Count FIGURE 26-5: N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ DONE Cleared by hardware on falling edge of TxGVAL Set by software Counting enabled on rising edge of selected source selected gate source TxCKI TxGVAL TMRxH:TMRxL Count TMRxGIF N Cleared by software  2017-2021 Microchip Technology Inc. N+1 N+2 Set by hardware on falling edge of TxGVAL Cleared by software DS40001873E-page 373 PIC16(L)F19195/6/7 FIGURE 26-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ DONE Cleared by hardware on falling edge of TxGVAL Set by software Counting enabled on rising edge of selected source selected gate source TxCKI TxGVAL TMRxH:TMRxL Count TMRxGIF N N+1 Cleared by software N+2 N+3 N+4 Set by hardware on falling edge of TxGVAL Cleared by software 26.11 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bit for Timer1 (TMR1MD) are in the PMD1 register. See Section 16.0 “Peripheral Module Disable (PMD)” for more information.  2017-2021 Microchip Technology Inc. DS40001873E-page 374 PIC16(L)F19195/6/7 26.12 Register Definitions: Timer1 Control REGISTER 26-1: T1CON: TIMER1 CONTROL REGISTER U-0 U-0 — — R/W-0/u R/W-0/u CKPS U-0 R/W-0/u R/W-0/u R/W-0/u — SYNC RD16 ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CKPS: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 Unimplemented: Read as ‘0’ bit 2 SYNC: Timer1 Synchronization Control bit When TMR1CLK = FOSC or FOSC/4 This bit is ignored. The timer uses the internal clock and no additional synchronization is performed. ELSE 0 = Synchronize external clock input with system clock 1 = Do not synchronize external clock input bit 1 RD16: 16-bit Read/Write Mode Enable bit 0 = Enables register read/write of Timer1 in two 8-bit operation 1 = Enables register read/write of Timer1 in one 16-bit operation bit 0 ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop  2017-2021 Microchip Technology Inc. DS40001873E-page 375 PIC16(L)F19195/6/7 REGISTER 26-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x U-0 U-0 GE GPOL GTM GSPM GGO/DONE GVAL — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 GE: Timer1 Gate Enable bit If ON = 0: This bit is ignored If ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 is always counting bit 6 GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when GSPM is cleared bit 2 GVAL: Timer1 Gate Value Status bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L Unaffected by Timer1 Gate Enable (GE) bit 1-0 Unimplemented: Read as ‘0’  2017-2021 Microchip Technology Inc. DS40001873E-page 376 PIC16(L)F19195/6/7 REGISTER 26-3: T1CLK TIMER1 CLOCK SELECT REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/u R/W-0/u R/W-0/u R/W-0/u CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CS: Timer1 Clock Select bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = LC4_out 1011 = LC3_out 1010 = LC2_out 1001 = LC1_out 1000 = Timer0 Overflow Output 0111 = SOSC 0110 = MFINTOSC/16 (31.25 kHz) 0101 = MFINTOSC (500 kHz) 0100 = LFINTOSC 0011 = HFINTOSC 0010 = FOSC 0001 = FOSC/4 0000 = TxCKIPPS  2017-2021 Microchip Technology Inc. DS40001873E-page 377 PIC16(L)F19195/6/7 REGISTER 26-4: T1GATE TIMER1 GATE SELECT REGISTER U-0 U-0 U-0 — — — R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u GSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 GSS: Timer1 Gate Select bits 11111-10001 = Reserved 10000 = RTCC second output 01111 = ZCD1 output 01110 = C2OUT output 01101 = C1OUT output 01100 = LC4 out 01011 = LC3 out 01010 = LC2 out 01001 = LC1 out 01000 = PWM4 out 00111 = PWM3 out 00110 = CCP2 out 00101 = CCP1 out 00100 = SMT1 overflow output 00011 = TMR4 postscaled 00010 = TMR2 postscaled 00001 = Timer0 overflow output 00000 = T1GPPS  2017-2021 Microchip Technology Inc. DS40001873E-page 378 PIC16(L)F19195/6/7 TABLE 26-3: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE ― ― ― ― ― INTEDG 147 PIE4 — — — — TMR4IE — TMR2IE TMR1IE 152 PIR4 — — — — TMR4IF — TMR2IF TMR1IF 161 — SYNC RD16 ON 375 GGO/DONE GVAL — — 376 T1CON — — T1GCON GE GPOL GTM T1GATE — — — — — — T1CLK CKPS GSPM GSS — 378 CS TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 377 T1CKIPPS ― ― ― T1CKIPPS 259 T1GPPS ― ― ― T1GPPS 259 CCPTMRS0 P4TSEL P3TSEL C2TSEL C1TSEL 457 CCPxCON CCPxEN — CLCxSELy ― ― ― LCxDyS 499 ― ― ― ACT 319 ADACT Legend: * CCPxOUT CCPxFMT CCPxMODE 454 — = Unimplemented location, read as ‘0’. Shaded cells are not used with the Timer1 modules. Page with register information.  2017-2021 Microchip Technology Inc. DS40001873E-page 379 PIC16(L)F19195/6/7 27.0 TIMER2/4 MODULE WITH HARDWARE LIMIT TIMER (HLT) • • • • • • • The Timer2/4 modules are 8-bit timers that can operate as free-running period counters or in conjunction with external signals that control start, run, freeze, and reset operation in One-Shot and Monostable modes of operation. Sophisticated waveform control like pulse density modulation are possible by combining the operation of these timers with other internal peripherals such as the comparators and CCP modules. Features of the timer include: Selectable external hardware timer Resets Programmable prescaler (1:1 to 1:128) Programmable postscaler (1:1 to 1:16) Selectable synchronous/asynchronous operation Alternate clock sources Interrupt-on-period Three modes of operation: - Free Running Period - One-shot - Monostable See Figure 27-1 for a block diagram of Timer2/4. See Figure 27-2 for the clock source block diagram. • 8-bit timer register • 8-bit period register Note: FIGURE 27-1: TIMER2/4 BLOCK DIAGRAM RSEL INPPS TxIN PPS External Reset (2) Sources Two identical Timer2 modules are implemented on this device. The timers are named Timer2 and Timer4. All references to Timer2 apply as well to Timer4. All references to T2PR apply as well to T4PR. Rev. 10-000168C 9/10/2015 MODE TMRx_ers Edge Detector Level Detector Mode Control (2 clock Sync) MODE reset CCP_pset(1) MODE=01 enable D MODE=1011 Q Clear ON CPOL 0 Prescaler TMRx_clk T[7MR 3 CKPS Sync 1 Fosc/4 PSYNC R Comparator Set flag bit TMRxIF Postscaler TMRx_postscaled 4 Sync (2 Clocks) ON 1 7[PR OUTPS 0 CSYNC Note 1: 2: Signal to the CCP to trigger the PWM pulse. See Register 27-4 for external Reset sources.  2017-2021 Microchip Technology Inc. DS40001873E-page 380 PIC16(L)F19195/6/7 FIGURE 27-2: TIMER2/4 CLOCK SOURCE BLOCK DIAGRAM TxCLKCON Rev. 10-000 169B 5/29/201 4 TXINPPS TXIN 27.1.2 PPS Timer Clock Sources (See Table 27-2) to 00h on the next rising TMR2_clk edge and increments the output postscaler counter. When the postscaler count equals the value in the OUTPS bits of the TMRxCON1 register, a one TMR2_clk period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared. TMR2_clk The One-Shot mode is identical to the Free Running Period mode except that the ON bit is cleared and the timer is stopped when TMR2 matches T2PR and will not restart until the T2ON bit is cycled off and on. Postscaler OUTPS values other than 0 are meaningless in this mode because the timer is stopped at the first period event and the postscaler is reset when the timer is restarted. 27.1.3 27.1 Timer2/4 Operation Timer2 operates in three major modes: • Free Running Period • One-shot • Monostable Within each mode there are several options for starting, stopping, and reset. Table 27-1 lists the options. In all modes, the TMR2 count register is incremented on the rising edge of the clock signal from the programmable prescaler. When TMR2 equals T2PR, a high level is output to the postscaler counter. TMR2 is cleared on the next clock input. An external signal from hardware can also be configured to gate the timer operation or force a TMR2 count Reset. In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes the TMR2 count is reset on either the level or edge from the external source. The TMR2 and T2PR registers are both directly readable and writable. The TMR2 register is cleared and the T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters are cleared on the following events: • • • • a write to the TMR2 register a write to the T2CON register any device Reset External Reset Source event that resets the timer. Note: 27.1.1 TMR2 is not cleared when T2CON is written. FREE RUNNING PERIOD MODE The value of TMR2 is compared to that of the Period register, T2PR, on each TMR2_clk cycle. When the two values match, the comparator resets the value of TMR2  2017-2021 Microchip Technology Inc. ONE-SHOT MODE MONOSTABLE MODE Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can be restarted by an external Reset event. 27.2 Timer2/4 Output The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period when the postscaler counter matches the value in the OUTPS bits of the TMR2CON register. The T2PR postscaler is incremented each time the TMR2 value matches the T2PR value. This signal can be selected as an input to several other input modules: • The ADC module, as an Auto-conversion Trigger • COG, as an auto-shutdown source In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. Both the actual TMR2 value as well as other internal signals are sent to the CCP module to properly clock both the period and pulse width of the PWM signal. See Section 29.0 “Capture/Compare/PWM Modules” for more details on setting up Timer2/4 for use with the CCP, as well as the timing diagrams in Section 27.5 “Operation Examples” for examples of how the varying Timer2 modes affect CCP PWM output. 27.3 External Reset Sources In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset source is selected for Timer2 with the T2RST register. This source can control starting and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. The mode of the timer is controlled by the MODE bits of the TMRxHLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug Freeze mode. DS40001873E-page 381 PIC16(L)F19195/6/7 TABLE 27-1: TIMER2/4 OPERATING MODES MODE Mode Output Operation 000 001 Period Pulse 010 Free Running Period 00 Reset Stop ON = 1 — ON = 0 Hardware gate, active-high (Figure 27-5) ON = 1 and TMRx_ers = 1 — ON = 0 or TMRx_ers = 0 Hardware gate, active-low ON = 1 and TMRx_ers = 0 — ON = 0 or TMRx_ers = 1 Rising or falling edge Reset TMRx_ers ↕ 100 Rising edge Reset (Figure 27-6) TMRx_ers ↑ 110 Period Pulse with Hardware Reset 111 000 001 010 011 01 Start Software gate (Figure 27-4) 011 101 One-shot 100 101 110 111 One-shot Edge triggered start (Note 1) Edge triggered start and hardware Reset (Note 1) Falling edge Reset 001 010 011 Reserved 10 Reserved High level Reset (Figure 27-7) 111 Reserved Note 1: 2: 3: 11 ON = 0 or TMRx_ers = 0 TMRx_ers = 1 ON = 0 or TMRx_ers = 1 ON = 1 — Rising edge start (Figure 27-9) ON = 1 and TMRx_ers ↑ — Falling edge start ON = 1 and TMRx_ers ↓ — Any edge start ON = 1 and TMRx_ers ↕ — Rising edge start and Rising edge Reset (Figure 27-10) ON = 1 and TMRx_ers ↑ TMRx_ers ↑ Falling edge start and Falling edge Reset ON = 1 and TMRx_ers ↓ TMRx_ers ↓ Rising edge start and Low level Reset (Figure 27-11) ON = 1 and TMRx_ers ↑ TMRx_ers = 0 Falling edge start and High level Reset ON = 1 and TMRx_ers ↓ TMRx_ers = 1 ON = 0 or Next clock after TMRx = PRx (Note 2) Reserved Edge triggered start (Note 1) Rising edge start (Figure 27-12) ON = 1 and TMRx_ers ↑ — Falling edge start ON = 1 and TMRx_ers ↓ — Any edge start ON = 1 and TMRx_ers ↕ — ON = 0 or Next clock after TMRx = PRx (Note 3) Reserved Reserved 101 One-shot TMRx_ers = 0 Software start (Figure 27-8) 100 110 ON = 0 TMRx_ers ↓ ON = 1 Low level Reset 000 Mono-stable Timer Control Operation Level triggered start and hardware Reset xxx High level start and Low level Reset (Figure 27-13) ON = 1 and TMRx_ers = 1 TMRx_ers = 0 Low level start & High level Reset ON = 1 and TMRx_ers = 0 TMRx_ers = 1 ON = 0 or Held in Reset (Note 2) Reserved If ON = 0 then an edge is required to restart the timer after ON = 1. When TMRx = PRx then the next clock clears ON and stops TMRx at 00h. When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.  2017-2021 Microchip Technology Inc. DS40001873E-page 382 PIC16(L)F19195/6/7 27.4 Timer2/4 Interrupt Timer2/4 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches one of 16 postscale options (from 1:1 through 1:16), which are selected with the postscaler control bits, OUTPS of the T2CON register. The interrupt is enabled by setting the TMR2IE interrupt enable bit of the PIE4 register. Interrupt timing is illustrated in Figure 27-3. FIGURE 27-3: TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM Rev. 10-000205A 4/7/2016 0b010 CKPS PRx 1 OUTPS 0b0001 TMRx_clk TMRx 0 1 0 1 0 1 0 TMRx_postscaled (1) TMRxIF Note 1: 2: (2) (1) Setting the interrupt flag is synchronized with the instruction clock. Synchronization may take as many as 2 instruction cycles Cleared by software.  2017-2021 Microchip Technology Inc. DS40001873E-page 383 PIC16(L)F19195/6/7 27.5 Operation Examples Unless otherwise specified, the following notes apply to the following timing diagrams: - Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the TxCON register are cleared). - The diagrams illustrate any clock except Fosc/4 and show clock-sync delays of at least two full cycles for both ON and Timer2/4_ers. When using Fosc/4, the clock-sync delay is at least one instruction period for Timer2/4_ers; ON applies in the next instruction period. - The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in Section 29.0 “Capture/Compare/PWM Modules”. The signals are not a part of the Timer2/4 module.  2017-2021 Microchip Technology Inc. 27.5.1 SOFTWARE GATE MODE This mode corresponds to legacy Timer2/4 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 27-4. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock. DS40001873E-page 384 PIC16(L)F19195/6/7 FIGURE 27-4: SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000) Rev. 10-000195B 5/30/2014 0b00000 MODE TMRx_clk Instruction(1) BSF BCF BSF ON PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2017-2021 Microchip Technology Inc. DS40001873E-page 385 PIC16(L)F19195/6/7 27.5.2 HARDWARE GATE MODE When MODE = 00001 then the timer is stopped when the external signal is high. When MODE = 00010 then the timer is stopped when the external signal is low. The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal gates the timer. When used with the CCP the gating extends the PWM period. If the timer is stopped when the PWM output is high then the duty cycle is also extended. FIGURE 27-5: Figure 27-5 illustrates the Hardware Gating mode for MODE = 00001 in which a high input level starts the counter. HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001) Rev. 10-000 196B 5/30/201 4 0b00001 MODE TMRx_clk TMRx_ers PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output  2017-2021 Microchip Technology Inc. DS40001873E-page 386 PIC16(L)F19195/6/7 27.5.3 EDGE-TRIGGERED HARDWARE LIMIT MODE When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 27-6. In Hardware Limit mode the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: • Reset on rising or falling edge (MODE= 00011) • Reset on rising edge (MODE = 00100) • Reset on falling edge (MODE = 00101) FIGURE 27-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM (MODE = 00100) Rev. 10-000 197B 5/30/201 4 MODE 0b00100 TMRx_clk PRx 5 Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2017-2021 Microchip Technology Inc. DS40001873E-page 387 PIC16(L)F19195/6/7 27.5.4 LEVEL-TRIGGERED HARDWARE LIMIT MODE When the CCP uses the timer as the PWM time base then the PWM output will be set high when the timer starts counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the timer count matches the PRx value or two clock periods after the external Reset signal goes true and stays true. In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 27-7. Selecting MODE = 00110 will cause the timer to reset on a low level external signal. Selecting MODE = 00111 will cause the timer to reset on a high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0 the external signal is ignored. FIGURE 27-7: The timer starts counting, and the PWM output is set high, on either the clock following the PRx match or two clocks after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to match the CCPRx pulse width value. If the external Reset signal goes true while the PWM output is high then the PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx value. LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM (MODE = 00111) Rev. 10-000198B 5/30/2014 0b00111 MODE TMRx_clk 5 PRx Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2017-2021 Microchip Technology Inc. DS40001873E-page 388 PIC16(L)F19195/6/7 27.5.5 SOFTWARE START ONE-SHOT MODE In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the PRx period value. The ON bit must be set by software to start another timer cycle. Setting MODE = 01000 selects One-Shot mode which is illustrated in Figure 27-8. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. FIGURE 27-8: When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match. SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000) Rev. 10-000199B 4/7/2016 0b01000 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.  2017-2021 Microchip Technology Inc. DS40001873E-page 389 PIC16(L)F19195/6/7 27.5.6 EDGE-TRIGGERED ONE-SHOT MODE The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer: • Rising edge (MODE = 01001) • Falling edge (MODE = 01010) • Rising or Falling edge (MODE = 01011) FIGURE 27-9: If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 27-9 illustrates operation in the rising edge One-Shot mode. When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay deactivated when the timer halts at the PRx period count match. EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001) Rev. 10-000200B 5/19/2016 0b01001 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 CCP_pset TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 27.5.7 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: • Rising edge start and Reset (MODE = 01100) • Falling edge start and Reset (MODE = 01101)  2017-2021 Microchip Technology Inc. The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 27-10 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs. DS40001873E-page 390 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01100) Rev. 10-000201B 4/7/2016 MODE 0b01100 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 2 0 1 2 3 4 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 5 0 PIC16(L)F19195/6/7 DS40001873E-page 391 FIGURE 27-10:  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 27.5.8 LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODES In Level -Triggered One-Shot mode the timer count is reset on the external signal level and starts counting on the rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are selected as follows: • Low Reset level (MODE = 01110) • High Reset level (MODE = 01111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control a new external signal edge is required after the ON bit is set to start the counter. When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx period count match.  2017-2021 Microchip Technology Inc. DS40001873E-page 392 LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110) Rev. 10-000202B 4/7/2016 MODE 0b01110 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 0 1 2 3 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 4 5 0 PIC16(L)F19195/6/7 DS40001873E-page 393 FIGURE 27-11:  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 27.5.9 EDGE-TRIGGERED MONOSTABLE MODES The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON bit is set, and stop incrementing the timer when the timer matches the PRx period value. The following edges will start the timer: • Rising edge (MODE = 10001) • Falling edge (MODE = 10010) • Rising or Falling edge (MODE = 10011) When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the PRx value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP PWM.  2017-2021 Microchip Technology Inc. DS40001873E-page 394 RISING EDGE-TRIGGERED MONOSTABLE MODE TIMING DIAGRAM (MODE = 10001) Rev. 10-000203A 4/7/2016 0b10001 MODE TMRx_clk PRx Instruction(1) 5 BSF BCF BSF BCF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 3 4 5 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 0 1 2 3 4 5 0 PIC16(L)F19195/6/7 DS40001873E-page 395 FIGURE 27-12:  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 27.5.10 LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODES The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level and start counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external signal is not in Reset or the ON bit is set then the other signal being set/made active will start the timer. Reset levels are selected as follows: • Low Reset level (MODE = 10110) • High Reset level (MODE = 10111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control the timer will stay in Reset until both the ON bit is set and the external signal is not at the Reset level. When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation the PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts the timer.  2017-2021 Microchip Technology Inc. DS40001873E-page 396 LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110) Rev. 10-000204A 4/7/2016 0b10110 MODE TMR2_clk PRx 5 Instruction(1) BSF BSF BCF BSF ON TMR2_ers TMRx 0 1 2 3 4 5 0 1 2 3 TMR2_postscaled PWM Duty Cycle ‘D3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 0 1 2 3 4 5 0 PIC16(L)F19195/6/7 DS40001873E-page 397 FIGURE 27-13:  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 27.6 Timer2/4 Operation During Sleep When PSYNC = 1, Timer2/4 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and T2PR registers will remain unchanged while processor is in Sleep mode. When PSYNC = 0, Timer2/4 will operate in Sleep as long as the clock source selected is also still running. Selecting the LFINTOSC, MFINTOSC, or HFINTOSC oscillator as the timer clock source will keep the selected oscillator running during Sleep.  2017-2021 Microchip Technology Inc. DS40001873E-page 398 PIC16(L)F19195/6/7 27.7 Register Definitions: Timer2/4 Control REGISTER 27-1: TxCLKCON: TIMER2/4 CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CS: Timer2/4 Clock Select bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = LC4_out 1011 = LC3_out 1010 = LC2_out 1001 = LC1_out 1000 = ZCD1_output 0111 = SOSC 0110 = MFINTOSC/16 (31.25 kHz) 0101 = MFINTOSC (500 kHz) 0100 = LFINTOSC 0011 = HFINTOSC (32 MHz) 0010 = FOSC 0001 = FOSC/4 0000 = T2CKIPPS  2017-2021 Microchip Technology Inc. DS40001873E-page 399 PIC16(L)F19195/6/7 REGISTER 27-2: R/W/HC-0/0 TxCON: TIMER2/4 CONTROL REGISTER R/W-0/0 ON(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CKPS R/W-0/0 R/W-0/0 OUTPS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 ON: Timer2/4 On bit 1 = Timer2/4 is on 0 = Timer2/4 is off: all counters and state machines are reset bit 6-4 CKPS: Timer2/4-type Clock Prescale Select bits 111 = 1:128 Prescaler 110 = 1:64 Prescaler 101 = 1:32 Prescaler 100 = 1:16 Prescaler 011 = 1:8 Prescaler 010 = 1:4 Prescaler 001 = 1:2 Prescaler 000 = 1:1 Prescaler bit 3-0 OUTPS: Timer2/4 Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 27.5 “Operation Examples”.  2017-2021 Microchip Technology Inc. DS40001873E-page 400 PIC16(L)F19195/6/7 REGISTER 27-3: R/W-0/0 TxHLT: TIMER2/4 HARDWARE LIMIT CONTROL REGISTER R/W-0/0 PSYNC(1, 2) (3) CKPOL R/W-0/0 R/W-0/0 R/W-0/0 (4, 5) R/W-0/0 R/W-0/0 R/W-0/0 (6, 7) CKSYNC MODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PSYNC: Timer2/4 Prescaler Synchronization Enable bit(1, 2) 1 = TMRx Prescaler Output is synchronized to Fosc/4 0 = TMRx Prescaler Output is not synchronized to Fosc/4 bit 6 CKPOL: Timer2/4 Clock Polarity Selection bit(3) 1 = Falling edge of input clock clocks timer/prescaler 0 = Rising edge of input clock clocks timer/prescaler bit 5 CKSYNC: Timer2/4 Clock Synchronization Enable bit(4, 5) 1 = ON register bit is synchronized to TMR2_clk input 0 = ON register bit is not synchronized to TMR2_clk input bit 4-0 MODE: Timer2/4 Control Mode Selection bits(6, 7) See Table 27-1. Note 1: Setting this bit ensures that reading TMRx will return a valid value. 2: When this bit is ‘1’, Timer2/4 cannot operate in Sleep mode. 3: CKPOL should not be changed while ON = 1. 4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled. 5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set. 6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TMRx). 7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.  2017-2021 Microchip Technology Inc. DS40001873E-page 401 PIC16(L)F19195/6/7 REGISTER 27-4: TXRST: TIMER2/4 EXTERNAL RESET SIGNAL SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RSEL: Timer2/4 External Reset Signal Source Selection bits 1111 = Reserved 1110 = RTCC_Seconds 1101 = LC4_out 1100 = LC3_out 1011 = LC2_out 1010 = LC1_out 1001 = ZCD1_output 1000 = C2OUT_sync 0111 = C1OUT_sync 0110 = PWM3_out 0101 = PWM4_out 0100 = CCP2_out 0011 = CCP1_out 0010 = TMR4_postscaled(2) 0001 = TMR2_postscaled(1) 0000 = T2INPPS Note 1: 2: For Timer2, this bit is Reserved. For Timer4, this bit is Reserved.  2017-2021 Microchip Technology Inc. DS40001873E-page 402 PIC16(L)F19195/6/7 TABLE 27-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4 Bit 6 Bit 5 Bit 4 CCP1CON EN — OUT FMT MODE 454 CCP2CON EN — OUT FMT MODE 454 CCPTMRS0 INTCON P4TSEL Bit 3 P3TSEL Bit 2 Bit 1 Bit 0 Register on Page Bit 7 C2TSEL C1TSEL 457 GIE PEIE — — — — — INTEDG 147 PIE1 OSFIE CSWIE — — — — ADTIE ADIE 149 PIR1 OSFIF CSWIF — — — — ADTIF ADIF 158 T2TMR TMR2 380* T2PR PR2 380* T2CON ON T2HLT CKPS OUTPS PSYNC CKPOL CKSYNC T2CLKCON — — — — MODE CS T2RST — — — — RSEL 400 401 399 402 T4TMR TMR4 380* T4PR PR4 380* T4CON ON T4HLT PSYNC CKPOL CKSYNC — — — — CS 399 — — — — RSEL 402 T4CLKCON T4RST Legend: * CKPS OUTPS MODE 400 401 — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2/4 module. Page provides register information.  2017-2021 Microchip Technology Inc. DS40001873E-page 403 PIC16(L)F19195/6/7 28.0 SIGNAL MEASUREMENT TIMER (SMT) The SMT is a 24-bit counter with advanced clock and gating logic, which can be configured for measuring a variety of digital signal parameters such as pulse width, frequency and duty cycle, and the time difference between edges on two signals. Features of the SMT include: • 24-bit timer/counter - Three 8-bit registers (SMTxTMRL/H/U) - Readable and writable - Optional 16-bit operating mode • Two 24-bit measurement capture registers • One 24-bit period match register • Multi-mode operation, including relative timing measurement • Interrupt on period match • Multiple clock, gate and signal sources • Interrupt on acquisition complete • Ability to read current input values  2017-2021 Microchip Technology Inc. DS40001873E-page 404 PIC16(L)F19195/6/7 FIGURE 28-1: SMTx BLOCK DIAGRAM Rev. 10-000161F 11/21/2016 Period Latch SMT_window SMT Clock Sync Circuit SMT_signal SMT Clock Sync Circuit Set SMTxPRAIF SMTxPR Control Logic Set SMTxIF Comparator Reset Enable Reserved 111 SOSC 110 MFINTOSC/16 101 MFINTOSC 100 LFINTOSC 011 HFINTOSC 010 FOSC 001 FOSC/4 000 SMTxTMR Window Latch 24-bit Buffer SMTxCPR 24-bit Buffer SMTxCPW Set SMTxPWAIF Prescaler CSEL FIGURE 28-2: SMTx SIGNAL AND WINDOW BLOCK DIAGRAM Rev. 10-000173C 1/20/2016 See SMTxSIG Register SMTxSIG  2017-2021 Microchip Technology Inc. SMT_signal See SMTxWIN Register SMT_window SMTxWIN DS40001873E-page 405 PIC16(L)F19195/6/7 28.1 Register Definitions: SMT Control Long bit name prefixes for the SMT peripherals are shown in Table 28-1. Refer to Section 1.1.2.2 “Long Bit Names” for more information. TABLE 28-1: Peripheral Bit Name Prefix SMT1 SMT1 REGISTER 28-1: SMTxCON0: SMT CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EN(1) — STP WPOL SPOL CPOL R/W-0/0 bit 7 R/W-0/0 SMTxPS bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EN: SMT Enable bit(1) 1 = SMT is enabled 0 = SMT is disabled; internal states are reset, clock requests are disabled bit 6 Unimplemented: Read as ‘0’ bit 5 STP: SMT Counter Halt Enable bit When SMTxTMR = SMTxPR: 1 = Counter remains SMTxPR; period match interrupt occurs when clocked 0 = Counter resets to 24'h000000; period match interrupt occurs when clocked bit 4 WPOL: SMTxWIN Input Polarity Control bit 1 = SMTxWIN signal is active-low/falling edge enabled 0 = SMTxWIN signal is active-high/rising edge enabled bit 3 SPOL: SMTxSIG Input Polarity Control bit 1 = SMTx_signal is active-low/falling edge enabled 0 = SMTx_signal is active-high/rising edge enabled bit 2 CPOL: SMT Clock Input Polarity Control bit 1 = SMTxTMR increments on the falling edge of the selected clock signal 0 = SMTxTMR increments on the rising edge of the selected clock signal bit 1-0 SMTxPS: SMT Prescale Select bits 11 = Prescaler = 1:8 10 = Prescaler = 1:4 01 = Prescaler = 1:2 00 = Prescaler = 1:1 Note 1: Setting EN to ‘0‘ does not affect the register contents.  2017-2021 Microchip Technology Inc. DS40001873E-page 406 PIC16(L)F19195/6/7 REGISTER 28-2: SMTxCON1: SMT CONTROL REGISTER 1 R/W/HC-0/0 R/W-0/0 U-0 U-0 SMTxGO REPEAT — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SMTxGO: SMT GO Data Acquisition bit 1 = Incrementing, acquiring data is enabled 0 = Incrementing, acquiring data is disabled bit 6 REPEAT: SMT Repeat Acquisition Enable bit 1 = Repeat Data Acquisition mode is enabled 0 = Single Acquisition mode is enabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 MODE SMT Operation Mode Select bits 1111 = Reserved • • • 1011 = Reserved 1010 = Windowed counter 1001 = Gated counter 1000 = Counter 0111 = Capture 0110 = Time of flight 0101 = Gated windowed measure 0100 = Windowed measure 0011 = High and low time measurement 0010 = Period and Duty-Cycle Acquisition 0001 = Gated Timer 0000 = Timer  2017-2021 Microchip Technology Inc. DS40001873E-page 407 PIC16(L)F19195/6/7 REGISTER 28-3: SMTxSTAT: SMT STATUS REGISTER R/W/HC-0/0 R/W/HC-0/0 R/W/HC-0/0 U-0 U-0 R-0/0 R-0/0 R-0/0 CPRUP CPWUP RST — — TS WS AS bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 CPRUP: SMT Manual Period Buffer Update bit 1 = Request update to SMTxCPRx registers 0 = SMTxCPRx registers update is complete bit 6 CPWUP: SMT Manual Pulse Width Buffer Update bit 1 = Request update to SMTxCPW registers 0 = SMTxCPW registers update is complete bit 5 RST: SMT Manual Timer Reset bit 1 = Request Reset to SMTxTMR registers 0 = SMTxTMR registers update is complete bit 4-3 Unimplemented: Read as ‘0’ bit 2 TS: SMT GO Value Status bit 1 = SMT timer is incrementing 0 = SMT timer is not incrementing bit 1 WS: SMTxWIN Value Status bit 1 = SMT window is open 0 = SMT window is closed bit 0 AS: SMT_signal Value Status bit 1 = SMT acquisition is in progress 0 = SMT acquisition is not in progress  2017-2021 Microchip Technology Inc. DS40001873E-page 408 PIC16(L)F19195/6/7 REGISTER 28-4: SMTxCLK: SMT CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/0 R/W-0/0 R/W-0/0 CSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CSEL: SMT Clock Selection bits 111 = Reserved 110 = SOSC 101 = MFINTOSC/16 (31.25 kHz) 100 = MFINTOSC (500 kHz) 011 = LFINTOSC 010 = HFINTOSC 001 = FOSC 000 = FOSC/4  2017-2021 Microchip Technology Inc. DS40001873E-page 409 PIC16(L)F19195/6/7 REGISTER 28-5: SMTxWIN: SMTx WINDOW INPUT SELECT REGISTER U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 WSEL: SMTx Window Selection bits 11111 = Reserved • • • 10011 = Reserved 10010 = RTCC_Seconds 10001 = CLC4OUT 10000 = CLC3OUT 01111 = CLC2OUT 01110 = CLC1OUT 01101 = ZCDOUT 01100 = C2OUT 01011 = C1OUT 01010 = PWM4_out 01001 = PWM3_out 01000 = CCP1OUT 00111 = CCP1OUT 00110 = TMR4_postscaler 00101 = TMR2_postscaler 00100 = TMR0_overflow 00011 = SOSC 00010 = MFINTOSC/16 (31.25 kHz) 00001 = LFINTOSC (31 kHz) 00000 = SMTWINx pin  2017-2021 Microchip Technology Inc. DS40001873E-page 410 PIC16(L)F19195/6/7 REGISTER 28-6: SMTxSIG: SMTx SIGNAL INPUT SELECT REGISTER U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 SSEL: SMTx Signal Selection bits 11111 = Reserved • • • 10001 = Reserved 10000 = RTCC_Seconds 01111 = CLC4OUT 01110 = CLC3OUT 01101 = CLC2OUT 01100 = CLC1OUT 01011 = ZCDOUT 01010 = C2OUT 01001 = C1OUT 01000 = PWM4_out 00111 = PWM3_out 00110 = CCP2OUT 00101 = CCP1OUT 00100 = TMR4_postscaler 00011 = TMR2_postscaler 00010 = TMR1_overflow 00001 = TMR0_overflow 00000 = SMTSIG pin  2017-2021 Microchip Technology Inc. DS40001873E-page 411 PIC16(L)F19195/6/7 REGISTER 28-7: R/W-0/0 SMTxTMRL: SMT TIMER REGISTER – LOW BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMTxTMR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxTMR: Significant bits of the SMT Counter – Low Byte REGISTER 28-8: R/W-0/0 SMTxTMRH: SMT TIMER REGISTER – HIGH BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMTxTMR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxTMR: Significant bits of the SMT Counter – High Byte REGISTER 28-9: R/W-0/0 SMTxTMRU: SMT TIMER REGISTER – UPPER BYTE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SMTxTMR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxTMR: Significant bits of the SMT Counter – Upper Byte  2017-2021 Microchip Technology Inc. DS40001873E-page 412 PIC16(L)F19195/6/7 REGISTER 28-10: SMTxCPRL: SMT CAPTURED PERIOD REGISTER – LOW BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxCPR: Significant bits of the SMT Period Latch – Low Byte REGISTER 28-11: SMTxCPRH: SMT CAPTURED PERIOD REGISTER – HIGH BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxCPR: Significant bits of the SMT Period Latch – High Byte REGISTER 28-12: SMTxCPRU: SMT CAPTURED PERIOD REGISTER – UPPER BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxCPR: Significant bits of the SMT Period Latch – Upper Byte  2017-2021 Microchip Technology Inc. DS40001873E-page 413 PIC16(L)F19195/6/7 REGISTER 28-13: SMTxCPWL: SMT CAPTURED PULSE WIDTH REGISTER – LOW BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPW bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxCPW: Significant bits of the SMT PW Latch – Low Byte REGISTER 28-14: SMTxCPWH: SMT CAPTURED PULSE WIDTH REGISTER – HIGH BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPW bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxCPW: Significant bits of the SMT PW Latch – High Byte REGISTER 28-15: SMTxCPWU: SMT CAPTURED PULSE WIDTH REGISTER – UPPER BYTE R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x R-x/x SMTxCPW bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxCPW: Significant bits of the SMT PW Latch – Upper Byte  2017-2021 Microchip Technology Inc. DS40001873E-page 414 PIC16(L)F19195/6/7 REGISTER 28-16: SMTxPRL: SMT PERIOD REGISTER – LOW BYTE R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 SMTxPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxPR: Significant bits of the SMT Timer Value for Period Match – Low Byte REGISTER 28-17: SMTxPRH: SMT PERIOD REGISTER – HIGH BYTE R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 SMTxPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxPR: Significant bits of the SMT Timer Value for Period Match – High Byte REGISTER 28-18: SMTxPRU: SMT PERIOD REGISTER – UPPER BYTE R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 R/W-x/1 SMTxPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SMTxPR: Significant bits of the SMT Timer Value for Period Match – Upper Byte  2017-2021 Microchip Technology Inc. DS40001873E-page 415 PIC16(L)F19195/6/7 28.2 SMT Operation The core of the module is the 24-bit counter, SMTxTMR combined with a complex data acquisition front-end. Depending on the mode of operation selected, the SMT can perform a variety of measurements summarized in Table . 28.2.1 CLOCK SOURCES Clock sources available to the SMT include: • • • • • • FOSC FOSC/4 HFINTOSC MFINTOSC (500 kHz and 31.25 kHz) LFINTOSC SOSC The SMT clock source is selected by configuring the CSEL bits in the SMTxCLK register. The clock source can also be prescaled using the PS bits of the SMTxCON0 register. The prescaled clock source is used to clock both the counter and any synchronization logic used by the module. 28.2.2 PERIOD MATCH INTERRUPT Similar to other timers, the SMT triggers an interrupt when SMTxTMR rolls over to ‘0’. This happens when SMTxTMR = SMTxPR, regardless of mode. Hence, in any mode that relies on an external signal or a window to reset the timer, proper operation requires that SMTxPR be set to a period larger than that of the expected signal or window. 28.3 Basic Timer Function Registers The SMTxTMR time base and the SMTxCPW/SMTxPR/SMTxCPR buffer registers serve several functions and can be manually updated using software. 28.3.1 TIME BASE The SMTxTMR is the 24-bit counter that is the center of the SMT. It is used as the basic counter/timer for measurement in each of the modes of the SMT. It can be reset to a value of 24'h00_0000 by setting the RST bit of the SMTxSTAT register. It can be written to and read from software, but it is not guarded for atomic access, therefore reads and writes to the SMTxTMR should only be made when the GO = 0, or the software should have other measures to ensure integrity of SMTxTMR reads/writes. 28.3.2 PULSE-WIDTH LATCH REGISTERS The SMTxCPW registers are the 24-bit SMT pulse width latch. They are used to latch in the value of the SMTxTMR when triggered by various signals, which are determined by the mode the SMT is currently in.  2017-2021 Microchip Technology Inc. The SMTxCPW registers can also be updated with the current value of the SMTxTMR value by setting the CPWUP bit of the SMTxSTAT register. 28.3.3 PERIOD LATCH REGISTERS The SMTxCPR registers are the 24-bit SMT period latch. They are used to latch in values of the SMTxTMR when triggered by various other signals, which are determined by the mode the SMT is currently in. The SMTxCPR registers can also be updated with the current value of the SMTxTMR value by setting the CPRUP bit in the SMTxSTAT register. 28.4 Halt Operation The counter can be prevented from rolling-over using the STP bit in the SMTxCON0 register. When halting is enabled, the period match interrupt persists until the SMTxTMR is reset (either by a manual Reset, Section 28.3.1 “Time Base”) or by clearing the SMTxGO bit of the SMTxCON1 register and writing the SMTxTMR values in software. 28.5 Polarity Control The three input signals for the SMT have polarity control to determine whether or not they are active high/positive edge or active low/negative edge signals. The following bits apply to Polarity Control: • WSEL bit (Window Polarity) • SSEL bit (Signal Polarity) • CSEL bit (Clock Polarity) These bits are located in the SMTxCON0 register. 28.6 Status Information The SMT provides input status information for the user without requiring the need to deal with the polarity of the incoming signals. 28.6.1 WINDOW STATUS Window status is determined by the WS bit of the SMTxSTAT register. This bit is only used in Windowed Measure, Gated Counter and Gated Window Measure modes, and is only valid when TS = 1, and will be delayed in time by synchronizer delays in non-Counter modes. 28.6.2 SIGNAL STATUS Signal status is determined by the AS bit of the SMTxSTAT register. This bit is used in all modes except Window Measure, Time of Flight and Capture modes, and is only valid when TS = 1, and will be delayed in time by synchronizer delays in non-Counter modes. DS40001873E-page 416 PIC16(L)F19195/6/7 28.6.3 GO STATUS 28.7.1 Timer run status is determined by the TS bit of the SMTxSTAT register, and will be delayed in time by synchronizer delays in non-Counter modes. 28.7 Timer mode is the simplest mode of operation where the SMTxTMR is used as a 16/24-bit timer. No data acquisition takes place in this mode. The timer increments as long as the SMTxGO bit has been set by software. No SMT window or SMT signal events affect the SMTxGO bit. Everything is synchronized to the SMT clock source. When the timer experiences a period match (SMTxTMR = SMTxPR), SMTxTMR is reset and the period match interrupt trips. See Figure 28-3. Modes of Operation The modes of operation are summarized in Table 28-2. The following sections provide detailed descriptions, examples of how the modes can be used. Note that all waveforms assume WPOL/SPOL/CPOL = 0. When WPOL/SPOL/CPOL = 1, all SMTSIGx, SMTWINx and SMT clock signals will have a polarity opposite to that indicated. For all modes, the REPEAT bit controls whether the acquisition is repeated or single. When REPEAT = 0 (Single Acquisition mode), the timer will stop incrementing and the SMTxGO bit will be reset upon the completion of an acquisition. Otherwise, the timer will continue and allow for continued acquisitions to overwrite the previous ones until the timer is stopped in software. TABLE 28-2: TIMER MODE MODES OF OPERATION MODE Mode of Operation Synchronous Operation Reference 0000 Timer Yes Section 28.7.1 “Timer Mode” 0001 Gated Timer Yes Section 28.7.2 “Gated Timer Mode” 0010 Period and Duty Cycle Acquisition Yes Section 28.7.3 “Period and Duty-Cycle Mode” 0011 High and Low Time Measurement Yes Section 28.7.4 “High and Low-Measure Mode” 0100 Windowed Measurement Yes Section 28.7.5 “Windowed Measure Mode” 0101 Gated Windowed Measurement Yes Section 28.7.6 “Gated Window Measure Mode” 0110 Time of Flight Yes Section 28.7.7 “Time of Flight Measure Mode” 0111 Capture Yes Section 28.7.8 “Capture Mode” 1000 Counter No Section 28.7.9 “Counter Mode” 1001 Gated Counter No Section 28.7.10 “Gated Counter Mode” 1010 Windowed Counter No Section 28.7.11 “Windowed Counter Mode” Reserved — 1011-1111  2017-2021 Microchip Technology Inc. — DS40001873E-page 417 TIMER MODE TIMING DIAGRAM Rev. 10-000 174A 12/19/201 3 SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR SMTxIF 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 PIC16(L)F19195/6/7 DS40001873E-page 418 FIGURE 28-3:  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 28.7.2 GATED TIMER MODE Gated Timer mode uses the SMTSIGx input to control whether or not the SMTxTMR will increment. Upon a falling edge of the external signal, the SMTxCPW register will update to the current value of the SMTxTMR. Example waveforms for both repeated and single acquisitions are provided in Figure 28-4 and Figure 28-5.  2017-2021 Microchip Technology Inc. DS40001873E-page 419 GATED TIMER MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 176A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR SMTxCPW SMTxPWAIF 0xFFFFFF 0 1 2 3 4 5 6 5 7 7 PIC16(L)F19195/6/7 DS40001873E-page 420 FIGURE 28-4:  2017-2021 Microchip Technology Inc.  2017-2021 Microchip Technology Inc. FIGURE 28-5: GATED TIMER MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 175A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR SMTxCPW 0xFFFFFF 0 1 2 3 4 5 5 SMTxPWAIF PIC16(L)F19195/6/7 DS40001873E-page 421 PIC16(L)F19195/6/7 28.7.3 PERIOD AND DUTY-CYCLE MODE In Duty-Cycle mode, either the duty cycle or period (depending on polarity) of the SMTx_signal can be acquired relative to the SMT clock. The CPW register is updated on a falling edge of the signal, and the CPR register is updated on a rising edge of the signal, along with the SMTxTMR resetting to 0x0001. In addition, the SMTxGO bit is reset on a rising edge when the SMT is in Single Acquisition mode. See Figure 28-6 and Figure 28-7.  2017-2021 Microchip Technology Inc. DS40001873E-page 422  2017-2021 Microchip Technology Inc. FIGURE 28-6: PERIOD AND DUTY-CYCLE REPEAT ACQUISITION MODE TIMING DIAGRAM Rev. 10-000 177A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPW SMTxCPR 0 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 5 2 11 SMTxPWAIF DS40001873E-page 423 PIC16(L)F19195/6/7 SMTxPRAIF PERIOD AND DUTY-CYCLE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 178A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPW SMTxCPR SMTxPWAIF SMTxPRAIF 0 1 2 3 4 5 6 7 8 9 10 11 5 11 PIC16(L)F19195/6/7 DS40001873E-page 424 FIGURE 28-7:  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 28.7.4 HIGH AND LOW-MEASURE MODE This mode measures the high and low-pulse time of the SMTSIGx relative to the SMT clock. It begins incrementing the SMTxTMR on a rising edge on the SMTSIGx input, then updates the SMTxCPW register with the value and resets the SMTxTMR on a falling edge, starting to increment again. Upon observing another rising edge, it updates the SMTxCPR register with its current value and once again resets the SMTxTMR value and begins incrementing again. See Figure 28-8 and Figure 28-9.  2017-2021 Microchip Technology Inc. DS40001873E-page 425 HIGH AND LOW-MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 180A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPW SMTxCPR SMTxPWAIF SMTxPRAIF 0 1 2 3 4 5 1 2 3 4 5 6 1 2 1 2 3 5 2 6 PIC16(L)F19195/6/7 DS40001873E-page 426 FIGURE 28-8:  2017-2021 Microchip Technology Inc.  2017-2021 Microchip Technology Inc. FIGURE 28-9: HIGH AND LOW-MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 179A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPW SMTxCPR 0 1 2 3 4 5 1 2 3 4 5 6 5 6 SMTxPWAIF DS40001873E-page 427 PIC16(L)F19195/6/7 SMTxPRAIF PIC16(L)F19195/6/7 28.7.5 WINDOWED MEASURE MODE Windowed Measure mode measures the window duration of the SMTWINx input of the SMT. It begins incrementing the timer on a rising edge of the SMTWINx input and updates the SMTxCPR register with the value of the timer and resets the timer on a second rising edge. See Figure 28-10 and Figure 28-11.  2017-2021 Microchip Technology Inc. DS40001873E-page 428  2017-2021 Microchip Technology Inc. FIGURE 28-10: WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 182A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPR 0 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 12 5 6 7 8 1 2 3 4 8 SMTxPRAIF PIC16(L)F19195/6/7 DS40001873E-page 429 WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 181A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPR SMTxPRAIF 0 1 2 3 4 5 6 7 8 9 10 11 12 12 PIC16(L)F19195/6/7 DS40001873E-page 430 FIGURE 28-11:  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 28.7.6 GATED WINDOW MEASURE MODE Gated Window Measure mode measures the duty cycle of the SMTx_signal input over a known input window. It does so by incrementing the timer on each pulse of the clock signal while the SMTx_signal input is high, updating the SMTxCPR register and resetting the timer on every rising edge of the SMTWINx input after the first. See Figure 28-12 and Figure 28-13.  2017-2021 Microchip Technology Inc. DS40001873E-page 431 GATED WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 184A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPR SMTxPRAIF 0 1 2 3 4 5 6 0 1 6 2 3 0 3 PIC16(L)F19195/6/7 DS40001873E-page 432 FIGURE 28-12:  2017-2021 Microchip Technology Inc.  2017-2021 Microchip Technology Inc. FIGURE 28-13: GATED WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAMS Rev. 10-000 183A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR SMTxCPR 1 2 3 4 5 6 6 DS40001873E-page 433 PIC16(L)F19195/6/7 SMTxPRAIF 0 PIC16(L)F19195/6/7 28.7.7 TIME OF FLIGHT MEASURE MODE Time of Flight Measure mode measures the time interval between a rising edge on the SMTWINx input and a rising edge on the SMTx_signal input, beginning to increment the timer upon observing a rising edge on the SMTWINx input, while updating the SMTxCPR register and resetting the timer upon observing a rising edge on the SMTx_signal input. In the event of two SMTWINx rising edges without an SMTx_signal rising edge, it will update the SMTxCPW register with the current value of the timer and reset the timer value. See Figure 28-14 and Figure 28-15.  2017-2021 Microchip Technology Inc. DS40001873E-page 434  2017-2021 Microchip Technology Inc. FIGURE 28-14: TIME OF FLIGHT MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000186A 4/22/2016 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 1 SMTxCPW SMTxPWAIF SMTxPRAIF 3 4 5 6 7 8 9 10 11 12 13 1 2 13 4 DS40001873E-page 435 PIC16(L)F19195/6/7 SMTxCPR 2 TIME OF FLIGHT MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000185A 4/26/2016 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 SMTxCPW SMTxCPR SMTxPWAIF  2017-2021 Microchip Technology Inc. SMTxPRAIF 4 PIC16(L)F19195/6/7 DS40001873E-page 436 FIGURE 28-15: PIC16(L)F19195/6/7 28.7.8 CAPTURE MODE Capture mode captures the Timer value based on a rising or falling edge on the SMTWINx input and triggers an interrupt. This mimics the capture feature of a CCP module. The timer begins incrementing upon the SMTxGO bit being set, and updates the value of the SMTxCPR register on each rising edge of SMTWINx, and updates the value of the CPW register on each falling edge of the SMTWINx. The timer is not reset by any hardware conditions in this mode and must be reset by software, if desired. See Figure 28-16 and Figure 28-17.  2017-2021 Microchip Technology Inc. DS40001873E-page 437 CAPTURE MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000 188A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SMTxCPW SMTxCPR SMTxPWAIF SMTxPRAIF 3 2 19 18 32 31 PIC16(L)F19195/6/7 DS40001873E-page 438 FIGURE 28-16:  2017-2021 Microchip Technology Inc.  2017-2021 Microchip Technology Inc. FIGURE 28-17: CAPTURE MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000 187A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 SMTxCPW SMTxCPR SMTxPRAIF 2 DS40001873E-page 439 PIC16(L)F19195/6/7 SMTxPWAIF 3 PIC16(L)F19195/6/7 28.7.9 COUNTER MODE Counter mode increments the timer on each pulse of the SMTx_signal input. This mode is asynchronous to the SMT clock and uses the SMTx_signal as a time source. The SMTxCPW register will be updated with the current SMTxTMR value on the rising edge of the SMTxWIN input. See Figure 28-18.  2017-2021 Microchip Technology Inc. DS40001873E-page 440  2017-2021 Microchip Technology Inc. FIGURE 28-18: COUNTER MODE TIMING DIAGRAM Rev. 10-000189A 4/12/2016 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR SMTxCPW 0 1 2 3 4 5 6 7 8 27 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 12 25 PIC16(L)F19195/6/7 DS40001873E-page 441 PIC16(L)F19195/6/7 28.7.10 GATED COUNTER MODE Gated Counter mode counts pulses on the SMTx_signal input, gated by the SMTxWIN input. It begins incrementing the timer upon seeing a rising edge of the SMTxWIN input and updates the SMTxCPW register upon a falling edge on the SMTxWIN input. See Figure 28-19 and Figure 28-20.  2017-2021 Microchip Technology Inc. DS40001873E-page 442  2017-2021 Microchip Technology Inc. FIGURE 28-19: GATED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM Rev. 10-000190A 12/18/2013 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 SMTxCPW 9 10 11 12 8 13 13 SMTxPWAIF FIGURE 28-20: GATED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM Rev. 10-000191A 12/18/2013 SMTx_signal SMTxEN SMTxGO SMTxTMR DS40001873E-page 443 SMTxCPW SMTxPWAIF 0 1 2 3 4 5 6 7 8 8 PIC16(L)F19195/6/7 SMTxWIN PIC16(L)F19195/6/7 28.7.11 WINDOWED COUNTER MODE Windowed Counter mode counts pulses on the SMTx_signal input, within a window dictated by the SMTxWIN input. It begins counting upon seeing a rising edge of the SMTxWIN input, updates the SMTxCPW register on a falling edge of the SMTxWIN input, and updates the SMTxCPR register on each rising edge of the SMTxWIN input beyond the first. See Figure 28-21 and Figure 28-22.  2017-2021 Microchip Technology Inc. DS40001873E-page 444  2017-2021 Microchip Technology Inc. FIGURE 28-21: WINDOWED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 SMTxCPW 2 3 5 4 9 5 SMTxCPR 16 SMTxPWAIF SMTxPRAIF FIGURE 28-22: WINDOWED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM SMTxWIN SMTxEN SMTxGO SMTxTMR SMTxCPW DS40001873E-page 445 SMTxCPR SMTxPWAIF SMTxPRAIF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 9 16 PIC16(L)F19195/6/7 SMTx_signal PIC16(L)F19195/6/7 28.8 Interrupts tively. The SMTxCPR interrupt is controlled by the SMTxPRAIF and SMTxPRAIE bits, also located in registers PIR8 and PIE8, respectively. The SMT can trigger an interrupt under three different conditions: In Synchronous SMT modes, the interrupt trigger is synchronized to the SMTxCLK. In Asynchronous modes, the interrupt trigger is asynchronous. In either mode, once triggered, the interrupt will be synchronized to the CPU clock. • PW Acquisition Complete • PR Acquisition Complete • Counter Period Match The interrupts are controlled by the PIR8 and PIE8 registers of the device. 28.8.1 28.8.2 PW AND PR ACQUISITION INTERRUPTS As described in Section 28.2.2 “Period Match interrupt”, the SMT will also interrupt upon SMTxTMR, matching SMTxPR with its period match limit functionality described in Section 28.4 “Halt Operation”. The period match interrupt is controlled by SMTxIF and SMTxIE. The SMT can trigger interrupts whenever it updates the SMTxCPW and SMTxCPR registers, the circumstances for which are dependent on the SMT mode, and are discussed in each mode’s specific section. The SMTxCPW interrupt is controlled by SMTxPWAIF and SMTxPWAIE bits in registers PIR8 and PIE8, respec- TABLE 28-3: Name COUNTER PERIOD MATCH INTERRUPT SUMMARY OF REGISTERS ASSOCIATED WITH SMTx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PIE8 LCDIE RTCCIE — — — PIR8 LCDIF RTCCIF — — — SMT1CLK — — — — — SMT1CON0 EN — STP WPOL SPOL SMT1CON1 SMT1GO REPEAT — — Bit 0 Register on Page SMT1PWAIE SMT1PRAIE SMT1IE 156 SMT1PWAIF SMT1IF 165 Bit 2 Bit 1 SMT1PRAIF CSEL CPOL 409 SMT1PS MODE 406 407 SMT1CPRH SMT1CPR 413 SMT1CPRL SMT1CPR 413 SMT1CPRU SMT1CPR 413 SMT1CPWH SMT1CPW 414 SMT1CPWL SMT1CPW 414 SMT1CPWU SMT1CPW 414 SMT1PRH SMT1PR 415 SMT1PRL SMT1PR 415 SMT1PRU SMT1PR SMT1SIG SMT1STAT — — — CPRUP CPWUP RST 415 SSEL — — TS 411 WS AS 408 SMT1TMRH SMT1TMR 412 SMT1TMRL SMT1TMR 412 SMT1TMRU SMT1TMR SMT1WIN Legend: — — — 412 WSEL 410 x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for SMTx module.  2017-2021 Microchip Technology Inc. DS40001873E-page 446 PIC16(L)F19195/6/7 29.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. The Capture/Compare/PWM modules available are shown in Table 29-1. TABLE 29-1: AVAILABLE CCP MODULES Device PIC16(L)F19195/6/7 CCP1 CCP2 ● ● The Capture and Compare functions are identical for all CCP modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required.  2017-2021 Microchip Technology Inc. DS40001873E-page 447 PIC16(L)F19195/6/7 29.1 Capture Mode Figure 29-1 shows a simplified diagram of the capture operation. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the capture source, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCPxMODE bits of the CCPxCON register: • • • • 29.1.1 In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Note: Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge If the CCPx pin is configured as an output, a write to the port can cause a capture condition. The capture source is selected by configuring the CCPxCTS bits of the CCPxCAP register. The following sources can be selected: • • • • • • • • When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIR6 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. FIGURE 29-1: CAPTURE SOURCES CCPxPPS input C1OUT_sync C2OUT_sync IOC_interrupt LC1_out LC2_out LC3_out LC4_out CAPTURE MODE OPERATION BLOCK DIAGRAM Rev. 10-000158F 9/1/2015 RxyPPS CCPx CTS TRIS Control CCPx LC4_out 111 LC3_out 110 LC2_out 101 LC1_out 100 IOC_interrupt 011 C2OUT_sync 010 C1OUT_sync 001 PPS 000 CCPRxH CCPRxL 16 Prescaler 1,4,16 set CCPxIF and Edge Detect 16 MODE TMR1H TMR1L CCPxPPS  2017-2021 Microchip Technology Inc. DS40001873E-page 448 PIC16(L)F19195/6/7 29.1.2 TIMER1 MODE RESOURCE 29.1.5 CAPTURE DURING SLEEP Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. See Section 26.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. 29.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIE6 register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIR6 register following any change in Operating mode. Note: 29.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP PRESCALER There are four prescaler settings specified by the CCPxMODE bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 29-1 demonstrates the code to perform this function. EXAMPLE 29-1: Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 29.2 Compare Mode Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate an Auto-conversion Trigger Generate a Software Interrupt The action on the pin is based on the value of the CCPxMODE control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set, and an ADC conversion can be triggered, if selected. All Compare modes can generate an interrupt and trigger and ADC conversion. Figure 29-2 shows a simplified diagram of the compare operation. FIGURE 29-2: COMPARE MODE OPERATION BLOCK DIAGRAM CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW MOVWF ;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value CCPxMODE Mode Select BANKSEL CCPxCON Set CCPxIF Interrupt Flag (PIR6) 4 CCPRxH CCPRxL CCPx Pin Q S R Output Logic Match Comparator TMR1H TRIS Output Enable TMR1L Auto-conversion Trigger  2017-2021 Microchip Technology Inc. DS40001873E-page 449 PIC16(L)F19195/6/7 29.2.1 CCPX PIN CONFIGURATION The software must configure the CCPx pin as an output by clearing the associated TRIS bit and defining the appropriate output pin through the RxyPPS registers. See Section 15.0 “Peripheral Pin Select (PPS) Module” for more details. The CCP output can also be used as an input for other peripherals. Note: 29.2.2 Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. TIMER1 MODE RESOURCE In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 26.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. Note: 29.2.3 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. AUTO-CONVERSION TRIGGER All CCPx modes set the CCP interrupt flag (CCPxIF). When this flag is set and a match occurs, an Auto-conversion Trigger can take place if the CCP module is selected as the conversion trigger source. Refer to Section 19.2.5 “Auto-Conversion Trigger” for more information. Note: 29.2.4 Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring COMPARE DURING SLEEP Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the timer is running. The device will wake on interrupt (if enabled). 29.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 29-3 shows a typical waveform of the PWM signal. 29.3.1 STANDARD PWM OPERATION The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • PR2 registers T2CON registers CCPRxL registers CCPxCON registers Figure 29-4 shows a simplified block diagram of PWM operation. Note: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. FIGURE 29-3: CCP PWM OUTPUT SIGNAL Period Pulse Width TMR2 = PR2 TMR2 = CCPRxH:CCPRxL TMR2 = 0  2017-2021 Microchip Technology Inc. DS40001873E-page 450 PIC16(L)F19195/6/7 FIGURE 29-4: SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000 157C 9/5/201 4 Duty cycle registers CCPRxH CCPRxL CCPx_out set CCPIF 10-bit Latch(2) (Not accessible by user) Comparator R PPS Q RxyPPS S TMR2 Module R TMR2 To Peripherals CCPx TRIS Control (1) ERS logic Comparator CCPx_pset PR2 29.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register, and the CCPRxH register with the PWM duty cycle value and configure the CCPxFMT bit of the CCPxCON register to set the proper register alignment. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR4 register. See Note below. • Configure the CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the Timer2 ON bit of the T2CON register.  2017-2021 Microchip Technology Inc. 6. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR4 register is set. See Note below. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: 29.3.3 In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. CCP/PWM CLOCK SELECTION The PIC16(L)F19195/6/7 allows each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. DS40001873E-page 451 PIC16(L)F19195/6/7 29.3.4 TIMER2 TIMER RESOURCE This device has a newer version of the Timer2 module that has many new modes, which allow for greater customization and control of the PWM signals than on older parts. Refer to Section 27.5 “Operation Examples” for examples of PWM signal generation using the different modes of Timer2. The CCP operation requires that the timer used as the PWM time base has the FOSC/4 clock source selected 29.3.5 FIGURE 29-5: PWM 10-BIT ALIGNMENT Rev. 10-000 160A 12/9/201 3 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 PWM PERIOD 10-bit Duty Cycle The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 29-1. EQUATION 29-1: PWM PERIOD PWM Period =   PR2  + 1   4  T OSC  9 8 7 6 5 4 3 2 1 0 EQUATION 29-2: • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is transferred from the CCPRxL/H register pair into a 10-bit buffer. 29.3.6 T OSC  (TMR2 Prescale Value) TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: Note: PULSE WIDTH Pulse Width =  CCPRxH:CCPRxL register pair   (TMR2 Prescale Value) Note 1: FMT = 0 EQUATION 29-3: DUTY CYCLE RATIO CCPRxH:CCPRxL register pair Duty Cycle Ratio = --------------------------------------------------------------------------------4  PR2 + 1  CCPRxH:CCPRxL register pair are used to double buffer the PWM duty cycle. This double buffering provides for glitchless PWM operation. The Timer postscaler (see Section 27.4 “Timer2/4 Interrupt”) is not used in the determination of the PWM frequency. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. PWM DUTY CYCLE When the 10-bit time base matches the CCPRxH:CCPRxL register pair, then the CCPx pin is cleared (see Figure 29-4). The PWM duty cycle is specified by writing a 10-bit value to the CCPRxH:CCPRxL register pair. The alignment of the 10-bit value is determined by the CCPRxFMT bit of the CCPxCON register (see Figure 29-5). The CCPRxH:CCPRxL register pair can be written to at any time; however the duty cycle value is not latched into the 10-bit buffer until after a match between PR2 and TMR2. Equation 29-2 is used to calculate the PWM pulse width. Equation 29-3 is used to calculate the PWM duty cycle ratio. 29.3.7 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 29-4. EQUATION 29-4: PWM RESOLUTION log  4  PR2 + 1  - bits Resolution = ----------------------------------------log  2  Note:  2017-2021 Microchip Technology Inc. If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged. DS40001873E-page 452 PIC16(L)F19195/6/7 TABLE 29-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Timer Prescale PR2 Value Maximum Resolution (bits) TABLE 29-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz Timer Prescale PR2 Value 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 29.3.8 4.90 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 29.3.9 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 9.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 29.3.10 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states.  2017-2021 Microchip Technology Inc. DS40001873E-page 453 PIC16(L)F19195/6/7 29.4 Register Definitions: CCP Control Long bit name prefixes for the CCP peripherals are shown in Section 1.1 “Register and Bit Naming Conventions”. TABLE 29-4: LONG BIT NAMES PREFIXES FOR CCP PERIPHERALS Peripheral Bit Name Prefix CCP1 CCP1 CCP2 CCP2 REGISTER 29-1: CCPxCON: CCPx CONTROL REGISTER R/W-0/0 U-0 R-x R/W-0/0 EN — OUT FMT R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EN: CCPx Module Enable bit 1 = CCPx is enabled 0 = CCPx is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 OUT: CCPx Output Data bit (read-only) bit 4 FMT: CCPW (Pulse Width) Alignment bit MODE = Capture mode Unused MODE = Compare mode Unused MODE = PWM mode 1 = Left-aligned format 0 = Right-aligned format  2017-2021 Microchip Technology Inc. DS40001873E-page 454 PIC16(L)F19195/6/7 REGISTER 29-1: bit 3-0 Note 1: CCPxCON: CCPx CONTROL REGISTER (CONTINUED) MODE: CCPx Mode Select bits(1) 1111 = PWM mode 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = 1010 = 1001 = 1000 = Compare mode: output will pulse 0-1-0; Clears TMR1 Compare mode: output will pulse 0-1-0 Compare mode: clear output on compare match Compare mode: set output on compare match 0111 = 0110 = 0101 = 0100 = Capture mode: every 16th rising edge of CCPx input Capture mode: every 4th rising edge of CCPx input Capture mode: every rising edge of CCPx input Capture mode: every falling edge of CCPx input 0011 = 0010 = 0001 = 0000 = Capture mode: every edge of CCPx input Compare mode: toggle output on match Compare mode: toggle output on match; clear TMR1 Capture/Compare/PWM off (resets CCPx module) All modes will set the CCPxIF bit, and will trigger an ADC conversion if CCPx is selected as the ADC trigger source.  2017-2021 Microchip Technology Inc. DS40001873E-page 455 PIC16(L)F19195/6/7 REGISTER 29-2: CCPxCAP: CAPTURE INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/x R/W-0/x R/W-0/x CTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 CTS: Capture Trigger Input Selection bits CTS CCP1.capture 1000 RTCC_seconds 0111 LC4_out 0110 LC3_out 0101 LC2_out 0100 LC1_out 0011 IOC_interrupt 0010 C2OUT 0001 C1OUT 0000 REGISTER 29-3: R/W-x/x CCP2.capture CCP1PPS CCP2PPS CCPRxL REGISTER: CCPx REGISTER LOW BYTE R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x CCPRx bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 CCPxMODE = Capture mode CCPRxL: Capture value of TMR1L CCPxMODE = Compare mode CCPRxL: LS Byte compared to TMR1L CCPxMODE = PWM modes when CCPxFMT = 0: CCPRxL: Pulse-width Least Significant eight bits CCPxMODE = PWM modes when CCPxFMT = 1: CCPRxL: Pulse-width Least Significant two bits CCPRxL: Not used.  2017-2021 Microchip Technology Inc. DS40001873E-page 456 PIC16(L)F19195/6/7 REGISTER 29-4: R/W-x/x CCPRxH REGISTER: CCPx REGISTER HIGH BYTE R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x CCPRx bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 CCPxMODE = Capture mode CCPRxH: Captured value of TMR1H CCPxMODE = Compare mode CCPRxH: MS Byte compared to TMR1H CCPxMODE = PWM modes when CCPxFMT = 0: CCPRxH: Not used CCPRxH: Pulse-width Most Significant two bits CCPxMODE = PWM modes when CCPxFMT = 1: CCPRxH: Pulse-width Most Significant eight bits REGISTER 29-5: R/W-0/0 CCPTMRS0: CCP TIMERS CONTROL 0 REGISTER R/W-1/1 R/W-0/0 P4TSEL R/W-1/1 P3TSEL R/W-0/0 R/W-1/1 R/W-0/0 C2TSEL bit 7 R/W-1/1 C1TSEL bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 P4TSEL: PWM4 Timer Selection bit 11 = Reserved 10 = PWM4 based on TMR4 01 = PWM4 based on TMR2 00 = Reserved bit 5-4 P3TSEL: PWM3 Timer Selection bit 11 = Reserved 10 = PWM3 based on TMR4 01 = PWM3 based on TMR2 00 = Reserved bit 3-2 C2TSEL: CCP2 Timer Selection bit 11 = Reserved 10 = CCP2 based on TMR1 (Capture/Compare) or TMR4 (PWM) 01 = CCP2 based on TMR1 (Capture/Compare) or TMR2 (PWM) 00 = Reserved bit 1-0 C1TSEL: CCP1 Timer Selection bit 11 = Reserved 10 = CCP1 based on TMR1 (Capture/Compare) or TMR4 (PWM) 01 = CCP1 based on TMR1 (Capture/Compare) or TMR2 (PWM) 00 = Reserved  2017-2021 Microchip Technology Inc. DS40001873E-page 457 PIC16(L)F19195/6/7 TABLE 29-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH CCPx Bit 7 Bit 6 Bit 5 Bit 4 GIE PEIE — — — — PIE4 — — CCP1CON EN — — — — — INTCON PIR4 CCP1CAP Bit 3 Bit 2 — — — TMR4IF — — TMR4IE OUT FMT CCPR1L Capture/Compare/PWM Register 1 (LSB) CCPR1H Capture/Compare/PWM Register 1 (MSB) CCP2CON CCP2CAP OUT FMT — — — — CCPR2H Capture/Compare/PWM Register 1 (MSB) — — INTEDG 147 — TMR2IF TMR1IF 161 — TMR2IE TMR1IE MODE — 152 454 CTS 456 457 — Capture/Compare/PWM Register 1 (LSB) Bit 0 456 EN CCPR2L Register on Page Bit 1 MODE — 454 CTS 456 456 456 CCPTMRS0 P4TSEL P3TSEL C2TSEL C1TSEL CCP1PPS — — — CCP1PPS 457 259 CCP2PPS — — — CCP2PPS 259 RxyPPS — — — RxyPPS 260 ADACT — — — ACT 319 CLCxSELy — — — LCxDyS 499 CWG1ISM — — — Legend: — IS 488 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCPx module.  2017-2021 Microchip Technology Inc. DS40001873E-page 458 PIC16(L)F19195/6/7 30.0 PULSE-WIDTH MODULATION (PWM) The PWMx modules generate Pulse-Width Modulated (PWM) signals of varying frequency and duty cycle. In addition to the CCP modules, the PIC16(L)F19195/6/7 devices contain two PWM modules (PWM3 and PWM4). The PWM modules reproduce the PWM capability of the CCP modules. Note: The PWM3/4 modules are four instances of the same PWM module design. Throughout this section, the lower case ‘x’ in register and bit names is a generic reference to the PWM module number (which should be substituted with 3, or 4 during code development). For example, the control register is generically described in this chapter as PWMxCON, but the actual device registers are PWM3CON and PWM4CON. Similarly, the PWMxEN bit represents the PWM3EN and PWM4EN bits. FIGURE 30-1: Q1 PWM OUTPUT Q2 Q3 Q4 Rev. 10-000023C 8/26/2015 FOSC PWM Pulse Width TMRx = 0 TMRx = PWMxDC TMRx = PRx (1) (1) (1) Note 1: Timer dependent on PWMTMRS register settings. Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully ON and fully OFF states. The PWM signal resembles a square wave where the high portion of the signal is considered the ‘ON’ state (pulse width), and the low portion of the signal is considered the ‘OFF’ state. The term duty cycle describes the proportion of the ‘on’ time to the ‘off’ time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and, in turn, the power that is applied to the load. Figure 30-1 shows a typical waveform of the PWM signal.  2017-2021 Microchip Technology Inc. DS40001873E-page 459 PIC16(L)F19195/6/7 30.1 Standard PWM Mode The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the PWMx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • • Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the PWMx pin. 2: Two identical Timer2 modules are implemented on this device. The timers are named Timer2 and Timer4. All references to Timer2 apply as well to Timer4. All references to T2PR apply as well to T4PR. TMR2 register PR2 register PWMxCON registers PWMxDCH registers PWMxDCL registers Figure 30-2 shows a simplified block diagram of PWM operation. If PWMPOL = 0, the default state of the output is ‘0‘. If PWMPOL = 1, the default state is ‘1’. If PWMEN = 0, the output will be the default state. FIGURE 30-2: SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000022B 9/24/2014 PWMxDCL Duty cycle registers PWMxDCH PWMx_out 10-bit Latch (Not visible to user) R Comparator Q 0 1 S To Peripherals PPS PWMx Q TMR2 Module TMR2 R PWMxPOL (1) Comparator RxyPPS TRIS Control T2_match PR2 Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base.  2017-2021 Microchip Technology Inc. DS40001873E-page 460 PIC16(L)F19195/6/7 30.1.1 PWM CLOCK SELECTION The PIC16(L)F19195/6/7 allows each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. 30.1.2 USING THE TMR2 WITH THE PWM MODULE This device has a newer version of the TMR2 module that has many new modes, which allow for greater customization and control of the PWM signals than on older parts. Refer to Section 27.5 “Operation Examples” for examples of PWM signal generation using the different modes of Timer2. Note: 30.1.3 PWM operation requires that the timer used as the PWM time base has the FOSC/4 clock source selected. PWM PERIOD Referring to Figure 30-1, the PWM output has a period and a pulse width. The frequency of the PWM is the inverse of the period (1/period). The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: EQUATION 30-1: 30.1.4 The PWM duty cycle is specified by writing a 10-bit value to the PWMxDC register. The PWMxDCH contains the eight MSbs and the PWMxDCL bits contain the two LSbs. The PWMDC register is double-buffered and can be updated at any time. This double buffering is essential for glitch-free PWM operation. New values take effect when TMR2 = PR2. Note that PWMDC is left-justified. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. Equation 30-2 is used to calculate the PWM pulse width. Equation 30-3 is used to calculate the PWM duty cycle ratio. EQUATION 30-2: Note 1: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The PWMx pin is set (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM pulse width is latched from PWMxDC. EQUATION 30-3: If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged.  2017-2021 Microchip Technology Inc. DUTY CYCLE RATIO ‫ ݋݅ݐܴ݈ܽ݁ܿݕܥݕݐݑܦ‬ൌ  30.1.5 ሺܹܲ‫ܥܦݔܯ‬ሻ  Ͷሺܴܲʹ ൅ ͳሻ PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 30-4. EQUATION 30-4: Note: PULSE WIDTH Pulse Widthൌሺܹܲ‫ܥܦݔܯ‬ሻ  ή ܱܶܵ‫ ܥ‬ή ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ PWM PERIOD ܹܲ‫ ݀݋݅ݎ݁ܲܯ‬ൌ  ሾሺܴܲʹሻ  ൅ ͳሿ  ή Ͷ ή ܱܶܵ‫ܥ‬ ή  ሺܶ‫݁ݑ݈ܸ݈ܽ݁ܽܿݏ݁ݎܲʹܴܯ‬ሻ PWM DUTY CYCLE PWM RESOLUTION log  4  PR2 + 1   Resolution = ------------------------------------------ bits log  2  DS40001873E-page 461 PIC16(L)F19195/6/7 30.1.6 OPERATION IN SLEEP MODE 30.1.7 To operate in Sleep, TMR2 must be configured to use a clock source which is active during Sleep. Otherwise, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the timer clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 9.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 30.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWMx registers to their Reset states. TABLE 30-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Timer Prescale PR2 Value Maximum Resolution (bits) TABLE 30-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Timer Prescale PR2 Value Maximum Resolution (bits) 30.1.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the module for using the PWMx outputs: 1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). 2. Configure the PWM output polarity by configuring the PWMxPOL bit of the PWMxCON register. 3. Load the PR2 register with the PWM period value, as determined by Equation 30-1. 4. Load the PWMxDCH register and bits of the PWMxDCL register with the PWM duty cycle value, as determined by Equation 30-2. 5. Configure and start Timer2: - Clear the TMR2IF interrupt flag bit of the PIR4 register. - Select the Timer2 prescale value by configuring the CKPS bits of the T2CON register. - Enable Timer2 by setting the Timer2 ON bit of the T2CON register.  2017-2021 Microchip Technology Inc. 6. 7. Wait until the TMR2IF is set. When the TMR2IF flag bit is set: - Clear the associated TRIS bit(s) to enable the output driver. - Route the signal to the desired pin by configuring the RxyPPS register. - Enable the PWMx module by setting the PWMxEN bit of the PWMxCON register. In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then the PWM module can be enabled during Step 2 by setting the PWMxEN bit of the PWMxCON register. DS40001873E-page 462 PIC16(L)F19195/6/7 30.2 Register Definitions: PWM Control REGISTER 30-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 U-0 R-0 R/W-0/0 U-0 U-0 U-0 U-0 PWMxEN — PWMxOUT PWMxPOL — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PWMxEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 PWMxOUT: PWM Module Output Level when Bit is Read bit 4 PWMxPOL: PWMx Output Polarity Select bit 1 = PWM output is active-low 0 = PWM output is active-high bit 3-0 Unimplemented: Read as ‘0’  2017-2021 Microchip Technology Inc. DS40001873E-page 463 PIC16(L)F19195/6/7 REGISTER 30-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDC: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register. REGISTER 30-3: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — PWMxDC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PWMxDC: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register. bit 5-0 Unimplemented: Read as ‘0’  2017-2021 Microchip Technology Inc. DS40001873E-page 464 PIC16(L)F19195/6/7 TABLE 30-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH PWMx Bit 7 T2CON Bit 6 ON Bit 5 Bit 4 Bit 3 Bit 2 CKPS T2TMR Bit 1 Bit 0 OUTPS Register on Page 400 Holding Register for the 8-bit TMR2 Register 380* TMR2 Period Register 380* T2PR RxyPPS ― ― — RxyPPS CWG1ISM — — — CLCxSELy — — TRISA TRISA7 TRISA6 — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 205 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 219 — 260 IS 488 LCxDyS 499 Legend: - = Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWMx module. *Page provides register information.  2017-2021 Microchip Technology Inc. DS40001873E-page 465 PIC16(L)F19195/6/7 31.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms. It is backwards compatible with previous ECCP functions. The CWG has the following features: • Six Operating modes: - Synchronous Steering mode - Asynchronous Steering mode - Full-Bridge mode, Forward - Full-Bridge mode, Reverse - Half-Bridge mode - Push-Pull mode • Output Polarity Control • Output Steering: - Synchronized to rising event - Immediate effect • Independent 6-Bit Rising and Falling Event DeadBand Timers: - Clocked dead band - Independent rising and falling dead-band enables • Auto-Shutdown Control with: - Selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control 31.1 Fundamental Operation The CWG module can operate in six different modes, as specified by MODE of the CWG1CON0 register: • Half-Bridge mode (Figure 31-9) • Push-Pull mode (Figure 31-2) - Full-Bridge mode, Forward (Figure 31-3) - Full-Bridge mode, Reverse (Figure 31-3) • Steering mode (Figure 31-10) • Synchronous Steering mode (Figure 31-11) It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. Thus, all output modes support auto-shutdown, which is covered in Section 31.10 “Auto-Shutdown”. 31.1.1 HALF-BRIDGE MODE In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 31-9. A non-overlap (dead-band) time is inserted between the two outputs as described in Section 31.5 “Dead-Band Control”. The unused outputs CWG1C and CWG1D drive similar signals, with polarity independently controlled by the POLC and POLD bits of the CWG1CON1 register, respectively. The CWG modules available are shown in Table 31-1. TABLE 31-1: AVAILABLE CWG MODULES Device PIC16(L)F19195/6/7  2017-2021 Microchip Technology Inc. CWG1 ● DS40001873E-page 466  2017-2021 Microchip Technology Inc. FIGURE 31-1: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE) Rev. 10-000166B 8/29/2014 CWG_data Rising Deadband Block See CWGxISM Register CWG_dataA clock signal_out CWG_dataC signal_in D Q CWGxISM E R Q Falling Deadband Block CWG_dataB clock signal_out EN SHUTDOWN HFINTOSC 1 FOSC 0 CWGxCLK CWG_dataD DS40001873E-page 467 PIC16(L)F19195/6/7 signal_in PIC16(L)F19195/6/7 31.1.2 PUSH-PULL MODE In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 31-2. This alternation creates the push-pull effect required for driving some transformer-based power supply designs. The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWG1A. The unused outputs CWG1C and CWG1D drive copies of CWG1A and CWG1B, respectively, but with polarity controlled by the POLC and POLD bits of the CWG1CON1 register, respectively. 31.1.3 FULL-BRIDGE MODES In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the input data signal. In Forward Full-Bridge mode, CWG1A is driven to its active state, CWG1B and CWG1C are driven to their inactive state, and CWG1D is modulated by the input signal. In Reverse Full-Bridge mode, CWG1C is driven to its active state, CWG1A and CWG1D are driven to their inactive states, and CWG1B is modulated by the input signal. In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice-versa. This dead-band control is described in Section 31.5 “Dead-Band Control”, with additional details in Section 31.6 “Rising Edge and Reverse Dead Band” and Section 31.7 “Falling Edge and Forward Dead Band”. The mode selection may be toggled between forward and reverse toggling the MODE bit of the CWG1CON0 while keeping MODE static, without disabling the CWG module.  2017-2021 Microchip Technology Inc. DS40001873E-page 468  2017-2021 Microchip Technology Inc. FIGURE 31-2: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE) Rev. 10-000167B 8/29/2014 CWG_data See CWGxISM Register D Q CWG_dataA Q CWG_dataC R CWG_dataB D Q CWG_dataD CWGxISM E R Q EN DS40001873E-page 469 PIC16(L)F19195/6/7 SHUTDOWN SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES) Rev. 10-000165B 8/29/2014 Reverse Deadband Block MODE0 clock signal_out See CWGxISM Register signal_in CWG_dataA D D Q Q CWG_dataB Q CWG_dataC CWGxISM E R CWG_dataD Q clock signal_out signal_in Forward Deadband Block EN CWG_data SHUTDOWN HFINTOSC FOSC  2017-2021 Microchip Technology Inc. CWGxCLK 1 0 PIC16(L)F19195/6/7 DS40001873E-page 470 FIGURE 31-3: PIC16(L)F19195/6/7 31.1.4 STEERING MODES In Steering modes, the data input can be steered to any or all of the four CWG output pins. In Synchronous Steering mode, changes to steering selection registers take effect on the next rising input. In Non-Synchronous mode, steering takes effect on the next instruction cycle. Additional details are provided in Section 31.9 “CWG Steering Mode”. FIGURE 31-4: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES) Rev. 10-000164B 8/26/2015 See CWGxISM Register CWG_dataA CWG_data CWG_dataB CWG_dataC CWG_dataD D Q CWGxISM E R Q EN SHUTDOWN 31.2 Clock Source The CWG module allows the following clock sources to be selected: • Fosc (system clock) • HFINTOSC (16 MHz only) The clock sources are selected using the CS bit of the CWG1CLKCON register.  2017-2021 Microchip Technology Inc. DS40001873E-page 471 PIC16(L)F19195/6/7 31.3 Selectable Input Sources The CWG generates the output waveforms from the input sources (See Register 31-9). The input sources are selected using the CWG1ISM register. 31.4 31.4.1 Output Control POLARITY CONTROL The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the POLx bits of the CWG1CON1. Auto-shutdown and steering options are unaffected by polarity.  2017-2021 Microchip Technology Inc. DS40001873E-page 472 PIC16(L)F19195/6/7 FIGURE 31-5: CWG OUTPUT BLOCK DIAGRAM Rev. 10-000171B 9/24/2014 LSAC CWG_dataA 1 POLA OVRA ‘1’ 11 ‘0’ 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 PPS CWGxA STRA(1) LSBD CWG_dataB 1 POLB OVRB ‘1’ 11 ‘0’ 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 PPS CWGxB STRB(1) LSAC CWG_dataC 1 POLC OVRC ‘1’ 11 ‘0’ 10 High Z 01 00 0 RxyPPS TRIS Control 1 0 PPS CWGxC STRC(1) LSBD CWG_dataD 1 POLD OVRD ‘1’ 11 ‘0’ 10 High Z 01 0 00 RxyPPS TRIS Control 1 0 PPS CWGxD STRD(1) CWG_shutdown Note 1: STRx is held to 1 in all modes other than Output Steering Mode.  2017-2021 Microchip Technology Inc. DS40001873E-page 473 PIC16(L)F19195/6/7 31.5 Dead-Band Control The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM switches. Dead-band operation is employed for HalfBridge and Full-Bridge modes. The CWG contains two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge mode or for reverse dead-band Full-Bridge mode. The other is used for the falling edge of the input source control in Half-Bridge mode or for forward dead band in FullBridge mode. Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. See CWG1DBR and CWG1DBF registers, respectively. 31.5.1 DEAD-BAND FUNCTIONALITY IN HALF-BRIDGE MODE In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the rising edge of the inverted output. This can be seen in Figure 31-9. 31.5.2 DEAD-BAND FUNCTIONALITY IN FULL-BRIDGE MODE In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE bit of the CWG1CON0 register can be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWG1A and CWG1C signals will change upon the first rising input edge following a direction change, but the modulated signals (CWG1B or CWG1D, depending on the direction of the change) will experience a delay dictated by the deadband counters. This is demonstrated in Figure 31-3.  2017-2021 Microchip Technology Inc. 31.6 Rising Edge and Reverse Dead Band CWG1DBR controls the rising edge dead-band time at the leading edge of CWG1A (Half-Bridge mode) or the leading edge of CWG1B (Full-Bridge mode). The CWG1DBR value is double-buffered. When EN = 0, the CWG1DBR register is loaded immediately when CWG1DBR is written. When EN = 1, then software must set the LD bit of the CWG1CON0 register, and the buffer will be loaded at the next falling edge of the CWG input signal. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. 31.7 Falling Edge and Forward Dead Band CWG1DBF controls the dead-band time at the leading edge of CWG1B (Half-Bridge mode) or the leading edge of CWG1D (Full-Bridge mode). The CWG1DBF value is double-buffered. When EN = 0, the CWG1DBF register is loaded immediately when CWG1DBF is written. When EN = 1 then software must set the LD bit of the CWG1CON0 register, and the buffer will be loaded at the next falling edge of the CWG input signal. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. Refer to Figure 31-6 and Figure 31-7 for examples. DS40001873E-page 474  2017-2021 Microchip Technology Inc. FIGURE 31-6: DEAD-BAND OPERATION CWG1DBR = 0X01, CWG1DBF = 0X02 cwg_clock Input Source CWG1A CWG1B FIGURE 31-7: DEAD-BAND OPERATION, CWG1DBR = 0X03, CWG1DBF = 0X04, SOURCE SHORTER THAN DEAD BAND Input Source CWG1A CWG1B source shorter than dead band DS40001873E-page 475 PIC16(L)F19195/6/7 cwg_clock PIC16(L)F19195/6/7 31.8 Dead-Band Uncertainty EQUATION 31-1: When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates uncertainty in the dead-band time delay. The maximum uncertainty is equal to one CWG clock period. Refer to Equation 31-1 for more details. DEAD-BAND UNCERTAINTY 1 TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock Example: FCWG_CLOCK = 16 MHz Therefore: 1 TDEADBAND_UNCERTAINTY = ---------------------------Fcwg_clock 1 = ----------------16MHz = 62.5ns FIGURE 31-8: EXAMPLE OF PWM DIRECTION CHANGE MODE0 CWG1A CWG1B CWG1C CWG1D No delay CWG1DBR No delay CWG1DBF CWG1_data Note 1: WGPOL{ABCD} = 0 2: The direction bit MODE (Register 31-1) can be written any time during the PWM cycle, and takes effect at the next rising CWG1_data. 3: When changing directions, CWG1A and CWG1C switch at rising CWG1_data; modulated CWG1B and CWG1D are held inactive for the dead band duration FIGURE 31-9: CWG HALF-BRIDGE MODE OPERATION CWG1_clock CWG1A CWG1C Falling Event Dead Band Rising Event Dead Band Rising Event D Falling Event Dead Band CWG1B CWG1D CWG1_data Note: CWG1_rising_src = CCP1_out, CWG1_falling_src = ~CCP1_out  2017-2021 Microchip Technology Inc. DS40001873E-page 476 PIC16(L)F19195/6/7 31.9 CWG Steering Mode 31.9.1 In Steering mode (MODE = 00x), the CWG allows any combination of the CWG1x pins to be the modulated signal. The same signal can be simultaneously available on multiple pins, or a fixed-value output can be presented. When the respective STRx bit of CWG1OCON0 is ‘0’, the corresponding pin is held at the level defined. When the respective STRx bit of CWG1OCON0 is ‘1’, the pin is driven by the input data signal. The user can assign the input data signal to one, two, three, or all four output pins. The POLx bits of the CWG1CON1 register control the signal polarity only when STRx = 1. The CWG auto-shutdown operation also applies in Steering modes as described in Section 31.10 “AutoShutdown”. An auto-shutdown event will only affect pins that have STRx = 1. FIGURE 31-10: STEERING SYNCHRONIZATION Changing the MODE bits allows for two modes of steering, synchronous and asynchronous. When MODE = 000, the steering event is asynchronous and will happen at the end of the instruction that writes to STRx (that is, immediately). In this case, the output signal at the output pin may be an incomplete waveform. This can be useful for immediately removing a signal from the pin. When MODE = 001, the steering update is synchronous and occurs at the beginning of the next rising edge of the input data signal. In this case, steering the output on/off will always produce a complete waveform. Figure 31-10 and Figure 31-11 illustrate the timing of asynchronous and synchronous steering, respectively. EXAMPLE OF ASYNCHRONOUS STEERING EVENT (MODE = 000) Rising Event CWG1_data (Rising and Falling Source) STR CWG1 OVR Data OVR follows CWG1_data FIGURE 31-11: EXAMPLE OF STEERING EVENT (MODE = 001) CWG1_data (Rising and Falling Source) STR CWG1 OVR Data OVR Data follows CWG1_data  2017-2021 Microchip Technology Inc. DS40001873E-page 477 PIC16(L)F19195/6/7 31.10 Auto-Shutdown 31.11 Operation During Sleep Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. The auto-shutdown circuit is illustrated in Figure 31-12. The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. 31.10.1 • CWG module is enabled • Input source is active • HFINTOSC is selected as the clock source, regardless of the system clock source selected. SHUTDOWN The shutdown state can be entered by either of the following two methods: • Software generated • External input 31.10.1.1 Software Generated Shutdown Setting the SHUTDOWN bit of the CWG1AS0 register will force the CWG into the shutdown state. When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set. The HFINTOSC remains active during Sleep when all the following conditions are met: In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, then the CPU will go Idle during Sleep, but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current. When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. 31.10.2 EXTERNAL INPUT SOURCE External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. Several input sources can be selected to cause a shutdown condition. All input sources are active-low. The sources are: • • • • Comparator C1OUT_sync Comparator C2OUT_sync Timer2 – TMR2_postscaled CWG1IN input pin Shutdown inputs are selected using the CWG1AS1 register (Register 31-6). Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling autoshutdown, as long as the shutdown input level persists.  2017-2021 Microchip Technology Inc. DS40001873E-page 478  2017-2021 Microchip Technology Inc. FIGURE 31-12: CWG SHUTDOWN BLOCK DIAGRAM Write ‘1’ to SHUTDOWN bit Rev. 10-000172B 1/21/2015 PPS INAS CWGINPPS C1OUT_sync C1AS C2OUT_sync C2AS TMR2_postscaled TMR2AS TMR4_postscaled TMR4AS TMR6_postscaled TMR6AS S Q SHUTDOWN S D FREEZE REN Write ‘0’ to SHUTDOWN bit Q CWG_shutdown R CWG_data CK PIC16(L)F19195/6/7 DS40001873E-page 479 PIC16(L)F19195/6/7 31.12 Configuring the CWG 31.12.2 The following steps illustrate how to properly configure the CWG. After an auto-shutdown event has occurred, there are two ways to resume operation: 1. • Software controlled • Auto-restart 2. 3. 4. 5. Ensure that the TRIS control bits corresponding to the desired CWG pins for your application are set so that the pins are configured as inputs. Clear the EN bit, if not already cleared. Set desired mode of operation with the MODE bits. Set desired dead-band times, if applicable to mode, with the CWG1DBR and CWG1DBF registers. Setup the following controls in the CWG1AS0 and CWG1AS1 registers. a. Select the desired shutdown source. b. Select both output overrides to the desired levels (this is necessary even if not using autoshutdown because start-up will be from a shutdown state). c. Set which pins will be affected by auto-shutdown with the CWG1AS1 register. d. Set the SHUTDOWN bit and clear the REN bit. 6. 7. Select the desired input source using the CWG1ISM register. Configure the following controls. a. Select desired clock source CWG1CLKCON register. using the AUTO-SHUTDOWN RESTART The restart method is selected with the REN bit of the CWG1CON2 register. Waveforms of software controlled and automatic restarts are shown in Figure 31-13 and Figure 31-14. 31.12.2.1 Software Controlled Restart When the REN bit of the CWG1AS0 register is cleared, the CWG must be restarted after an auto-shutdown event by software. Clearing the shutdown state requires all selected shutdown inputs to be low, otherwise the SHUTDOWN bit will remain set. The overrides will remain in effect until the first rising edge event after the SHUTDOWN bit is cleared. The CWG will then resume operation. 31.12.2.2 Auto-Restart When the REN bit of the CWG1CON2 register is set, the CWG will restart from the auto-shutdown state automatically. The SHUTDOWN bit will clear automatically when all shutdown sources go low. The overrides will remain in effect until the first rising edge event after the SHUTDOWN bit is cleared. The CWG will then resume operation. b. Select the desired output polarities using the CWG1CON1 register. c. Set the output enables for the desired outputs. 8. 9. Set the EN bit. Clear TRIS control bits corresponding to the desired output pins to configure these pins as outputs. 10. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit to start the CWG. 31.12.1 PIN OVERRIDE LEVELS The levels driven to the output pins, while the shutdown input is true, are controlled by the LSBD and LSAC bits of the CWG1AS0 register. LSBD controls the CWG1B and D override levels and LSAC controls the CWG1A and C override levels. The control bit logic level corresponds to the output logic drive level while in the shutdown state. The polarity control does not affect the override level.  2017-2021 Microchip Technology Inc. DS40001873E-page 480  2017-2021 Microchip Technology Inc. FIGURE 31-13: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01) Shutdown Event Ceases REN Cleared by Software CWG Input Source Shutdown Source SHUTDOWN CWG1A CWG1C Tri-State (No Pulse) CWG1B CWG1D Tri-State (No Pulse) No Shutdown Output Resumes Shutdown FIGURE 31-14: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01) REN auto-cleared by hardware CWG Input Source Shutdown Source SHUTDOWN DS40001873E-page 481 CWG1A CWG1C Tri-State (No Pulse) CWG1B CWG1D Tri-State (No Pulse) No Shutdown Shutdown Output Resumes PIC16(L)F19195/6/7 Shutdown Event Ceases PIC16(L)F19195/6/7 31.13 Register Definitions: CWG Control Long bit name prefixes for the CWG peripherals are shown in Section 1.1 “Register and Bit Naming Conventions”. REGISTER 31-1: CWG1CON0: CWG1 CONTROL REGISTER 0 R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 EN LD(1) — — — R/W-0/0 R/W-0/0 R/W-0/0 MODE bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 EN: CWG1 Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 LD: CWG1 Load Buffer bits(1) 1 = Buffers to be loaded on the next rising/falling event 0 = Buffers not loaded bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 MODE: CWG1 Mode bits 111 = Reserved 110 = Reserved 101 = CWG outputs operate in Push-Pull mode 100 = CWG outputs operate in Half-Bridge mode 011 = CWG outputs operate in Reverse Full-Bridge mode 010 = CWG outputs operate in Forward Full-Bridge mode 001 = CWG outputs operate in Synchronous Steering mode 000 = CWG outputs operate in Steering mode Note 1: This bit can only be set after EN = 1 and cannot be set in the same instruction that EN is set.  2017-2021 Microchip Technology Inc. DS40001873E-page 482 PIC16(L)F19195/6/7 REGISTER 31-2: CWG1CON1: CWG1 CONTROL REGISTER 1 U-0 U-0 R-x U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IN — POLD POLC POLB POLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5 IN: CWG Input Value bit bit 4 Unimplemented: Read as ‘0’ bit 3 POLD: CWG1D Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 2 POLC: CWG1C Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 1 POLB: CWG1B Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 0 POLA: CWG1A Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity  2017-2021 Microchip Technology Inc. DS40001873E-page 483 PIC16(L)F19195/6/7 REGISTER 31-3: CWG1DBR: CWG1 RISING DEAD-BAND COUNTER REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 DBR: Rising Event Dead-Band Value for Counter bits REGISTER 31-4: CWG1DBF: CWG1 FALLING DEAD-BAND COUNTER REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 DBF: Falling Event Dead-Band Value for Counter bits  2017-2021 Microchip Technology Inc. DS40001873E-page 484 PIC16(L)F19195/6/7 REGISTER 31-5: CWG1AS0: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 0 R/W/HS-0/0 R/W-0/0 SHUTDOWN(1, 2) REN R/W-0/0 R/W-1/1 LSBD R/W-0/0 R/W-1/1 LSAC U-0 U-0 — — bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1, 2) 1 = An Auto-Shutdown state is in effect 0 = No Auto-shutdown event has occurred bit 6 REN: Auto-Restart Enable bit 1 = Auto-restart enabled 0 = Auto-restart disabled bit 5-4 LSBD: CWG1B and CWG1D Auto-Shutdown State Control bits 11 =A logic ‘1’ is placed on CWG1B/D when an auto-shutdown event is present 10 =A logic ‘0’ is placed on CWG1B/D when an auto-shutdown event is present 01 =Pin is tri-stated on CWG1B/D when an auto-shutdown event is present 00 =The inactive state of the pin, including polarity, is placed on CWG1B/D after the required deadband interval bit 3-2 LSAC: CWG1A and CWG1C Auto-Shutdown State Control bits 11 =A logic ‘1’ is placed on CWG1A/C when an auto-shutdown event is present 10 =A logic ‘0’ is placed on CWG1A/C when an auto-shutdown event is present 01 =Pin is tri-stated on CWG1A/C when an auto-shutdown event is present 00 =The inactive state of the pin, including polarity, is placed on CWG1A/C after the required deadband interval bit 1-0 Unimplemented: Read as ‘0’ Note 1: This bit may be written while EN = 0 (CWG1CON0 register) to place the outputs into the shutdown configuration. 2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is cleared.  2017-2021 Microchip Technology Inc. DS40001873E-page 485 PIC16(L)F19195/6/7 REGISTER 31-6: CWG1AS1: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 1 U-1 U-1 U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — AS4E AS3E AS2E AS1E AS0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 AS4E: CLC2 Output bit 1 = LC2_out shut-down is enabled 0 = LC2_out shut-down is disabled bit 3 AS3E: Comparator C2 Output bit 1 = C2 output shut-down is enabled 0 = C2 output shut-down is disabled bit 2 AS2E: Comparator C1 Output bit 1 = C1 output shut-down is enabled 0 = C1 output shut-down is disabled bit 2 AS1E: TMR2 Postscale Output bit 1 = TMR2 Postscale shut-down is enabled 0 = TMR2 Postscale shut-down is disabled bit 0 AS0E: CWG1 Input Pin bit 1 = Input pin selected by CWG1PPS shut-down is enabled 0 = Input pin selected by CWG1PPS shut-down is disabled  2017-2021 Microchip Technology Inc. DS40001873E-page 486 PIC16(L)F19195/6/7 CWG1STR: CWG1 STEERING CONTROL REGISTER(1) REGISTER 31-7: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 OVRD: Steering Data D bit bit 6 OVRC: Steering Data C bit bit 5 OVRB: Steering Data B bit bit 4 OVRA: Steering Data A bit bit 3 STRD: Steering Enable D bit(2) 1 = CWG1D output has the CWG1_data waveform with polarity control from POLD bit 0 = CWG1D output is assigned the value of OVRD bit bit 2 STRC: Steering Enable C bit(2) 1 = CWG1C output has the CWG1_data waveform with polarity control from POLC bit 0 = CWG1C output is assigned the value of OVRC bit bit 1 STRB: Steering Enable B bit(2) 1 = CWG1B output has the CWG1_data waveform with polarity control from POLB bit 0 = CWG1B output is assigned the value of OVRB bit bit 0 STRA: Steering Enable A bit(2) 1 = CWG1A output has the CWG1_data waveform with polarity control from POLA bit 0 = CWG1A output is assigned the value of OVRA bit Note 1: The bits in this register apply only when MODE = 00x. 2: This bit is effectively double-buffered when MODE = 001.  2017-2021 Microchip Technology Inc. DS40001873E-page 487 PIC16(L)F19195/6/7 REGISTER 31-8: CWG1CLK: CWG1 CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as ‘0’ bit 0 CS: CWG1 Clock Selection bit 1 = HFINTOSC 16 MHz is selected 0 = FOSC is selected REGISTER 31-9: CWG1ISM: CWG1 INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 IS: CWG1 Input Selection bits 1011-1111 = Reserved. No channel connected. 1010 = LC4_out 1001 = LC3_out 1000 = LC2_out 0111 = LC1_out 0110 = Comparator C2 out 0101 = Comparator C1 out 0100 = PWM4_out 0011 = PWM3_out 0010 = CCP2_out 0001 = CCP1_out 0000 = CWG11CLK  2017-2021 Microchip Technology Inc. DS40001873E-page 488 PIC16(L)F19195/6/7 TABLE 31-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWG Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CWG1CLKCON — — — — — — — CS 488 CWG1ISM — — — — CWG1DBR — — IS CWG1DBF — — CWG1CON0 EN LD — — — IN — POLD — — SHUTDOWN REN CWG1AS1 — — — AS4E AS3E CWG1STR OVRD OVRC OVRB OVRA STRD Legend: 484 DBF CWG1AS0 CWG1CON1 488 DBR LSBD 484 MODE POLC 482 POLB POLA — — 485 AS2E AS1E AS0E 486 STRC STRB STRA 487 LSAC 483 – = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.  2017-2021 Microchip Technology Inc. DS40001873E-page 489 PIC16(L)F19195/6/7 32.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) module provides programmable logic that operates outside the speed limitations of software execution. The logic cell selects from 40 input signals and, through the use of configurable gates, reduces the inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: • • • • I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. Refer to Figure 32-1 for a simplified diagram showing signal flow through the CLCx. Possible configurations include: • Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR • Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset The CLC modules available are shown in Table 32-1. TABLE 32-1: AVAILABLE CLC MODULES Device CLC1 CLC2 CLC3 CLC4 PIC16(L)F19195/6/7 Note: ● ● ● ● The CLC1, CLC2, CLC3 and CLC4 are four separate module instances of the same CLC module design. Throughout this section, the lower case ‘x’ in register and bit names is a generic reference to the CLC number (which should be substituted with 1, 2, 3, or 4 during code development). For example, the control register is generically described in this chapter as CLCxCON, but the actual device registers are CLC1CON, CLC2CON, CLC3CON and CLC4CON. Similarly, the LCxEN bit represents the LC1EN, LC2EN, LC3EN and LC4EN bits.  2017-2021 Microchip Technology Inc. DS40001873E-page 490 PIC16(L)F19195/6/7 FIGURE 32-1: CLCx SIMPLIFIED BLOCK DIAGRAM Rev. 10-000025H 11/9/2016 D OUT CLCxOUT Q Q1 . . . LCx_in[n-2] LCx_in[n-1] LCx_in[n] CLCx_out Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] EN lcxg1 lcxg2 lcxg3 to Peripherals CLCxPPS Logic lcxq Function PPS CLCx (2) lcxg4 POL MODE TRIS Interrupt det INTP INTN set bit CLCxIF Interrupt det Note 1: 2: See Figure 32-2: Input Data Selection and Gating See Figure 32-3: Programmable Logic Functions  2017-2021 Microchip Technology Inc. DS40001873E-page 491 PIC16(L)F19195/6/7 32.1 CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: TABLE 32-2: CLCx DATA INPUT SELECTION LCxDyS Value CLCx Input Source 100101 to 111111 Reserved 100100 EUSART2 (TX/CK) output 100011 EUSART2 (DT) output 100010 CWG1B output 100001 CWG1A output 100000 RTCC seconds 011111 MSSP1 SCK output 011110 MSSP1 SDO output 011101 EUSART1 (TX/CK) output 011100 EUSART1 (DT) output 011011 CLC4 output 011010 CLC3 output Data selection is through four multiplexers as indicated on the left side of Figure 32-2. Data inputs in the figure are identified by a generic numbered input name. 011001 CLC2 output 011000 CLC1 output 010111 IOCIF Table 32-2 correlates the generic input name to the actual signal for each CLC module. The column labeled ‘LCxDyS Value’ indicates the MUX selection code for the selected data input. LCxDyS is an abbreviation to identify specific multiplexers: LCxD1S through LCxD4S. 010110 ZCD output 010101 C2OUT 010100 C1OUT 010011 PWM4 output 010010 PWM3 output Data inputs are selected with CLCxSEL0 through CLCxSEL3 registers (Register 32-3 through Register 32-6). 010001 CCP2 output 010000 CCP1 output 001111 SMT overflow 001110 Timer4 overflow 001101 Timer2 overflow 001100 Timer1 overflow 001011 Timer0 overflow 001010 ADCRC 001001 SOSC 001000 MFINTOSC/16 (31.25 kHz) 000111 MFINTOSC (500 kHz) 000110 LFINTOSC 000101 HFINTOSC 000100 FOSC 000011 CLCIN3PPS 000010 CLCIN2PPS 000001 CLCIN1PPS 000000 CLCIN0PPS • • • • Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 32.1.1 DATA SELECTION There are 40 signals available as inputs to the configurable logic. Four 40-input multiplexers are used to select the inputs to pass on to the next stage.  2017-2021 Microchip Technology Inc. DS40001873E-page 492 PIC16(L)F19195/6/7 32.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND or all enabled inputs. Table 32-3 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. TABLE 32-3: CLCxGLSy DATA GATING LOGIC EXAMPLES LCxGyPOL Gate Logic 0x55 1 4-input AND 0x55 0 4-input NAND 0xAA 1 4-input NOR 0xAA 0 4-input OR 0x00 0 Logic 0 0x00 1 Logic 1 Data gating is indicated in the right side of Figure 32-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 32.1.3 LOGIC FUNCTION There are eight available logic functions including: • • • • • • • • AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 32-2. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. 32.1.4 OUTPUT POLARITY The last stage in the Configurable Logic Cell is the output polarity. Setting the LCxPOL bit of the CLCxPOL register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: • • • • Gate 1: CLCxGLS0 (Register 32-7) Gate 2: CLCxGLS1 (Register 32-8) Gate 3: CLCxGLS2 (Register 32-9) Gate 4: CLCxGLS3 (Register 32-10) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register.  2017-2021 Microchip Technology Inc. DS40001873E-page 493 PIC16(L)F19195/6/7 32.2 CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR5 register will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: • CLCxIE bit of the PIE5 register • LCxINTP bit of the CLCxCON register (for a rising edge detection) • LCxINTN bit of the CLCxCON register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The CLCxIF bit of the PIR5 register, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 32.3 Output Mirror Copies Mirror copies of all LCxCON output bits are contained in the CLCxDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the LCxOUT bits in the individual CLCxCON registers. 32.4 Effects of a Reset 32.6 CLCx Setup Steps The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 through CLCxSEL3 registers (See Table 32-2). • Clear any associated ANSEL bits. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. • Select the gate output polarities with the LCxGyPOL bits of the CLCxPOL register. • Select the desired logic function with the LCxMODE bits of the CLCxCON register. • Select the desired polarity of the logic output with the LCxPOL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). • If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. • If interrupts are desired, configure the following bits: - Set the LCxINTP bit in the CLCxCON register for rising event. - Set the LCxINTN bit in the CLCxCON register for falling event. - Set the CLCxIE bit of the PIE5 register. - Set the GIE and PEIE bits of the INTCON register. • Enable the CLCx by setting the LCxEN bit of the CLCxCON register. The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 32.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go Idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.  2017-2021 Microchip Technology Inc. DS40001873E-page 494 PIC16(L)F19195/6/7 FIGURE 32-2: LCx_in INPUT DATA SELECTION AND GATING Data Selection Data GATE 1 lcxd1T LCxD1G1T lcxd1N LCxD1G1N LCx_in LCxD2G1T LCxD1S LCxD2G1N lcxg1 LCx_in LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCxD4G1T LCx_in LCxD2S LCxD4G1N LCx_in Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N Data GATE 3 LCx_in lcxg3 LCxD3S (Same as Data GATE 1) Data GATE 4 LCx_in lcxg4 lcxd4T (Same as Data GATE 1) lcxd4N LCx_in LCxD4S  2017-2021 Microchip Technology Inc. DS40001873E-page 495 PIC16(L)F19195/6/7 FIGURE 32-3: PROGRAMMABLE LOGIC FUNCTIONS Rev. 10-000122A 5/18/2016 AND-OR OR-XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxq lcxg3 lcxg3 lcxg4 lcxg4 LCxMODE = 000 LCxMODE = 001 4-input AND S-R Latch lcxg1 lcxg1 S Q lcxq Q lcxq lcxg2 lcxg2 lcxq lcxg3 lcxg3 R lcxg4 lcxg4 LCxMODE = 010 LCxMODE = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 R lcxg3 R lcxg3 LCxMODE = 100 LCxMODE = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 J Q lcxq lcxg2 D lcxg3 LE S Q lcxq lcxg1 lcxg4 K R lcxg3 R lcxg1 LCxMODE = 110  2017-2021 Microchip Technology Inc. LCxMODE = 111 DS40001873E-page 496 PIC16(L)F19195/6/7 32.7 Register Definitions: CLC Control REGISTER 32-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 LCxEN — LCxOUT LCxINTP LCxINTN R/W-0/0 R/W-0/0 R/W-0/0 LCxMODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxEN: Configurable Logic Cell Enable bit 1 = Configurable logic cell is enabled and mixing input signals 0 = Configurable logic cell is disabled and has logic zero output bit 6 Unimplemented: Read as ‘0’ bit 5 LCxOUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on CLCxOUT 0 = CLCxIF will not be set bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on CLCxOUT 0 = CLCxIF will not be set bit 2-0 LCxMODE: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K flip-flop with R 101 = Cell is 2-input D flip-flop with R 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR  2017-2021 Microchip Technology Inc. DS40001873E-page 497 PIC16(L)F19195/6/7 REGISTER 32-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: CLCxOUT Output Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as ‘0’ bit 3 LCxG4POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 2 LCxG3POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 1 LCxG2POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted bit 0 LCxG1POL: Gate 0 Output Polarity Control bit 1 = The output of gate 0 is inverted when applied to the logic cell 0 = The output of gate 0 is not inverted  2017-2021 Microchip Technology Inc. DS40001873E-page 498 PIC16(L)F19195/6/7 REGISTER 32-3: CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD1S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD1S: CLCx Data1 Input Selection bits See Table 32-2. REGISTER 32-4: CLCxSEL1: GENERIC CLCx DATA 1 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD2S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD2S: CLCx Data 2 Input Selection bits See Table 32-2. REGISTER 32-5: CLCxSEL2: GENERIC CLCx DATA 2 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD3S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD3S: CLCx Data 3 Input Selection bits See Table 32-2. REGISTER 32-6: CLCxSEL3: GENERIC CLCx DATA 3 SELECT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD4S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 LCxD4S: CLCx Data 4 Input Selection bits See Table 32-2.  2017-2021 Microchip Technology Inc. DS40001873E-page 499 PIC16(L)F19195/6/7 REGISTER 32-7: CLCxGLS0: GATE 0 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 0 0 = CLCIN3 (true) is not gated into CLCx Gate 0 bit 6 LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 0 0 = CLCIN3 (inverted) is not gated into CLCx Gate 0 bit 5 LCxG1D3T: Gate 0 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 0 0 = CLCIN2 (true) is not gated into CLCx Gate 0 bit 4 LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 0 0 = CLCIN2 (inverted) is not gated into CLCx Gate 0 bit 3 LCxG1D2T: Gate 0 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 0 0 = CLCIN1 (true) is not gated into l CLCx Gate 0 bit 2 LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 0 0 = CLCIN1 (inverted) is not gated into CLCx Gate 0 bit 1 LCxG1D1T: Gate 0 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 0 0 = CLCIN0 (true) is not gated into CLCx Gate 0 bit 0 LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 0 0 = CLCIN0 (inverted) is not gated into CLCx Gate 0  2017-2021 Microchip Technology Inc. DS40001873E-page 500 PIC16(L)F19195/6/7 REGISTER 32-8: CLCxGLS1: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 1 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 1 0 = CLCIN3 (true) is not gated into CLCx Gate 1 bit 6 LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 1 0 = CLCIN3 (inverted) is not gated into CLCx Gate 1 bit 5 LCxG2D3T: Gate 1 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 1 0 = CLCIN2 (true) is not gated into CLCx Gate 1 bit 4 LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 1 0 = CLCIN2 (inverted) is not gated into CLCx Gate 1 bit 3 LCxG2D2T: Gate 1 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 1 0 = CLCIN1 (true) is not gated into CLCx Gate 1 bit 2 LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 1 0 = CLCIN1 (inverted) is not gated into CLCx Gate 1 bit 1 LCxG2D1T: Gate 1 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 1 0 = CLCIN0 (true) is not gated into CLCx Gate1 bit 0 LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 1 0 = CLCIN0 (inverted) is not gated into CLCx Gate 1  2017-2021 Microchip Technology Inc. DS40001873E-page 501 PIC16(L)F19195/6/7 REGISTER 32-9: CLCxGLS2: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 2 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 2 0 = CLCIN3 (true) is not gated into CLCx Gate 2 bit 6 LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 2 0 = CLCIN3 (inverted) is not gated into CLCx Gate 2 bit 5 LCxG3D3T: Gate 2 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 2 0 = CLCIN2 (true) is not gated into CLCx Gate 2 bit 4 LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 2 0 = CLCIN2 (inverted) is not gated into CLCx Gate 2 bit 3 LCxG3D2T: Gate 2 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 2 0 = CLCIN1 (true) is not gated into CLCx Gate 2 bit 2 LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 2 0 = CLCIN1 (inverted) is not gated into CLCx Gate 2 bit 1 LCxG3D1T: Gate 2 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 2 0 = CLCIN0 (true) is not gated into CLCx Gate 2 bit 0 LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 2 0 = CLCIN0 (inverted) is not gated into CLCx Gate 2  2017-2021 Microchip Technology Inc. DS40001873E-page 502 PIC16(L)F19195/6/7 REGISTER 32-10: CLCxGLS3: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 3 Data 4 True (non-inverted) bit 1 = CLCIN3 (true) is gated into CLCx Gate 3 0 = CLCIN3 (true) is not gated into CLCx Gate 3 bit 6 LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit 1 = CLCIN3 (inverted) is gated into CLCx Gate 3 0 = CLCIN3 (inverted) is not gated into CLCx Gate 3 bit 5 LCxG4D3T: Gate 3 Data 3 True (non-inverted) bit 1 = CLCIN2 (true) is gated into CLCx Gate 3 0 = CLCIN2 (true) is not gated into CLCx Gate 3 bit 4 LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit 1 = CLCIN2 (inverted) is gated into CLCx Gate 3 0 = CLCIN2 (inverted) is not gated into CLCx Gate 3 bit 3 LCxG4D2T: Gate 3 Data 2 True (non-inverted) bit 1 = CLCIN1 (true) is gated into CLCx Gate 3 0 = CLCIN1 (true) is not gated into CLCx Gate 3 bit 2 LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit 1 = CLCIN1 (inverted) is gated into CLCx Gate 3 0 = CLCIN1 (inverted) is not gated into CLCx Gate 3 bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit 1 = CLCIN0 (true) is gated into CLCx Gate 3 0 = CLCIN0 (true) is not gated into CLCx Gate 3 bit 0 LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit 1 = CLCIN0 (inverted) is gated into CLCx Gate 3 0 = CLCIN0 (inverted) is not gated into CLCx Gate 3  2017-2021 Microchip Technology Inc. DS40001873E-page 503 PIC16(L)F19195/6/7 REGISTER 32-11: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 MLC4OUT: Mirror copy of LC4OUT bit bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit  2017-2021 Microchip Technology Inc. DS40001873E-page 504 PIC16(L)F19195/6/7 TABLE 32-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE ― ― ― ― ― INTEDG 147 PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — — — TMR1GIF 162 PIE5 CLC4IE CLC4IE CLC2IE CLC1IE — — — TMR1GIE CLC1CON LC1EN ― LC1OUT LC1INTP LC1INTN CLC1POL LC1POL ― ― ― LC1G4POL Name INTCON LC1MODE LC1G3POL LC1G2POL 153 497 LC1G1POL 498 CLC1SEL0 ― ― LC1D1S 499 CLC1SEL1 ― ― LC1D2S 499 CLC1SEL2 ― ― LC1D3S 499 CLC1SEL3 ― ― LC1D4S CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 500 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 501 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 502 CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 503 CLC2CON LC2EN ― LC2OUT LC2INTP LC2INTN CLC2POL LC2POL ― ― ― LC2G4POL 499 LC2MODE LC2G3POL LC2G2POL 497 LC2G1POL 498 CLC2SEL0 ― ― LC2D1S 499 CLC2SEL1 ― ― LC2D2S 499 CLC2SEL2 ― ― LC2D3S 499 CLC2SEL3 ― ― CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 500 CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 501 CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 502 CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 503 CLC3CON LC3EN ― LC3OUT LC3INTP LC3INTN CLC3POL LC3POL ― ― ― LC3G4POL CLC3SEL0 ― ― LC3D1S 499 CLC3SEL1 ― ― LC3D2S 499 CLC3SEL2 ― ― LC3D3S 499 CLC3SEL3 ― ― LC3D4S 499 CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 500 CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 501 CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 502 CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 503 CLC4CON LC4EN ― LC4OUT LC4INTP LC4INTN CLC4POL LC4POL ― ― ― LC4G4POL CLC4SEL0 ― ― LC4D1S 499 CLC4SEL1 ― ― LC4D2S 499 CLC4SEL2 ― ― LC4D3S 499 CLC4SEL3 ― ― LC4D4S 499 LC4G1D4T LC4G1D4N CLC4GLS0 Legend: LC2D4S LC4G1D3T LC4G1D3N LC4G1D2T 499 LC3MODE LC3G3POL LC3G2POL 497 LC3G1POL LC4MODE LC4G3POL LC4G1D2N LC4G2POL LC4G1D1T 498 497 LC4G1POL LC4G1D1N 498 500 — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.  2017-2021 Microchip Technology Inc. DS40001873E-page 505 PIC16(L)F19195/6/7 TABLE 32-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 501 CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 502 CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N CLCIN0PPS ― ― ― CLCIN0PPS 259 CLCIN1PPS ― ― ― CLCIN1PPS 259 CLCIN2PPS ― ― ― CLCIN2PPS 259 ― ― ― CLCIN3PPS 259 CLCIN3PPS Legend: 503 — = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.  2017-2021 Microchip Technology Inc. DS40001873E-page 506 PIC16(L)F19195/6/7 33.0 HOST SYNCHRONOUS SERIAL PORT (MSSP) MODULES 33.1 MSSP Module Overview The Host Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: • • • • • Host mode Client mode Clock Polarity Client Select Synchronization (Client mode only) Daisy-chain connection of client devices Figure 33-1 is a block diagram of the SPI interface module. FIGURE 33-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SSPDATPPS SDI PPS SSPSR Reg Shift Clock bit 0 SDO PPS RxyPPS SS SS Control Enable PPS SSPSSPPS Edge Select SSPCLKPPS(2) SCK SSPM 4 PPS PPS TRIS bit 2 (CKP, CKE) Clock Select RxyPPS(1) Edge Select ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) Note 1: Output selection for host mode 2: Input selection for client mode  2017-2021 Microchip Technology Inc. DS40001873E-page 507 PIC16(L)F19195/6/7 The I2C interface supports the following modes and features: • • • • • • • • • • • • Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names. SSPxCON1 and SSPxCON2 registers control different operational aspects of the same module, while SSPxCON1 and SSP2CON1 control the same features for two different modules. Host mode Client mode Byte NACKing (Client mode) Limited multi-host support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Selectable SDA hold times 2: Throughout this section, generic references to an MSSPx module in any of its operating modes may be interpreted as being equally applicable to MSSPx or MSSP2. Register names, module I/O signals, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module when required. Figure 33-2 is a block diagram of the I2C interface module in Host mode. Figure 33-3 is a diagram of the I2C interface module in Client mode. FIGURE 33-2: MSSP BLOCK DIAGRAM (I2C HOST MODE) Internal data bus SSPDATPPS(1) Read [SSPM] Write SDA SDA in PPS SSPxBUF Baud Rate Generator (SSPxADD) SSPCLKPPS SCL PPS LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) (Hold off clock source) (2) Receive Enable (RCEN) MSb Clock Cntl SSPSR PPS Clock arbitrate/BCOL detect Shift Clock RxyPPS(1) PPS RxyPPS(2) SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSPxIF, BCL1IF Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output  2017-2021 Microchip Technology Inc. DS40001873E-page 508 PIC16(L)F19195/6/7 FIGURE 33-3: MSSP BLOCK DIAGRAM (I2C CLIENT MODE) Internal Data Bus Read Write SSPCLKPPS(2) SCL PPS PPS SSPxBUF Reg Shift Clock Clock Stretching SSPSR Reg LSb MSb RxyPPS(2) SSPxMSK Reg (1) SSPDATPPS SDA Match Detect Addr Match PPS SSPxADD Reg PPS RxyPPS(1) Start and Stop bit Detect Set, Reset S, P bits (SSPxSTAT Reg) Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output  2017-2021 Microchip Technology Inc. DS40001873E-page 509 PIC16(L)F19195/6/7 33.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a host/client environment where the host device initiates the communication. A client device is controlled through a Chip Select known as Client Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Client Select (SS) Figure 33-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single host device and one or more client devices. When multiple client devices are used, an independent Client Select connection can be used to address each client individually. Figure 33-4 shows a typical connection between a host device and multiple client devices. The host selects only one client at a time. Most client devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the host and one in the client. Data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the host device is sending out the MSb from its shift register (on its SDO pin) and the client device is reading this bit and saving it as the LSb of its shift register, that the client device is also sending out the MSb from its shift register (on its SDO pin) and the host device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the host and client have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Host sends useful data and client sends dummy data. • Host sends useful data and client sends useful data. • Host sends dummy data and client sends useful data. Transmissions must be performed in multiples of eight clock pulses. When there is no more data to be transmitted, the host stops sending the clock signal and it deselects the client. Every client device connected to the bus that has not been selected through its client select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 33-5 shows a typical connection between two processors configured as host and client devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The host device transmits information out on its SDO output pin which is connected to, and received by, the client’s SDI input pin. The client device transmits information out on its SDO output pin, which is connected to, and received by, the host’s SDI input pin. To begin communication, the host device first sends out the clock signal. Both the host and the client devices should be configured for the same clock polarity. The host device starts a transmission by sending out the MSb from its shift register. The client device reads this bit from that same line and saves it into the LSb position of its shift register.  2017-2021 Microchip Technology Inc. DS40001873E-page 510 PIC16(L)F19195/6/7 FIGURE 33-4: SPI HOST AND MULTIPLE CLIENT CONNECTION SPI Host SCK SCK SDO SDI General I/O General I/O SDI General I/O SCK SDO SPI Client #1 SS SDI SDO SPI Client #2 SS SCK SDI SDO SPI Client #3 SS 33.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: • • • • • • MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPxSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. In one SPI host mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 33.7 “Baud Rate Generator”. SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR.  2017-2021 Microchip Technology Inc. DS40001873E-page 511 PIC16(L)F19195/6/7 33.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1 and SSPxSTAT). These control bits allow the following to be specified: • • • • Host mode (SCK is the clock output) Client mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Host mode only) • Client Select mode (Client mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial PORT pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRISx register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Host mode) must have corresponding TRIS bit cleared • SCK (Client mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set The MSSP consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF, of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF, of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. FIGURE 33-5: SPI HOST/CLIENT CONNECTION SPI Host SSPM = 00xx = 1010 SPI Client SSPM = 010x SDO SDI Serial Input Buffer (SSPxBUF) SDI Shift Register (SSPxSR) MSb Serial Input Buffer (SSPxBUF) LSb SCK General I/O Processor 1  2017-2021 Microchip Technology Inc. SDO Serial Clock Client Select (optional) Shift Register (SSPxSR) MSb LSb SCK SS Processor 2 DS40001873E-page 512 PIC16(L)F19195/6/7 33.2.3 SPI HOST MODE The host can initiate the data transfer at any time because it controls the SCK line. The host determines when the client (Processor 2, Figure 33-5) is to broadcast data by the software protocol. In Host mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 33-6, Figure 33-8, Figure 33-9 and FIGURE 33-6: Figure 33-10, where the MSB is transmitted first. In Host mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) If SMP = 0, it is necessary to select the SCK pin as an input using SCKPPS. The input and output PPS selectors must go to the same pin. If SMP = 1 this is not required, and only the SCK output has to be routed; the input selection is ignored. Figure 33-6 shows the waveforms for Host mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. SPI MODE WAVEFORM (HOST MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF  2017-2021 Microchip Technology Inc. DS40001873E-page 513 PIC16(L)F19195/6/7 33.2.4 SPI CLIENT MODE In Client mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Client mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Client mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the client can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 33.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first client output is connected to the second client input, the second client output is connected to the third client input, and so on. The final client output is connected to the host input. Each client sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Client Select line from the host device. Figure 33-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the client. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 33.2.5 CLIENT SELECT SYNCHRONIZATION The Client Select can also be used to synchronize communication. The Client Select line is held high until the host device is ready to communicate. When the Client Select line is pulled low, the client knows that a new transmission is starting. If the client fails to receive the communication properly, it will be reset at the end of the transmission, when the Client Select line returns to a high state. The client is then ready to receive a new transmission when the Client Select line is pulled low again. If the Client Select line is not used, there is a risk that the client will eventually become out of sync with the host. If the client misses a bit, it will always be one bit off in future transmissions. Use of the Client Select line allows the client and host to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Client mode. The SPI must be in Client mode with SS pin control enabled (SSPxCON1 = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Client mode with SS pin control enabled (SSPxCON1 = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Client mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Client mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit.  2017-2021 Microchip Technology Inc. DS40001873E-page 514 PIC16(L)F19195/6/7 FIGURE 33-7: SPI DAISY-CHAIN CONNECTION SPI Host SCK SCK SDO SDI General I/O SDI SPI Client #1 SDO SS SCK SDI SPI Client #2 SDO SS SCK SDI SPI Client #3 SDO SS FIGURE 33-8: CLIENT SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF  2017-2021 Microchip Technology Inc. DS40001873E-page 515 PIC16(L)F19195/6/7 FIGURE 33-9: SPI MODE WAVEFORM (CLIENT MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 33-10: SPI MODE WAVEFORM (CLIENT MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active  2017-2021 Microchip Technology Inc. DS40001873E-page 516 PIC16(L)F19195/6/7 33.2.6 SPI OPERATION IN SLEEP MODE In SPI Host mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. In SPI Host mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Client mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. 33.3 To begin communication, the host device sends out a Start condition followed by the address byte of the client it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the host intends to transmit to or receive data from the client device. If the requested client exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The host then continues to either transmit or receive data from the client. FIGURE 33-11: VDD I2C MODE OVERVIEW The Inter-Integrated Circuit (I2C) bus is a multi-host serial data communication bus. Devices communicate in a host/client environment where the host devices initiate the communication. A client device is controlled through addressing. I2C HOST/ CLIENT CONNECTION SCL SCL VDD Host Client SDA SDA The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 33-2 and Figure 33-3 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Note: On the last byte of data communicated, the host device may end the transmission by sending a Stop bit. If the host device is in Receive mode, it sends the Stop condition in place of the last ACK bit. A Stop condition is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the host may want to maintain control of the bus and re-initiate another transmission. If so, the host device may send Restart condition in place of the Stop condition. When using designated I2C pins, the associated pin values in INLVLx will be ignored. Figure 33-11 shows a typical connection between two processors configured as host and client devices. The I2C bus can operate with one or more host devices and one or more client devices. There are four potential modes of operation for a given device: • Host Transmit mode (host is transmitting data to a client) • Host Receive mode (host is receiving data from a client) • Client Transmit mode (client is transmitting data to a host) • Client Receive mode (client is receiving data from the host)  2017-2021 Microchip Technology Inc. DS40001873E-page 517 PIC16(L)F19195/6/7 33.3.1 CLOCK STRETCHING When a client device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed client device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The host that is communicating with the client will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the client has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 33.3.2 ARBITRATION Each host device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two host devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a host device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. Client Transmit mode can also be arbitrated, when a host addresses multiple clients, but this is less common.  2017-2021 Microchip Technology Inc. 33.4 I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 33.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a host to a client or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the host. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 33.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 33.4.3 SDA AND SCL PINS When selecting any I2C mode, the SCL and SDA pins should be set by the user to inputs by setting the appropriate TRIS bits. Note 1: Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPDATPPS registers. The SCL input is selected with the SSPCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user’s responsibility to make the selections so that both the input and the output for each function is on the same pin. DS40001873E-page 518 PIC16(L)F19195/6/7 33.4.4 SDA HOLD TIME 33.4.5 The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. TABLE 33-1: TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Host The device that initiates a transfer, generates clock signals and terminates a transfer. Client The device addressed by the host. Multi-host A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one host at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No host is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more host devices are controlling the bus. Addressed Cli- Client device that has received a ent matching address and is actively being clocked by a host. Matching Address byte that is clocked into a Address client that matches the value stored in SSPxADD. Write Request Client receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Host sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Client. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state.  2017-2021 Microchip Technology Inc. START CONDITION The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the host and signifies the transition of the bus from an Idle to an Active state. Figure 33-12 shows wave forms for Start and Stop conditions. 33.4.6 STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. 33.4.7 RESTART CONDITION A Restart is valid any time that a Stop would be valid. A host can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the client that a Start would, resetting all client logic and preparing it to clock in an address. The host may want to address the same or another client. Figure 33-13 shows the wave form for a Restart condition. In 10-bit Addressing Client mode a Restart is required for the host to clock data out of the addressed client. Once a client has been fully addressed, matching both high and low address bytes, the host can issue a Restart and the high address byte with the R/W bit set. The client logic will then hold the clock and prepare to clock out data. 33.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Client modes that do not typically support this function. Client modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. DS40001873E-page 519 PIC16(L)F19195/6/7 FIGURE 33-12: I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 33-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition 33.4.9 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register.  2017-2021 Microchip Technology Inc. Client software, when the AHEN and DHEN bits are set, the clock is stretched, allowing the client time to change the ACK value before it is sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. There are certain conditions where an ACK will not be sent by the client. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. DS40001873E-page 520 PIC16(L)F19195/6/7 33.5 I2C CLIENT MODE OPERATION The MSSP Client mode operates in one of four modes selected by the SSPM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 33.5.1 CLIENT MODE ADDRESSES The SSPxADD register (Register 33-6) contains the Client mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 33-5) affects the address matching process. See Section 33.5.9 “SSP Mask Register” for more information. 33.5.1.1 I2C Client 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 33.5.1.2 I2C Client 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb’s of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the client is addressed, and clocking in the high address with the R/W bit set. The client hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a client after it has received a complete high and low address byte match.  2017-2021 Microchip Technology Inc. 33.5.2 CLIENT RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 33-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register. 33.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C client in 7-bit Addressing mode. Figure 33-14 and Figure 33-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The client pulls SDA low sending an ACK to the host, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Client software sets CKP bit to release the SCL line. The host clocks out a data byte. Client drives SDA low sending an ACK to the host, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the host. Host sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. DS40001873E-page 521 PIC16(L)F19195/6/7 33.5.2.2 7-bit Reception with AHEN and DHEN Client device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow time for the client software to decide whether it wants to ACK the receive address or data byte. This list describes the steps that need to be taken by client software to use these options for I2C communication. Figure 33-16 displays a module using both address and data holding. Figure 33-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge of SCL. 3. Client clears the SSPxIF. 4. Client can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Client reads the address value from SSPxBUF, clearing the BF flag. 6. Client sets ACK value clocked out to the host by setting ACKDT. 7. Client releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the client hardware will stretch the clock after the ACK. 10. Client clears SSPxIF. Note: SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to host is SSPxIF not set 11. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Client looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Client reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the client sending an ACK = 1, or the host sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the client will only know by polling the P bit of the SSPxSTAT register.  2017-2021 Microchip Technology Inc. DS40001873E-page 522  2017-2021 Microchip Technology Inc. I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 33-14: Bus Host sends Stop condition From Client to Host Receiving Address SDA SCL S Receiving Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 ACK 8 9 Receiving Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 ACK = 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software BF SSPxBUF is read First byte of data is available in SSPxBUF SSPOV SSPOV set because SSPxBUF is still full. ACK is not sent. SSPxIF set on 9th falling edge of SCL DS40001873E-page 523 PIC16(L)F19195/6/7 Cleared by software Bus Host sends Stop condition Receive Address SDA SCL S Receive Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 R/W=0 ACK 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to ‘1’ SSPxIF Cleared by software BF SSPxBUF is read Cleared by software SSPxIF set on 9th falling edge of SCL First byte of data is available in SSPxBUF SSPOV  2017-2021 Microchip Technology Inc. SSPOV set because SSPxBUF is still full. ACK is not sent. CKP CKP is written to ‘1’ in software, releasing SCL CKP is written to ‘1’ in software, releasing SCL SCL is not held low because ACK= 1 PIC16(L)F19195/6/7 DS40001873E-page 524 I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 33-15:  2017-2021 Microchip Technology Inc. I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 33-16: Host sends Stop condition Host Releases SDA to client for ACK sequence Receiving Address SDA Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 Received Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPxIF If AHEN = 1: SSPxIF is set BF ACKDT SSPxIF is set on 9th falling edge of SCL, after ACK Address is read from SSPxBUF Data is read from SSPxBUF Client software clears ACKDT to Client software sets ACKDT to not ACK ACK the received byte When AHEN = 1: CKP is cleared by hardware and SCL is stretched When DHEN = 1: CKP is cleared by hardware on 8th falling edge of SCL CKP set by software, SCL is released ACKTIM ACKTIM set by hardware on 8th falling edge of SCL DS40001873E-page 525 S P ACKTIM cleared by hardware in 9th rising edge of SCL ACKTIM set by hardware on 8th falling edge of SCL PIC16(L)F19195/6/7 CKP No interrupt after not ACK from Client Cleared by software R/W = 0 Receiving Address SDA ACK A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 3 4 5 6 7 Host sends Stop condition Host releases SDA to client for ACK sequence 8 9 Receive Data 1 2 3 4 5 6 7 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 8 ACK 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P SSPxIF No interrupt after if not ACK from Client Cleared by software BF Received address is loaded into SSPxBUF Received data is available on SSPxBUF ACKDT Client software clears ACKDT to ACK the received byte SSPxBUF can be read any time before next byte is loaded Client sends not ACK CKP When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared  2017-2021 Microchip Technology Inc. ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL S P ACKTIM is cleared by hardware on 9th rising edge of SCL Set by software, release SCL CKP is not cleared if not ACK PIC16(L)F19195/6/7 DS40001873E-page 526 I2C CLIENT, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 33-17: PIC16(L)F19195/6/7 33.5.3 CLIENT TRANSMISSION 33.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the client on the ninth bit. A host device can transmit a read request to a client, and then clock data out of the client. The list below outlines what software for a client will need to do to accomplish a standard transmission. Figure 33-18 can be used as a reference to this list. Following the ACK, client hardware clears the CKP bit and the SCL pin is held low (see Section 33.5.6 “Clock Stretching” for more detail). By stretching the clock, the host will be unable to assert another clock pulse until the client is done preparing the transmit data. 1. 2. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then the SCL pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the host-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. When the not ACK is latched by the client, the client goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 33.5.3.1 Client Mode Bus Collision A client receives a read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCL1IF bit of the PIR3 register is set. Once a bus collision is detected, the client goes idle and waits to be addressed again. User software can use the BCL1IF bit to handle a client bus collision.  2017-2021 Microchip Technology Inc. Host sends a Start condition on SDA and SCL. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Client setting SSPxIF bit. 4. Client hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The client software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCL, allowing the host to clock the data out of the client. 10. SSPxIF is set after the ACK response from the host is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The client software checks the ACKSTAT bit to see if the host wants to clock out more data. Note 1: If the host ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the host sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The host sends a Restart condition or a Stop. 16. The client is no longer addressed. DS40001873E-page 527 Host sends Stop condition Receiving Address R/W = 1 A7 A6 A5 A4 A3 A2 A1 SDA SCL S 1 2 3 4 5 6 7 ACK 8 9 Automatic Transmitting Data Automatic ACK Transmitting Data D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL CKP When R/W is set SCL is always held low after 9th SCL falling edge Set by software CKP is not held for not ACK ACKSTAT Hosts not ACK is copied to ACKSTAT R/W  2017-2021 Microchip Technology Inc. R/W is copied from the matching address byte D/A Indicates an address has been received S P 9 P PIC16(L)F19195/6/7 DS40001873E-page 528 I2C CLIENT, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) FIGURE 33-18: PIC16(L)F19195/6/7 33.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 33-19 displays a standard waveform of a 7-bit address client transmission with AHEN enabled. 1. 2. Bus starts Idle. Host sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Host sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Client software clears SSPxIF. 5. Client software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Client reads the address value from the SSPxBUF register clearing the BF bit. 7. Client software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPxCON2 register accordingly. 8. Client sets the CKP bit releasing SCL. 9. Host clocks in the ACK value from the client. 10. Client hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Client software clears SSPxIF. 12. Client loads value to transmit to the host into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Client sets the CKP bit releasing the clock. 14. Host clocks out the data from the client and sends an ACK value on the ninth SCL pulse. 15. Client hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the host from the client. 17. If the host sends a not ACK the client releases the bus allowing the host to send a Stop and end the communication. Note: Host must send a not ACK on the last byte to ensure that the client releases the SCL line to receive a Stop.  2017-2021 Microchip Technology Inc. DS40001873E-page 529 I2C CLIENT, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) Host sends Stop condition Host releases SDA to client for ACK sequence Receiving Address SDA SCL S 1 2 3 4 5 6 Automatic R/W = 1 ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL ACKDT Client clears ACKDT to ACK address ACKSTAT Host’s ACK response is copied to SSPxSTAT CKP  2017-2021 Microchip Technology Inc. When AHEN = 1; CKP is cleared by hardware after receiving matching address. ACKTIM R/W D/A ACKTIM is set on 8th falling edge of SCL When R/W = 1; CKP is always cleared after ACK Set by software, releases SCL ACKTIM is cleared on 9th rising edge of SCL CKP not cleared after not ACK ACK 8 9 P PIC16(L)F19195/6/7 DS40001873E-page 530 FIGURE 33-19: PIC16(L)F19195/6/7 33.5.4 CLIENT MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C client in 10-bit Addressing mode. Figure 33-20 is used as a visual reference for this description. This is a step by step process of what must be done by client software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Host sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Host sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Client sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Client loads low address into SSPxADD, releasing SCL. Host sends matching low address byte to the client; UA bit is set. 33.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 33-21 can be used as a reference of a client in 10-bit addressing with AHEN set. Figure 33-22 shows a standard waveform for a client transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Client sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the client software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Client clears SSPxIF. 11. Client reads the received matching address from SSPxBUF clearing BF. 12. Client loads high address into SSPxADD. 13. Host clocks a data byte to the client and clocks out the clients ACK on the ninth SCL pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Client clears SSPxIF. 16. Client reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the client sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Host sends Stop to end the transmission.  2017-2021 Microchip Technology Inc. DS40001873E-page 531 Host sends Stop condition Receive Second Address Byte Receive First Address Byte SDA SCL S 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 Receive Data Receive Data 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 SCL is held low while CKP = 0 SSPxIF Set by hardware on 9th falling edge Cleared by software BF Receive address is read from SSPxBUF If address matches SSPxADD it is loaded into SSPxBUF Data is read from SSPxBUF UA  2017-2021 Microchip Technology Inc. When UA = 1; SCL is held low Software updates SSPxADD and releases SCL CKP Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte 8 9 P PIC16(L)F19195/6/7 DS40001873E-page 532 I2C CLIENT, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 33-20:  2017-2021 Microchip Technology Inc. I2C CLIENT, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 33-21: Receive First Address Byte SDA SCL S Receive Second Address Byte R/W = 0 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 UA Receive Data A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 UA Receive Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 D6 D5 2 SSPxIF Set by hardware on 9th falling edge Cleared by software Cleared by software BF SSPxBUF can be read anytime before the next received byte Received data is read from SSPxBUF ACKDT UA Update to SSPxADD is not allowed until 9th falling edge of SCL CKP DS40001873E-page 533 If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL Update of SSPxADD, clears UA and releases SCL Set CKP with software releases SCL PIC16(L)F19195/6/7 Client software clears ACKDT to ACK the received byte Host sends Restart event Receiving Address R/W = 0 1 1 1 1 0 A9 A8 SDA SCL S 1 2 3 4 5 6 7 ACK 8 9 Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 Transmitting Data Byte ACK 9 1 2 3 4 5 6 7 SSPxIF Cleared by software Set by hardware BF SSPxBUF loaded with received address Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF UA UA indicates SSPxADD must be updated CKP After SSPxADD is updated, UA is cleared and SCL is released High address is loaded back into SSPxADD When R/W = 1; CKP is cleared on 9th falling edge of SCL ACKSTAT Set by software releases SCL  2017-2021 Microchip Technology Inc. Hosts not ACK is copied R/W R/W is copied from the matching address byte D/A Indicates an address has been received ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 Sr Set by hardware Host sends Stop condition Host sends not ACK 8 9 P PIC16(L)F19195/6/7 DS40001873E-page 534 I2C CLIENT, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 33-22: PIC16(L)F19195/6/7 33.5.6 CLOCK STRETCHING 33.5.6.3 Byte NACKing Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The client may stretch the clock to allow more time to handle data or prepare a response for the host device. A host device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a client is invisible to the host software and handled by the hardware that generates SCL. When AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When DHEN bit of SSPxCON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 33.5.7 33.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the client hardware will clear CKP. This allows the client time to update SSPxBUF with data to transfer to the host. If the SEN bit of SSPxCON2 is set, the client hardware will always stretch the clock after the ACK sequence. Once the client is ready; CKP is set by software and communication resumes. 33.5.6.2 Stretching after the eighth falling edge of SCL allows the client to look at the received address or data and decide if it wants to ACK the received data. CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C host device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 33-23). 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. FIGURE 33-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Host device asserts clock Host device releases clock WR SSPxCON1  2017-2021 Microchip Technology Inc. DS40001873E-page 535 PIC16(L)F19195/6/7 33.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The client will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the client addressed by the host device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the client hardware will stretch the clock after the eighth falling edge of SCL. The client must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the client module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the client clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and client software can read SSPxBUF and respond. Figure 33-24 shows a general call reception sequence. FIGURE 33-24: CLIENT MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT) Cleared by software GCEN (SSPxCON2) SSPxBUF is read ’1’ 33.5.9 SSP MASK REGISTER An SSP Mask (SSPxMSK) register (Register 33-5) is available in I2C Client mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”.  2017-2021 Microchip Technology Inc. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A. • 10-bit Address mode: address compare of A only. The SSP mask has no effect during the reception of the first (high) byte of the address. DS40001873E-page 536 PIC16(L)F19195/6/7 33.6 I2C Host Mode 33.6.1 I2C HOST MODE OPERATION Host mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Host mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The host device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Host mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Host Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the client address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Host mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled): • • • • • Start condition generated Stop condition generated Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Host mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur In Host Receive mode, the first byte transmitted contains the client address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit client address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 33.7 “Baud Rate Generator” for more detail. 2: When in Host mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete.  2017-2021 Microchip Technology Inc. DS40001873E-page 537 PIC16(L)F19195/6/7 33.6.2 CLOCK ARBITRATION Clock arbitration occurs when the host, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 33-25). FIGURE 33-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL deasserted but client holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 33.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete.  2017-2021 Microchip Technology Inc. DS40001873E-page 538 PIC16(L)F19195/6/7 33.6.4 I2C HOST MODE START CONDITION TIMING Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. To initiate a Start condition (Figure 33-26), the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. FIGURE 33-26: 2: The Philips I2C specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT) At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 1st bit 2nd bit TBRG SCL S  2017-2021 Microchip Technology Inc. TBRG DS40001873E-page 539 PIC16(L)F19195/6/7 33.6.5 I2C HOST MODE REPEATED START cally cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. CONDITION TIMING A Repeated Start condition (Figure 33-27) occurs when the RSEN bit of the SSPxCON2 register is programmed high and the host state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSPxCON2 register will be automati- FIGURE 33-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another host is attempting to transmit a data ‘1’. REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPxIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start  2017-2021 Microchip Technology Inc. DS40001873E-page 540 PIC16(L)F19195/6/7 33.6.6 I2C HOST MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the host releases SDA. This allows the client device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the host receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the host clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 33-28). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the host will release the SDA pin, allowing the client to respond with an Acknowledge. On the falling edge of the ninth clock, the host will sample the SDA pin to see if the address was recognized by a client. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 33.6.6.1 BF Status Flag 33.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the client has sent an Acknowledge (ACK = 0) and is set when the client does not Acknowledge (ACK = 1). A client sends an Acknowledge when it has recognized its address (including a general call), or when the client has properly received its data. 33.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the client address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the client device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the client device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 33.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2017-2021 Microchip Technology Inc. DS40001873E-page 541 Write SSPxCON2 SEN = 1 Start condition begins From client, clear ACKSTAT bit SSPxCON2 SEN = 0 Transmit Address to Client A7 SDA A6 A5 A4 ACKSTAT in SSPxCON2 = 1 A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 A1 ACK = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCL held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 SSPxBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 9 P SSPxIF Cleared by software Cleared by software service routine from SSP interrupt BF (SSPxSTAT) SSPxBUF written SEN  2017-2021 Microchip Technology Inc. After Start condition, SEN cleared by hardware PEN R/W SSPxBUF is written by software Cleared by software PIC16(L)F19195/6/7 DS40001873E-page 542 I2C HOST MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) FIGURE 33-28: PIC16(L)F19195/6/7 33.6.7 I2C HOST MODE RECEPTION Host mode reception (Figure 33-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSPxCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register. 33.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 33.6.7.2 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 33.6.7.3 33.6.7.4 WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2017-2021 Microchip Technology Inc. 12. 13. 14. 15. Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the client address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the client device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the host clocks in a byte from the client. After the eighth falling edge of SCL, SSPxIF and BF are set. Host clears SSPxIF and reads the received byte from SSPxBUF, clears BF. Host sets ACK value sent to client in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Host’s ACK is clocked out to the client and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the client. Host sends a not ACK or Stop to end communication. DS40001873E-page 543 Write to SSPxCON2 to start Ackno1wledge sequence SDA = ACKDT (SSPxCON2) = 0 Write to SSPxCON2(SEN = 1), begin Start condition SEN = 0 Write to SSPxBUF occurs here, ACK from Client start XMIT A6 A5 A4 A3 A2 RCEN = 1, start next receive RCEN cleared automatically Transmit Address to Client A7 SDA ACK PEN bit = 1 written here RCEN cleared automatically Receiving Data from Client Receiving Data from Client A1 R/W Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 ACK from Host SDA = ACKDT = 0 Host configured as a receiver by programming SSPxCON2 (RCEN = 1) D7 D6 D5 D4 D3 D2 D1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Bus host terminates transfer ACK is not sent SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 Data shifted in on falling edge of CLK Set SSPxIF interrupt at end of receive Cleared by software Cleared by software Cleared by software BF (SSPxSTAT) P Set SSPxIF at end of receive Set SSPxIF interrupt at end of Acknowledge sequence SSPxIF SDA = 0, SCL = 1 while CPU responds to SSPxIF 9 8 Cleared by software Cleared in software Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF SSPOV  2017-2021 Microchip Technology Inc. SSPOV is set because SSPxBUF is still full ACKEN RCEN Host configured as a receiver by programming SSPxCON2 (RCEN = 1) RCEN cleared automatically ACK from Host SDA = ACKDT = 0 RCEN cleared automatically Set SSPxIF interrupt at end of Acknowledge sequence Set P bit (SSPxSTAT) and SSPxIF PIC16(L)F19195/6/7 DS40001873E-page 544 I2C HOST MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) FIGURE 33-29: PIC16(L)F19195/6/7 33.6.8 ACKNOWLEDGE SEQUENCE TIMING 33.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the host will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 33-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPxCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 33-30). 33.6.8.1 33.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 33-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 33-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period.  2017-2021 Microchip Technology Inc. DS40001873E-page 545 PIC16(L)F19195/6/7 33.6.10 SLEEP OPERATION 33.6.13 2 While in Sleep mode, the I C client module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 33.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 33.6.12 MULTI-HOST MODE In Multi-Host mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-host operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCL1IF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -HOST COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Host mode support is achieved by bus arbitration. When the host outputs address/data bits onto the SDA pin, arbitration takes place when the host outputs a ‘1’ on SDA, by letting SDA float high and another host asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The host will set the Bus Collision Interrupt Flag, BCL1IF and reset the I2C port to its Idle state (Figure 33-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The host will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Host mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 33-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by host Sample SDA. While SCL is high, data does not match what is driven by the host. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF  2017-2021 Microchip Technology Inc. DS40001873E-page 546 PIC16(L)F19195/6/7 33.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 33-33). SCL is sampled low before SDA is asserted low (Figure 33-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 33-35). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCL1IF flag is set and • the MSSP module is reset to its Idle state (Figure 33-33). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another host is attempting to drive a data ‘1’ during the Start condition. FIGURE 33-33: The reason that bus collision is not a factor during a Start condition is that no two bus hosts can assert a Start condition at the exact same time. Therefore, one host will always assert SDA before the other. This condition does not cause a bus collision because the two hosts must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSPxIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCL1IF SDA sampled low before Start condition. Set BCL1IF. S bit and SSPxIF set because SDA = 0, SCL = 1. SSPxIF and BCL1IF are cleared by software S SSPxIF SSPxIF and BCL1IF are cleared by software  2017-2021 Microchip Technology Inc. DS40001873E-page 547 PIC16(L)F19195/6/7 FIGURE 33-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software ’0’ ’0’ SSPxIF ’0’ ’0’ S FIGURE 33-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPxIF TBRG SDA pulled low by other host. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN BCL1IF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSPxIF SDA = 0, SCL = 1, set SSPxIF  2017-2021 Microchip Technology Inc. Interrupts cleared by software DS40001873E-page 548 PIC16(L)F19195/6/7 33.6.13.2 Bus Collision During a Repeated Start Condition counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two hosts can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another host is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 33-37. A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another host is attempting to transmit a data ‘1’ (Case 2). If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another host is attempting to transmit a data ‘0’, Figure 33-36). If SDA is sampled high, the BRG is reloaded and begins FIGURE 33-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL1IF Cleared by software S ’0’ SSPxIF ’0’ FIGURE 33-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCL1IF SCL goes low before SDA, set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN S ’0’ SSPxIF  2017-2021 Microchip Technology Inc. DS40001873E-page 549 PIC16(L)F19195/6/7 33.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another host attempting to drive a data ‘0’ (Figure 33-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another host attempting to drive a data ‘0’ (Figure 33-39). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 33-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCL1IF SDA asserted low SCL PEN BCL1IF P ’0’ SSPxIF ’0’ FIGURE 33-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCL1IF PEN BCL1IF P ’0’ SSPxIF ’0’  2017-2021 Microchip Technology Inc. DS40001873E-page 550 PIC16(L)F19195/6/7 33.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Host modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 33-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 33-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 33-1: FOSC FCLOCK = ------------------------------------------------- SSP1ADD + 1   4  An internal signal “Reload” in Figure 33-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 33-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM SSPM Reload SCL Control SSPCLK SSPxADD Reload BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 33-2: Note: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical specifications in Table 39-4 to ensure the system is designed to support I/O requirements.  2017-2021 Microchip Technology Inc. DS40001873E-page 551 PIC16(L)F19195/6/7 33.8 Register Definitions: MSSPx Control REGISTER 33-1: SSPxSTAT: SSPx STATUS REGISTER R/W-0/0 R/W-0/0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 R/HS/HC-0 SMP CKE(1) D/A P(2) S(2) R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS/HC = Hardware set/clear bit 7 SMP: SPI Data Input Sample bit SPI Host mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Client mode: SMP must be cleared when SPI is used in Client mode In I2 C Host or Client mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)(1) In SPI Host or Client mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(2) (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (2) (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Client mode: 1 = Read 0 = Write In I2 C Host mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty Note 1: 2: Polarity of clock state is set by the CKP bit of the SSPxCON register. This bit is cleared on Reset and when SSPEN is cleared.  2017-2021 Microchip Technology Inc. DS40001873E-page 552 PIC16(L)F19195/6/7 REGISTER 33-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV(1) SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Client mode. In Client mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, the following pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial PORT pins(2) 0 = Disables serial port and configures these pins as I/O PORT pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial PORT pins(3) 0 = Disables serial port and configures these pins as I/O PORT pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Client mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Host mode: Unused in this mode bit 3-0 SSPM: Synchronous Serial Port Mode Select bits 1111 = I2C Client mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Client mode, 7-bit address with Start and Stop bit interrupts enabled 1101 = Reserved 1100 = Reserved 1011 = I2C firmware controlled Host mode (client idle) 1010 = SPI Host mode, clock = FOSC/(4 * (SSPxADD+1))(5) 1001 = Reserved 1000 = I2C Host mode, clock = FOSC/(4 * (SSPxADD+1))(4) 0111 = I2C Client mode, 10-bit address 0110 = I2C Client mode, 7-bit address 0101 = SPI Client mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Client mode, clock = SCK pin, SS pin control enabled 0011 = SPI Host mode, clock = T2_match/2 0010 = SPI Host mode, clock = FOSC/64 0001 = SPI Host mode, clock = FOSC/16 0000 = SPI Host mode, clock = FOSC/4 Note 1: 2: 3: 4: 5: In Host mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. Use SSPxSSPPS, SSPxCLKPPS, SSPxDATPPS, and RxyPPS to select the pins. When enabled, the SDA and SCL pins must be configured as inputs. Use SSPxCLKPPS, SSPxDATPPS, and RxyPPS to select the pins. SSPxADD values of 0, 1 or 2 are not supported for I2C mode. SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead.  2017-2021 Microchip Technology Inc. DS40001873E-page 553 PIC16(L)F19195/6/7 REGISTER 33-3: SSPxCON2: SSPx CONTROL REGISTER 2 (I2C MODE ONLY)(1) R/W-0/0 R/HS/HC-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Client mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Host mode only) In Host Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Host mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Host mode only) 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Host mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Host mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Client mode: 1 = Clock stretching is enabled for both client transmit and client receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle state, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).  2017-2021 Microchip Technology Inc. DS40001873E-page 554 PIC16(L)F19195/6/7 REGISTER 33-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Client mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2 C Host mode and SPI Host mode: This bit is ignored. In I2 C Client mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Client Mode Bus Collision Detect Enable bit (I2C Client mode only) If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR3 register is set, and bus goes idle 1 = Enable client bus collision interrupts 0 = Client bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Client mode only) 1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Client mode only) 1 = Following the eighth falling edge of SCL for a received data byte; client hardware clears the CKP bit of the SSPxCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Client modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.  2017-2021 Microchip Technology Inc. DS40001873E-page 555 PIC16(L)F19195/6/7 REGISTER 33-5: R/W-1/1 SSPxMSK: SSPx MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SSPxMSK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 SSPxMSK: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 SSPxMSK: Mask bit for I2C Client mode, 10-bit Address I2C Client mode, 10-bit address (SSPM = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Client mode, 7-bit address: MSK0 bit is ignored. REGISTER 33-6: R/W-0/0 SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPxADD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Host mode: bit 7-0 SSPxADD: Baud Rate Clock Divider bits SCL pin clock period = ((ADD + 1) *4)/FOSC 10-Bit Client mode – Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pattern sent by host is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 SSPxADD: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Client mode – Least Significant Address Byte: bit 7-0 SSPxADD: Eight Least Significant bits of 10-bit address 7-Bit Client mode: bit 7-1 SSPxADD: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2017-2021 Microchip Technology Inc. DS40001873E-page 556 PIC16(L)F19195/6/7 REGISTER 33-7: R/W-x SSPxBUF: MSSPx BUFFER REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SSPxBUF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TABLE 33-3: Name INTCON SSPxBUF: MSSP Buffer bits SUMMARY OF REGISTERS ASSOCIATED WITH MSSPx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE — — — — — INTEDG 147 — — — PIR1 OSFIF CSWIF — ADTIF ADIF 158 PIE1 OSFIE CSWIE — — — — ADTIE ADIE 149 SSP1STAT SMP CKE D/A P S R/W UA BF 552 SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN SSPM 553 554 555 SSP1MSK SSPMSK 556 SSP1ADD SSPADD 556 SSP1BUF SSPBUF 557 CKE D/A P S R/W ACKEN RCEN PEN RSEN SEN 554 BOEN SDAHT SBCDE AHEN DHEN 555 SSP2STAT SMP SSP2CON1 WCOL SSPOV SSPEN CKP SSP2CON2 GCEN ACKSTAT ACKDT SSP2CON3 ACKTIM PCIE SCIE UA BF SSPM 552 553 SSP2MSK SSPMSK 556 SSP2ADD SSPADD 556 SSP2BUF SSPBUF 557 SSP1CLKPPS — — — SSP1CLKPPS 259 SSP1DATPPS — — — SSP1DATPPS 259 SSP1SSPPS — — — SSP1SSPPS 259 SSP2CLKPPS — — — SSP2CLKPPS 259 SSP2DATPPS — — — SSP2DATPPS 259 SSP2SSPPS — — — SSP2SSPPS 259 RxyPPS — — — RxyPPS 260 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx module.  2017-2021 Microchip Technology Inc. DS40001873E-page 557 PIC16(L)F19195/6/7 34.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART1/2) The EUSART module includes the following capabilities: • • • • • • • • • • Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous host Half-duplex synchronous client Programmable clock polarity in synchronous modes • Sleep operation The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a host synchronous device. Note: The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 34-1 and Figure 34-2. The EUSART transmit output (TX_out) is available to the TX/CK pin and internally to the following peripherals: Two identical EUSART modules are implemented on this device. The timers are named EUSART1 and EUSART4. All references to EUSART1 apply as well to EUSART2. FIGURE 34-1: • Configurable Logic Cell (CLC) EUSART TRANSMIT BLOCK DIAGRAM Data Bus SYNC CSRC 8 TXEN MSb 1 • • • 0 TRMT PPS TX9 n Multiplier TX_out ÷n BRG16 SPxBRGH SPxBRGL RX/DT pin SYNC FOSC +1 Pin Buffer and Control Transmit Shift Register (TSR) CKPPS Note 1: RxyPPS(1) LSb (8) 0 Baud Rate Generator Interrupt TXxIF TXxREG Register CK pin PPS TXxIE x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 TX9D In Synchronous mode the DT output and RX input PPS selections should enable the same pin.  2017-2021 Microchip Technology Inc. 0 TX/CK pin PPS 1 RxyPPS SYNC CSRC DS40001873E-page 558 PIC16(L)F19195/6/7 FIGURE 34-2: EUSART RECEIVE BLOCK DIAGRAM SPEN RX/DT pin CREN OERR RXPPS(1) RSR Register MSb PPS Pin Buffer and Control Baud Rate Generator Data Recovery FOSC BRG16 +1 SPxBRGH SPxBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop (8) ••• 7 1 LSb 0 Start RX9 ÷n n FERR RX9D RCxREG Register 8 Note 1: RCIDL In Synchronous mode the DT output and RX input PPS selections should enable the same pin. FIFO Data Bus RXxIF RXxIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXxSTA) • Receive Status and Control (RCxSTA) • Baud Rate Control (BAUDxCON) These registers are detailed in Register 34-1, Register 34-2 and Register 34-3, respectively. The RX input pin is selected with the RXPPS. The CK input is selected with the TXPPS register. TX, CK, and DT output pins are selected with each pin’s RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically.  2017-2021 Microchip Technology Inc. DS40001873E-page 559 PIC16(L)F19195/6/7 34.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 34-3 for examples of baud rate configurations. 34.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 34.1.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 34.4.1.2 “Clock Polarity”. 34.1.1 34.1.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 34-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. 34.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXxSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXxIF interrupt flag bit of the PIR3 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution. Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software. The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIE3 register. However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit. To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. The TXxIF Transmitter Interrupt flag is set when the TXEN enable bit is set.  2017-2021 Microchip Technology Inc. DS40001873E-page 560 PIC16(L)F19195/6/7 34.1.1.5 TSR Status 34.1.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 34.1.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 34.1.2.7 “Address Detection” for more information on the Address mode. FIGURE 34-3: Write to TXxREG BRG Output (Shift Clock) TX/CK pin TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) 4. 5. 6. 7. 8. Asynchronous Transmission Set-up: Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 34.3 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set. If interrupts are desired, set the TXxIE interrupt enable bit of the PIE3 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXxREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg.  2017-2021 Microchip Technology Inc. DS40001873E-page 561 PIC16(L)F19195/6/7 FIGURE 34-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG BRG Output (Shift Clock) Word 1 TX/CK pin TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Note: 34.1.2 Word 2 Start bit bit 0 1 TCY bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 34-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 34.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCxSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note: bit 1 Word 1 34.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 34.1.2.4 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RXxIF interrupt flag bit of the PIR3 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 34.1.2.5 “Receive Overrun Error” for more information on overrun errors. If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function.  2017-2021 Microchip Technology Inc. DS40001873E-page 562 PIC16(L)F19195/6/7 34.1.2.3 Receive Interrupts The RXxIF interrupt flag bit of the PIR3 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RXxIF interrupt flag bit is read-only, it cannot be set or cleared by software. RXxIF interrupts are enabled by setting all of the following bits: • RXxIE, Interrupt Enable bit of the PIE3 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RXxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 34.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. 34.1.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 34.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RXxIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 34.1.2.5 If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register.  2017-2021 Microchip Technology Inc. DS40001873E-page 563 PIC16(L)F19195/6/7 34.1.2.8 Asynchronous Reception Setup: 34.1.2.9 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 34.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RXxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RXxIE interrupt enable bit was also set. 8. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 34-5: This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 34.3 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RXxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RXxIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Setup bit 1 Rcv Shift Reg Rcv Buffer Reg. RCIDL bit 7/8 Stop bit Start bit Word 1 RCxREG bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCxREG Read Rcv Buffer Reg. RCxREG RXxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.  2017-2021 Microchip Technology Inc. DS40001873E-page 564 PIC16(L)F19195/6/7 34.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 9.2.2.2 “Internal Oscillator Frequency Adjustment” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 34.3.1 “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.  2017-2021 Microchip Technology Inc. DS40001873E-page 565 PIC16(L)F19195/6/7 34.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH, SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Table 34-1 contains the formulas for determining the baud rate. Example 34-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various Asynchronous modes have been computed for your convenience and are shown in Table 34-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. EXAMPLE 34-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = ----------------------------------------------------------------------64  [SPBRGH:SPBRGL] + 1  Solving for SPxBRGH:SPxBRGL: F OS C -------------------------------------------Desired Baud Rate – 1 X = --------------------------------------------64 16000000 -----------------------9600 - – 1 = ----------------------64 =  25.042  = 25 16000000Calculated Baud Rate = -------------------------64  25 + 1  = 9615 Baud Rate – Desired Baud RateError = Calc. ------------------------------------------------------------------------------------------Desired Baud Rate 9615 – 9600  = 0.16% = ---------------------------------9600 Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock.  2017-2021 Microchip Technology Inc. DS40001873E-page 566 PIC16(L)F19195/6/7 34.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 34-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH, SPxBRGL register pair, the ABDEN bit is automatically cleared and the RXxIF interrupt flag is set. The value in the RCxREG needs to be read to clear the RXxIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 34-1. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at FIGURE 34-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 34.3.3 “Auto-Wake-up on Break”). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. TABLE 34-1: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 1 FOSC/4 FOSC/32 Note: During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter, independent of the BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. 0000h RX pin 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RXxIF bit (Interrupt) Read RCxREG SPxBRGL XXh 1Ch SPxBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2017-2021 Microchip Technology Inc. DS40001873E-page 567 PIC16(L)F19195/6/7 34.3.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. The overflow condition will set the RXxIF flag. The counter continues to count until the fifth rising edge is detected on the RX pin. The RCIDL bit will remain false (‘0’) until the fifth rising edge at which time the RCIDL bit will be set. If the RCxREG is read after the overflow occurs but before the fifth rising edge then the fifth rising edge will set the RXxIF again. Terminating the auto-baud process early to clear an overflow condition will prevent proper detection of the sync character fifth rising edge. If any falling edges of the sync character have not yet occurred when the ABDEN bit is cleared then those will be falsely detected as Start bits. The following steps are recommended to clear the overflow condition: 1. 2. 3. Read RCxREG to clear RXxIF. If RCIDL is ‘0’ then wait for RDCIF and repeat step 1. Clear the ABDOVF bit. 34.3.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) 34.3.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RXxIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The EUSART module generates an RXxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 34-7), and asynchronously if the device is in Sleep mode (Figure 34-8). The interrupt condition is cleared by reading the RCxREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2017-2021 Microchip Technology Inc. DS40001873E-page 568 PIC16(L)F19195/6/7 FIGURE 34-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RXxIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set. FIGURE 34-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RXxIF Sleep Command Executed Note 1: 2: 34.3.4 Cleared due to User Read of RCxREG Sleep Ends If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 34-9 for the timing of the Break character sequence.  2017-2021 Microchip Technology Inc. 34.3.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus host. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG. DS40001873E-page 569 PIC16(L)F19195/6/7 34.3.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when: • RXxIF bit is set • FERR bit is set • RCxREG = 00h The second method uses the Auto-Wake-up feature described in Section 34.3.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RXxIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. FIGURE 34-9: Write to TXxREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit)  2017-2021 Microchip Technology Inc. SENDB Sampled Here Auto Cleared DS40001873E-page 570 PIC16(L)F19195/6/7 34.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single host and one or more clients. The host device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Client devices can take advantage of the host clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Clients use the external clock supplied by the host to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that host and client devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a host or client device. Start and Stop bits are not used in synchronous transmissions. 34.4.1 SYNCHRONOUS HOST MODE The following bits are used to configure the EUSART for synchronous host operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXxSTA register configures the device as a host. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 34.4.1.1 Host Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a host transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.  2017-2021 Microchip Technology Inc. 34.4.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 34.4.1.3 Synchronous Host Transmission Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous host transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the host clock and remains valid until the subsequent leading clock edge. Note: 34.4.1.4 1. 2. 3. 4. 5. 6. 7. 8. The TSR register is not mapped in data memory, so it is not available to the user. Synchronous Host Transmission Set-up: Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 34.3 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous host serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXxREG register. DS40001873E-page 571 PIC16(L)F19195/6/7 FIGURE 34-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXxREG Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Host mode, SPxBRGL = 0, continuous transmission of two 8-bit words. FIGURE 34-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXxREG reg TXxIF bit TRMT bit TXEN bit 34.4.1.5 Synchronous Host Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous host receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence.  2017-2021 Microchip Technology Inc. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RXxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RXxIF bit remains set as long as there are unread characters in the receive FIFO. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. DS40001873E-page 572 PIC16(L)F19195/6/7 34.4.1.6 Client Clock received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a client receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous client transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: 34.4.1.7 34.4.1.9 1. Initialize the SPxBRGH, SPxBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous host serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RXxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RXxIE was set. 9. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. If the device is configured as a client and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 34.4.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character FIGURE 34-12: RX/DT pin Synchronous Host Reception Set-up: SYNCHRONOUS RECEPTION (HOST MODE, SREN) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RXxIF bit (Interrupt) Read RCxREG Note: Timing diagram demonstrates Sync Host mode with bit SREN = 1 and bit BRGH = 0.  2017-2021 Microchip Technology Inc. DS40001873E-page 573 PIC16(L)F19195/6/7 34.4.2 SYNCHRONOUS CLIENT MODE The following bits are used to configure the EUSART for synchronous client operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a client. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 34.4.2.1 The operation of the Synchronous Host and Client modes are identical (see Section 34.4.1.3 “Synchronous Host Transmission”), except in the case of the Sleep mode. If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. 5. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXxREG register. The TXxIF bit will not be set. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXxIF bit will now be set. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. 34.4.2.2 1. 2. 3. 4. 5. 6. 7. 8.  2017-2021 Microchip Technology Inc. EUSART Synchronous Client Transmit Synchronous Client Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXxREG register. DS40001873E-page 574 PIC16(L)F19195/6/7 34.4.2.3 EUSART Synchronous Client Reception The operation of the Synchronous Host and Client modes is identical (Section 34.4.1.5 “Synchronous Host Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Client mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RXxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 34.4.2.4 1. 2. 3. 4. 5. 6. 7. 8. 9.  2017-2021 Microchip Technology Inc. Synchronous Client Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RXxIF bit will be set when reception is complete. An interrupt will be generated if the RXxIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. DS40001873E-page 575 PIC16(L)F19195/6/7 34.5 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Client mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Client mode uses an externally generated clock to run the Transmit and Receive Shift registers. 34.5.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: • RCxSTA and TXxSTA Control registers must be configured for Synchronous Client Reception (see Section 34.4.2.4 “Synchronous Client Reception Set-up:”). • If interrupts are desired, set the RXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. • The RXxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RXxIF interrupt flag bit of the PIR3 register will be set. Thereby, waking the processor from Sleep. 34.5.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • The RCxSTA and TXxSTA Control registers must be configured for synchronous client transmission (see Section 34.4.2.2 “Synchronous Client Transmission Set-up:”). • The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and transmit buffer. • If interrupts are desired, set the TXxIE bit of the PIE3 register and the PEIE bit of the INTCON register. • Interrupt enable bits TXxIE of the PIE3 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another character for transmission, which will clear the TXxIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.  2017-2021 Microchip Technology Inc. DS40001873E-page 576 PIC16(L)F19195/6/7 34.6 Register Definitions: EUSART Control REGISTER 34-1: R/W-/0 CSRC TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Unused in this mode – value ignored Synchronous mode: 1 = Host mode (clock generated internally from BRG) 0 = Client mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send SYNCH BREAK on next transmission – Start bit, followed by 12 ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = SYNCH BREAK transmission disabled or completed Synchronous mode: Unused in this mode – value ignored bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode – value ignored bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2017-2021 Microchip Technology Inc. DS40001873E-page 577 PIC16(L)F19195/6/7 REGISTER 34-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN(1) RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit(1) 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Unused in this mode – value ignored Synchronous mode – Host: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Client Unused in this mode – value ignored bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in the receive buffer is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Unused in this mode – value ignored bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCxREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Note 1: The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the associated TRIS bits for TX/CK and RX/DT to 1.  2017-2021 Microchip Technology Inc. DS40001873E-page 578 PIC16(L)F19195/6/7 REGISTER 34-3: BAUDxCON: BAUD RATE CONTROL REGISTER R/W-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Clock/Transmit Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is a low level 0 = Idle state for transmit (TX) is a high level Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = USART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge. 0 = RX pin not monitored nor rising edge detected Synchronous mode: Unused in this mode – value ignored bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character – requires reception of a SYNCH field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode – value ignored  2017-2021 Microchip Technology Inc. DS40001873E-page 579 PIC16(L)F19195/6/7 RCxREG(1): RECEIVE DATA REGISTER REGISTER 34-4: R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RCxREG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: RCxREG: Lower eight bits of the received data; read-only; see also RX9D (Register 34-2) RCxREG (including the 9th bit) is double buffered, and data is available while new data is being received. TXxREG(1): TRANSMIT DATA REGISTER REGISTER 34-5: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXxREG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: TXxREG: Lower eight bits of the received data; read-only; see also RX9D (Register 34-1) TXxREG (including the 9th bit) is double buffered, and can be written when previous data has started shifting. SPxBRGL(1): BAUD RATE GENERATOR REGISTER REGISTER 34-6: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPxBRG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: SPxBRG: Lower eight bits of the Baud Rate Generator Writing to SP1BRG resets the BRG counter.  2017-2021 Microchip Technology Inc. DS40001873E-page 580 PIC16(L)F19195/6/7 SPxBRGH(1, 2): BAUD RATE GENERATOR HIGH REGISTER REGISTER 34-7: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPxBRG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Note 1: 2: SPxBRG: Upper eight bits of the Baud Rate Generator SPxBRGH value is ignored for all modes unless BAUDxCON is active. Writing to SPxBRGH resets the BRG counter.  2017-2021 Microchip Technology Inc. DS40001873E-page 581 PIC16(L)F19195/6/7 TABLE 34-2: SUMMARY OF REGISTERS ASSOCIATED WITH EUSART Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE ― ― ― ― ― INTEDG 147 PIR3 RC2IF TX2IF RC1IF TX1IF ― ― BCL1IF SSP1IF 160 PIE3 RC2IE TX2IE RC1IE TX1IE ― ― BCL1IE SSP1IE 151 RCxSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 578 TXxSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 577 ABDOVF RCIDL ― SCKP BRG16 ― WUE ABDEN 579 Name INTCON BAUDxCON RCxREG RCxREG 580* TXxREG TXxREG 580* SPxBRGL SPxBRG 580* SPxBRGH SPxBRG 581* RXPPS ― ― ― CKPPS ― ― ― CXPPS 259 RxyPPS ― ― ― RxyPPS 260 ― ― ― LCxDyS 499 CLCxSELy Legend: * RXPPS 259 — = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART module. Page with register information.  2017-2021 Microchip Technology Inc. DS40001873E-page 582 PIC16(L)F19195/6/7 TABLE 34-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[16 (n+1)] FOSC/[4 (n+1)] x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair. TABLE 34-4: BAUD RATE FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k — -3.55 — 3 — — — — — — — 57.60k — 0.00 7 — 57.60k — 0.00 2 — — 115.2k — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — 1202 — 0.16 — 103 300 1202 0.16 0.16 207 51 300 1200 0.00 191 47 300 1202 0.16 0.16 51 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 0.00 0 — — — 115.2k — — — — — — 57.60k — — — — — —  2017-2021 Microchip Technology Inc. 0.00 DS40001873E-page 583 PIC16(L)F19195/6/7 TABLE 34-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE 300 1200 FOSC = 32.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 20.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 18.432 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 11.0592 MHz SPBRG Actual % value Rate Error (decimal) — — — — — — — — — — — — — — — — — — — — — — — — — 9600 — 0.00 — 71 2400 — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 BAUD RATE FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 — — — — — — — — — 300 0.16 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — 207 SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 32.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 20.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 18.432 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 11.0592 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 300.0 1200 0.00 -0.02 6666 3332 300.0 1200 -0.01 -0.03 4166 1041 300.0 1200 0.00 0.00 3839 959 300.0 1200 0.00 0.00 2303 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 BAUD RATE 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5  2017-2021 Microchip Technology Inc. DS40001873E-page 584 PIC16(L)F19195/6/7 TABLE 34-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 299.9 1199 -0.02 -0.08 1666 416 300.1 1202 0.04 0.16 832 207 300.0 1200 0.00 0.00 767 191 300.5 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — BAUD RATE SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 Actual Rate 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 300.0 1200 0.00 -0.02 6666 1666 300.0 1200 0.01 0.04 3332 832 300.0 1200 0.00 0.00 3071 767 300.1 1202 0.04 0.16 832 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — BAUD RATE  2017-2021 Microchip Technology Inc. DS40001873E-page 585 PIC16(L)F19195/6/7 35.0 LIQUID CRYSTAL DISPLAY (LCD) CONTROLLER A simplified block diagram of the module is shown in Figure 35-1. The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. The module is capable of driving panels with up to eight commons and up to 46 segments. It also provides control of the LCD pixel data. The LCD driver module supports: • Direct driving of LCD panel • Two LCD clock sources with selectable prescaler • Up to eight commons: See Table 35-1 device specific for multiplexing options. - Static (One common) - 1/2 Multiplex (two commons) - 1/3 Multiplex (three commons) - 1/4 Multiplex (four commons) - 1/5 Multiplex (five commons) - 1/6 Multiplex (six commons) - 1/7 Multiplex (seven commons) - 1/8 Multiplex (eight commons) • Static, 1/2 (1/2 Multiplex only) or 1/3 LCD bias (1/3 Multiplex and higher) • On-chip bias generator with dedicated charge pump to support a range of fixed and variable bias options • Internal resistors for bias voltage generation • Software contrast control through internal biasing TABLE 35-1: COM AND SEG MULTIPLEXING OPTIONS Device Pin Count 64-Pin Number of COM Used Number of SEG Pins Available Number of Possible Segments 1 46 46 2 46 92 3 46 138 4 46 184 5 46 230 6 46 276 7 46 322 8 45 360  2017-2021 Microchip Technology Inc. DS40001873E-page 586 PIC16(L)F19195/6/7 FIGURE 35-1: Data Bus LCD CONTROLLER MODULE BLOCK DIAGRAM LCD DATA 48 x 8 (= 8 x 46) Rev. 10-000316A 1/31/2017 LCDDATA47 LCDDATA46 ... LCDDATA01 368 to 48 MUX SEG LCDDATA00 8  LCDCON To I/O Pins Bias Voltage Timing Control 8 LCDPS COM LCDSENx LCD Bias Generation Resistor Ladder SOSC LCD Clock Source Select LFINTOSC  2017-2021 Microchip Technology Inc. LCD Charge Pump DS40001873E-page 587 PIC16(L)F19195/6/7 35.1 LCD Registers The LCD controller is made up of the following registers: • LCD Control Register (LCDCON) • LCD Phase Register (LCDPS) • Two LCD Voltage Control Registers (LCDVCON1 and LCDVCON2) • LCD Internal Reference Ladder Control Register (LCDRL) • LCD Reference Voltage/Contrast Control Register (LCDCST) • Six LCD Segment Enable Registers (LCDSE5:LCDSE0) • 48 LCD Data Registers (LCDDATA47:LCDDATA0) The LCDCON register, shown in Register 35-1, controls the overall operation of the module. Once the module is configured, the LCDEN (LCDCON) bit is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN (LCDCON) bit. The LCDPS register, shown in Register 35-2, configures the LCD clock source prescaler and the type of waveform: Type-A or Type-B. For details on these features, see Section 35.3 “LCD Clock Source Selection” and Section 35.12 “LCD Waveform Generation”. TABLE 35-2: 35.2 LCD Segment Pins Configuration The LCDSEx registers are used to configure the PORT pin functions. Setting the segment enable bit for a particular segment configures that pin as an LCD driver and overrides all PPS options along with all other nonLCD pin functions. Table 35-2 shows the six LCD Segment Enable registers, and the generic LCDSEx register is shown in Register 35-3. Once the module has been initialized for the LCD panel, the individual bits of the LCDDATAx registers can be cleared or set to represent a clear or dark pixel, depending upon on whether the display produces a positive or negative image. Specific subsets of LCDDATAx registers are used with specific segments and common signal combinations. Each bit represents a unique combination of a specific segment associated with a specific common. Once the module has been initialized for the LCD panel, the individual bits of the LCDDATAx registers can be cleared or set to represent a clear or dark pixel, depending upon whether the display produces a positive or negative image. Specific subsets of LCDDATAx registers are used with specific segments and common signal combinations. Each bit represents a unique combination of a specific segment associated with a specific common. Individual bits of the LCDDATAx register are named by the convention, “SxxCy”, with “xx” representing the segment number and “y” as the common number. LCDSEx REGISTERS AND ASSOCIATED SEGMENTS Register Segments LCDSE0 SEG 7:SEG 0 LCDSE1 SEG 15:SEG 8 LCDSE2 SEG 23:SEG 16 LCDSE3 SEG 31:SEG 24 LCDSE4 SEG 39:SEG 32 LCDSE5 SEG 45:SEG40  2017-2021 Microchip Technology Inc. DS40001873E-page 588 PIC16(L)F19195/6/7 TABLE 35-3: Register LCDDATAX REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDDATA0 SEG7 COM0 SEG6 COM0 SEG5 COM0 SEG4 COM0 SEG3 COM0 SEG2 COM0 SEG1 COM0 LCDDATA1 SEG15 COM0 SEG14 COM0 SEG13 COM0 SEG12 COM0 SEG11 COM0 SEG10 COM0 SEG9 COM0 SEG0 COM0 SEG8 COM0 LCDDATA2 SEG23 COM0 SEG22 COM0 SEG21 COM0 SEG20 COM0 SEG19 COM0 SEG18 COM0 SEG17 COM0 SEG16 COM0 LCDDATA3 SEG31 COM0 SEG30 COM0 SEG29 COM0 SEG28 COM0 SEG27 COM0 SEG26 COM0 SEG25 COM0 SEG24 COM0 LCDDATA4 SEG39 COM0 SEG38 COM0 SEG37 COM0 SEG36 COM0 SEG35 COM0 SEG34 COM0 SEG33 COM0 SEG32 COM0 LCDDATA5 SEG45 COM0 SEG44 COM0 SEG43 COM0 SEG42 COM0 SEG41 COM0 SEG40 COM0 LCDDATA6 SEG7 COM1 — SEG6 COM1 — SEG5 COM1 SEG4 COM1 SEG3 COM1 SEG2 COM1 SEG1 COM1 SEG0 COM1 LCDDATA7 SEG15 COM1 SEG14 COM1 SEG13 COM1 SEG12 COM1 SEG11 COM1 SEG10 COM1 SEG9 COM1 SEG8 COM1 LCDDATA8 SEG23 COM1 SEG22 COM1 SEG21 COM1 SEG20 COM1 SEG19 COM1 SEG18 COM1 SEG17 COM1 SEG16 COM1 SEG24 COM1 LCDDATA9 SEG31 COM1 SEG30 COM1 SEG29 COM1 SEG28 COM1 SEG27 COM1 SEG26 COM1 SEG25 COM1 LCDDATA10 SEG39 COM1 SEG38 COM1 SEG37 COM1 SEG36 COM1 SEG35 COM1 SEG34 COM1 SEG33 COM1 SEG32 COM1 LCDDATA11 — — SEG45 COM1 SEG44 COM1 SEG43 COM1 SEG42 COM1 SEG41 COM1 SEG40 COM1 SEG0 COM2 LCDDATA12 SEG7 COM2 SEG6 COM2 SEG5 COM2 SEG4 COM2 SEG3 COM2 SEG2 COM2 SEG1 COM2 LCDDATA13 SEG15 COM2 SEG14 COM2 SEG13 COM2 SEG12 COM2 SEG11 COM2 SEG10 COM2 SEG9 COM2 SEG8 COM2 LCDDATA14 SEG23 COM2 SEG22 COM2 SEG21 COM2 SEG20 COM2 SEG19 COM2 SEG18 COM2 SEG17 COM2 SEG16 COM2 LCDDATA15 SEG31 COM2 SEG30 COM2 SEG29 COM2 SEG28 COM2 SEG27 COM2 SEG26 COM2 SEG25 COM2 SEG24 COM2 LCDDATA16 SEG39 COM2 SEG38 COM2 SEG37 COM2 SEG36 COM2 SEG35 COM2 SEG34 COM2 SEG33 COM2 SEG32 COM2 LCDDATA17 SEG45 COM2 SEG44 COM2 SEG43 COM2 SEG42 COM2 SEG41 COM2 SEG40 COM2 LCDDATA18 SEG7 COM3 — SEG6 COM3 — SEG5 COM3 SEG4 COM3 SEG3 COM3 SEG2 COM3 SEG1 COM3 SEG0 COM3 LCDDATA19 SEG15 COM3 SEG14 COM3 SEG13 COM3 SEG12 COM3 SEG11 COM3 SEG10 COM3 SEG9 COM3 SEG8 COM3 LCDDATA20 SEG23 COM3 SEG22 COM3 SEG21 COM3 SEG20 COM3 SEG19 COM3 SEG18 COM3 SEG17 COM3 SEG16 COM3 LCDDATA21 SEG31 COM3 SEG30 COM3 SEG29 COM3 SEG28 COM3 SEG27 COM3 SEG26 COM3 SEG25 COM3 SEG24 COM3 LCDDATA22 SEG39 COM3 SEG38 COM3 SEG37 COM3 SEG36 COM3 SEG35 COM3 SEG34 COM3 SEG33 COM3 SEG32 COM3 LCDDATA23 SEG45 COM3 SEG44 COM3 SEG43 COM3 SEG42 COM3 SEG41 COM3 SEG40 COM3 LCDDATA24 SEG7 COM4 — SEG6 COM4 — SEG5 COM4 SEG4 COM4 SEG3 COM4 SEG2 COM4 SEG1 COM4 SEG0 COM4 LCDDATA25 SEG15 COM4 SEG14 COM4 SEG13 COM4 SEG12 COM4 SEG11 COM4 SEG10 COM4 SEG9 COM4 SEG8 COM4 LCDDATA26 SEG23 COM4 SEG22 COM4 SEG21 COM4 SEG20 COM4 SEG19 COM4 SEG18 COM4 SEG17 COM4 SEG16 COM4 LCDDATA27 SEG31 COM4 SEG30 COM4 SEG29 COM4 SEG28 COM4 SEG27 COM4 SEG26 COM4 SEG25 COM4 SEG24 COM4 LCDDATA28 SEG39 COM4 SEG38 COM4 SEG37 COM4 SEG36 COM4 SEG35 COM4 SEG34 COM4 SEG33 COM4 SEG32 COM4 LCDDATA29 SEG45 COM4 SEG44 COM4 SEG43 COM4 SEG42 COM4 SEG41 COM4 SEG40 COM4 LCDDATA30 SEG7 COM5 — SEG6 COM5 — SEG5 COM5 SEG4 COM5 SEG3 COM5 SEG2 COM5 SEG1 COM5 SEG0 COM5 LCDDATA31 SEG15 COM5 SEG14 COM5 SEG13 COM5 SEG12 COM5 SEG11 COM5 SEG10 COM5 SEG9 COM5 SEG8 COM5 LCDDATA32 SEG23 COM5 SEG22 COM5 SEG21 COM5 SEG20 COM5 SEG19 COM5 SEG18 COM5 SEG17 COM5 SEG16 COM5 LCDDATA33 SEG31 COM5 SEG30 COM5 SEG29 COM5 SEG28 COM5 SEG27 COM5 SEG26 COM5 SEG25 COM5 SEG24 COM5 LCDDATA34 SEG39 COM5 SEG38 COM5 SEG37 COM5 SEG36 COM5 SEG35 COM5 SEG34 COM5 SEG33 COM5 SEG32 COM5 LCDDATA35 SEG45 COM5 SEG44 COM5 SEG43 COM5 SEG42 COM5 SEG41 COM5 SEG40 COM5 LCDDATA36 SEG7 COM6 — SEG6 COM6 — SEG5 COM6 SEG4 COM6 SEG3 COM6 SEG2 COM6 SEG1 COM6 SEG0 COM6 LCDDATA37 SEG15 COM6 SEG14 COM6 SEG13 COM6 SEG12 COM6 SEG11 COM6 SEG10 COM6 SEG9 COM6 SEG8 COM6 LCDDATA38 SEG23 COM6 SEG22 COM6 SEG21 COM6 SEG20 COM6 SEG19 COM6 SEG18 COM6 SEG17 COM6 SEG16 COM6 LCDDATA39 SEG31 COM6 SEG30 COM6 SEG29 COM6 SEG28 COM6 SEG27 COM6 SEG26 COM6 SEG25 COM6 SEG24 COM6 LCDDATA40 SEG39 COM6 SEG38 COM6 SEG37 COM6 SEG36 COM6 SEG35 COM6 SEG34 COM6 SEG33 COM6 SEG32 COM6 LCDDATA41 SEG45 COM6 SEG44 COM6 SEG43 COM6 SEG42 COM6 SEG41 COM6 SEG40 COM6 LCDDATA42 SEG7 COM7 — SEG6 COM7 — SEG5 COM7 SEG4 COM7 SEG3 COM7 SEG2 COM7 SEG1 COM7 SEG0 COM7 LCDDATA43 SEG15 COM7 SEG14 COM7 SEG13 COM7 SEG12 COM7 SEG11 COM7 SEG10 COM7 SEG9 COM7 SEG8 COM7 LCDDATA44 SEG23 COM7 SEG22 COM7 SEG21 COM7 SEG20 COM7 SEG19 COM7 SEG18 COM7 SEG17 COM7 SEG16 COM7 LCDDATA45 SEG31 COM7 SEG30 COM7 SEG29 COM7 SEG28 COM7 SEG27 COM7 SEG26 COM7 SEG25 COM7 SEG24 COM7 LCDDATA46 SEG39 COM7 SEG38 COM7 SEG37 COM7 SEG36 COM7 SEG35 COM7 SEG34 COM7 SEG33 COM7 SEG32 COM7 LCDDATA47 — — SEG45 COM7 SEG44 COM7 SEG43 COM7 SEG42 COM7 SEG41 COM7 SEG40 COM7  2017-2021 Microchip Technology Inc. DS40001873E-page 589 PIC16(L)F19195/6/7 35.3 LCD Clock Source Selection The LCD driver module has two possible clock sources: • Secondary Oscillator (SOSC) • Low-Frequency Internal Oscillator (LFINTOSC) The SOSC will supply 1 kHz to the LCD module when a 32.768 kHz crystal is used. The LFINTOSC clock source is a 31.25 kHz internal oscillator that provides approximately 1 kHz to the LCD module. These clock sources may be used to continue running the LCD while the processor is in Sleep. The clock sources are selected through the bits, CS (LCDCON4). 35.3.1 LCD PRESCALER A 4-bit prescaler is provided for the LCD clock. The prescaler is not directly readable or writable. Its value is set by configuring the LP bits (LCDPS) that determine the prescaler assignment and prescale ratio. Selectable prescaler values range from 1:1 through 1:16 in increments of one. Table 35-2 shows a simplified diagram of the LCD clock generation block. FIGURE 35-2: LCD CLOCK GENERATION SOSC 32.768 kHz LFINTOSC 31 kHz 1 ÷4 Static ÷2 1/2 0 MUX CS LCDCON LMUX LCDCON  2017-2021 Microchip Technology Inc. 4-Bit Prog Prescaler LP LCDPS ÷32 COM7 :::::::::: COM1 COM0 Rev. 10-000317A 10/18/2016 ÷1, 2, 3....8 Ring Counter LMUX LCDCON DS40001873E-page 590 PIC16(L)F19195/6/7 35.4 LCD Bias Types 35.5 The LCD module will operate in one of three different bias types depending upon the number of commons on the display: Resistor Biasing The LCD module is capable of generating bias voltages using the built in internal resistor ladder. Rather than adding additional external circuitry to derive bias voltages, the internal resistor ladders are available and can be configured to generate the bias voltages needed. Table 35-4 shows the total resistance values for each of the resistor ladders. • Static bias (two voltage levels: VSS and VDD or Boost Pump Voltage) • 1/2 bias (three voltage levels: VSS, 1/2 VDD or Boost Pump Voltage and VDD or Boost Pump Voltage) • 1/3 bias (four voltage levels: VSS, 1/3 VDD or Boost Pump Voltage, 2/3 VDD or Boost Pump Voltage and VDD or Boost Pump Voltage) Driving a display using the internal resistor ladder is recommended if the resistance specifications meet the drive requirements of the LCD panel being used, otherwise a specifically calculated external resistor ladder may need to be used to meet the drive requirements of the display. LCD bias voltages can be generated with internal resistor ladders, internal bias generator or external resistor ladder. 35.5.1 INTERNAL RESISTOR BIASING The internal resistor ladder network consists of three separate ladders. Disabling the internal reference ladder disconnects all three of the ladders, allowing external and internal boost pump voltages to be supplied. Depending on the total resistance from the resistor ladders, the biasing can be classified as low, medium or high power. Table 35-4 shows the total resistance of each of the internal resistor ladders. Figure 35-4 shows the internal resister ladder connections. When the internal resistor ladder is selected, the bias voltage can either be derived from VDD, the LCD charge pump, the 3x FVR or externally supplied, depending on the LCDVSRC setting. This LCD module includes an LCD reference voltage and contrast control ladder that is tuned to the nominal resistance of the reference ladder. This reference ladder can be used to provide software contrast control by configuring the LCDCST bits of the LCDREF register. TABLE 35-4: INTERNAL RESISTANCE LADDER POWER MODES Power Mode Nominal Resistance of Entire Ladder IDD Low 3.3 MΩ 1 µA Medium 300 kΩ 10 µA High 30 kΩ 100 µA  2017-2021 Microchip Technology Inc. DS40001873E-page 591 PIC16(L)F19195/6/7 35.5.2 AUTOMATIC POWER MODE SWITCHING Mode A is active. Power Mode B is active for the remaining time before the segments or commons change again. Each segment within an LCD display can be perceived electrically like a small capacitor. Due to this fact, power is mainly consumed during the transition periods when voltage is being supplied to the segments. In order to manage total current consumption, the LCD reference ladder can be used in different power modes during these transition periods. Control of the LCD reference ladder is done through the LCDRL register (see Register 35-7). As shown in Figure 35-3, there are 32 counts in a single segment time. Type-A can be chosen during the time when the wave form is in transition. Type-B can be used when the clock is stable or not in transition. By using this feature of automatic power switching using Type-A/Type-B waveforms, the power consumption can be optimized for a given contrast. As shown in Figure 35-3, Power Mode A is active for a programmable amount of time, beginning when the LCD segment waveform is transitioning. The LRLAT bits (LCDRL) determines how long FIGURE 35-3: LCD REFERENCE LADDER POWER MODE SWITCHING DIAGRAM Single Segment Time lcd_32x_clk cnt 'H00 'H01 'H02 'H03 'H04 'H05 'H06 'H07 'H1E 'H1F 'H00 'H01 lcd_clk 'H3 LRLAT Segment Data LRLAT Power Mode Power Mode A  2017-2021 Microchip Technology Inc. Power Mode B Mode A DS40001873E-page 592 PIC16(L)F19195/6/7 35.5.3 CONTRAST CONTROL The LCD contrast control circuit consists of a 7-tap resistor ladder, controlled by the LCDCSTx bits of the LCDREF register (see Figure 35-4). FIGURE 35-4: INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM 7 Stages VDD R R R R Analog MUX 7 0 To Top of Reference Ladder LCDCST 3 Internal Reference 35.6 35.6.1 Contrast Control Bias Generation INTERNAL REFERENCE An internal reference for the LCD bias voltage can be enabled under firmware control. When enabled, the source of this voltage can be VDD, the LCD charge pump or 3x FVR. When no internal reference is selected, the LCD contrast control circuit is disabled and LCD bias must be provided externally. Whenever the LCD module is inactive (LCDA = 0), the internal reference will be turned off. 35.6.2 VLCDx PINS The VLCD3(1), VLCD2 and VLCD1 pins provide the ability for an external LCD bias network to be used instead of the internal ladder. Use of the VLCDx pins does not prevent use of the internal ladder. Note 1: When not in use, VLCD3 needs to be floated and not tied to ground. 35.6.3 LCD BIAS GENERATION The LCD driver module is capable of generating the required bias voltages for LCD operation with a minimum of external components. This includes the ability to generate the different voltage levels required by the different bias types that are required by the LCD. The  2017-2021 Microchip Technology Inc. driver module can also provide bias voltages, both above and below microcontroller VDD, through the use of an on-chip LCD charge pump. 35.6.4 LCD CHARGE PUMP The purpose of the LCD charge pump is to provide proper bias voltage and good contrast for the LCD, regardless of VDD levels. This module contains a charge pump and internal voltage reference. The charge pump can be configured by using external components to boost bias voltage above VDD. It can also operate a display at a constant voltage below VDD. The charge pump can also be selectively disabled to allow bias voltages to be generated by an external resistor network. The LCD charge pump is controlled through the LCDVCONx registers. 35.6.5 VLCD3 MONITORING The ADC can be used to measure the VLCD3 voltage via a VLCD3 divided by 4 channel on the ADC. This feature is useful when active adjustment of the LCDCST or BIAS bits need to be made to account of contrast changes due to extreme temperatures and/or a high number of large active pixels. See Section 19.0 “Analog-to-Digital Converter with Computation (ADC2) Module” for additional details. DS40001873E-page 593 PIC16(L)F19195/6/7 35.7 BIAS CONFIGURATIONS 35.7.2 PIC16(L)F19195/6/7 devices have eight distinct circuit configurations for LCD bias generation: • LCD voltage supplied from External Resistor Ladder • LCD voltage supplied from Charge Pump + Internal Resistor Ladder • LCD voltage supplied from Charge Pump + External Resistor Ladder • LCD voltage supplied from Charge Pump Only (no Resistor ladder) • LCD voltage supplied from Internal Resistor Ladder + External Capacitors + VDD for VLCD3 • LCD voltage supplied from Internal Resistor Ladder + External Capacitors + External VLCD3 • LCD voltage supplied from Internal Resistor Ladder + FVR for VLCD3 • LCD voltage supplied from Internal Resistor Ladder + VDD for VLCD3 • LCD voltage supplied from Internal Resistor Ladder + External VLCD3 35.7.1 LCD CHARGE PUMP When the LCD charge pump feature is enabled, it allows the regulator to generate voltages up to 3.5V in 3V mode, and up to 5.01V in 5V mode (as measured at VLCD3). The LCD charge pump uses a flyback capacitor connected between CFLY1 and CFLY2, as well as output hold and storage capacitors on VLCD1 through VLCD3, to obtain the required voltage boost (Figure 35-5). The output voltage (VBIAS) is the difference of the potential between VLCD3 and GND. It is set by the BIAS bits which adjust the offset between VLCD3 and VSS. The flyback capacitor (CFLY) acts as a charge storage element for large LCD loads. This mode is useful in those cases where the voltage requirements of the LCD are higher than the microcontroller’s VDD and vice versa. The integrated LCD charge pump also makes this LCD module ideal for battery powered LCD applications to help ensure that the contrast of the display does not degrade as the batteries discharge over time. It also permits software control of the display’s contrast, by adjustment of bias voltage, by changing the value of the BIAS bits. LCD BIAS TYPES PIC16(L)F19195/6/7 family devices support three bias types, based on the waveforms generated to control segments and commons: • Static (two discrete levels) • 1/2 Bias (three discrete levels) • 1/3 Bias (four discrete levels) The use of different waveforms in driving the LCD is discussed in more detail in Section 35.12 “LCD Waveform Generation”. TABLE 35-5: LCD MODES WITH INTERNAL CHARGE PUMP Supported LCD Modes Charge Pump Mode Resistor Mode Bias Mode Internal No Resistor Note 1: 3V 3V Low Current 5V 5V Low Current Static Supported Supported Supported Supported 1/2 Supported Supported Supported Supported 1/3 Supported Supported Supported Supported Static Supported Supported Supported Supported 1/2 Not Supported(1) Supported Not Supported(1) Not Supported(1) 1/3 Supported Not Supported(1) Not Supported(1) Supported The mode is not supported as the required voltages on VLCDx pins driving the VLCDx voltages does not coincide with what is required for the charge pump to operate.  2017-2021 Microchip Technology Inc. DS40001873E-page 594 PIC16(L)F19195/6/7 FIGURE 35-5: LCD REGULATOR CONNECTIONS FOR LCD VOLTAGE SUPPLIED FROM CHARGE PUMP WITH AND WITHOUT INTERNAL RESISTOR LADDER PIC16(L)F191xx Rev. 10-000320A 2/17/2017 CFLY1 1.0µF(1) CFLY2 VLCD3 0.27µF(1) VLCD2 0.27µF (1)(2) VLCD1 0.27µF(1)(2)(3)(4) Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer. 2: When EN5V = 0 and LPEN = 1, this pin can be used as a GPIO and the external capacitor is not required. 3: When EN5V = 1 and LPEN = 1, this pin can be used as a GPIO and the external capacitor is not required. 4: EN5V = 0 and LPEN = 0  2017-2021 Microchip Technology Inc. DS40001873E-page 595 PIC16(L)F19195/6/7 35.7.3 LCD VOLTAGE SUPPLIED FROM EXTERNAL RESISTOR LADDER range; no software adjustment is possible. This configuration is also used in instances where the current requirements of the LCD panel exceed the capacity of the charge pump and the high power (HP) internal resistor ladder. In this mode, the LCD charge pump is completely disabled. The LCD bias levels are tied to VDD and are generated using an external divider. The difference is that the internal voltage reference is also disabled and the bottom of the ladder is tied to ground (VSS); see Figure 35-6. The value of the resistors, and the difference between VSS and VDD, determine the contrast FIGURE 35-6: Depending on the bias type required, resistors are connected between some or all of the pins. A potentiometer can also be connected between VLCD3 and VDD to allow for hardware controlled contrast adjustment. CONNECTIONS FOR LCD VOLTAGE SUPPLIED FROM EXTERNAL LADDER, STATIC, 1/2 AND 1/3 BIAS MODES (LCDVSRC = 1000) Rev. 10-000 323B 6/14/201 9 PIC16(L)F191xx 1/3 BIAS MODE 1/2 BIAS MODE STATIC BIAS MODE CFLY1(2) CFLY2(2) VDD VDD VDD 1kΩ(1) 1kΩ(1) 1kΩ(1) 1kΩ(1) 1kΩ(1) 1kΩ(1) 1kΩ(1) 1kΩ(1) VLCD3 VLCD2(3)(4) VLCD1(4) 1kΩ(1) Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer. 2: It can be used as GPIO. 3: In 1/2 Bias mode, this pin can be used a GPIO. 4: In Static mode, this pin can be used a GPIO.  2017-2021 Microchip Technology Inc. DS40001873E-page 596 PIC16(L)F19195/6/7 35.7.4 INTERNAL RESISTOR LADDER WITH EXTERNAL CAPACITORS In this configuration, the user can use the internal resistor ladders to generate the LCD bias levels, and use external capacitors to guard again burst currents. It is recommend the user utilize external capacitors when driving large glass panels with large pixels and a high pixel count. The external capacitors will help dampen current spikes during segment switching. Contrast is adjusted using the LCDCST bits. The CFLYx pins are available as GPIO since the charge pump is not being used in this configuration. See Figure 35-7 for supported connections. External capacitors can be used when voltage to the internal resistor ladder is supplied by VDD (LCDVSRC = 0101) or an external source (LCDVSRC = 0100). When supplying an external voltage to the internal resistor ladder the external capacitors should be limited to VLCD2, and VLCD3.  2017-2021 Microchip Technology Inc. DS40001873E-page 597 PIC16(L)F19195/6/7 FIGURE 35-7: CONNECTIONS FOR LCD VOLTAGE SUPPLIED EXTERNALLY OR FROM VDD ALONG WITH INTERNAL RESISTOR LADDER AND EXTERNAL CAPACITORS, STATIC, 1/2 AND 1/3 BIAS MODES (LCDVSRC = 0100, 0101) Rev. 10-000 324A 5/15/201 9 PIC16(L)F191xx 1/3 BIAS MODE 1/2 BIAS MODE STATIC BIAS MODE CFLY1(2) CFLY2(2) EXT(4) VLCD3 0.27µF(1) 0.27µF(1) 0.27µF(1) 0.27µF(1) 0.27µF(1) VLCD2(3) VLCD1 0.27µF(1) Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer. 2: It can be used as GPIO. 3: In Static mode, this pin can be used a GPIO. 4: LCDVSRC = 0100. 35.7.5 INTERNAL RESISTOR When driving a small LCD load such as an LCD with a small pixel count and small pixels, the user can use the internal resistor ladder to generate the LCD bias levels. The top of the internal ladder can be supplied by the FVR, VDD and externally. See Register 35-6 for additional details.  2017-2021 Microchip Technology Inc. DS40001873E-page 598 PIC16(L)F19195/6/7 35.8 LCD Multiplex Types The LCD driver module can be configured into eight multiplex types: • • • • • • • • Static (only COM0 used) 1/2 multiplex (COM0 and COM1 are used) 1/3 multiplex (COM0, COM1 and COM2 are used) 1/4 multiplex (COM0, COM1, COM2 and COM3 are used) 1/5 multiplex (COM0, COM1, COM2, COM3 and COM4 are used) 1/6 multiplex (COM0, COM1, COM2, COM3, COM4 and COM5 are used) 1/7 multiplex (COM0, COM1, COM2, COM3, COM4, COM5 and COM6 are used) 1/8 multiplex (COM0, COM1, COM2, COM3, COM4, COM5, COM6 and COM7 are used) The LMUX setting (LCDCON) determines the function of the COM pins. (For details, see Table 35-6). If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, the TRIS setting of that pin is overridden. Note: On a Power-on Reset, the LMUX bits are ‘0000’. TABLE 35-6: LMUX 1000 0111 0110 0101 0100 0011 0010 0001 0000 COM PIN FUNCTIONS COM7 Pin COM6 Pin COM5 Pin COM4 Pin COM3 Pin COM2 Pin COM1 Pin COM0 Pin COM7 I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin COM6 COM6 I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin  2017-2021 Microchip Technology Inc. COM5 COM5 COM5 I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin COM4 COM4 COM4 COM4 I/O Pin I/O Pin I/O Pin I/O Pin I/O Pin COM3 COM3 COM3 COM3 COM3 I/O Pin I/O Pin I/O Pin I/O Pin COM2 COM2 COM2 COM2 COM2 COM2 I/O Pin I/O Pin I/O Pin COM1 COM1 COM1 COM1 COM1 COM1 COM1 I/O Pin I/O Pin COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 I/O Pin DS40001873E-page 599 PIC16(L)F19195/6/7 35.9 Segment Enables 35.10 Pixel Control The LCDSENx registers are used to select the pin function for each segment pin. The selection allows the designated SEG pins to be configured as LCD segment driver pins. To configure the pin as a segment pin, the corresponding bits in the LCDSENx registers must be set to ‘1’. The LCDDATAx registers contain bits that define the state of each pixel. Each bit defines one unique pixel. Table 35-2 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSENx registers overrides any bit settings in the corresponding TRIS register. 35.11 LCD Frame Frequency Note: On a Power-on Reset, these pins are configured as digital I/O. TABLE 35-7: FRAME FREQUENCY FORMULAS Multiplex Note: The rate at which the COM and SEG outputs change is called the LCD frame frequency. Table 35-7 shows the frame frequency calculations while operating within the different multiplex modes. Static (‘0001’) 1/2 (‘0010’) 1/3 (‘0011’) 1/4 (‘0100’) 1/5 (‘0101’) 1/6 (‘0110’) 1/7 (‘0111’) 1/8 (‘1000’) The clock source is SOSC/32 or LFINTOSC/32. 35.12 LCD Waveform Generation LCD waveform generation is based on the theory that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. Frame Frequency = Clock Source/(4 x 1 x (LP + 1)) Clock Source/(2 x 2 x (LP + 1)) Clock Source/(1 x 3 x (LP + 1)) Clock Source/(1 x 4 x (LP + 1)) Clock Source/(1 x 5 x (LP + 1)) Clock Source/(1 x 6 x (LP + 1)) Clock Source/(1 x 7 x (LP + 1)) Clock Source/(1 x 8 x (LP + 1)) Figure 35-8 through Figure 35-15 provide waveforms for static, half-multiplex, one-third multiplex and quarter multiplex drives for Type-A and Type-B waveforms. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and can take only one of the two rms values. The higher rms value will create a dark pixel and a lower rms value will create a clear pixel. As the number of commons increases, the delta between the two rms values decreases. The delta represents the maximum contrast that the display can have. The LCDs can be driven by two types of waveforms: Type-A and Type-B. In a Type-A waveform, the phase changes within each common type, whereas a Type-B waveform’s phase changes on each frame boundary. Thus, Type-A waveforms maintain 0 VDC over a single frame, whereas Type-B waveforms take two frames. Note: If Sleep has to be executed with LCD Sleep enabled (SLPEN (LCDCON) = 1), care must be taken to execute Sleep only when VDC on all the pixels is ‘0’.  2017-2021 Microchip Technology Inc. DS40001873E-page 600 PIC16(L)F19195/6/7 FIGURE 35-8: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE V1 COM0 V0 COM0 V1 SEG0 V0 V1 SEG1 SEG0 SEG2 SEG7 SEG6 SEG5 SEG4 SEG3 SEG1 V0 V1 V0 COM0-SEG0 -V1 COM0-SEG1 V0 1 Frame  2017-2021 Microchip Technology Inc. DS40001873E-page 601 PIC16(L)F19195/6/7 FIGURE 35-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM1 V2 COM0 COM1 V1 V0 V2 V1 SEG0 V0 SEG0 SEG1 SEG2 SEG3 V2 V1 SEG1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame  2017-2021 Microchip Technology Inc. DS40001873E-page 602 PIC16(L)F19195/6/7 FIGURE 35-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 V1 COM0 COM1 V0 COM0 V2 COM1 V1 V0 V2 SEG0 V1 V2 SEG1 SEG0 SEG1 SEG2 SEG3 V0 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames  2017-2021 Microchip Technology Inc. DS40001873E-page 603 PIC16(L)F19195/6/7 FIGURE 35-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 SEG2 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 1 Frame  2017-2021 Microchip Technology Inc. DS40001873E-page 604 PIC16(L)F19195/6/7 FIGURE 35-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 2 Frames  2017-2021 Microchip Technology Inc. DS40001873E-page 605 PIC16(L)F19195/6/7 FIGURE 35-13: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 COM2 COM1 SEG0 SEG1 COM0 1 Frame  2017-2021 Microchip Technology Inc. DS40001873E-page 606 PIC16(L)F19195/6/7 FIGURE 35-14: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 COM2 COM1 SEG0 SEG1 COM0 2 Frames  2017-2021 Microchip Technology Inc. DS40001873E-page 607 PIC16(L)F19195/6/7 FIGURE 35-15: TYPE-B WAVEFORMS IN 1/8 MUX, 1/3 BIAS DRIVE COM4 COM3 COM5 COM0 COM7 COM2 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM6 COM1 COM0 COM7 SEG0 SEG0 COM0 - SEG0 COM1 - SEG0  2017-2021 Microchip Technology Inc. V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3 DS40001873E-page 608 PIC16(L)F19195/6/7 35.13 LCD Interrupts When the LCD driver is running with Type-B waveforms, and the LMUX bits are not equal to ‘0001’, the following issues may arise. The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame, which produces a visually crisp transition of the image. Since the DC voltage on the pixel takes two frames to maintain 0V, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel. This interrupt can also be used to synchronize external events to the LCD. For example, the interface to an external segment driver can be synchronized for segment data updates to the LCD frame. Because of this, using Type-B waveforms requires synchronizing the LCD pixel updates to occur within a subframe after the frame interrupt. A new frame is defined as beginning at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (TFINT), as shown in Figure 35-16. To correctly sequence writing in Type-B, the interrupt only occurs on complete phase intervals. If the user attempts to write when the write is disabled, the WERR bit (LCDCON) is set. The LCD controller will begin to access the next frame between the interrupt and when the controller accesses the data (TFWR). New data must be written within TFWR, as this is when the LCD controller will begin to access the data for the next frame. FIGURE 35-16: Note: The interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex (static) is selected. EXAMPLE WAVEFORMS AND INTERRUPT TIMING IN QUARTER DUTY CYCLE DRIVE LCD Interrupt Occurs Controller Accesses Next Frame Data COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 V3 V2 V1 V0 COM3 2 Frames TFINT Frame Boundary Frame Boundary TFWR Frame Boundary TFWR = TFRAME/2 * (LMUX + 1) + TCY/2 TFINT = (TFWR/2 – (2 TCY + 40 ns)) Minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns) (TFWR/2 – (1 TCY + 40 ns)) Maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)  2017-2021 Microchip Technology Inc. DS40001873E-page 609 PIC16(L)F19195/6/7 35.14 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by the SLPEN bit (LCDCON). Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very Low-Current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 35-17 shows this operation. FIGURE 35-17: The LCD module current consumption will not decrease in this mode, but the overall consumption of the device will be lower due to shut down of the core and other peripheral functions. To ensure that no DC component is introduced on the panel, the SLEEP instruction should be executed immediately after an LCD frame boundary. The LCD interrupt can be used to determine the frame boundary. See Section 35.13 “LCD Interrupts” for the formulas to calculate the delay. If a SLEEP instruction is executed and SLPEN = 0, the module will continue to display the current contents of the LCDDATA registers. The LCD data cannot be changed. SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS = 00 V3 V2 V1 COM0 V0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 SEG0 2 Frames SLEEP Instruction Execution  2017-2021 Microchip Technology Inc. Wake-up DS40001873E-page 610 PIC16(L)F19195/6/7 REGISTER 35-1: LCDCON: LCD CONTROL REGISTER R/W-0 R/W-0 HS/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDEN SLPEN WERR CS LMUX3 LMUX2 LMUX1 LMUX0 bit 7 bit 0 Legend: C = Clearable bit HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 LCDEN: LCD Enable bit 1 = LCD module is enabled 0 = LCD module is disabled bit 6 SLPEN: LCD Display Sleep-Enabled bit 1 = Module will stop driving in Sleep 0 = Module will continue driving in Sleep bit 5 WERR: LCD Write Failed Error bit(1) 1 = Write failure to LCDDATA register occurred (must be reset in software) 0 = No LCD write error bit 4 CS: Clock Source Select bit 1 = SOSC Selected 0 = LFINTOSC Selected bit 3-0 LMUX: Common Selection bits. Specifies the number of commons(2) LMUX Multiplex Bias 0000 0001 0010 0011 0100 0101 0110 0111 1000 All COMs off Static (COM0) 1/2 MUX (COM) 1/3 MUX (COM) 1/4 MUX (COM) 1/5 MUX (COM) 1/6 MUX (COM) 1/7 MUX (COM) 1/8 MUX (COM) — Static 1/2 1/3 1/3 1/3 1/3 1/3 1/3 Note 1: Bit can only be set by hardware and only cleared in software by writing to zero. 2: Cannot be changed when LCDEN = 1.  2017-2021 Microchip Technology Inc. DS40001873E-page 611 PIC16(L)F19195/6/7 REGISTER 35-2: LCDPS: LCD PHASE REGISTER R/W-0 R-0 R-0 R-0 WFT — LCDA WA R/W-0 R/W-0 R/W-0 R/W-0 LP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) bit 6 Reserved: Read as ‘0’ bit 5 LCDA: LCD Active Status bit 1 = LCD driver module is active 0 = LCD driver module is inactive bit 4 WA: LCD Write Allow Status bit This Status bit reflects the value of write_allow signal. 1 = Writes into the LCDDATAx registers are allowed 0 = Writes into the LCDDATAx registers are not allowed bit 3-0 LP: LCD Prescaler Select bits Work with LMUX bits to select frame clock prescaler value. 4-Bit Programmable Prescaler = (LP + 1) 1111 = 1:16 1110 = 1:15 1101 = 1:14 1100 = 1:13 1011 = 1:12 1010 = 1:11 1001 = 1:10 1000 = 1:9 0111 = 1:8 0110 = 1:7 0101 = 1:6 0100 = 1:5 0011 = 1:4 0010 = 1:3 0001 = 1:2 0000 = 1:1  2017-2021 Microchip Technology Inc. DS40001873E-page 612 PIC16(L)F19195/6/7 REGISTER 35-3: LCDSEx: LCD SEGMENT x ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n) SE(n) SE(n) SE(n) SE(n) SE(n) SE(n) SE(n) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SE(n+7):SE(n) Segment Enable bits For LCDSE0: n = 0-7 For LCDSE1: n = 8-15 For LCDSE2: n = 16-23 For LCDSE3: n = 24-31 For LCDSE4: n = 32-39 For LCDSE5: n = 40-47 1 = Segment function of the pin is enabled, digital I/O is disabled 0 = Segment function of the pin is disabled, digital I/O is enabled REGISTER 35-4: LCDDATAx: LCD DATA x REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEGxCOMy SEGxCOMy SEGxCOMy SEGxCOMy SEGxCOMy SEGxCOMy SEGxCOMy SEGxCOMy bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SEGxCOMy: Pixel On bits 1 = Pixel on 0 = Pixel off  2017-2021 Microchip Technology Inc. DS40001873E-page 613 PIC16(L)F19195/6/7 REGISTER 35-5: LCDVCON1: LCD VOLTAGE CONTROL 1 BITS R/W-0/0 R/W-0/0 R-0 R-0 R-0 R/W-0/0 R/W-0/0 R/W-0/0 LPEN EN5V — — — BIAS2 BIAS1 BIAS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 LPEN: LCD Charge Pump Low Power Enable (Low-Current (LC) mode enable) 1 = LCD Charge Pump is operating in Low-Current mode 0 = LCD Charge Pump is operating in Normal-Current mode bit 6 EN5V: 5V Range Enable bit 1 = The pump generates 5.0V voltage range 0 = The pump generates 3.6V voltage range bit 5-3 Reserved: Read as ‘0’ bit 2-0 BIAS: Boost Pump Voltage Output Control bits (Only valid when LCDVSRC = 100, 101, 110) When EN5V = 0 111 = Set boost pump output to 3.50V 110 = Set boost pump output to 3.40V 101 = Set boost pump output to 3.30V 100 = Set boost pump output to 3.20V 011 = Set boost pump output to 3.10V 010 = Set boost pump output to 3.00V 001 = Set boost pump output to 2.90V 000 = Set boost pump output to 2.80V When EN5V = 1 111 = Set boost pump output to 5.01V 110 = Set boost pump output to 4.83V 101 = Set boost pump output to 4.66V 100 = Set boost pump output to 4.48V 011 = Set boost pump output to 4.31V 010 = Set boost pump output to 4.13V 001 = Set boost pump output to 3.95V 000 = Set boost pump output to 3.78V  2017-2021 Microchip Technology Inc. DS40001873E-page 614 PIC16(L)F19195/6/7 REGISTER 35-6: LCDVCON2: LCD VOLTAGE CONTROL 2 BITS R/W-0/0 R-0 R-0 R-0 CPWDT — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 LCDVSRC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CPWDT: LCD Charge Pump Discharge Watchdog Disable 1 = The LCD CP Timer is disabled 0 = The LCD CP Timer is enabled bit 6-4 Reserved: Read as ‘0’ bit 2-0 LCDVSRC: LCD Voltage Source Control bits 1111-1010 = Reserved 1001 = LCD voltage supplied from Charge Pump + External Resistor Ladder(2)(3) 1000 = LCD voltage supplied from External Resistor Ladder(1)(4) 0111 = LCD voltage supplied from Charge Pump + Internal Resistor Ladder(2)(3) 0110 = LCD voltage supplied from Charge Pump Only (no Resistor ladder)(2)(3) 0101 = LCD voltage supplied from Internal Resistor Ladder + External Capacitors + VDD for VLCD3(1)(4) 0100 = LCD voltage supplied from Internal Resistor Ladder + External Capacitors + External VLCD3(1)(4) 0011 = LCD voltage supplied from Internal Resistor Ladder + FVR for VLCD3(4) 0010 = LCD voltage supplied from Internal Resistor Ladder + VDD for VLCD3(4) 0001 = LCD voltage supplied from Internal Resistor Ladder + External VLCD3(4) 0000 = All voltage sources are disabled Note 1: VLCD1/2/3 used for 1/3 BIAS, VLCD3/2 for 1/2 BIAS, VLCD3 for Static BIAS. 2: VLCD1 is only used when (EN5V = 1 and LPEN = 0). 3: Only valid when LCDPEN = 1. If selected when LCDPEN = 0, module will behave as if all sources are disabled. 4: Only valid when LCDPEN = 0. If selected when LCDPEN = 1, module will behave as if all sources are disabled.  2017-2021 Microchip Technology Inc. DS40001873E-page 615 PIC16(L)F19195/6/7 REGISTER 35-7: LCDRL: LCD INTERNAL REFERENCE LADDER CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 LRLAP1 LRLAP0 LRLBP1 LRLBP0 LCDIRI LRLAT2 LRLAT1 LRLAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 LRLAP: LCD Reference Ladder A Time Power Control bits During Time Interval A: 11 = Internal LCD reference is the High-Power (HP) ladder 10 = Internal LCD reference ladder is powered in Medium Power mode 01 = Internal LCD reference ladder is powered in Low-Power mode 00 = Internal LCD reference ladder is powered down and unconnected bit 5-4 LRLBP: LCD Reference Ladder B Time Power Control bits During Time Interval B: 11 = Internal LCD reference ladder is powered in High-Power mode 10 = Internal LCD reference ladder is powered in Medium Power mode 01 = Internal LCD reference ladder is powered in Low-Power mode 00 = Internal LCD reference ladder is powered down and unconnected bit 3 LCDIRI: LCD Internal Reference Buffer Idle Enable bit Allows the Internal reference band gap buffer to shut down when the LCD Reference Ladder is in Power mode ‘B’ 1 = When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal Reference Band Gap buffer is disabled 0 = The LCD Internal Reference Buffer ignores the LCD Reference Ladder power mode bit 2-0 LRLAT: LCD Reference Ladder A Time Interval Control bits Sets the number of 32 clock counts when the A Time Interval Power mode is active. For Type-A Waveforms (WFT = 0): 111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks 110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks 101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks 100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks 011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks 010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks 001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks 000 = Internal LCD reference ladder is always in B Power mode For Type-B Waveforms (WFT = 1): 111 = Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks 110 = Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks 101 = Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks 100 = Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks 011 = Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks 010 = Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks 001 = Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks 000 = Internal LCD reference ladder is always in B Power mode  2017-2021 Microchip Technology Inc. DS40001873E-page 616 PIC16(L)F19195/6/7 REGISTER 35-8: LCDREF: LCD REFERENCE VOLTAGE/CONTRAST CONTROL REGISTER R-0 R-0 R-0 R-0 R-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — LCDCST2 LCDCST1 LCDCST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’. bit 2-0 LCDCST: LCD Contrast Control bits(1) Selects the resistance of the LCD contrast control resistor ladder Bit Value Resistor ladder 000 = Contrast Control Bypassed (Maximum contrast). 001 = Contrast Control Resistor ladder is at 1/7th of maximum resistance 010 = Contrast Control Resistor ladder is at 2/7th of maximum resistance 011 = Contrast Control Resistor ladder is at 3/7th of maximum resistance 100 = Contrast Control Resistor ladder is at 4/7th of maximum resistance 101 = Contrast Control Resistor ladder is at 5/7th of maximum resistance 110 = Contrast Control Resistor ladder is at 6/7th of maximum resistance 111 = Contrast Control Resistor ladder is at maximum resistance (Minimum contrast) Note 1: This setting is only valid in Internal Resistance Ladder only modes.  2017-2021 Microchip Technology Inc. DS40001873E-page 617 PIC16(L)F19195/6/7 TABLE 35-8: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH LCD MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE — — — — — INTEDG 147 PIR8 LCDIF RTCCIF — — — SMT1PWAIF SMT1PRAIF SMT1IF 165 PIE8 LCDIE RTCCIE — — — SMT1PWAIE SMT1PRAIE SMT1IE 156 — SMT1MD LCDMD CLC4MD CLC3MD CLC2MD CLC1MD — 269 PMD5 LCDCON LCDEN SLPEN WERR CS LMUX 611 LCDPS WFT — LCDA WA LP 612 LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 613 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 613 LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 613 LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 613 LCDSE4 SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 613 LCDSE5 SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 613 LCDVCON1 LPEN EN5V — — — LCDVCON2 CPWDT — — — — — — — LCDREF LCDRL LRLAP LRLBP BIAS 614 LCDVSRC — LCDCST LCDIRI LRLAT 615 617 616 LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 613 LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 613 LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 613 LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 613 LCDDATA4 S39C0 S38C0 S37C0 S36C0 S35C0 S34C0 S33C0 S32C0 613 LCDDATA5 — — S45C0 S44C0 S43C0 S42C0 S41C0 S40C0 613 LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 613 LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 613 LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 613 LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 613 LCDDATA10 S39C1 S38C1 S37C1 S36C1 S35C1 S34C1 S33C1 S32C1 613 LCDDATA11 — — S45C1 S44C3 S43C1 S42C1 S41C1 S40C1 613 LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 613 LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 613 LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 613 LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 613 LCDDATA16 S39C2 S38C2 S37C2 S36C2 S35C2 S34C2 S33C2 S32C2 613 LCDDATA17 — — S45C2 S44C2 S43C2 S42C2 S41C2 S40C2 613 LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 613 LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 613 LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 613 LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 613 LCDDATA22 S39C3 S38C3 S37C3 S36C3 S35C3 S34C3 S33C3 S32C3 613 LCDDATA23 — — S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 613 LCDDATA24 S07C4 S06C4 S05C4 S04C4 S03C4 S02C4 S01C4 S00C4 613 LCDDATA25 S15C4 S14C4 S13C4 S12C4 S11C4 S10C4 S09C4 S08C4 613 LCDDATA26 S23C4 S22C4 S21C4 S20C4 S19C4 S18C4 S17C4 S16C4 613 LCDDATA27 S31C4 S30C4 S29C4 S28C4 S27C4 S26C4 S25C4 S24C4 613 LCDDATA28 S39C4 S38C4 S37C4 S36C4 S35C4 S34C4 S33C4 S32C4 613 LCDDATA29 — — S45C4 S44C4 S43C4 S42C4 S41C4 S32C4 613 LCDDATA30 S07C5 S06C5 S37C4 S04C5 S03C5 S02C5 S01C5 S00C5 613 LCDDATA31 S15C5 S14C5 S13C4 S12C5 S11C5 S10C5 S09C5 S08C5 613 LCDDATA32 S23C5 S22C5 S21C4 S20C5 S19C5 S18C5 S17C5 S16C5 613 LCDDATA33 S31C5 S30C5 S29C4 S28C5 S27C5 S26C5 S25C5 S24C5 613  2017-2021 Microchip Technology Inc. DS40001873E-page 618 PIC16(L)F19195/6/7 TABLE 35-8: SUMMARY OF REGISTERS ASSOCIATED WITH LCD MODULE (CONTINUED) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page S38C5 S37C4 S36C5 S35C5 S34C5 S33C5 S32C5 613 — S45C4 S44C5 S43C5 S42C5 S41C5 S40C5 613 S07C6 S06C6 S05C6 S04C6 S03C6 S02C6 S01C6 S00C6 613 LCDDATA37 S15C6 S14C6 S13C6 S12C6 S11C6 S10C6 S09C6 S08C6 613 LCDDATA38 S23C6 S22C6 S21C6 S20C6 S19C6 S18C6 S17C6 S16C6 613 LCDDATA39 S31C6 S30C6 S29C6 S28C6 S27C6 S26C6 S25C6 S24C6 613 LCDDATA40 S39C6 S38C6 S37C6 S36C6 S35C6 S34C6 S33C6 S32C6 613 LCDDATA41 — — S45C6 S44C6 S43C6 S42C6 S41C6 S40C6 613 LCDDATA42 S07C7 S06C7 S05C7 S04C7 S03C7 S02C7 S01C7 S00C7 613 LCDDATA43 S15C7 S14C7 S13C7 S12C7 S11C7 S10C7 S09C7 S08C7 613 LCDDATA44 S23C7 S22C7 S21C7 S20C7 S19C7 S18C7 S17C7 S16C7 613 LCDDATA45 S31C7 S30C7 S29C7 S28C7 S27C7 S26C7 S25C7 S24C7 613 LCDDATA46 S39C7 S38C7 S37C7 S36C7 S35C7 S34C7 S33C7 S24C7 613 LCDDATA47 — — S45C7 S44C7 S43C7 S42C7 S41C7 S40C7 613 Name Bit 7 Bit 6 LCDDATA34 S39C5 LCDDATA35 — LCDDATA36  2017-2021 Microchip Technology Inc. DS40001873E-page 619 PIC16(L)F19195/6/7 36.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, data EEPROM, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16(L)F153XX Memory Programming Specification” (DS40001838). 36.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 36.2 Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. 36.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 36-1. FIGURE 36-1: VDD ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 VPP/MCLR VSS Target PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 36-2. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 36-3 for more information. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 6.6“MCLR” for more information.  2017-2021 Microchip Technology Inc. DS40001873E-page 620 PIC16(L)F19195/6/7 FIGURE 36-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 36-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins. TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2017-2021 Microchip Technology Inc. DS40001873E-page 621 PIC16(L)F19195/6/7 37.0 INSTRUCTION SET SUMMARY 37.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any WRITE instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the working (W) register, or the originating file register, depending on the state of the destination designator ‘d’ (see Table 37-1 for more information). The literal and control category contains the most varied instruction word format. TABLE 37-1: Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 37-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine entry takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. . n FSR or INDF number. (0-1) mm Prepost increment-decrement mode selection TABLE 37-2: ABBREVIATION DESCRIPTIONS Field Description PC Program Counter TO Time-Out bit C DC Z PD  2017-2021 Microchip Technology Inc. OPCODE FIELD DESCRIPTIONS Carry bit Digit Carry bit Zero bit Power-Down bit DS40001873E-page 622 PIC16(L)F19195/6/7 37.2 General Format for Instructions TABLE 37-3: INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF f, b f, b Bit Clear f Bit Set f BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 1, 2 1, 2 BIT-ORIENTED SKIP OPERATIONS 1 (2) 1 (2) 01 01 10bb bfff ffff 11bb bfff ffff 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 000 0001 0000 1100 1010 LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 2: Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W  2017-2021 Microchip Technology Inc. kkkk kkkk kkkk 0k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z DS40001873E-page 623 PIC16(L)F19195/6/7 TABLE 37-3: PIC16(L)F19195/6/7 INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP RESET SLEEP TRIS – – – – f Clear Watchdog Timer No Operation Software device Reset Go into Standby or Idle mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 0000 0000 0000 0000 0000 0110 0000 0000 0110 0110 0100 TO, PD 0000 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] Note 1: 2: 3: 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z 2, 3 1 1 11 00 1111 0nkk kkkk Z 0000 0001 1nmm 2 2, 3 1 11 1111 1nkk kkkk 2 If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Section 37.3 “Instruction Descriptions” for detailed MOVIW and MOVWI instruction descriptions.  2017-2021 Microchip Technology Inc. DS40001873E-page 624 PIC16(L)F19195/6/7 37.3 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32  k  31 n  [ 0, 1] Operands: 0  k  255 Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f AND literal with W k FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0  k  255 Operation: Status Affected: Syntax: [ label ] ANDWF Operands: 0  f  127 d 0,1 (W) + k  (W) Operation: (W) .AND. (f)  (destination) C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0  f  127 d 0,1 Operation: (W) + (f)  (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC k f,d ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Syntax: [ label ] ASRF Operands: 0  f  127 d [0,1] f {,d} Operation: (f) dest (f)  dest, (f)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f C f {,d} Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2017-2021 Microchip Technology Inc. f,d DS40001873E-page 625 PIC16(L)F19195/6/7 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0  f  127 0b7 Operands: 0  f  127 0b7 Operands: Operation: 0  (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: 0  f  127 0b — C2TSEL 21Fh — Unimplemented 28Ch T2TMR TMR2 C1TSEL 457 — 28Dh T2PR 28Eh T2CON ON PR2 28Fh T2HLT PSYNC CKPOL CKSYNC 290h T2CLKCON — — — — CS 399 291h T2RST — — — — RSEL 402 292h T4TMR OUTPS 400 CKPS OUTPS MODE 400 401 TMR4 293h T4PR 294h T4CON ON PR4 295h T4HLT PSYNC CKPOL CKSYNC 296h T4CLKCON — — — — CS 399 297h T4RST — — — — RSEL 402 298h — Unimplemented — 299h — Unimplemented — 29Ah — Unimplemented — 29Bh — Unimplemented — 29Ch — Unimplemented — 29Dh — Unimplemented — 29Eh — Unimplemented — 29Fh — Unimplemented — CKPS MODE 401 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 637 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 30Ch CCPR1L RL 30Dh CCPR1H RH 30Eh CCP1CON CCP1EN — CCP1OUT CCP1FMT — — — — — 30Fh CCP1CAP — 311h CCPR2H RH 312h CCP2CON CCP2EN — CCP2OUT CCP2FMT — — — — — PWM3DC — — — PWM3DC1 317h — 318h PWM4DCL CCP1CTS2 CCP1CTS1 CCP1CTS0 PWM3DC0 457 CCP2MODE CCP2MODE3 454 CCP2MODE0 — CCP2CTS2 CCP2CTS1 CCP2CTS0 454 456 — — — — — 464 — — — — — 464 456 464 PWM3DC8 PWM3DC7 PWM3DC6 PWM3DC5 PWM3DC4 PWM3DC3 PWM3DC2 PWM3EN — PWM3OUT PWM3POL — — — — Unimplemented PWM4DC0 456 456 PWM3DC9 PWM4DC 454 456 PWM3DC PWM4DC1 319h CCP1MODE0 CCP2MODE1 PWM3DCH PWM3CON CCP1MODE1 CCP2CTS — 316h 454 CCP1MODE2 CCP2MODE2 CCP2CAP 315h 457 — RL Register on page 456 CCP1MODE3 CCPR2L PWM3DCL Bit 0 CCP1MODE 310h 314h Bit 1 CCP1CTS — 313h Bit 2 464 463 463 — — — — — — 464 — — — — — — 464 PWM4DCH PWM4DC 464 PWM4DC9 PWM4DC8 PWM4DC7 PWM4DC6 PWM4DC5 PWM4DC4 PWM4DC3 PWM4DC2 464 PWM4EN — PWM4OUT PWM4POL — — — — 463 31Ah PWM4CON 31Bh 31Fh — Unimplemented — 38Ch — Unimplemented — 38Dh — Unimplemented — 38Eh — Unimplemented — 38Fh — Unimplemented — 390h — Unimplemented — 391h — Unimplemented — 392h — Unimplemented — 393h — Unimplemented — 394h — Unimplemented — 395h — Unimplemented — 396h — Unimplemented — 397h — Unimplemented — 398h — Unimplemented — 399h — Unimplemented — 39Ah — Unimplemented — 39Bh — Unimplemented — 39Ch — Unimplemented — 39Dh — Unimplemented — 39Eh — Unimplemented — 39Fh — Unimplemented — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 638  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 40Ch — Unimplemented — 40Dh — Unimplemented — 40Eh — Unimplemented — 40Fh — Unimplemented — 410h — Unimplemented — 411h — Unimplemented — 412h — Unimplemented — 413h — Unimplemented — 414h — Unimplemented — 415h — Unimplemented — 416h — Unimplemented — 417h — Unimplemented — 418h — Unimplemented — 419h — Unimplemented — 41Ah — Unimplemented — 41Bh — Unimplemented — 41Ch — Unimplemented — 41Dh — Unimplemented — 41Eh — Unimplemented — 41Fh — Unimplemented — 48Ch SMT1TMRL SMT1TMR 412 48Dh SMT1TMRH SMT1TMR 412 48Eh SMT1TMRU SMT1TMR 412 48Fh SMT1CPRL CPR 413 490h SMT1CPRH CPR 413 491h SMT1CPRU CPR 413 492h SMT1CPWL CPW 414 493h SMT1CPWH CPW 414 494h SMT1CPWU CPW 414 495h SMT1PRL SMT1PR 415 496h SMT1PRH SMT1PR 415 497h SMT1PRU SMT1PR 498h SMT1CON0 EN — STP WPOL 499h SMT1CON1 SMT1GO REPEAT — — — — 415 SPOL CPOL SMT1PS MODE 406 407 49Ah SMT1STAT CPRUP CPWUP RST — 49Bh SMT1CLK — — — — 49Ch SMT1SIG — — — SSEL 411 49Dh SMT1WIN — — — WSEL 410 TS WS AS CSEL 408 409 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 639 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 49Eh — Unimplemented — 49Fh — Unimplemented — 50Ch — Unimplemented — 50Dh — Unimplemented — 50Eh — Unimplemented — 50Fh — Unimplemented — 510h — Unimplemented — 511h — Unimplemented — 512h — Unimplemented — 513h — Unimplemented — 514h — Unimplemented — 515h — Unimplemented — 516h — Unimplemented — 517h — Unimplemented — 518h — Unimplemented — 519h — Unimplemented — 51Ah — Unimplemented — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 640  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 51Bh — Unimplemented — 51Ch — Unimplemented — 51Dh — Unimplemented — 51Eh — Unimplemented — 51Fh — Unimplemented — 58Ch — Unimplemented — 58Dh — Unimplemented — 58Eh — Unimplemented — 58Fh — Unimplemented — 590h — Unimplemented — 591h — Unimplemented — 592h — Unimplemented — 593h — Unimplemented — 594h — Unimplemented — 595h — Unimplemented — 596h — Unimplemented — 597h — Unimplemented — 598h — Unimplemented — 599h — Unimplemented — 59Ah — Unimplemented — 59Bh — Unimplemented — 59Ch TMR0L TMR0L 59Dh TMR0H TMR0H 59Eh T0CON0 59Fh T0CON1 60Ch CWG1CLKCON — — — — 60Dh CWG1ISM — — — — 60Eh CWG1DBR — — T0PR T0EN — T0OUT T0CS T016BIT T0OUTPS T0ASYNC T0CKPS — — — 364 365 CS IS 488 DBR 60Fh CWG1DBF — — 610h CWG1CON0 EN LD — — — 611h CWG1CON1 — — IN — POLD 612h CWG1AS0 SHUTDOWN REN 484 DBF LSBD 484 MODE POLC LSAC 488 482 POLB POLA 483 — — 485 613h CWG1AS1 — — — AS4E AS3E AS2E AS1E AS0E 486 614h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 487 615h — Unimplemented — 616h — Unimplemented — 617h — Unimplemented — 618h — Unimplemented — 619h — Unimplemented — 61Ah — Unimplemented — 61Bh — Unimplemented — 61Ch — Unimplemented — 61Dh — Unimplemented — 61Eh — Unimplemented — 61Fh — Unimplemented — 68Ch — Unimplemented — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 641 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 68Dh — Unimplemented — 68Eh — Unimplemented — 68Fh — Unimplemented — 690h — Unimplemented — 691h — Unimplemented — 692h — Unimplemented — 693h — Unimplemented — 694h — Unimplemented — 695h — Unimplemented — 696h — Unimplemented — 697h — Unimplemented — 698h — Unimplemented — 699h — Unimplemented — 69Ah — Unimplemented — 69Bh — Unimplemented — 69Ch — Unimplemented — 69Dh — Unimplemented — 69Eh — Unimplemented — 69Fh — Unimplemented 70Ch PIR0 — — TMR0IF IOCIF — — — INTF 157 70Dh PIR1 OSFIF CSWIF — — — — ADTIF ADIF 158 70Eh PIR2 — ZCDIF — — — — C2IF C1IF 159 70Fh PIR3 RC2IF TX2IF RC1IF TX1IF — — BCL1IF SSP1IF 160 710h PIR4 — — — — TMR4IF — TMR2IF TMR1IF 161 711h PIR5 CLC4IF CLC3IF CLC2IF CLC1IF — — — TMR1GIF 162 712h PIR6 CRIF — — — — — CCP2IF CCP1IF 163 — 713h PIR7 — — NVMIF — — — — CWG1IF 164 714h PIR8 LCDIF RTCCIF — — — SMT1PWAIF SMT1PRAIF SMT1IF 165 715h — 716h PIE0 — — TMR0IE IOCIE — — — INTE 148 717h PIE1 OSFIE CSWIE — — — — ADTIE ADIE 149 718h PIE2 — ZCDIE — — — — C2IE C1IE 150 719h PIE3 RC2IE TX2IE RC1IE TX1IE — — BCL1IE SSP1IE 151 Unimplemented — 71Ah PIE4 — — — — TMR4IF — TMR2IE TMR1IE 152 71Bh PIE5 CLC4IE CLC3IE CLC2IE CLC1IE — — — TMR1GIE 153 71Ch PIE6 CRIE — — — — — CCP2IE CCP1IE 154 71Dh PIE7 — — NVMIE — — — — CWG1IE 155 71Eh PIE8 LCDIE RTCCIE — — — SMT1PWAIE SMT1PRAIE SMT1IE 156 71Fh Legend: — Unimplemented — x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. DS40001873E-page 642  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 78Ch — Unimplemented — 78Dh — Unimplemented — 78Eh — Unimplemented — 78Fh — Unimplemented — 790h — Unimplemented — 791h — Unimplemented — 792h — Unimplemented — 793h — Unimplemented — 794h — Unimplemented — 795h — Unimplemented 796h PMD0 SYSCMD FVRMD ACTMD — — — NVMMD — IOCMD 264 265 797h PMD1 — — — TMR4MD — TMR2MD TMR1MD TMR0MD 798h PMD2 RTCCMD DACMD ADCMD — — CMP2MD CMP1MD ZCDMD 266 799h PMD3 — — — — PWM4MD PWM3MD CCP2MD CCP1MD 267 79Ah PMD4 UART2MD UART1MD — MSSP1MD — — — CWG1MD 268 79Bh PMD5 — SMT1MD LCDMD CLC4MD CLC3MD CLC2MD CLC1MD — 269 79Ch — Unimplemented — 79Dh — Unimplemented — 79Eh — Unimplemented — 79Fh — Unimplemented 80Ch WDTCON0 — 80Dh WDTCON1 — 80Eh WDTPSL PSCNT 80Fh WDTPSH PSCNT 810h WDTTMR — 811h BORCON SBOREN — — — 812h VREGCON — — — — — WDTPS SWDTEN — WDTCS 179 180 WINDOW 181 181 WDTTMR STATE PSCNT17 PSCNT16 — — — BORRDY 181 115 — — — VREGPM — 172 813h PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 120 814h PCON1 — — — — — — MEMV VBATBOR 121 815h — Unimplemented — 816h — Unimplemented — 817h — Unimplemented — 818h — Unimplemented — 819h — Unimplemented 81Ah NVMADRL 81Bh 81Ch — NVMADR7 NVMADR6 NVMADR5 NVMADR4 NVMADR3 NVMADR2 NVMADR1 NVMADR0 199 NVMADRH — NVMADR14 NVMADR13 NVMADR12 NVMADR11 NVMADR10 NVMADR9 NVMADR8 199 NVMDATL NVMDAT7 NVMDAT6 NVMDAT5 NVMDAT4 NVMDAT3 NVMDAT2 NVMDAT1 NVMDAT0 199 81Dh NVMDATH — — NVMDAT13 NVMDAT12 NVMDAT11 NVMDAT10 NVMDAT9 NVMDAT8 199 81Eh NVMCON1 — NVMREGS LWLO FREE WRERR WREN WR RD 200 81Fh NVMCON2 88Ch CPUDOZE IDLEN DOZE2 DOZE1 DOZE0 173 88Dh OSCCON1 — NOSC NDIV 88Eh OSCCON2 — COSC CDIV 88Fh OSCCON3 CSWHOLD SOSCPWR — ORDY NOSCR — — — 137 890h OSCSTAT EXTOR HFOR MFOR LFOR SOR ADOR — PLLR 138 NVMCON2 DOZEN ROI DOE — 201 135 135 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 643 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Register on page Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 891h OSCEN EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN — — 892h OSCTUNE — — 893h OSCFRQ — — — — — 894h ACTCON ACTEN ACTUD — — ACTLOCK 895h — Unimplemented — 896h — Unimplemented — 897h — Unimplemented — 898h — Unimplemented — 899h — Unimplemented — 89Ah — Unimplemented — 89Bh — Unimplemented — 89Ch — Unimplemented — 89Dh — Unimplemented — 89Eh — Unimplemented — 89Fh — Unimplemented 90Ch FVRCON HFTUN FVREN FVRRDY TSEN TSRNG OE2 90Dh — 90Eh DAC1CON0 EN — OE1 90Fh DAC1CON1 — — — — — — 90Fh HFFRQ — 140 ACTORS — ADFVR 280 — DAC1PSS — — DAC1R1 DAC1R0 DAC1R DAC1R3 141 — CDAFVR Unimplemented DAC1R4 139 140 DAC1R2 328 328 328 910h — Unimplemented — 911h — Unimplemented — 912h — Unimplemented — 913h — Unimplemented — 914h — Unimplemented — 915h — Unimplemented — 916h — Unimplemented — 917h — Unimplemented — 918h — Unimplemented — 919h — Unimplemented — 91Ah — Unimplemented — 91Bh — Unimplemented — 91Ch — Unimplemented — 91Dh — Unimplemented — 91Eh — Unimplemented 91Fh ZCDCON 98Ch — Unimplemented — 98Dh — Unimplemented — 98Eh — Unimplemented 98Fh CMOUT — — — — — — 990h CM1CON0 ON OUT — POL — 991h CM1CON1 — — — — — 992h CM1NSEL — — — — — — — — — — — — — — — — — — 992h 993h CM1PSEL 993h ZCDSEN — ZCDOUT ZCDPOL — — — ZCDINTP ZCDINTN — MC2OUT MC1OUT 339 — HYS SYNC 336 — INTP INTN 337 NCH NCH2 NCH1 338 NCH0 PCH — 345 PCH2 PCH1 338 338 PCH0 338 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 644  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Bit 1 Bit 0 Register on page — HYS SYNC 336 — INTP INTN 337 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 994h CM2CON0 ON OUT — POL — 995h CM2CON1 — — — — — 996h CM2NSEL — — — — — — — — — — — — — — — — — — — — 996h 997h CM2PSEL 997h NCH NCH2 NCH1 338 NCH0 PCH PCH2 PCH1 338 338 PCH0 338 998h — Unimplemented — 999h — Unimplemented — 99Ah — Unimplemented — 99Bh — Unimplemented — 99Ch — Unimplemented — 99Dh — Unimplemented — 99Eh — Unimplemented — 99Fh — Unimplemented — A0Ch — Unimplemented — A0Dh — Unimplemented — A0Eh — Unimplemented — A0Fh — Unimplemented — A10h — Unimplemented — A11h — Unimplemented — A12h — Unimplemented — A13h — Unimplemented — A14h — Unimplemented — A15h — Unimplemented — A16h — Unimplemented — A17h — Unimplemented — A18h — Unimplemented — A19h RC2REG RC2REG A1Ah TX2REG TX2REG A1Bh SP2BRGL SP2BRGL A1Ch SP2BRGH A1Dh RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR A1Eh TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D A1Fh BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN A8Ch — A9Fh — Unimplemented B0Ch — B1Fh — Unimplemented B8Ch — B9Fh — Unimplemented SP2BRGH RX9D — — — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 645 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 C0Ch RTCCON RTCEN — RTCWREN RTCSYNC C0Dh RTCCAL C0Eh ALRMCON C0Fh ALRMRPT Bit 3 Bit 2 HALFSEC — Bit 1 Bit 0 RTCCLKSEL CAL ALRMEN CHIME — — ARPT YEAR C11h MONTH — — — — 357 357 YEARH MONTHH — 353 354 AMASK C10h Register on page YEARL 354 MONTHL 354 C12h WEEKDAY — — C13h DAY — — DAYH — DAYL WDAY 355 C14h HOURS — — HRH HRL 355 C15h MINUTES — MINH MINL 356 C16h SECONDS — SECH SECL 356 C17h ALRMMTH — — — ALRMHMONTH ALRMLMONTH 358 — — 355 C18h ALRMWD — — — C19h ALRMDAY — — ALRMHDAY C1Ah ALRMHR — — C1Bh ALRMMIN — ALRMHMIN C1Ch ALRMSEC — ALRMHSEC ALRMLSEC 359 C1Dh — Unimplemented — C1Eh — Unimplemented — C1Fh — Unimplemented — C8Ch PORTG RG7 RG6 RG5 RG4 RG3 RG2 RG1 RG0 243 C8Dh PORTH — — — — RH3 RH2 RH1 RH0 250 C8Eh TRISG TRISG7 TRISG6 — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 243 C8Fh TRISH — — — — TRISH3 TRISH2 TRISH1 TRISH0 250 C90h LATG LATG7 LATG6 — LATG4 LATG3 LATG2 LATG1 LATG0 244 — — — — LATH3 LATH2 LATH1 LATH0 250 ALRMHHR ALRMLWDAY 358 ALRMLDAY 358 ALRMLHR 359 ALRMLMIN 359 C91h LATH C92h — Unimplemented — C93h — Unimplemented — C94h — Unimplemented — C95h — Unimplemented — C96h — Unimplemented — C97h — Unimplemented — C98h — Unimplemented — C99h — Unimplemented — C9Ah — Unimplemented — C9Bh — Unimplemented — C9Ch — Unimplemented — C9Dh — Unimplemented — C9Eh — Unimplemented — C9Fh — Unimplemented — D0Ch — D1Fh — Unimplemented D8Ch — D9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 646  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page E0Ch — E1Fh — Unimplemented E8Ch VB0GPR VB0GPR E8Dh VB1GPR VB1GPR E8Eh VB2GPR VB2GPR E8Fh VB3GPR VB3GPR E90h — Unimplemented — E91h — Unimplemented — E92h — Unimplemented — E93h — Unimplemented — E94h — Unimplemented — E95h — Unimplemented — E96h — Unimplemented — E97h — Unimplemented — E98h — Unimplemented — E99h — Unimplemented — E9Ah — Unimplemented — E9Bh — Unimplemented — E9Ch — Unimplemented — E9Dh — Unimplemented — E9Eh — Unimplemented — E9Fh — Unimplemented — F0Ch — 1C9Fh — Unimplemented 1D0Ch LCDCON LCDEN SLPEN WERR CS LMUX 611 1D0Dh LCDPS WFT — LCDA WA LP 612 1D0Eh LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 613 1D0Fh LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 613 1D10h LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 613 1D11h LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 613 1D12h LCDSE4 SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 613 1D13h LCDSE5 SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 613 1D14h LCDVCON1 LPEN EN5V — — — BIAS 614 LCDVSRC1 LCDVSRC0 615 — — 1D15h LCDVCON2 CPWDT — — — LCDVSRC3 1D16h LCDREF — — — — — LCDCST 1D17h LCDRL LCDIRI LRLAT 1D18h LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 613 1D19h LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 613 1D1Ah LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 613 1D1Bh LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 613 1D1Ch LCDDATA4 S39C0 S38C0 S37C0 S36C0 S35C0 S34C0 S33C0 S32C0 613 1D1Dh LCDDATA5 — — S45C0 S44C0 S43C0 S42C0 S41C0 S40C0 613 1D1Eh LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 613 1D1Fh LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 613 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: LRLAP  2017-2021 Microchip Technology Inc. LRLBP LCDVSRC2 617 616 DS40001873E-page 647 PIC16(L)F19195/6/7 TABLE 38-1: REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 613 1D21h LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 613 1D22h LCDDATA10 S39C1 S38C1 S37C1 S36C1 S35C1 S34C1 S33C1 S32C1 613 1D23h LCDDATA11 — — S45C1 S44C1 S43C1 S42C1 S41C1 S40C1 613 1D24h LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 613 1D25h LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 613 1D26h LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 613 1D27h LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 613 1D28h LCDDATA16 S39C2 S38C2 S37C2 S36C2 S35C2 S34C2 S33C2 S32C2 613 1D29h LCDDATA17 — — S45C2 S44C2 S43C2 S42C2 S41C2 S40C2 613 1D2Ah LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 613 1D2Bh LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 613 1D2Ch LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 613 1D2Dh LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 613 1D2Eh LCDDATA22 S39C3 S38C3 S37C3 S36C3 S35C3 S34C3 S33C3 S32C3 613 1D2Fh LCDDATA23 — — S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 613 1D30h LCDDATA24 S07C4 S06C4 S05C4 S04C4 S03C4 S02C4 S01C4 S00C4 613 1D31h LCDDATA25 S15C4 S14C4 S13C4 S12C4 S11C4 S10C4 S09C4 S08C4 613 1D32h LCDDATA26 S23C4 S22C4 S21C4 S20C4 S19C4 S18C4 S17C4 S16C4 613 1D33h LCDDATA27 S31C4 S30C4 S29C4 S28C4 S27C4 S26C4 S25C4 S24C4 613 1D34h LCDDATA28 S39C4 S38C4 S37C4 S36C4 S35C4 S34C4 S33C4 S32C4 613 1D35h LCDDATA29 — — S45C4 S44C4 S43C4 S42C4 S41C4 S40C4 613 1D36h LCDDATA30 S07C5 S06C5 S05C5 S04C5 S03C5 S02C5 S01C5 S00C5 613 1D37h LCDDATA31 S15C5 S14C5 S13C5 S12C5 S11C5 S10C5 S09C5 S08C5 613 1D38h LCDDATA32 S23C5 S22C5 S21C5 S20C5 S19C5 S18C5 S17C5 S16C5 613 1D39h LCDDATA33 S31C5 S30C5 S29C5 S28C5 S27C5 S26C5 S25C5 S24C5 613 1D3Ah LCDDATA34 S39C5 S38C5 S37C5 S36C5 S35C5 S34C5 S33C5 S32C5 613 1D3Bh LCDDATA35 — — S45C5 S44C5 S43C5 S42C5 S41C5 S40C5 613 1D3Ch LCDDATA36 S07C6 S06C6 S05C6 S04C6 S03C6 S02C6 S01C6 S00C6 613 1D3Dh LCDDATA37 S15C6 S14C6 S13C6 S12C6 S11C6 S10C6 S09C6 S08C6 613 1D3Eh LCDDATA38 S23C6 S22C6 S21C6 S20C6 S19C6 S18C6 S17C6 S16C6 613 1D3Fh LCDDATA39 S31C6 S30C6 S29C6 S28C6 S27C6 S26C6 S25C6 S24C6 613 1D40h LCDDATA40 S39C6 S38C6 S37C6 S36C6 S35C6 S34C6 S33C6 S32C6 613 1D41h LCDDATA41 — — S45C6 S44C6 S43C6 S42C6 S41C6 S40C6 613 1D42h LCDDATA42 S07C7 S06C7 S05C7 S04C7 S03C7 S02C7 S01C7 S00C7 613 1D43h LCDDATA43 S15C7 S14C7 S13C7 S12C7 S11C7 S10C7 S09C7 S08C7 613 1D44h LCDDATA44 S23C7 S22C7 S21C7 S20C7 S19C7 S18C7 S17C7 S16C7 613 1D45h LCDDATA45 S31C7 S30C7 S29C7 S28C7 S27C7 S26C7 S25C7 S24C7 613 1D46h LCDDATA46 S39C7 S38C7 S37C7 S36C7 S35C7 S34C7 S33C7 S32C7 613 1D47h LCDDATA47 — — S45C7 S44C7 S43C7 S42C7 S41C7 S40C7 613 1D48h — 1D6Fh — Address 1D20h — Unimplemented Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 648  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1D8Ch — 1D9Fh — Unimplemented — 1E0Ch — Unimplemented — 1E0Dh — Unimplemented — 1E0Eh — Unimplemented 1E0Fh CLCDATA — — — — — MLC4OUT MLC3OUT MLC2OUT MLC1OUT 504 LC1G1POL 498 1E10h CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN 1E11h CLC1POL LC1POL — — — LC1G4POL 1E12h CLC1SEL0 — — LC1D1S 499 1E13h CLC1SEL1 — — LC1D2S 499 1E14h CLC1SEL2 — — LC1D3S 499 1E15h CLC1SEL3 — — LC1D4S 1E16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 500 1E17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 501 1E18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 502 1E19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 1E1Ah CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN 1E1Bh CLC2POL LC2POL — — — LC2G4POL — LC1MODE LC1G3POL LC1G2POL 497 499 LC2MODE LC2G3POL LC2G2POL 503 497 LC2G1POL 498 1E1Ch CLC2SEL0 — LC2D1S 499 1E1Dh CLC2SEL1 — — LC2D2S 499 1E1Eh CLC2SEL2 — — LC2D3S 499 1E1Fh CLC2SEL3 — — LC2D4S 1E20h CLC2GLS0 LC2G1D4T LC1G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 500 1E21h CLC2GLS1 LC2G2D4T LC1G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 501 1E22h CLC2GLS2 LC2G3D4T LC1G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 502 1E23h CLC2GLS3 LC2G4D4T LC1G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 1E24h CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN 1E25h CLC3POL LC3POL — — — LC3G4POL 499 LC3MODE LC3G3POL LC3G2POL 503 497 LC3G1POL 498 1E26h CLC3SEL0 — — LC3D1S 499 1E27h CLC3SEL1 — — LC3D2S 499 1E28h CLC3SEL2 — — LC3D3S 499 1E29h CLC3SEL3 — — LC3D4S 1E2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 500 1E2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 501 1E2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 502 1E2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 503 1E2Eh CLC4CON LC4EN — LC4OUT LC4INTP LC4INTN 1E2Fh CLC4POL LC4POL — — — LC4G4POL 499 LC4MODE LC4G3POL LC4G2POL 497 LC4G1POL 498 1E30h CLC4SEL0 — — LC4D1S 499 1E31h CLC4SEL1 — — LC4D2S 499 1E32h CLC4SEL2 — — LC4D3S 499 1E33h CLC4SEL3 — — LC4D4S 1E34h CLC4GLS0 LC4G1D4T LC4G1D4N LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N LC4G1D1T LC4G1D1N 500 1E35h CLC4GLS1 LC4G2D4T LC4G2D4N LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N LC4G2D1T LC4G2D1N 501 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. 499 DS40001873E-page 649 PIC16(L)F19195/6/7 TABLE 38-1: REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1E36h CLC4GLS2 LC4G3D4T LC4G3D4N LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N LC4G3D1T LC4G3D1N 502 1E37h CLC4GLS3 LC4G4D4T LC4G4D4N LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N LC4G4D1T LC4G4D1N 503 1E38h RF0PPS — — — RF0PPS4 RF0PPS3 RF0PPS2 RF0PPS1 RF0PPS0 260 1E39h RF1PPS — — — RF1PPS4 RF1PPS3 RF1PPS2 RF1PPS1 RF1PPS0 260 1E3Ah RF2PPS — — — RF2PPS4 RF2PPS3 RF2PPS2 RF2PPS1 RF2PPS0 260 1E3Bh RF3PPS — — — RF3PPS4 RF3PPS3 RF3PPS2 RF3PPS1 RF3PPS0 260 1E3Ch RF4PPS — — — RF4PPS4 RF4PPS3 RF4PPS2 RF4PPS1 RF4PPS0 260 1E3Dh RF5PPS — — — RF5PPS4 RF5PPS3 RF5PPS2 RF5PPS1 RF5PPS0 260 1E3Eh RF6PPS — — — RF6PPS4 RF6PPS3 RF6PPS2 RF6PPS1 RF6PPS0 260 1E3Fh RF7PPS — — — RF7PPS4 RF7PPS3 RF7PPS2 RF7PPS1 RF7PPS0 260 1E40h RG0PPS — — — RG0PPS4 RG0PPS3 RG0PPS2 RG0PPS1 RG0PPS0 260 1E41h RG1PPS — — — RG1PPS4 RG1PPS3 RG1PPS2 RG1PPS1 RG1PPS0 260 1E42h RG2PPS — — — RG2PPS4 RG2PPS3 RG2PPS2 RG2PPS1 RG2PPS0 260 1E43h RG3PPS — — — RG3PPS4 RG3PPS3 RG3PPS2 RG3PPS1 RG3PPS0 260 1E44h RG4PPS — — — RG4PPS4 RG4PPS3 RG4PPS2 RG4PPS1 RG4PPS0 260 1E45h — 1E46h RG6PPS — — — RG6PPS4 RG6PPS3 RG6PPS2 RG6PPS1 RG6PPS0 260 1E47h RG7PPS — — — RG7PPS4 RG7PPS3 RG7PPS2 RG7PPS1 RG7PPS0 260 1E48h RH0PPS — — — RH0PPS4 RH0PPS3 RH0PPS2 RH0PPS1 RH0PPS0 260 1E49h RH1PPS — — — RH1PPS4 RH1PPS3 RH1PPS2 RH1PPS1 RH1PPS0 260 1E4Ah RH2PPS — — — RH2PPS4 RH2PPS3 RH2PPS2 RH2PPS1 RH2PPS0 260 1E4Bh RH3PPS — — — RH3PPS4 RH3PPS3 RH3PPS2 RH3PPS1 RH3PPS0 260 1E4Ch — Unimplemented — 1E4Dh — Unimplemented — 1E4Eh — Unimplemented — 1E4Fh — Unimplemented 1E50h ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 238 1E51h WPUF WPUF7 WPUF6 WPUF5 WPUF4 WPUF3 WPUF2 WPUF1 WPUF0 238 1E52h ODCONF ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 239 1E53h SLRCONF SLRF7 SLRF6 SLRF5 SLRF4 SLRF3 SLRF2 SLRF1 SLRF0 239 1E54h INLVLF INLVLF7 INLVLF6 INLVLF5 INLVLF4 INLVLF3 INLVLF2 INLVLF1 INLVLF0 239 1E55h HIDRVF HIDF7 — — — — — — — 240 Address Unimplemented — — 1E56h — Unimplemented — 1E57h — Unimplemented — 1E58h — Unimplemented — 1E59h — Unimplemented — 1E5Ah — Unimplemented — 1E5Bh ANSELG ANSG7 ANSG6 — ANSG4 ANSG3 ANSG2 ANSG1 ANSG0 244 1E5Ch WPUG WPUG7 WPUG6 WPUG5 WPUG4 WPUG3 WPUG2 WPUG1 WPUG0 245 1E5Dh ODCONG ODCG7 ODCG6 — ODCG4 ODCG3 ODCG2 ODCG1 ODCG0 245 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 650  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1E5Eh SLRCONG SLRG7 SLRG6 — SLRG4 SLRG3 SLRG2 SLRG1 SLRG0 246 1E5Fh INLVLG INLVLG7 INLVLG6 INLVLG5 INLVLG4 INLVLG3 INLVLG2 INLVLG1 INLVLG0 246 1E60h IOCGP — — IOCGP5 — — — — — 275 1E61h IOCGN — — IOCGN5 — — — — — 275 1E62h IOCGF — — IOCGF5 — — — — — 276 1E63h — Unimplemented — 1E64h — Unimplemented — 1E65h — Unimplemented — 1E66h — 1E67h WPUH — — — — WPUH3 WPUH2 WPUH1 WPUH0 251 1E68h ODCONH — — — — ODCH3 ODCH2 ODCH1 ODCH0 252 1E69h SLRCONH — — — — SLRH3 SLRH2 SLRH1 SLRH0 252 1E6Ah INLVLH — — — — INLVLH3 INLVLH2 INLVLH1 INLVLH0 252 Unimplemented — 1E6Bh — Unimplemented — 1E6Ch — Unimplemented — 1E6Dh — Unimplemented — 1E6Eh — Unimplemented — 1E6Fh — Unimplemented — 1E8Ch — Unimplemented — 1E8Dh — Unimplemented — 1E8Eh — Unimplemented — 1E8Fh PPSLOCK — — — 1E90h INTPPS — — — INTPPS 259 1E91h T0CKIPPS — — — T0CKIPPS 259 1E92h T1CKIPPS — — — T1CKIPPS 259 1E93h T1GPPS — — — T1GPPS 259 1E94h — — — — — PPSLOCKED Unimplemented 260 — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 651 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1E95h — Unimplemented — 1E96h — Unimplemented — 1E97h — Unimplemented — 1E98h — Unimplemented — 1E99h — Unimplemented — 1E9Ah — Unimplemented — 1E9Bh — Unimplemented 1E9Ch T2AINPPS — — — T2INPPS 259 1E9Dh T4AINPPS — — — T4INPPS 259 — 1E9Eh — Unimplemented — 1E9Fh — Unimplemented — 1EA0h — Unimplemented 1EA1h CCP1PPS — — — CCP1PPS 259 1EA2h CCP2PPS — — — CCP2PPS 259 — 1EA3h — Unimplemented — 1EA4h — Unimplemented — 1EA5h — Unimplemented — 1EA6h — Unimplemented — 1EA7h — Unimplemented — 1EA8h — 1EA9h SMT1WINPPS — — — 1EAAh SMT1SIGPPS — — — 1EABh — Unimplemented — 1EACh — Unimplemented — 1EADh — Unimplemented — 1EAEh — Unimplemented — 1EAFh — Unimplemented — 1EB0h — Unimplemented 1EB1h CWG1PPS Unimplemented — — — — SMT1WINPPS 259 SMT1SIGPPS 259 — CWG1PPS 259 1EB2h — Unimplemented — 1EB3h — Unimplemented — 1EB4h — Unimplemented — 1EB5h — Unimplemented — 1EB6h — Unimplemented — 1EB7h — Unimplemented — 1EB8h — Unimplemented — 1EB9h — Unimplemented — 1EBAh — Unimplemented 1EBBh CLCIN0PPS — — — CLCIN0PPS 259 1EBCh CLCIN1PPS — — — CLCIN1PPS 259 1EBDh CLCIN2PPS — — — CLCIN2PPS 259 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 652 —  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Bit 7 Bit 6 Bit 5 1EBEh CLCIN3PPS — — — 1EBFh — Unimplemented — 1EC0h — Unimplemented — 1EC1h — Unimplemented — 1EC2h — 1EC3h ADCACTPPS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page Name CLCIN3PPS Unimplemented — — 259 — ADCACTPPS 259 1EC4h — 1EC5h SSP1CLKPPS — — — SSP1CLKPPS 259 1EC6h SSP1DATPPS — — — SSP1DATPPS 259 1EC7h SSP1SSPPS — — — SSP1SSPPS 259 1EC8h — Unimplemented — 1EC9h — Unimplemented — 1ECAh — Unimplemented 1ECBh RX1PPS — — — 1ECCh TX1PPS — — 1ECDh RX2PPS — — 1ECEh TX2PPS — — 1ECFh — Unimplemented — 1ED0h — Unimplemented — 1ED1h — Unimplemented — 1ED2h — Unimplemented — 1ED3h — Unimplemented — 1ED4h — Unimplemented — 1ED5h — Unimplemented — 1ED6h — Unimplemented — 1ED7h — Unimplemented — 1ED8h — Unimplemented — 1ED9h — Unimplemented — 1EDAh — Unimplemented — 1EDBh — Unimplemented — 1EDCh — Unimplemented — 1EDDh — Unimplemented — 1EDEh — Unimplemented — 1EDFh — Unimplemented — 1EE0h — Unimplemented — 1EE1h — Unimplemented — 1EE2h — Unimplemented — 1EE3h — Unimplemented — 1EE4h — Unimplemented — 1EE5h — Unimplemented — 1EE6h — Unimplemented — 1EE7h — Unimplemented — 1EE8h — Unimplemented — 1EE9h — Unimplemented — 1EEAh — Unimplemented — Unimplemented — — RX1PPS 259 — TX1PPS 259 — RX2PPS 259 — TX2PPS 259 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 653 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1EEBh — Unimplemented — 1EECh — Unimplemented — 1EEDh — Unimplemented — 1EEEh — Unimplemented — 1EEFh — Unimplemented — 1F0Ch — Unimplemented — 1F0Dh — Unimplemented — 1F0Eh — Unimplemented — 1F0Fh — Unimplemented 1F10h RA0PPS — — — RA0PPS4 RA0PPS3 RA0PPS2 RA0PPS1 RA0PPS0 260 1F11h RA1PPS — — — RA1PPS4 RA1PPS3 RA1PPS2 RA1PPS1 RA1PPS0 260 1F12h RA2PPS — — — RA2PPS4 RA2PPS3 RA2PPS2 RA2PPS1 RA2PPS0 260 1F13h RA3PPS — — — RA3PPS4 RA3PPS3 RA3PPS2 RA3PPS1 RA3PPS0 260 1F14h RA4PPS — — — RA4PPS4 RA4PPS3 RA4PPS2 RA4PPS1 RA4PPS0 260 1F15h RA5PPS — — — RA5PPS4 RA5PPS3 RA5PPS2 RA5PPS1 RA5PPS0 260 1F16h RA6PPS — — — RA6PPS4 RA6PPS3 RA6PPS2 RA6PPS1 RA6PPS0 260 1F17h RA7PPS — — — RA7PPS4 RA7PPS3 RA7PPS2 RA7PPS1 RA7PPS0 260 1F18h RB0PPS — — — RB0PPS4 RB0PPS3 RB0PPS2 RB0PPS1 RB0PPS0 260 1F19h RB1PPS — — — RB1PPS4 RB1PPS3 RB1PPS2 RB1PPS1 RB1PPS0 260 1F1Ah RB2PPS — — — RB2PPS4 RB2PPS3 RB2PPS2 RB2PPS1 RB2PPS0 260 1F1Bh RB3PPS — — — RB3PPS4 RB3PPS3 RB3PPS2 RB3PPS1 RB3PPS0 260 1F1Ch RB4PPS — — — RB4PPS4 RB4PPS3 RB4PPS2 RB4PPS1 RB4PPS0 260 1F1Dh RB5PPS — — — RB5PPS4 RB5PPS3 RB5PPS2 RB5PPS1 RB5PPS0 260 1F1Eh RB6PPS — — — RB6PPS4 RB6PPS3 RB6PPS2 RB6PPS1 RB6PPS0 260 1F1Fh RB7PPS — — — RB7PPS4 RB7PPS3 RB7PPS2 RB7PPS1 RB7PPS0 260 1F20h RC0PPS — — — RC0PPS4 RC0PPS3 RC0PPS2 RC0PPS1 RC0PPS0 260 1F21h RC1PPS — — — RC1PPS4 RC1PPS3 RC1PPS2 RC1PPS1 RC1PPS0 260 1F22h RC2PPS — — — RC2PPS4 RC2PPS3 RC2PPS2 RC2PPS1 RC2PPS0 260 1F23h RC3PPS — — — RC3PPS4 RC3PPS3 RC3PPS2 RC3PPS1 RC3PPS0 260 1F24h RC4PPS — — — RC4PPS4 RC4PPS3 RC4PPS2 RC4PPS1 RC4PPS0 260 1F25h RC5PPS — — — RC5PPS4 RC5PPS3 RC5PPS2 RC5PPS1 RC5PPS0 260 1F26h RC6PPS — — — RC6PPS4 RC6PPS3 RC6PPS2 RC6PPS1 RC6PPS0 260 1F27h RC7PPS — — — RC7PPS4 RC7PPS3 RC7PPS2 RC7PPS1 RC7PPS0 260 1F28h RD0PPS — — — RD0PPS4 RD0PPS3 RD0PPS2 RD0PPS1 RD0PPS0 260 1F29h RD1PPS — — — RD1PPS4 RD1PPS3 RD1PPS2 RD1PPS1 RD1PPS0 260 1F2Ah RD2PPS — — — RD2PPS4 RD2PPS3 RD2PPS2 RD2PPS1 RD2PPS0 260 1F2Bh RD3PPS — — — RD3PPS4 RD3PPS3 RD3PPS2 RD3PPS1 RD3PPS0 260 1F2Ch RD4PPS — — — RD4PPS4 RD4PPS3 RD4PPS2 RD4PPS1 RD4PPS0 260 1F2Dh RD5PPS — — — RD5PPS4 RD5PPS3 RD5PPS2 RD5PPS1 RD5PPS0 260 1F2Eh RD6PPS — — — RD6PPS4 RD6PPS3 RD6PPS2 RD6PPS1 RD6PPS0 260 1F2Fh RD7PPS — — — RD7PPS4 RD7PPS3 RD7PPS2 RD7PPS1 RD7PPS0 260 1F30h RE0PPS — — — RE0PPS4 RE0PPS3 RE0PPS2 RE0PPS1 RE0PPS0 260 1F31h RE1PPS — — — RE1PPS4 RE1PPS3 RE1PPS2 RE1PPS1 RE1PPS0 260 1F32h — — — — — — — — — — — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 654  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1F33h RE3PPS — — — RE3PPS4 RE3PPS3 RE3PPS2 RE3PPS1 RE3PPS0 260 1F34h RE4PPS — — — RE4PPS4 RE4PPS3 RE4PPS2 RE4PPS1 RE4PPS0 260 1F35h RE5PPS — — — RE5PPS4 RE5PPS3 RE5PPS2 RE5PPS1 RE5PPS0 260 1F36h RE6PPS — — — RE6PPS4 RE6PPS3 RE6PPS2 RE6PPS1 RE6PPS0 260 1F37h RE7PPS — — — RE7PPS4 RE7PPS3 RE7PPS2 RE7PPS1 RE7PPS0 260 1F38h ANSELA ANSA7 ANSA6 — ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 206 1F39h WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 207 1F3Ah ODCONA ODCA7 ODCA6 — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 207 1F3Bh SLRCONA SLRA7 SLRA6 — SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 208 1F3Ch INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 208 1F3Dh IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 1F3Eh IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 1F3Fh IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 1F40h — Unimplemented — 1F41h — Unimplemented — 1F42h — Unimplemented — 1F43h ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 213 1F44h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 214 1F45h ODCONB ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 214 1F46h SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 215 1F47h INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 215 1F48h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 272 1F49h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 272 1F4Ah IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 272 1F4Bh — Unimplemented — 1F4Ch — Unimplemented — 1F4Dh — Unimplemented — 1F4Eh — Unimplemented — Address 1F4Fh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 220 1F50h ODCONC ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 220 1F51h SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 220 1F52h INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 221 1F53h IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 273 1F54h IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 273 1F55h IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 273 1F56h — Unimplemented — 1F57h — Unimplemented — 1F58h — 1F59h ANSELD ANSD7 ANSD6 ANSD5 ANSD4 Unimplemented ANSD3 ANSD2 ANSD1 ANSD0 225 — 1F5Ah WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 226 1F5Bh ODCOND ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 226 1F5Ch SLRCOND SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 226 1F5Dh INLVLD INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 226 Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 655 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1F5Eh — Unimplemented — 1F5Fh — Unimplemented — 1F60h — Unimplemented — 1F61h — Unimplemented — 1F62h — Unimplemented — 1F63h — Unimplemented — 1F64h ANSELE ANSE7 ANSE6 ANSE5 ANSE4 ANSE3 — ANSE1 ANSE0 231 1F65h WPUE WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 — WPUE1 WPUE0 232 ODCE3 — ODCE1 ODCE0 232 1F66h ODCONE ODCE7 ODCE6 ODCE5 ODCE4 1F67h SLRCONE SLRE7 SLRE6 SLRE5 SLRE4 SLRE3 — SLRE1 SLRE0 233 1F68h INLVLE INLVLE7 INLVLE6 INLVLE5 INLVLE4 INLVLE3 — INLVLE1 INLVLE0 233 1F69h IOCEP IOCEP7 IOCEP6 IOCEP5 IOCEP4 IOCEP3 IOCEP2 IOCEP1 IOCEP0 274 1F6Ah IOCEN IOCEN7 IOCEN6 IOCEN5 IOCEN4 IOCEN3 IOCEN2 IOCEN1 IOCEN0 274 1F6Bh IOCEF IOCEF7 IOCEF6 IOCEF5 IOCEF4 IOCEF3 IOCEF2 IOCEF1 IOCEF0 274 1F6Ch — Unimplemented — 1F6Dh — Unimplemented — 1F6Fh — Unimplemented — 1F8Ch — Unimplemented — 1F8Dh — Unimplemented — 1F8Eh — Unimplemented — 1F8Fh — Unimplemented — 1F90h — Unimplemented — 1F91h — Unimplemented — 1F92h — Unimplemented — 1F93h — Unimplemented — 1F94h — Unimplemented — 1F95h — Unimplemented — 1F96h — Unimplemented — 1F97h — Unimplemented — 1F98h — Unimplemented — 1F99h — Unimplemented — 1F9Ah — Unimplemented — 1F9Bh — Unimplemented — 1F9Ch — Unimplemented — 1F9Dh — Unimplemented — 1F9Eh — Unimplemented — 1F9Fh — Unimplemented — 1FA0h — Unimplemented — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 656  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1FA1h — Unimplemented — 1FA2h — Unimplemented — 1FA3h — Unimplemented — 1FA4h — Unimplemented — 1FA5h — Unimplemented — 1FA6h — Unimplemented — 1FA7h — Unimplemented — 1FA8h — Unimplemented — 1FA9h — Unimplemented — 1FAAh — Unimplemented — 1FABh — Unimplemented — 1FACh — Unimplemented — 1FADh — Unimplemented — 1FAEh — Unimplemented — 1FAFh — Unimplemented — 1FB0h — Unimplemented — 1FB1h — Unimplemented — 1FB2h — Unimplemented — 1FB3h — Unimplemented — 1FB4h — Unimplemented — 1FB5h — Unimplemented — 1FB6h — Unimplemented — 1FB7h — Unimplemented — 1FB8h — Unimplemented — 1FB9h — Unimplemented — 1FBAh — Unimplemented — 1FBBh — Unimplemented — 1FBCh — Unimplemented — 1FBDh — Unimplemented — 1FBEh — Unimplemented — 1FBFh — Unimplemented — 1FC0h — Unimplemented — 1FC1h — Unimplemented — 1FC2h — Unimplemented — 1FC3h — Unimplemented — 1FC4h — Unimplemented — 1FC5h — Unimplemented — 1FC6h — Unimplemented — 1FC7h — Unimplemented — 1FC8h — Unimplemented — 1FC9h — Unimplemented — 1FCAh — Unimplemented — 1FCBh — Unimplemented — 1FCCh — Unimplemented — 1FCDh — Unimplemented — 1FCEh — Unimplemented — 1FCFh — Unimplemented — Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1:  2017-2021 Microchip Technology Inc. DS40001873E-page 657 PIC16(L)F19195/6/7 TABLE 38-1: Address REGISTER FILE SUMMARY FOR PIC16(L)F19195/6/7 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 1FD0h — Unimplemented — 1FD1h — Unimplemented — 1FD2h — Unimplemented — 1FD3h — Unimplemented — 1FD4h — Unimplemented — 1FD5h — Unimplemented — 1FD6h — Unimplemented — 1FD7h — Unimplemented — 1FD8h — Unimplemented — 1FD9h — Unimplemented — 1FDAh — Unimplemented — 1FDBh — Unimplemented — 1FDCh — Unimplemented — 1FDDh — Unimplemented — 1FDEh — Unimplemented — 1FDFh — Unimplemented — 1FE0h — Unimplemented — 1FE1h — Unimplemented — 1FE2h — Unimplemented — 1FE3h — Unimplemented — 1FE4h STATUS_SHAD 1FE5h WREG_SHAD — — — — — 1FE6h BSR_SHAD — 1FE7h PCLATH_SHAD — — — FSR0L_SHAD FSR0L_SHAD FSR0H_SHAD FSR0H_SHAD 1FEAh FSR1L_SHAD FSR1L_SHAD 1FEBh FSR1H_SHAD FSR1H_SHAD 1FECh — STKPTR TOSL 1FEFh TOSH C_SHAD BSR_SHAD 1FE9h 1FEEh DC_SHAD PCLATH_SHAD 1FE8h 1FEDh Z_SHAD WREG_SHAD Unimplemented — — — — STKPTR TOSL — TOSH Legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’. Note Unimplemented data memory locations, read as ‘0’. 1: DS40001873E-page 658  2017-2021 Microchip Technology Inc. PIC16(L)F19195/6/7 39.0 ELECTRICAL SPECIFICATIONS 39.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC16F19195/6/7 ...................................................................................................... -0.3V to +6.5V PIC16(L)F19195/6/7 ................................................................................................. -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40°C  TA  +85°C .............................................................................................................. 350 mA 85°C  TA  +125°C ............................................................................................................. 120 mA on VDD pin for 28-Pin devices(1) -40°C  TA  +85°C .............................................................................................................. 250 mA 85°C  TA  +125°C ............................................................................................................... 85 mA on VDD pin for 40-Pin devices(1) -40°C  TA  +85°C .............................................................................................................. 350 mA 85°C  TA  +125°C ............................................................................................................. 120 mA on any standard I/O pin ...................................................................................................................... 50 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Total power dissipation(2)................................................................................................................................ 800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 39-6 to calculate device specifications. Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2017-2021 Microchip Technology Inc. DS40001873E-page 659 PIC16(L)F19195/6/7 39.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16(L)F19195/6/7 VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +3.6V PIC16F19195/6/7 VDDMIN (Fosc  16 MHz) ......................................................................................................... +2.3V VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ..................................................................................................................................... -40°C TA_MAX.................................................................................................................................... +85°C Extended Temperature TA_MIN ..................................................................................................................................... -40°C TA_MAX.................................................................................................................................. +125°C Note 1: See Parameter Supply Voltage, DS Characteristics: Supply Voltage.  2017-2021 Microchip Technology Inc. DS40001873E-page 660 PIC16(L)F19195/6/7 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F19195/6/7 ONLY FIGURE 39-1: VDD (V) 5.5 2.5 2.3 0 16 10 4 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 39-7 for each Oscillator mode’s supported frequencies. VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16(L)F19195/6/7 ONLY VDD (V) FIGURE 39-2: 3.6 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 39-7 for each Oscillator mode’s supported frequencies.  2017-2021 Microchip Technology Inc. DS40001873E-page 661 PIC16(L)F19195/6/7 39.3 DC Characteristics TABLE 39-1: PIC16(L)F19195/6/7 Standard Operating Conditions (unless otherwise stated) PIC16F19195/6/7 Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions VDD 1.8 — 3.6 V D002 VDD 2.3 — 3.6 V FOSC  16 MHz, -40C  TA  25C D002 VDD 2.5 — 3.6 V FOSC  16 MHz Supply Voltage D002 FOSC  16 MHz, TA  25C RAM Data Retention(1) D003 VDR 1.5 — — V Device in Sleep mode D003 VDR 1.7 — — V Device in Sleep mode Power-on Reset Release Voltage(2) D004 VPOR — 1.6 — V BOR or LPBOR disabled(3) D004 VPOR — 1.6 — V BOR or LPBOR disabled(3) Power-on Reset Rearm Voltage(2) D005 VPORR — 0.8 — V BOR or LPBOR disabled(3) D005 VPORR — 1.5 — V BOR or LPBOR disabled(3) VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3) D006 SVDD 0.05 — — V/ms BOR or LPBOR disabled(3) † Note 1: 2: 3: 4: Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. See Figure 39-3, POR and POR REARM with Slow Rising VDD. Please see Table 39-11 for BOR and LPBOR trip point information. = LF device  2017-2021 Microchip Technology Inc. DS40001873E-page 662 PIC16(L)F19195/6/7 FIGURE 39-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) Note 1: 2: 3: TPOR(2) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.  2017-2021 Microchip Technology Inc. DS40001873E-page 663 PIC16(L)F19195/6/7 SUPPLY CURRENT (IDD/IBAT)(1,2,4) TABLE 39-2: Standard Operating Conditions (unless otherwise stated) PIC16(L)F19195/6/7 PIC16F19195/6/7 Param. No. Symbol Device Characteristics Min. Typ.† Max. Units Conditions VDD D101 IDDHFO16 HFINTOSC = 16 MHz — 1.79 3.0 mA 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz — 1.85 3.5 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 3.63 5.6 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 3.65 5.8 mA 3.0V D104 IDDIDLE Idle mode, HFINTOSC = 16 MHz — 1.14 2.8 mA 3.0V D104 IDDIDLE Idle mode, HFINTOSC = 16 MHz — 1.2 3.0 mA 3.0V D105 IDDDOZE(3) Doze mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.23 2.5 mA 3.0V D105 IDDDOZE(3) Doze mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.4 2.7 mA 3.0V D106 IBAT VBAT Current with SOSC + RTCC — 1.05 4.8 IBAT VBAT Current with SOSC + RTCC — 1.1 5.0 A A 2.5V D106 † Note 1: 2: 3: 4: Note 2.5V Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in external operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 11-2). PMD bits are all in the default state, no modules are disabled.  2017-2021 Microchip Technology Inc. DS40001873E-page 664 PIC16(L)F19195/6/7 POWER-DOWN CURRENT (IPD)(1,2) TABLE 39-3: PIC16(L)F19195/6/7 Standard Operating Conditions (unless otherwise stated) PIC16F19195/6/7 Standard Operating Conditions (unless otherwise stated) VREGPM = 1 Param. No. Symbol Device Characteristics Min. Typ.† Max. Max. Units +85°C +125°C Conditions VDD D200 IPD IPD Base — 0.35 2.0 9.0 A 3.0V D200 D200A IPD IPD Base — 0.6 4.0 12 18 35 42 D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — 1.1 3.3 9.0 A A A 3.0V — D201 IPD_WDT Low-Frequency Internal Oscillator/WDT — 1.2 3.4 9.0 A 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.6 3.2 6.0 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.8 4.0 7.0 D203 IPD_FVR FVR — 37 57 75 D203 IPD_FVR FVR — 48 58 76 D204 IPD_BOR Brown-out Reset (BOR) — 10 16 18 D204 IPD_BOR Brown-out Reset (BOR) — 14 17 19 D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.35 3.0 5.0 D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.6 3.0 6.0 D206 IPD_ADCA ADC - Active — 395 547 547 D206 IPD_ADCA ADC - Active — 396 590 590 D207 IPD_ADCA_CHGPUMP ADC - Active with Charge Pump — 495 602 602 D207 IPD_ADCA_CHGPUMP ADC - Active with Charge Pump — 495 602 602 D208 IPD_CMP Comparator C1 — 30 45 55 D208 IPD_CMP Comparator C1 — 33 50 60 D209 IPD_CMP_LP LP Comparator C2(6) — 1.3 2.64 3.5 D209 IPD_CMP_LP LP Comparator C2(6) — 1.52 2.65 3.5 D210 IPD_LCD_PUMP_3V 3V Pump Output — 2.8 6.5 9.0 D210 IPD_LCD_PUMP_5V 5V Pump Output — 3.0 7.0 11 A A A A A A A A A A A A A A A A A A Note † 1: 2: 3: 4: 5: 6: Note 3.0V VREGPM = 0 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V ADC is converting (4) 3.0V ADC is converting (4) 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 2.5V 2.5V Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. ADC clock source is FRC. = LF device The IPD spec for the LP comparator does not include current consumed by the supporting clock.  2017-2021 Microchip Technology Inc. DS40001873E-page 665 PIC16(L)F19195/6/7 TABLE 39-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D300 with TTL buffer D301 — — 0.8 V 4.5V  VDD  5.5V — — 0.15 VDD V 1.8V  VDD  4.5V 2.0V  VDD  5.5V D302 with Schmitt Trigger buffer — — 0.2 VDD V D303 with I2C levels — — 0.3 VDD V with SMBus levels — — 0.8 V — — 0.2 VDD V D304 D305 MCLR VIH 2.7V  VDD  5.5V Input High Voltage I/O PORT: D320 with TTL buffer D321 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V 2.0V  VDD  5.5V D322 with Schmitt Trigger buffer 0.8 VDD — — V D323 with I2C levels 0.7 VDD — — V D324 with SMBus levels D325 MCLR IIL D340 — — V — — V — ±5 ± 125 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C — ±5 ± 1000 nA VSS  VPIN  VDD, Pin at high-impedance, 125°C — ± 50 ± 200 nA VSS  VPIN  VDD, Pin at high-impedance, 85°C 25 120 200 A VDD = 3.0V, VPIN = VSS Input Leakage Current(1) I/O Ports D341 MCLR(2) D342 2.7V  VDD  5.5V 2.1 0.7 VDD IPUR Weak Pull-up Current VOL Output Low Voltage D350 D080 Standard I/O ports — — 0.6 V IOL = 8 mA, VDD = 5.0V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V D080A High-Drive I/O Ports — — — — 0.6 0.6 0.6 — — V V V IOH = 10 mA, VDD = 2.3V, HIDCX = 1 IOH = 32 mA, VDD = 3.0V, HIDCX = 1 IOH = 51 mA, VDD = 5.0V, HIDCX = 1 Standard I/O Ports VDD - 0.7 — — V IOH = 3.5 mA, VDD = 5.0V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V High-Drive I/O Ports VDD - 0.7 — VDD - 0.7 VDD - 0.7 — — — V V V IOH = 10 mA, VDD = 2.3V, HIDCX = 1 IOH = 37 mA, VDD = 3.0V, HIDCX = 1 IOH = 54 mA, VDD = 5.0V, HIDCX = 1 — 5 50 pF D090 VOH D090A D380 CIO Output High Voltage All I/O pins † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.  2017-2021 Microchip Technology Inc. DS40001873E-page 666 PIC16(L)F19195/6/7 TABLE 39-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions High Voltage Entry Programming Mode Specifications MEM01 VIHH Voltage on MCLR/VPP pin to enter programming mode 8 — 9 V MEM02 IPPGM Current on MCLR/VPP pin during programming mode — 1 — mA (Note 2, Note 3) (Note 2) Programming Mode Specifications MEM10 VBE VDD for Bulk Erase — 2.7 — V MEM11 IDDPGM Supply Current during Programming operation — — 10 mA Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance MEM21 TD-RET Characteristic Retention 100k 40 MEM22 ND_REF Total Erase/Write Cycles before Refresh MEM23 VD_RW 100k VDD for Read or Erase/Write operation VDDMIN MEM24 TD_BEW Byte Erase and Write Cycle Time E/W -40C  TA  +85C Year Provided no other specifications are violated E/W VDDMAX V 5.0 ms 4.0 Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance 10k — — E/W -40C  TA  +85C (Note 1) MEM32 TP_RET Characteristic Retention — 40 — Year Provided no other specifications are violated MEM33 VP_RD VDD for Read operation VDDMIN — VDDMAX V MEM34 VP_REW VDD for Row Erase or Write operation VDDMIN — VDDMAX V MEM35 TP_REW Self-Timed Row Erase or Self-Timed Write — 2.0 2.5 ms † Note 1: 2: 3: Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. Required only if CONFIG4, bit LVP is disabled. The MPLAB® ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between the ICD2 and target system when programming or debugging with the ICD2.  2017-2021 Microchip Technology Inc. DS40001873E-page 667 PIC16(L)F19195/6/7 TABLE 39-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +125C Param. No. TH01 TH02 Sym. Characteristic Typ. Units θJA Thermal Resistance Junction to Ambient 48.3 C/W 28 C/W 64-pin QFN package 23.9 C/W 64-pin VQFN package 64-pin TQFP package θJC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Conditions 64-pin TQFP package 26.1 C/W 0.24 C/W 64-pin QFN package 8.9 C/W 64-pin VQFN package 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 P I /O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature  2017-2021 Microchip Technology Inc. DS40001873E-page 668 PIC16(L)F19195/6/7 39.4 AC Characteristics FIGURE 39-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins  2017-2021 Microchip Technology Inc. DS40001873E-page 669 PIC16(L)F19195/6/7 FIGURE 39-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS2 OS1 OS2 OS20 CLKOUT (CLKOUT Mode) Note 1: See Table 39-7. TABLE 39-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency — — 500 kHz OS2 TECL_DC Clock Duty Cycle 40 — 60 % ECM Oscillator OS3 FECM Clock Frequency — — 8 MHz OS4 TECM_DC Clock Duty Cycle 40 — 60 % ECH Oscillator OS5 FECH Clock Frequency — — 32 MHz OS6 TECH_DC Clock Duty Cycle 40 — 60 % System Oscillator OS20 FOSC System Clock Frequency — — 32 MHz OS21 FCY Instruction Frequency — FOSC/4 — MHz OS22 TCY Instruction Period 125 1/FCY — ns (Note 2, Note 3) * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 9.0 “Oscillator Module (with Fail-Safe Clock Monitor)”. 3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 39.2 “Standard Operating Conditions”.  2017-2021 Microchip Technology Inc. DS40001873E-page 670 PIC16(L)F19195/6/7 INTERNAL OSCILLATOR PARAMETERS(1) TABLE 39-8: Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions OS50 FHFOSC Precision Calibrated HFINTOSC Frequency — 4 8 12 16 32 — MHz (Note 2) OS51 FHFOSCLP Low-Power Optimized HFINTOSC Frequency — — 1 2 — — MHz MHz OS52 FMFOSC Internal Calibrated MFINTOSC Frequency — 500 — kHz OS53 FLFOSC Internal LFINTOSC Frequency — 31 — kHz OS54 THFOSCST HFINTOSC Wake-up from Sleep Start-up Time — — 11 50 20 — s s OS56 TLFOSCST — 0.2 — ms LFINTOSC Wake-up from Sleep Start-up Time VREGPM = 0 VREGPM = 1 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 39-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature. FIGURE 39-6: PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 0 ± 5% -40 1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Note 1: HFINTOSC accuracy is ±0.2% (typical) at 3V, 25°C.  2017-2021 Microchip Technology Inc. DS40001873E-page 671 PIC16(L)F19195/6/7 TABLE 39-9: PLL SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD 2.5V Param. No. Sym. Characteristic PLL Input Frequency Range Min. Typ† Max. Units Conditions 4 — 8 MHz MHz Note 1 PLL01 FPLLIN PLL02 FPLLOUT PLL Output Frequency Range 16 — 32 PLL03 TPLLST PLL Lock Time from Start-up — 200 — s PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) -0.25 — 0.25 % * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002.  2017-2021 Microchip Technology Inc. DS40001873E-page 672 PIC16(L)F19195/6/7 FIGURE 39-7: CLKOUT AND I/O TIMING Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 CLKOUT IO8, IO9 IO6, IO7 IO5 IO4 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO6, IO7, IO8, IO9 TABLE 39-10: I/O AND CLKOUT TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions IO7* CLKOUT rising edge delay (rising edge Fosc (Q1 cycle) to falling edge CLKOUT CLKOUT falling edge delay (rising TCLKOUTL edge Fosc (Q3 cycle) to rising edge CLKOUT TIO_VALID Port output valid time (rising edge Fosc (Q1 cycle) to port valid) Port input setup time (Setup time TIO_SETUP before rising edge Fosc – Q2 cycle) Port input hold time (Hold time after TIO_HOLD rising edge Fosc – Q2 cycle) TIOR_SLREN Port I/O rise time, slew rate enabled TIOR_SLRDIS Port I/O rise time, slew rate disabled IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD = 3.0V IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD = 3.0V IO10* TINT 25 — — ns IO11* TIOC 25 — — ns IO1* IO2* IO3* IO4* IO5* IO6* TCLKOUTH INT pin high or low time to trigger an interrupt Interrupt-on-Change minimum high or low time to trigger interrupt *These parameters are characterized but not tested.  2017-2021 Microchip Technology Inc. — — 70 ns — — 72 ns — 50 70 ns 20 — — ns 50 — — ns — 25 — ns VDD = 3.0V — 5 — ns VDD = 3.0V DS40001873E-page 673 PIC16(L)F19195/6/7 FIGURE 39-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST03 RST02 RST02 I/O pins Note 1: Asserted low. FIGURE 39-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device not in Brown-out Reset) (Device in Brown-out Reset) (RST08)(1) Reset (due to BOR) (RST04)(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0.  2017-2021 Microchip Technology Inc. DS40001873E-page 674 PIC16(L)F19195/6/7 TABLE 39-11: RESET, WDT, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ† Max. Units RST01* TMCLR MCLR Pulse Width Low to ensure Reset 2 — — s RST02* TIOZ I/O high-impedance from Reset detection — — 2 s RST03 TWDT Watchdog Timer Time-out Period — 16 — ms RST04* TPWRT Power-up Timer Period — 65 — ms RST05 VBOR Brown-out Reset Voltage(4) — 2.70 2.45 1.90 — V V V RST06 VBORHYS Brown-out Reset Hysteresis — 40 — mV RST07 TBORDC Brown-out Reset Response Time — 3 — s RST08 VLPBOR Low-Power Brown-out Reset Voltage — 2.45 — V Conditions 16 ms Nominal Reset Time BORV = 0 BORV = 1 (PIC16F19195/6/7) BORV = 1 (PIC16(L)F19195/6/7) * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. TABLE 39-12: ANALOG-TO-DIGITAL CONVERTER (ADC) ACCURACY SPECIFICATIONS(1,2) Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 12 AD02 EIL Integral Error — ±0.1 ±2.0 LSb ADCREF+ = 3.0V bit AD03 EDL Differential Error — ±0.2 ±1.0 LSb ADCREF+ = 3.0V AD04 EOFF Offset Error — 2 6 LSb ADCREF+ = 3.0V AD05 EGN Gain Error — 2 6 LSb ADCREF+ = 3.0V AD06 VADREF ADC Reference Voltage 1.8 — VDD V AD07 VAIN Full-Scale Range — — ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source — 1 — k AD09 RVREF ADC Voltage Reference Ladder Impedance — 50 — k * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Use of the ADC charge pump to improve linearity performance is recommended for VDD 3.6V — IO7 — — (Note 1) — IO8 — — (Note 1) — 32 FOSC MHz CLC03* TCLCOUT CLC output time Rise Time Fall Time CLC04* FCLCMAX CLC maximum switching frequency * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Table 39-10 for IO5, IO7 and IO8 rise and fall times.  2017-2021 Microchip Technology Inc. DS40001873E-page 682 PIC16(L)F19195/6/7 FIGURE 39-15: EUSART SYNCHRONOUS TRANSMISSION (HOST/CLIENT) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 39-4 for load conditions. TABLE 39-22: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. US120 Symbol TCKH2DTV Characteristic Min. Max. Units Conditions 3.0V  VDD  5.5V SYNC XMIT (Host and Client) Clock high to data-out valid — 80 ns — 100 ns 1.8V  VDD  5.5V US121 TCKRF Clock out rise time and fall time (Host mode) — 45 ns 3.0V  VDD  5.5V — 50 ns 1.8V  VDD  5.5V US122 TDTRF Data-out rise time and fall time — 45 ns 3.0V  VDD  5.5V — 50 ns 1.8V  VDD  5.5V FIGURE 39-16: EUSART SYNCHRONOUS RECEIVE (HOST/CLIENT) TIMING CK US125 DT US126 Note: Refer to Figure 39-4 for load conditions. TABLE 39-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol US125 TDTV2CKL US126 TCKL2DTL Characteristic Min. Max. Units SYNC RCV (Host and Client) Data-setup before CK  (DT hold time) 10 — ns Data-hold after CK  (DT hold time) 15 — ns  2017-2021 Microchip Technology Inc. Conditions DS40001873E-page 683 PIC16(L)F19195/6/7 FIGURE 39-17: SPI HOST MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 39-4 for load conditions. FIGURE 39-18: SPI HOST MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO SP78 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 39-4 for load conditions.  2017-2021 Microchip Technology Inc. DS40001873E-page 684 PIC16(L)F19195/6/7 FIGURE 39-19: SPI CLIENT MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 39-4 for load conditions. FIGURE 39-20: SS SPI CLIENT MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 39-4 for load conditions.  2017-2021 Microchip Technology Inc. DS40001873E-page 685 PIC16(L)F19195/6/7 TABLE 39-24: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. SP70* Symbol Characteristic Min. Typ† Max. Units TSSL2SCH, TSSL2SCL SS to SCK or SCK input 2.25*TCY — — ns SP71* TSCH SCK input high time (Client mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Client mode) TCY + 20 — — ns SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 — — ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 — — ns SP75* TDOR SDO data output rise time TDOF SP76* Conditions — 10 25 ns 3.0V  VDD  5.5V — 25 50 ns 1.8V  VDD  5.5V SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Host mode) — 10 25 ns 3.0V  VDD  5.5V — 25 50 ns 1.8V  VDD  5.5V 25 ns SP79* TSCF SCK output fall time (Host mode) — 10 SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge — — 50 ns 3.0V  VDD  5.5V — — 145 ns 1.8V  VDD  5.5V SP81* TDOV2SCH, TDOV2SCL SDO data output setup to SCK edge 1 Tcy — — ns SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns SP83* TSCH2SSH, TSCL2SSH SS after SCK edge 1.5 TCY + 40 — — ns * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2017-2021 Microchip Technology Inc. DS40001873E-page 686 PIC16(L)F19195/6/7 FIGURE 39-21: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 39-4 for load conditions. TABLE 39-25: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. SP90* Symbol TSU:STA SP91* THD:STA TSU:STO SP92* THD:STO SP93 * Characteristic Min. Typ Max. Units Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Start condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — Stop condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — ns ns These parameters are characterized but not tested. FIGURE 39-22: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 39-4 for load conditions.  2017-2021 Microchip Technology Inc. DS40001873E-page 687 PIC16(L)F19195/6/7 TABLE 39-26: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. SP100* Symbol THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SSP module SP102* SP103* SP106* SP107* SP109* SP110* TR TF THD:DAT TSU:DAT TAA TBUF SDA and SCL rise time SDA and SCL fall time 100 kHz mode Data input hold time Data input setup time Output valid from clock Bus free time Conditions — 250 ns 400 kHz mode 20 + 0.1CB 250 ns 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 100 kHz mode 250 — ns 400 kHz mode 100 — ns 100 kHz mode — 3500 ns 400 kHz mode — — ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start SP111 CB * Note 1: These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 2: Bus capacitive loading  2017-2021 Microchip Technology Inc. DS40001873E-page 688 PIC16(L)F19195/6/7 40.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range.  2017-2021 Microchip Technology Inc. DS40001873E-page 689 PIC16(L)F19195/6/7 ϱ ϯ͘Ϯ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϰ͘ϱ Ϯ͘ϴ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž DĂdž ϰ dLJƉŝĐĂů Ϯ dLJƉŝĐĂů ϯ͘ϱ / ;ŵͿ / ;ŵͿ Ϯ͘ϰ ϭ͘ϲ ϯ Ϯ͘ϱ ϭ͘Ϯ Ϭ͘ϴ Ϯ Ϭ͘ϰ ϭ͘ϱ Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϭ ϱ͘ϱs ϭ͘ϴs Ϯ͘ϯs ϯs s ;sͿ FIGURE 40-1: IDD, HFINTOSC = 16 MHz, PIC16F19195/6/7 Only. ϰ͘ϰ FIGURE 40-4: IDD, HFINTOSC = 32 MHz with PLL, PIC16LF19195/6/7 Only. Ϯ͘ϴ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž ϰ͘ϭ Ϯ͘ϰ ϯ͘ϴ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ Ϯ dLJƉŝĐĂů ϯ͘ϱ /W ;ƵͿ / ;ŵͿ ϯ͘ϲs s ;sͿ ϯ͘Ϯ DĂdž ϭ͘ϲ ϭ͘Ϯ Ϯ͘ϵ dLJƉŝĐĂů Ϭ͘ϴ Ϯ͘ϲ Ϭ͘ϰ Ϯ͘ϯ Ϯ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs Ϭ ϱ͘ϱs ϭ͘ϴs Ϯ͘ϯs ϯs s ;sͿ FIGURE 40-2: IDD, HFINTOSC = 32 MHz with PLL, PIC16F19195/6/7 Only. ϱ͘ϱs ϳϱ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϳϬ Ϯ͘ϰ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž ϲϱ DĂdž Ϯ͘Ϯ ϲϬ Ϯ /W ;ƵͿ / ;ŵͿ ϱs FIGURE 40-5: IPD Base, LP Mode, PIC16F19195/6/7 Only. Ϯ͘ϴ Ϯ͘ϲ ϯ͘ϲs s ;sͿ dLJƉŝĐĂů ϭ͘ϴ ϭ͘ϲ ϱϱ dLJƉŝĐĂů ϱϬ ϰϱ ϭ͘ϰ ϰϬ ϭ͘Ϯ ϯϱ ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs s ;sͿ FIGURE 40-3: IDD, HFINTOSC = 16 MHz, PIC16LF19195/6/7 Only.  2017-2021 Microchip Technology Inc. ϯϬ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϱ͘ϱs s ;sͿ FIGURE 40-6: IPD, Fixed Voltage Reference (FVR), PIC16F19195/6/7 Only. DS40001873E-page 690 PIC16(L)F19195/6/7 ϵϬϬ ϱϬ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϴϬϬ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϰϱ DĂdž ϳϬϬ ϰϬ /W ;ƵͿ /W ;ƵͿ DĂdž ϯϱ ϲϬϬ dLJƉŝĐĂů ϱϬϬ ϰϬϬ dLJƉŝĐĂů ϯϬ ϯϬϬ ϮϬϬ Ϯϱ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϭ͘ϴs ϱ͘ϱs Ϯ͘ϯs ϯs ϱs ϱ͘ϱs FIGURE 40-10: IPD, ADC-Active, PIC16F19195/6/7 Only. FIGURE 40-7: IPD, Comparator C1, PIC16F19195/6/7 Only. ϴ ϰ ϯ͘ϱ ϯ͘ϲs s ;sͿ s ;sͿ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϳ DĂdž DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϲ ϯ DĂdž /W ;ƵͿ /W ;ƵͿ ϱ Ϯ͘ϱ dLJƉŝĐĂů Ϯ ϰ ϯ dLJƉŝĐĂů ϭ͘ϱ Ϯ ϭ ϭ Ϭ Ϭ͘ϱ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϭ͘ϴs ϱ͘ϱs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϱ͘ϱs s ;sͿ s ;sͿ FIGURE 40-8: IPD, Comparator C2, PIC16F19195/6/7 Only. FIGURE 40-11: IPD, Low_Frequency Oscillator/WDT, PIC16F19195/6/7 Only. ϴ ϳ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϲ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž ϲ ϱ DĂdž ϰ ϰ /W ;ƵͿ /W ;ƵͿ ϱ ϯ ϯ Ϯ Ϯ dLJƉŝĐĂů ϭ dLJƉŝĐĂů ϭ Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϱ͘ϱs s ;sͿ FIGURE 40-9: IPD, Secondary Oscillator (SOSC), PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϱ͘ϱs s ;sͿ FIGURE 40-12: IPD, Low-Power Brown-Out Reset (LPBOR), PIC16F19195/6/7 Only DS40001873E-page 691 PIC16(L)F19195/6/7 Ϯϱ Ϯϯ Ϯ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϭ͘ϴ DĂdž Ϯϭ ϭ͘ϲ DĂdž ϭϵ ϭ͘ϰ ϭϳ /W ;ƵͿ /W ;ƵͿ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϭϱ dLJƉŝĐĂů ϭ͘Ϯ ϭ ϭϯ Ϭ͘ϴ ϭϭ Ϭ͘ϲ ϵ Ϭ͘ϰ ϳ Ϭ͘Ϯ dLJƉŝĐĂů ϱ Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϱ͘ϱs ϭ͘ϴs Ϯ͘ϯs s ;sͿ ϯs ϯ͘ϲs s ;sͿ FIGURE 40-16: IPD, Base, LP mode, PIC16LF19195/6/7 Only. FIGURE 40-13: IPD, Brown-Out Reset (BOR), PIC16F19195/6/7 Only. ϴϬ ϵϬϬ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϳϬ ϴϬϬ DĂdž /W ;ƵͿ /W ;ƵͿ ϲϬ ϳϬϬ DĂdž dLJƉŝĐĂů ϲϬϬ ϱϬ ϰϬ ϱϬϬ dLJƉŝĐĂů ϯϬ ϮϬ ϰϬϬ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϭ͘ϴs ϱ͘ϱs Ϯ͘ϯs FIGURE 40-14: IPD, ADC-Active with Charge Pump, PIC16F19195/6/7 Only. ϯ͘ϲs FIGURE 40-17: IPD, Fixed Voltage Reference (FVR), PIC16LF19195/6/7 Only. ϲ ϱ͘ϱ ϯs s ;sͿ s ;sͿ ϱϬ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž ϱ ϰϱ DĂdž /W ;ƵͿ /W ;ƵͿ ϰ͘ϱ ϰ ϰϬ ϯϱ ϯ͘ϱ ϯ dLJƉŝĐĂů dLJƉŝĐĂů ϯϬ Ϯ͘ϱ Ϯ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs s ;sͿ FIGURE 40-15: IPD, 5V Pump Output, PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. Ϯϱ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs s ;sͿ FIGURE 40-18: IPD, Comparator C1, PIC16LF19195/6/7 Only. DS40001873E-page 692 PIC16(L)F19195/6/7 ϰ ϰ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ ϯ͘ϱ ϯ͘ϱ DĂdž ϯ ϯ DĂdž Ϯ͘ϱ Ϯ͘ϱ /W ;ƵͿ /W ;ƵͿ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ Ϯ Ϯ ϭ͘ϱ ϭ͘ϱ dLJƉŝĐĂů dLJƉŝĐĂů ϭ ϭ Ϭ͘ϱ Ϭ͘ϱ Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϭ͘ϴs Ϯ͘ϯs s ;sͿ ϯs ϯ͘ϲs s ;sͿ FIGURE 40-19: IPD, LP Comparator C2, PIC16LF19195/6/7 Only. FIGURE 40-22: IPD, Low_Frequency Internal Oscillator/WDT, PIC16LF19195/6/7 Only ϰ͘ϱ ϳϬϬ ϲϬϬ ϰ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž ϯ͘ϱ DĂdž ϯ /W ;ƵͿ /W ;ƵͿ ϱϬϬ ϰϬϬ dLJƉŝĐĂů Ϯ͘ϱ Ϯ ϯϬϬ ϭ͘ϱ ϮϬϬ ϭ dLJƉŝĐĂů Ϭ͘ϱ ϭϬϬ Ϭ Ϭ ϭ͘ϴ Ϯ͘ϯ ϯ ϭ͘ϴs ϯ͘ϲ Ϯ͘ϯs ϯ͘ϲs FIGURE 40-23: IPD, Low-Power Brown-Out Reset (LPBOR), PIC16LF19195/6/7 Only. FIGURE 40-20: IPD, ADC-Active, PIC16LF19195/6/7 Only. ϳϱϬ ϳϬϬ ϯs s ;sͿ s ;sͿ ϭϵ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ DĂdž ϭϳ ϲϱϬ ϭϱ DĂdž /W ;ƵͿ /W ;ƵͿ ϲϬϬ ϱϱϬ ϭϯ ϭϭ ϱϬϬ dLJƉŝĐĂů dLJƉŝĐĂů ϵ ϰϱϬ ϳ ϰϬϬ ϱ ϯϱϬ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs s ;sͿ FIGURE 40-21: IPD, ADC-Active with Charge Pump, PIC16LF19195/6/7 Only.  2017-2021 Microchip Technology Inc. ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs s ;sͿ FIGURE 40-24: IPD, Brown-Out Reset (BOR), PIC16LF19195/6/7 Only. DS40001873E-page 693 PIC16(L)F19195/6/7 ϰ͘ϱ ϰ Ϭ͘ϬϬϬϬϬϭϰ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ Ϭ͘ϬϬϬϬϬϭϮ ϯ͘ϱ /d ;ƵͿ /W ;ƵͿ Ϭ͘ϬϬϬϬϬϭ DĂdž ϯ Ϯ͘ϱ Ϯ Ϭ͘ϬϬϬϬϬϬϴ Ϭ͘ϬϬϬϬϬϬϲ Ϭ͘ϬϬϬϬϬϬϰ ϭ͘ϱ dLJƉŝĐĂů ϭ Ϭ͘ϬϬϬϬϬϬϮ Ϭ͘ϱ Ϭ ϭ͘ϴ Ϯ͘Ϯ Ϯ͘ϲ ϯ͘Ϭ ϯ͘ϰ Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs sdсϮ͘ϱs s ;sͿ FIGURE 40-25: IPD, Secondary Oscillator (SOSC), PIC16LF19195/6/7 Only. ϯ͘ϴ ϰ͘Ϯ ϰ͘ϲ ϱ͘Ϭ s ;sͿ ϯ͘ϲs FIGURE 40-28: sdсϯ͘Ϭs Typical IBAT. Ϭ͘ϴϬй Ϭ͘ϰϬй ϲ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ Ϭ͘ϬϬй ϱ ZZKZ ;йͿ DĂdž /W ;ƵͿ ϰ ϯ ͲϬ͘ϰϬй ͲϬ͘ϴϬй Ͳϭ͘ϮϬй dLJƉŝĐĂů Ͳϭ͘ϲϬй Ϯ ͲϮ͘ϬϬй ϭ Ϯ͘ϯ Ϯ͘ϳ ϯ͘ϭ ϯ͘ϱ ϯ͘ϵ ϰ͘ϯ ϰ͘ϳ ϱ͘ϭ ϱ͘ϱ s ;sͿ ͲϰϬΣ Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs s ;sͿ FIGURE 40-26: IPD, 3V Pump Output (LP), PIC16LF19195/6/7 Only. ϮϱΣ ϴϱΣ ϭϮϱΣ FIGURE 40-29: LFINTOSC Typical Frequency Error, PIC16F19195/6/7 Only. ϭ͘ϱϬй ϭ͘ϬϬй ϲ DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ Ϭ͘ϱϬй ϱ ZZKZ ;йͿ DĂdž /W ;ƵͿ ϰ ϯ Ϭ͘ϬϬй ͲϬ͘ϱϬй Ͳϭ͘ϬϬй dLJƉŝĐĂů Ͳϭ͘ϱϬй Ϯ ͲϮ͘ϬϬй ϭ͘ϴ ϭ Ϯ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ s ;sͿ ͲϰϬΣ Ϭ ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs s ;sͿ FIGURE 40-27: IPD, 3V Pump Output (NP), PIC16LF19195/6/7 Only.  2017-2021 Microchip Technology Inc. ϮϱΣ ϴϱΣ ϭϮϱΣ FIGURE 40-30: LFINTOSC Typical Frequency Error, PIC16LF19195/6/7 Only. DS40001873E-page 694 PIC16(L)F19195/6/7 Ϭ͘ϮϬй ͲϬ͘ϮϬй ͲϬ͘ϲϬй Ϭ͘ϬϬй Ͳϭ͘ϬϬй ZZKZ ;йͿ ZZKZ ;йͿ ͲϬ͘ϮϬй ͲϬ͘ϰϬй Ͳϭ͘ϰϬй Ͳϭ͘ϴϬй ͲϬ͘ϲϬй ͲϮ͘ϮϬй ͲϬ͘ϴϬй ͲϮ͘ϲϬй Ͳϭ͘ϬϬй Ͳϯ͘ϬϬй ϭ͘ϴ Ϯ͘Ϭ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ͘Ϭ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ ϯ͘ϴ Ϯ͘ϯ ϰ͘Ϭ Ϯ͘ϳ ϯ͘ϭ ϯ͘ϱ ϯ͘ϵ ͲϰϬΣ ϮϱΣ ϰ͘ϯ ϰ͘ϳ ϱ͘ϭ ϱ͘ϱ ϱ͘ϵ s ;sͿ s ;sͿ ϴϱΣ ͲϰϬΣ ϭϮϱΣ FIGURE 40-31: HFINTOSC Typical Frequency Error, PIC16LF19195/6/7 Only. ϮϱΣ ϴϱΣ ϭϮϱΣ FIGURE 40-34: Low-Power Optimized HFINTOSC Typical Frequency Error, PIC16F19195/6/7 Only. Ϭ͘ϮϬй ͲϬ͘ϱϬй Ϭ͘ϬϬй ZZKZ ;йͿ ZZKZ ;йͿ Ͳϭ͘ϬϬй ͲϬ͘ϮϬй ͲϬ͘ϰϬй ͲϬ͘ϲϬй Ͳϭ͘ϱϬй ͲϮ͘ϬϬй ͲϬ͘ϴϬй Ϯ͘ϯ Ϯ͘ϳ ϯ͘ϭ ϯ͘ϱ ϯ͘ϵ ϰ͘ϯ ϰ͘ϳ ϱ͘ϭ ϱ͘ϱ ͲϮ͘ϱϬй s ;sͿ ͲϰϬΣ ϮϱΣ ϭ͘ϴ ϴϱΣ Ϯ͘Ϯ Ϯ͘ϲ ϯ ϭϮϱΣ ϯ͘ϰ ϯ͘ϴ s ;sͿ ͲϰϬΣ FIGURE 40-32: HFINTOSC Typical Frequency Error, PIC16F19195/6/7 Only. ϮϱΣ ϴϱΣ ϭϮϱΣ FIGURE 40-35: Low-Power Optimized HFINTOSC Typical Frequency Error, PIC16LF19195/6/7 Only. ϭ͘ϴϬй ϭ͘ϲϬй Ϭ͘ϬϬϬй ϭ͘ϰϬй ͲϬ͘ϬϬϱй ϭ͘ϮϬй ͲϬ͘ϬϭϬй Ϭ͘ϴϬй ZZKZ ;йͿ ZZKZ ;йͿ ϭ͘ϬϬй Ϭ͘ϲϬй Ϭ͘ϰϬй ͲϬ͘Ϭϭϱй ͲϬ͘ϬϮϬй Ϭ͘ϮϬй ͲϬ͘ϬϮϱй Ϭ͘ϬϬй ͲϬ͘ϮϬй ͲϬ͘ϬϯϬй ͲϬ͘ϰϬй ͲϰϬ Ϯϱ ϴϱ ϭϮϱ dDWZdhZ ;Ϳ dLJƉŝĐĂů нϯƐŝŐŵĂ ͲϯƐŝŐŵĂ FIGURE 40-33: HFINTOSC Typical Frequency Error vs. Temperature, VDD = 3V.  2017-2021 Microchip Technology Inc. ͲϬ͘Ϭϯϱй ͲϰϬ Ϯϱ ϴϱ ϭϮϱ dDWZdhZ ;Ϳ dLJƉŝĐĂů нϯƐŝŐŵĂ ͲϯƐŝŐŵĂ FIGURE 40-36: Low-Power Optimized HFINTOSC Frequency Error, VDD = 3V. DS40001873E-page 695 PIC16(L)F19195/6/7 ϯϱϬ͘Ϭ ϯ *UDSKUHSUHVHQWVı /LPLWV ϮϱϬ͘Ϭ Ϯ ϮϬϬ͘Ϭ sK> ;sͿ WƵůůͲhƉƵƌƌĞŶƚ;ђͿ ϯϬϬ͘Ϭ ϭϱϬ͘Ϭ ϭϮϱΣ ϭϬϬ͘Ϭ ϭ dLJƉŝĐĂů ϱϬ͘Ϭ ͲϰϬΣ Ϭ͘Ϭ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ Ϭ s ;sͿ dLJƉŝĐĂůϮϱΣ Ϭ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ ϭϬ ϮϬ ϯϬ ϰϬ ϱϬ ϲϬ /K> ;ŵͿ Ͳ ϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-37: Weak Pull-Up Current, PIC16F19195/6/7 Only. FIGURE 40-40: VOL vs. IOL Over Temperature, VDD = 5.5V, PIC16F19195/6/7 Only. ϮϬϬ͘Ϭ ϯ͘ϱ ϭϴϬ͘Ϭ ϯ͘Ϭ ϭϰϬ͘Ϭ ϭϮϬ͘Ϭ Ϯ͘ϱ ϭϬϬ͘Ϭ sK, ;sͿ WƵůůͲhƉƵƌƌĞŶƚ;ђͿ *UDSKUHSUHVHQWVı /LPLWV ϭϲϬ͘Ϭ ϴϬ͘Ϭ ϲϬ͘Ϭ Ϯ͘Ϭ ϭ͘ϱ ͲϰϬΣ ϰϬ͘Ϭ ϭ͘Ϭ ϮϬ͘Ϭ dLJƉŝĐĂů Ϭ͘Ϭ ϭ͘ϴ Ϯ͘Ϭ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ͘Ϭ ϯ͘Ϯ ϯ͘ϰ Ϭ͘ϱ ϯ͘ϲ ϭϮϱΣ s ;sͿ dLJƉŝĐĂů ϮϱΣ Ϭ͘Ϭ н ϯʍ ; ϰϬΣ ƚŽ нϭϮϱΣͿ ͲϯϬ ϯʍ ; ϰϬΣ ƚŽ нϭϮϱΣͿ FIGURE 40-38: Weak Pull-Up Current, PIC16LF19195/6/7 Only. ͲϮϱ ͲϮϬ Ͳϭϱ ͲϭϬ Ͳϱ Ϭ /K, ;ŵͿ FIGURE 40-41: VOH vs. IOH Over Temperature, VDD = 3.0V. ϲ *UDSKUHSUHVHQWVı /LPLWV ϯ͘Ϭ ϭϮϱΣ *UDSKUHSUHVHQWVı /LPLWV ϱ ͲϰϬΣ Ϯ͘ϱ dLJƉŝĐĂů Ϯ͘Ϭ ϯ sK> ;sͿ sK, ;sͿ ϰ ϭϮϱΣ dLJƉŝĐĂů ϭ͘ϱ Ϯ ϭ͘Ϭ ͲϰϬΣ ϭ Ϭ͘ϱ Ϭ Ͳϰϱ ͲϰϬ Ͳϯϱ ͲϯϬ ͲϮϱ ͲϮϬ Ͳϭϱ ͲϭϬ Ͳϱ /K, ;ŵͿ FIGURE 40-39: VOH vs. IOH Over Temperature, VDD = 5.5V, PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. Ϭ Ϭ͘Ϭ Ϭ ϱ ϭϬ ϭϱ ϮϬ Ϯϱ ϯϬ ϯϱ ϰϬ ϰϱ ϱϬ ϱϱ ϲϬ /K> ;ŵͿ FIGURE 40-42: VOL vs. IOL Over Temperature, VDD = 3.0V. DS40001873E-page 696 PIC16(L)F19195/6/7 Ϯ͘Ϭ ϱϬ *UDSKUHSUHVHQWVı /LPLWV ϭ͘ϴ ϰϱ ϭ͘ϲ ϰϬ ϭ͘ϰ ϯϱ dLJƉŝĐĂů sK>d' ;sͿ sK, ;sͿ ͲϰϬΣ ϭ͘Ϯ ϭϮϱΣ ϭ͘Ϭ Ϭ͘ϴ ϯϬ Ϯϱ ϮϬ ϭϱ Ϭ͘ϲ ϭϬ Ϭ͘ϰ ϱ Ϭ͘Ϯ Ϭ Ϭ͘Ϭ Ͳϴ Ͳϳ͘ϱ Ͳϳ Ͳϲ͘ϱ Ͳϲ Ͳϱ͘ϱ Ͳϱ Ͳϰ͘ϱ Ͳϰ Ͳϯ͘ϱ Ͳϯ ͲϮ͘ϱ ͲϮ Ͳϭ͘ϱ Ͳϭ ͲϬ͘ϱ ͲϰϬ Ϭ Ϯϱ ϴϱ ϭϮϱ dDWZdhZ ;ΣͿ dLJƉŝĐĂů /K, ;ŵͿ нϯƐŝŐŵĂ ͲϯƐŝŐŵĂ FIGURE 40-46: Brown-Out Reset Hysteresis, Trip Point (BORV = 0), PIC16F19195/6/7 Only. FIGURE 40-43: VOH vs. IOH Over Temperature, VDD = 1.8V, PIC16LF19195/6/7 Only. Ϯ͘ϴ ϭ͘ϴ *UDSKUHSUHVHQWVı /LPLWV ϭ͘ϲ Ϯ͘ϳ ϭ͘ϰ Ϯ͘ϲ dLJƉŝĐĂů sK> ;sͿ ϭϮϱΣ ͲϰϬΣ sK>d' ;sͿ ϭ͘Ϯ ϭ Ϭ͘ϴ Ϭ͘ϲ Ϯ͘ϱ Ϯ͘ϰ Ϯ͘ϯ Ϯ͘Ϯ Ϭ͘ϰ Ϯ͘ϭ Ϭ͘Ϯ Ϯ ͲϰϬ Ϭ Ϭ ϭ Ϯ ϯ ϰ ϱ ϲ ϳ ϴ ϵ ϭϬ ϭϭ ϭϮ ϭϯ ϭϰ ϭϱ ϭϲ ϭϳ ϭϴ ϭϵ Ϯϱ ϮϬ dLJƉŝĐĂů /K> ;ŵͿ FIGURE 40-44: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF19195/6/7 Only. ϴϱ ϭϮϱ dDWZdhZ ;ΣͿ нϯƐŝŐŵĂ ͲϯƐŝŐŵĂ FIGURE 40-47: Brown-Out Reset Voltage, Trip Point (BORV = 1), PIC16F19195/6/7 Only. ϱϬ ϯ ϰϱ ϰϬ Ϯ͘ϵ ϯϱ sK>d' ;sͿ sK>d' ;sͿ Ϯ͘ϴ Ϯ͘ϳ Ϯ͘ϲ ϯϬ Ϯϱ ϮϬ ϭϱ Ϯ͘ϱ ϭϬ ϱ Ϯ͘ϰ Ϭ ͲϰϬ Ϯ͘ϯ ͲϰϬ Ϯϱ ϴϱ dDWZdhZ ;ΣͿ нϯƐŝŐŵĂ ͲϯƐŝŐŵĂ Ϯϱ ϭϮϱ dLJƉŝĐĂů dLJƉŝĐĂů FIGURE 40-45: Brown-Out Reset Voltage, Trip Point (BORV = 0).  2017-2021 Microchip Technology Inc. ϴϱ ϭϮϱ dDWZdhZ ;ΣͿ нϯƐŝŐŵĂ ͲϯƐŝŐŵĂ FIGURE 40-48: Brown-Out Reset Hysteresis, Trip Point (BORV = 1). DS40001873E-page 697 PIC16(L)F19195/6/7 Ϯ͘ϱϲ ϭ͘Ϭ Ϯ͘ϱϮ Ϭ͘ϱ E>;>^ďͿ sK>d' ;sͿ Ϯ͘ϰϴ Ϯ͘ϰϰ Ϭ͘Ϭ Ϯ͘ϰ ͲϬ͘ϱ Ϯ͘ϯϲ Ϯ͘ϯϮ ͲϰϬ Ϯϱ ϴϱ Ͳϭ͘Ϭ ϭϮϱ Ϭ dDWZdhZ ;ΣͿ dLJƉŝĐĂů FIGURE 40-49: нϯƐŝŐŵĂ ϱϭϮ ϭϬϮϰ ϭϱϯϲ ͲϯƐŝŐŵĂ ϮϬϰϴ ϮϱϲϬ ϯϬϳϮ ϯϱϴϰ KƵƚƉƵƚŽĚĞ LPBOR Reset Voltage. FIGURE 40-52: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 1 S, CP ON, 25°C. ϴϬ ϳϬ ϭ͘Ϭ ϱϬ Ϭ͘ϱ ϰϬ E>;>^ďͿ sK>d' ;sͿ ϲϬ ϯϬ ϮϬ Ϭ͘Ϭ ϭϬ ͲϬ͘ϱ Ϭ ͲϰϬ Ϯϱ ϴϱ ϭϮϱ dDWZdhZ ;ΣͿ dLJƉŝĐĂů FIGURE 40-50: нϯƐŝŐŵĂ ͲϯƐŝŐŵĂ Ͳϭ͘Ϭ Ϭ LPBOR Reset Hysteresis. ϱϭϮ ϭϬϮϰ ϭϱϯϲ ϮϬϰϴ ϮϱϲϬ ϯϬϳϮ ϯϱϴϰ KƵƚƉƵƚŽĚĞ FIGURE 40-53: ADC 12-bit Mode, Single-Ended DNL, VDD = 2.3V, VREF = 2.3V, TAD = 1 S, CP ON, 25°C. ϭ͘Ϭ ϭ͘Ϭ Ϭ͘ϱ Ϭ͘Ϭ /E>;>^ďͿ E>;>^ďͿ Ϭ͘ϱ Ϭ͘Ϭ ͲϬ͘ϱ ͲϬ͘ϱ Ͳϭ͘Ϭ Ϭ ϱϭϮ ϭϬϮϰ ϭϱϯϲ ϮϬϰϴ ϮϱϲϬ ϯϬϳϮ ϯϱϴϰ KƵƚƉƵƚŽĚĞ FIGURE 40-51: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V, TAD = 1 S, CP OFF, 25°C.  2017-2021 Microchip Technology Inc. Ͳϭ͘Ϭ Ϭ ϱϭϮ ϭϬϮϰ ϭϱϯϲ ϮϬϰϴ ϮϱϲϬ ϯϬϳϮ ϯϱϴϰ KƵƚƉƵƚŽĚĞ FIGURE 40-54: ADC 12-bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 1 S, CP OFF, 25°C. DS40001873E-page 698 PIC16(L)F19195/6/7 ϭ͘Ϭ ϭ Ϭ͘ϱ Ϭ͘ϱ DĂdžϴϱΣ /E>;>^Ϳ /E>;>^ďͿ DĂdžϮϱΣ Ϭ͘Ϭ DĂdžͲϰϬΣ Ϭ DŝŶϴϱΣ DŝŶϮϱΣ ͲϬ͘ϱ ͲϬ͘ϱ DŝŶͲϰϬΣ Ͳϭ͘Ϭ Ϭ ϱϭϮ ϭϬϮϰ ϭϱϯϲ ϮϬϰϴ ϮϱϲϬ ϯϬϳϮ Ͳϭ ϯϱϴϰ ϭ͘ϴ Ϯ͘ϯ Ϯ͘ϱ KƵƚƉƵƚŽĚĞ ϯ sZ& FIGURE 40-55: ADC 12-bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V, TAD = 1 S, CP ON, 25°C. FIGURE 40-58: ADC 12-bit Mode, Single-Ended Typical INL, VDD = 3.0V, TAD = 1 S, CP ON. ϱ͘Ϭ ϭ͘Ϭ ϰ͘ϱ ϰ͘Ϭ ϯ͘ϱ dŝŵĞ;ђƐͿ /E>;>^ďͿ Ϭ͘ϱ Ϭ͘Ϭ ϯ͘Ϭ Ϯ͘ϱ Ϯ͘Ϭ ϭ͘ϱ ϭ͘Ϭ ͲϬ͘ϱ Ϭ͘ϱ Ϭ͘Ϭ ϭ͘ϳ ϭ͘ϵ Ϯ͘ϭ Ϯ͘ϯ Ϯ͘ϱ Ϯ͘ϳ s ;sͿ Ͳϭ͘Ϭ Ϭ ϱϭϮ ϭϬϮϰ ϭϱϯϲ ϮϬϰϴ ϮϱϲϬ ϯϬϳϮ Ϯ͘ϵ ϯ͘ϭ ϯ͘ϯ ϯ͘ϱ ϯ͘ϳ ϯϱϴϰ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ KƵƚƉƵƚŽĚĞ FIGURE 40-56: ADC 12-bit Mode, Single-Ended INL, VDD = 2.3V, VREF = 2.3V, TAD = 1 S, CP ON, 25°C. FIGURE 40-59: ADC RC Oscillator Period, PIC16LF19195/6/7 Only. ϭ ϰ͘Ϭ ϯ͘ϱ DĂdžϴϱΣ Ϭ͘ϱ ϯ͘Ϭ DĂdžϮϱΣ Ϭ DŝŶϴϱΣ dŝŵĞ;ђƐͿ E>;>^Ϳ Ϯ͘ϱ DĂdžͲϰϬΣ Ϯ͘Ϭ ϭ͘ϱ DŝŶϮϱΣ ϭ͘Ϭ ͲϬ͘ϱ DŝŶͲϰϬΣ Ϭ͘ϱ Ϭ͘Ϭ Ͳϭ Ϯ͘Ϯ ϭ͘ϴ Ϯ͘ϯ Ϯ͘ϱ sZ& FIGURE 40-57: ADC 12-bit Mode, Single-Ended Typical DNL, VDD = 3.0V, TAD = 1 S, CP ON.  2017-2021 Microchip Technology Inc. Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ ϯ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ ϯ͘ϴ ϰ ϰ͘Ϯ ϰ͘ϰ ϰ͘ϲ ϰ͘ϴ ϱ ϱ͘Ϯ ϱ͘ϰ ϱ͘ϲ s ;sͿ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-60: ADC RC Oscillator Period, PIC16F19195/6/7 Only. DS40001873E-page 699 Ϭ͘ϬϮϱ Ϭ͘ϬϬ Ϭ͘ϬϮ ͲϬ͘Ϭϱ Ϭ͘Ϭϭϱ ͲϬ͘ϭϬ Ϭ͘Ϭϭ ͲϬ͘ϭϱ Ϭ͘ϬϬϱ ͲϰϬΣ ϮϱΣ Ϭ /E>;>^ďͿ E>;>^ďͿ PIC16(L)F19195/6/7 ͲϬ͘ϮϬ ͲϰϬΣ ϮϱΣ ͲϬ͘Ϯϱ ϴϱΣ ͲϬ͘ϬϬϱ ϴϱΣ ͲϬ͘ϯϬ ϭϮϱΣ ͲϬ͘Ϭϭ ͲϬ͘ϯϱ ͲϬ͘Ϭϭϱ ͲϬ͘ϰϬ ͲϬ͘ϬϮ ϭϮϱΣ ͲϬ͘ϰϱ Ϭ ϭϲ ϯϮ ϰϴ ϲϰ ϴϬ ϵϲ ϭϭϮ ϭϮϴ ϭϰϰ ϭϲϬ ϭϳϲ ϭϵϮ ϮϬϴ ϮϮϰ ϮϰϬ Ϭ ϭϮ Ϯϰ ϯϲ ϰϴ ϲϬ ϳϮ ϴϰ ϵϲ ϭϬϴ ϭϮϬ ϭϯϮ ϭϰϰ ϭϱϲ ϭϲϴ ϭϴϬ ϭϵϮ ϮϬϰ Ϯϭϲ ϮϮϴ ϮϰϬ ϮϱϮ KƵƚƉƵƚŽĚĞ KƵƚƉƵƚŽĚĞ FIGURE 40-61: Typical DAC DNL Error, VDD = 3.0V, VREF = External 3.0V. FIGURE 40-64: Typical DAC INL Error, VDD = 5.0V, VREF = External 5.0V PIC16F19195/6/7 Only Ϭ͘ϬϬ Ϯϰ ͲϬ͘ϭϬ ϮϮ ͲϬ͘ϭϱ ϮϬ DĂdž͘ ͲϬ͘ϮϬ ͲϰϬΣ ϮϱΣ ͲϬ͘Ϯϱ E>;>^ďͿ /E>;>^ďͿ ͲϬ͘Ϭϱ ϴϱΣ ͲϬ͘ϯϬ ϭϴ dLJƉŝĐĂů ϭϲ ϭϮϱΣ ϭϰ ͲϬ͘ϯϱ DŝŶ͘ 0D[7\SLFDOı ƒ&WRƒ& 7\SLFDOVWDWLVWLFDOPHDQ#ƒ& 0LQ7\SLFDO ı ƒ&WRƒ& ϭϮ ͲϬ͘ϰϬ ͲϬ͘ϰϱ ϭϬ Ϭ ϭϮ Ϯϰ ϯϲ ϰϴ ϲϬ ϳϮ ϴϰ ϵϲ ϭϬϴ ϭϮϬ ϭϯϮ ϭϰϰ ϭϱϲ ϭϲϴ ϭϴϬ ϭϵϮ ϮϬϰ Ϯϭϲ ϮϮϴ ϮϰϬ ϮϱϮ ϭ͘ϲ ϭ͘ϴ Ϯ͘Ϭ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ͘Ϭ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ ϯ͘ϴ KƵƚƉƵƚŽĚĞ KƵƚƉƵƚŽĚĞ FIGURE 40-62: Typical DAC INL Error, VDD = 3.0V, VREF = External 3.0V. FIGURE 40-65: DAC DNL Error, VDD = 3.0V, PIC16LF19195/6/7 Only. Ϭ͘ϬϮϬ Ϭ͘ϰ Ϭ͘Ϭϭϱ sƌĞĨс/Ŷƚ͘sĚĚ Ϭ͘ϬϭϬ sƌĞĨсdžƚ͘ϭ͘ϴs Ϭ͘ϯ ͲϰϬΣ ϮϱΣ Ϭ͘ϬϬϬ ϴϱΣ ϭϮϱΣ ͲϬ͘ϬϬϱ ďƐŽůƵƚĞE>;>^ďͿ E>;>^ďͿ sƌĞĨсdžƚ͘Ϯ͘Ϭs Ϭ͘ϬϬϱ sƌĞĨсdžƚ͘ϯ͘Ϭs Ϭ͘Ϯ Ϭ͘ϭ ͲϬ͘ϬϭϬ ͲϬ͘Ϭϭϱ Ϭ ϭϮ Ϯϰ ϯϲ ϰϴ ϲϬ ϳϮ ϴϰ ϵϲ ϭϬϴ ϭϮϬ ϭϯϮ ϭϰϰ ϭϱϲ ϭϲϴ ϭϴϬ ϭϵϮ ϮϬϰ Ϯϭϲ ϮϮϴ ϮϰϬ ϮϱϮ KƵƚƉƵƚŽĚĞ FIGURE 40-63: Typical DAC DNL Error, VDD = 5.0V, VREF = External 5.0V PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. Ϭ͘Ϭ ͲϲϬ ͲϰϬ ͲϮϬ Ϭ ϮϬ ϰϬ ϲϬ ϴϬ ϭϬϬ ϭϮϬ ϭϰϬ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ FIGURE 40-66: Absolute Value of DAC DNL Error, VDD = 3.0V, VREF = VDD. DS40001873E-page 700 PIC16(L)F19195/6/7 Ϭ͘ϵϬ ϰϱ ϰϯ Ϭ͘ϴϴ ϰϭ sƌĞĨс/Ŷƚ͘sĚĚ ,LJƐƚĞƌĞƐŝƐ;ŵsͿ ďƐŽůƵƚĞ/E>;>^ďͿ ϯϵ sƌĞĨсdžƚ͘ϭ͘ϴs Ϭ͘ϴϲ sƌĞĨсdžƚ͘Ϯ͘Ϭs sƌĞĨсdžƚ͘ϯ͘Ϭs Ϭ͘ϴϰ ϯϳ ϯϱ ϯϯ ϯϭ Ϭ͘ϴϮ Ϯϵ Ϯϳ Ϭ͘ϴϬ Ϯϱ Ϭ Ϭ͘ϳϴ ͲϲϬ͘Ϭ Ϭ͘ϱ ϭ ϭ͘ϱ Ϯ Ϯ͘ϱ ϯ ϯ͘ϱ ŽŵŵŽŶDŽĚĞsŽůƚĂŐĞ;sͿ ͲϰϬ͘Ϭ ͲϮϬ͘Ϭ Ϭ͘Ϭ ϮϬ͘Ϭ ϰϬ͘Ϭ ϲϬ͘Ϭ ϴϬ͘Ϭ ϭϬϬ͘Ϭ ϭϮϬ͘Ϭ ϭϰϬ͘Ϭ ͲϰϬΣ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ FIGURE 40-67: Absolute Value of DAC INL Error, VDD = 3.0V, VREF = VDD. ϮϱΣ ϭϮϱΣ ϴϱΣ FIGURE 40-70: Comparator Hysteresis, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values. Ϭ͘ϯϬ ϯϬ sƌĞĨс/Ŷƚ͘sĚĚ Ϭ͘Ϯϲ Ϯϱ ϮϬ sƌĞĨсdžƚ͘Ϯ͘Ϭs Ϭ͘ϮϮ sƌĞĨсdžƚ͘ϯ͘Ϭs KĨĨƐĞƚsŽůƚĂŐĞ;ŵsͿ ďƐŽůƵƚĞE>;>^ďͿ sƌĞĨсdžƚ͘ϭ͘ϴs sƌĞĨсdžƚ͘ϱ͘Ϭs Ϭ͘ϭϴ ϭϱ ϭϬ Dy ϱ Ϭ Ͳϱ D/E Ϭ͘ϭϰ ͲϭϬ Ͳϭϱ Ϭ͘ϭϬ ͲϲϬ͘Ϭ ͲϰϬ͘Ϭ ͲϮϬ͘Ϭ Ϭ͘Ϭ ϮϬ͘Ϭ ϰϬ͘Ϭ ϲϬ͘Ϭ ϴϬ͘Ϭ ϭϬϬ͘Ϭ ϭϮϬ͘Ϭ ͲϮϬ ϭϰϬ͘Ϭ Ϭ͘Ϭ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ FIGURE 40-68: Absolute Value of DAC DNL Error, VDD = 5.0V, VREF = VDD, PIC16F19195/6/7 Only. Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ŽŵŵŽŶDŽĚĞsŽůƚĂŐĞ;sͿ FIGURE 40-71: Comparator Offset, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25°C. Ϭ͘ϵ Ϭ͘ϴϴ sƌĞĨс/Ŷƚ͘sĚĚ ϯϬ sƌĞĨсdžƚ͘ϭ͘ϴs sƌĞĨсdžƚ͘ϯ͘Ϭs ϮϬ sƌĞĨсdžƚ͘ϱ͘Ϭs KĨĨƐĞƚsŽůƚĂŐĞ;ŵsͿ ďƐŽůƵƚĞ/E>;>^ďͿ Ϯϱ sƌĞĨсdžƚ͘Ϯ͘Ϭs Ϭ͘ϴϲ Ϭ͘ϴϰ Ϭ͘ϴϮ Ϭ͘ϴ ϭϱ ϭϬ Dy ϱ Ϭ Ͳϱ D/E ͲϭϬ Ϭ͘ϳϴ ͲϲϬ͘Ϭ ͲϰϬ͘Ϭ ͲϮϬ͘Ϭ Ϭ͘Ϭ ϮϬ͘Ϭ ϰϬ͘Ϭ ϲϬ͘Ϭ ϴϬ͘Ϭ ϭϬϬ͘Ϭ ϭϮϬ͘Ϭ ϭϰϬ͘Ϭ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ FIGURE 40-69: Absolute Value of DAC INL Error, VDD = 5.0V, VREF = VDD, PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. Ͳϭϱ ͲϮϬ Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ŽŵŵŽŶDŽĚĞsŽůƚĂŐĞ;sͿ FIGURE 40-72: Comparator Offset, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values from -40°C to 125°C. DS40001873E-page 701 ϱϬ ϭϰϬ ϰϱ ϭϮϬ ϰϬ ϭϬϬ ϯϱ 0D[7\SLFDOı ƒ&WRƒ& 7\SLFDOVWDWLVWLFDOPHDQ#ƒ& 0LQ7\SLFDO ı ƒ&WRƒ& ϭϮϱΣ dŝŵĞ;ŶƐͿ ,LJƐƚĞƌĞƐŝƐ;ŵsͿ PIC16(L)F19195/6/7 ϴϬ ϮϱΣ ϯϬ ϲϬ Ϯϱ ϰϬ ͲϰϬΣ ϮϬ ϮϬ Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ Ϭ ŽŵŵŽŶDŽĚĞsŽůƚĂŐĞ;sͿ ͲϰϬΣ ϮϱΣ ϭ͘ϳ ϭϮϱΣ Ϯ͘Ϭ Ϯ͘ϯ Ϯ͘ϲ ϴϱΣ Ϯ͘ϵ ϯ͘Ϯ ϯ͘ϱ s ;sͿ FIGURE 40-76: Comparator Response Time Over Voltage, NP Mode (CxSP = 1), Typical Measured Values, PIC16LF19195/6/7 Only. FIGURE 40-73: Comparator Hysteresis, NP Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values, PIC16F19195/6/7 Only. ϯϬ ϵϬ ϮϬ ϴϬ ϭϱ ϳϬ ϭϬ 0D[7\SLFDOı ƒ&WRƒ& 7\SLFDOVWDWLVWLFDOPHDQ#ƒ& 0LQ7\SLFDO ı ƒ&WRƒ& ϭϮϱΣ ϲϬ Dy dŝŵĞ;ŶƐͿ ,LJƐƚĞƌĞƐŝƐ;ŵsͿ Ϯϱ ϱ Ϭ ϱϬ ϮϱΣ ϰϬ Ͳϱ D/E ϯϬ ͲϭϬ ͲϰϬΣ ϮϬ Ͳϭϱ ϭϬ ͲϮϬ Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ Ϭ ŽŵŵŽŶDŽĚĞsŽůƚĂŐĞ;sͿ Ϯ͘Ϯ FIGURE 40-74: Comparator Offset, NP Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values at 25°C, PIC16F19195/6/7 Only Ϯ͘ϱ Ϯ͘ϴ ϯ͘ϭ ϯ͘ϰ ϯ͘ϳ ϰ͘Ϭ ϰ͘ϯ ϰ͘ϲ ϰ͘ϵ ϱ͘Ϯ ϱ͘ϱ s ;sͿ FIGURE 40-77: Comparator Response Time Over Voltage, NP Mode (CxSP = 1), Typical Measured Values, PIC16F19195/6/7 Only ϭ͕ϰϬϬ ϰϬ 0D[7\SLFDOı ƒ&WRƒ& 7\SLFDOVWDWLVWLFDOPHDQ#ƒ& 0LQ7\SLFDO ı ƒ&WRƒ& ϭ͕ϮϬϬ ϯϬ ϭϬ dŝŵĞ;ŶƐͿ KĨĨƐĞƚsŽůƚĂŐĞ;ŵsͿ ϭ͕ϬϬϬ ϮϬ Dy ϴϬϬ ϭϮϱΣ ϲϬϬ Ϭ ϮϱΣ ϰϬϬ D/E ͲϭϬ ϮϬϬ ͲϰϬΣ ͲϮϬ Ϭ Ϭ͘Ϭ Ϭ͘ϱ ϭ͘Ϭ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ŽŵŵŽŶDŽĚĞsŽůƚĂŐĞ;sͿ FIGURE 40-75: Comparator Offset, NP Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values from -40°C to 125°C, PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. ϱ͘Ϭ ϱ͘ϱ ϭ͘ϴ Ϯ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ s ;sͿ FIGURE 40-78: Comparator Output Filter Delay Time Over Temp., NP Mode (CxSP = 1), Typical Measured Values, PIC16LF19195/6/7 Only. DS40001873E-page 702 PIC16(L)F19195/6/7  ϴϬϬ 0D[7\SLFDOı ƒ&WRƒ& 7\SLFDOVWDWLVWLFDOPHDQ#ƒ& 0LQ7\SLFDO ı ƒ&WRƒ& ϳϬϬ   7LPHQV dŝŵĞ;ŶƐͿ ϲϬϬ ϱϬϬ ϭϮϱΣ ϰϬϬ ϯϬϬ    ϮϱΣ ϮϬϬ  ϭϬϬ ͲϰϬΣ   Ϭ Ϯ͘Ϯ Ϯ͘ϱ Ϯ͘ϴ ϯ͘ϭ ϯ͘ϰ ϯ͘ϳ ϰ ϰ͘ϯ ϰ͘ϲ ϰ͘ϵ ϱ͘Ϯ      7\SLFDOƒ& s ;sͿ FIGURE 40-79: Comparator Output Filter Delay Time Over Temp., NP Mode (CxSP = 1), Typical Measured Values, PIC16F19195/6/7 Only.      9'' 9 ϱ͘ϱ 6LJPDƒ& FIGURE 40-82: Comparator Response Time Rising Edge, PIC16LF19195/6/7 Only.       7LPHQV 7LPHQV                                         9'' 9 7\SLFDOƒ& 9'' 9 6LJPDƒ& FIGURE 40-80: Comparator Response Time Falling Edge, PIC16LF19195/6/7 Only. 7\SLFDOƒ& 6LJPDƒ& FIGURE 40-83: Comparator Response Time Rising Edge, PIC16F19195/6/7 Only.  ϯ͘Ϯ  DĂdž͗ϴϱΣнϯʍ dLJƉŝĐĂů͗ϮϱΣ Ϯ͘ϴ DĂdž  / ;ŵͿ 7LPHQV Ϯ͘ϰ  dLJƉŝĐĂů Ϯ ϭ͘ϲ ϭ͘Ϯ Ϭ͘ϴ  Ϭ͘ϰ  Ϭ                   9'' 9 7\SLFDOƒ& 6LJPDƒ& FIGURE 40-81: Comparator Response Time Falling Edge, PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. ϭ͘ϴs Ϯ͘ϯs ϯs ϯ͘ϲs ϱs ϱ͘ϱs s ;sͿ FIGURE 40-84: Band Gap Ready Time, PIC16LF19195/6/7 Only. DS40001873E-page 703 PIC16(L)F19195/6/7 ϭ͘ϮϬй ϭ͘ϮϬй ϭ͘ϬϬй ϭ͘ϬϬй Ϭ͘ϴϬй ZZKZ ;йͿ ZZKZ ;йͿ Ϭ͘ϴϬй Ϭ͘ϲϬй Ϭ͘ϲϬй Ϭ͘ϰϬй Ϭ͘ϰϬй Ϭ͘ϮϬй Ϭ͘ϮϬй Ϭ͘ϬϬй Ϭ͘ϬϬй ͲϬ͘ϮϬй Ϯ͘ϱ Ϯ͘ϳ Ϯ͘ϵ ϯ͘ϭ ϯ͘ϯ Ϯ͘ϱ ϯ͘ϱ Ϯ͘ϴ ϯ͘ϭ ϯ͘ϰ ϯ͘ϳ s ;sͿ dLJƉŝĐĂůͲϰϬΣ dLJƉŝĐĂůϮϱΣ ϰ ϰ͘ϯ ϰ͘ϲ ϰ͘ϵ ϱ͘Ϯ ϱ͘ϱ s ;sͿ dLJƉŝĐĂůϴϱΣ dLJƉŝĐĂůϭϮϱΣ dLJƉŝĐĂůͲϰϬΣ FIGURE 40-85: Typical FVR Voltage 1x Error, PIC16LF19195/6/7 Only. dLJƉŝĐĂůϮϱΣ dLJƉŝĐĂůϴϱΣ dLJƉŝĐĂůϭϮϱΣ FIGURE 40-88: FVR Voltage Error 2x, PIC16F19195/6/7 Only. ϭ͘ϮϬй ϭ͘ϮϬй ϭ͘ϬϬй ϭ͘ϬϬй Ϭ͘ϴϬй Ϭ͘ϲϬй ZZKZ ;йͿ ZZKZ ;йͿ Ϭ͘ϴϬй Ϭ͘ϲϬй Ϭ͘ϰϬй Ϭ͘ϮϬй Ϭ͘ϰϬй Ϭ͘ϬϬй Ϭ͘ϮϬй ͲϬ͘ϮϬй Ϭ͘ϬϬй ͲϬ͘ϰϬй Ϯ͘ϱ Ϯ͘ϴ ϯ͘ϭ ϯ͘ϰ ϯ͘ϳ ϰ ϰ͘ϯ ϰ͘ϲ ϰ͘ϵ ϱ͘Ϯ ϱ͘ϱ ϰ͘ϴ ϰ͘ϵ ϱ ϱ͘ϭ s ;sͿ dLJƉŝĐĂůͲϰϬΣ dLJƉŝĐĂůϮϱΣ dLJƉŝĐĂůϴϱΣ dLJƉŝĐĂůϭϮϱΣ FIGURE 40-86: Typical FVR Voltage 1x Error, PIC16F19195/6/7 Only. ϱ͘ϯ ϱ͘ϰ ϱ͘ϱ dLJƉŝĐĂůͲϰϬΣ dLJƉŝĐĂůϮϱΣ dLJƉŝĐĂůϴϱΣ dLJƉŝĐĂůϭϮϱΣ FIGURE 40-89: Typical FVR Voltage 4x Error, PIC16F19195/6/7 Only. ϰ ϭ͘ϮϬй ϯ͘ϱ ϭ͘ϬϬй ϯ sK>d' ;sͿ Ϭ͘ϴϬй ZZKZ ;йͿ ϱ͘Ϯ s ;sͿ Ϭ͘ϲϬй Ϭ͘ϰϬй Ϯ͘ϱ Ϯ ϭ͘ϱ Ϭ͘ϮϬй ϭ Ϭ͘ϬϬй Ϭ͘ϱ ͲϬ͘ϮϬй Ϯ͘ϱ Ϯ͘ϴ ϯ͘ϭ ϯ͘ϰ s ;sͿ dLJƉŝĐĂůͲϰϬΣ dLJƉŝĐĂůϮϱΣ dLJƉŝĐĂůϴϱΣ Ϯ͘ϯ ϯ ϯ͘ϲ ϰ ϱ ϱ͘ϱ s ;sͿ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ dLJƉŝĐĂůϭϮϱΣ FIGURE 40-87: Typical FVR Voltage 2x Error, PIC16LF19195/6/7 Only.  2017-2021 Microchip Technology Inc. ϭ͘ϴ FIGURE 40-90: Schmitt Trigger High Values. DS40001873E-page 704 PIC16(L)F19195/6/7 Ϯ͘ϱ ϰ Ϯ͘ϯ ϯ͘ϱ Ϯ͘ϭ ϯ sK>d' ;sͿ sK>d' ;sͿ ϭ͘ϵ ϭ͘ϳ ϭ͘ϱ ϭ͘ϯ Ϯ͘ϱ Ϯ ϭ͘ϱ ϭ͘ϭ ϭ Ϭ͘ϵ Ϭ͘ϱ Ϭ͘ϳ Ϭ ͲϰϬΣ Ϭ͘ϱ ϭ͘ϴ Ϯ͘ϯ ϯ ϯ͘ϲ ϰ ϱ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-91: ϮϱΣ sсϭ͘ϴs Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Schmitt Trigger Low Values. ϴϱΣ ϭϮϱΣ dDWZdhZ ;Ϳ ϱ͘ϱ s ;sͿ FIGURE 40-94: with I2C Level. sсϮ͘ϯs sсϱ͘ϱs Typical Input High Voltage ϭ͘ϴ ϭ͘ϰ ϭ͘ϲ ϭ͘Ϯ ϭ͘ϰ ϭ sK>d' ;sͿ sK>d' ;sͿ ϭ͘Ϯ ϭ Ϭ͘ϴ Ϭ͘ϲ Ϭ͘ϴ Ϭ͘ϲ Ϭ͘ϰ Ϭ͘ϰ Ϭ͘Ϯ Ϭ͘Ϯ Ϭ Ϭ ϭ͘ϴ Ϯ͘ϯ ϯ ϯ͘ϲ ϱ ϱ͘ϱ ͲϰϬΣ ϮϱΣ s ;sͿ dLJƉŝĐĂůϮϱΣ FIGURE 40-92: ϴϱΣ ϭϮϱΣ dDWZdhZ ;Ϳ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ sсϭ͘ϴs Input Voltage TTL. sсϮ͘ϯs sсϱ͘ϱs FIGURE 40-95: Typical Input Low Voltage with SMBus Level. Ϯ Ϯ͘ϱ ϭ͘ϴ ϭ͘ϲ Ϯ ϭ͘Ϯ sK>d' ;sͿ sK>d' ;sͿ ϭ͘ϰ ϭ Ϭ͘ϴ Ϭ͘ϲ ϭ͘ϱ ϭ Ϭ͘ϰ Ϭ͘ϱ Ϭ͘Ϯ Ϭ ͲϰϬΣ ϮϱΣ ϴϱΣ ϭϮϱΣ Ϭ ͲϰϬΣ dDWZdhZ ;Ϳ ϮϱΣ ϴϱΣ ϭϮϱΣ dDWZdhZ ;Ϳ sсϭ͘ϴs sсϮ͘ϯs sсϱ͘ϱs sсϭ͘ϴs FIGURE 40-93: with I2C Level. Typical Input Low Voltage  2017-2021 Microchip Technology Inc. sсϮ͘ϯs sсϱ͘ϱs FIGURE 40-96: Typical Input High Voltage with SMBus Level. DS40001873E-page 705 ϱϬ ϮϬ ϰϱ ϭϴ ϰϬ ϭϲ ϯϱ ϭϰ ϯϬ ϭϮ dŝŵĞ;ŶƐͿ dŝŵĞ;ŶƐͿ PIC16(L)F19195/6/7 Ϯϱ ϮϬ ϭϬ ϴ ϭϱ ϲ ϭϬ ϰ ϱ Ϯ Ϭ Ϭ ϭ͘ϱ Ϯ Ϯ͘ϱ ϯ ϯ͘ϱ ϰ ϰ͘ϱ ϱ ϱ͘ϱ ϭ͘ϱ ϲ Ϯ Ϯ͘ϱ ϯ ϯ͘ϱ dLJƉŝĐĂůϮϱΣ FIGURE 40-97: Control Enabled. нϯ^ŝŐŵĂ;ͲϰϬΣƚŽϭϮϱΣͿ dLJƉŝĐĂůϮϱΣ Rise Time, Slew Rate FIGURE 40-100: Disabled. ϰ͘ϱ ϱ ϱ͘ϱ ϲ нϯ^ŝŐŵĂ;ͲϰϬΣƚŽϭϮϱΣͿ Fall Time, Slew Rate Control Ϯ ϲϬ ϱϬ ϭ͘ϴ ϰϬ ϭ͘ϲ sŽůƚĂŐĞ;sͿ dŝŵĞ;ŶƐͿ ϰ s ;sͿ s ;sͿ ϯϬ нϯ^ŝŐŵĂ dLJƉŝĐĂů ϭ͘ϰ ϮϬ Ͳϯ^ŝŐŵĂ ϭ͘Ϯ ϭϬ ϭ Ϭ ϭ͘ϱ Ϯ Ϯ͘ϱ ϯ ϯ͘ϱ ϰ ϰ͘ϱ ϱ ϱ͘ϱ ϲ Ϭ͘ϴ s ;sͿ dLJƉŝĐĂůϮϱΣ FIGURE 40-98: Enabled. ͲϲϬ ͲϰϬ ͲϮϬ Ϭ ϮϬ ϰϬ ϲϬ ϴϬ ϭϬϬ ϭϮϬ ϭϰϬ dĞŵƉĞƌĂƚƵƌĞ;ΣͿ нϯ^ŝŐŵĂ;ͲϰϬΣƚŽϭϮϱΣͿ Fall Time, Slew Rate Control FIGURE 40-101: POR Rearm Voltage. ϯϬ ϳϰ͘Ϭ Ϯϱ ϳϮ͘Ϭ ϳϬ͘Ϭ dŝŵĞ;ŵƐͿ dŝŵĞ;ŶƐͿ ϮϬ ϭϱ ϲϴ͘Ϭ ϲϲ͘Ϭ ϭϬ ϲϰ͘Ϭ ϱ ϲϮ͘Ϭ Ϭ ϭ͘ϱ Ϯ Ϯ͘ϱ ϯ ϯ͘ϱ ϰ ϰ͘ϱ ϱ ϱ͘ϱ s ;sͿ ϲ ϲϬ͘Ϭ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ ϲ͘Ϭ s ;sͿ dLJƉŝĐĂůϮϱΣ FIGURE 40-99: Control Disabled. нϯ^ŝŐŵĂ;ͲϰϬΣƚŽϭϮϱΣͿ Rise Time, Slew Rate  2017-2021 Microchip Technology Inc. dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳ ϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-102: PWRT Period, PIC16F19195/6/7 Only. DS40001873E-page 706 PIC16(L)F19195/6/7 ϳϱ͘Ϭ Ϯϴ ϳϯ͘Ϭ Ϯϳ ϳϭ͘Ϭ Ϯϲ dŝŵĞ;ђƐͿ dŝŵĞ;ŵƐͿ ϲϵ͘Ϭ ϲϳ͘Ϭ ϲϱ͘Ϭ Ϯϱ Ϯϰ Ϯϯ ϲϯ͘Ϭ ϲϭ͘Ϭ ϮϮ ϱϵ͘Ϭ Ϯϭ ϱϳ͘Ϭ ϭ͘ϲ ϭ͘ϴ Ϯ͘Ϭ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ͘Ϭ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ ϮϬ ϯ͘ϴ ϭ͘ϱ s ;sͿ dLJƉŝĐĂůϮϱΣ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ ϲ͘Ϭ s ;sͿ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳ ϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ dLJƉŝĐĂůϮϱΣ FIGURE 40-103: PWRT Period, PIC16LF19195/6/7 Only. нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-106: Wake from Sleep, VREGPM = 0, HFINTOSC = 16 MHz, PIC16F19195/6/7 Only. ϭϮϬ ϭϴ ϭϭϬ ϭϳ ϭϬϬ ϵϬ dŝŵĞ;ђƐͿ dŝŵĞ;ђƐͿ ϭϲ ϭϱ ϴϬ ϳϬ ϭϰ ϲϬ ϭϯ ϱϬ ϰϬ ϭϮ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ ϭ͘ϱ ϲ͘Ϭ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ dLJƉŝĐĂůϮϱΣ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ ϲ͘Ϭ s ;sͿ s ;sͿ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-107: Wake from Sleep, VREGPM = 1, HFINTOSC = 16 MHz, PIC16F19195/6/7 Only. FIGURE 40-104: Wake from Sleep, VREGPM = 0, HFINTOSC = 4 MHz, PIC16F19195/6/7 Only. ϮϵϬ ϭϴ ϮϳϬ ϭϳ ϮϱϬ d/D ;—^Ϳ dŝŵĞ;ђƐͿ ϭϲ ϭϱ ϮϯϬ ϮϭϬ ϭϵϬ ϭϰ ϭϳϬ ϭϯ ϭϱϬ ϭ͘ϴs ϭϮ ϭ͘ϱ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ ϲ͘Ϭ Ϯ͘ϯs ϯ͘ϲs ϱ͘ϱs s ;sͿ s ;sͿ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-105: Wake from Sleep, VREGPM = 1, HFINTOSC = 4 MHz, PIC16F19195/6/7 Only.  2017-2021 Microchip Technology Inc. ƚLJƉ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-108: LFINTOSC Wake-up from Sleep Start-up Time DS40001873E-page 707 PIC16(L)F19195/6/7 ϰ͘Ϯ dŝŵĞ;ŵƐͿ ϰ͘ϭ ϰ͘Ϭ ϯ͘ϵ ϯ͘ϴ Ϯ͘Ϭ Ϯ͘ϱ ϯ͘Ϭ ϯ͘ϱ ϰ͘Ϭ ϰ͘ϱ ϱ͘Ϭ ϱ͘ϱ ϲ͘Ϭ s ;sͿ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-109: WDT Time-Out Period, PIC16F19195/6/7 Only. ϰ͘Ϯ dŝŵĞ;ŵƐͿ ϰ͘ϭ ϰ͘Ϭ ϯ͘ϵ ϯ͘ϴ ϭ͘ϲ ϭ͘ϴ Ϯ͘Ϭ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ͘Ϭ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ ϯ͘ϴ s ;sͿ dLJƉŝĐĂůϮϱΣ нϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ Ͳϯʍ;ͲϰϬΣƚŽнϭϮϱΣͿ FIGURE 40-110: WDT Time-Out Period, PIC16LF19195/6/7 Only.  2017-2021 Microchip Technology Inc. DS40001873E-page 708 DEVICE FAMILY 41.0 DEVELOPMENT SUPPORT Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs) in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools. Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application, while our line of third party tools round out our comprehensive development tool solutions. Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which support multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows. Go to the following website for more information and details: https://www.microchip.com/development-tools/  2019 Microchip Technology Inc. Advance Information DS00000000A-page 709 DEVICE FAMILY NOTES: DS00000000A-page 710 Advance Information  2019 Microchip Technology Inc. PIC16(L)F19195/6/7 42.0 PACKAGING INFORMATION 42.1 Package Marking Information 64-Lead QFN (9x9x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16LF19195 /MR e3 64-Lead VQFN (9x9x1 mm) Example PIN 1 1526017 PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: PIC16LF19197 /5LX e3 1526017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2017-2021 Microchip Technology Inc. DS40001873E-page 711 PIC16(L)F19195/6/7 42.1 Package Marking Information (Continued) 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16LF19196 /PT e3 Legend: XX...X Y YY WW NNN * Note: 1526017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2017-2021 Microchip Technology Inc. DS40001873E-page 712 PIC16(L)F19195/6/7 The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2017-2021 Microchip Technology Inc. DS40001873E-page 713 PIC16(L)F19195/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2017-2021 Microchip Technology Inc. DS40001873E-page 714 PIC16(L)F19195/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2017-2021 Microchip Technology Inc. DS40001873E-page 715 PIC16(L)F19195/6/7 64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN] With 5.4 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 64X 0.08 C D NOTE 1 A 0.10 C B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X 0.10 A1 TOP VIEW 0.10 C (A3) A C A B SEATING C PLANE D2 SIDE VIEW (K) 0.10 A C A B A E2 e 2 A4 NOTE 1 2 1 D3 SECTION A-A N L e BOTTOM VIEW 64X b 0.10 0.05 STEPPED WETTABLE FLANK C A B C Microchip Technology Drawing C04-483 Rev B Sheet 1 of 2  2017-2021 Microchip Technology Inc. DS40001873E-page 716 PIC16(L)F19195/6/7 64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN] With 5.4 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Notes: Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 Terminal Thickness A3 Overall Length D Exposed Pad Length D2 Overall Width E Exposed Pad Width E2 b Terminal Width Terminal Length L Terminal-to-Exposed-Pad K D3 Wettable Flank Step Length Wettable Flank Step Height A4 MILLIMETERS NOM MAX 64 0.50 BSC 0.90 0.90 1.00 0.00 0.02 0.05 0.203 REF 9.00 BSC 5.30 5.40 5.50 9.00 BSC 5.40 5.30 5.50 0.25 0.20 0.30 0.40 0.30 0.50 1.40 REF 0.035 0.06 0.085 0.05 0.12 0.19 MIN 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-483 Rev A Sheet 2 of 2  2017-2021 Microchip Technology Inc. DS40001873E-page 717 PIC16(L)F19195/6/7 64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN] With 5.4 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 20 1 2 ØV G2 C2 Y2 EV G1 Y1 X1 SILK SCREEN E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X64) X1 Contact Pad Length (X64) Y1 Contact Pad to Center Pad (X64) G1 Contact Pad to Contact Pad (X60) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 8.90 8.90 5.50 5.50 0.30 0.85 1.28 0.20 0.33 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2483 Rev B  2017-2021 Microchip Technology Inc. DS40001873E-page 718 PIC16(L)F19195/6/7 64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN] With 5.4 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 64X 0.08 C D NOTE 1 A 0.10 C B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X 0.10 A1 TOP VIEW 0.10 C (A3) A C A B SEATING C PLANE D2 SIDE VIEW (K) 0.10 A C A B A E2 e 2 A4 NOTE 1 2 1 D3 SECTION A-A N L e BOTTOM VIEW 64X b 0.10 0.05 STEPPED WETTABLE FLANK C A B C Microchip Technology Drawing C04-483 Rev B Sheet 1 of 2  2017-2021 Microchip Technology Inc. DS40001873E-page 719 PIC16(L)F19195/6/7 64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN] With 5.4 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Notes: Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 Terminal Thickness A3 Overall Length D Exposed Pad Length D2 Overall Width E Exposed Pad Width E2 b Terminal Width Terminal Length L Terminal-to-Exposed-Pad K D3 Wettable Flank Step Length Wettable Flank Step Height A4 MILLIMETERS NOM MAX 64 0.50 BSC 0.90 0.90 1.00 0.00 0.02 0.05 0.203 REF 9.00 BSC 5.30 5.40 5.50 9.00 BSC 5.40 5.30 5.50 0.25 0.20 0.30 0.40 0.30 0.50 1.40 REF 0.035 0.06 0.085 0.05 0.12 0.19 MIN 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-483 Rev A Sheet 2 of 2  2017-2021 Microchip Technology Inc. DS40001873E-page 720 PIC16(L)F19195/6/7 64-Lead Very Thin Plastic Quad Flat, No Lead Package (5LX) - 9x9x1.0 mm Body [VQFN] With 5.4 mm Exposed Pad and Stepped Wettable Flanks Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 20 1 2 ØV G2 C2 Y2 EV G1 Y1 X1 SILK SCREEN E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X64) X1 Contact Pad Length (X64) Y1 Contact Pad to Center Pad (X64) G1 Contact Pad to Contact Pad (X60) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 8.90 8.90 5.50 5.50 0.30 0.85 1.28 0.20 0.33 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2483 Rev B  2017-2021 Microchip Technology Inc. DS40001873E-page 721 PIC16(L)F19195/6/7 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D NOTE 2 A B E1/2 E1 A SEE DETAIL 1 E A N 4X N/4 TIPS 0.20 C A-B D 1 3 2 4X NOTE 1 0.20 H A-B D TOP VIEW A2 A 0.05 C SEATING PLANE 0.08 C 64 X b 0.08 e A1 C A-B D SIDE VIEW Microchip Technology Drawing C04-085C Sheet 1 of 2  2017-2021 Microchip Technology Inc. DS40001873E-page 722 PIC16(L)F19195/6/7 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: H c E L (L1) T X=A—B OR D X SECTION A-A e/2 DETAIL 1 Notes: Units Dimension Limits Number of Leads N e Lead Pitch Overall Height A Molded Package Thickness A2 Standoff A1 Foot Length L Footprint L1 I Foot Angle Overall Width E Overall Length D Molded Package Width E1 Molded Package Length D1 c Lead Thickness b Lead Width D Mold Draft Angle Top E Mold Draft Angle Bottom MIN 0.95 0.05 0.45 0° 0.09 0.17 11° 11° MILLIMETERS NOM 64 0.50 BSC 1.00 0.60 1.00 REF 3.5° 12.00 BSC 12.00 BSC 10.00 BSC 10.00 BSC 0.22 12° 12° MAX 1.20 1.05 0.15 0.75 7° 0.20 0.27 13° 13° 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-085C Sheet 2 of 2  2017-2021 Microchip Technology Inc. DS40001873E-page 723 PIC16(L)F19195/6/7 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 E C2 G Y1 X1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X28) X1 Contact Pad Length (X28) Y1 Distance Between Pads G MIN MILLIMETERS NOM 0.50 BSC 11.40 11.40 MAX 0.30 1.50 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2085B Sheet 1 of 1  2017-2021 Microchip Technology Inc. DS40001873E-page 724 PIC16(L)F19195/6/7 APPENDIX A: DATA SHEET REVISION HISTORY Revision E (9/2021) Updated Section 13.4.5; Figure 13.4; Tables 13.4. 39.1; Register 13.5. Revision D (6/2019) Removed Figures 35-11: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive; Figures 35-12: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive; Figure 35-13: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive; and Figure 35-16: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive. Updated Figures 1, 35-6, and 35-7; Registers 11-1, 12-2, 14-1, 14-2, 14-5, 19-8, 19-36, 24-1, 24-2, 24-3, 26-3, 27-1, 28-5, 29-5, and 35-6; Sections 1.0, 9.2.2.3, 19.1.2, 24.0, 24.1, 24.1.1, 24.1.2, 24.1.3, 35.0, 35.1, 35.2, 35.3, 35.3.1, 35.4, 35.5, 35.5.1, 35.5.2, 35.5.3, 35.6.1, 35.7.2, 35.7.3, 35.7.4, 35.7.5, and 35.8; Tables 2, 3, 1-2, 4-12, 13-1, 14-2, 19-1, 30-3, 32-2, 38-1, 39-2, 39-3, 39-6, 39-7, 39-8, 39-12, 39-14, 39-15, and 39-18. Removed Preliminary status. Added Characterization Data. Revision C (9/2017) Updated Equation 19-1; Figures 1, 11-1 and 35-6; Registers 5-2 and 11-2; Sections 11.1, 11.1.1, 11.1.2, and 19.3; Tables 1, 11-1, 19-1, 35-1, 35-4, 35-5, 39-12, and 39-13. Updated TQFP packaging specifications in Section 42. Added Table 35-1: COM and SEG Multiplexing Options. Removed Figure 35-19: Type-A Waveforms in 1/8 MUX, 1/3 Bias Drive. Revision B (3/2017) Added the Register Summary chapter. Corrected Section 4.0 table numbering. Updated Table 4-12. Updated Figure 19-1. Updated Register 19-8. Updated Figure 22-2. Added section 22.2.1. Updated Register 27-1. Updated Register 27-4. Updated Table 35-1. Updated Register 35-7. Revision A (01/2017) Initial release of the document.  2017-2021 Microchip Technology Inc. DS40001873E-page 725 PIC16(L)F19195/6/7 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2017-2021 Microchip Technology Inc. DS40001873E-page 726 PIC16(L)F19195/6/7 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Device: PIC16F19195, PIC16(L)F19195 PIC16F19196, PIC16(L)F19196 PIC16F19197, PIC16(L)F19197 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) 5LX MR PT = 64-lead VQFN (9x9x1mm) = 64-lead QFN (9x9x0.9mm) = 64-lead TQFP (10x10x1) Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) Examples: a) PIC16(L)F19197 - I/PT Industrial temperature TQFP package (Industrial) (Extended) Note 1: 2:  2017-2021 Microchip Technology Inc. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. DS40001873E-page 727 Note the following details of the code protection feature on Microchip products: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. • Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https:// www.microchip.com/en-us/support/design-help/client-supportservices. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, QuietWire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017-2021, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.  2017-2021 Microchip Technology Inc. and its subsidiaries ISBN: 978-1-5224-8907-8 DS40001873E-page 728 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4485-5910 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 Israel - Ra’anana Tel: 972-9-744-7705 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 DS40001873E-page 729 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7288-4388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820  2017-2021 Microchip Technology Inc. and its subsidiaries 09/14/21