PIC16F527-E/GZ

PIC16F527 20-Pin, 8-Bit Flash Microcontroller Processor Features: eXtreme Low-Power (XLP) Features • Interrupt Capability • PIC16F527 Operating Speed: - DC – 20 MHz Crystal oscillator - DC – 200 ns Instruction cycle • High-Endurance Program and Flash Data Memory Cells: - 1024 x 12 user execution memory - 64 x 8 self-writable data memory - 100,000 write program memory endurance - 1,000,000 write Flash data memory endurance - Program and Flash data retention: >40 years • General Purpose Registers (SRAM): - 68 x 8 for PIC16F527 • Only 36 Single-Word Instructions to Learn: - Added RETURN and RETFIE instructions - Added MOVLB instruction • All Instructions are Single-Cycle except for Program Branches which are Two-Cycle • Four-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes for Data and Instructions • Sleep mode 50 nA @ 2.0V, typical • Watchdog Timer (WDT): 500 nA @ 2.0V, typical Peripheral Features: • Device Features: - One Input-only pin - 17 I/Os - Individual direction control - High-current source/sink • 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit Programmable Prescaler • In-Circuit Serial Programming™ (ICSP™) via Two External Pin Connections • Analog Comparator (CMP): - Two analog comparators - Absolute and programmable references • Analog-to-Digital Converter (ADC): - 8-bit resolution - Eight external input channels - One internal channel to convert comparator - 0.6V reference input • Operational Amplifiers (op amps): - Two operational amplifiers - Fully-accessible visibility  2012-2016 Microchip Technology Inc. Microcontroller Features: • • • • • • • • Brown-out Reset (BOR) Power-on Reset (POR) Device Reset Timer (DRT) Watchdog Timer (WDT) with a Dedicated RC Oscillator Programmable Code Protection (CP) Power-Saving Sleep mode with Wake-up on Change Feature Selectable Oscillator Options: - INTOSC: Precision 4 or 8 MHz internal oscillator - EXTRC: Low-cost external RC oscillator - LP: Power-saving, low-frequency crystal - XT: Standard crystal/resonator - HS: High-speed crystal/resonator - EC: High-speed external clock Variety of Packaging Options: - 20-Lead PDIP, SOIC, SSOP, QFN, UQFN CMOS Technology: • Low-Power, High-Speed CMOS Flash Technology • Fully-Static Design • Wide Operating Voltage and Temperature Range: - Industrial: 2.0V to 5.5V - Extended: 2.0V to 5.5V • Operating Current: - 170 uA @ 2V, 4 MHz, typical - 15 uA @ 2V, 32 kHz, typical • Standby Current: - 100 nA @ 2V, typical DS40001652D-page 1 PIC16F527 Data Sheet Index I/O Pins(1) Flash Data EE (B) SRAM (B) 8-Bit ADC Channels Op Amp Comparator 8-Bit Timers BOR Stack Levels Interrupts 8 MHz Int. Osc. Interrupt-on-Change Pins Weak Pull-up Pins XLP PIC16F527 AND PIC16F570 FAMILY TYPES Device TABLE 1: PIC16F527 (1) 18 1 KW 64 68 8 2 2 1 Y 4 Y Y 4 4 Y PIC16F570 (2) 25 2 KW 64 132 8 2 2 1 Y 4 Y Y 8 8 Y Note 1: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001652 PIC16F527 Data Sheet, 20-Pin, 8-bit Flash Microcontroller. PIC16F570 Data Sheet, 28-Pin, 8-bit Flash Microcontroller. 2: DS40001684 FIGURE 1: 20-PIN DIAGRAM FOR PIC16F527 VDD 1 RA5 2 3 RA4 RA3/MCLR/VPP FIGURE 2: PIC16F527 PDIP, SSOP, SOIC 20 19 VSS 18 RA1/ICSPCLK RA2 RC0 17 RA0/ICSPDAT RC5 4 5 RC4 6 RC3 7 RC6 8 13 RC1 RC2 RB4 RC7 RB7 9 12 RB5 10 11 RB6 16 15 14 20-PIN DIAGRAM FOR PIC16F527 DS40001652D-page 2 VSS RA0/ICSPDAT 17 16 VDD 18 RC2 9 10 RC1 11 8 RC0 12 RB5 RB4 RC6 RA2 PIC16F527 13 RB6 RC3 RA4 RA5 3 4 5 RA1/ICSPCLK 14 7 RC4 15 6 2 RB7 1 RC5 RC7 RA3/MCLR/VPP 20 19 QFN, UQFN  2012-2016 Microchip Technology Inc. PIC16F527 Oscillator Comparator Reference Timers Op Amp Clock Reference 16 AN0 — C1IN+ — — — — ICSPDAT — Y Y 18 15 AN1 — C1IN- CVREF — — — ICSPCLK — Y Y RA2 17 14 AN2 — C1OUT — T0CKI — — — — — — RA3 4 1 — — — — — — — — MCLR VPP Y Y RA4 3 20 AN3 OSC2 — — — — CLKOUT — — Y Y — — — Basic Interrupt-on-Change Analog 19 RA1 Pull-up 20-Pin QFN/UQFN RA0 ICSP™ 20-Pin PDIP/SOIC/SSOP 20-PIN ALLOCATION TABLE I/O TABLE 2: RA5 2 19 — OSC1 — — — — CLKIN — RB4 13 10 — — — — — OP2- — — — — — RB5 12 9 — — — — — OP2+ — — — — — RB6 11 8 — — — — — — — — — — — RB7 10 7 — — — — — — — — — — — RC0 16 13 AN4 — C2IN+ — — — — — — — — RC1 15 12 AN5 — C2IN- — — — — — — — — RC2 14 11 AN6 — — — — OP2 — — — — — RC3 7 4 AN7 — — — — OP1 — — — — — RC4 6 3 — — C2OUT — — — — — — — — RC5 5 2 — — — — — — — — — — — RC6 8 5 — — — — — OP1- — — — — — RC7 9 6 — — — — — OP1+ — — — — — VDD 1 18 — — — — — — — — — — — VSS 20 17 — — — — — — — — — — —  2012-2016 Microchip Technology Inc. DS40001652D-page 3 PIC16F527 Table of Contents 1.0 General Description..................................................................................................................................................................... 5 2.0 PIC16F527 Device Varieties ..................................................................................... .................................................................. 6 3.0 Architectural Overview ................................................................................................................................................................ 7 4.0 Memory Organization ................................................................................................................................................................ 12 5.0 Self-Writable Flash Data Memory Control ................................................................................................................................. 22 6.0 I/O Port ...................................................................................................................................................................................... 26 7.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 31 8.0 Special Features of the CPU ..................................................................................................................................................... 36 9.0 Analog-to-Digital (A/D) Converter.............................................................................................................................................. 54 10.0 Comparator(s) ........................................................................................................................................................................... 59 11.0 Comparator Voltage Reference Module .................................................................................................................................... 64 12.0 Operational Amplifier (OPA) Module ......................................................................................................................................... 66 13.0 Instruction Set Summary ........................................................................................................................................................... 68 14.0 Development Support................................................................................................................................................................ 76 15.0 Electrical Characteristics ........................................................................................................................................................... 80 16.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 98 17.0 Packaging Information............................................................................................................................................................. 112 The Microchip Website...................................................................................................................................................................... 130 Customer Change Notification Service ............................................................................................................................................. 130 Customer Support ............................................................................................................................................................................. 130 Product Identification System............................................................................................................................................................ 131 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS40001652D-page 4  2012-2016 Microchip Technology Inc. PIC16F527 1.0 GENERAL DESCRIPTION The PIC16F527 device from Microchip Technology is a low-cost, high-performance, 8-bit, fully-static, Flashbased CMOS microcontroller. It employs a RISC architecture with only 36 single-word/single-cycle instructions. All instructions are single cycle except for program branches, which take two cycles. The PIC16F527 device delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easy to remember instruction set reduces development time significantly. The PIC16F527 product is equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are several oscillator configurations to choose from, including INTRC Internal Oscillator mode and the power-saving LP (Low-Power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. 1.1 Applications The PIC16F527 device fits in applications ranging from personal care appliances and security systems to lowpower remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16F527 device very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and PLDs in larger systems and coprocessor applications). The PIC16F527 device is available in the cost-effective Flash programmable version, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC16F527 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer and a full-featured programmer. All the tools are supported on IBM® PC and compatible machines. TABLE 1-1: FEATURES AND MEMORY OF PIC16F527 PIC16F527 Clock Maximum Frequency of Operation (MHz) Memory Flash Program Memory Peripherals Features 20 1024 SRAM Data Memory (bytes) 68 Flash Data Memory (bytes) 64 Timer Module(s) TMR0 Wake-up from Sleep on Pin Change Yes I/O Pins 17 Input Pins 1 Internal Pull-ups Yes In-Circuit Serial ProgrammingTM Yes Number of Instructions 36 Packages 20-pin PDIP, SOIC, SSOP, QFN, UQFN Interrupts Yes  2012-2016 Microchip Technology Inc. DS40001652D-page 5 PIC16F527 2.0 PIC16F527 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16F527 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 Quick Turn Programming (QTP) Devices 2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number. Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. DS40001652D-page 6  2012-2016 Microchip Technology Inc. PIC16F527 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F527 device can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F527 device uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions execute in a single cycle (200 ns @ 20 MHz, 1 s @ 4 MHz) except for program branches. The PIC16F527 device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is eight bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other operand is either a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Table 3-1 below lists memory supported by the PIC16F527 device. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. TABLE 3-1: A simplified block diagram is shown in Figure 3-2, with the corresponding device pins described in Table 3-2. PIC16F527 MEMORY Program Memory Data Memory Device PIC16F527 Flash (words) SRAM (bytes) Flash (bytes) 1024 68 64 The PIC16F527 device can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC16F527 device has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any Addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC16F527 device simple, yet efficient. In addition, the learning curve is reduced significantly.  2012-2016 Microchip Technology Inc. DS40001652D-page 7 PIC16F527 FIGURE 3-1: PIC16F527 BLOCK DIAGRAM 11 Flash 1K x 12 Self-write 64x8 STACK2 STACK3 Program Bus 12 STACK4 RAM Addr RA0/ICSPDAT RA1/ICSPCLK RA2 RA3 RA4 RA5 9 PORTB Addr MUX Instruction reg 0-4 Direct Addr 3 PORTA RAM 68 bytes File Registers STACK1 Program Memory 8 Data Bus Program Counter Direct Addr BSR 0-7 5-7 RB4 RB5 RB6 RB7 Indirect Addr FSR reg PORTC STATUS reg 8 3 Brown-out Reset Instruction Decode & Control Device Reset Timer Power-on Reset OSC1/CLKIN OSC2/CLKOUT Timing Generation Watchdog Timer Internal RC Clock RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 MUX ALU 8 OPAMP1 & OPAMP2 W reg OP1 OP1OP1+ OP2 OP2OP2+ Timer0 MCLR Comparator 1 VDD, VSS T0CKI VREF C2IN+ AN0 Comparator 2 AN1 AN2 AN3 C1IN+ C1INC1OUT 8-bit ADC AN4 CVREF CVREF AN5 C2INC2OUT CVREF AN6 AN7 VDD DS40001652D-page 8  2012-2016 Microchip Technology Inc. PIC16F527 TABLE 3-2: PIC16F527 PINOUT DESCRIPTION Name Function Input Type Output Type RA0/AN0/C1IN+/ICSPDAT RA0 TTL CMOS ICSPDAT ST CMOS C1IN+ AN — Comparator 1 input. AN0 AN — ADC channel input. RA1 TTL CMOS RA1/AN1/C1IN-/CVREF/ ICSPCLK RA2/AN2/C1OUT/T0CKI RA3/MCLR/VPP RA4/AN3/OSC2/CLKOUT RA5/OSC1/CLKIN RB4/OP2RB5/OP2+ Description Bidirectional I/O pin. It can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSP™ mode Schmitt Trigger. Bidirectional I/O pin. It can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPCLK ST — ICSP™ mode Schmitt Trigger. C1IN- AN — Comparator 1 input. CVREF — AN Programmable Voltage Reference output. AN1 AN — RA2 TTL CMOS Bidirectional I/O port. ADC channel input. C1OUT — CMOS Comparator 1 output. AN2 AN — ADC channel input. T0CKI ST — Timer0 Schmitt Trigger input pin. RA3 TTL — Standard TTL input with weak pull-up. MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. Weak pull-up is always on if configured as MCLR. Test mode high-voltage pin. VPP HV — RA4 TTL CMOS Bidirectional I/O pin. It can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. OSC2 — XTAL Oscillator crystal output. Connections to crystal or resonator in Crystal Oscillator mode (XT, HS and LP modes only, PORTB in other modes). CLKOUT — CMOS EXTRC/INTRC CLKOUT pin (FOSC/4). AN3 AN — RA5 TTL CMOS OSC1 XTAL — CLKIN ST — RB4 TTL CMOS OP2- AN — RB5 TTL CMOS ADC channel input. Bidirectional I/O port. XTAL oscillator input pin. EXTRC Schmitt Trigger input. Bidirectional I/O port. Op amp 2 inverting input. Bidirectional I/O port. OP2+ AN — RB6 RB6 TTL CMOS RB7 RB7 TTL CMOS Bidirectional I/O port. RC0/AN4/C2IN+ RC0 ST CMOS Bidirectional I/O port. RC1/AN5/C2IN- Legend: Op amp 2 non-inverting input. Bidirectional I/O port. AN4 AN — ADC channel input. C2IN+ AN — Comparator 2 input. RC1 ST CMOS Bidirectional I/O port. AN5 AN — ADC channel input. C2IN- AN — Comparator 2 input. I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input, HV = High Voltage, AN = Analog Voltage  2012-2016 Microchip Technology Inc. DS40001652D-page 9 PIC16F527 TABLE 3-2: PIC16F527 PINOUT DESCRIPTION (CONTINUED) Name RC2/AN6/OP2 RC3/AN7/OP1 RC4/C2OUT Function Input Type Output Type Description RC2 ST CMOS AN6 AN — ADC channel input. OP2 — AN Op amp 2 output. RC3 ST CMOS AN7 AN — ADC channel input. OP1 — AN Op amp 1 output. RC4 ST CMOS Bidirectional I/O port. Comparator 2 output. Bidirectional I/O port. Bidirectional I/O port. C2OUT — CMOS RC5 RC5 ST CMOS Bidirectional I/O port. RC6/OP1- RC6 ST CMOS Bidirectional I/O port. OP1- AN — RC7/OP1+ Op amp 1 inverting input. RC7 ST CMOS OP1+ AN — Op amp 1 non-inverting input. VDD VDD — P Positive supply for logic and I/O pins. VSS VSS — P Ground reference for logic and I/O pins. Legend: Bidirectional I/O port. I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input, HV = High Voltage, AN = Analog Voltage DS40001652D-page 10  2012-2016 Microchip Technology Inc. PIC16F527 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO or an interrupt), then two cycles are required to complete the instruction (see Example 3-1). The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1. A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC PC PC + 1 Fetch INST (PC) Execute INST (PC – 1) EXAMPLE 3-1: PC + 2 Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTB, BIT1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.  2012-2016 Microchip Technology Inc. DS40001652D-page 11 PIC16F527 4.1 Program Memory Organization for PIC16F527 The PIC16F527 device has an 11-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Program memory is partitioned into user memory, data memory and configuration memory spaces. The user memory space is the on-chip user program memory. As shown in Figure 4-1, it extends from 0x000 to 0x3FF and partitions into pages, including an Interrupt vector at address 0x004 and a Reset vector at address 0x3FF. MEMORY MAP 000h Interrupt Vector User Memory Space The PIC16F527 memories are organized into program memory and data memory (SRAM).The self-writable portion of the program memory called self-writable Flash data memory is located at addresses 400h-43Fh. All program mode commands that work on the normal Flash memory, work on the Flash data memory. This includes bulk erase, row/column/cycling toggles, Load and Read data commands (Refer to Section 5.0 “SelfWritable Flash Data Memory Control” for more details). For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the PIC16F527, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR). FIGURE 4-1: Data Memory Space MEMORY ORGANIZATION On-chip User Program Memory (Page 0) On-chip User Program Memory (Page 1) Reset Vector Self-writable Flash Data Memory User ID Locations Backup OSCCAL Locations Configuration Memory Space 4.0 004h 005h 1FFh 200h 3FEh 3FFh 400h 43Fh 440h 443h 444h 447h 448h Reserved 49Fh 4A0h Unimplemented 7FEh Configuration Word 7FFh The data memory space is the self-writable Flash data memory block and is located at addresses PC = 400h43Fh. All program mode commands that work on the normal Flash memory, work on the Flash data memory block. This includes bulk erase, Load and Read data commands. The configuration memory space extends from 0x440 to 0x7FF. Locations from 0x448 through 0x49F are reserved. The user ID locations extend from 0x440 through 0x443. The Backup OSCCAL locations extend from 0x444 through 0x447. The Configuration Word is physically located at 0x7FF. Refer to “PIC16F527 Memory Programming Specification” (DS41640) for more details. DS40001652D-page 12  2012-2016 Microchip Technology Inc. PIC16F527 4.2 4.2.1 Data Memory (SRAM and SFRs) Data memory is composed of registers or bytes of SRAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). GENERAL PURPOSE REGISTER FILE The General Purpose Register file is accessed directly or indirectly. See Section 4.8 “Direct and Indirect Addressing”. 4.2.2 The Special Function Registers are registers used by the CPU and peripheral functions for controlling desired operations of the PIC16F527. See Section 4.3 “STATUS Register” for details. SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (see Section 4.3 “STATUS Register”). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. FIGURE 4-2: PIC16F527 REGISTER FILE MAP BSR 00 01 40h 11 60h 00h INDF(1) INDF(1) INDF(1) 01h TMR0 EECON TMR0 IW 02h PCL PCL PCL PCL 03h STATUS STATUS STATUS STATUS INDF(1) 04h FSR FSR FSR FSR 05h OSCCAL EEDATA OSCCAL INTCON1 06h PORTA EEADR PORTA ISTATUS 07h PORTB CM1CON0 PORTB IFSR 08h PORTC CM2CON0 PORTC IBSR 09h ADCON0 VRCON ADCON0 OPACON 0Ah ADRES INTCON0 ANSEL INTCON0 ADRES INTCON0 4Ch ANSEL INTCON0 0Bh 2Ch 0Ch General Purpose Registers 10h 4Fh 30h General Purpose Registers 1Fh 6Fh 50h General Purpose Registers 3Fh Bank 0 6Ch Addresses map back to addresses in Bank 0. 2Fh 0Fh Note 1: 10 20h File Address 70h General Purpose Registers 5Fh Bank 1 General Purpose Registers 7Fh Bank 2 Bank 3 Not a physical register. See Section 4.8 “Direct and Indirect Addressing”.  2012-2016 Microchip Technology Inc. DS40001652D-page 13 PIC16F527 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Value on all other Resets Bank 0 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) ---- -000 ---- -0uu — — — — — — BSR1 BSR0 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 02h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111 (2) Reserved Reserved PA0 TO PD Z DC 03h STATUS 04h FSR(2) 05h OSCCAL 06h PORTA 07h PORTB RB7 RB6 RB5 RB4 — — 08h PORTC RC7 RC6 RC5 RC4 RC3 RC2 09h ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE 0Ah ADRES RAIF — — — 0Bh — C Indirect data memory address pointer -00q qqqq 0uuu uuuu CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- uuuu uuu- — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu — — xxxx ---- uuuu ---- RC1 RC0 xxxx xxxx uuuu uuuu ADON 1111 1100 1111 1100 xxxx xxxx uuuu uuuu 0000 ---0 0000 ---0 ADC Conversion Result INTCON0 -001 1xxx 0xxx xxxx ADIF CWIF T0IF GIE Bank 1 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) ---- -0uu 20h INDF 21h EECON 22h PCL(1) 23h STATUS(2) 24h FSR(2) 25h EEDATA 26h EEADR — — — — — — BSR1 BSR0 ---- -000 Uses contents of FSR to address data memory (not a physical register) — — xxxx xxxx uuuu uuuu — FREE WRERR WREN WR RD ---0 0000 ---0 0000 1111 1111 1111 1111 PA0 TO PD Z DC C -001 1xxx -00q qqqq 0xxx xxxx 0uuu uuuu xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu quuu uuuu Low-order eight bits of PC Reserved — Reserved Indirect data memory address pointer Self Read/Write Data — — Self Read/Write Address 27h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 28h CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 quuu uuuu 29h VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 001- 0000 uuu- uuuu 2Ah ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 RAIF — — — GIE 0000 ---0 0000 ---0 2Bh INTCON0 Legend: Note 1: 2: 3: ADIF CWIF T0IF x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable), q = value depends on condition. Shaded cells = unimplemented or unused The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access these bits. Registers are implemented as two physical registers. When executing from within an ISR, a secondary register is used at the same logical location. Both registers are persistent. See Section 8.11 “Interrupts”. These registers show the contents of the registers in the other context: ISR or main line code. See Section 8.11 “Interrupts”. DS40001652D-page 14  2012-2016 Microchip Technology Inc. PIC16F527 TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Value on all other Resets Bank 2 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) ---- -000 ---- -0uu — — — — — — BSR1 BSR0 40h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 41h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu 42h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111 -001 1xxx -00q qqqq (2) 43h STATUS 44h FSR(2) 45h OSCCAL Reserved — CAL6 Reserved PA0 TO PD Z DC C Indirect data memory address pointer CAL5 0xxx xxxx 0uuu uuuu CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- uuuu uuu- 46h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu 47h PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- 48h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 49h ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 1111 1100 1111 1100 4Ah ADRES xxxx xxxx uuuu uuuu RAIF — — — 0000 ---0 0000 ---0 4Bh INTCON0 ADC Conversion Result ADIF CWIF T0IF GIE Bank 3 N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111 N/A BSR(2) ---- -000 ---- -0uu — — — — — — BSR1 BSR0 60h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 61h IW(3) Interrupt Working Register. (Addressed also as W register when within ISR) xxxx xxxx xxxx xxxx 62h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111 63h STATUS(2) -001 1xxx -00q qqqq 64h FSR(2) 0xxx xxxx 0uuu uuuu Reserved — Reserved DC — — C ADIE CWIE T0IE RAIE WUR 0000 ---0 0000 ---0 Reserved PA0 TO PD Z DC C -xxx xxxx -00q qqqq 0xxx xxxx 0uuu uuuu — — — BSR1 BSR0 ---- -0xx ---- -0uu — — — — OPA2ON OPA1ON ---- --00 ---- --00 T0IF RAIF — — — GIE 0000 ---0 0000 ---0 67h IFSR(3) — 68h IBSR(3) — 69h OPACON — — 6Bh INTCON0 ADIF CWIF 3: Z Reserved INTCON1 ISTATUS(3) 2: PD — 65h Note 1: TO Indirect data memory address pointer 66h Legend: PA0 Indirect data memory address pointer — — x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable), q = value depends on condition. Shaded cells = unimplemented or unused The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access these bits. Registers are implemented as two physical registers. When executing from within an ISR, a secondary register is used at the same logical location. Both registers are persistent. See Section 8.11 “Interrupts”. These registers show the contents of the registers in the other context: ISR or main line code. See Section 8.11 “Interrupts”.  2012-2016 Microchip Technology Inc. DS40001652D-page 15 PIC16F527 4.3 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 4-1: For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 13.0 “Instruction Set Summary”. STATUS: STATUS REGISTER R-0 R-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x Reserved Reserved PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Reserved: Read as ‘0’ bit 5 PA0: Program Page Preselect bit 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur; Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred DS40001652D-page 16  2012-2016 Microchip Technology Inc. PIC16F527 4.4 OPTION Register The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. Note: By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION bits. REGISTER 4-2: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of RAPU and RAWU). OPTION: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RAWU(2) RAPU T0CS(1) T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RAWU: Enable PORTA Interrupt Flag on Pin Change bit(2) 1 = Disabled 0 = Enabled bit 6 RAPU: Enable PORTA Weak Pull-Ups bit 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Clock Source Select bit(1) 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS: Prescaler Rate Select bits Note 1: 2: Bit Value Timer0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 x = Bit is unknown If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin. The RAWU bit of the OPTION register must be cleared to enable the RAIF function in the INTCON0 register.  2012-2016 Microchip Technology Inc. DS40001652D-page 17 PIC16F527 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the 8 MHz internal oscillator macro. It contains seven bits of calibration that uses a two’s complement scheme for controlling the oscillator speed. See Register 4-3 for details. REGISTER 4-3: OSCCAL: OSCILLATOR CALIBRATION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 CAL: Oscillator Calibration bits 0111111 = Maximum frequency • • • 0000001 0000000 = Center frequency 1111111 • • • 1000000 = Minimum frequency bit 0 Unimplemented: Read as ‘0’ DS40001652D-page 18 x = Bit is unknown  2012-2016 Microchip Technology Inc. PIC16F527 4.6 4.6.1 Program Counter EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code. For a GOTO instruction, bits of the PC are provided by the GOTO instruction word. The Program Counter (PCL) is mapped to PC. Bit 5 of the STATUS register provides page information to bit 9 of the PC (see Figure 4-3). The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is pre-selected. For a CALL instruction, or any instruction where the PCL is the destination, bits of the PC again are provided by the instruction word. However, PC does not come from the instruction word, but is always cleared (see Figure 4-3). Instructions where the PCL is the destination, or modify PCL instructions, include MOVWF PCL, ADDWF PCL and BSF PCL,5. Note: Because bit 8 of the PC is cleared in the CALL instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). FIGURE 4-3: LOADING OF PC BRANCH INSTRUCTIONS GOTO Instruction 10 9 8 7 PC 0 PCL Instruction Word PA0 7 Status CALL or Modify PCL Instruction 10 9 8 7 4.7 Stack The PIC16F527 device has a 4-deep, 12-bit wide hardware PUSH/POP stack. A CALL instruction or an interrupt will PUSH the current PC value, incremented by one, into Stack Level 1. If there was a previous value in the Stack 1 location, it will be pushed into the Stack 2 location. This process will be continued throughout the remaining stack locations populated with values. If more than four sequential CALLs are executed, only the most recent four return addresses are stored. A RETLW, RETURN or RETFIE instruction will POP the contents of Stack Level 1 into the PC. If there was a previous value in the Stack 2 location, it will be copied into the Stack Level 1 location. This process will be continued throughout the remaining stack locations populated with values. If more than four sequential RETLWs are executed, the stack will be filled with the address previously stored in Stack Level 4. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Note 1: There are no Status bits to indicate Stack Overflows or Stack Underflow conditions. 0 PC Therefore, upon a Reset, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 0 2: There are no instruction mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETFIE and RETLW instructions. PCL 7 Instruction Word Reset to ‘0’ PA0 0 Status  2012-2016 Microchip Technology Inc. DS40001652D-page 19 PIC16F527 4.8 4.8.1 Direct and Indirect Addressing DIRECT DATA ADDRESSING: BSR REGISTER Traditional data memory addressing is performed in the Direct Addressing mode. In Direct Addressing, the Bank Select Register bits BSR, in the new BSR register, are used to select the data memory bank. The address location within that bank comes directly from the opcode being executed. BSR are the bank select bits and are used to select the bank to be addressed (00 = Bank 0, 01 = Bank 1, 10 = Bank 2, 11 = Bank 3). A new instruction supports the addition of the BSR register, called the MOVLB instruction. See Section 13.0 “Instruction Set Summary” for more information. 4.8.2 INDIRECT DATA ADDRESSING: INDF AND FSR REGISTERS The INDF Register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR Register (FSR is a pointer). This is indirect addressing. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF Register indirectly results in a no-operation (although Status bits may be affected). The FSR is an 8-bit wide register. It is used in conjunction with the INDF Register to indirectly address the data memory area. The FSR bits are used to select data memory addresses 00h to 1Fh. FSR is unimplemented and read as ‘0’. A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-1. EXAMPLE 4-1: NEXT MOVLW MOVWF CLRF INCF BTFSC GOTO CONTINUE : : HOW TO CLEAR RAM USING INDIRECT ADDRESSING 0x10 FSR INDF FSR,F FSR,4 NEXT DS40001652D-page 20 ;initialize pointer ;to RAM ;clear INDF ;register ;inc pointer ;all done? ;NO, clear next ;YES, continue  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 4-4: (BSR) 1 DIRECT/INDIRECT ADDRESSING Direct Addressing (opcode) 0 Bank Select 4 3 2 1 Indirect Addressing (FSR) 0 6 Location Select 5 4 3 2 1 0 Location Select 00 01 10 11 00h Data Memory(1) 0Bh 0Ch Addresses map back to addresses in Bank 0. 0Fh 10h 2Fh 4Fh 6Fh 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1:For register map detail see Figure 4-2.  2012-2016 Microchip Technology Inc. DS40001652D-page 21 PIC16F527 5.0 SELF-WRITABLE FLASH DATA MEMORY CONTROL Flash Data memory consists of 64 bytes of selfwritable memory and supports a self-write capability that can write a single byte of memory at one time. Data to be written to the self-writable data memory is first written into a write latch before writing the data to Flash memory. Although each Flash data memory location is 12 bits wide, access is limited to the lower eight bits. The upper four bits will automatically default to ‘1’ in any self-write procedure. The lower eight bits are fully readable and writable during normal operation and throughout the full VDD range. The self-writable Flash data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers, EECON, EEDATA and EEADR. Note 1: To prevent accidental corruption of the Flash data memory, an unlock sequence is required to initiate a write or erase cycle. This sequence requires that the bit set instructions used to configure the EECON register happen exactly as shown in Example 5-2 and Example 5-3, depending on the operation requested. 2: In order to prevent any disruptions of selfwrites or row erases performed on the self-writable Flash data memory, interrupts should be disabled prior to executing those routines. 5.1.1 A row must be manually erased before writing new data. The following sequence must be performed for a single row erase. 1. 5.1 Reading Flash Data Memory To read a Flash data memory location the user must: • Write the EEADR register • Set the RD bit of the EECON register The value written to the EEADR register determines which Flash data memory location is read. Setting the RD bit of the EECON register initiates the read. Data from the Flash data memory read is available in the EEDATA register immediately. The EEDATA register will hold this value until another read is initiated or it is modified by a write operation. Program execution is suspended while the read cycle is in progress. Execution will continue with the instruction following the one that sets the WR bit. See Example 5-1 for sample code. EXAMPLE 5-1: READING FROM FLASH DATA MEMORY MOVLB 0x01 MOVF DATA_EE_ADDR,W ; ; Switch to Bank 1 MOVWF EEADR 2. 3. 4. 5. Load EEADR with an address in the row to be erased. Set the FREE bit to enable the erase. Set the WREN bit to enable write access to the array. Disable interrupts. Set the WR bit to initiate the erase cycle. If the WREN bit is not set in the instruction cycle after the FREE bit is set, the FREE bit will be cleared in hardware. If the WR bit is not set in the instruction cycle after the WREN bit is set, the WREN bit will be cleared in hardware. Sample code that follows this procedure is included in Example 5-2. Program execution is suspended while the erase cycle is in progress. Execution will continue with the instruction following the one that sets the WR bit. EXAMPLE 5-2: ERASING A FLASH DATA MEMORY ROW ; Data Memory ; Address to read BSF EECON, RD ; EE Read MOVF EEDATA, W ; W = EEDATA Note: Only a BSF command will work to enable the Flash data memory read documented in Example 5-1. No other sequence of commands will work, no exceptions. DS40001652D-page 22 ERASING FLASH DATA MEMORY MOVLB 0x01 ; Switch to Bank 1 MOVLW EE_ADR_ERASE ; LOAD ADDRESS OF ROW TO MOVWF EEADR ; BSF EECON,FREE ; SELECT ERASE BSF EECON,WREN ; ENABLE WRITES BSF EECON,WR ; INITITATE ERASE ; ERASE  2012-2016 Microchip Technology Inc. PIC16F527 EXAMPLE 5-3: Note 1: The FREE bit may be set by any command normally used by the core. However, the WREN and WR bits can only be set using a series of BSF commands, as documented in Example 5-1. No other sequence of commands will work, no exceptions. 2: Bits of the EEADR register indicate which row is to be erased. 5.1.2 MOVLW MOVWF EE_ADR_WRITE EEADR MOVLW MOVWF EE_DATA_WRITE EEDATA BSF BCF BSF EECON, WREN INTCON, GIE EECON,WR The self-write operation writes one byte of data at one time. The data must first be loaded into a write latch. Once the write latch is loaded, the data will be written to Flash data memory. Note 1: Only a series of BSF commands will work to enable the memory write sequence documented in Example 5-3. No other sequence of commands will work, no exceptions. 2: For reads, erases and writes to the Flash data memory, there is no need to insert a NOP into the user code as is done on midrange devices. The instruction immediately following the “BSF EECON,WR/RD” will be fetched and executed properly. The self-write sequence is shown below. 4. 5. ;LOAD ADDRESS ;INTO EEADR ;REGISTER ;LOAD DATA ;INTO EEDATA ;REGISTER ;ENABLE WRITES ;DISABLE INTERRUPTS ;LOAD WRITE LATCH ;AND PERFORM DATA ;MEMORY WRITE WRITING TO FLASH DATA MEMORY Once a cell is erased, new data can be written. Program execution is suspended during the write cycle. 1. 2. 3. WRITING TO FLASH DATA MEMORY Load EEADR with the address. Load EEDATA with the data to be written. Set the WREN bit to enable write access to the array. Disable interrupts. Set the WR bit to load the data into the write latch. Once the WR bit is set and the processor recognizes that the write latch is loaded, it will immediately perform the Flash data memory write of that byte. The specific sequence of setting the WREN bit and setting the WR bit must be executed to properly initiate loading of the write latches and the write to Flash data memory. If the WR bit is not set in the instruction cycle after the WREN bit is set, the WREN bit will be cleared in hardware. 5.2 Write/Verify Depending on the application, good programming practice may dictate that data written to the Flash data memory be verified. Example 5-4 is an example of a write/verify. EXAMPLE 5-4: WRITE/VERIFY OF FLASH DATA MEMORY MOVF EEDATA, W ;EEDATA has not changed BSF EECON, RD ;Read the value written ;from previous write XORWF EEDATA, W ; BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error ;Yes, continue Sample code that follows this procedure is included in Example 5-3.  2012-2016 Microchip Technology Inc. DS40001652D-page 23 PIC16F527 5.3 Register Definitions — Memory Control REGISTER 5-1: EEDATA: FLASH DATA REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EEDATA7 EEDATA6 EEDATA5 EEDATA4 EEDATA3 EEDATA2 EEDATA1 EEDATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EEDATA: Eight bits of data to be read from/written to data Flash REGISTER 5-2: EEADR: FLASH ADDRESS REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’. bit 5-0 EEADR: Six bits of data to be read from/written to data Flash DS40001652D-page 24  2012-2016 Microchip Technology Inc. PIC16F527 REGISTER 5-3: EECON: FLASH CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FREE WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’. bit 4 FREE: Flash Data Memory Row Erase Enable bit 1 = Program memory row being pointed to by EEADR will be erased on the next write cycle. No write will be performed. This bit is cleared at the completion of the erase operation. 0 = Perform write only bit 3 WRERR: Write Error Flag bit 1 = A write operation terminated prematurely (by device Reset) 0 = Write operation completed successfully bit 2 WREN: Write Enable bit 1 = Allows write cycle to Flash data memory 0 = Inhibits write cycle to Flash data memory bit 1 WR: Write Control bit 1 = Initiate a erase or write cycle 0 = Write/Erase cycle is complete bit 0 RD: Read Control bit 1 = Initiate a read of Flash data memory 0 = Do not read Flash data memory 5.4 Code Protection Code protection does not prevent the CPU from performing read or write operations on the Flash data memory. Refer to the code protection chapter for more information.  2012-2016 Microchip Technology Inc. DS40001652D-page 25 PIC16F527 6.0 I/O PORT As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at highimpedance) since the I/O control registers are all set. 6.1 PORTA PORTA is a 6-bit I/O register. Only the low-order six bits are used (RA). Bits 7 and 6 are unimplemented and read as ‘0’s. Please note that RA3 is an input-only pin. The Configuration Word can set several I/Os to alternate functions. When acting as alternate functions, the pins will read as ‘0’ during a port read. Pins RA0, RA1, RA3 and RA4 can be configured with weak pull-ups and also for wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If RA3/MCLR is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled. DS40001652D-page 26 6.2 PORTB PORTB is a 4-bit I/O register. Only the high-order four bits are used (RB). Bits 0 through 3 are unimplemented and read as ‘0’s. 6.3 PORTC PORTC is an 8-bit I/O register. 6.4 TRIS Register The Output Driver Control register is loaded with the contents of the W register by executing the TRIS instruction. A ‘1’ from a TRIS register bit puts the corresponding output driver in a High-Impedance mode. A ‘0’ puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are RA3, which is input-only and the T0CKI pin, which may be controlled by the OPTION register (see Register 4-2). TRIS registers are “write-only”. Active bits in these registers are set (output drivers disabled) upon Reset.  2012-2016 Microchip Technology Inc. PIC16F527 6.5 I/O Interfacing The equivalent circuit for an I/O port pin is shown in Figure 6-1. All port pins, except the MCLR pin which is input-only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except MCLR) can be programmed individually as input or output. FIGURE 6-1: BLOCK DIAGRAM OF I/O PIN (Example shown of RA2 with Weak Pull-up and Wake-up on change) RxPU Data Bus D Q Data Latch WR Port I/O Pin(1) Q CK W Reg D Q TRIS Latch TRIS ‘f’ Q CK Reset (2) ADC pin Ebl (2) COMP pin Ebl RD Port Q D CK Pin Change ADC COMP Note 1: 2:  2012-2016 Microchip Technology Inc. I/O pins have protection diodes to VDD and VSS. Pin enabled as analog for ADC or comparator. DS40001652D-page 27 PIC16F527 6.6 Register Definitions — PORT Control TABLE 6-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA: PORTA I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is VIH min. 0 = Port pin is VIH min. 0 = Port pin is 4.5V, C1 = C2  30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. Figure 8-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs. +5V To Other Devices 10k 74AS04 4.7k CLKIN 74AS04 PIC® Device 10k XTAL 10k 20 pF 20 pF Figure 8-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 8-4: 330 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT To Other Devices 330 74AS04 74AS04 74AS04 CLKIN 0.1 mF PIC® Device XTAL 8.3.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 8-5 shows how the R/C combination is connected to the PIC16F527 device. For REXT values below 3.0 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 5.0 k and 100 k.  2012-2016 Microchip Technology Inc. DS40001652D-page 39 PIC16F527 Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no external capacitance or with values below 20 pF, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Section 15.0 “Electrical Characteristics” shows RC frequency variation from part-to-part due to normal process variation. The variation is larger for larger values of R (since leakage current variation will affect RC frequency more for large R) and for smaller values of C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications section for variation of oscillator frequency due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for given R, C and VDD values. FIGURE 8-5: EXTERNAL RC OSCILLATOR MODE 8.3.5 The internal RC oscillator provides a fixed 4/8 MHz (nominal) system clock at VDD = 5V and 25°C, (see Section 15.0 “Electrical Characteristics” for information on variation overvoltage and temperature). In addition, a calibration instruction is programmed into the last address of memory, which contains the calibration value for the internal RC oscillator. This location is always non-code protected, regardless of the code-protect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the Reset vector. This will load the W register with the calibration value upon Reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register or ignoring it. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. Note: VDD REXT OSC1 Internal clock N CEXT PIC® Device VSS FOSC/4 DS40001652D-page 40 OSC2/CLKOUT INTERNAL 4/8 MHz RC OSCILLATOR Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. For the PIC16F527 device, only bits of OSCCAL are used for calibration. See Register 4-3 for more information. Note: The bit 0 of the OSCCAL register is unimplemented and should be written as ‘0’ when modifying OSCCAL for compatibility with future devices.  2012-2016 Microchip Technology Inc. PIC16F527 8.4 Reset The device differentiates between various kinds of Reset: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Time-out Reset during normal operation WDT Time-out Reset during Sleep Wake-up from Sleep on pin change Some registers are not reset in any way, they are unknown on POR/BOR and unchanged in any other Reset. Most other registers are reset to “Reset state” on Power-on Reset (POR)/Brown-out Reset (BOR), MCLR, WDT or Wake-up on pin change Reset during normal operation. They are not affected by a WDT Reset during Sleep or MCLR Reset during Sleep, since these Resets are viewed as resumption of normal operation. The exceptions to this are the TO and PD bits. They are set or cleared differently in different Reset situations. These bits are used in software to determine the nature of Reset. See Table 4-1 for a full description of Reset states of all registers. TABLE 8-3: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h Power-on Reset (POR) or Brown-out Reset (BOR) 0001 1xxx MCLR Reset during normal operation 000u uuuu MCLR Reset during Sleep 0001 0uuu WDT Reset during Sleep 0000 0uuu WDT Reset normal operation 0000 uuuu Wake-up from Sleep on pin change 1001 0uuu Wake-up from Sleep on comparator change 0101 0uuu Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.  2012-2016 Microchip Technology Inc. DS40001652D-page 41 PIC16F527 8.4.1 MCLR ENABLE This Configuration bit, when set to a ‘1’, enables the external MCLR Reset function. When cleared to ‘0’, the MCLR function is tied to the internal VDD and the pin is assigned to be an input-only pin function. See Figure 8-6. FIGURE 8-6: MCLR SELECT RAPU MCLR/VPP MCLRE 8.5 Internal MCLR Power-on Reset (POR) The PIC16F527 device incorporates an on-chip Poweron Reset (POR) circuitry, which provides an internal chip Reset for most power-up situations. The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program the MCLR/VPP pin as MCLR and tie through a resistor to VDD, or program the pin as an input pin. An internal weak pull-up resistor is implemented using a transistor (refer to Table 15-8 for the pull-up resistor ranges). This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Section 15.0 “Electrical Characteristics” for details. When the device starts normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating parameters are met. The Power-on Reset circuit and the Device Reset Timer (see Section 8.6 “Device Reset Timer (DRT)”) circuit are closely related. On power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, it will reset the Reset latch and thus end the on-chip Reset signal. A power-up example where MCLR is held low is shown in Figure 8-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. In Figure 8-9, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be an input pin). The VDD is stable before the start-up timer times out and there is no problem in getting a proper Reset. However, Figure 8-10 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip may not function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (see Figure 89). Note: When the device starts normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Notes AN522, Power-Up Considerations (DS00522) and AN607, Power-up Trouble Shooting (DS00607). A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 8-7. DS40001652D-page 42  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 8-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) BOR BOREN MCLR/VPP MCLR Reset WDT Time-out Pin Change Sleep WDT Reset S Q R Q Device Reset Timer (10 us or 18 ms) CHIP Reset Wake-up on pin Change Reset Comparator Change Wake-up on Comparator Change TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) FIGURE 8-8: VDD MCLR Internal POR TDRT DRT Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME FIGURE 8-9: VDD MCLR Internal POR TDRT DRT Time-out Internal Reset  2012-2016 Microchip Technology Inc. DS40001652D-page 43 PIC16F527 FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1  VDD min. DS40001652D-page 44  2012-2016 Microchip Technology Inc. PIC16F527 8.6 Device Reset Timer (DRT) On the PIC16F527 device, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 8-4). The DRT operates on an internal RC oscillator. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD min. and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a Reset condition after MCLR has reached a logic high (VIH MCLR) level. Programming MCLR/VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases. This allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of that pin as a general purpose input. The Device Reset Time delays will vary from chip-tochip due to VDD, temperature and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out from Sleep. This is particularly important for applications using the WDT to wake from Sleep mode automatically. Reset sources are POR, MCLR, WDT time-out and wake-up on pin or comparator change. See Section 8.10.2 “Wake-up from Sleep”, Notes 1, 2 and 3. 8.7 TABLE 8-4: Oscillator Configuration TYPICAL DRT PERIODS POR Reset Subsequent Resets HS, XT, LP 18 ms 18 ms EC 10 us 10 s INTOSC, EXTRC 10 us 10 s 8.7.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst-case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. 8.7.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device Reset. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT wake-up Reset. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the external RC oscillator of the OSC1/CLKIN pin and the internal 4/8 MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset. The TO bit of the STATUS register will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration WDTE as a ‘0’ (see Section 8.1 “Configuration Bits”). Refer to the PIC16F527 Programming Specifications to determine how to access the Configuration Word.  2012-2016 Microchip Technology Inc. DS40001652D-page 45 PIC16F527 FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure 7-1) 0 M U X 1 Watchdog Time Postscaler 8-to-1 MUX PS(1) PSA WDT Enable Configuration Bit To Timer0 (Figure 7-4) 0 1 MUX PSA(1) WDT Time-out Note 1: TABLE 8-5: PSA, PS are bits in the OPTION register. REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page OPTION RAWU RAPU T0SC T0SE PSA PS2 PS1 PS0 17 Legend: Shaded boxes = Not used by Watchdog Timer. 8.8 Time-out Sequence (TO) and Power-down (PD) Reset Status The TO and PD bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset. TABLE 8-6: TO/PD STATUS AFTER RESET TO PD Reset Caused By 0 0 WDT wake-up from Sleep 0 u WDT time-out (not from Sleep) 1 0 MCLR wake-up from Sleep 1 1 Power-up or Brown-out Reset u u MCLR not during Sleep Legend: u = unchanged Note 1: The TO and PD bits maintain their status (u) until a Reset occurs. A low pulse on the MCLR input does not change the TO and PD Status bits. DS40001652D-page 46  2012-2016 Microchip Technology Inc. PIC16F527 8.9 Brown-out Reset (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 8-12). If enabled, the Device Reset Timer will now be invoked, and will keep the chip in Reset an additional 18 ms. A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. The Brown-out Reset feature is enabled by the BOREN Configuration bit. Note: If VDD falls below VBOR for greater than parameter (TBOR) (see Figure 8-12), the brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOR for less than parameter (TBOR). If VDD drops below VBOR while the Device Reset Timer is running, the chip will go back into a Brown-out Reset and the Device Reset Timer will be re-initialized. Once VDD rises above VBOR, the Device Reset Timer will execute a 18 ms Reset. Please see Section 15.0 “Electrical Characteristics” for the VBOR specification and other parameters shown in Figure 8-12. FIGURE 8-12: The Device Reset Timer is enabled by the DRTEN bit in the Configuration Word register. BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) TBOR Reset (due to BOR) TDRT FIGURE 8-13: BROWN-OUT SITUATIONS VDD Internal Reset VBOR 18 ms (DRTEN = 1) VDD Internal Reset VBOR < 18 ms 18 ms (DRTEN = 1) VDD Internal Reset  2012-2016 Microchip Technology Inc. VBOR 18 ms (DRTEN = 1) DS40001652D-page 47 PIC16F527 8.10 Power-down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). 8.10.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit of the STATUS register is set, the PD bit of the STATUS register is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or high-impedance). Note: The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. Note: Caution: Right before entering Sleep, read the comparator Configuration register(s) CM1CON0 and CM2CON0. When in Sleep, wake-up occurs when the comparator output bit C1OUT and C2OUT change from the state they were in at the last reading. If a wake-up on comparator change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately, even if no pins change while in Sleep mode. A Reset generated by a WDT time-out does not drive the MCLR pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the MCLR/VPP pin must be at a logic high level if MCLR is enabled. 8.10.2 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. An external Reset input on RB3/MCLR/VPP pin, when configured as MCLR. A Watchdog Timer Time-out Reset (if WDT was enabled). From an interrupt source, see Section 8.11 “Interrupts” for more information. On waking from Sleep, the processor will continue to execute the instruction immediately following the SLEEP instruction. If the WUR bit is also set, upon waking from Sleep, the device will reset. If the GIE bit is also set, upon waking from Sleep, the processor will branch to the interrupt vector. Please see Section 8.11 “Interrupts” for more information. The TO and PD bits can be used to determine the cause of the device Reset. The TO bit is cleared if a WDT time-out occurred and subsequently caused a wake-up. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. . Note: Caution: Right before entering Sleep, read the input pins. When in Sleep, wakeup occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode. DS40001652D-page 48  2012-2016 Microchip Technology Inc. PIC16F527 8.11 Interrupts The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. These following interrupt sources are available on the PIC16F527 device: • • • • Timer0 Overflow ADC Completion Comparator Output Change Interrupt-on-change pin Refer to the corresponding chapters for details. 8.11.1 OPERATION Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) 8.12 Automatic Context Switching While the device is executing from the ISR, a secondary set of W, STATUS, FSR and BSR registers are used by the CPU. These registers are still addressed at the same location, but hold persistent, independent values for use inside the ISR. This allows the contents of the primary set of registers to be unaffected by interrupts in the main line execution. The contents of the secondary set of context registers are visible in the SFR map as the IW, ISTATUS, IFSR and IBSR registers. When executing code from within the ISR, these registers will read back the main line context, and vice versa. The RETFIE instruction exits the ISR by popping the previous address from the stack, switching back to the original set of critical registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits may be set, regardless of the state of any other enable bits. The enable bits for specific interrupts can be found in the INTCON1 register. An interrupt is recorded for a specific interrupt via flag bits found in the INTCON0 register. The ADC Conversion flag and the Timer0 Overflow flags will be set regardless of the status of the GIE and individual interrupt enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. The Comparator and Interrupt-on-change flags must be enabled for use. One or both of the comparator outputs can be enabled to affect the interrupt flag by clearing the C1WU bit in the CM1CON0 register and the C2WU bit in the CM2CON0 register. The Interrupton-change flag is enabled by clearing the RAWU bit in the OPTION register. 4: The user must manage the contents of the context registers if they are using interrupts that will vector to the Interrupt Service Routine (ISR). The context registers (IW, ISTATUS, IFSR and IBSR) power up in unknown states following POR and BOR events. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Several registers are automatically switched to a secondary set of registers to store critical data. (See Section 8.12 “Automatic Context Switching”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.  2012-2016 Microchip Technology Inc. 3: All interrupts should be disabled prior to executing writes or row erases in the selfwritable Flash data memory. 8.13 Interrupts during Sleep Any of the interrupt sources can be used to wake from Sleep. To wake from Sleep, the peripheral must be operating without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 8.10 “Power-down Mode (Sleep)” for more details. DS40001652D-page 49 PIC16F527 TABLE 8-7: INTERRUPT PRIORITIES In Sleep GIE WUR X 1 0 1 X 1 Wake-up Inline 1 0 0 Watchdog Wake-up Inline 1 X 0 Watchdog Wake-up Reset 1 X 1 Vector or Wake-up and Vector Wake-up Reset DS40001652D-page 50  2012-2016 Microchip Technology Inc. PIC16F527 8.14 Register Definitions — Interrupt Control REGISTER 8-2: INTCON0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 ADIF CWIF T0IF RAIF — — — GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADIF: A/D Converter Interrupt Flag bit 1 = A/D conversion complete (must be cleared by software) 0 = A/D conversion has not completed or has not been started bit 6 CWIF: Comparator 1 or 2 Interrupt Flag bit 1 = Comparator interrupt-on-change has occurred(1) 0 = No change in Comparator 1 or 2 output bit 5 T0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared by software) 0 = TMR0 register did not overflow bit 4 RAIF: Port A Interrupt-on-change Flag bit 1 = Wake-up or interrupt has occurred (cleared in software)(2) 0 = Wake-up or interrupt has not occurred bit 3-1 Unimplemented: Read as ‘0’ bit 0 GIE: Global Interrupt Enable bit 1 = Interrupt sets PC to address 0x004 (Vector to ISR) 0 = Interrupt causes wake-up and inline code execution x = Bit is unknown Note 1: This bit only functions when the C1WU or C2WU bits are cleared (see Register 10-1 and Register 10-2). 2: The RAWU bit of the OPTION register must be cleared to enable this function (see Register 4-2).  2012-2016 Microchip Technology Inc. DS40001652D-page 51 PIC16F527 REGISTER 8-3: INTCON1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 ADIE CWIE T0IE RAIE — — — WUR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 6 CWIE: Comparator 1 and 2 Interrupt Enable bit 1 = Enables the Comparator 1 and 2 Interrupt 0 = Disables the Comparator 1 and 2 Interrupt bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 RAIE: Port A on Pin Change Interrupt Enable bit 1 = Interrupt-on-change pin enabled 0 = Interrupt-on-change pin disabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 WUR: Wake-up Reset Enable bit 1 = Interrupt source causes device Reset on wake-up 0 = Interrupt source wakes up device from Sleep (Vector to ISR or inline execution) DS40001652D-page 52  2012-2016 Microchip Technology Inc. PIC16F527 8.15 Program Verification/Code Protection FIGURE 8-14: If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the code protection bit setting. 8.16 ID Locations Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify. External Connector Signals TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections PIC® Device +5V VDD 0V VSS VPP MCLR/VPP CLK ICSPCLK Data ICSPDAT VDD Use only the lower four bits of the ID locations and always program the upper eight bits as ‘0’s. 8.17 In-Circuit Serial Programming™ To Normal Connections The PIC16F527 microcontroller can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware, to be programmed. The devices are placed into a Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). ICSPCLK becomes the programming clock and ICSPDAT becomes the programming data. Both ICSPCLK and ICSPDAT are Schmitt Trigger inputs in this mode. After Reset, a 6-bit command is then supplied to the device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16F527 Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure 8-14.  2012-2016 Microchip Technology Inc. DS40001652D-page 53 PIC16F527 9.0 ANALOG-TO-DIGITAL (A/D) CONVERTER Note: The A/D Converter allows conversion of an analog signal into an 8-bit digital signal. 9.1 Clock Divisors The ADC has four clock source settings ADCS. There are three divisor values 16, 8 and 4. The fourth setting is INTOSC with a divisor of four. These settings will allow a proper conversion when using an external oscillator at speeds from 20 MHz to 350 kHz. Using an external oscillator at a frequency below 350 kHz requires the ADC oscillator setting to be INTOSC/4 (ADCS = 11) for valid ADC results. The ADC requires 13 TAD periods to complete a conversion. The divisor values do not affect the number of TAD periods required to perform a conversion. The divisor values determine the length of the TAD period. When the ADCS bits are changed while an ADC conversion is in process, the new ADC clock source will not be selected until the next conversion is started. This clock source selection will be lost when the device enters Sleep. Note: 9.1.1 The ADC clock is derived from the instruction clock. The ADCS divisors are then applied to create the ADC clock VOLTAGE REFERENCE There is no external voltage reference for the ADC. The ADC reference voltage will always be VDD. 9.1.2 ANALOG MODE SELECTION The ANS bits are used to configure pins for analog input. Upon any Reset, ANS defaults to FF. This configures the affected pins as analog inputs. Pins configured as analog inputs are not available for digital output. Users should not change the ANS bits while a conversion is in process. ANS bits are active regardless of the condition of ADON. 9.1.3 ADC CHANNEL SELECTION The CHS bits are used to select the analog channel to be sampled by the ADC. The CHS bits can be changed at any time without adversely effecting a conversion. To acquire an external analog signal, the CHS selection must match one of the pin(s) selected by the ANS bits. When the ADC is on (ADON = 1) and a channel is selected that is also being used by the comparator, then both the comparator and the ADC will see the analog voltage on the pin. DS40001652D-page 54 It is the user’s responsibility to ensure that the use of the ADC and op amp simultaneously on the same pin does not adversely affect the signal being monitored or adversely effect device operation. When the CHS bits are changed during an ADC conversion, the new channel will not be selected until the current conversion is completed. This allows the current conversion to complete with valid results. All channel selection information will be lost when the device enters Sleep. 9.1.4 THE GO/DONE BIT The GO/DONE bit is used to determine the status of a conversion, to start a conversion and to manually halt a conversion in process. Setting the GO/DONE bit starts a conversion. When the conversion is complete, the ADC module clears the GO/DONE bit and sets the ADIF bit in the INTCON0 register. A conversion can be terminated by manually clearing the GO/DONE bit while a conversion is in process. Manual termination of a conversion may result in a partially converted result in ADRES. The GO/DONE bit is cleared when the device enters Sleep, stopping the current conversion. The ADC does not have a dedicated oscillator, it runs off of the instruction clock. Therefore, no conversion can occur in Sleep. The GO/DONE bit cannot be set when ADON is clear. 9.1.5 A/D ACQUISITION REQUIREMENTS For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-1. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-1. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (256 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.  2012-2016 Microchip Technology Inc. PIC16F527 EQUATION 9-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10 k 5.0V VDD Tacq = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2 s + TC + [(Temperature - 25°C)(0.05 s/°C)] Solving for Tc: = CHOLD (RIC + RSS + RS) ln(1/512) Tc = -25pF (l k + 7 k + 10 k ) ln(0.00196) = 2.81 s Therefore: = 2 s + 2.81 s + [(50°C-25°C)(0.0 5s/°C)] Tacq = 6.06 s Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion. 2: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. FIGURE 9-1: ANALOG INPUT MODULE VDD Rs VA ANx CPIN 5 pF VT = 0.6V VT = 0.6V RIC  1k Sampling Switch SS Rss I LEAKAGE ± 500 nA CHOLD = 25 pF VSS/VREF- Legend: CPIN VT ILEAKAGE RIC SS CHOLD = Input Capacitance = Threshold Voltage = Leakage current at the pin due to various junctions = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance  2012-2016 Microchip Technology Inc. 6V 5V VDD 4V 3V 2V RSS 5 6 7 8 9 10 11 Sampling Switch (k) DS40001652D-page 55 PIC16F527 9.1.6 ANALOG CONVERSION RESULT REGISTER right shifts of the ‘leading one’ have taken place, the conversion is complete; the ‘leading one’ has been shifted out and the GO/DONE bit is cleared. The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0). A ‘leading one’ is then right shifted into the ADRES to serve as an internal conversion complete bit. As each bit weight, starting with the MSB, is converted, the leading one is shifted right and the converted bit is stuffed into ADRES. After a total of nine REGISTER 9-1: If the GO/DONE bit is cleared in software during a conversion, the conversion stops and the ADIF bit will not be set to a ‘1’. The data in ADRES is the partial conversion result. This data is valid for the bit weights that have been converted. The position of the ‘leading one’ determines the number of bits that have been converted. The bits that were not converted before the GO/DONE was cleared are unrecoverable. ADCON0: A/D CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADCS: ADC Conversion Clock Select bits 00 = FOSC/16 01 = FOSC/8 10 = FOSC/4 11 = INTOSC/4 bit 5-2 CHS: ADC Channel Select bits(1) 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1xxx = Reserved 1111 = 0.6V Fixed Input Reference (VFIR) bit 1 GO/DONE: ADC Conversion Status bit(2) 1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC is done converting. 0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process terminates the current conversion. bit 0 ADON: ADC Enable bit 1 = ADC module is operating 0 = ADC module is shut-off and consumes no power Note 1: 2: CHS bits default to 1 after any Reset. If the ADON bit is clear, the GO/DONE bit cannot be set. DS40001652D-page 56  2012-2016 Microchip Technology Inc. PIC16F527 REGISTER 9-2: ADRES: A/D CONVERSION RESULTS REGISTER R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES: ADC Result Register bits EXAMPLE 9-1: PERFORMING AN ANALOG-TO-DIGITAL CONVERSION EXAMPLE 9-2: ;Sample code operates out of BANK0 loop0 x = Bit is unknown MOVLW 0xF1 ;configure A/D MOVWF ADCON0 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop0 MOVF ADRES, W ;read result MOVWF result0 ;save result loop1 ;setup for read of ;channel 1 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop1 MOVF ADRES, W ;read result MOVWF result1 ;save result loop2 BSF ADCON0, 3 ;setup for read of BCF ADCON0, 2 ;channel 2 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop2 MOVF ADRES, W ;read result MOVWF result2 ;save result MOVLW 0xF1 MOVWF ADCON0 BSF ADCON0, 1 BSF ADCON0, 2 ;configure A/D loop0 ;start conversion ;setup for read of ;channel 1 BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop0 MOVF ADRES, W ;read result MOVWF result0 ;save result loop1 BSF ADCON0, 1 ;start conversion BSF ADCON0, 3 ;setup for read of BCF ADCON0, 2 ;channel 2 BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop1 MOVF ADRES, W ;read result MOVWF result1 ;save result BSF ADCON0, 2  2012-2016 Microchip Technology Inc. CHANNEL SELECTION CHANGE DURING CONVERSION loop2 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop2 MOVF ADRES, W ;read result MOVWF result2 ;save result CLRF ADCON0 ;optional: returns ;pins to Digital mode and turns off ;the ADC module DS40001652D-page 57 PIC16F527 9.1.7 SLEEP This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bits will be cleared. This will stop any conversion in process and power-down the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may contain a partial conversion. At least one bit must have been converted prior to Sleep to have partial conversion data in ADRES. The ADCS and CHS bits are reset to their default condition; ANS = 1s and CHS = 1s. For accurate conversions, TAD must meet the following: • 500 ns < TAD < 50 s • TAD = 1/(FOSC/divisor) Shaded areas indicate TAD out of range for accurate conversions. If analog input is desired at these frequencies, use INTOSC/8 for the ADC clock source. TABLE 9-1: Source TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS ADCS Divisor 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz 500 kHz 350 kHz 200 kHz 100 kHz 32 kHz INTOSC 11 4 — — .5 s 1 s — — — — — — FOSC 10 4 .2 s .25 s .5 s 1 s 4 s 8 s 11 s 20 s 40 s 125 s FOSC 01 8 .4 s .5 s 1 s 2 s 8 s 16 s 23 s 40 s 80 s 250 s FOSC 00 16 .8 s 1 s 2 s 4 s 16 s 32 s 46 s 80 s 160 s 500 s TABLE 9-2: EFFECTS OF SLEEP ON ADCON0 ANS ADCS1 ADCS0 CHS GO/DONE ADON Entering Sleep Unchanged 1 1 1 0 0 Wake or Reset 1 1 1 1 0 0 DS40001652D-page 58  2012-2016 Microchip Technology Inc. PIC16F527 10.0 COMPARATOR(S) This device contains two comparators comparator voltage reference. FIGURE 10-1: and a COMPARATORS BLOCK DIAGRAM C1OUT C1PREF C1IN+ 1 C1OUTEN + C1IN- 0 C1OUT (Register) 1 Fixed Input Reference (VFIR) 0 C1NREF C1POL C1ON 0 T0CKI 1 T0CKI Pin C1T0CS Q D S C2OUT C2PREF1 C2IN+ READ CM1CON0 C2OUTEN 1 + 0 1 C2OUT (Register) 0 C2PREF2 C2IN- C2POL C2ON 1 0 CVREF C2NREF Q D C2WU S CWIF READ CM2CON0 C1WU  2012-2016 Microchip Technology Inc. DS40001652D-page 59 PIC16F527 10.1 Comparator Operation 10.4 A single comparator is shown in Figure 10-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of the comparator in Figure 10-2 represent the uncertainty due to input offsets and response time. See Table 15-2 for Common Mode Voltage. FIGURE 10-2: VIN+ Note: 10.5 Result VIN- The comparator output is read through the CxOUT bit in the CM1CON0 or CM2CON0 register. This bit is read-only. The comparator output may also be used externally, see Section 10.1 “Comparator Operation”. SINGLE COMPARATOR + – Comparator Output Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. Comparator Wake-up Flag The Comparator Wake-up Flag bit, CWIF, in the INTCON0 register, is set whenever all of the following conditions are met: • C1WU = 0 (CM1CON0) or C2WU = 0 (CM2CON0) • CM1CON0 or CM2CON0 has been read to latch the last known state of the C1OUT and C2OUT bit (MOVF CM1CON0, W) • The output of a comparator has changed state VINVIN+ The wake-up flag may be cleared in software or by another device Reset. Result 10.6 10.2 Comparator Reference An internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (see Figure 10-2). Please see Section 11.0 “Comparator Voltage Reference Module” for internal reference specifications. 10.3 Comparator Response Time Response time is the minimum time after selecting a new reference voltage or input source before the comparator output is to have a valid level. If the comparator inputs are changed, a delay must be used to allow the comparator to settle to its new state. Please see Table 15-7 for comparator response time specifications. DS40001652D-page 60 Comparator Operation During Sleep When the comparator is enabled it is active. To minimize power consumption while in Sleep mode, turn off the comparator before entering Sleep. 10.7 Effects of Reset A Power-on Reset (POR) forces the CMxCON0 register to its Reset state. This forces the Comparator input pins to analog Reset mode. Device current is minimized when analog inputs are present at Reset time. 10.8 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 10-3. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 10-3: ANALOG INPUT MODE VDD VT = 0.6V RS < 10 K RIC AIN VA CPIN 5 pF VT = 0.6V ILEAKAGE ±500 nA VSS Legend: CPIN VT ILEAKAGE RIC RS VA  2012-2016 Microchip Technology Inc. = = = = = = Input Capacitance Threshold Voltage Leakage Current at the Pin Interconnect Resistance Source Impedance Analog Voltage DS40001652D-page 61 PIC16F527 10.9 Register Definitions — Comparator Control REGISTER 10-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VIN- bit 6 C1OUTEN: Comparator Output Enable bit(1) 1 = Output of comparator is NOT placed on the C1OUT pin 0 = Output of comparator is placed in the C1OUT pin bit 5 C1POL: Comparator Output Polarity bit 1 = Output of comparator is not inverted 0 = Output of comparator is inverted bit 4 C1T0CS: Comparator TMR0 Clock Source bit 1 = TMR0 clock source selected by T0CS control bit 0 = Comparator output used as TMR0 clock source bit 3 C1ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 C1NREF: Comparator Negative Reference Select bit(2) 1 = C1IN- pin 0 = 0.6V Fixed Input Reference (VFIR) bit 1 C1PREF: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C1IN- pin bit 0 C1WU: Comparator Wake-up On Change Enable bit(3) 1 = Wake-up On Comparator Change is disabled 0 = Wake-up On Comparator Change is enabled Note 1: x = Bit is unknown Overrides TRIS control of the port. 2: When this bit selects an I/O pin and the comparator is turned on, this feature will override the TRIS and ANSEL settings to make the respective pin an analog input. The value in the ANSEL register, however, is not overwritten. When the comparator is turned off, the respective pin will revert back to the original TRIS and ANSEL settings. 3: The C1WU bit must be cleared to enable the CWIF function. See the INTCON0 register (see Register 82) for more information. DS40001652D-page 62  2012-2016 Microchip Technology Inc. PIC16F527 REGISTER 10-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VIN- bit 6 C2OUTEN: Comparator Output Enable bit(1) 1 = Output of comparator is NOT placed on the C2OUT pin 0 = Output of comparator is placed in the C2OUT pin bit 5 C2POL: Comparator Output Polarity bit 1 = Output of comparator not inverted 0 = Output of comparator inverted bit 4 C2PREF2: Comparator Positive Reference Select bit 1 = C1IN+ pin 0 = C2IN- pin bit 3 C2ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 C2NREF: Comparator Negative Reference Select bit(2) 1 = C2IN- pin 0 = CVREF bit 1 C2PREF1: Comparator Positive Reference Select bit(2) 1 = C2IN+ pin 0 = C2PREF2 controls analog input selection bit 0 C2WU: Comparator Wake-up on Change Enable bit(3) 1 = Wake-up on Comparator change is disabled 0 = Wake-up on Comparator change is enabled. x = Bit is unknown Note 1: Overrides TRIS control of the port. 2: When this bit selects an I/O pin and the comparator is turned on, this feature will override the TRIS and ANSEL settings to make the respective pin an analog input. The value in the ANSEL register, however, is not overwritten. When the comparator is turned off, the respective pin will revert back to the original TRIS and ANSEL settings. 3: The C2WU bit must be cleared to enable the CWIF function. See the INTCON0 register (see Register 82) for more information. TABLE 10-1: Name STATUS CM1CON0 CM2CON0 TRIS REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 Register on page DC C 16 C1PREF C1WU 62 C2WU 63 Bit 7 Bit 6 Bit 1 — — PA0 TO PD Z C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 I/O Control Register (TRISA, TRISB, TRISC) — Legend: x = Unknown, u = Unchanged, – = Unimplemented, read as ‘0’, q = Depends on condition.  2012-2016 Microchip Technology Inc. DS40001652D-page 63 PIC16F527 11.0 COMPARATOR VOLTAGE REFERENCE MODULE 11.2 The Comparator Voltage Reference module also allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON register (see Register 11-1) controls the voltage reference module shown in Figure 11-1. 11.1 Configuring The Voltage Reference The voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range. Equation 11-1 determines the output voltages: EQUATION 11-1: Voltage Reference Accuracy The full range of VSS to VDD cannot be realized due to construction of the module. The transistors on the top and bottom of the resistor ladder network (see Figure 11-1) keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing the VREN bit of the VRCON register. When disabled, the reference voltage is VSS when VR is ‘0000’ and the VRR bit of the VRCON register is set. This allows the comparator to detect a zero crossing and not consume the CVREF module current. The voltage reference is VDD derived and, therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage reference can be found in Section 15.0 “Electrical Characteristics”. VRR = 1 (low range): CVREF = (VR/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR x VDD/32) REGISTER 11-1: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 VREN: CVREF Enable bit 1 = CVREF is powered on 0 = CVREF is powered down, no current is drawn bit 6 VROE: CVREF Output Enable bit(1) 1 = CVREF output is enabled 0 = CVREF output is disabled bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR CVREF Value Selection bits When VRR = 1: CVREF= (VR/24)*VDD When VRR = 0: CVREF= VDD/4+(VR/32)*VDD x = Bit is unknown Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the CVREF pin. DS40001652D-page 64  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 11-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator 2 Input VR CVREF VREN VR = 0000 VRR VROE TABLE 11-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page VREN VROE VRR — VR3 VR2 VR1 VR0 64 CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 62 CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 63 Name VRCON Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, q = value depends on condition.  2012-2016 Microchip Technology Inc. DS40001652D-page 65 PIC16F527 12.0 OPERATIONAL AMPLIFIER (OPA) MODULE The OPA module has the following features: • Two independent Operational Amplifiers • External connections to all ports • 3 MHz Gain Bandwidth Product (GBWP) 12.1 OPACON Register The OPA module is enabled by setting the OPAxON bit of the OPACON Register. Note: When OPA1 or OPA2 is enabled, the OP1 pin or OP2 pin, respectively, is driven by the op amp output, not by the port driver. Refer to Table 15-5 for the electrical specifications for the op amp output drive capability. FIGURE 12-1: OPA MODULE BLOCK DIAGRAM OPACON OP1+ OPA1 OP1OP1 OPACON OP2+ OPA2 OP2OP2 DS40001652D-page 66  2012-2016 Microchip Technology Inc. PIC16F527 REGISTER 12-1: OPACON: OP AMP CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OPA2ON OPA1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 OPA2ON: Op Amp Enable bit 1 = Op amp 2 is enabled 0 = Op amp 2 is disabled bit 0 OPA1ON: Op Amp Enable bit 1 = Op amp 1 is enabled 0 = Op amp 1 is disabled 12.2 Effects of a Reset Leakage current is a measure of the small source or sink currents on the OP+ and OP- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OP+ and OP- inputs should be kept as small as possible and equal. A device Reset forces all registers to their Reset state. This disables both op amps. 12.3 OPA Module Performance Input offset voltage is a measure of the voltage difference between the OP+ and OP- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the common mode voltage. Common AC and DC performance specifications for the OPA module: • • • • • Common Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain Gain Bandwidth Product (GBWP) Open loop gain is the ratio of the output voltage to the differential input voltage, (OP+) - (OP-). The gain is greatest at DC and falls off with frequency. Common mode voltage range is the specified voltage range for the OP+ and OP- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between 0 and VDD-1.5V. Behavior for common mode voltages greater than VDD-1.5V, or below 0V, are beyond the normal operating range. TABLE 12-1: x = Bit is unknown Gain Bandwidth Product or GBWP is the frequency at which the open loop gain falls off to 0 dB. 12.4 Effects of Sleep When enabled, the op amps continue to operate and consume current while the processor is in Sleep mode. REGISTERS ASSOCIATED WITH THE OPA MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 29 — — — — — — OPACON TRIS I/O Control Registers (TRISA, TRISB, TRISC) OPA2ON OPA1ON 67 — Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for the OPA module.  2012-2016 Microchip Technology Inc. DS40001652D-page 67 PIC16F527 13.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field designator which selects the number of the bit affected by the operation, while ‘f’ represents the number of the file in which the bit is located. For literal and control operations, ‘k’ represents an 8 or 9-bit constant or literal value. TABLE 13-1: Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0 (store result in W) d = 1 (store result in file register ‘f’) Default is d = 1 label Label name TOS Top-of-Stack PC WDT TO Power-down bit [ ] Options ( ) Contents italics FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 11 6 OPCODE 5 d 4 0 f (FILE #) d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 8 7 5 4 b (BIT #) 0 f (FILE #) b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 8 7 OPCODE 0 k (literal) k = 8-bit immediate value Literal and control operations – GOTO instruction 11 9 8 OPCODE 0 k (literal) k = 9-bit immediate value Watchdog Timer counter Destination, either the W register or the specified register file location Œ where ‘h’ signifies a hexadecimal digit. Time-out bit PD < > 0xhhh Program Counter dest Æ Figure 13-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: OPCODE FIELD DESCRIPTIONS Field f All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Assigned to Register bit field In the set of User defined term (font is courier) DS40001652D-page 68  2012-2016 Microchip Technology Inc. PIC16F527 TABLE 13-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF 12-Bit Opcode Description Cycles MSb LSb Status Notes Affected f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d 0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decrement f 1 Z 2, 4 0010 11df ffff Decrement f, Skip if 0 1(2) None 2, 4 1 0010 10df ffff Increment f Z 2, 4 1(2) 0011 11df ffff Increment f, Skip if 0 None 2, 4 1 0001 00df ffff Inclusive OR W with f Z 2, 4 1 0010 00df ffff Move f Z 2, 4 1 0000 001f ffff Move W to f None 1, 4 1 0000 0000 0000 No Operation None 1 0011 01df ffff Rotate left f through Carry C 2, 4 1 0011 00df ffff Rotate right f through Carry C 2, 4 1 0000 10df ffff C, DC, Z 1, 2, 4 Subtract W from f 1 0011 10df ffff Swap f None 2, 4 1 0001 10df ffff Exclusive OR W with f Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS 0100 bbbf ffff None 2, 4 1 Bit Clear f BCF f, b 0101 bbbf ffff None 2, 4 1 Bit Set f BSF f, b 0110 bbbf ffff None Bit Test f, Skip if Clear 1(2) BTFSC f, b 1(2) 0111 bbbf ffff None f, b Bit Test f, Skip if Set BTFSS LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z 1 CALL k Call Subroutine 2 1001 kkkk kkkk None CLRWDT — Clear Watchdog Timer 1 0000 0000 0100 TO, PD None GOTO k Unconditional branch 2 101k kkkk kkkk Z IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk None MOVLB k Move Literal to BSR Register 1 0000 0001 0kkk None MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION — Load OPTION register 1 0000 0000 0010 None RETFIE — Return from Interrupt 2 0000 0001 1111 3 None RETLW k Return, place literal in W 2 1000 kkkk kkkk None RETURN — Return, maintain W 2 0000 0001 1110 SLEEP — Go into Standby mode 1 0000 0000 0011 TO, PD None TRIS f Load TRIS register 1 0000 0000 0fff Z XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for GOTO. See Section 4.6 “Program Counter”. 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of PORTA. A ‘1’ forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).  2012-2016 Microchip Technology Inc. DS40001652D-page 69 PIC16F527 ADDWF Add W and f BCF f,d Bit Clear f Syntax: [ label ] ADDWF Syntax: [ label ] BCF Operands: 0  f  31 d 01 Operands: 0  f  31 0b7 Operation: (W) + (f)  (dest) Operation: 0  (f) Status Affected: C, DC, Z Status Affected: None Description: Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f Syntax: [ label ] BSF Operands: 0  f  31 0b7 Status Affected: Z Operation: 1  (f) Description: Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. BTFSC Bit Test f, Skip if Clear Add the contents of the W register and register ‘f’. If ‘d’ is’0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0  k  255 Operation: (W).AND. (k)  (W) The contents of the W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0  f  31 d [0,1] Operation: f,d Description: The contents of the W register are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001652D-page 70 f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  31 0b7 Operation: skip if (f) = 0 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped. If bit ‘b’ is ‘0’, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2-cycle instruction. (W) .AND. (f)  (dest) Status Affected: Z f,b  2012-2016 Microchip Technology Inc. PIC16F527 BTFSS Bit Test f, Skip if Set CLRW Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW 0  f  31 0b VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA Max. output current sunk by any I/O pin...............................................................................................................25 mA Max. output current sourced by any I/O pin .........................................................................................................25 mA Max. output current sourced by I/O port ..............................................................................................................75 mA Max. output current sunk by I/O port ...................................................................................................................75 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS40001652D-page 80  2012-2016 Microchip Technology Inc. PIC16F527 PIC16F527 VOLTAGE-FREQUENCY GRAPH, -40C  TA  +125C FIGURE 15-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 8 20 10 25 Frequency (MHz) FIGURE 15-2: MAXIMUM OSCILLATOR FREQUENCY TABLE Oscillator Mode LP XT XTRC INTOSC EC HS 0 200 kHz 4 MHz 8 MHz 20 MHz Frequency  2012-2016 Microchip Technology Inc. DS40001652D-page 81 PIC16F527 15.1 DC Characteristics: PIC16F527 (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) DC Characteristics Param. No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 15-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — VSS — V See Section 8.5 “Power-on Reset (POR)” for details D004 SVDD VDD Rise Rate to ensure Power-on Reset 0.05* — — V/ms See Section 8.5 “Power-on Reset (POR)” for details D005 IDDP Supply Current During Prog/Erase — 1.0* — mA VDD = 5.0V D010 IDD Supply Current(3,4,6) — — 175 490 300 750 A A FOSC = 4 MHz, VDD = 2.0V FOSC = 4 MHz, VDD = 5.0V — — 350 850 500 1300 A A FOSC = 8 MHz, VDD = 2.0V FOSC = 8 MHz, VDD = 5.0V — 1800 2500 A FOSC = 20 MHz, VDD = 5.0V — — 13 30 22 55 A A FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 5.0V D020 IPD Power-down Current(5) — — 0.05 0.35 1.2 3.0 A A VDD = 2.0V VDD = 5.0V D021 IBOR BOR Current(5) — — 3.5 4.0 7.0 9.0 A A VDD = 3.0V VDD = 5.0V D022 IWDT WDT Current(5) — — 0.5 8.0 3.0 18.0 A A VDD = 2.0V VDD = 5.0V D023 ICMP Comparator Current(5) — — 15 60 26 85 A A VDD = 2.0V (per comparator) VDD = 5.0V (per comparator) D024 ICVREF CVREF Current(5) — — 30 75 70 125 A A VDD = 2.0V (high range) VDD = 5.0V (high range) D025 IVFIR Internal 0.6V Fixed Voltage Reference Current(5) — 100 130 A — 175 220 A VDD = 2.0V (reference and 1 comparator enabled) VDD = 5.0V (reference and 1 comparator enabled) D026 IAD2 A/D Current — — 0.5 0.8 2.0 3.2 A A 2.0V, No conversion in progress 5.0V, No conversion in progress D027 IOPA Op Amp Current(5) — — 330 360 415 465 A A VDD = 2.0V VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: Does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k. DS40001652D-page 82  2012-2016 Microchip Technology Inc. PIC16F527 15.2 DC Characteristics: PIC16F527 (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +125C (extended) DC Characteristics Param. No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions D001 VDD Supply Voltage 2.0 5.5 V See Figure 15-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure Power-on Reset — VSS — V See Section 8.5 “Power-on Reset (POR)” for details. D004 SVDD VDD Rise Rate to ensure Power-on Reset 0.05* — — V/ms See Section 8.5 “Power-on Reset (POR)” for details. D005 IDDP Supply Current During Prog/Erase — 1.0* — mA VDD = 5.0V D010 IDD Supply Current(3,4,6) — — 175 490 300 750 A A FOSC = 4 MHz, VDD = 2.0V FOSC = 4 MHz, VDD = 5.0V — — 350 850 500 1300 A A FOSC = 8 MHz, VDD = 2.0V FOSC = 8 MHz, VDD = 5.0V — 1800 2500 A FOSC = 20 MHz, VDD = 5.0V — — 13 30 29 115 A A FOSC = 32 kHz, VDD = 2.0V FOSC = 32 kHz, VDD = 5.0V D020 IPD Power-down Current(5) — — 0.1 0.35 9.0 15.0 A A VDD = 2.0V VDD = 5.0V D021 IBOR BOR Current(5) — — 3.5 4.0 10 12 A A VDD = 3.0V VDD = 5.0V D022 IWDT WDT Current(5) — — 1.0 8.0 18 22 A A VDD = 2.0V VDD = 5.0V D023 ICMP Comparator Current(5) — — 15 60 30 92 A A VDD = 2.0V (per comparator) VDD = 5.0V (per comparator) D024 ICVREF CVREF Current(5) — — 30 75 75 135 A A VDD = 2.0V (high range) VDD = 5.0V (high range) D025 IVFIR Internal 0.6V Fixed Voltage Reference Current(5) — 100 135 A — 175 235 A VDD = 2.0V (reference and 1 comparator enabled) VDD = 5.0V (reference and 1 comparator enabled) D026 IAD2 A/D Current — — 0.5 0.8 10.0 16.0 A A 2.0V, No conversion in progress 5.0V, No conversion in progress D027 IOPA Op Amp Current(5) — — 330 360 450 505 A A VDD = 2.0V VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: Does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k.  2012-2016 Microchip Technology Inc. DS40001652D-page 83 PIC16F527 TABLE 15-1: DC CHARACTERISTICS: PIC16F527 (INDUSTRIAL, EXTENDED) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C  TA  +85°C (industrial) -40°C  TA  +125°C (extended) DC CHARACTERISTICS Param. No. Sym. VIL Characteristic Min. Typ.† Max. Units Conditions Input Low Voltage I/O ports D030 with TTL buffer D030A Vss — 0.8V V For all 4.5  VDD 5.5V Vss — 0.15VDD V Otherwise D031 with Schmitt Trigger buffer Vss — 0.15VDD V D032 MCLR, T0CKI Vss — 0.15VDD V D033 OSC1 (EXTRC mode), (EC mode) Vss — 0.15VDD V D033 OSC1 (HS mode) Vss — 0.3VDD V OSC1 (XT and LP modes) Vss — 0.3 V 2.0 — VDD V 4.5  VDD 5.5V 0.25VDD + 0.8VDD — VDD V Otherwise with Schmitt Trigger buffer 0.85VDD — VDD V For entire VDD range D042 MCLR, T0CKI 0.85VDD — VDD V D042A OSC1 (EXTRC mode), (EC mode) 0.85VDD — VDD V D042A OSC1 (HS mode) 0.7VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V PORTA and MCLR weak pull-up current(4) 50 250 400 A VDD = 5V, VPIN = VSS D033 VIH Input High Voltage I/O ports D040 with TTL buffer D040A D041 D070 IPUR IIL (Note 1) — (Note 1) Input Leakage Current(2,3) D060 I/O ports — — ±1 A Vss VPIN VDD, Pin at high-impedance D061 MCLR — ±0.7 ±5 A Vss VPIN VDD D063 OSC1 — — ±5 A Vss VPIN VDD, XT, HS and LP osc configuration — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C VOL D080 Output Low Voltage I/O ports/CLKOUT D080A D083 OSC2 D083A † Note 1: 2: 3: 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F527 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. This spec applies to all weak pull-up devices, including the weak pull-up found on MCLR. DS40001652D-page 84  2012-2016 Microchip Technology Inc. PIC16F527 TABLE 15-1: DC CHARACTERISTICS: PIC16F527 (INDUSTRIAL, EXTENDED) (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C  TA  +85°C (industrial) -40°C  TA  +125°C (extended) DC CHARACTERISTICS Param. No. Sym. VOH D090 Characteristic D090A OSC2 D092A † Note 1: 2: 3: 4: Typ.† Max. Units Conditions VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C VDD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C Output High Voltage I/O ports/CLKOUT D092 Min. Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F527 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. This spec applies to all weak pull-up devices, including the weak pull-up found on MCLR.  2012-2016 Microchip Technology Inc. DS40001652D-page 85 PIC16F527 TABLE 15-1: DC CHARACTERISTICS: PIC16F527 (INDUSTRIAL, EXTENDED) (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C  TA  +85°C (industrial) -40°C  TA  +125°C (extended) DC CHARACTERISTICS Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions In XT, HS and LP modes when external clock is used to drive OSC1. Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF D101 CIO — — 50 pF All I/O pins and OSC2 Flash Data Memory D120 ED Byte endurance 100K 1M — E/W -40C  TA  +85C D120A ED Byte endurance 10K 100K — E/W +85C  TA  +125C D121 VDRW VDD for read/write VMIN — 5.5 V † Note 1: 2: 3: 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16F527 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. This spec applies to all weak pull-up devices, including the weak pull-up found on MCLR. DS40001652D-page 86  2012-2016 Microchip Technology Inc. PIC16F527 TABLE 15-2: COMPARATOR SPECIFICATIONS Comparator Specifications Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C to 125°C Characteristics Sym. Min. Typ. Max. Units Input offset voltage VOS — ± 5.0 ±10.0 mV Input common mode voltage* VCM 0 — VDD – 1.5 V — db CMRR* Response Time (1)* Comparator Mode Change to Output Valid* CMRR 55 — TRT — 150 — ns TMC2COV — — 10 s Comments * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from VSS to VDD – 1.5V. TABLE 15-3: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Sym. CVRES * Note 1: 2: Characteristics Min. Typ. Max. Units Comments Resolution — — VDD/24* VDD/32 — — LSb LSb Low Range (VRR = 1) High Range (VRR = 0) Absolute Accuracy(2) — — — — ±1/2* ±1/2* LSb LSb Low Range (VRR = 1) High Range (VRR = 0) Unit Resistor Value (R) — — 2K* —  Settling Time(1) — — 10* s These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR transitions from 0000 to 1111. Do not use reference externally when VDD < 2.7V. Under this condition, reference should only be used with comparator Voltage Common mode observed. TABLE 15-4: FIXED INPUT REFERENCE SPECIFICATION Input Reference Specifications Characteristics Absolute Accuracy  2012-2016 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C to 125°C Sym. Min. Typ. Max. Units VFIR 0.5 0.60 0.7 V Comments DS40001652D-page 87 PIC16F527 TABLE 15-5: A/D CONVERTER CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature: 25°C Param. Sym. No. A01 NR Characteristic Min. Typ.† Max. Units Resolution — — 8 bit Integral Error — — 1.5 LSb VDD = 5.0V — — EDNL 1.7 LSb No missing codes VDD = 5.0V 2.0* — 5.5* V A03 EINL A04 EDNL Differential Error A05 EFS A06 EOFF Offset Error A07 EGN Full Scale Range Gain Error Conditions — — 1.5 LSb VDD = 5.0V -0.7 — 2.2 LSb VDD = 5.0V A10 — Monotonicity — guaranteed(1) — — A25* VAIN Analog Input Voltage VSS — VDD V A30* ZAIN Recommended Impedance of Analog Voltage Source — — 10 K VSS  VAIN  VDD * † These parameters are characterized but not tested. Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. DS40001652D-page 88  2012-2016 Microchip Technology Inc. PIC16F527 15.3 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc Oscillator cy Cycle time os OSC1 drt Device Reset Timer t0 T0CKI io I/O port wdt Watchdog Timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (high-impedance) V Valid L Low Z High-impedance FIGURE 15-3: LOAD CONDITIONS Legend: Pin CL CL = 50 pF for all pins except OSC2 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2  2012-2016 Microchip Technology Inc. DS40001652D-page 89 PIC16F527 TABLE 15-6: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial), -40C  TA  +125C (extended) Operating voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)”. AC Characteristics Param. No. Sym. 1A FOSC Characteristic Min. Typ.(1) Max. External CLKIN Frequency(2) DC — 4 MHz XT Oscillator Oscillator Frequency 1 TOSC External CLKIN (2) Period(2) Oscillator Period(2) Units Conditions DC — 20 MHz HS/EC Oscillator DC — 200 kHz LP Oscillator DC — 4 MHz EXTRC Oscillator 0.1 — 4 MHz XT Oscillator 4 — 20 MHz HS/EC Oscillator DC — 200 kHz LP Oscillator 250 — — ns XT Oscillator 50 — — ns HS/EC Oscillator 5 — — s LP Oscillator 250 — — ns EXTRC Oscillator 250 — 10,000 ns XT Oscillator 50 — 250 ns HS/EC Oscillator LP Oscillator 5 — — s 2 TCY Instruction Cycle Time 200 4/FOSC DC ns 3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT Oscillator 2* — — s LP Oscillator 10* — — ns HS/EC Oscillator TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT Oscillator — — 50* ns LP Oscillator — — 15* ns HS/EC Oscillator 4 * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS40001652D-page 90  2012-2016 Microchip Technology Inc. PIC16F527 TABLE 15-7: CALIBRATED INTERNAL RC FREQUENCIES Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial), -40C  TA  +125C (extended) Operating voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)”. AC Characteristics Param. No. Sym. F10 FOSC Characteristic Internal Calibrated INTOSC Frequency(1) Freq. Min. Tolerance Typ.† Max. Units Conditions 1% 7.92 8.00 8.08 MHz 3.5V, 25C 2% 7.84 8.00 8.16 MHz 2.5V VDD  5.5V 0C  TA  +85C 5% 7.60 8.00 8.40 MHz 2.0V VDD  5.5V -40C  TA  +85C (Ind.) -40C  TA  +125C (Ext.) * † These parameters are characterized but not tested. Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.  2012-2016 Microchip Technology Inc. DS40001652D-page 91 PIC16F527 FIGURE 15-5: I/O TIMING Q1 Q4 Q2 Q3 OSC1 I/O Pin (input) 17 I/O Pin (output) 19 18 New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 15-8: TIMING REQUIREMENTS AC Characteristics Param. No. Sym. Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) -40C  TA  +125C (extended) Operating voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)”. Characteristic Min. Typ.(1) Max. Units 17 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid(2,3) — — 100* ns 18 TOSH2IOI 50* — — ns 19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 20* — — ns 20 TIOR Port Output Rise Time(3) — 10 50** ns 21 TIOF Port Output Fall Time(3) — 10 50** ns OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time)(2) * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 15-3 for loading conditions. DS40001652D-page 92  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 15-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING VDD MCLR 30 Internal POR 32 32 32 DRT Time-out(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: 2: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. Runs in MCLR or WDT Reset only in XT, LP and HS modes. FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) TBOR Reset (due to BOR)  2012-2016 Microchip Technology Inc. TDRT DS40001652D-page 93 PIC16F527 TABLE 15-9: BOR, POR, WATCHDOG TIMER AND DEVICE RESET TIMER Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) -40C  TA  +125C (extended) Operating voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)”. AC Characteristics Param. No. Sym. Characteristic Min. 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0V 31 TWDT Watchdog Timer Time-out Period (no prescaler) 9* 9* 18* 18 30* 40* ms ms VDD = 5.0V (Industrial) VDD = 5.0V (Extended) 32 TDRT Device Reset Timer Period 9* 9* 18* 18 30* 40* ms ms VDD = 5.0V (Industrial) VDD = 5.0V (Extended) 34 TIOZ I/O High-impedance from MCLR low — — 2000* ns 35 VBOR Brown-out Reset Voltage 1.95 — 2.25 V 36* VHYST Brown-out Reset Hysteresis — 50 — mV 37* TBOR Brown-out Reset Minimum Detection Period 100 — — s Typ.(1) Max. Units Conditions (Note 2) VDD  VBOR * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. TABLE 15-10: DRT (DEVICE RESET TIMER PERIOD) Oscillator Configuration IntRC, ExtRC, and EC POR Reset Subsequent Resets 10 s (typical) + 18 ms (DRTEN = 1) 10 s (typical) + 18 ms (DRTEN = 1) 18 ms (typical) 18 ms (typical) XT, HS and LP TABLE 15-11: PULL-UP RESISTOR RANGES VDD (Volts) Temperature (C) Min. Typ. Max. Units -40 73K 105K 186K  25 73K 113K 187K  85 82K 123K 190K  125 86K 132k 190K  -40 15K 21K 33K  25 15K 22K 34K  85 19K 26k 35K  125 23K 29K 35K  -40 63K 81K 96K  25 77K 93K 116K  85 82K 96k 116K  125 86K 100K 119K  -40 16K 20k 22K  25 16K 21K 23K  85 24K 25k 28K  125 26K 27K 29K  RB0-RB7 2.0 5.5 MCLR 2.0 5.5 DS40001652D-page 94  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 15-8: TIMER0 CLOCK TIMINGS T0CKI 40 41 42 TABLE 15-12: TIMER0 CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) -40C  TA  +125C (extended) AC Characteristics Operating voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)”. Param. No. Sym. 40 Tt0H Characteristic T0CKI High Pulse Width No Prescaler With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler 42 Tt0P T0CKI Period With Prescaler Min. Typ.(1) Max. Units 0.5 TCY + 20* — — ns 10* — — ns 0.5 TCY + 20* — — ns 10* — — ns 20 or TCY + 40* N — — ns Conditions Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2012-2016 Microchip Technology Inc. DS40001652D-page 95 PIC16F527 15.4 Operational Amplifiers TABLE 15-13: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 5.0V Operating temperature: 25°C OPA DC CHARACTERISTICS Param. No. Sym. Characteristics Min. Typ. Max. Units Comments VOS Input Offset Voltage — 5 13 mV OPA02* OPA03* IB IOS Input current and impedance Input bias current Input offset bias current — — 2* 1* — — nA pA OPA04* OPA05* VCM CMR Common Mode Common mode input range Common mode rejection VSS 55 — 65 VDD – 1.4 — V dB — 70 — dB Standard load VSS + 50 — VDD – 50 mV To VDD/2 (10 k connected to VDD, 10 k + 20 pF to Vss) OPA01 OPA06A* AOL Open Loop Gain DC Open loop gain OPA07* VOUT Output Output voltage swing OPA08* ISC Output short circuit current — 25 28 mA PSR Power Supply Power supply rejection — 70 — dB OPA10* * These parameters are characterized but not tested. TABLE 15-14: AC CHARACTERISTICS: OPERATIONAL AMPLIFIER (OPA) AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating Temperature: 25°C VDD = 5.0V Param. No. Symbol Min. Typ. Max. Units GBWP — 3 — MHz VDD = 5V OPA13* Turn on Time TON — — 10 µs VDD = 5V OPA14* Phase Margin M — 55 — OPA15* Slew Rate SR 2 — — Parameters OPA12* Gain Bandwidth Product Conditions degrees VDD = 5V V/µs VDD = 5V * These parameters are characterized but not tested. Note 1: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001652D-page 96  2012-2016 Microchip Technology Inc. PIC16F527 TABLE 15-15: FLASH DATA MEMORY WRITE/ERASE TIME Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527 (Industrial)”. AC CHARACTERISTICS Param. No. Sym. 43 TDW 44 TDE Note 1: Min. Typ.(1) Max. Units Flash Data Memory Write Cycle Time 2 3.5 5 ms Flash Data Memory Erase Cycle Time 2 3.5 5 ms Characteristic Conditions Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 15-16: THERMAL CONSIDERATIONS Standard Operating Conditions (unless otherwise stated) VDD = 5.0V Operating temperature: 25°C Param. No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 62.2 C/W 20-pin PDIP package 77.7 C/W 20-pin SOIC package 87.3 C/W 20-pin SSOP package 43 C/W 20-pin QFN 4x4mm package 32.8 C/W 20-pin UQFN 4x4mm package 41 C/W 20-pin UQFN 3x3mm package 27.5 C/W 20-pin PDIP package 23.1 C/W 20-pin SOIC package 31.1 C/W 20-pin SSOP package 5.3 C/W 20-pin QFN 4x4mm package 27.4 C/W 20-pin UQFN 4x4mm package 49 C/W 20-pin UQFN 3x3mm package 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: 2: IDD is current to run the chip alone without driving any load on the output pins. TA = Ambient Temperature. TJ = Junction Temperature.  2012-2016 Microchip Technology Inc. DS40001652D-page 97 PIC16F527 16.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range. DS40001652D-page 98  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 16-1: IDD, LP OSCILLATOR, FOSC = 32 kHz 45 40 Max. Typical: Mean (25°C) Max: Mean + 3ı (85°C) 35 Typical IDD (µA) 30 25 20 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2012-2016 Microchip Technology Inc. DS40001652D-page 99 PIC16F527 FIGURE 16-2: IDD TYPICAL, XT AND EXTRC OSCILLATOR 800 Typical: Mean (25°C) 700 4 MHz XT 600 IDD (µA) 500 400 4 MHz EXTRC 300 1 MHz XT 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IDD MAXIMUM, XT AND EXTRC OSCILLATOR FIGURE 16-3: 800 Max: Mean + 3ı (-40°C to 125°C) 700 600 4 MHz XT IDD (µA) 500 400 4 MHz EXTRC 300 1 MHz XT 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001652D-page 100  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 16-4: IDD TYPICAL, EXTERNAL CLOCK MODE 800 700 Typical: Mean (25°C) 600 IDD (µA) 4 MHz 500 400 300 1 MHz 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 16-5: IDD MAXIMUM, EXTERNAL CLOCK MODE 800 Max: Mean + 3ı (-40°C to 125°C) 700 4 MHz 600 IDD (µA) 500 1 MHz 400 300 200 100 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2012-2016 Microchip Technology Inc. DS40001652D-page 101 PIC16F527 FIGURE 16-6: IDD TYPICAL, INTOSC 1.4 1.2 Typical: Mean (25°C) 1.0 IDD (mA) 8 MHz 0.8 0.6 4 MHz 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IDD MAXIMUM, INTOSC FIGURE 16-7: 1.4 Max: Mean + 3ı (-40°C to 125°C) 1.2 8 MHz IDD (mA) 1.0 0.8 0.6 4 MHz 0.4 0.2 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001652D-page 102  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 16-8: IDD TYPICAL, HS OSCILLATOR 2.5 Typical: Mean (25°C) 2.0 20 MHz IDD (mA) 1.5 1.0 8 MHz 0.5 4 MHz 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 16-9: IDD MAXIMUM, HS OSCILLATOR 2.5 20 MHz Max: Mean + 3ı (-40°C to 125°C) 2.0 IDD (mA) 1.5 8 MHz 1.0 4 MHz 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2012-2016 Microchip Technology Inc. DS40001652D-page 103 PIC16F527 FIGURE 16-10: IPD BASE, LOW-POWER SLEEP MODE 400 Typical: Mean (25°C) Max: Mean + 3ı (85°C) 350 Max. IPD (nA) 300 250 200 150 100 Typical 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 16-11: IPD, WATCHDOG TIMER (WDT) 18.0 Max. M 16.0 Typical: Mean (25°C) Max: Mean + 3ı (-40°C to 85°C) 14.0 IPD (µA A) 12.0 Typical 10.0 8.0 6.0 4.0 2.0 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001652D-page 104  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 16-12: IPD, FIXED VOLTAGE REFERENCE (FVR) 210 Max. Typical: Mean (25°C) Max: Mean + 3ı (-40°C to 85°C) 190 Typical 170 IPD (µA) 150 130 110 90 70 50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 16-13: IPD, BROWN-OUT RESET (BOR) 6 Typical: T i l M Mean (25°C) Max: Mean + 3ı (-40°C to 85°C) 5 Max. IPD (µA) 4 Typical 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2012-2016 Microchip Technology Inc. DS40001652D-page 105 PIC16F527 FIGURE 16-14: IPD, SINGLE COMPARATOR 80 Typical: Mean (25°C) Max: Mean + 3ı (-40°C to 85°C) 70 M Max. 60 Typical IPD (µA) 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) IPD, CVREF FIGURE 16-15: 100 Max. 90 Typical: Mean (25°C) Max: Mean + 3ı (-40°C to 85°C) 80 IPD (µA A) 70 Typical 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) DS40001652D-page 106  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 16-16: IPD, SINGLE OPERATIONAL AMPLIFIER (OPA) – UNITY GAIN MODE 500 Typical: Mean (25°C) Max: Mean + 3ı (-40°C to 85°C) 450 400 IPD (µA A) Max. 350 300 Typical 250 200 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2012-2016 Microchip Technology Inc. DS40001652D-page 107 PIC16F527 FIGURE 16-17: VOH vs. IOH OVER TEMPERATURE, VDD = 5.0V 5.5 5 VOH (V) Max. 4.5 Typical 4 Min. Max: Mean + 3ı (-40°C) Typical: Mean (25°C) Min: Mean - 3ı (125°C) 3.5 3 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 IOH (mA) VOL vs. IOL OVER TEMPERATURE, VDD = 5.0 V FIGURE 16-18: 0.5 0.45 Max: Mean + 3ı (125°C) Typical: Mean (25°C) Min: Mean - 3ı (-40°C) 0.4 Max. VOL (V) 0.35 0.3 0.25 Typical 0.2 0.15 Min. 0.1 0.05 0 4.5 DS40001652D-page 108 5.5 6.5 7.5 IOL (mA) 8.5 9.5 10.5  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 16-19: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0 V 3.5 3.0 Max. VOH (V) 2.5 Typical 2.0 1.5 Min. 1.0 Max: Mean + 3ı (-40°C) Typical: Mean (25°C) Min: Mean - 3ı (125°C) 0.5 0.0 -4.5 FIGURE 16-20: -4 -3.5 -3 -2.5 -2 IOH (mA) -1.5 -1 -0.5 0 VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V 0.8 Max: Mean + 3ı (125°C) Typical: Mean (25°C) Min: Mean - 3ı (-40°C) 0.7 0.6 Max. VOL (V) 0.5 0.4 Typical 0.3 0.2 Min. 0.1 0.0 4.5 5.5 6.5 7.5 8.5 9.5 10.5 IOL (mA)  2012-2016 Microchip Technology Inc. DS40001652D-page 109 PIC16F527 FIGURE 16-21: TTL INPUT THRESHOLD VIN vs. VDD 1.7 Max: Mean + 3ı (-40°C) Typical: Mean (25°C) Min: Mean - 3ı (125°C) 1.5 Max. 1.3 VIN (V) Typical 1.1 Min. 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 16-22: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD 4 VIH Max. (125°C) Max: Mean + 3ı (at Temp.) Min: Mean - 3ı (at Temp.) 3.5 3 VIN (V) VIH Min. (-40°C) 2.5 2 VIL Max. (-40°C) 1.5 VIL Min. (125°C) 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) DS40001652D-page 110  2012-2016 Microchip Technology Inc. PIC16F527 FIGURE 16-23: BROWN-OUT RESET VOLTAGE 2.40 2.35 Max: Mean Typical + 3ı Min: Mean Typical - 3ı 2.30 2.25 Voltage (V) 2.20 Max. 2.15 2.10 Min. 2.05 2.00 1.95 1.90 1.85 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 16-24: 50 WDT TIME-OUT PERIOD 45 Max: Mean + 3ı (at Temp.) Typical: Mean (25°C) Min: Mean - 3ı (-40°C) Max. (125°C) 40 35 Max. (85°C) Time (ms) 30 25 Typical 20 15 Min. 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V)  2012-2016 Microchip Technology Inc. DS40001652D-page 111 PIC16F527 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SOIC (7.50 mm) Example PIC16F527 -E/P e3 1307123 Example PIC16F527 -E/SO e3 1307123 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001652D-page 112  2012-2016 Microchip Technology Inc. PIC16F527 Package Marking Information (Continued) 20-Lead SSOP (5.30 mm) Example PIC16F527 -E/SS e3 1307123 20-Lead QFN (4x4x0.9 mm) 20-Lead UQFN (4x4x0.5mm) PIN 1 PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: * Example PIC16 F527 E/ML e3 307123 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard PICmicro® device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2012-2016 Microchip Technology Inc. DS40001652D-page 113 PIC16F527 Package Marking Information (Continued) 20-Lead UQFN (3x3x0.5 mm) XXX DAF YYWW NNN TABLE 17-1: Example 1307 123 20-LEAD 3x3x0.5 UQFN (JP) TOP MARKING Part Number Marking PIC16F527T-E/JP DAF PIC16F527T-I/JP DAE DS40001652D-page 114  2012-2016 Microchip Technology Inc. PIC16F527 /HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ  N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV ,1&+(6 0,1 1 120 0$;  3LWFK H 7RSWR6HDWLQJ3ODQH $ ± ±  0ROGHG3DFNDJH7KLFNQHVV $    %DVHWR6HDWLQJ3ODQH $  ± ± 6KRXOGHUWR6KRXOGHU:LGWK (    0ROGHG3DFNDJH:LGWK (    2YHUDOO/HQJWK '    7LSWR6HDWLQJ3ODQH /    /HDG7KLFNQHVV F    E    E    H% ± ± 8SSHU/HDG:LGWK /RZHU/HDG:LGWK 2YHUDOO5RZ6SDFLQJ† %6&  1RWHV  3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD  †6LJQLILFDQW&KDUDFWHULVWLF  'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH  'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(6623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV L 0,//,0(7(56 0,1 1 120 0$;  3LWFK H 2YHUDOO+HLJKW $ ± %6& ±  0ROGHG3DFNDJH7KLFNQHVV $    6WDQGRII $  ± ± 2YHUDOO:LGWK (    0ROGHG3DFNDJH:LGWK (    2YHUDOO/HQJWK '    )RRW/HQJWK /    )RRWSULQW / 5() /HDG7KLFNQHVV F  ± )RRW$QJOH  ƒ ƒ  ƒ /HDG:LGWK E  ±  1RWHV  3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD  'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH  'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(