PIC16F627A/628A/648A
Data Sheet
Flash-Based, 8-Bit CMOS
Microcontrollers with nanoWatt Technology
© 2009 Microchip Technology Inc.
DS40044G
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS40044G-page 2
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
18-pin Flash-Based, 8-Bit CMOS Microcontrollers
with nanoWatt Technology
High-Performance RISC CPU:
Low-Power Features:
•
•
•
•
•
• Standby Current:
- 100 nA @ 2.0V, typical
• Operating Current:
- 12 μA @ 32 kHz, 2.0V, typical
- 120 μA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 μA @ 2.0V, typical
• Timer1 Oscillator Current:
- 1.2 μA @ 32 kHz, 2.0V, typical
• Dual-speed Internal Oscillator:
- Run-time selectable between 4 MHz and
48 kHz
- 4 μs wake-up from Sleep, 3.0V, typical
Operating speeds from DC – 20 MHz
Interrupt capability
8-level deep hardware stack
Direct, Indirect and Relative Addressing modes
35 single-word instructions:
- All instructions single cycle except branches
Special Microcontroller Features:
• Internal and external oscillator options:
- Precision internal 4 MHz oscillator factory
calibrated to ±1%
- Low-power internal 48 kHz oscillator
- External Oscillator support for crystals and
resonators
• Power-saving Sleep mode
• Programmable weak pull-ups on PORTB
• Multiplexed Master Clear/Input-pin
• Watchdog Timer with independent oscillator for
reliable operation
• Low-voltage programming
• In-Circuit Serial Programming™ (via two pins)
• Programmable code protection
• Brown-out Reset
• Power-on Reset
• Power-up Timer and Oscillator Start-up Timer
• Wide operating voltage range (2.0-5.5V)
• Industrial and extended temperature range
• High-Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- 40 year data retention
Device
Program
Memory
Peripheral Features:
• 16 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Selectable internal or external reference
- Comparator outputs are externally accessible
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• Timer1: 16-bit timer/counter with external crystal/
clock capability
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module:
- 16-bit Capture/Compare
- 10-bit PWM
• Addressable Universal Synchronous/Asynchronous
Receiver/Transmitter USART/SCI
Data Memory
I/O
CCP
(PWM)
128
16
1
Y
2
2/1
128
16
1
Y
2
2/1
256
16
1
Y
2
2/1
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC16F627A
1024
224
PIC16F628A
2048
224
PIC16F648A
4096
256
© 2009 Microchip Technology Inc.
USART Comparators
Timers
8/16-bit
DS40044G-page 3
PIC16F627A/628A/648A
Pin Diagrams
PDIP, SOIC
1
18
RA1/AN1
RA3/AN3/CMP1
2
17
RA0/AN0
16
RA7/OSC1/CLKIN
15
RA6/OSC2/CLKOUT
14
VDD
13
RB7/T1OSI/PGD
12
RB6/T1OSO/T1CKI/PGC
11
RB5
10
RB4/PGM
3
RA5/MCLR/VPP
4
RB0/INT
6
RB1/RX/DT
7
RB2/TX/CK
8
RB3/CCP1
9
RA5/MCLR/VPP
DS40044G-page 4
RA1/AN1
RA0/AN0
8
9
10
NC 11
12
RB4/PGM
13
RB5
NC 14
1
21
NC 2
20
VSS
3
19
NC 4 PIC16F627A/628A 18 NC
PIC16F648A
VSS
17
5
NC 6
16
RB0/INT
7
15
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
VSS
VSS
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
1
2
3
4
5
6
7
8
9
10
PIC16F627A/628A/648A
28
27
26
25 NC
24
23
22 NC
RA4/T0CKI/CMP2
RA3/AN3/CMP1
RA2/AN2/VREF
28-Pin QFN
20
19
18
17
16
15
14
13
12
11
RA1/AN1
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5
RB4/PGM
VSS
5
PIC16F627A/628A/648A
RA4/T0CKI/CMP2
27A/628A/648A
SSOP
RA2/AN2/VREF
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
Table of Contents
1.0 General Description ........................................................................................................................................................................ 7
2.0 PIC16F627A/628A/648A Device Varieties...................................................................................................................................... 9
3.0 Architectural Overview .................................................................................................................................................................. 11
4.0 Memory Organization .................................................................................................................................................................... 17
5.0 I/O Ports ........................................................................................................................................................................................ 33
6.0 Timer0 Module .............................................................................................................................................................................. 47
7.0 Timer1 Module .............................................................................................................................................................................. 50
8.0 Timer2 Module .............................................................................................................................................................................. 54
9.0 Capture/Compare/PWM (CCP) Module ........................................................................................................................................ 57
10.0 Comparator Module .................................................................................................................................................................... 63
11.0 Voltage Reference Module ......................................................................................................................................................... 69
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module......................................................................... 73
13.0 Data EEPROM Memory .............................................................................................................................................................. 91
14.0 Special Features of the CPU ...................................................................................................................................................... 97
15.0 Instruction Set Summary........................................................................................................................................................... 117
16.0 Development Support ............................................................................................................................................................... 131
17.0 Electrical Specifications ............................................................................................................................................................ 135
18.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 151
19.0 Packaging Information .............................................................................................................................................................. 163
Appendix A: Data Sheet Revision History......................................................................................................................................... 171
Appendix B: Device Differences ....................................................................................................................................................... 171
Appendix C: Device Migrations ......................................................................................................................................................... 172
Appendix D: Migrating from other PIC® Devices .............................................................................................................................. 172
The Microchip Web Site .................................................................................................................................................................... 173
Customer Change Notification Service ............................................................................................................................................. 173
Customer Support ............................................................................................................................................................................. 173
Reader Response ............................................................................................................................................................................. 174
Product Identification System ........................................................................................................................................................... 179
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined
and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
© 2009 Microchip Technology Inc.
DS40044G-page 5
PIC16F627A/628A/648A
NOTES:
DS40044G-page 6
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
1.0
GENERAL DESCRIPTION
The PIC16F627A/628A/648A are 18-pin Flash-based
members of the versatile PIC16F627A/628A/648A
family of low-cost, high-performance, CMOS, fullystatic, 8-bit microcontrollers.
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC16F627A/628A/648A have
enhanced core features, an eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a singlecycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available, complemented by a large register
set.
PIC16F627A/628A/648A microcontrollers typically
achieve a 2:1 code compression and a 4:1 speed
improvement over other 8-bit microcontrollers in their
class.
PIC16F627A/628A/648A devices have integrated
features to reduce external components, thus reducing
system cost, enhancing system reliability and reducing
power consumption.
The PIC16F627A/628A/648A has 8 oscillator
configurations. The single-pin RC oscillator provides a
low-cost solution. The LP oscillator minimizes power
consumption, XT is a standard crystal, and INTOSC is
a self-contained precision two-speed internal oscillator.
TABLE 1-1:
Clock
Memory
Peripherals
The Sleep (Power-down) mode offers power savings.
Users can wake-up the chip from Sleep through several
external interrupts, internal interrupts and Resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
Table 1-1 shows the features of the PIC16F627A/628A/
648A mid-range microcontroller family.
A simplified block diagram of the PIC16F627A/628A/
648A is shown in Figure 3-1.
The PIC16F627A/628A/648A series fits in applications
ranging from battery chargers to low power remote
sensors. The Flash technology makes customizing
application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The
small footprint packages makes this microcontroller
series ideal for all applications with space limitations.
Low cost, low power, high performance, ease of use
and I/O flexibility make the PIC16F627A/628A/648A
very versatile.
1.1
Development Support
The PIC16F627A/628A/648A family is supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a low cost in-circuit debugger, a low
cost development programmer and a full-featured
programmer. A Third Party “C” compiler support tool is
also available.
PIC16F627A/628A/648A FAMILY OF DEVICES
PIC16F627A
PIC16F628A
PIC16F648A
PIC16LF627A
PIC16LF628A
PIC16LF648A
20
20
20
20
20
20
Flash Program
Memory (words)
1024
2048
4096
1024
2048
4096
RAM Data Memory
(bytes)
224
224
256
224
224
256
EEPROM Data
Memory (bytes)
128
128
256
128
128
256
Timer module(s)
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
Comparator(s)
2
2
2
2
2
2
Capture/Compare/
PWM modules
1
1
1
1
1
1
USART
USART
USART
USART
USART
USART
Yes
Yes
Yes
Yes
Yes
Yes
10
Maximum Frequency
of Operation (MHz)
Serial Communications
Internal Voltage
Reference
Features
The HS mode is for High-Speed crystals. The EC mode
is for an external clock source.
Interrupt Sources
10
10
10
10
10
I/O Pins
16
16
16
16
16
16
3.0-5.5
3.0-5.5
3.0-5.5
2.0-5.5
2.0-5.5
2.0-5.5
Voltage Range (Volts)
Brown-out Reset
Packages
Yes
Yes
Yes
Yes
Yes
Yes
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
All PIC® family devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect and high I/O current capability.
All PIC16F627A/628A/648A family devices use serial programming with clock pin RB6 and data pin RB7.
© 2009 Microchip Technology Inc.
DS40044G-page 7
PIC16F627A/628A/648A
NOTES:
DS40044G-page 8
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
2.0
PIC16F627A/628A/648A
DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16F627A/628A/648A
Product Identification System, at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1
Flash Devices
Flash devices can be erased and re-programmed
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
A further advantage of the electrically erasable Flash is
that it can be erased and reprogrammed in-circuit, or by
device programmers, such as Microchip’s PICSTART®
Plus or PRO MATE® II programmers.
2.2
Quick-Turnaround-Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are standard Flash devices, but
with all program locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more
details.
2.3
Serialized Quick-TurnaroundProduction (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
© 2009 Microchip Technology Inc.
DS40044G-page 9
PIC16F627A/628A/648A
NOTES:
DS40044G-page 10
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16F627A/628A/648A
family can be attributed to a number of architectural
features commonly found in RISC microprocessors. To
begin with, the PIC16F627A/628A/648A uses a
Harvard architecture in which program and data are
accessed from separate memories using separate
busses. This improves bandwidth over traditional Von
Neumann architecture where program and data are
fetched from the same memory. Separating program
and data memory further allows instructions to be sized
differently than 8-bit wide data word. Instruction
opcodes are 14-bits wide making it possible to have all
single-word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single
cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35)
execute in a single-cycle (200 ns @ 20 MHz) except for
program branches.
Table 3-1 lists device memory sizes (Flash, Data and
EEPROM).
TABLE 3-1:
DEVICE MEMORY LIST
Memory
Device
Flash
Program
RAM
Data
EEPROM
Data
PIC16F627A
1024 x 14
224 x 8
128 x 8
PIC16F628A
2048 x 14
224 x 8
128 x 8
PIC16F648A
4096 x 14
256 x 8
256 x 8
PIC16LF627A
1024 x 14
224 x 8
128 x 8
PIC16LF628A
2048 x 14
224 x 8
128 x 8
PIC16LF648A
4096 x 14
256 x 8
256 x 8
The PIC16F627A/628A/648A can directly or indirectly
address its register files or data memory. All Special
Function Registers (SFR), including the program
counter, are mapped in the data memory. The
PIC16F627A/628A/648A have an orthogonal (symmetrical) instruction set that makes it possible to carry out
any operation, on any register, using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ makes programming with the
PIC16F627A/628A/648A simple yet efficient. In
addition, the learning curve is reduced significantly.
The PIC16F627A/628A/648A devices contain an 8-bit
ALU and working register. The ALU is a general
purpose arithmetic unit. It performs arithmetic and
Boolean functions between data in the working register
and any register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two’s
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the Status Register. The C and DC bits
operate as Borrow and Digit Borrow out bits,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, and
a description of the device pins in Table 3-2.
Two types of data memory are provided on the
PIC16F627A/628A/648A
devices.
Nonvolatile
EEPROM data memory is provided for long term
storage of data, such as calibration values, look-up
table data, and any other data which may require
periodic updating in the field. These data types are not
lost when power is removed. The other data memory
provided is regular RAM data memory. Regular RAM
data memory is provided for temporary storage of data
during normal operation. Data is lost when power is
removed.
© 2009 Microchip Technology Inc.
DS40044G-page 11
PIC16F627A/628A/648A
FIGURE 3-1:
BLOCK DIAGRAM
13
Flash
Program
Memory
RAM
File
Registers
8-Level Stack
(13-bit)
Program
Bus
14
8
Data Bus
Program Counter
RAM Addr (1)
PORTA
9
Addr MUX
Instruction Reg
Direct Addr
7
8
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
Indirect
Addr
FSR Reg
Status Reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MUX
ALU
8
W Reg
PORTB
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
Low-Voltage
Programming
MCLR
Comparator
Timer0
VREF
CCP1
Note
1:
VDD, VSS
Timer1
USART
Timer2
Data EEPROM
Higher order bits are from the Status register.
DS40044G-page 12
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 3-2:
PIC16F627A/628A/648A PINOUT DESCRIPTION
Name
Function
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
Input Type Output Type
CMOS
Description
RA0
ST
Bidirectional I/O port
AN0
AN
—
RA1
ST
CMOS
AN1
AN
—
RA2
ST
CMOS
AN2
AN
—
Analog comparator input
VREF
—
AN
VREF output
RA3
ST
CMOS
AN3
AN
—
CMP1
—
CMOS
Comparator 1 output
RA4
ST
OD
Bidirectional I/O port
T0CKI
ST
—
Timer0 clock input
CMP2
—
OD
Comparator 2 output
RA5
ST
—
Input port
MCLR
ST
—
Master clear. When configured as MCLR, this
pin is an active low Reset to the device.
Voltage on MCLR/VPP must not exceed VDD
during normal device operation.
Programming voltage input
Analog comparator input
Bidirectional I/O port
Analog comparator input
Bidirectional I/O port
Bidirectional I/O port
Analog comparator input
VPP
—
—
RA6
ST
CMOS
Bidirectional I/O port
OSC2
—
XTAL
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
CLKOUT
—
CMOS
In RC/INTOSC mode, OSC2 pin can output
CLKOUT, which has 1/4 the frequency of
OSC1.
RA7
ST
CMOS
Bidirectional I/O port
OSC1
XTAL
—
Oscillator crystal input
External clock source input. RC biasing pin.
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
CLKIN
ST
—
RB0/INT
RB0
TTL
CMOS
INT
ST
—
RB1/RX/DT
RB1
TTL
CMOS
RX
ST
—
DT
ST
CMOS
Synchronous data I/O
RB2
TTL
CMOS
Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
RB2/TX/CK
RB3/CCP1
O = Output
— = Not used
TTL = TTL Input
© 2009 Microchip Technology Inc.
External interrupt
Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
USART receive pin
TX
—
CMOS
USART transmit pin
CK
ST
CMOS
Synchronous clock I/O
RB3
TTL
CMOS
Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
ST
CMOS
Capture/Compare/PWM I/O
CCP1
Legend:
Bidirectional I/O port. Can be software
programmed for internal weak pull-up.
CMOS = CMOS Output
I
= Input
OD
= Open Drain Output
P = Power
ST = Schmitt Trigger Input
AN = Analog
DS40044G-page 13
PIC16F627A/628A/648A
TABLE 3-2:
PIC16F627A/628A/648A PINOUT DESCRIPTION (CONTINUED)
Name
RB4/PGM
Function
Input Type Output Type
Description
RB4
TTL
CMOS
Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
PGM
ST
—
RB5
RB5
TTL
CMOS
Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
RB6/T1OSO/T1CKI/PGC
RB6
TTL
CMOS
Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
T1OSO
—
XTAL
Timer1 oscillator output
Low-voltage programming input pin. When
low-voltage programming is enabled, the
interrupt-on-pin change and weak pull-up
resistor are disabled.
T1CKI
ST
—
Timer1 clock input
PGC
ST
—
ICSP™ programming clock
RB7
TTL
CMOS
T1OSI
XTAL
—
PGD
ST
CMOS
VSS
VSS
Power
—
Ground reference for logic and I/O pins
VDD
VDD
Power
—
Positive supply for logic and I/O pins
RB7/T1OSI/PGD
Legend:
O = Output
— = Not used
TTL = TTL Input
DS40044G-page 14
Bidirectional I/O port. Interrupt-on-pin change.
Can be software programmed for internal
weak pull-up.
Timer1 oscillator input
ICSP data I/O
CMOS = CMOS Output
I
= Input
OD
= Open Drain Output
P = Power
ST = Schmitt Trigger Input
AN = Analog
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
The clock input (RA7/OSC1/CLKIN pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the Program Counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
A fetch cycle begins with the program counter
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q1
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC + 1
PC + 2
CLKOUT
Fetch INST (PC)
Execute INST (PC - 1)
EXAMPLE 3-1:
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, 3
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
Note:
All instructions are single cycle except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
© 2009 Microchip Technology Inc.
DS40044G-page 15
PIC16F627A/628A/648A
NOTES:
DS40044G-page 16
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
The PIC16F627A/628A/648A has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h-03FFh)
for the PIC16F627A, 2K x 14 (0000h-07FFh) for the
PIC16F628A and 4K x 14 (0000h-0FFFh) for the
PIC16F648A are physically implemented. Accessing a
location above these boundaries will cause a wraparound within the first 1K x 14 space (PIC16F627A),
2K x 14 space (PIC16F628A) or 4K x 14 space
(PIC16F648A). The Reset vector is at 0000h and the
interrupt vector is at 0004h (Figure 4-1).
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK
PC
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
On-chip Program
Memory
The data memory (Figure 4-2 and Figure 4-3) is
partitioned into four banks, which contain the General
Purpose Registers (GPRs) and the Special Function
Registers (SFRs). The SFRs are located in the first 32
locations of each bank. There are General Purpose
Registers implemented as static RAM in each bank.
Table 4-1 lists the General Purpose Register available
in each of the four banks.
TABLE 4-1:
Bank0
GENERAL PURPOSE STATIC
RAM REGISTERS
PIC16F627A/628A
PIC16F648A
20-7Fh
20-7Fh
Bank1
A0h-FF
A0h-FF
Bank2
120h-14Fh, 170h-17Fh
120h-17Fh
Bank3
1F0h-1FFh
1F0h-1FFh
Table 4-2 lists how to access the four banks of registers
via the Status register bits RP1 and RP0.
Stack Level 8
Interrupt Vector
Data Memory Organization
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
13
Reset Vector
4.2
TABLE 4-2:
000h
0004
0005
4.2.1
PIC16F627A,
PIC16F628A and
PIC16F648A
03FFh
On-chip Program
Memory
PIC16F628A and
PIC16F648A
ACCESS TO BANKS OF
REGISTERS
Bank
RP1
RP0
0
0
0
1
0
1
2
1
0
3
1
1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 224 x 8 in the
PIC16F627A/628A and 256 x 8 in the PIC16F648A.
Each is accessed either directly or indirectly through
the File Select Register (FSR), See Section 4.4
“Indirect Addressing, INDF and FSR Registers”.
07FFh
On-chip Program
Memory
PIC16F648A only
0FFFh
1FFFh
© 2009 Microchip Technology Inc.
DS40044G-page 17
PIC16F627A/628A/648A
FIGURE 4-2:
DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A
File
Address
Indirect addr.(1)
00h
Indirect addr.(1)
80h
Indirect addr.(1)
100h
Indirect addr.(1)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
PORTB
06h
TRISB
86h
PCL
105h
PORTB
106h
185h
TRISB
186h
07h
87h
107h
187h
08h
88h
108h
188h
89h
109h
09h
189h
8Ah
PCLATH
10Ah
PCLATH
18Ah
8Bh
INTCON
10Bh
INTCON
18Bh
PCLATH
0Ah
INTCON
0Bh
PCLATH
INTCON
PIR1
0Ch
PIE1
8Ch
10Ch
18Ch
8Dh
10Dh
18Dh
8Eh
10Eh
18Eh
10Fh
18Fh
0Dh
TMR1L
0Eh
TMR1H
0Fh
8Fh
T1CON
10h
90h
TMR2
11h
T2CON
12h
PCON
91h
PR2
92h
13h
93h
14h
94h
CCPR1L
15h
95h
CCPR1H
16h
96h
CCP1CON
17h
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
99h
RCREG
1Ah
SPBRG
EEDATA
1Bh
EEADR
9Bh
1Ch
EECON1
9Ch
1Dh
EECON2(1)
9Dh
1Eh
CMCON
1Fh
9Eh
VRCON
20h
9Fh
A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
6Fh
70h
16 Bytes
7Fh
Bank 0
9Ah
accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
General
Purpose
Register
48 Bytes
accesses
70h-7Fh
11Fh
120h
14Fh
150h
16Fh
170h
17Fh
Bank 2
accesses
70h-7Fh
Bank 3
1EFh
1F0h
1FFh
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
DS40044G-page 18
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 4-3:
DATA MEMORY MAP OF THE PIC16F648A
File
Address
Indirect addr.(1)
00h
Indirect addr.(1)
80h
Indirect addr.(1)
100h
Indirect addr.(1)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
PORTB
06h
TRISB
86h
PCL
105h
PORTB
106h
185h
TRISB
186h
07h
87h
107h
187h
08h
88h
108h
188h
89h
109h
189h
09h
8Ah
PCLATH
10Ah
PCLATH
18Ah
8Bh
INTCON
10Bh
INTCON
18Bh
PCLATH
0Ah
PCLATH
INTCON
0Bh
INTCON
PIR1
0Ch
PIE1
8Ch
10Ch
18Ch
8Dh
10Dh
18Dh
8Eh
10Eh
18Eh
10Fh
18Fh
0Dh
TMR1L
0Eh
TMR1H
0Fh
8Fh
T1CON
10h
90h
TMR2
11h
T2CON
12h
PCON
91h
PR2
92h
13h
93h
14h
94h
CCPR1L
15h
95h
CCPR1H
16h
96h
CCP1CON
17h
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
99h
RCREG
1Ah
SPBRG
EEDATA
1Bh
EEADR
9Bh
1Ch
EECON1
9Ch
1Dh
EECON2(1)
9Dh
1Eh
CMCON
1Fh
9Ah
9Eh
VRCON
20h
9Fh
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
6Fh
70h
16 Bytes
7Fh
Bank 0
11Fh
120h
A0h
accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
accesses
70h-7Fh
16Fh
170h
17Fh
Bank 2
accesses
70h-7Fh
Bank 3
1EFh
1F0h
1FFh
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
© 2009 Microchip Technology Inc.
DS40044G-page 19
PIC16F627A/628A/648A
4.2.2
SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3:
Address
SPECIAL REGISTERS SUMMARY BANK0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
30
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
47
02h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
30
03h
STATUS
0001 1xxx
24
04h
FSR
xxxx xxxx
30
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx 0000
33
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
38
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
---0 0000
30
0Ah
PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
26
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
28
0Dh
—
Unimplemented
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
11h
TMR2
12h
T2CON
13h
—
14h
—
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TMR2 Module’s Register
—
—
xxxx xxxx
50
xxxx xxxx
50
--00 0000
50
0000 0000
54
-000 0000
54
Unimplemented
—
—
Unimplemented
—
—
xxxx xxxx
57
—
TOUTPS3
TOUTPS2 TOUTPS1
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
16h
CCPR1H
Capture/Compare/PWM Register (MSB)
17h
CCP1CON
18h
RCSTA
19h
TXREG
1Ah
RCREG
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
xxxx xxxx
57
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
57
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x
74
USART Transmit Data Register
0000 0000
79
USART Receive Data Register
0000 0000
82
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
—
Unimplemented
—
—
0000 0000
63
1Fh
Legend:
Note 1:
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
DS40044G-page 20
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 4-4:
Address
SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
xxxx xxxx
30
1111 1111
25
0000 0000
30
0001 1xxx
24
xxxx xxxx
30
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
81h
OPTION
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
33
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
38
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
---0 0000
30
8Ah
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
26
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000
27
—
—
—
—
OSCF
—
POR
BOR
---- 1-0x
29
8Dh
—
8Eh
PCON
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
1111 1111
54
92h
PR2
Unimplemented
—
—
Timer2 Period Register
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
0000 -010
73
99h
SPBRG
Baud Rate Generator Register
0000 0000
75
9Ah
EEDATA
EEPROM Data Register
xxxx xxxx
91
9Bh
EEADR
EEPROM Address Register
xxxx xxxx
92
9Ch
EECON1
---- x000
92
9Dh
EECON2
---- ----
92
9Eh
—
CSRC
TX9
—
—
TXEN
—
SYNC
—
—
WRERR
BRGH
WREN
TRMT
WR
TX9D
RD
EEPROM Control Register 2 (not a physical register)
Unimplemented
VREN
VRR
—
000- 0000
69
9Fh
VRCON
Legend:
Note 1:
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
© 2009 Microchip Technology Inc.
VROE
—
—
VR3
VR2
VR1
VR0
DS40044G-page 21
PIC16F627A/628A/648A
TABLE 4-5:
Address
SPECIAL FUNCTION REGISTERS SUMMARY BANK2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
Bank 2
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
30
101h
TMR0
Timer0 Module’s Register
xxxx xxxx
47
102h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
30
103h
STATUS
0001 1xxx
24
104h
FSR
xxxx xxxx
30
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
105h
—
106h
PORTB
107h
—
108h
—
109h
—
10Ah
PCLATH
10Bh
INTCON
Unimplemented
—
—
xxxx xxxx
38
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
---0 0000
30
RB7
RB6
RB5
—
—
—
GIE
PEIE
T0IE
RB4
RB3
RB2
RB1
RB0
Write Buffer for upper 5 bits of Program Counter
0000 000x
26
10Ch
—
Unimplemented
—
—
10Dh
—
Unimplemented
—
—
10Eh
—
Unimplemented
—
—
10Fh
—
Unimplemented
—
—
110h
—
Unimplemented
—
—
111h
—
Unimplemented
—
—
112h
—
Unimplemented
—
—
113h
—
Unimplemented
—
—
114h
—
Unimplemented
—
—
115h
—
Unimplemented
—
—
116h
—
Unimplemented
—
—
117h
—
Unimplemented
—
—
118h
—
Unimplemented
—
—
119h
—
Unimplemented
—
—
11Ah
—
Unimplemented
—
—
11Bh
—
Unimplemented
—
—
11Ch
—
Unimplemented
—
—
11Dh
—
Unimplemented
—
—
11Eh
—
Unimplemented
—
—
11Fh
—
Unimplemented
—
—
Legend:
Note 1:
INTE
RBIE
T0IF
INTF
RBIF
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented.
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
DS40044G-page 22
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 4-6:
Address
SPECIAL FUNCTION REGISTERS SUMMARY BANK3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details
on Page
Bank 3
180h
INDF
181h
OPTION
182h
PCL
183h
STATUS
184h
FSR
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
185h
—
186h
TRISB
187h
—
188h
—
189h
—
18Ah
PCLATH
18Bh
INTCON
Unimplemented
1111 1111
30
25
0000 0000
30
0001 1xxx
24
xxxx xxxx
30
—
—
1111 1111
38
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
---0 0000
30
TRISB7
TRISB6
TRISB5
—
—
—
GIE
PEIE
T0IE
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
Write Buffer for upper 5 bits of Program Counter
0000 000x
26
18Ch
—
Unimplemented
—
—
18Dh
—
Unimplemented
—
—
18Eh
—
Unimplemented
—
—
18Fh
—
Unimplemented
—
—
190h
—
Unimplemented
—
—
191h
—
Unimplemented
—
—
192h
—
Unimplemented
—
—
193h
—
Unimplemented
—
—
194h
—
Unimplemented
—
—
195h
—
Unimplemented
—
—
196h
—
Unimplemented
—
—
197h
—
Unimplemented
—
—
198h
—
Unimplemented
—
—
199h
—
Unimplemented
—
—
19Ah
—
Unimplemented
—
—
19Bh
—
Unimplemented
—
—
19Ch
—
Unimplemented
—
—
19Dh
—
Unimplemented
—
—
19Eh
—
Unimplemented
—
—
19Fh
—
Unimplemented
—
—
Legend:
Note 1:
INTE
RBIE
T0IF
INTF
RBIF
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.
© 2009 Microchip Technology Inc.
DS40044G-page 23
PIC16F627A/628A/648A
4.2.2.1
Status Register
The Status register, shown in Register 4-1, contains the
arithmetic status of the ALU; the Reset status and the
bank select bits for data memory (SRAM).
The Status register can be the destination for any
instruction, like any other register. If the Status register
is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are nonwritable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
REGISTER 4-1:
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the Status register
as “000uu1uu” (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Status register because these instructions do not affect
any Status bit. For other instructions, not affecting any
Status bits, see the “Instruction Set Summary”.
Note:
The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5
RP: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4
TO: Time Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for Borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
DS40044G-page 24
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.2
OPTION Register
Note:
The Option register is a readable and writable register,
which contains various control bits to configure the
TMR0/WDT prescaler, the external RB0/INT interrupt,
TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1). See Section 6.3.1 “Switching
Prescaler Assignment”.
OPTION_REG – OPTION REGISTER (ADDRESS: 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI/CMP2 pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI/CMP2 pin
0 = Increment on low-to-high transition on RA4/T0CKI/CMP2 pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate WDT Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 25
PIC16F627A/628A/648A
4.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See
Section 4.2.2.4
“PIE1
Register”
and
Section 4.2.2.5 “PIR1 Register” for a description of
the comparator enable and flag bits.
REGISTER 4-3:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB pins changes state (must be cleared in software)
0 = None of the RB pins have changed state
Legend:
DS40044G-page 26
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.4
PIE1 Register
This register contains interrupt enable bits.
REGISTER 4-4:
PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable Bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 27
PIC16F627A/628A/648A
4.2.2.5
PIR1 Register
Note:
This register contains interrupt flag bits.
REGISTER 4-5:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
PIR1 – PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0
R/W-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6
CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed
0 = Comparator output has not changed
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
DS40044G-page 28
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.6
PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR Reset,
WDT Reset or a Brown-out Reset.
REGISTER 4-6:
Note:
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent Resets to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR Status bit is a “don’t
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
clearing the BOREN bit in the
Configuration Word).
PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0
U-0
U-0
U-0
R/W-1
U-0
R/W-0
R/W-x
—
—
—
—
OSCF
—
POR
BOR
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
OSCF: INTOSC Oscillator Frequency bit
1 = 4 MHz typical
0 = 48 kHz typical
bit 2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 29
PIC16F627A/628A/648A
4.3
PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The high byte (PC) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 4-4 shows the
two situations for loading the PC. The upper example
in Figure 4-4 shows how the PC is loaded on a write to
PCL (PCLATH → PCH). The lower example in
Figure 4-4 shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH → PCH).
FIGURE 4-4:
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
LOADING OF PC IN
DIFFERENT SITUATIONS
4.4
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
ALU result
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no-operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS), as shown in Figure 4-5.
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH
Indirect Addressing, INDF and
FSR Registers
11
Opcode
PCLATH
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
EXAMPLE 4-1:
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556 “Implementing a Table Read”
(DS00556).
4.3.2
NEXT
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
STACK
The PIC16F627A/628A/648A family has an 8-level
deep x 13-bit wide hardware stack (Figure 4-1). The
stack space is not part of either program or data space
and the Stack Pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.
DS40044G-page 30
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 4-5:
Status
Register
RP1 RP0
DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A
Status
Register
IRP
Direct Addressing
6
from opcode
bank select
0
location select
00
00h
Indirect Addressing
7
bank select
01
10
FSR Register
0
location select
11
180h
RAM
File
Registers
7Fh
1FFh
Bank 0
Note:
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.
© 2009 Microchip Technology Inc.
DS40044G-page 31
PIC16F627A/628A/648A
NOTES:
DS40044G-page 32
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
5.0
I/O PORTS
The PIC16F627A/628A/648A have two ports, PORTA
and PORTB. Some pins for these I/O ports are
multiplexed with alternate functions for the peripheral
features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
5.1
PORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. RA5(1) is a Schmitt Trigger
input only and has no output drivers. All other RA port
pins have Schmitt Trigger input levels and full CMOS
output drivers. All pins have data direction bits (TRIS
registers) which can configure these pins as input or
output.
A ‘1’ in the TRISA register puts the corresponding
output driver in a High-impedance mode. A ‘0’ in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(Comparator Control register) register and the VRCON
(Voltage Reference Control register) register. When
selected as a comparator input, these pins will read
as ‘0’s.
Note 1: RA5 shares function with VPP. When VPP
voltage levels are applied to RA5, the
device will enter Programming mode.
2: On Reset, the TRISA register is set to all
inputs. The digital inputs (RA) are
disabled and the comparator inputs are
forced to ground to reduce current
consumption.
3: TRISA is overridden by oscillator
configuration. When PORTA is
overridden, the data reads ‘0’ and the
TRISA bits are ignored.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
INITIALIZING PORTA
CLRF
PORTA
MOVLW
MOVWF
0x07
CMCON
BCF
BSF
MOVLW
STATUS, RP1
STATUS, RP0 ;Select Bank1
0x1F
;Value used to initialize
;data direction
TRISA
;Set RA as inputs
;TRISA always
;read as ‘1’.
;TRISA
;depend on oscillator
;mode
MOVWF
;Initialize PORTA by
;setting
;output data latches
;Turn comparators off and
;enable pins for I/O
;functions
FIGURE 5-1:
Data
Bus
D
WR
PORTA
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
Q
CK
VDD
Q
Data Latch
D
WR
TRISA
Q
CK
Q
TRIS Latch
RD
TRISA
I/O Pin
Analog
Input Mode
(CMCON Reg.)
VSS
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high-impedance output. The user must configure
TRISA bit as an input and use high-impedance
loads.
© 2009 Microchip Technology Inc.
DS40044G-page 33
PIC16F627A/628A/648A
FIGURE 5-2:
Data
Bus
BLOCK DIAGRAM OF
RA2/AN2/VREF PIN
D
WR
PORTA
Q
CK
VDD
Q
Data Latch
D
WR
TRISA
Q
CK
RA2 Pin
Analog
Input Mode
(CMCON Reg.)
Q
TRIS Latch
RD
TRISA
VSS
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
VROE
VREF
FIGURE 5-3:
Data
Bus
BLOCK DIAGRAM OF THE RA3/AN3/CMP1 PIN
Comparator Mode = 110 (CMCON Reg.)
D
Comparator Output
WR
PORTA
1
CK
Q
Data Latch
D
WR
TRISA
VDD
Q
0
Q
CK
RA3 Pin
Analog
Input Mode
(CMCON Reg.)
Q
TRIS Latch
RD
TRISA
VSS
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
DS40044G-page 34
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-4:
Data
Bus
BLOCK DIAGRAM OF RA4/T0CKI/CMP2 PIN
Comparator Mode = 110
D
(CMCON Reg.)
Q
Comparator Output
WR
PORTA
1
CK
Q
Data Latch
D
WR
TRISA
0
Q
RA4 Pin
N
CK
Q
Vss
Vss
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
FIGURE 5-5:
MCLR
circuit
BLOCK DIAGRAM OF THE
RA5/MCLR/VPP PIN
MCLRE (Configuration Bit)
BLOCK DIAGRAM OF
RA6/OSC2/CLKOUT PIN
From OSC1
OSC
Circuit
1
HV Detect
WR
PORTA
Schmitt Trigger
Input Buffer
RA5/MCLR/VPP
Data
Bus
VSS
Q
0
WR
TRISA
D
VSS
Q
CK Q
TRIS Latch
Schmitt
Trigger
Input Buffer
FOSC =
011, 100, 110 (1)
VSS
Q
D
CK Q
FOSC =
Data Latch
(2)
101, 111
RD
TRISA
RD
TRISA
VDD
CLKOUT(FOSC/4)
MCLR Filter
Program
mode
FIGURE 5-6:
D
Q
EN
EN
RD
PORTA
D
RD PORTA
Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.
2: INTOSC with RA6 = CLKOUT or RC with
RA6 = CLKOUT.
© 2009 Microchip Technology Inc.
DS40044G-page 35
PIC16F627A/628A/648A
FIGURE 5-7:
BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
To Clock Circuits
Data Bus
D
WR PORTA
VDD
Q
RA7/OSC1/CLKIN Pin
CK
Q
Data Latch
D
WR TRISA
CK
VSS
Q
Q
TRIS Latch
RD TRISA
FOSC = 100, 101(1)
Q
D
EN
Schmitt Trigger
Input Buffer
RD PORTA
Note 1:
DS40044G-page 36
INTOSC with CLKOUT and INTOSC with I/O.
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 5-1:
PORTA FUNCTIONS
Name
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
Legend:
Function
Input
Type
Output
Type
RA0
ST
CMOS
AN0
AN
—
RA1
ST
CMOS
AN1
AN
—
RA2
ST
CMOS
AN2
AN
—
Analog comparator input
VREF
—
AN
VREF output
RA3
ST
CMOS
AN3
AN
—
CMP1
—
CMOS
RA4
ST
OD
Bidirectional I/O port. Output is open drain type.
T0CKI
ST
—
External clock input for TMR0 or comparator output
CMP2
—
OD
Comparator 2 output
RA5
ST
—
Input port
MCLR
ST
—
Master clear. When configured as MCLR, this pin is an
active low Reset to the device. Voltage on MCLR/VPP must
not exceed VDD during normal device operation.
VPP
HV
—
Programming voltage input
Bidirectional I/O port
Analog comparator input
Bidirectional I/O port
Analog comparator input
Bidirectional I/O port
Bidirectional I/O port
Analog comparator input
Comparator 1 output
RA6
ST
CMOS
Bidirectional I/O port
OSC2
—
XTAL
Oscillator crystal output. Connects to crystal resonator in
Crystal Oscillator mode.
CLKOUT
—
CMOS
In RC or INTOSC mode. OSC2 pin can output CLKOUT,
which has 1/4 the frequency of OSC1.
RA7
ST
CMOS
OSC1
XTAL
—
Oscillator crystal input. Connects to crystal resonator in
Crystal Oscillator mode.
CLKIN
ST
—
External clock source input. RC biasing pin.
O = Output
— = Not used
TTL = TTL Input
TABLE 5-2:
Description
Bidirectional I/O port
CMOS = CMOS Output
I
= Input
OD
= Open Drain Output
P = Power
ST = Schmitt Trigger Input
AN = Analog
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
Resets
05h
PORTA
RA7
RA6
RA5(1)
RA4
RA3
RA2
RA1
RA0
xxxx 0000
qqqu 0000
85h
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
1111 1111
1111 1111
1Fh
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
0000 0000
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
Legend:
- = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition. Shaded cells
are not used for PORTA.
MCLRE configuration bit sets RA5 functionality.
Address
Note 1:
© 2009 Microchip Technology Inc.
DS40044G-page 37
PIC16F627A/628A/648A
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. A ‘1’ in
the TRISB register puts the corresponding output driver
in a High-impedance mode. A ‘0’ in the TRISB register
puts the contents of the output latch on the selected
pin(s).
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR1 clock input/output.
The standard port functions and the alternate port
functions are shown in Table 5-3. Alternate port
functions may override the TRIS setting when enabled.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 μA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON).
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 5-8:
BLOCK DIAGRAM OF
RB0/INT PIN
VDD
RBPU
P Weak Pull-up
VDD
Data Bus
WR PORTB
D
Q
RB0/INT
CK
Q
VSS
Data Latch
D
WR TRISB
CK
Q
Q
TRIS Latch
TTL
Input
Buffer
RD TRISB
Q
D
EN
EN
RD PORTB
INT
Schmitt
Trigger
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (See Application Note
AN552 “Implementing Wake-up on Key Strokes”
(DS00552).
Note:
If a change on the I/O pin should occur
when a read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
DS40044G-page 38
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-9:
BLOCK DIAGRAM OF
RB1/RX/DT PIN
FIGURE 5-10:
BLOCK DIAGRAM OF
RB2/TX/CK PIN
VDD
RBPU
Weak
P Pull-up
VDD
SPEN
USART Data Output
Data Bus
WR PORTB
Q
CK
Q
RB1/
RX/DT
0
WR TRISB
Q
CK
Q
Data Bus
WR PORTB
Data Latch
D
SPEN
USART TX/CK Output
1
D
VDD
Weak
P Pull-up
VDD
RBPU
1
D
Q
CK
Q
Data Latch
VSS
WR TRISB
TRIS Latch
D
Q
CK
Q
VSS
TRIS Latch
Peripheral OE(1)
Peripheral OE(1)
TTL
Input
Buffer
RD TRISB
Q
TTL
Input
Buffer
RD TRISB
D
Q
EN
RD PORTB
RD PORTB
USART Slave Clock In
Schmitt
Trigger
1:
D
EN
USART Receive Input
Note
RB2/
TX/CK
0
Peripheral OE (output enable) is only active if
peripheral select is active.
© 2009 Microchip Technology Inc.
Schmitt
Trigger
Note
1:
Peripheral OE (output enable) is only active if
peripheral select is active.
DS40044G-page 39
PIC16F627A/628A/648A
FIGURE 5-11:
BLOCK DIAGRAM OF
RB3/CCP1 PIN
VDD
Weak
P Pull-up
VDD
RBPU
CCP1CON
CCP output
0
Data Bus
WR PORTB
D
Q
CK
Q
RB3/
CCP1
1
Data Latch
WR TRISB
D
Q
CK
Q
VSS
TRIS Latch
Peripheral OE(2)
TTL
Input
Buffer
RD TRISB
Q
D
EN
RD PORTB
CCP In
Schmitt
Trigger
Note
1:
Peripheral OE (output enable) is only active if
peripheral select is active.
DS40044G-page 40
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-12:
BLOCK DIAGRAM OF RB4/PGM PIN
VDD
RBPU
P weak pull-up
Data Bus
WR PORTB
D
Q
CK
Q
VDD
Data Latch
WR TRISB
D
Q
CK
Q
RB4/PGM
VSS
TRIS Latch
RD TRISB
LVP (Configuration Bit)
RD PORTB
PGM input
TTL
input
buffer
Schmitt
Trigger
Q
D
EN
Q1
Set RBIF
From other
RB pins
Q
D
EN
Note:
Q3
The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.
© 2009 Microchip Technology Inc.
DS40044G-page 41
PIC16F627A/628A/648A
FIGURE 5-13:
BLOCK DIAGRAM OF RB5 PIN
VDD
RBPU
weak VDD
P pull-up
Data Bus
D
Q
CK
Q
RB5 pin
WR PORTB
Data Latch
VSS
WR TRISB
D
Q
CK
Q
TRIS Latch
TTL
input
buffer
RD TRISB
Q
D
RD PORTB
EN
Q1
Set RBIF
From other
RB pins
Q
D
EN
DS40044G-page 42
Q3
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-14:
BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN
VDD
RBPU
P weak pull-up
Data Bus
WR PORTB
D
Q
CK
Q
VDD
Data Latch
WR TRISB
D
Q
CK
Q
RB6/
T1OSO/
T1CKI/
PGC
pin
VSS
TRIS Latch
RD TRISB
T1OSCEN
TTL
input
buffer
RD PORTB
TMR1 Clock
From RB7
Schmitt
Trigger
TMR1 oscillator
Serial Programming Clock
Q
D
EN
Q1
Set RBIF
From other
RB pins
Q
D
EN
© 2009 Microchip Technology Inc.
Q3
DS40044G-page 43
PIC16F627A/628A/648A
FIGURE 5-15:
BLOCK DIAGRAM OF THE RB7/T1OSI/PGD PIN
VDD
RBPU
P weak pull-up
TMR1 oscillator
To RB6
VDD
Data Bus
WR PORTB
D
Q
CK
Q
RB7/T1OSI/
PGD pin
Data Latch
WR TRISB
D
Q
CK
Q
VSS
TRIS Latch
RD TRISB
T10SCEN
TTL
input
buffer
RD PORTB
Serial Programming Input
Schmitt
Trigger
Q
D
EN
Q1
Set RBIF
From other
RB pins
Q
D
EN
DS40044G-page 44
Q3
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 5-3:
PORTB FUNCTIONS
Name
Function Input Type
RB0/INT
RB1/RX/DT
Output
Type
RB0
TTL
CMOS
INT
ST
—
RB1
TTL
CMOS
Description
Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
External interrupt
Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
RX
ST
—
DT
ST
CMOS
RB2
TTL
CMOS
Bidirectional I/O port
TX
—
CMOS
USART Transmit Pin
CK
ST
CMOS
Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
RB3
TTL
CMOS
Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
CCP1
ST
CMOS
Capture/Compare/PWM/I/O
RB4
TTL
CMOS
Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
PGM
ST
—
Low-voltage programming input pin. When low-voltage
programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5
RB5
TTL
CMOS
Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
RB6/T1OSO/T1CKI/
PGC
RB6
TTL
CMOS
Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSO
—
XTAL
T1CKI
ST
—
Timer1 Clock Input
PGC
ST
—
ICSP™ Programming Clock
RB7
TTL
CMOS
T1OSI
XTAL
—
PGD
ST
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB7/T1OSI/PGD
Legend:
O = Output
— = Not used
TTL = TTL Input
TABLE 5-4:
CMOS
USART Receive Pin
Synchronous data I/O
Timer1 Oscillator Output
Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
Timer1 Oscillator Input
ICSP Data I/O
CMOS = CMOS Output
I
= Input
OD
= Open Drain Output
P = Power
ST = Schmitt Trigger Input
AN = Analog
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
Resets
06h, 106h
PORTB
RB7
RB6
RB5
RB4(1)
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
86h, 186h
TRISB
TRISB7
TRISB6
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
1111 1111
81h, 181h
OPTION
RBPU
INTEDG
Legend:
Note 1:
u = unchanged, x = unknown. Shaded cells are not used for PORTB.
LVP configuration bit sets RB4 functionality.
© 2009 Microchip Technology Inc.
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
DS40044G-page 45
PIC16F627A/628A/648A
5.3
I/O Programming Considerations
5.3.1
EXAMPLE 5-2:
BIDIRECTIONAL I/O PORTS
Any instruction that writes operates internally as a read
followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit 5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit 5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(e.g., bit 0) and is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the Input mode, no problem occurs. However,
if bit 0 is switched into Output mode later on, the
content of the data latch may now be unknown.
Reading a port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-2 shows the effect of two sequential readmodify-write instructions (ex., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-OR”, “wiredAND”). The resulting high output currents may damage
the chip.
FIGURE 5-16:
;Initial PORT settings:PORTB Inputs
;
PORTB Outputs
;PORTB have external pull-up and are
;not connected to other circuitry
;
;
PORT latchPORT Pins
---------- ---------BCF STATUS, RP0
;
BCF PORTB, 7
;01pp pppp 11pp pppp
BSF STATUS, RP0
;
BCF TRISB, 7
;10pp pppp 11pp pppp
BCF TRISB, 6
;10pp pppp 10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp pppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(High).
5.3.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-16). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction, which causes
that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into
the CPU rather than the new state. When in doubt, it
is better to separate these instructions with a NOP or
another instruction not accessing this I/O port.
SUCCESSIVE I/O OPERATION
Q1
PC
Instruction
fetched
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
Q2 Q3 Q4 Q1
PC
MOVWF PORTB
Write to PORTB
Q2 Q3 Q4
PC + 1
MOVF PORTB, W
Read to PORTB
Q1
Q2 Q3 Q4 Q1
PC + 2
NOP
Q2 Q3 Q4
PC + 3
NOP
Port pin
sampled here
TPD
Execute
MOVWF
PORTB
Note 1:
2:
Execute
MOVF
PORTB, W
Execute
NOP
This example shows write to PORTB followed by a read from PORTB.
Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle
to output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS40044G-page 46
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
6.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Read/write capabilities
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module. Additional information is available in the “PIC®
Mid-Range MCU Family Reference Manual” (DS33023).
Timer mode is selected by clearing the T0CS bit
(OPTION). In Timer mode, the TMR0 register value
will increment every instruction cycle (without
prescaler). If the TMR0 register is written to, the
increment is inhibited for the following two cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
this mode the TMR0 register value will increment either
on every rising or falling edge of pin RA4/T0CKI/CMP2.
The incrementing edge is determined by the source
edge (T0SE) control bit (OPTION). Clearing the
T0SE bit selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 6.2 “Using Timer0 with External Clock”.
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4,..., 1:256 are
selectable. Section 6.3 “Timer0 Prescaler” details
the operation of the prescaler.
6.1
6.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-1). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device. See Table 17-8.
Timer0 Interrupt
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON). The T0IF bit
(INTCON) must be cleared in software by the
Timer0 module interrupt service routine before reenabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut
off during Sleep.
© 2009 Microchip Technology Inc.
DS40044G-page 47
PIC16F627A/628A/648A
6.3
The PSA and PS bits (OPTION) determine
the prescaler assignment and prescale ratio.
Timer0 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. A prescaler assignment for the Timer0 module
means that there is no postscaler for the Watchdog
Timer, and vice-versa.
FIGURE 6-1:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler
is not readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT
Data Bus
FOSC/4
8
0
T0CKI
pin
SYNC
2
Cycles
1
1
0
T0SE
T0CS
0
Watchdog
Timer
1
Set flag bit T0IF
on Overflow
PSA
TMR1 Clock Source
TMR0 Reg
WDT Postscaler/
TMR0 Prescaler
8
PSA
8-to-1MUX
PS
WDT Enable bit
1
0
WDT
Time-out
PSA
Note:
DS40044G-page 48
T0SE, T0CS, PSA,. PS are bits in the Option Register.
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
6.3.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). Use the instruction sequences
shown in Example 6-1 when changing the prescaler
assignment from Timer0 to WDT, to avoid an
unintended device Reset.
EXAMPLE 6-1:
BCF
CLRWDT
CLRF
TMR0
BSF
MOVLW
STATUS, RP0
'00101111’b
MOVWF
OPTION_REG
CLRWDT
MOVLW
'00101xxx’b
MOVWF
OPTION_REG
BCF
STATUS, RP0
Address
01h, 101h
85h
Legend:
Note 1:
CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT
;Skip if already in
;Bank 0
;Clear WDT
;Clear TMR0 and
;Prescaler
;Bank 1
;These 3 lines
;(5, 6, 7)
;are required only
;if desired PS
;are
;000 or 001
;Set Postscaler to
;desired WDT rate
;Return to Bank 0
;Clear WDT and
;prescaler
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx’
MOVWF
BCF
OPTION_REG
STATUS, RP0
;Select TMR0, new
;prescale value and
;clock source
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
0Bh, 8Bh,
INTCON
10Bh, 18Bh
81h, 181h
EXAMPLE 6-2:
CHANGING PRESCALER
(TIMER0 → WDT)
STATUS, RP0
TABLE 6-1:
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
OPTION(2)
TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 Module Register
Value on
POR
Value on
All Other
Resets
xxxx xxxx uuuu uuuu
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used for Timer0.
Option is referred by OPTION_REG in MPLAB® IDE Software.
© 2009 Microchip Technology Inc.
DS40044G-page 49
PIC16F627A/628A/648A
7.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The Timer1 Interrupt, if
enabled, is generated on overflow of the TMR1 register
pair which latches the interrupt flag bit TMR1IF
(PIR1). This interrupt can be enabled/disabled by
setting/clearing the Timer1 interrupt enable bit TMR1IE
(PIE1).
Timer1 can operate in one of two modes:
• As a timer
• As a counter
In Timer mode, the TMR1 register pair value
increments every instruction cycle. In Counter mode, it
increments on every rising edge of the external clock
input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (Section 9.0
“Capture/Compare/PWM
(CCP)
Module”).
Register 7-1 shows the Timer1 control register.
For the PIC16F627A/628A/648A, when the Timer1
oscillator is enabled (T1OSCEN is set), the RB7/
T1OSI/PGD and RB6/T1OSO/T1CKI/PGC pins
become inputs. That is, the TRISB value is
ignored.
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON).
REGISTER 7-1:
T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
U-0
—
—
R/W-0
R/W-0
T1CKPS1 T1CKPS0
R/W-0
T1OSCEN
R/W-0
R/W-0
R/W-0
T1SYNC TMR1CS TMR1ON
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
T1CKPS: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off(1)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI/PGC (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:
DS40044G-page 50
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
7.1
7.2.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON) has no effect since the internal clock is
always in sync.
7.2
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the TMR1 register pair value increments on
every rising edge of clock input on pin RB7/T1OSI/PGD
when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI/
PGC when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple-counter.
In this configuration, during Sleep mode, the TMR1
register pair value will not increment even if the
external clock is present, since the synchronization
circuit is shut off. The prescaler however will continue
to increment.
FIGURE 7-1:
EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
When an external clock input is used for Timer1 in
Synchronized Counter mode, it must meet certain
requirements. The external clock requirement is due to
internal phase clock (TOSC) synchronization. Also,
there is a delay in the actual incrementing of the TMR1
register pair value after synchronization.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to Table 17-8 in
the Electrical Specifications Section, timing parameters
45, 46 and 47.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple-counter
type prescaler so that the prescaler output is symmetrical. In order for the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T1CKI to have a
period of at least 4 TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement on
T1CKI high and low time is that they do not violate the
minimum pulse width requirements of 10 ns). Refer to
the appropriate electrical specifications in Table 17-8,
parameters 45, 46 and 47.
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
TMR1H
Synchronized
0
TMR1
Clock Input
TMR1L
1
TMR1ON
T1SYNC
T1OSC
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
1
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS
Sleep Input
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
© 2009 Microchip Technology Inc.
DS40044G-page 51
PIC16F627A/628A/648A
7.3
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up the
processor. However, special precautions in software are
needed to read/write the timer (Section 7.3.2 “Reading
and Writing Timer1 in Asynchronous Counter
Mode”).
Note:
7.3.1
In Asynchronous Counter mode, Timer1
cannot be used as a time base for capture
or compare operations.
EXTERNAL CLOCK INPUT TIMING
WITH UNSYNCHRONIZED CLOCK
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high and low time requirements. Refer
to Table 17-8 in the Electrical Specifications Section,
timing parameters 45, 46 and 47.
7.3.2
EXAMPLE 7-1:
READING A 16-BIT FREERUNNING TIMER
; All interrupts are disabled
MOVF
TMR1H, W
;Read high byte
MOVWF
TMPH
;
MOVF
TMR1L, W
;Read low byte
MOVWF
TMPL
;
MOVF
TMR1H, W
;Read high byte
SUBWF
TMPH, W
;Sub 1st read with
;2nd read
BTFSC
STATUS,Z
;Is result = 0
GOTO
CONTINUE
;Good 16-bit read
;
; TMR1L may have rolled over between the
; read of the high and low bytes. Reading
; the high and low bytes now will read a good
; value.
;
MOVF
TMR1H, W
;Read high byte
MOVWF
TMPH
;
MOVF
TMR1L, W
;Read low byte
MOVWF
TMPL
;
; Re-enable the Interrupts (if required)
CONTINUE
;Continue with your
;code
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading the TMR1H or TMR1L register, while the timer
is running from an external asynchronous clock, will
produce a valid read (taken care of in hardware).
However, the user should keep in mind that reading the
16-bit timer in two 8-bit values itself poses certain
problems since the timer may overflow between the
reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Example 7-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
DS40044G-page 52
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
7.4
Timer1 Oscillator
7.5
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON). It will
continue to run during Sleep. It is primarily intended for
a 32.768 kHz watch crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M =
1011), this signal will reset Timer1.
C1
C2
32.768 kHz
15 pF
15 pF
Note:
Timer1 must be configured for either timer or
Synchronized Counter mode to take advantage of this
feature. If Timer1 is running in Asynchronous Counter
mode, this Reset operation may not work.
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Freq
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Note:
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 7-1:
Resetting Timer1 Using a CCP
Trigger Output
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
These values are for design guidance only.
Consult Application Note AN826 “Crystal
Oscillator Basics and Crystal Selection for
rfPIC® and PIC® Devices” (DS00826) for
further information on Crystal/Capacitor
Selection.
In this mode of operation, the CCPRxH:CCPRxL
register pair effectively becomes the period register for
Timer1.
7.6
Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on
a POR or any other Reset except by the CCP1 special
event triggers (see Section 9.2.4 “Special Event
Trigger”).
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
10h
T1CON
--00 0000
--uu uuuu
Legend:
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.
© 2009 Microchip Technology Inc.
DS40044G-page 53
PIC16F627A/628A/648A
8.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
Reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS
(T2CON).
The Timer2 module has an 8-bit period register PR2.
The TMR2 register value increments from 00h until it
matches the PR2 register value and then resets to 00h
on the next increment cycle. The PR2 register is a
readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of Timer2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a Timer2 interrupt (latched in flag bit
TMR2IF, (PIR1)).
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON) to minimize power consumption.
8.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
The TMR2 register is not cleared when T2CON is
written.
8.2
TMR2 Output
The TMR2 output (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 8-1:
Sets flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
output
Reset
Register 8-1 shows the Timer2 control register.
Postscaler
1:1 to 1:16
4
EQ
TMR2 Reg
Comparator
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
T2CKPS
PR2 Reg
TOUTPS
DS40044G-page 54
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
REGISTER 8-1:
T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h)
U-0
R/W-0
—
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1
R/W-0
TOUTPS0
R/W-0
R/W-0
TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale Value
0001 = 1:2 Postscale Value
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS: Timer2 Clock Prescale Select bits
00 = 1:1 Prescaler Value
01 = 1:4 Prescaler Value
1x = 1:16 Prescaler Value
Legend:
TABLE 8-1:
Address
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
POR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000 0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000 0000 -000
11h
TMR2
12h
T2CON
92h
PR2
Legend:
Name
Timer2 Module’s Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
Timer2 Period Register
0000 0000 0000 0000
T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.
© 2009 Microchip Technology Inc.
DS40044G-page 55
PIC16F627A/628A/648A
NOTES:
DS40044G-page 56
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
9.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
TABLE 9-1:
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit Capture
register, as a 16-bit Compare register or as a PWM
master/slave Duty Cycle register. Table 9-1 shows the
timer resources of the CCP module modes.
CCP MODE – TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). The CCP1CON register
controls the operation of CCP1. All are readable and
writable.
Additional information on the CCP module is available
in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023).
REGISTER 9-1:
CCP1CON – CCP OPERATION REGISTER (ADDRESS: 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3
R/W-0
R/W-0
R/W-0
CCP1M2 CCP1M1 CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode
Unused
Compare Mode
Unused
PWM Mode
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCP1M: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 57
PIC16F627A/628A/648A
9.1
9.1.4
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M
(CCP1CON). When a capture is made, the
interrupt request flag bit CCP1IF (PIR1) is set. It
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value will be lost.
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the RB3/CCP1 pin should be configured as an input by setting the TRISB bit.
Note:
If the RB3/CCP1 is configured as an
output, a write to the port can cause a
capture condition.
FIGURE 9-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
³ 1, 4, 16
Set flag bit CCP1IF
(PIR1)
RB3/CCP1
pin
CCPR1H
and
edge detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
CCP1CON
Q’s
9.1.2
9.1.3
There are four prescaler settings, specified by bits
CCP1M. Whenever the CCP module is turned
off, or the CCP module is not in Capture mode, the
prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will not
be cleared, therefore the first capture may be from a
non-zero
prescaler.
Example 9-1
shows
the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 9-1:
CLRF
MOVLW
MOVWF
9.2
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
DS40044G-page 58
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M (CCP1CON). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
CCP PRESCALER
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Set flag bit CCP1IF
(PIR1)
CCPR1H CCPR1L
Q S Output
Logic
match
RB3/CCP1
R
pin
TRISB
Output Enable CCP1CON
Mode Select
Note:
Comparator
TMR1H
TMR1L
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1).
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
9.2.1
CCP PIN CONFIGURATION
9.2.4
The user must configure the RB3/CCP1 pin as an
output by clearing the TRISB bit.
Note:
9.2.2
In this mode (CCP1M=1011), an internal hardware trigger is generated, which may be used to initiate
an action. See Register 9-1.
Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to
the default low level. This is not the data
latch.
The special event trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and CCPR1H, CCPR1L register
pair. The TMR1H, TMR1L register pair is not reset until
the next rising edge of the TMR1 clock. This allows the
CCPR1 register pair to effectively be a 16-bit programmable period register for Timer1. The special event
trigger output also starts an A/D conversion provided
that the A/D module is enabled.
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
Note:
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
TABLE 9-2:
Address
SPECIAL EVENT TRIGGER
Removing the match condition by changing the contents of the CCPR1H, CCPR1L
register pair between the clock edge that
generates the special event trigger and
the clock edge that generates the TMR1
Reset will preclude the Reset from
occuring.
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name
Value on
POR
Value on
all other
Resets
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
PIR1
EEIF CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF 0000 -000 0000 -000
8Ch
PIE1
EEIE CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE 0000 -000 0000 -000
86h, 186h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
—
—
0000 000x 0000 000u
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
Legend:
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.
© 2009 Microchip Technology Inc.
DS40044G-page 59
PIC16F627A/628A/648A
9.3
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB bit must be cleared to make the CCP1
pin an output.
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(frequency = 1/period).
FIGURE 9-4:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Note:
Period
Duty Cycle
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
TMR2 = PR2
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3 “SetUp for PWM Operation”.
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty cycle registers
PWM OUTPUT
TMR2 = Duty Cycle
TMR2 = PR2
9.3.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
CCP1CON
CCPR1L
PWM period = [ ( PR2 ) + 1 ] ⋅ 4 ⋅ Tosc ⋅ TMR2 prescale
value
PWM frequency is defined as 1/[PWM period].
CCPR1H (Slave)
R
Comparator
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Q
RB3/CCP1
(1)
TMR2
S
TRISB
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note
1:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time base.
DS40044G-page 60
The Timer2 postscaler (see Section 8.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
9.3.2
PWM DUTY CYCLE
Maximum PWM resolution (bits) for a given PWM
frequency:
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
Fosc
log ⎛⎝ -------------------------------------------------------------⎞⎠
PWM
F PWM × TMR2 Prescaler
Resolution = --------------------------------------------------------------------------- bits
log(2)
If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
cleared.
Note:
PWM duty cycle =
(CCPR1L:CCP1CON) ⋅ Tosc ⋅ TMR2 prescale
value
For an example PWM period and duty cycle
calculation, see the PIC® Mid-Range Reference Manual (DS33023).
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
9.3.3
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
2.
When the CCPR1H and 2-bit latch match TMR2
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
TABLE 9-3:
SET-UP FOR PWM OPERATION
3.
4.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISB bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 9-4:
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.5
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
86h, 186h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
11h
TMR2
Timer2 Module’s Register
0000 0000
0000 0000
92h
PR2
Timer2 Module’s Period Register
1111 1111
1111 1111
12h
T2CON
-000 0000
uuuu uuuu
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
--00 0000
--00 0000
Legend:
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
—
—
CCP1X
CCP1Y
CCP1M3
TMR2ON T2CKPS1 T2CKPS0
CCP1M2
CCP1M1
CCP1M0
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.
© 2009 Microchip Technology Inc.
DS40044G-page 61
PIC16F627A/628A/648A
NOTES:
DS40044G-page 62
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
10.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The on-chip
Voltage Reference (Section 11.0 “Voltage Reference
Module”) can also be an input to the comparators.
REGISTER 10-1:
The CMCON register, shown in Register 10-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 10-1.
CMCON – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 01Fh)
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 7
bit 0
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 Output inverted
0 = C2 Output not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM: = 001
Then:
1 = C1 VIN- connects to RA3
0 = C1 VIN- connects to RA0
When CM = 010
Then:
1 = C1 VIN- connects to RA3
C2 VIN- connects to RA2
0 = C1 VIN- connects to RA0
C2 VIN- connects to RA1
bit 2-0
CM: Comparator Mode bits
Figure 10-1 shows the comparator modes and CM bit settings
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 63
PIC16F627A/628A/648A
10.1
If the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
change delay shown in Table 17-2.
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 10-1 shows the eight possible
modes. The TRISA register controls the data direction
of the comparator pins for each mode.
Note 1: Comparator interrupts should be disabled
during a Comparator mode change,
otherwise a false interrupt may occur.
2: Comparators can have an inverted
output. See Figure 10-1.
FIGURE 10-1:
COMPARATOR I/O OPERATING MODES
Comparators Off
CM = 111
Comparators Reset (POR Default Value)
CM = 000
RA0/AN0
A
VIN-
RA3/AN3/CMP1
A
VIN+
RA1/AN1
A
VIN-
RA2/AN2/VREF
A
VIN+
C1
Off (Read as ‘0’)
RA0/AN0
D
VIN-
RA3/AN3/CMP1
D
VIN+
D
VIN-
D
VIN+
RA1/AN1
C2
Off (Read as ‘0’)
RA2/AN2/VREF
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
VSS
Four Inputs Multiplexed to Two Comparators
CM = 010
Two Independent Comparators
CM = 100
A
RA0/AN0
VIN+
A
RA3/AN3/CMP1
RA0/AN0
VIN-
RA1/AN1
A
VIN-
RA2/AN2/VREF
A
VIN+
C1
C2
C1VOUT
A
CIS = 0
CIS = 1
RA3/AN3/CMP1 A
RA1/AN1
A
RA2/AN2/VREF
A
CIS = 0
CIS = 1
C2VOUT
VINVIN+
C1
C1VOUT
C2
C2VOUT
VINVIN+
From VREF
Module
Two Common Reference Comparators with Outputs
CM = 110
Two Common Reference Comparators
CM = 011
RA0/AN0
A
D
VIN+
RA1/AN1
A
VIN-
RA2/AN2/VREF
A
VIN+
RA3/AN3/CMP1
A
VIN-
RA3/AN3/CMP1
D
VIN+
RA1/AN1
A
VIN-
RA2/AN2/VREF
A
VIN+
RA0/AN0
VINC1
C2
C1VOUT
C2VOUT
C1
C1VOUT
C2
C2VOUT
RA4/T0CKI/CMP2 Open Drain
Three Inputs Multiplexed to Two Comparators
CM = 001
One Independent Comparator
CM = 101
RA0/AN0
D
RA3/AN3/CMP1 D
VINVIN+
C1
Off (Read as ‘0’)
RA0/AN0
A
RA3/AN3/CMP1 A
CIS = 0
CIS = 1
VINVIN+
C1
C1VOUT
C2
C2VOUT
VSS
RA1/AN1
RA2/AN2/VREF
A
VIN-
A
VIN+
C2
A = Analog Input, port reads zeros always.
DS40044G-page 64
C2VOUT
RA1/AN1
A
VIN-
RA2/AN2/VREF
A
VIN+
D = Digital Input.
CIS (CMCON) is the Comparator Input Switch.
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
The code example in Example 10-1 depicts the steps
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 10-1:
BCF
BSF
BSF
BCF
BSF
BSF
10.2
0X20
;Init flag register
;Init PORTA
;Load comparator bits
;Mask comparator bits
;Store bits in flag register
;Init comparator mode
;CM = 011
;Select Bank1
;Initialize data direction
;Set RA as inputs
;RA as outputs
;TRISA always read ‘0’
STATUS,RP0 ;Select Bank 0
DELAY10
;10Μs delay
CMCON,F
;Read CMCON to end change
;condition
PIR1,CMIF ;Clear pending interrupts
STATUS,RP0 ;Select Bank 1
PIE1,CMIE ;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
Comparator Operation
A single comparator is shown in Figure 10-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 10-2 represent
the uncertainty due to input offsets and response time.
See Table 17-2 for Common Mode voltage.
10.3
SINGLE COMPARATOR
VIN+
+
VIN-
–
Result
INITIALIZING
COMPARATOR MODULE
FLAG_REG
EQU
CLRF
FLAG_REG
CLRF
PORTA
MOVF
CMCON, W
ANDLW
0xC0
IORWF
FLAG_REG,F
MOVLW
0x03
MOVWF
CMCON
BSF
STATUS,RP0
MOVLW
0x07
MOVWF
TRISA
BCF
CALL
MOVF
FIGURE 10-2:
Comparator Reference
An external or internal reference signal may be used
depending on the comparator Operating mode. The
analog signal that is present at VIN- is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 10-2).
© 2009 Microchip Technology Inc.
VINVIN+
Result
10.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
Comparator module can be configured to have the
comparators operate from the same or different
reference sources. However, threshold detector
applications may require the same reference. The
reference signal must be between VSS and VDD, and
can be applied to either pin of the comparator(s).
10.3.2
INTERNAL REFERENCE SIGNAL
The Comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 11.0 “Voltage Reference
Module”, contains a detailed description of the Voltage
Reference module that provides this signal. The
internal reference signal is used when the comparators
are in mode CM = 010 (Figure 10-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
10.4
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is to have a valid level. If the internal
reference is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (Table 17-2, page 142).
DS40044G-page 65
PIC16F627A/628A/648A
10.5
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM = 110 or 001, multiplexors
in the output path of the RA3 and RA4/T0CK1/CMP2
pins will switch and the output of each pin will be the
unsynchronized output of the comparator. The
uncertainty of each of the comparators is related to the
input offset voltage and the response time given in the
specifications. Figure 10-3 shows the comparator output
block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3/AN3/CMP1 and RA4/T0CK1/
CMP2 pins while in this mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is
specified.
FIGURE 10-3:
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
CnINV
To RA3/AN3/CMP1 or
RA4/T0CK1/CMP2 pin
To Data Bus
CMCON
CnVOUT
Q
D
Q3
EN
RD CMCON
Q
Set CMIF bit
D
EN
CL
From other Comparator
DS40044G-page 66
Q1
Reset
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
10.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that has occurred. The
CMIF bit, PIR1, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE1) and the PEIE bit
(INTCON) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1)
interrupt flag may not get set.
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Any write or read of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
© 2009 Microchip Technology Inc.
10.7
Comparator Operation During
Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered-up, higher Sleep
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in Sleep mode, turn off the
comparators, CM = 111, before entering Sleep. If
the device wakes up from Sleep, the contents of the
CMCON register are not affected.
10.8
Effects of a Reset
A device Reset forces the CMCON register to its Reset
state. This forces the Comparator module to be in the
comparator Reset mode, CM = 000. This ensures
that all potential inputs are analog inputs. Device current
is minimized when analog inputs are present at Reset
time. The comparators will be powered-down during the
Reset interval.
10.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 10-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
DS40044G-page 67
PIC16F627A/628A/648A
FIGURE 10-4:
ANALOG INPUT MODE
VDD
VT = 0.6V
RS < 10 K
AIN
CPIN
5 pF
VA
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN
VT
ILEAKAGE
RIC
RS
VA
TABLE 10-1:
Address
1Fh
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the Pin
Interconnect Resistance
Source Impedance
Analog Voltage
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
POR
Value on
All Other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON
C2OUT
C1OUT
C2INV
C1NV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Bh, 8Bh,
INTCON
10Bh, 18Bh
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
85h
Legend:
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3
TRISA2
TRISA1
TRISA0
1111 1111 1111 1111
x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’
DS40044G-page 68
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
11.0
The equations used to calculate the output of the
Voltage Reference module are as follows:
VOLTAGE REFERENCE
MODULE
if VRR = 1:
The Voltage Reference module consists of a 16-tap
resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down
function to conserve power when the reference is not
being used. The VRCON register controls the operation of the reference as shown in Figure 11-1. The
block diagram is given in Figure 11-1.
11.1
VR
VREF = ----------------------- × VDD
24
if VRR = 0:
VR
1
VREF = ⎛ VDD × ---⎞ + ----------------------- × VDD
⎝
4⎠
32
The setting time of the Voltage Reference module must
be considered when changing the VREF output
(Table 17-3). Example 11-1 demonstrates how voltage
reference is configured for an output voltage of 1.25V
with VDD = 5.0V.
Voltage Reference Configuration
The Voltage Reference module can output 16 distinct
voltage levels for each range.
REGISTER 11-1:
VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Fh)
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
VREN: VREF Enable bit
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6
VROE: VREF Output Enable bit
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5
VRR: VREF Range Selection bit
1 = Low range
0 = High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR: VREF Value Selection bits 0 ≤ VR ≤ 15
When VRR = 1: VREF = (VR/ 24) * VDD
When VRR = 0: VREF = 1/4 * VDD + (VR/ 32) * VDD
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 69
PIC16F627A/628A/648A
FIGURE 11-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
VREN
16 Stages
8R
R
R
R
R
8R
VSS
VREF
Note:
11.2
0x02
CMCON
STATUS,RP0
0x07
TRISA
0xA6
VRCON
STATUS,RP0
DELAY10
VOLTAGE REFERENCE
CONFIGURATION
;4 Inputs Muxed
;to 2 comps.
;go to Bank 1
;RA3-RA0 are
;outputs
;enable VREF
;low range set VR=6
;go to Bank 0
;10μs delay
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 11-1) keep VREF from approaching VSS or VDD.
The Voltage Reference module is VDD derived and
therefore, the VREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Voltage Reference module can be found in Table 17-3.
11.3
VSS
VR3
(From VRCON)
VR0
R is defined in Table 17-3.
EXAMPLE 11-1:
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
16-1 Analog Mux
VRR
11.5
Connection Considerations
The Voltage Reference module operates independently
of the Comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA bit is set and the VROE bit, VRCON, is
set. Enabling the Voltage Reference module output onto
the RA2 pin with an input signal present will increase
current consumption. Connecting RA2 as a digital output
with VREF enabled will also increase current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference module output for external connections to VREF. Figure 11-2 shows an example buffering
technique.
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time out, the contents of
the VRCON register are not affected. To minimize
current consumption in Sleep mode, the Voltage
Reference module should be disabled.
11.4
Effects of a Reset
A device Reset disables the Voltage Reference module
by clearing bit VREN (VRCON). This Reset also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON) and selects the high voltage
range by clearing bit VRR (VRCON). The VREF
value select bits, VRCON, are also cleared.
DS40044G-page 70
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 11-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
R(1)
VREF
Op Amp
RA2
+
Module
VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the voltage reference configuration VRCON and VRCON.
TABLE 11-1:
Address
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR
Value On
All Other
Resets
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000 000- 0000
1Fh
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
85h
TRISA
TRISA7 TRISA6
TRISA5
TRISA4
TRISA3
Legend:
TRISA2 TRISA1
TRISA0 1111 1111 1111 1111
- = Unimplemented, read as ‘0’.
© 2009 Microchip Technology Inc.
DS40044G-page 71
PIC16F627A/628A/648A
NOTES:
DS40044G-page 72
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
12.0
The USART can be configured in the following modes:
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) is also known as a Serial
Communications Interface (SCI). The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices such as A/D
or D/A integrated circuits, Serial EEPROMs, etc.
REGISTER 12-1:
Bit SPEN (RCSTA) and bits TRISB have to be
set in order to configure pins RB2/TX/CK and RB1/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
Register 12-1 shows the Transmit Status and Control
Register (TXSTA) and Register 12-2 shows the
Receive Status and Control Register (RCSTA).
TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
U-0
R/W-0
R-1
R/W-0
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as ‘0’
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of transmit data. Can be parity bit.
Note 1: SREN/CREN overrides TXEN in SYNC mode.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 73
PIC16F627A/628A/648A
REGISTER 12-2:
RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB are set)
1 = Serial port enabled
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR
is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of received data (Can be parity bit)
Legend:
DS40044G-page 74
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
12.1
EQUATION 12-1:
USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit baud rate generator. The SPBRG register
controls the period of a free running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 12-1 shows the formula for
computation of the baud rate for different USART
modes, which only apply in Master mode (internal
clock).
CALCULATING BAUD
RATE ERROR
Fosc
Desired Baud Rate = ----------------------64 ( x + 1 )
16000000
9600 = -----------------------64 ( x + 1 )
x = 25.042
16000000
Calculated Baud Rate = --------------------------- = 9615
64 ( 25 + 1 )
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
(Calculated Baud Rate - Desired Baud Rate)
Error = ----------------------------------------------------------------------------------------------------------Desired Baud Rate
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
9615 – 9600
= ------------------------------ = 0.16%
9600
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
SYNC = 0
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared) and ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
The data on the RB1/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 12-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
(Asynchronous) Baud Rate = FOSC/(64(X+1))
Baud Rate = FOSC/(16(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
NA
1
Legend:
X = value in SPBRG (0 to 255)
TABLE 12-2:
Address
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other Resets
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x
0000 000x
99h
SPBRG
0000 0000
0000 0000
Legend:
Baud Rate Generator Register
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the BRG.
© 2009 Microchip Technology Inc.
DS40044G-page 75
PIC16F627A/628A/648A
TABLE 12-3:
BAUD RATES FOR SYNCHRONOUS MODE
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
1.2
NA
2.4
NA
—
—
NA
—
—
NA
—
—
NA
—
—
—
—
NA
—
9.6
NA
—
—
—
NA
—
—
9.766
+1.73%
255
19.2
19.53
+1.73%
255
19.23
+0.16%
207
19.23
+0.16%
129
76.8
76.92
96
96.15
+0.16%
64
76.92
+0.16%
51
75.76
-1.36%
32
+0.16%
51
95.24
-0.79%
41
96.15
+0.16%
300
25
294.1
-1.96
16
307.69
+2.56%
12
312.5
+4.17%
500
7
500
0
9
500
0
7
500
0
4
HIGH
5000
—
0
4000
—
0
2500
—
0
LOW
19.53
—
255
15.625
—
255
9.766
—
255
5.0688 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
FOSC = 20 MHz
10 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
NA
—
—
NA
—
—
NA
—
—
1.2
NA
—
—
NA
—
—
NA
—
—
2.4
NA
—
—
NA
—
—
NA
—
—
BAUD
RATE (K)
FOSC = 7.15909 MHz
16 MHz
4 MHz
9.6
9.622
+0.23%
185
9.6
0
131
9.615
+0.16%
103
19.2
19.24
+0.23%
92
19.2
0
65
19.231
+0.16%
51
76.8
77.82
+1.32
22
79.2
+3.13%
15
75.923
+0.16%
12
96
94.20
-1.88
18
97.48
+1.54%
12
1000
+4.17%
9
300
298.3
-0.57
5
316.8
5.60%
3
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
1789.8
—
0
1267
—
0
100
—
0
LOW
6.991
—
255
4.950
—
255
3.906
—
255
32.768 kHz
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
FOSC = 3.579545 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
1 MHz
KBAUD
0.3
NA
—
—
NA
—
—
0.303
+1.14%
26
1.2
NA
—
—
1.202
+0.16%
207
1.170
-2.48%
6
2.4
NA
—
—
2.404
+0.16%
103
NA
—
—
9.6
9.622
+0.23%
92
9.615
+0.16%
25
NA
—
—
19.2
19.04
-0.83%
46
19.24
+0.16%
12
NA
—
—
76.8
74.57
-2.90%
11
83.34
+8.51%
2
NA
—
—
96
99.43
+3.57%
8
NA
—
—
NA
—
—
300
298.3
0.57%
2
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
894.9
—
0
250
—
0
8.192
—
0
LOW
3.496
—
255
0.9766
—
255
0.032
—
255
DS40044G-page 76
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 12-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
NA
—
1.2
1.221
2.4
2.404
9.6
19.2
BAUD
RATE (K)
FOSC = 20 MHz
16 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
—
NA
—
+1.73%
255
1.202
+0.16%
129
2.404
9.469
-1.36%
32
19.53
+1.73%
10 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
—
NA
—
—
+0.16%
207
1.202
+0.16%
129
+0.16%
103
2.404
+0.16%
64
9.615
+0.16%
25
9.766
+1.73%
15
15
19.23
+0.16%
12
19.53
+1.73V
7
76.8
78.13
+1.73%
3
83.33
+8.51%
2
78.13
+1.73%
1
96
104.2
+8.51%
2
NA
—
—
NA
—
—
300
312.5
+4.17%
0
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
312.5
—
0
250
—
0
156.3
—
0
LOW
1.221
—
255
0.977
—
255
0.6104
—
255
SPBRG
value
(decimal)
5.0688 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
FOSC = 7.15909 MHz
KBAUD
ERROR
4 MHz
KBAUD
0.3
NA
—
—
0.31
+3.13%
255
0.3005
-0.17%
207
1.2
1.203
+0.23%
92
1.2
0
65
1.202
+1.67%
51
2.4
2.380
-0.83%
46
2.4
0
32
2.404
+1.67%
25
9.6
9.322
-2.90%
11
9.9
+3.13%
7
NA
—
—
19.2
18.64
-2.90%
5
19.8
+3.13%
3
NA
—
—
76.8
NA
—
—
79.2
+3.13%
0
NA
—
—
96
NA
—
—
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
NA
—
—
500
NA
—
—
NA
—
—
NA
—
—
HIGH
111.9
—
0
79.2
—
0
62.500
—
0
LOW
0.437
—
255
0.3094
—
255
3.906
—
255
32.768 kHz
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
0.3
0.301
+0.23%
185
0.300
+0.16%
51
0.256
-14.67%
1
1.2
1.190
-0.83%
46
1.202
+0.16%
12
NA
—
—
2.4
2.432
+1.32%
22
2.232
-6.99%
6
NA
—
—
9.6
9.322
-2.90%
5
NA
—
—
NA
—
—
19.2
18.64
-2.90%
2
NA
—
—
NA
—
—
76.8
NA
—
—
NA
—
—
NA
—
—
96
NA
—
—
NA
—
—
NA
—
—
300
NA
—
—
NA
—
—
NA
—
—
—
BAUD
RATE (K)
FOSC = 3.579545 MHz
1 MHz
500
NA
—
—
NA
—
—
NA
—
HIGH
55.93
—
0
15.63
—
0
0.512
—
0
LOW
0.2185
—
255
0.0610
—
255
0.0020
—
255
© 2009 Microchip Technology Inc.
DS40044G-page 77
PIC16F627A/628A/648A
TABLE 12-5:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
KBAUD
ERROR
SPBRG
value
(decimal)
9.615
+0.16%
19200
19.230
38400
37.878
BAUD
RATE (K)
9600
FOSC = 20 MHz
16 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
129
9.615
+0.16%
103
+0.16%
64
19.230
+0.16%
-1.36%
32
38.461
+0.16%
10 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
9.615
+0.16%
64
51
18.939
-1.36%
32
25
39.062
+1.7%
15
57600
56.818
-1.36%
21
58.823
+2.12%
16
56.818
-1.36%
10
115200
113.636
-1.36%
10
111.111
-3.55%
8
125
+8.51%
4
250000
250
0
4
250
0
3
NA
—
—
625000
625
0
1
NA
—
—
625
0
0
1250000
1250
0
0
NA
—
—
NA
—
—
5.068 MHz
ERROR
SPBRG
value
(decimal)
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
FOSC = 7.16 MHz
KBAUD
KBAUD
4 MHz
9600
9.520
-0.83%
46
9598.485
0.016%
32
9615.385
0.160%
25
19200
19.454
+1.32%
22
18632.35
-2.956%
16
19230.77
0.160%
12
38400
37.286
-2.90%
11
39593.75
3.109%
7
35714.29
-6.994%
6
57600
55.930
-2.90%
7
52791.67
-8.348%
5
62500
8.507%
3
115200
111.860
-2.90%
3
105583.3
-8.348%
2
125000
8.507%
1
250000
NA
—
—
316750
26.700%
0
250000
0.000%
0
625000
NA
—
—
NA
—
—
NA
—
—
1250000
NA
—
—
NA
—
—
NA
—
—
32.768 kHz
KBAUD
ERROR
SPBRG
value
(decimal)
ERROR
SPBRG
value
(decimal)
BAUD
RATE (K)
FOSC = 3.579 MHz
KBAUD
ERROR
SPBRG
value
(decimal)
1 MHz
KBAUD
9600
9725.543
1.308%
22
8.928
-6.994%
6
NA
NA
NA
19200
18640.63
-2.913%
11
20833.3
8.507%
2
NA
NA
NA
38400
37281.25
-2.913%
5
31250
-18.620%
1
NA
NA
NA
57600
55921.88
-2.913%
3
62500
+8.507
0
NA
NA
NA
115200
111243.8
-2.913%
1
NA
—
—
NA
NA
NA
250000
223687.5
-10.525%
0
NA
—
—
NA
NA
NA
625000
NA
—
—
NA
—
—
NA
NA
NA
1250000
NA
—
—
NA
—
—
NA
NA
NA
DS40044G-page 78
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
12.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-tozero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8-bit. A dedicated 8-bit baud rate generator is used to
derive baud rate frequencies from the oscillator. The
USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The baud rate generator produces a clock either
x16 or x64 of the bit shift rate, depending on bit BRGH
(TXSTA). Parity is not supported by the hardware,
but can be implemented in software (and stored as the
ninth data bit). Asynchronous mode is stopped during
Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA).
The USART Asynchronous module consists of the
following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
12.2.1
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 12-1). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate
transfer to TSR resulting in an empty TXREG. A backto-back transfer is thus possible (Figure 12-3). Clearing
enable bit TXEN during a transmission will cause the
transmission to be aborted and will reset the
transmitter. As a result the RB2/TX/CK pin will revert to
high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA) should be set and the ninth bit should be
written to TX9D (TXSTA). The ninth bit must be
written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG
register can result in an immediate transfer of the data
to the TSR register (if the TSR is empty). In such a
case, an incorrect ninth data bit may be loaded in the
TSR register.
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the Stop bit has been
transmitted from the previous load. As soon as the Stop
bit is transmitted, the TSR is loaded with new data from
the TXREG register (if available). Once the TXREG
register transfers the data to the TSR register (occurs
in one TCY), the TXREG register is empty and flag bit
TXIF (PIR1) is set. This interrupt can be enabled/
disabled by setting/clearing enable bit TXIE
( PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicated the
status of the TXREG register, another bit TRMT
(TXSTA) shows the status of the TSR register.
Status bit TRMT is a read-only bit which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
© 2009 Microchip Technology Inc.
DS40044G-page 79
PIC16F627A/628A/648A
FIGURE 12-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
(8)
LSb
0
² ² ²
Pin Buffer
and Control
TSR register
RB2/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
TX9
Baud Rate Generator
TX9D
Follow these steps when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
TRISB and TRISB should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
FIGURE 12-2:
Write to TXREG
BRG output
(shift clock)
RB2/TX/CK (pin)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit
DS40044G-page 80
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
bit 0
Word 1
Transmit Shift Reg.
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 12-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
Word 2
Start bit
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
bit 0
bit 1
Word 1
bit 7/8
Word 1
Transmit Shift Reg.
Start bit
Word 2
Stop bit
bit 0
Word 2
Transmit Shift Reg.
.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 12-6:
Address
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 000x
0000 000x
19h
TXREG USART Transmit Data Register
0000 0000
0000 0000
0000 -000
0000 -000
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
99h
SPBRG Baud Rate Generator Register
8Ch
Legend:
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented locations read as ‘0’.
Shaded cells are not used for Asynchronous Transmission.
© 2009 Microchip Technology Inc.
DS40044G-page 81
PIC16F627A/628A/648A
12.2.2
USART ASYNCHRONOUS
RECEIVER
double buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
shifting to the RSR register. On the detection of the
Stop bit of the third byte, if the RCREG register is still
full, then overrun error bit OERR (RCSTA) will be
set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhibited, so it is essential to clear error bit OERR if it is set.
Framing error bit FERR (RCSTA) is set if a Stop bit
is detected as clear. Bit FERR and the 9th receive bit
are buffered the same way as the receive data. Reading the RCREG, will load bits RX9D and FERR with
new values, therefore it is essential for the user to read
the RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
The receiver block diagram is shown in Figure 12-4.
The data is received on the RB1/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter
operates at the bit rate or at FOSC.
When Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA).
The heart of the receiver is the Receive (serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read-only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
FIGURE 12-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
÷ 64
or
÷ 16
Baud Rate Generator
FERR
OERR
CREN
RSR register
MSb
Stop (8)
7
• • •
1
LSb
0 Start
RB1/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
ADEN
Enable
Load of
RX9
ADEN
RSR
Receive
Buffer
8
RX9D
RCREG register
RX9D
RCREG register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
DS40044G-page 82
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 12-5:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit
RB1/RX/DT (Pin)
bit 0
bit 1
bit 8
Stop
bit
Start
bit
bit 0
bit 8
Stop
bit
RCV Shift Reg
RCV Buffer Reg
bit 8 = 0, Data Byte
bit 8 = 1, Address Byte
Read RCV
Buffer Reg
RCREG
Word 1
RCREG
RCIF
(interrupt flag)
ADEN = 1
(Address Match
Enable)
Note:
‘1’
‘1’
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and bit 8 = 0.
FIGURE 12-6:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit
RB1/RX/DT (pin)
bit 0
bit 1
bit 8
Stop
bit
Start
bit
bit 0
bit 8
Stop
bit
RCV Shift Reg
RCV Buffer Reg
bit 8 = 1, Address Byte
Read RCV
Buffer Reg
RCREG
Word 1
RCREG
bit 8 = 0, Data Byte
RCIF
(Interrupt Flag)
ADEN = 1
(Address Match
Enable)
Note:
‘1’
‘1’
This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0.
FIGURE 12-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
RB1/RX/DT (pin)
Start
bit
bit 0
RCV Shift
Reg
RCV Buffer Reg
Read RCV
Buffer Reg
RCREG
bit 1
bit 8
bit 8 = 1, Address Byte
Stop
bit
Start
bit
Word 1
RCREG
bit 0
bit 8
bit 8 = 0, Data Byte
Stop
bit
Word 2
RCREG
RCIF
(Interrupt Flag)
ADEN
(Address Match
Enable)
Note:
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.
© 2009 Microchip Technology Inc.
DS40044G-page 83
PIC16F627A/628A/648A
Follow these steps when setting up an Asynchronous
Reception:
1.
TRISB and TRISB should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section 12.1 “USART Baud
Rate Generator (BRG)”).
3. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. Enable the reception by setting bit CREN.
7. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If an OERR error occurred, clear the error by
clearing enable bit CREN.
TABLE 12-7:
Address
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
1Ah
RCREG USART Receive Data Register
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
SPBRG Baud Rate Generator Register
Legend:
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
DS40044G-page 84
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
12.3
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = 1). When ADEN is
disabled (= 0), all data bytes are received and the 9th
bit can be used as the parity bit.
USART Address Detect Function
12.3.1
USART 9-BIT RECEIVER WITH
ADDRESS DETECT
The receive block diagram is shown in Figure 12-4.
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a
special provision for multiprocessor communication.
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA) along with the RX9 bit. The
port is now programmed such that when the last bit is
received, the contents of the Receive Shift Register
(RSR) are transferred to the receive buffer, the ninth bit
of the RSR (RSR) is transferred to RX9D, and the
receive interrupt is set if and only if RSR = 1. This
feature can be used in a multiprocessor system as
follows:
Reception is
(RCSTA).
12.3.1.1
bit
CREN
Setting up 9-bit mode with Address
Detect
TRISB and TRISB should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
3. Enable asynchronous communication by setting
or clearing bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
RCIE.
5. Set bit RX9 to enable 9-bit reception.
6. Set ADEN to enable address detect.
7. Enable the reception by setting enable bit CREN
or SREN.
8. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
9. Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
10. If an OERR error occurred, clear the error by
clearing enable bit CREN if it was already set.
11. If the device has been addressed (RSR = 1
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN
1Ah
RCREG USART Receive Data Register
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
SPBRG Baud Rate Generator Register
Legend:
setting
1.
When ADEN is enabled (= 1), all data bytes are
ignored. Following the Stop bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
Address
by
Follow these steps when setting up Asynchronous
Reception with Address Detect Enabled:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR) to a ‘1’
(instead of a ‘0’ for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling
multiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
TABLE 12-8:
enabled
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous
reception.
© 2009 Microchip Technology Inc.
DS40044G-page 85
PIC16F627A/628A/648A
12.4
USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA). In
addition enable bit SPEN (RCSTA) is set in order to
configure the RB2/TX/CK and RB1/RX/DT I/O pins to
CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA).
12.4.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 12-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and
interrupt bit, TXIF (PIR1) is set. The interrupt can
be enabled/disabled by setting/clearing enable bit TXIE
(PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA) shows the status of the TSR register.
TRMT is a read-only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR
register is empty. The TSR is not mapped in data
memory so it is not available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is
stable around the falling edge of the synchronous clock
(Figure 12-8). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 12-9). This is advantageous when slow
baud rates are selected, since the BRG is kept in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
DS40044G-page 86
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to highimpedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a high-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
reset although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from high-impedance Receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Follow these steps when setting up a Synchronous
Master Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
TRISB and TRISB should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start each transmission by loading data to the
TXREG register.
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 12-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
TXIF
0Ch
PIR1
EEIF
CMIF
RCIF
18h
RCSTA
SPEN
RX9
SREN CREN
19h
TXREG USART Transmit Data Register
8Ch
PIE1
EEIE
CMIE
RCIE
98h
TXSTA
CSRC
TX9
99h
SPBRG Baud Rate Generator Register
Bit 3
—
Bit 2
—
TXEN SYNC
—
Bit 0
Value on
POR
CCP1IF TMR2IF TMR1IF 0000 -000
ADEN
TXIE
Bit 1
FERR
OERR
RX9D
TRMT
TX9D
0000 -000
0000 000x
0000 000x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 -000
BRGH
Value on all
other Resets
0000 -000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Legend:
FIGURE 12-8:
SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
bit 0
RB1/RX/DT pin
bit 1
Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
bit 2
bit 7
bit 0
Word 1
bit 1
Word 2
bit 7
RB2/TX/CK pin
Write to
TXREG Reg
Write Word 1
TXIF bit
(Interrupt Flag)
Write Word 2
TRMT
TRMT
bit
‘1’
‘1’
TXEN bit
Note:
Sync Master Mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 12-9:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RB1/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RB2/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
© 2009 Microchip Technology Inc.
DS40044G-page 87
PIC16F627A/628A/648A
12.4.2
USART SYNCHRONOUS MASTER
RECEPTION
Follow these steps when setting up a Synchronous
Master Reception:
1.
TRISB and TRISB should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
2. Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1 “USART Baud Rate
Generator (BRG)”).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
5. If interrupts are desired, then set enable bit
RCIE.
6. If 9-bit reception is desired, then set bit RX9.
7. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
8. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an OERR error occurred, clear the error by
clearing bit CREN.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA) or enable bit CREN (RCSTA). Data is
sampled on the RB1/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are
set, then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read-only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e., it is a twodeep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
TXIF
0Ch
PIR1
EEIF
CMIF
RCIF
18h
RCSTA
SPEN
RX9
SREN CREN
1Ah
RCREG USART Receive Data Register
8Ch
PIE1
EPIE
CMIE
98h
TXSTA
CSRC
TX9
99h
SPBRG Baud Rate Generator Register
Legend:
RCIE
Bit 3
—
ADEN
TXIE
—
TXEN SYNC
—
Bit 2
Bit 1
Bit 0
Value on:
POR
CCP1IF TMR2IF TMR1IF 0000 -000
FERR
OERR
RX9D
Value on all
other Resets
0000 -000
0000 000x
0000 000x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE -000 0000
-000 -000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception.
DS40044G-page 88
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 12-10:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4
RB1/RX/DT pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RB2/TX/CK pin
WRITE to
Bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note:
12.5
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA).
12.5.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
© 2009 Microchip Technology Inc.
Follow these steps when setting up a Synchronous
Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
TRISB and TRISB should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
DS40044G-page 89
PIC16F627A/628A/648A
12.5.2
USART SYNCHRONOUS SLAVE
RECEPTION
Follow these steps when setting up a Synchronous
Slave Reception:
1.
The operation of the Synchronous Master and Slave
modes is identical except in the case of the Sleep
mode. Also, bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
2.
3.
4.
5.
6.
7.
8.
9.
TRISB and TRISB should both be set to
‘1’ to configure the RB1/RX/DT and RB2/TX/CK
pins as inputs. Output drive, when required, is
controlled by the peripheral circuitry.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If an OERR error occurred, clear the error by
clearing bit CREN.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
18h
RCSTA
SPEN
RX9
SREN CREN
19h
TXREG USART Transmit Data Register
PIE1
EEIE
CMIE
98h
TXSTA
CSRC
TX9
99h
SPBRG Baud Rate Generator Register
8Ch
Legend:
RCIE
ADEN
TXIE
—
TXEN SYNC
—
Bit 2
Bit 1
Bit 0
Value on
POR
CCP1IF TMR2IF TMR1IF 0000 -000
FERR
OERR
RX9D
Value on all
other Resets
0000 -000
0000 000x
0000 000x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 -000
0000 -000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
TXIF
0Ch
PIR1
EEIF
CMIF
RCIF
18h
RCSTA
SPEN
RX9
SREN CREN
1Ah
RCREG USART Receive Data Register
PIE1
EEIE
CMIE
98h
TXSTA
CSRC
TX9
99h
SPBRG Baud Rate Generator Register
8Ch
RCIE
Bit 3
—
ADEN
TXIE
—
TXEN SYNC
—
Bit 2
Bit 1
Bit 0
Value on
POR
CCP1IF TMR2IF TMR1IF 0000 -000
FERR
OERR
RX9D
0000 000x
Value on all
other Resets
0000 -000
0000 000x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 -000
0000 -000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.
DS40044G-page 90
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
13.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers (SFRs). There are four SFRs used to read
and write this memory. These registers are:
•
•
•
•
EECON1
EECON2 (Not a physically implemented register)
EEDATA
EEADR
When the device is code-protected, the CPU can
continue to read and write the data EEPROM memory. A
device programmer can no longer access this memory.
EEDATA holds the 8-bit data for read/write and EEADR
holds the address of the EEPROM location being
accessed. PIC16F627A/628A devices have 128 bytes
of data EEPROM with an address range from 0h to
7Fh. The PIC16F648A device has 256 bytes of data
EEPROM with an address range from 0h to FFh.
REGISTER 13-1:
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip-to-chip. Please refer to AC specifications for
exact limits.
Additional information on the data EEPROM is
available in the PIC® Mid-Range Reference Manual
(DS33023).
EEDATA – EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
R/W-x
R/W-x
EEDAT2 EEDAT1
R/W-x
EEDAT0
bit 7
bit 7-0
bit 0
EEDATn: Byte value to Write to or Read from data EEPROM memory location.
Legend:
REGISTER 13-2:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
EEADR – EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EADR7
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 7
bit 0
PIC16F627A/628A
Unimplemented Address: Must be set to ‘0’
PIC16F648A
EEADR: Set to ‘1’ specifies top 128 locations (128-255) of EEPROM Read/Write Operation
bit 6-0
EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS40044G-page 91
PIC16F627A/628A/648A
13.1
EEADR
13.2
EECON1 and EECON2 Registers
The PIC16F648A EEADR register addresses 256
bytes of data EEPROM. All eight bits in the register
(EEADR) are required.
EECON1 is the control register with four low order bits
physically implemented. The upper-four bits are nonexistent and read as ‘0’s.
The PIC16F627A/628A EEADR register addresses
only the first 128 bytes of data EEPROM so only seven
of the eight bits in the register (EEADR) are
required. The upper bit is address decoded. This
means that this bit should always be ‘0’ to ensure that
the address is in the 128 byte memory space.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit and rewrite the location. The
data and address will be unchanged in the EEDATA
and EEADR registers.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
REGISTER 13-3:
EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 9Ch)
U-0
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
—
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software).
0 = Does not initiate an EEPROM read
Legend:
DS40044G-page 92
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
13.3
Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 13-1:
DATA EEPROM READ
BSF
MOVLW
MOVWF
BSF
MOVF
BCF
STATUS, RP0
CONFIG_ADDR
EEADR
EECON1, RD
EEDATA, W
STATUS, RP0
;Bank 1
;
;Address to read
;EE Read
;W = EEDATA
;Bank 0
13.4
Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
Required
Sequence
EXAMPLE 13-2:
BSF
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
DATA EEPROM WRITE
STATUS, RP0
EECON1, WREN
INTCON, GIE
INTCON,GIE
$-2
55h
EECON2
AAh
EECON2
EECON1,WR
BSF INTCON, GIE
;Bank 1
;Enable write
;Disable INTs.
;See AN576
;
;Write 55h
;
;Write AAh
;Set WR bit
;begin write
;Enable INTs.
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
cause the data not to be written into the EEPROM.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR1 registers must be cleared by software.
13.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
EXAMPLE 13-3:
BSF
MOVF
BSF
WRITE VERIFY
STATUS, RP0 ;Bank 1
EEDATA, W
EECON1, RD ;Read the
;value written
;
;Is the value written
;read (in EEDATA) the
;
SUBWF
EEDATA, W
BTFSS
STATUS, Z
GOTO
WRITE_ERR
:
:
13.6
(in W reg) and
same?
;
;Is difference 0?
;NO, Write error
;YES, Good write
;Continue program
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also
when enabled, the Power-up Timer (72 ms duration)
prevents EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
© 2009 Microchip Technology Inc.
DS40044G-page 93
PIC16F627A/628A/648A
13.7
Using the Data EEPROM
The data EEPROM is a high endurance, byte
addressable array that has been optimized for the storage
of frequently changing information (e.g., program
variables or other data that are updated often). When
variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the EEPROM
(specification D124) without exceeding the total number
of write cycles to a single byte (specifications D120 and
D120A). If this is the case, then an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
EXAMPLE 13-4:
BANKSEL
CLRF
BCF
BTFSC
GOTO
BSF
Loop
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
GOTO
A simple data EEPROM refresh routine is shown in
Example 13-4.
Note:
DATA EEPROM REFRESH ROUTINE
0X80
EEADR
INTCON, GIE
INTCON, GIE
$ - 2
EECON1, WREN
;select Bank1
;start at address 0
;disable interrupts
;see AN576
EECON1, RD
0x55
EECON2
0xAA
EECON2
EECON1, WR
EECON1, WR
$ - 1
;retrieve data into EEDATA
;first step of ...
;... required sequence
;second step of ...
;... required sequence
;start write sequence
;wait for write complete
;enable EE writes
#IFDEF __16F648A
;256 bytes in 16F648A
INCFSZ
#ELSE
INCF
BTFSS
#ENDIF
;test for end of memory
;128 bytes in 16F627A/628A
;next address
;test for end of memory
;end of conditional assembly
EEADR, f
EEADR, f
EEADR, 7
GOTO
Loop
;repeat for all locations
BCF
BSF
EECON1, WREN
INTCON, GIE
;disable EE writes
;enable interrupts (optional)
DS40044G-page 94
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
13.8
Data EEPROM Operation During
Code-Protect
When the device is code-protected, the CPU is able to
read and write data to the data EEPROM.
TABLE 13-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
Power-on
Reset
Value on all
other
Resets
xxxx xxxx
xxxx xxxx
---- x000
uuuu uuuu
uuuu uuuu
---- q000
---- ---9Dh
EECON2(1) EEPROM Control Register 2
Legend:
x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM.
Note 1: EECON2 is not a physical register.
---- ----
Address
9Ah
9Bh
9Ch
Name
EEDATA
EEADR
EECON1
Bit 7
Bit 6
Bit 5
EEPROM Data Register
EEPROM Address Register
—
—
—
© 2009 Microchip Technology Inc.
Bit 4
—
Bit 3
WRERR
Bit 2
WREN
Bit 1
WR
Bit 0
RD
DS40044G-page 95
PIC16F627A/628A/648A
NOTES:
DS40044G-page 96
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
14.0
SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real-time
applications are what sets a microcontroller apart from
other processors. The PIC16F627A/628A/648A family
has a host of such features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
OSC selection
Reset
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOR)
Interrupts
Watchdog Timer (WDT)
Sleep
Code protection
ID Locations
In-Circuit Serial Programming™ (ICSP™)
14.1
Configuration Bits
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special configuration memory space (2000h-3FFFh),
which can be accessed only during programming. See
“PIC16F627A/628A/648A EEPROM Memory
Programming Specification” (DS41196) for additional
information.
The PIC16F627A/628A/648A has a Watchdog Timer
which is controlled by configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in Reset while the
power supply stabilizes. There is also circuitry to reset
the device if a brown-out occurs. With these three
functions on-chip, most applications need no external
Reset circuitry.
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
© 2009 Microchip Technology Inc.
DS40044G-page 97
PIC16F627A/628A/648A
REGISTER 14-1:
CP
—
CONFIG – CONFIGURATION WORD REGISTER
—
—
—
CPD
LVP
BOREN
MCLRE
FOSC2
PWRTE
WDTE
F0SC1
bit 13
F0SC0
bit 0
bit 13:
CP: Flash Program Memory Code Protection bit(2)
(PIC16F648A)
1 = Code protection off
0 = 0000h to 0FFFh code-protected
(PIC16F628A)
1 = Code protection off
0 = 0000h to 07FFh code-protected
(PIC16F627A)
1 = Code protection off
0 = 0000h to 03FFh code-protected
bit 12-9:
Unimplemented: Read as ‘0’
bit 8:
CPD: Data Code Protection bit(3)
1 = Data memory code protection off
0 = Data memory code-protected
bit 7:
LVP: Low-Voltage Programming Enable bit
1 = RB4/PGM pin has PGM function, low-voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6:
BOREN: Brown-out Reset Enable bit (1)
1 = BOR Reset enabled
0 = BOR Reset disabled
bit 5:
MCLRE: RA5/MCLR/VPP Pin Function Select bit
1 = RA5/MCLR/VPP pin function is MCLR
0 = RA5/MCLR/VPP pin function is digital Input, MCLR internally tied to VDD
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0:
FOSC: Oscillator Selection bits(4)
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
110 = RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note
1:
2:
3:
4:
Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it does on the
PIC16F627/628 devices.
The code protection scheme has changed from the code protection scheme used on the PIC16F627/628 devices. The
entire Flash program memory needs to be bulk erased to set the CP bit, turning the code protection off. See
“PIC16F627A/628A/648A EEPROM Memory Programming Specification” (DS41196) for details.
The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See “PIC16F627A/
628A/648A EEPROM Memory Programming Specification” (DS41196) for details.
When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = bit is set
‘0’ = bit is cleared
DS40044G-page 98
x = bit is unknown
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
14.2
TABLE 14-1:
Oscillator Configurations
14.2.1
OSCILLATOR TYPES
The PIC16F627A/628A/648A can be operated in eight
different oscillator options. The user can program three
configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
•
•
•
•
•
•
LP
Low Power Crystal
XT
Crystal/Resonator
HS
High Speed Crystal/Resonator
RC
External Resistor/Capacitor (2 modes)
INTOSC Internal Precision Oscillator (2 modes)
EC
External Clock In
14.2.2
FIGURE 14-1:
CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
Note:
C1(2)
XTAL
RF
Sleep
OSC2
RS(1)
C2(2)
1:
2:
FOSC
PIC16F627A/628A/648A
A series resistor may be required for AT strip cut
crystals.
See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
© 2009 Microchip Technology Inc.
Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external components.
TABLE 14-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Mode
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
15-30 pF
0-15 pF
15-30 pF
0-15 pF
XT
100 kHz
2 MHz
4 MHz
68-150 pF
15-30 pF
15-30 pF
150-200 pF
15-30 pF
15-30 pF
HS
8 MHz
10 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
Note:
OSC1
Note
Mode
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 14-1). The PIC16F627A/628A/648A
oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may give a frequency
out of the crystal manufacturers specifications. When in
XT, LP or HS modes, the device can have an external
clock source to drive the OSC1 pin (Figure 14-4).
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time. These values are for design
guidance only. A series resistor (RS) may
be required in HS mode, as well as XT
mode, to avoid overdriving crystals with
low drive level specification. Since each
crystal has its own characteristics, the
user should consult the crystal manufacturer for appropriate values of external
components.
DS40044G-page 99
PIC16F627A/628A/648A
14.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance, or one with parallel
resonance.
Figure 14-2 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180° phase shift that a
parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The
10 kΩ potentiometers bias the 74AS04 in the linear
region. This could be used for external oscillator
designs.
FIGURE 14-2:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To other
Devices
10K
4.7K
74AS04
PIC16F627A/628A/648A
CLKIN
74AS04
10K
FIGURE 14-3:
330 KΩ
330 KΩ
74AS04
74AS04
Figure 14-3 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
DS40044G-page 100
74AS04
CLKIN
PIC16F627A/
628A/648A
XTAL
14.2.4
PRECISION INTERNAL 4 MHZ
OSCILLATOR
The internal precision oscillator provides a fixed 4 MHz
(nominal) system clock at VDD = 5V and 25°C. See
Section 17.0 “Electrical Specifications”, for information on variation over voltage and temperature.
14.2.5
EXTERNAL CLOCK IN
For applications where a clock is already available
elsewhere, users may directly drive the PIC16F627A/
628A/648A provided that this external clock source meets
the AC/DC timing requirements listed in Section 17.6
“Timing Diagrams and Specifications”. Figure 14-4
below shows how an external clock circuit should be
configured.
FIGURE 14-4:
10K
C2
To other
Devices
0.1 pF
XTAL
C1
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Clock from
ext. system
EXTERNAL CLOCK INPUT
OPERATION (EC, HS, XT
OR LP OSC
CONFIGURATION)
RA7/OSC1/CLKIN
PIC16F627A/628A/648A
RA6
RA6/OSC2/CLKOUT
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
14.2.6
RC OSCILLATOR
14.2.8
For applications where precise timing is not a
requirement, the RC oscillator option is available. The
operation and functionality of the RC oscillator is
dependent upon a number of variables. The RC oscillator
frequency is a function of:
• Supply voltage
• Resistor (REXT) and capacitor (CEXT) values
• Operating temperature
The oscillator frequency will vary from unit-to-unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 14-5 shows how the R/C combination is
connected.
FIGURE 14-5:
VDD
RC OSCILLATOR MODE
PIC16F627A/628A/648A
REXT
RA7/OSC1/
CLKIN
Internal
Clock
CEXT
VSS
FOSC/4
RA6/OSC2/CLKOUT
Recommended Values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3.0V)
CEXT > 20 pF
The RC Oscillator mode has two options that control
the unused OSC2 pin. The first allows it to be used as
a general purpose I/O port. The other configures the
pin as an output providing the FOSC signal (internal
clock divided by 4) for test or external synchronization
purposes.
14.2.7
CLKOUT
The PIC16F627A/628A/648A can be configured to
provide a clock out signal by programming the
Configuration Word. The oscillator frequency, divided
by 4 can be used for test purposes or to synchronize
other logic.
© 2009 Microchip Technology Inc.
SPECIAL FEATURE: DUAL-SPEED
OSCILLATOR MODES
A software programmable dual-speed oscillator mode
is provided when the PIC16F627A/628A/648A is
configured in the INTOSC oscillator mode. This feature
allows users to dynamically toggle the oscillator speed
between 4 MHz and 48 kHz nominal in the INTOSC
mode. Applications that require low-current power
savings, but cannot tolerate putting the part into Sleep,
may use this mode.
There is a time delay associated with the transition
between fast and slow oscillator speeds. This oscillator
speed transition delay consists of two existing clock
pulses and eight new speed clock pulses. During this
clock speed transition delay, the System Clock is halted
causing the processor to be frozen in time. During this
delay, the program counter and the CLKOUT stop.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See Section 4.2.2.6 “PCON
Register”, Register 4-6.
14.3
Reset
The PIC16F627A/628A/648A differentiates between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset (normal operation)
WDT wake-up (Sleep)
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset, Brown-out Reset, MCLR
Reset, WDT Reset and MCLR Reset during Sleep.
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations as indicated in Table 14-4. These bits are
used in software to determine the nature of the Reset.
See Table 14-7 for a full description of Reset states of
all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-7 for pulse width
specification.
DS40044G-page 101
PIC16F627A/628A/648A
FIGURE 14-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
Schmitt Trigger Input
MCLR/
VPP Pin
Sleep
WDT
Module
VDD Rise
Detect
WDT
Time-out
Reset
Power-on Reset
VDD
Brown-out
Reset
S
Q
R
Q
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
PWRT
On-chip(1)
OSC
10-bit Ripple-counter
Enable PWRT
See Table 14-3 for time out situations.
Enable OST
Note
1:
This is a separate oscillator from the INTOSC/RC oscillator.
DS40044G-page 102
© 2009 Microchip Technology Inc.
PIC16F627A/628A/648A
14.4
14.4.1
14.4.3
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
The OST provides a 1024 oscillator cycle (from OSC1
input) delay after the PWRT delay is over. Program
execution will not start until the OST time out is
complete. This ensures that the crystal oscillator or
resonator has started and stabilized.
POWER-ON RESET (POR)
The on-chip POR holds the part in Reset until a VDD
rise is detected (in the range of 1.2-1.7V). A maximum rise time for VDD is required. See Section 17.0
“Electrical Specifications” for details.
The OST time out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep. See Table 17-7.
The POR circuit does not produce an internal Reset
when VDD declines.
14.4.4
BROWN-OUT RESET (BOR)
The PIC16F627A/628A/648A have on-chip BOR
circuitry. A configuration bit, BOREN, can disable (if
clear/programmed) or enable (if set) the BOR circuitry.
If VDD falls below VBOR for longer than TBOR, the
brown-out situation will reset the chip. A Reset is not
assured if VDD falls below VBOR for shorter than TBOR.
VBOR and TBOR are defined in Table 17-2 and
Table 17-7, respectively.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset via MCLR, BOR
or PWRT until the operating conditions are met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting” (DS00607).
14.4.2
OSCILLATOR START-UP TIMER
(OST)
On any Reset (Power-on, Brown-out, Watchdog, etc.),
the chip will remain in Reset until VDD rises above
VBOR (see Figure 14-7). The Power-up Timer will now
be invoked, if enabled, and will keep the chip in Reset
an additional 72 ms.
POWER-UP TIMER (PWRT)
The PWRT provides a fixed 72 ms (nominal) time out
on power-up (POR) or if enabled from a Brown-out
Reset. The PWRT operates on an internal RC oscillator. The chip is kept in Reset as long as PWRT is active.
The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if
set) or enable (if cleared or programmed) the PWRT. It
is recommended that the PWRT be enabled when
Brown-out Reset is enabled.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-Up Timer will execute a
72 ms Reset. Figure 14-7 shows typical brown-out
situations.
The power-up time delay will vary from chip-to-chip and
due to VDD, temperature and process variation. See
DC parameters Table 17-7 for details.
FIGURE 14-7:
BROWN-OUT SITUATIONS WITH PWRT ENABLED
VDD
VBOR
≥ TBOR
Internal
Reset
72 ms
VDD
VBOR
Internal
Reset
工商网监
湘ICP备2023018690号
