PIC16F630/676
Data Sheet
14-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
2010 Microchip Technology Inc.
DS40039F
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
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Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
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Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
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© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-173-4
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS40039F-page 2
2010 Microchip Technology Inc.
PIC16F630/676
14-Pin, Flash-Based 8-Bit CMOS Microcontroller
High-Performance RISC CPU:
Low-Power Features:
• Only 35 Instructions to Learn
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
• 8-level Deep Hardware Stack
• Direct, Indirect, and Relative Addressing modes
• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
- 8.5 A @ 32 kHz, 2.0V, typical
- 100 A @ 1 MHz, 2.0V, typical
• Watchdog Timer Current
- 300 nA @ 2.0V, typical
• Timer1 Oscillator Current:
- 4 A @ 32 kHz, 2.0V, typical
Special Microcontroller Features:
Peripheral Features:
• Internal and External Oscillator Options
- Precision Internal 4 MHz oscillator factory
calibrated to ±1%
- External Oscillator support for crystals and
resonators
- 5 s wake-up from Sleep, 3.0V, typical
• Power-Saving Sleep mode
• Wide Operating Voltage Range – 2.0V to 5.5V
• Industrial and Extended Temperature Range
• Low-Power Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Detect (BOD)
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Multiplexed MCLR/Input-pin
• Interrupt-on-Pin Change
• Individual Programmable Weak Pull-ups
• Programmable Code Protection
• High Endurance Flash/EEPROM Cell
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/data EEPROM retention: > 40 years
Device
Program
Memory
• 12 I/O Pins with Individual Direction Control
• High Current Sink/Source for Direct LED Drive
• Analog Comparator module with:
- One analog comparator
- Programmable on-chip comparator voltage
reference (CVREF) module
- Programmable input multiplexing from device
inputs
- Comparator output is externally accessible
• Analog-to-Digital Converter module (PIC16F676):
- 10-bit resolution
- Programmable 8-channel input
- Voltage reference input
• Timer0: 8-bit Timer/Counter with 8-bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator, if INTOSC mode
selected
• In-Circuit Serial ProgrammingTM (ICSPTM) via
two pins
Data Memory
I/O
10-bit A/D
(ch)
Comparators
Timers
8/16-bit
128
12
–
1
1/1
128
12
8
1
1/1
Flash
(words)
SRAM
(bytes)
EEPROM
(bytes)
PIC16F630
1024
64
PIC16F676
1024
64
2010 Microchip Technology Inc.
DS40039F-page 3
PIC16F630/676
Pin Diagrams
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/AN3/CLKOUT
RA3/MCLR/VPP
RC5
RC4
RC3/AN7
DS40039F-page 4
1
2
3
4
5
6
7
1
2
3
4
5
6
7
PIC16F676
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5
RC4
RC3
PIC16F630
14-pin PDIP, SOIC, TSSOP
14
13
12
11
10
9
8
14
13
12
11
10
9
8
VSS
RA0/CIN+/ICSPDAT
RA1/CIN-/ICSPCLK
RA2/COUT/T0CKI/INT
RC0
RC1
RC2
VSS
RA0/AN0/CIN+/ICSPDAT
RA1/AN1/CIN-/VREF/ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RC0/AN4
RC1/AN5
RC2/AN6
2010 Microchip Technology Inc.
PIC16F630/676
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 7
2.0 Memory Organization .................................................................................................................................................................. 9
3.0 Ports A and C ............................................................................................................................................................................ 21
4.0 Timer0 Module .......................................................................................................................................................................... 31
5.0 Timer1 Module with Gate Control ............................................................................................................................................. 34
6.0 Comparator Module .................................................................................................................................................................. 39
7.0 Analog-to-Digital Converter (A/D) Module (PIC16F676 only) ................................................................................................... 45
8.0 Data EEPROM Memory............................................................................................................................................................ 51
9.0 Special Features of the CPU .................................................................................................................................................... 55
10.0 Instruction Set Summary ........................................................................................................................................................... 73
11.0 Development Support ............................................................................................................................................................... 81
12.0 Electrical Specifications ............................................................................................................................................................ 85
13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 107
14.0 Packaging Information ............................................................................................................................................................ 117
Appendix A: Data Sheet Revision History ......................................................................................................................................... 123
Appendix B: Device Differences ....................................................................................................................................................... 123
Appendix C: Device Migrations ......................................................................................................................................................... 124
Appendix D: Migrating from other PIC® Devices .............................................................................................................................. 124
Index ................................................................................................................................................................................................. 125
On-Line Support ................................................................................................................................................................................ 129
Systems Information and Upgrade Hot Line ..................................................................................................................................... 129
Reader Response ............................................................................................................................................................................. 130
Product Identification System ........................................................................................................................................................... 131
TO OUR VALUED CUSTOMERS
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Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2010 Microchip Technology Inc.
DS40039F-page 5
PIC16F630/676
NOTES:
DS40039F-page 6
2010 Microchip Technology Inc.
PIC16F630/676
1.0
DEVICE OVERVIEW
Sheet and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
This document contains device specific information for
the PIC16F630/676. Additional information may be
found in the PIC® Mid-Range Reference Manual
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this Data
FIGURE 1-1:
The PIC16F630 and PIC16F676 devices are covered
by this Data Sheet. They are identical, except the
PIC16F676 has a 10-bit A/D converter. They come in
14-pin PDIP, SOIC and TSSOP packages. Figure 1-1
shows a block diagram of the PIC16F630/676 devices.
Table 1-1 shows the pinout description.
PIC16F630/676 BLOCK DIAGRAM
INT
Configuration
13
Flash
8
Data Bus
Program Counter
PORTA
RA0
RA1
1K x 14
Program
Memory
Program
Bus
RA2
RAM
64
bytes
8-Level Stack
(13-bit)
14
RA3
RA4
File
Registers
RAM Addr
RA5
9
Addr MUX
Instruction Reg
7
Direct Addr
8
Indirect
Addr
FSR Reg
STATUS Reg
8
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
3
Power-up
Timer
Instruction
Decode and
Control
OSC1/CLKIN
Oscillator
Start-up Timer
Power-on
Reset
Timing
Generation
ALU
8
Watchdog
Timer
Brown-out
Detect
OSC2/CLKOUT
MUX
W Reg
Internal
Oscillator
T1G
MCLR VDD
VSS
T1CKI
Timer0
Timer1
T0CKI
Analog to Digital Converter
(PIC16F676 only)
Analog
Comparator
and reference
EEDATA
8 128 bytes
DATA
EEPROM
EEADDR
CIN- CIN+ COUT
VREF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
2010 Microchip Technology Inc.
DS40039F-page 7
PIC16F630/676
TABLE 1-1:
PIC16F630/676 PINOUT DESCRIPTION
Name
RA0/AN0/CIN+/ICSPDAT
RA1/AN1/CIN-/VREF/
ICSPCLK
RA2/AN2/COUT/T0CKI/INT
RA3/MCLR/VPP
RA4/T1G/AN3/OSC2/
CLKOUT
RA5/T1CKI/OSC1/CLKIN
RC0/AN4
RC1/AN5
RC2/AN6
RC3/AN7
RC4
RC5
VSS
VDD
Legend:
Function
Input
Type
Output
Type
RA0
TTL
CMOS
AN0
CIN+
ICSPDAT
RA1
AN
AN
TTL
TTL
—
CMOS
CMOS
AN1
CINVREF
ICSPCLK
RA2
AN
AN
AN
ST
ST
—
—
—
—
CMOS
AN2
COUT
T0CKI
INT
RA3
MCLR
VPP
RA4
AN
—
ST
ST
TTL
ST
HV
TTL
—
CMOS
—
—
—
—
—
CMOS
T1G
AN3
OSC2
CLKOUT
ST
AN3
—
—
—
—
XTAL
CMOS
RA5
TTL
CMOS
T1CKI
ST
OSC1
XTAL
CLKIN
ST
RC0
TTL
AN4
AN4
RC1
TTL
AN5
AN5
RC2
TTL
AN6
AN6
RC3
TTL
AN7
AN7
RC4
TTL
RC5
TTL
VSS
Power
VDD
Power
Shade = PIC16F676 only
TTL = TTL input buffer
ST = Schmitt Trigger input buffer
DS40039F-page 8
—
—
—
CMOS
—
CMOS
—
CMOS
—
CMOS
—
CMOS
CMOS
—
—
Description
Bidirectional I/O w/ programmable pull-up and
interrupt-on-change.
A/D Channel 0 input.
Comparator input.
Serial Programming Data I/O.
Bidirectional I/O w/ programmable pull-up and
interrupt-on-change.
A/D Channel 1 input.
Comparator input.
External Voltage reference.
Serial Programming Clock.
Bidirectional I/O w/ programmable pull-up and
interrupt-on-change.
A/D Channel 2 input.
Comparator output.
Timer0 clock input.
External Interrupt.
Input port with interrupt-on-change.
Master Clear.
Programming voltage.
Bidirectional I/O w/ programmable pull-up and
interrupt-on-change.
Timer1 gate.
A/D Channel 3 input.
Crystal/Resonator.
FOSC/4 output.
Bidirectional I/O w/ programmable pull-up and
interrupt-on-change.
Timer1 clock.
Crystal/Resonator.
External clock input/RC oscillator connection.
Bidirectional I/O.
A/D Channel 4 input.
Bidirectional I/O.
A/D Channel 5 input.
Bidirectional I/O.
A/D Channel 6 input.
Bidirectional I/O.
A/D Channel 7 input.
Bidirectional I/O.
Bidirectional I/O.
Ground reference.
Positive supply.
2010 Microchip Technology Inc.
PIC16F630/676
2.0
MEMORY ORGANIZATION
2.2
2.1
Program Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose Registers and the Special Function Registers. The Special
Function Registers are located in the first 32 locations
of each bank. Register locations 20h-5Fh are General
Purpose Registers, implemented as static RAM and
are mapped across both banks. All other RAM is
unimplemented and returns ‘0’ when read. RP0
(STATUS) is the bank select bit.
The PIC16F630/676 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h-03FFh)
for the PIC16F630/676 devices is physically implemented. Accessing a location above these boundaries
will cause a wrap around within the first 1K x 14 space.
The Reset vector is at 0000h and the interrupt vector is
at 0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F630/676
PC
CALL, RETURN
RETFIE, RETLW
• RP0 = 0 Bank 0 is selected
• RP0 = 1 Bank 1 is selected
Note:
2.2.1
13
Data Memory Organization
The IRP and RP1 bits STATUS are
reserved and should always be maintained
as ‘0’s.
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC16F630/676 devices. Each register is accessed,
either directly or indirectly, through the File Select
Register FSR (see Section 2.4 “Indirect Addressing,
INDF and FSR Registers”).
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
03FFh
0400h
1FFFh
2010 Microchip Technology Inc.
DS40039F-page 9
PIC16F630/676
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
FIGURE 2-2:
DATA MEMORY MAP OF
THE PIC16F630/676
File
Address
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON
ADRESH(2)
ADCON0(2)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Registers
File
Address
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
PCLATH
INTCON
PIE1
PCON
OSCCAL
ANSEL(2)
WPUA
IOCA
VRCON
EEDAT
EEADR
EECON1
EECON2(1)
ADRESL(2)
ADCON1(2)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
accesses
20h-5Fh
64 Bytes
5Fh
60h
DFh
E0h
7Fh
Bank 0
FFh
Bank 1
Unimplemented data memory locations, read as ‘0’.
1: Not a physical register.
2: PIC16F676 only.
DS40039F-page 10
2010 Microchip Technology Inc.
PIC16F630/676
TABLE 2-1:
Addr
Name
PIC16F630/676 SPECIAL REGISTERS SUMMARY BANK 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOD
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
20,63
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
31
02h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
19
03h
STATUS
0001 1xxx
13
04h
FSR
xxxx xxxx
20
05h
PORTA
--xx xxxx
21
06h
—
07h
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
Indirect data memory Address Pointer
PORTC
—
—
I/O Control Registers
Unimplemented
—
—
I/O Control Registers
—
—
--xx xxxx
28
—
08h
—
Unimplemented
—
09h
—
Unimplemented
—
—
---0 0000
19
0Ah
PCLATH
0Bh
INTCON
0Ch
PIR1
—
—
—
Write buffer for upper 5 bits of program counter
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
15
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF
00-- 0--0
17
0Dh
—
Unimplemented
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1
10h
T1CON
11h
—
12h
—
13h
—
—
xxxx xxxx
34
xxxx xxxx
34
-000 0000
36
Unimplemented
—
—
Unimplemented
—
—
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
—
Unimplemented
—
—
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
—
Unimplemented
—
—
-0-0 0000
39
19h
CMCON
—
—
T1GE
COUT
T1CKPS1
—
T1CKPS0
CINV
T1OSCEN
CIS
T1SYNC
TMR1CS
CM2
CM1
TMR1ON
CM0
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH(3)
xxxx xxxx
46
1Fh
ADCON0(3)
00-0 0000
47,63
Legend:
Note 1:
2:
3:
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ADFM
VCFG
—
CHS2
CHS1
CHS0
GO/DONE
ADON
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
IRP and RP1 bits are reserved, always maintain these bits clear.
PIC16F676 only.
2010 Microchip Technology Inc.
DS40039F-page 11
PIC16F630/676
TABLE 2-2:
Addr
PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOD
Page
Bank 1
80h
INDF
81h
OPTION_REG
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
86h
87h
Addressing this location uses contents of FSR to address data memory (not a physical register)
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
Program Counter’s (PC) Least Significant Byte
IRP(2)
RP1(2)
RP0
TO
Indirect data memory Address Pointer
—
TRISC
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Unimplemented
—
—
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
xxxx xxxx
20,63
1111 1111
14,32
0000 0000
19
0001 1xxx
13
xxxx xxxx
20
--11 1111
21
—
—
--11 1111
—
—
88h
—
Unimplemented
—
89h
—
Unimplemented
—
—
8Ah
PCLATH
---0 0000
19
—
—
—
Write buffer for upper 5 bits of program counter
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
15
8Ch
PIE1
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE
00-- 0--0
16
8Dh
8Eh
—
PCON
—
—
18
8Fh
Unimplemented
—
—
—
—
—
—
POR
BOD
---- --qq
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
1000 00--
18
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
—
48
—
—
—
—
—
—
90h
OSCCAL
91h
ANSEL(3)
—
92h
—
ANS7
ANS6
Unimplemented
93h
94h
—
—
Unimplemented
Unimplemented
95h
WPUA
—
—
WPUA5
WPUA4
—
WPUA2
WPUA1
WPUA0
--11 -111
22
96h
IOCA
—
—
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
--00 0000
23
—
—
—
—
0-0- 0000
0000 0000
44
51
0000 0000
---- x000
51
52
97h
98h
—
—
99h
VRCON
9Ah
EEDAT
9Bh
EEADR
9Ch
EECON1
9Dh
9Eh
EECON2
ADRESL(3)
Unimplemented
Unimplemented
VREN
—
EEPROM data register
—
—
VRR
EEPROM address register
—
—
—
VR3
VR2
VR1
VR0
—
WRERR
WREN
WR
RD
EEPROM control register 2 (not a physical register)
---- ----
51
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
xxxx xxxx
46
—
ADCS2
ADCS1
ADCS0
—
—
—
—
-000 ---47,63
9Fh
ADCON1(3)
Legend:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
2: IRP and RP1 bits are reserved, always maintain these bits clear.
3: PIC16F676 only.
DS40039F-page 12
2010 Microchip Technology Inc.
PIC16F630/676
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affecting any Status bits, see Section 10.0 “Instruction Set
Summary”.
Note 1: Bits IRP and RP1 (STATUS) are not
used by the PIC16F630/676 and should
be maintained as clear. Use of these bits
is not recommended, since this may affect
upward compatibility with future products.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
REGISTER 2-1:
STATUS — STATUS REGISTER (ADDRESS: 03h OR 83h)
Reserved Reserved
IRP
RP1
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: This bit is reserved and should be maintained as ‘0’
bit 6
RP1: This bit is reserved and should be maintained as ‘0’
bit 5
RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h-FFh)
0 = Bank 0 (00h-7Fh)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow, the polarity is reversed.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2010 Microchip Technology Inc.
x = Bit is unknown
DS40039F-page 13
PIC16F630/676
2.2.2.2
OPTION Register
Note:
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
•
•
•
•
TMR0/WDT prescaler
External RA2/INT interrupt
TMR0
Weak pull-ups on PORTA
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION). See
Section 4.4 “Prescaler”.
OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/INT pin
0 = Interrupt on falling edge of RA2/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/T0CKI pin
0 = Increment on low-to-high transition on RA2/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate WDT Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS40039F-page 14
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2010 Microchip Technology Inc.
PIC16F630/676
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTA change and
external RA2/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3
RAIE: Port Change Interrupt Enable bit(1)
1 = Enables the PORTA change interrupt
0 = Disables the PORTA change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0
RAIF: Port Change Interrupt Flag bit
1 = When at least one of the PORTA pins changed state (must be cleared in software)
0 = None of the PORTA pins have changed state
Note 1: IOCA register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should
be initialized before clearing T0IF bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2010 Microchip Technology Inc.
x = Bit is unknown
DS40039F-page 15
PIC16F630/676
2.2.2.4
PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4:
Note:
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE
bit 7
bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit (PIC16F676 only)
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4
Unimplemented: Read as ‘0’
bit 3
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 2-1
Unimplemented: Read as ‘0’
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
DS40039F-page 16
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2010 Microchip Technology Inc.
PIC16F630/676
2.2.2.5
PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
PIR1 — PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF
bit 7
bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6
ADIF: A/D Converter Interrupt Flag bit (PIC16F676 only)
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4
Unimplemented: Read as ‘0’
bit 3
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 2-1
Unimplemented: Read as ‘0’
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2010 Microchip Technology Inc.
x = Bit is unknown
DS40039F-page 17
PIC16F630/676
2.2.2.6
PCON Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
•
•
•
•
Power-on Reset (POR)
Brown-out Detect (BOD)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6:
PCON — POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-x
—
—
—
—
—
—
POR
BOD
bit 7
bit 0
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOD: Brown-out Detect Status bit
1 = No Brown-out Detect occurred
0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
Legend:
2.2.2.7
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to
calibrate the internal 4 MHz oscillator. It contains 6 bits
to adjust the frequency up or down to achieve 4 MHz.
The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7:
OSCCAL — INTERNAL OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
bit 7
bit 0
bit 7-2
CAL5:CAL0: 6-bit Signed Oscillator Calibration bits
111111 = Maximum frequency
100000 = Center frequency
000000 = Minimum frequency
bit 1-0
Unimplemented: Read as ‘0’
Legend:
DS40039F-page 18
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2010 Microchip Technology Inc.
PIC16F630/676
2.3
PCL and PCLATH
2.3.2
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC) is not
directly readable or writable and comes from PCLATH.
On any Reset, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figure 2-3 shows how the PC is loaded on
a write to PCL (PCLATH PCH). The lower
example in Figure 2-3 shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH
PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
STACK
The PIC16F630/676 family has an 8-level x 13-bit wide
hardware stack (see Figure 2-1). The stack space is
not part of either program or data space and the Stack
Pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL instruction is executed or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN,
RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH
11
Opcode
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note “Implementing a Table Read"
(AN556).
2010 Microchip Technology Inc.
DS40039F-page 19
PIC16F630/676
2.4
Indirect Addressing, INDF and
FSR Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-1:
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS), as shown in Figure 2-4.
FIGURE 2-4:
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
NEXT
0x20
FSR
INDF
FSR
FSR,4
NEXT
CONTINUE
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
DIRECT/INDIRECT ADDRESSING PIC16F630/676
Direct Addressing
RP1(1) RP0
INDIRECT ADDRESSING
6
From Opcode
Indirect Addressing
IRP(1)
0
7
Bank Select
Bank Select Location Select
00
01
10
FSR Register
0
Location Select
11
00h
180h
Data
Memory
Not Used
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
DS40039F-page 20
2010 Microchip Technology Inc.
PIC16F630/676
3.0
PORTS A AND C
There are as many as twelve general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
Note:
3.1
Additional information on I/O ports may be
found in the PIC® Mid-Range Reference
Manual, (DS33023)
PORTA and the TRISA Registers
PORTA is an 6-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
The exception is RA3, which is input only and its TRIS
bit will always read as ‘1’. Example 3-1 shows how to
initialize PORTA.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the PORT latch.
All write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the
PORT data latch. RA3 reads ‘0’ when MCLREN = 1.
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
REGISTER 3-1:
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
Note:
The ANSEL (91h) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC16F676.
EXAMPLE 3-1:
BCF
CLRF
MOVLW
MOVWF
BSF
CLRF
MOVLW
MOVWF
STATUS,RP0
PORTA
05h
CMCON
STATUS,RP0
ANSEL
0Ch
TRISA
BCF
STATUS,RP0
3.2
INITIALIZING PORTA
;Bank 0
;Init PORTA
;Set RA to
;digital I/O
;Bank 1
;digital I/O
;Set RA as inputs
;and set RA
;as outputs
;Bank 0
Additional Pin Functions
Every PORTA pin on the PIC16F630/676 has an
interrupt-on-change option and every PORTA pin,
except RA3, has a weak pull-up option. The next two
sections describe these functions.
3.2.1
WEAK PULL-UP
Each of the PORTA pins, except RA3, has an individually configurable weak internal pull-up. Control bits
WPUAx enable or disable each pull-up. Refer to
Register 3-3. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RAPU bit (OPTION).
PORTA — PORTA REGISTER (ADDRESS: 05h)
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as ‘0’
bit 5-0:
PORTA: PORTA I/O pin bits
1 = Port pin is >VIH
0 = Port pin is VIH
0 = Port pin is VIN0 = VIN+ < VINWhen CINV = 1:
1 = VIN+ < VIN0 = VIN+ > VIN-
bit 5
Unimplemented: Read as ‘0’
bit 4
CINV: Comparator Output Inversion bit
1 = Output inverted
0 = Output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM2:CM0 = 110 or 101:
1 = VIN- connects to CIN+
0 = VIN- connects to CIN-
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2010 Microchip Technology Inc.
x = Bit is unknown
DS40039F-page 39
PIC16F630/676
6.1
Comparator Operation
A single comparator is shown in Figure 6-1, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 6-1 represent
the uncertainty due to input offsets and response time.
Note:
To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be
programmed in the CMCON (19h) register.
The polarity of the comparator output can be inverted
by setting the CINV bit (CMCON). Clearing CINV
results in a non-inverted output. A complete table
showing the output state versus input conditions and
the polarity bit is shown in Table 6-1.
TABLE 6-1:
OUTPUT STATE VS. INPUT
CONDITIONS
Input Conditions
CINV
COUT
VIN- > VIN+
0
0
VIN- < VIN+
0
1
VIN- > VIN+
1
1
VIN- < VIN+
1
0
FIGURE 6-1:
SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
VINVIN+
Output
Note:
DS40039F-page 40
CINV bit (CMCON) is clear.
2010 Microchip Technology Inc.
PIC16F630/676
6.2
Comparator Configuration
There are eight modes of operation for the comparator.
The CMCON register, shown in Register 6-1, is used to
select the mode. Figure 6-2 shows the eight possible
modes. The TRISA register controls the data direction
of the comparator pins for each mode. If the
Comparator mode is changed, the comparator output
FIGURE 6-2:
level may not be valid for a specified period of time.
Refer to the specifications in Section 12.0 “Electrical Specifications”.
Note:
Comparator interrupts should be disabled
during a Comparator mode change. Otherwise, a false interrupt may occur.
COMPARATOR I/O OPERATING MODES
Comparator Reset (POR Default Value – low power)
Comparator Off (Lowest power)
CM2:CM0 = 000
CM2:CM0 = 111
RA1/CIN-
A
RA0/CIN+
A
RA2/COUT
D
Off (Read as ‘0’)
RA1/CIN-
D
RA0/CIN+
D
RA2/COUT
D
Off (Read as ‘0’)
Comparator without Output
Comparator w/o Output and with Internal Reference
CM2:CM0 = 010
CM2:CM0 = 100
RA1/CIN-
A
RA0/CIN+
A
RA2/COUT
D
COUT
RA1/CIN-
A
RA0/CIN+
D
RA2/COUT
D
COUT
From CVREF Module
Comparator with Output and Internal Reference
Multiplexed Input with Internal Reference and Output
CM2:CM0 = 011
CM2:CM0 = 101
RA1/CIN-
A
RA0/CIN+
D
RA2/COUT
D
COUT
From CVREF Module
RA1/CIN-
A
RA0/CIN+
A
RA2/COUT
D
CIS = 0
CIS = 1
COUT
From CVREF Module
Comparator with Output
Multiplexed Input with Internal Reference
CM2:CM0 = 001
CM2:CM0 = 110
RA1/CIN-
A
RA0/CIN+
A
RA2/COUT
D
COUT
RA1/CIN-
A
RA0/CIN+
A
RA2/COUT
D
CIS = 0
CIS = 1
COUT
From CVREF Module
A = Analog Input, ports always reads ‘0’
D = Digital Input
CIS = Comparator Input Switch (CMCON)
2010 Microchip Technology Inc.
DS40039F-page 41
PIC16F630/676
6.3
Analog Input Connection
Considerations
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
A simplified circuit for an analog input is shown in
Figure 6-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 6-3:
ANALOG INPUT MODE
VDD
VT = 0.6V
Rs < 10K
AIN
CPIN
5 pF
VA
VT = 0.6V
RIC
Leakage
±500 nA
Vss
Legend:
6.4
CPIN
VT
ILEAKAGE
RIC
RS
VA
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to Various Junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Comparator Output
The TRISA bit functions as an output enable/
disable for the RA2 pin while the comparator is in an
Output mode.
The comparator output, COUT, is read through the
CMCON register. This bit is read-only. The comparator
output may also be directly output to the RA2 pin in
three of the eight possible modes, as shown in
Figure 6-2. When in one of these modes, the output on
RA2 is asynchronous to the internal clock. Figure 6-4
shows the comparator output block diagram.
Note 1: When reading the PORTA register, all
pins configured as analog inputs will read
as a ‘0’. Pins configured as digital inputs
will convert an analog input according to
the TTL input specification.
2: Analog levels on any pin that is defined as
a digital input, may cause the input buffer
to consume more current than is
specified.
FIGURE 6-4:
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
RA0/CIN+
RA1/CIN-
To RA2/T0CKI pin
To Data Bus
Q
RD CMCON
Set CMIF bit
CVREF
D
EN
Q
CINV
CM2:CM0
D
RD CMCON
EN
Reset
DS40039F-page 42
2010 Microchip Technology Inc.
PIC16F630/676
6.5
Comparator Reference
The following equations determine the output voltages:
The comparator module also allows the selection of an
internally generated voltage reference for one of the
comparator inputs. The internal reference signal is
used for four of the eight Comparator modes. The
VRCON register, Register 6-2, controls the voltage
reference module shown in Figure 6-5.
6.5.1
CONFIGURING THE VOLTAGE
REFERENCE
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
FIGURE 6-5:
VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD
VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x
VDD / 32)
6.5.2
VOLTAGE REFERENCE
ACCURACY/ERROR
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 6-5) keep CVREF from approaching VSS or
VDD. The Voltage Reference is VDD derived and therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 12.0
“Electrical Specifications”.
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator
Input
VR3:VR0
6.6
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 12-7).
6.7
Operation During Sleep
Both the comparator and voltage reference, if enabled
before entering Sleep mode, remain active during
Sleep. This results in higher Sleep currents than shown
in the power-down specifications. The additional current consumed by the comparator and the voltage reference is shown separately in the specifications. To
minimize power consumption while in Sleep mode, turn
off the comparator, CM2:CM0 = 111, and voltage reference, VRCON = 0.
2010 Microchip Technology Inc.
While the comparator is enabled during Sleep, an interrupt will wake-up the device. If the device wakes up
from Sleep, the contents of the CMCON and VRCON
registers are not affected.
6.8
Effects of a Reset
A device Reset forces the CMCON and VRCON
registers to their Reset states. This forces the
comparator module to be in the Comparator Reset
mode, CM2:CM0 = 000 and the voltage reference to its
off state. Thus, all potential inputs are analog inputs
with the comparator and voltage reference disabled to
consume the smallest current possible.
DS40039F-page 43
PIC16F630/676
REGISTER 6-2:
VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
—
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
VREN: CVREF Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down, no IDD drain
bit 6
Unimplemented: Read as ‘0’
bit 5
VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR3:VR0: CVREF value selection bits 0 VR [3:0] 15
When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD
Legend:
6.9
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Comparator Interrupts
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that has occurred. The
CMIF bit, PIR1, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
a)
b)
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
Note:
The CMIE bit (PIE1) and the PEIE bit
(INTCON) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
TABLE 6-2:
Address
x = Bit is unknown
If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1) interrupt flag may not
get set.
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
all other
Resets
Bit 0
Value on
POR, BOD
RAIF
0000 0000 0000 000u
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
—
—
CMIF
—
—
19h
CMCON
—
COUT
—
CINV
CIS
CM2
CM1
8Ch
PIE1
EEIE
ADIE
—
—
CMIE
—
—
85h
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111 --11 1111
99h
VRCON
VREN
—
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000 0-0- 0000
Legend:
TMR1IF 00-- 0--0 00-- 0--0
CM0
-0-0 0000 -0-0 0000
TMR1IE 00-- 0--0 00-- 0--0
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
DS40039F-page 44
2010 Microchip Technology Inc.
PIC16F630/676
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC16F676 ONLY)
circuit. The output of the sample and hold is connected
to the input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
VDD or a voltage applied by the VREF pin. Figure 7-1
shows the block diagram of the A/D on the PIC16F676.
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. The PIC16F676 has eight
analog inputs, multiplexed into one sample and hold
FIGURE 7-1:
A/D BLOCK DIAGRAM
VDD
VCFG = 0
VREF
VCFG = 1
RA0/AN0
RA1/AN1/VREF
ADC
RA2/AN2
10
GO/DONE
RA4/AN3
RC0/AN4
ADFM
RC1/AN5
10
ADON
RC2/AN6
RC3/AN7
VSS
ADRESH
ADRESL
CHS2:CHS0
7.1
A/D Configuration and Operation
There are three registers available to control the
functionality of the A/D module:
1.
2.
3.
ADCON0 (Register 7-1)
ADCON1 (Register 7-2)
ANSEL (Register 7-3)
7.1.1
ANALOG PORT PINS
The ANS7:ANS0 bits (ANSEL) and the TRISA
bits control the operation of the A/D port pins. Set the
corresponding TRISA bits to set the pin output driver to
its high-impedance state. Likewise, set the corresponding ANS bit to disable the digital input buffer.
Note:
7.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
There are eight analog channels on the PIC16F676,
AN0
through
AN7.
The
CHS2:CHS0
bits
(ADCON0) control which channel is connected to
the sample and hold circuit.
2010 Microchip Technology Inc.
7.1.3
VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either VDD is used, or an analog voltage
applied to VREF is used. The VCFG bit (ADCON0)
controls the voltage reference selection. If VCFG is set,
then the voltage on the VREF pin is the reference;
otherwise, VDD is the reference.
7.1.4
CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ADCON1). There are seven possible
clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be selected to ensure a minimum TAD of
1.6 s. Table 7-1 shows a few TAD calculations for
selected frequencies.
DS40039F-page 45
PIC16F630/676
TABLE 7-1:
TAD vs. DEVICE OPERATING FREQUENCIES
A/D Clock Source (TAD)
Device Frequency
Operation
ADCS2:ADCS0
20 MHz
5 MHz
4 MHz
1.25 MHz
2 TOSC
000
100 ns(2)
400 ns(2)
500 ns(2)
1.6 s
4 TOSC
100
200 ns(2)
800 ns(2)
1.0 s(2)
3.2 s
001
400 ns(2)
1.6 s
2.0 s
6.4 s
8 TOSC
(2)
16 TOSC
101
800 ns
3.2 s
4.0 s
12.8 s(3)
(3)
32 TOSC
010
1.6 s
6.4 s
8.0 s
25.6 s(3)
(3)
(3)
64 TOSC
110
3.2 s
12.8 s
16.0 s
51.2 s(3)
A/D RC
x11
2 - 6 s(1,4)
2 - 6 s(1,4)
2 - 6 s(1,4)
2 - 6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.
7.1.5
STARTING A CONVERSION
previous conversion. After an aborted conversion, a
2 TAD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0). When the conversion is
complete, the A/D module:
Note:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1)
• Generates an interrupt (if enabled)
7.1.6
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
conversion
sample.
Instead,
the
ADRESH:ADRESL registers will retain the value of the
FIGURE 7-2:
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left
or right shifted. The ADFM bit (ADCON0) controls
the output format. Figure 7-2 shows the output formats.
10-BIT A/D RESULT FORMAT
ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
10-bit A/D Result
Unimplemented: Read as ‘0’
MSB
(ADFM = 1)
bit 7
Unimplemented: Read as ‘0’
DS40039F-page 46
bit 0
LSB
bit 0
bit 7
bit 0
10-bit A/D Result
2010 Microchip Technology Inc.
PIC16F630/676
REGISTER 7-1:
ADCON0 — A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0
ADFM
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG
—
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
bit 7
ADFM: A/D Result Formed Select bit
1 = Right justified
0 = Left justified
bit 6
VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5
Unimplemented: Read as zero
bit 4-2
CHS2:CHS0: Analog Channel Select bits
000 = Channel 00 (AN0)
001 = Channel 01 (AN1)
010 = Channel 02 (AN2)
011 = Channel 03 (AN3)
100 = Channel 04 (AN4)
101 = Channel 05 (AN5)
110 = Channel 06 (AN6)
111 = Channel 07 (AN7)
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: A/D Conversion Status bit
1 = A/D converter module is operating
0 = A/D converter is shut-off and consumes no operating current
Legend:
REGISTER 7-2:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
ADCON1 — A/D CONTROL REGISTER 1 (ADRESS: 9Fh)
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
ADCS2
ADCS1
ADCS0
—
—
—
—
bit 7
bit 0
bit 7:
Unimplemented: Read as ‘0’
bit 6-4:
ADCS: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0:
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2010 Microchip Technology Inc.
x = Bit is unknown
DS40039F-page 47
PIC16F630/676
REGISTER 7-3:
ANSEL — ANALOG SELECT REGISTER (ADRESS: 91h) (PIC16F676 ONLY)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
bit 7
bit 7-0:
bit 0
ANS: Analog Select between analog or digital function on pins AN, respectively.
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,
weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit
must be set to Input mode in order to allow external control of the voltage on the pin.
Legend:
DS40039F-page 48
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2010 Microchip Technology Inc.
PIC16F630/676
7.2
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 7-3. The maximum recommended impedance for analog sources is 10 k. As the impedance
EQUATION 7-1:
TACQ
TC
TACQ
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To calculate the minimum acquisition time, Equation 7-1
may be used. This equation assumes that 1/2 LSb error
is used (1024 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC® Mid-Range Reference Manual (DS33023).
ACQUISITION TIME
= Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2s + TC + [(Temperature -25°C)(0.05s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1k + 7k + 10k) In(0.0004885)
16.47s
2s + 16.47s + [(50°C -25C)(0.05s/C)
19.72s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
FIGURE 7-3:
ANALOG INPUT MODEL
VDD
RS
ANx
VA
CPIN
5 pF
VT = 0.6V
VT = 0.6V
Sampling
Switch
RIC 1K SS RSS
CHOLD
= DAC capacitance
= 120 pF
I LEAKAGE
± 500 nA
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
2010 Microchip Technology Inc.
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
DS40039F-page 49
PIC16F630/676
7.3
A/D Operation During Sleep
The A/D converter module can operate during Sleep.
This requires the A/D clock source to be set to the
internal oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from Sleep. If
the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
TABLE 7-2:
Address
PORTA
07h
PORTC
7.4
Effects of Reset
A device Reset forces all registers to their Reset state.
Thus, the A/D module is turned off and any pending
conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
SUMMARY OF A/D REGISTERS
Name
05h
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 --xx xxxx --uu uuuu
PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 --xx xxxx --uu uuuu
—
—
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
0Ch
PIR1
EEIF
ADIF
—
—
CMIF
—
—
1Eh
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
1Fh
ADCON0
TRISA
Value on
all other
Resets
Bit 6
0Bh, 8Bh INTCON
85h
Value on
POR, BOD
Bit 7
ADFM
VCFG
—
CHS2
CHS1
CHS0
GO
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
RAIF
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0
ADON
xxxx xxxx uuuu uuuu
00-0 0000 00-0 0000
TRISA0 --11 1111 --11 1111
87h
TRISC
—
—
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0 --11 1111 --11 1111
8Ch
PIE1
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE 00-- 0--0 00-- 0--0
91h
ANSEL
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
9Eh
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
9Fh
ADCON1
—
ADCS2
ADCS1
ADCS0
—
—
—
ANS0
—
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
-000 ---- -000 ----
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for A/D converter module.
DS40039F-page 50
2010 Microchip Technology Inc.
PIC16F630/676
8.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC Specifications for
exact limits.
•
•
•
•
EECON1
EECON2 (not a physically implemented register)
EEDATA
EEADR
When the data memory is code-protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
this memory.
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC16F630/676 devices have 128
bytes of data EEPROM with an address range from 0h
to 7Fh.
Additional information on the data EEPROM is
available in the PIC® Mid-Range Reference Manual,
(DS33023).
REGISTER 8-1:
EEDAT — EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
R/W-0
R/W-0
EEDAT2 EEDAT1
R/W-0
EEDAT0
bit 7
bit 7-0
bit 0
EEDATn: Byte value to write to or read from data EEPROM
Legend:
REGISTER 8-2:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
EEADR — EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 0
bit 7
Unimplemented: Should be set to ‘0’
bit 6-0
EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2010 Microchip Technology Inc.
x = Bit is unknown
DS40039F-page 51
PIC16F630/676
8.1
EEADR
The EEADR register can address up to a maximum of
128 bytes of data EEPROM. Only seven of the eight
bits in the register (EEADR) are required. The
MSb (bit 7) is ignored.
The upper bit should always be ‘0’ to remain upward
compatible with devices that have more data EEPROM
memory.
8.2
EECON1 AND EECON2
REGISTERS
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit
is set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the
user can check the WRERR bit, clear it, and rewrite
the location. The data and address will be cleared,
therefore, the EEDATA and EEADR registers will
need to be re-initialized.
EECON1 is the control register with four low order bits
physically implemented. The upper four bits are nonimplemented and read as ‘0’s.
The Interrupt flag bit EEIF in the PIR1 register is set
when the write is complete. This bit must be cleared in
software.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
REGISTER 8-3:
EECON1 — EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
—
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOD detect)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit
can only be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set, not cleared, in software.)
0 = Does not initiate an EEPROM read
Legend:
S = Bit can only be set
DS40039F-page 52
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2010 Microchip Technology Inc.
PIC16F630/676
8.3
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1), as shown in Example 8-1. The data
is available in the very next cycle in the EEDATA
register. Therefore, it can be read in the next
instruction. EEDATA holds this value until another read,
or until it is written to by the user (during a write
operation).
EXAMPLE 8-1:
BSF
MOVLW
MOVWF
BSF
MOVF
8.4
DATA EEPROM READ
STATUS,RP0
CONFIG_ADDR
EEADR
EECON1,RD
EEDATA,W
;Bank 1
;
;Address to read
;EE Read
;Move data to W
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR) register must be cleared by software.
8.5
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPLE 8-3:
WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
Required
Sequence
EXAMPLE 8-2:
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
DATA EEPROM WRITE
STATUS,RP0
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
;Bank 1
;Enable write
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
2010 Microchip Technology Inc.
WRITE VERIFY
WRITE VERIFY
BCF
:
BSF
MOVF
STATUS,RP0
BSF
EECON1,RD
STATUS,RP0
EEDATA,W
XORWF EEDATA,W
BTFSS STATUS,Z
GOTO
WRITE_ERR
:
8.5.1
;Bank 0
;Any code
;Bank 1 READ
;EEDATA not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specifications D120 or D120A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
8.6
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
DS40039F-page 53
PIC16F630/676
8.7
DATA EEPROM OPERATION
DURING CODE-PROTECT
Data memory can be code-protected by programming
the CPD bit to ‘0’.
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended to code-protect the program memory
when code protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which outputs the contents of data memory.
Programming unused locations to ‘0’ will also help
prevent data memory code protection from becoming
breached.
TABLE 8-1:
Address
0Ch
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Name
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
EEIF
ADIF
—
—
CMIF
—
—
9Ah
EEDATA
9Bh
EEADR
—
9Ch
EECON1
—
9Dh
EECON2(1) EEPROM Control Register 2
Bit 0
0000 0000 0000 0000
EEPROM Address Register
—
Value on all
other
Resets
TMR1IF 00-- 0--0 00-- 0--0
EEPROM Data Register
—
Value on
POR, BOD
—
-000 0000 -000 0000
WRERR WREN
WR
RD
---- x000 ---- q000
---- ---- ---- ----
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the data EEPROM module.
Note 1: EECON2 is not a physical register.
DS40039F-page 54
2010 Microchip Technology Inc.
PIC16F630/676
9.0
SPECIAL FEATURES OF THE
CPU
Certain special circuits that deal with the needs of real
time applications are what sets a microcontroller apart
from other processors. The PIC16F630/676 family has
a host of such features intended to:
• maximize system reliability
• minimize cost through elimination of external
components
• provide power-saving operating modes and offer
code protection
These features are:
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Detect (BOD)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming™
2010 Microchip Technology Inc.
The PIC16F630/676 has a Watchdog Timer that is
controlled by Configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in Reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can provide at least
a 72 ms Reset. With these three functions on-chip,
most applications need no external Reset circuitry.
The Sleep mode is designed to offer a very low current
Power-down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer wake-up
• An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 9-1).
DS40039F-page 55
PIC16F630/676
9.1
Configuration Bits
Note:
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations, as shown in Register 9-1. These
bits are mapped in program memory location 2007h.
REGISTER 9-1:
R/P-1 R/P-1
BG1
bit 13
bit 13-12
bit 11-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CONFIG — CONFIGURATION WORD (ADDRESS: 2007h)
U-0
U-0
U-0
R/P-1
R/P-1
—
—
—
CPD
CP
BG0
Address 2007h is beyond the user program
memory space. It belongs to the special configuration memory space (2000h-3FFFh),
which can be accessed only during programming. See PIC16F630/676 Programming
Specification for more information.
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0
bit 0
BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1)
00 = Lowest bandgap voltage
11 = Highest bandgap voltage
Unimplemented: Read as ‘0’
CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit(3)
1 = Program Memory code protection is disabled
0 = Program Memory code protection is enabled
BODEN: Brown-out Detect Enable bit(4)
1 = BOD enabled
0 = BOD disabled
MCLRE: RA3/MCLR pin function select bit(5)
1 = RA3/MCLR pin function is MCLR
0 = RA3/MCLR pin function is digital I/O, MCLR internally tied to VDD
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN
110 = RC oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN
011 = EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing
the device as specified in the PIC16F630/676 Programming Specification. These bits are reflected
in an export of the Configuration Word. Microchip Development Tools maintain all calibration bits to
factory settings.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased, including OSCCAL value, when the code protection is
turned off.
4: Enabling Brown-out Detect does not automatically enable Power-up Timer.
5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
Legend:
P = Programmed using ICSP™
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
x = bit is unknown
DS40039F-page 56
2010 Microchip Technology Inc.
PIC16F630/676
9.2
Oscillator Configurations
9.2.1
LP
Low-Power Crystal
XT
Crystal/Resonator
HS
High Speed Crystal/Resonator
RC
External Resistor/Capacitor (2 modes)
INTOSC Internal Oscillator (2 modes)
EC
External Clock In
Note:
Additional information on oscillator configurations is available in the PIC® Mid-Range
Reference Manual, (DS33023).
9.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (see Figure 9-1). The PIC16F630/676 oscillator design requires the use of a parallel cut crystal.
Use of a series cut crystal may yield a frequency
outside of the crystal manufacturers specifications.
When in XT, LP or HS modes, the device can have an
external clock source to drive the OSC1 pin (see
Figure 9-2).
FIGURE 9-1:
CRYSTAL OPERATION (OR
CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
RF(3)
PIC16F630/676
1:
2:
3:
Note 1: Functions as RA4 in EC Osc mode.
TABLE 9-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Ranges Characterized:
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external
components.
TABLE 9-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
OSC1(C1)
OSC2(C2)
LP
32 kHz
68-100 pF
68-100 pF
Sleep
XT
100 kHz
2 MHz
4 MHz
68-150 pF
15-30 pF
15-30 pF
150-200 pF
15-30 pF
15-30 pF
PIC16F630/676
HS
8 MHz
10 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
RS(2)
See Table 9-1 and Table 9-2 for recommended
values of C1 and C2.
A series resistor may be required for AT strip cut
crystals.
RF varies with the Oscillator mode selected
(Approx. value = 10 M
2010 Microchip Technology Inc.
OSC2(1)
Open
OSC2
C2(1)
OSC1
Freq
To Internal
Logic
XTAL
Clock from
External System
Mode
OSC1
C1(1)
Note
EXTERNAL CLOCK INPUT
OPERATION (HS, XT, EC,
OR LP OSC
CONFIGURATION)
OSCILLATOR TYPES
The PIC16F630/676 can be operated in eight different
Oscillator Option modes. The user can program three
Configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
•
•
•
•
•
•
FIGURE 9-2:
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode as well as XT mode to avoid
overdriving crystals with low drive level
specification. Since each crystal has its
own characteristics, the user should
consult the crystal manufacturer for
appropriate values of external
components.
DS40039F-page 57
PIC16F630/676
9.2.3
EXTERNAL CLOCK IN
9.2.5
For applications where a clock is already available
elsewhere, users may directly drive the PIC16F630/
676 provided that this external clock source meets the
AC/DC timing requirements listed in Section 12.0
“Electrical Specifications”. Figure 9-2 shows how
an external clock circuit should be configured.
9.2.4
RC OSCILLATOR
For applications where precise timing is not a
requirement, the RC oscillator option is available. The
operation and functionality of the RC oscillator is
dependent upon a number of variables. The RC
oscillator frequency is a function of:
• Supply voltage
• Resistor (REXT) and capacitor (CEXT) values
• Operating temperature
The oscillator frequency will vary from unit to unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 9-3 shows how the R/C combination is
connected.
Two options are available for this Oscillator mode
which allow RA4 to be used as a general purpose I/O
or to output FOSC/4.
FIGURE 9-3:
RC OSCILLATOR MODE
VDD
REXT
PIC16F630/676
RA5/OSC1/
CLKIN
CEXT
VSS
FOSC/4
RA4/OSC2/CLKOUT
DS40039F-page 58
Internal
Clock
INTERNAL 4 MHZ OSCILLATOR
When calibrated, the internal oscillator provides a fixed
4 MHz (nominal) system clock. See Electrical
Specifications, Section 12.0 “Electrical Specifications”, for information on variation over voltage and
temperature.
Two options are available for this Oscillator mode
which allow RA4 to be used as a general purpose I/O
or to output FOSC/4.
9.2.5.1
Calibrating the Internal Oscillator
A calibration instruction is programmed into the last
location of program memory. This instruction is a
RETLW XX, where the literal is the calibration value.
The literal is placed in the OSCCAL register to set the
calibration of the internal oscillator. Example 9-1
demonstrates how to calibrate the internal oscillator.
For best operation, decouple (with capacitance) VDD
and VSS as close to the device as possible.
Note:
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration value
must be saved prior to erasing part as
specified in the PIC16F630/676 Programming specification. Microchip Development Tools maintain all calibration bits to
factory settings.
EXAMPLE 9-1:
BSF
CALL
MOVWF
BCF
9.2.6
CALIBRATING THE
INTERNAL OSCILLATOR
STATUS, RP0
3FFh
OSCCAL
STATUS, RP0
;Bank 1
;Get the cal value
;Calibrate
;Bank 0
CLKOUT
The PIC16F630/676 devices can be configured to
provide a clock out signal in the INTOSC and RC
Oscillator modes. When configured, the oscillator
frequency divided by four (FOSC/4) is output on the
RA4/OSC2/CLKOUT pin. FOSC/4 can be used for test
purposes or to synchronize other logic.
2010 Microchip Technology Inc.
PIC16F630/676
9.3
Reset
The PIC16F630/676 differentiates between various
kinds of Reset:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Detect (BOD)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 9-4.
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
•
•
•
•
•
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations as indicated in Table 9-4. These bits are
used in software to determine the nature of the Reset.
See Table 9-7 for a full description of Reset states of all
registers.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 12-4 in Electrical
Specifications Section for pulse-width specification.
Power-on Reset
MCLR Reset
WDT Reset
WDT Reset during Sleep
Brown-out Detect (BOD)
FIGURE 9-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP pin
WDT
WDT
Module
SLEEP
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BODEN
S
Q
R
Q
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
OSC1/
CLKIN
pin
On-chip(1)
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT
See Table 9-3 for time-out situations.
Enable OST
Note
1:
This is a separate oscillator from the INTOSC/EC oscillator.
2010 Microchip Technology Inc.
DS40039F-page 59
PIC16F630/676
9.3.1
MCLR
PIC16F630/676 devices have a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 9-5, is suggested.
An internal MCLR option is enabled by setting the
MCLRE bit in the Configuration Word. When enabled,
MCLR is internally tied to VDD. No internal pull-up
option is available for the MCLR pin.
FIGURE 9-5:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC16F630/676
R1
1 kor greater
MCLR
C1
0.1 f
(optional, not critical)
9.3.2
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting.”
9.3.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates on an internal
RC oscillator. The chip is kept in Reset as long as
PWRT is active. The PWRT delay allows the VDD to
rise to an acceptable level. A Configuration bit, PWRTE
can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should always be enabled when Brown-out
Detect is enabled.
The Power-up Time delay will vary from chip to chip
and due to:
• VDD variation
• Temperature variation
• Process variation.
See DC parameters for details (Section 12.0 “Electrical Specifications”).
9.3.4
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply tie the
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. See Section 12.0 “Electrical Specifications” for details. If the BOD is enabled, the maximum
rise time specification does not apply. The BOD circuitry will keep the device in Reset until VDD reaches
VBOD (see Section 9.3.5 “Brown-out Detect
(BOD)”).
Note:
The POR circuit does not produce an internal Reset when VDD declines.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
DS40039F-page 60
2010 Microchip Technology Inc.
PIC16F630/676
9.3.5
BROWN-OUT DETECT (BOD)
On any Reset (Power-on, Brown-out Detect,
Watchdog, etc.), the chip will remain in Reset until VDD
rises above BVDD (see Figure 9-6). The Power-up
Timer will now be invoked, if enabled, and will keep the
chip in Reset an additional 72 ms.
The PIC16F630/676 members have on-chip Brown-out
Detect circuitry. A Configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If VDD falls below VBOD for
greater than parameter (TBOD) in Table 12-4 (see
Section 12.0 “Electrical Specifications”), the
Brown-out situation will reset the device. This will occur
regardless of VDD slew-rate. A Reset is not guaranteed
to occur if VDD falls below VBOD for less than parameter
(TBOD).
FIGURE 9-6:
Note:
A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
Configuration Word is set.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-up Timer will execute a
72 ms Reset.
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOD
72 ms(1)
VDD
Internal
Reset
VBOD
VDD)20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by PORTA and PORTC (combined) .......................................................................... 200 mA
Maximum current sourced PORTA and PORTC (combined) .......................................................................... 200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
2010 Microchip Technology Inc.
DS40039F-page 85
PIC16F630/676
FIGURE 12-1:
PIC16F630/676 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
8
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 12-2:
PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
8
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS40039F-page 86
2010 Microchip Technology Inc.
PIC16F630/676
FIGURE 12-3:
PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
0°C TA +125°C
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.2
2.0
0
4
8
10
12
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2010 Microchip Technology Inc.
DS40039F-page 87
PIC16F630/676
12.1
DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)
DC CHARACTERISTICS
Param
No.
Sym
VDD
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Min
Typ† Max Units
Supply Voltage
D001
D001A
D001B
D001C
D001D
Conditions
FOSC < = 4 MHz:
PIC16F630/676 with A/D off
PIC16F676 with A/D on, 0°C to +125°C
PIC16F676 with A/D on, -40°C to +125°C
4 MHZ < FOSC < = 10 MHz
2.0
2.2
2.5
3.0
4.5
—
—
—
—
—
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
1.5*
—
—
V
Device in Sleep mode
V
See section on Power-on Reset for details
D002
VDR
RAM Data Retention
Voltage(1)
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
D004
SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05*
—
—
D005
VBOD
—
2.1
—
V/ms See section on Power-on Reset for details
V
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
DS40039F-page 88
2010 Microchip Technology Inc.
PIC16F630/676
12.2
DC Characteristics: PIC16F630/676-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +85C for industrial
Param
No.
D010
Conditions
Device Characteristics
Min
Typ†
Max
Units
Supply Current (IDD)
—
9
16
A
2.0
—
18
28
A
3.0
D011
D012
D013
D014
D015
D016
D017
Note
VDD
—
35
54
A
5.0
—
110
150
A
2.0
—
190
280
A
3.0
—
330
450
A
5.0
—
220
280
A
2.0
—
370
650
A
3.0
—
0.6
1.4
mA
5.0
—
70
110
A
2.0
—
140
250
A
3.0
—
260
390
A
5.0
—
180
250
A
2.0
—
320
470
A
3.0
—
580
850
A
5.0
—
340
450
A
2.0
—
500
780
A
3.0
—
0.8
1.1
mA
5.0
—
180
250
A
2.0
—
320
450
A
3.0
—
580
800
A
5.0
—
2.1
2.95
mA
4.5
—
2.4
3.0
mA
5.0
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 1 MHz
EC Oscillator Mode
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
2010 Microchip Technology Inc.
DS40039F-page 89
PIC16F630/676
12.3
DC Characteristics: PIC16F630/676-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +85C for industrial
Param
No.
D020
Conditions
Device Characteristics
Min
Typ†
Max
Units
Power-down Base Current
(IPD)
—
0.99
700
nA
2.0
—
1.2
770
nA
3.0
D021
D022
D023
D024
D025
D026
Note
VDD
—
2.9
995
nA
5.0
—
0.3
1.5
A
2.0
—
1.8
3.5
A
3.0
—
8.4
17
A
5.0
—
58
70
A
3.0
—
109
130
A
5.0
—
3.3
6.5
A
2.0
—
6.1
8.5
A
3.0
—
11.5
16
A
5.0
—
58
70
A
2.0
—
85
100
A
3.0
—
138
160
A
5.0
—
4.0
6.5
A
2.0
—
4.6
7.0
A
3.0
—
6.0
10.5
A
5.0
—
1.2
755
nA
3.0
—
0.0022
1.0
A
5.0
WDT, BOD, Comparators, VREF,
and T1OSC disabled
WDT Current(1)
BOD Current(1)
Comparator Current(1)
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS40039F-page 90
2010 Microchip Technology Inc.
PIC16F630/676
12.4
DC Characteristics: PIC16F630/676-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +125C for extended
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max
Units
D010E
Supply Current (IDD)
—
9
16
A
2.0
—
18
28
A
3.0
D011E
D012E
D013E
D014E
D015E
D016E
D017E
Note
VDD
—
35
54
A
5.0
—
110
150
A
2.0
—
190
280
A
3.0
—
330
450
A
5.0
—
220
280
A
2.0
—
370
650
A
3.0
—
0.6
1.4
mA
5.0
—
70
110
A
2.0
—
140
250
A
3.0
—
260
390
A
5.0
—
180
250
A
2.0
—
320
470
A
3.0
—
580
850
A
5.0
—
340
450
A
2.0
—
500
780
A
3.0
—
0.8
1.1
mA
5.0
—
180
250
A
2.0
—
320
450
A
3.0
—
580
800
A
5.0
—
2.1
2.95
mA
4.5
—
2.4
3.0
mA
5.0
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 1 MHz
EC Oscillator Mode
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
2010 Microchip Technology Inc.
DS40039F-page 91
PIC16F630/676
12.5
DC Characteristics: PIC16F630/676-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C TA +125C for extended
Param
No.
D020E
Conditions
Device Characteristics
Min
Typ†
Max
Units
Power-down Base Current
(IPD)
—
0.00099
3.5
A
2.0
—
0.0012
4.0
A
3.0
D021E
D022E
D023E
D024E
D025E
D026E
Note
VDD
—
0.0029
8.0
A
5.0
—
0.3
6.0
A
2.0
—
1.8
9.0
A
3.0
—
8.4
20
A
5.0
—
58
70
A
3.0
—
109
130
A
5.0
—
3.3
10
A
2.0
—
6.1
13
A
3.0
—
11.5
24
A
5.0
—
58
70
A
2.0
—
85
100
A
3.0
—
138
165
A
5.0
—
4.0
10
A
2.0
—
4.6
12
A
3.0
—
6.0
20
A
5.0
—
0.0012
6.0
A
3.0
—
0.0022
8.5
A
5.0
WDT, BOD, Comparators, VREF,
and T1OSC disabled
WDT Current(1)
BOD Current(1)
Comparator Current(1)
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS40039F-page 92
2010 Microchip Technology Inc.
PIC16F630/676
12.6
DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)
DC CHARACTERISTICS
Param
Sym
No.
VIL
D030
D030A
D031
D032
D033
D033A
VIH
D040
D040A
D041
D042
D043
D043A
D043B
D070 IPUR
D060
IIL
D060A
D060B
D061
D063
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
OSC1 (XT and LP modes)
OSC1 (HS mode)
Input High Voltage
I/O ports
with TTL buffer
VOL
D090
D092
VOH
Min
Typ†
Max
Units
VSS
VSS
VSS
VSS
VSS
VSS
—
0.8
0.15 VDD
0.2 VDD
0.2 VDD
0.3
0.3 VDD
V
V
V
V
V
V
4.5V VDD 5.5V
Otherwise
Entire range
V
V
4.5V VDD 5.5V
otherwise
entire range
250
VDD
VDD
VDD
VDD
VDD
VDD
VDD
400*
V
V
V
V
A
Input Leakage Current(3)
I/O ports
—
01
1
A
—
—
01
01
01
01
1
1
5
5
A
A
A
A
Output Low Voltage
I/O ports
OSC2/CLKOUT (RC mode)
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V (Ind.)
IOL = 1.6 mA, VDD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
Output High Voltage
I/O ports
OSC2/CLKOUT (RC mode)
VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V (Ind.)
IOH = -1.3 mA, VDD = 4.5V (Ind.)
IOH = -1.0 mA, VDD = 4.5V (Ext.)
—
—
—
—
—
Conditions
(Note 1)
(Note 1)
—
2.0
(0.25 VDD+0.8)
with Schmitt Trigger buffer
0.8 VDD
MCLR
0.8 VDD
OSC1 (XT and LP modes)
1.6
OSC1 (HS mode)
0.7 VDD
OSC1 (RC mode)
0.9 VDD
PORTA Weak Pull-up
50*
Current
Analog inputs
VREF
MCLR(2)
OSC1
D080
D083
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
—
—
—
—
—
—
—
—
—
(Note 1)
(Note 1)
VDD = 5.0V, VPIN = VSS
VSS VPIN VDD,
Pin at high-impedance
VSS VPIN VDD
VSS VPIN VDD
VSS VPIN VDD
VSS VPIN VDD, XT, HS and
LP osc configuration
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use
an external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2010 Microchip Technology Inc.
DS40039F-page 93
PIC16F630/676
12.7
DC Characteristics: PIC16F630/676-I (Industrial), PIC16F630/676-E (Extended)
(Cont.)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Capacitive Loading Specs
on Output Pins
OSC2 pin
D100
COSC2
D101
CIO
D120
D120A
D121
ED
ED
VDRW
D122
D123
TDEW Erase/Write cycle time
TRETD Characteristic Retention
D124
TREF
D130
D130A
D131
EP
ED
VPR
D132
D133
D134
VPEW VDD for Erase/Write
TPEW Erase/Write cycle time
TRETD Characteristic Retention
All I/O pins
Data EEPROM Memory
Byte Endurance
Byte Endurance
VDD for Read/Write
Number of Total Erase/Write
Cycles before Refresh(1)
Program Flash Memory
Cell Endurance
Cell Endurance
VDD for Read
Min
Typ†
Max
Units
Conditions
—
—
15*
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1
—
—
50*
pF
100K
10K
VMIN
1M
100K
—
—
—
5.5
—
40
5
—
6
—
1M
10M
—
10K
1K
VMIN
100K
10K
—
—
—
5.5
4.5
—
40
—
2
—
5.5
2.5
—
E/W -40C TA +85°C
E/W +85°C TA +125°C
V
Using EECON to read/write
VMIN = Minimum operating
voltage
ms
Year Provided no other specifications
are violated
E/W -40C TA +85°C
E/W -40C TA +85°C
E/W +85°C TA +125°C
V
VMIN = Minimum operating
voltage
V
ms
Year Provided no other specifications
are violated
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Section 8.5.1 for additional information.
DS40039F-page 94
2010 Microchip Technology Inc.
PIC16F630/676
12.8
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 12-4:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
Legend:
RL = 464
CL = 50 pF
15 pF
2010 Microchip Technology Inc.
VSS
CL
Pin
VSS
for all pins
for OSC2 output
DS40039F-page 95
PIC16F630/676
12.9
AC CHARACTERISTICS: PIC16F630/676 (INDUSTRIAL, EXTENDED)
FIGURE 12-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
4
3
4
2
CLKOUT
TABLE 12-1:
Param
No.
Sym
FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
Units
External CLKIN Frequency(1)
DC
DC
DC
DC
5
—
DC
0.1
1
—
—
—
—
—
4
—
—
—
37
4
20
20
37
—
4
4
20
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
LP Osc mode
XT mode
HS mode
EC mode
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
27
50
50
250
27
—
250
250
50
—
—
—
—
200
—
—
10,000
1,000
s
ns
ns
ns
s
ns
ns
ns
ns
LP Osc mode
HS Osc mode
EC Osc mode
XT Osc mode
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
Oscillator Frequency(1)
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
2
TCY
250
—
—
—
Conditions
Instruction Cycle Time(1)
External CLKIN (OSC1) High
External CLKIN Low
200
TCY
DC
ns TCY = 4/FOSC
3
TosL,
2*
—
—
s LP oscillator, TOSC L/H duty cycle
TosH
20*
—
—
ns HS oscillator, TOSC L/H duty cycle
100 *
—
—
ns XT oscillator, TOSC L/H duty cycle
4
TosR, External CLKIN Rise
—
—
50*
ns LP oscillator
TosF External CLKIN Fall
—
—
25*
ns XT oscillator
—
—
15*
ns HS oscillator
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)
for all devices.
DS40039F-page 96
2010 Microchip Technology Inc.
PIC16F630/676
TABLE 12-2:
Param
No.
F10
F14
Sym
PRECISION INTERNAL OSCILLATOR PARAMETERS
Characteristic
FOSC Internal Calibrated
INTOSC Frequency
Freq
Min
Tolerance
Typ†
Max
Units
MHz VDD = 3.5V, 25C
MHz 2.5V VDD 5.5V
0C TA +85C
MHz 2.0V VDD 5.5V
-40C TA +85C (IND)
-40C TA +125C (EXT)
s VDD = 2.0V, -40C to +85C
s VDD = 3.0V, -40C to +85C
s VDD = 5.0V, -40C to +85C
1
2
3.96
3.92
4.00
4.00
4.04
4.08
5
3.80
4.00
4.20
—
—
—
—
Sleep start-up time*
—
—
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise
only and are not tested.
TIOSC Oscillator Wake-up from
ST
2010 Microchip Technology Inc.
6
4
3
8
6
5
Conditions
stated. These parameters are for design guidance
DS40039F-page 97
PIC16F630/676
FIGURE 12-6:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
19
14
12
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
TABLE 12-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
10
TosH2ckL OSC1 to CLOUT
—
75
200
ns
(Note 1)
11
TosH2ckH OSC1 to CLOUT
—
75
200
ns
(Note 1)
12
TckR
CLKOUT rise time
—
35
100
ns
(Note 1)
13
TckF
CLKOUT fall time
—
35
100
ns
(Note 1)
14
TckL2ioV
CLKOUT to Port out valid
15
TioV2ckH
Port in valid before CLKOUT
—
—
20
ns
(Note 1)
TOSC + 200 ns
—
—
ns
(Note 1)
16
TckH2ioI
Port in hold after CLKOUT
0
—
—
ns
(Note 1)
17
TosH2ioV
OSC1 (Q1 cycle) to Port out valid
—
50
150 *
ns
18
TosH2ioI
OSC1 (Q2 cycle) to Port input
invalid (I/O in hold time)
19
—
—
300
ns
100
—
—
ns
TioV2osH Port input valid to OSC1
(I/O in setup time)
0
—
—
ns
20
TioR
Port output rise time
—
10
40
ns
21
TioF
Port output fall time
—
10
40
ns
22
Tinp
INT pin high or low time
25
—
—
ns
PORTA change INT high or low
time
TCY
—
—
ns
23
Trbp
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.
DS40039F-page 98
2010 Microchip Technology Inc.
PIC16F630/676
FIGURE 12-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
34
31
34
I/O Pins
FIGURE 12-8:
BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD
BVDD
(Device not in Brown-out Detect)
(Device in Brown-out Detect)
35
Reset (due to BOD)
72 ms time-out(1)
Note 1: 72 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.
2010 Microchip Technology Inc.
DS40039F-page 99
PIC16F630/676
TABLE 12-4:
Param
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT DETECT REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
11
—
18
—
24
s
ms
VDD = 5V, -40°C to +85°C
Extended temperature
31
TWDT
Watchdog Timer Time-out
Period
(No Prescaler)
10
10
17
17
25
30
ms
ms
VDD = 5V, -40°C to +85°C
Extended temperature
32
TOST
Oscillation Start-up Timer
Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
TPWRT
Power-up Timer Period
28*
TBD
72
TBD
132*
TBD
ms
ms
VDD = 5V, -40°C to +85°C
Extended Temperature
34
TIOZ
I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
—
—
2.0
s
BVDD
Brown-out Detect Voltage
2.025
—
2.175
V
Brown-out Hysteresis
TBD
—
—
—
Brown-out Detect Pulse Width
100*
—
—
s
35
TBOD
VDD BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS40039F-page 100
2010 Microchip Technology Inc.
PIC16F630/676
FIGURE 12-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
48
47
TMR0 or
TMR1
TABLE 12-5:
Param
No.
40*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Sym
Tt0H
Characteristic
T0CKI High Pulse Width
Min
No Prescaler
With Prescaler
41*
Tt0L
T0CKI Low Pulse Width
No Prescaler
With Prescaler
42*
Tt0P
T0CKI Period
45*
Tt1H
T1CKI High Time Synchronous, No Prescaler
Synchronous,
with Prescaler
Asynchronous
46*
Tt1L
T1CKI Low Time
Synchronous, No Prescaler
Synchronous,
with Prescaler
Asynchronous
47*
Tt1P
T1CKI Input
Period
Synchronous
Asynchronous
Ft1
48
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
*
†
Typ†
Max
Units
0.5 TCY + 20
—
—
ns
10
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
30
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
30
—
—
ns
Greater of:
30 or TCY + 40
N
—
—
ns
60
—
—
ns
DC
—
200*
kHz
2 TOSC*
—
7 TOSC*
—
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2010 Microchip Technology Inc.
DS40039F-page 101
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TABLE 12-6:
COMPARATOR SPECIFICATIONS
Comparator Specifications
Sym
Characteristics
Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Min
Typ
Max
Units
VOS
Input Offset Voltage
—
5.0
10
mV
VCM
Input Common Mode Voltage
0
—
VDD - 1.5
V
CMRR
Common Mode Rejection Ratio
+55*
—
—
db
—
150
400*
ns
—
—
10*
s
Response Time
TRT
(1)
TMC2COV Comparator Mode Change to
Output Valid
Comments
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD - 1.5V.
TABLE 12-7:
COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Voltage Reference Specifications
Sym
Characteristics
Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Min
Typ
Max
Units
Comments
Resolution
—
—
VDD/24*
VDD/32
—
—
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy
—
—
—
—
1/2*
1/2*
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R)
—
2k*
—
Settling Time(1)
—
—
10*
s
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR transitions from 0000 to 1111.
DS40039F-page 102
2010 Microchip Technology Inc.
PIC16F630/676
TABLE 12-8:
Param
No.
Sym
PIC16F676 A/D CONVERTER CHARACTERISTICS:
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10 bits
A02
EABS
Total Absolute
Error*
—
—
1
LSb VREF = 5.0V
bit
A03
EIL
Integral Error
—
—
1
LSb VREF = 5.0V
A04
EDL
Differential Error
—
—
1
LSb No missing codes to 10 bits
VREF = 5.0V
A05
EFS
Full Scale Range
2.2*
—
5.5*
A06
EOFF
Offset Error
—
—
1
LSb VREF = 5.0V
A07
EGN
Gain Error
—
—
1
LSb VREF = 5.0V
A10
—
Monotonicity
—
guaranteed(3)
—
—
A20
A20A
VREF
Reference Voltage
2.0
2.5
—
—
VDD + 0.3
V
A21
VREF
Reference V High
(VDD or VREF)
VSS
—
VDD
V
A25
VAIN
Analog Input
Voltage
VSS
—
VREF
V
A30
ZAIN
Recommended
Impedance of
Analog Voltage
Source
—
—
10
k
A50
IREF
VREF Input
Current(2)
10
—
1000
A
—
—
10
A
V
VSS VAIN VREF+
Absolute minimum to ensure 10-bit
accuracy
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2010 Microchip Technology Inc.
DS40039F-page 103
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FIGURE 12-10:
PIC16F676 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
Q4
130
A/D CLK
9
A/D DATA
8
7
3
6
2
1
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
DONE
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 12-9:
Param
No.
PIC16F676 A/D CONVERSION REQUIREMENTS
Sym
Characteristic
130
TAD
A/D Clock Period
130
TAD
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
Q4 to A/D Clock
Start
Min
Typ†
Max
Units
Conditions
1.6
—
—
s
TOSC based, VREF 3.0V
3.0*
—
—
s
TOSC based, VREF full range
3.0*
6.0
9.0*
s
ADCS = 11 (RC mode)
At VDD = 2.5V
2.0*
4.0
6.0*
s
At VDD = 5.0V
—
11
—
TAD
Set GO bit to new data in A/D result
register
(Note 2)
11.5
—
s
5*
—
—
s
The minimum time is the amplifier
settling time. This may be used if the
“new” input voltage has not changed
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled voltage (as stored on CHOLD).
—
TOSC/2
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Table 7-1 for minimum conditions.
DS40039F-page 104
2010 Microchip Technology Inc.
PIC16F630/676
FIGURE 12-11:
PIC16F676 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
134
(TOSC/2 + TCY)(1)
1 TCY
131
Q4
130
A/D CLK
9
A/D DATA
8
7
3
6
2
1
NEW_DATA
OLD_DATA
ADRES
0
ADIF
1 TCY
GO
DONE
SAMPLE
SAMPLING STOPPED
132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 12-10: PIC16F676 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
1.6
—
—
s
3.0*
—
—
s
VREF full range
s
ADCS = 11 (RC mode)
At VDD = 2.5V
At VDD = 5.0V
130
TAD
A/D Clock Period
130
TAD
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
*
†
Q4 to A/D Clock
Start
Conditions
VREF 3.0V
3.0*
6.0
9.0*
2.0*
4.0
6.0*
s
—
11
—
TAD
(Note 2)
11.5
—
s
5*
—
—
s
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
—
TOSC/2 + TCY
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Table 7-1 for minimum conditions.
2010 Microchip Technology Inc.
DS40039F-page 105
PIC16F630/676
NOTES:
DS40039F-page 106
2010 Microchip Technology Inc.
PIC16F630/676
13.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. “Typical” represents the mean of the distribution at 25°C. “Max” or “min” represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 13-1:
TYPICAL IPD vs. VDD OVER TEMP (-40°C TO +25°C)
Typical Baseline IPD
6.0E-09
5.0E-09
IPD (A)
4.0E-09
-40
3.0E-09
0
25
2.0E-09
1.0E-09
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 13-2:
TYPICAL IPD vs. VDD OVER TEMP (+85°C)
Typical Baseline IPD
3.5E-07
3.0E-07
IPD (A)
2.5E-07
2.0E-07
85
1.5E-07
1.0E-07
5.0E-08
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2010 Microchip Technology Inc.
DS40039F-page 107
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FIGURE 13-3:
TYPICAL IPD vs. VDD OVER TEMP (+125°C)
Typical Baseline IPD
4.0E-06
3.5E-06
IPD (A)
3.0E-06
2.5E-06
125
2.0E-06
1.5E-06
1.0E-06
5.0E-07
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-4:
MAXIMUM IPD vs. VDD OVER TEMP (-40°C TO +25°C)
Maximum Baseline IPD
1.0E-07
9.0E-08
IPD (A)
8.0E-08
7.0E-08
6.0E-08
-40
5.0E-08
0
4.0E-08
25
3.0E-08
2.0E-08
1.0E-08
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
DS40039F-page 108
2010 Microchip Technology Inc.
PIC16F630/676
FIGURE 13-5:
MAXIMUM IPD vs. VDD OVER TEMP (+85°C)
Maximum Baseline IPD
9.0E-07
8.0E-07
IPD (A)
7.0E-07
6.0E-07
5.0E-07
4.0E-07
85
3.0E-07
2.0E-07
1.0E-07
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 13-6:
MAXIMUM IPD vs. VDD OVER TEMP (+125°C)
Maximum Baseline IPD
9.0E-06
8.0E-06
IPD (A)
7.0E-06
6.0E-06
5.0E-06
125
4.0E-06
3.0E-06
2.0E-06
1.0E-06
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2010 Microchip Technology Inc.
DS40039F-page 109
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FIGURE 13-7:
TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical BOD IPD
130
120
IPD (uA)
110
-40
100
0
90
25
80
85
125
70
60
50
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 13-8:
TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical Comparator IPD
1.8E-05
1.6E-05
1.4E-05
-40
IPD (A)
1.2E-05
0
1.0E-05
25
8.0E-06
85
6.0E-06
125
4.0E-06
2.0E-06
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40039F-page 110
2010 Microchip Technology Inc.
PIC16F630/676
FIGURE 13-9:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C)
IPD (A)
Typical A/D IPD
5.0E-09
4.5E-09
4.0E-09
3.5E-09
3.0E-09
2.5E-09
2.0E-09
1.5E-09
1.0E-09
5.0E-10
0.0E+00
-40
0
25
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 13-10:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C)
Typical A/D IPD
3.5E-07
3.0E-07
IPD (A)
2.5E-07
2.0E-07
85
1.5E-07
1.0E-07
5.0E-08
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
2010 Microchip Technology Inc.
DS40039F-page 111
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FIGURE 13-11:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)
Typical A/D IPD
3.5E-06
IPD (A)
3.0E-06
2.5E-06
2.0E-06
125
1.5E-06
1.0E-06
5.0E-07
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 13-12:
TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C),
32 KHZ, C1 AND C2=50 pF)
Typical T1 IPD
1.20E-05
1.00E-05
-40
IPD (A)
8.00E-06
0
25
6.00E-06
85
4.00E-06
125
2.00E-06
0.00E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40039F-page 112
2010 Microchip Technology Inc.
PIC16F630/676
FIGURE 13-13:
TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical CVREF IPD
160
IPD (uA)
140
-40
120
0
25
100
85
80
125
60
40
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 13-14:
TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical WDT IPD
16
IPD (uA)
14
12
-40
10
0
8
25
6
85
4
125
2
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD (V)
2010 Microchip Technology Inc.
DS40039F-page 113
PIC16F630/676
FIGURE 13-15:
MAXIMUM AND MINIMUMINTOSC FREQ vs. TEMPERATURE WITH 0.1F AND
0.01F DECOUPLING (VDD = 3.5V)
Internal Oscillator
Frequency vs Temperature
4.20E+06
Frequency (Hz)
4.15E+06
4.10E+06
4.05E+06
-3sigma
4.00E+06
average
3.95E+06
+3sigma
3.90E+06
3.85E+06
3.80E+06
-40°C
0°C
25°C
85°C
125°C
Temperature (°C)
FIGURE 13-16:
MAXIMUM AND MINIMUMINTOSC FREQ vs. VDD WITH 0.1F AND 0.01F
DECOUPLING (+25°C)
Internal Oscillator
Frequency vs VDD
Frequency (Hz)
4.20E+06
4.15E+06
4.10E+06
4.05E+06
4.00E+06
-3sigma
3.95E+06
3.90E+06
+3sigma
average
3.85E+06
3.80E+06
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
VDD (V)
DS40039F-page 114
2010 Microchip Technology Inc.
PIC16F630/676
TYPICAL WDT PERIOD vs. VDD (-40C TO +125C)
FIGURE 13-17:
WDT Time-out
50
Time (mS)
45
40
35
-40
30
25
0
20
15
10
5
85
25
125
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD (V)
2010 Microchip Technology Inc.
DS40039F-page 115
PIC16F630/676
NOTES:
DS40039F-page 116
2010 Microchip Technology Inc.
PIC16F630/676
14.0
PACKAGING INFORMATION
14.1
Package Marking Information
14-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
14-Lead SOIC
XXXXXXXX
1015/017
16F630-E e3
1015/017
Example
16F630 e3
1015
YYWW
NNN
017
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
16F630-I e3
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
14-Lead TSSOP
Example
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2010 Microchip Technology Inc.
DS40039F-page 117
PIC16F630/676
14.2
Package Details
The following sections give the technical details of the
packages.
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