PIC16(L)F722/3/4/6/7
28/40/44-Pin Flash Microcontrollers with XLP Technology
Devices Included In This Data Sheet:
PIC16F722/3/4/6/7 Devices:
• PIC16F722
• PIC16F726
• PIC16F723
• PIC16F727
Extreme Low-Power Management
PIC16LF722/3/4/6/7 with XLP:
• Sleep Mode: 20 nA
• Watchdog Timer: 500 nA
• Timer1 Oscillator: 600 nA @ 32 kHz
• PIC16F724
PIC16LF722/3/4/6/7 Devices:
• PIC16LF722
• PIC16LF726
• PIC16LF723
• PIC16LF727
• PIC16LF724
High-Performance RISC CPU:
• Only 35 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Up to 8K x 14 Words of Flash Program Memory
• Up to 368 Bytes of Data Memory (RAM)
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Processor Read Access to Program Memory
• Pinout Compatible to other 28/40-pin PIC16CXXX
and PIC16FXXX Microcontrollers
Special Microcontroller Features:
• Precision Internal Oscillator:
- 16 MHz or 500 kHz operation
- Factory calibrated to ±1%, typical
- Software tunable
- Software selectable ÷1, ÷2, ÷4 or ÷8 divider
• 1.8V-5.5V Operation – PIC16F722/3/4/6/7
• 1.8V-3.6V Operation – PIC16LF722/3/4/6/7
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Brown-out Reset (BOR):
- Selectable between two trip points
- Disable in Sleep option
• Programmable Code Protection
• In-Circuit Serial ProgrammingTM (ICSPTM) via Two
Pins
• Multiplexed Master Clear with Pull-up/Input Pin
• Industrial and Extended Temperature Range
• High-Endurance Flash Cell:
- 1,000 write Flash endurance (typical)
- Flash retention: > 40 years
• Power-Saving Sleep mode
2007-2015 Microchip Technology Inc.
Analog Features:
• A/D Converter:
- 8-bit resolution and up to 14 channels
- Conversion available during Sleep
- Selectable 1.024/2.048/4.096V voltage
reference
• On-chip 3.2V Regulator (PIC16F722/3/4/6/7
devices only)
Peripheral Highlights:
• Up to 35 I/O Pins and One Input-only Pin:
- High-current source/sink for direct LED drive
- Interrupt-on-pin change
- Individually programmable weak pull-ups
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- Dedicated low-power 32 kHz oscillator
- 16-bit timer/counter with prescaler
- External Gate Input mode with Toggle and
Single Shot modes
- Interrupt-on-gate completion
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture, Compare, PWM (CCP) Modules:
- 16-bit Capture, max. resolution 12.5 ns
- 16-bit Compare, max. resolution 200 ns
- 10-bit PWM, max. frequency 20 kHz
• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)
• Synchronous Serial Port (SSP):
- SPI (Master/Slave)
- I2C (Slave) with Address Mask
• mTouch® Sensing Oscillator Module:
- Up to 16 input channels
DS40001341F-page 1
PIC16(L)F722/3/4/6/7
DS40001341F-page 2
XLP
PIC16(L)F707
(1)
8192
363
0
36 14 32
4/2
1
1
2
PIC16(L)F720
(2)
2048
128
128
18 12 —
2/1
1
1
1
PIC16(L)F721
(2)
4096
256
128
18 12 —
2/1
1
1
1
PIC16(L)F722
(4)
2048
128
0
25 11 8
2/1
1
1
2
PIC16(L)F722A
(3)
2048
128
0
25 11 8
2/1
1
1
2
PIC16(L)F723
(4)
4096
192
0
25 11 8
2/1
1
1
2
PIC16(L)F723A
(3)
4096
192
0
25 11 8
2/1
1
1
2
PIC16(L)F724
(4)
4096
192
0
36 14 16
2/1
1
1
2
PIC16(L)F726
(4)
8192
368
0
25 11 8
2/1
1
1
2
PIC16(L)F727
(4)
8192
368
0
36 14 16
2/1
1
1
2
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS41418
PIC16(L)F707 Data Sheet, 40/44-Pin Flash, 8-bit Microcontrollers
2: DS41430
PIC16(L)F720/721 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers
3: DS41417
PIC16(L)F722A/723A Data Sheet, 28-Pin Flash, 8-bit Microcontrollers
4: DS41341
PIC16(L)F72X Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers
Debug(1)
CCP
SSP (I2C/SPI)
AUSART
Timers
(8/16-bit)
CapSense (ch)
8-bit ADC (ch)
I/O’s(2)
High-Endurance Flash
Memory (bytes)
Data SRAM
(bytes)
Program Memory
Flash (words)
Device
Data Sheet Index
PIC16(L)F72X Family Types
I
I
I
I
I
I
I
I
I
I
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
Pin Diagrams – 28-PIN PDIP/SOIC/SSOP/QFN/UQFN (PIC16F722/723/726/PIC16LF722/723/726)
PDIP, SOIC, SSOP
1
28
RB7/ICSPDAT
2
27
RB6/ICSPCLK
AN1/RA1
3
26
RB5/AN13/CPS5/T1G
AN2/RA2
4
25
RB4/AN11/CPS4
24
23
RB3/AN9/CPS3/CCP2(1)
22
21
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
20
VDD
19
VREF/AN3/RA3
5
T0CKI/CPS6/RA4
6
VCAP(3)/SS(2)/CPS7/AN4/RA5
7
VSS
8
CLKIN/OSC1/RA7
9
PIC16F722/723/726/
PIC16LF722/723/726
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
RB2/AN8/CPS2
(1)
CCP2 /T1OSI/RC1
12
17
RC6/TX/CK
CCP1/RC2
SCL/SCK/RC3
13
16
RC5/SDO
14
15
RC4/SDI/SDA
T1CKI/T1OSO/RC0
11
RA1/AN1
RA0/AN0/SS(2)/VCAP(3)
10
28
27
26
25
24
23
22
QFN, UQFN
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/CPS5/T1G
RB4/AN11/CPS4
18
VSS
RC7/RX/DT
VCAP(3)/CLKOUT/OSC2/RA6
1
2
3
PIC16F722/723/726/
4 PIC16LF722/723/726
5
6
7
21
20
19
18
17
16
15
RB3/AN9/CPS3/CCP2(1)
RB2/AN8/CPS2
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
VDD
VSS
RC7/RX/DT
CCP1/RC2
SCL/SCK/RC3
SDA/SDI/RC4
SDO/RC5
CK/TX/RC6
T1CKI/T1OSO/RC0
CCP2(1)/T1OSI/RC1
8
9
10
11
12
13
14
AN2/RA2
VREF/AN3/RA3
T0CKI/CPS6/RA4
VCAP(3)/SS(2)/CPS7/AN4/RA5
VSS
CLKIN/OSC1/RA7
VCAP(3)/CLKOUT/OSC2/RA6
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F722/723/726 devices only.
2007-2015 Microchip Technology Inc.
DS40001341F-page 3
PIC16(L)F722/3/4/6/7
TABLE 1:
28-PIN PDIP/SOIC/SSOP/QFN/UQFN SUMMARY (PIC16F722/723/726/PIC16LF722/723/
726)
I/O
28-Pin
PDIP,
SOIC,
SSOP
28-Pin
QFN,
UQFN
A/D
Cap Sensor
Timers
CCP
AUSART
SSP
RA0
2
27
AN0
—
—
—
—
SS(3)
—
—
VCAP(4)
RA1
3
28
AN1
—
—
—
—
—
—
—
—
RA2
4
1
AN2
—
—
—
—
—
—
—
—
RA3
5
2
AN3/VREF
—
—
—
—
—
—
—
—
Interrupt Pull-Up
Basic
RA4
6
3
—
CPS6
T0CKI
—
—
—
—
—
—
RA5
7
4
AN4
CPS7
—
—
—
SS(3)
—
—
VCAP(4)
RA6
10
7
—
—
—
—
—
—
—
—
OSC2/CLKOUT/VCAP(4)
RA7
9
6
—
—
—
—
—
—
—
—
OSC1/CLKIN
RB0
21
18
AN12
CPS0
—
—
—
—
IOC/INT
Y
—
RB1
22
19
AN10
CPS1
—
—
—
—
IOC
Y
—
—
RB2
23
20
AN8
CPS2
—
—
—
—
IOC
Y
RB3
24
21
AN9
CPS3
—
CCP2(2)
—
—
IOC
Y
—
RB4
25
22
AN11
CPS4
—
—
—
—
IOC
Y
—
RB5
26
23
AN13
CPS5
T1G
—
—
—
IOC
Y
—
RB6
27
24
—
—
—
—
—
—
IOC
Y
ICSPCLK/ICDCLK
ICSPDAT/ICDDAT
RB7
28
25
—
—
—
—
—
—
IOC
Y
RC0
11
8
—
—
T1OSO/T1CKI
—
—
—
—
—
—
RC1
12
9
—
—
T1OSI
CCP2(2)
—
—
—
—
—
RC2
13
10
—
—
—
CCP1
—
—
—
—
—
RC3
14
11
—
—
—
—
—
SCK/SCL
—
—
—
—
—
SDI/SDA
—
—
—
—
—
—
SDO
—
—
—
RC4
15
12
—
—
RC5
16
13
—
—
RC6
17
14
—
—
—
—
TX/CK
—
—
—
—
RC7
18
15
—
—
—
—
RX/DT
—
—
—
—
RE3
1
26
—
—
—
—
—
—
—
Y(1)
MCLR/VPP
—
20
17
—
—
—
—
—
—
—
—
VDD
—
8,19
5,16
—
—
—
—
—
—
—
—
VSS
Note
1:
2:
3:
4:
Note:
Pull-up enabled only with external MCLR Configuration.
RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
PIC16F724/727/PIC16LF724/727 devices only.
The PIC16F722/3/4/6/7 devices have an internal low dropout voltage regulator. An external capacitor must
be connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF722/3/4/6/7 devices do not have the
voltage regulator and therefore no external capacitor is required.
DS40001341F-page 4
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
Pin Diagrams – 40-PIN PDIP (PIC16F724/727/PIC16LF724/727)
1
40
RB7/ICSPDAT
2
39
RB6/ICSPCLK
AN1/RA1
3
38
RB5/AN13/CPS5/T1G
AN2/RA2
4
37
RB4/AN11/CPS4
VREF/AN3/RA3
5
36
RB3/AN9/CPS3/CCP2(1)
T0CKI/CPS6/RA4
6
35
RB2/AN8/CPS2
/CPS7/AN4/RA5
AN5/RE0
7
34
33
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
AN6/RE1
9
32
VDD
AN7/RE2
10
31
VSS
VDD
11
30
RD7/CPS15
VSS
12
29
RD6/CPS14
(3)
(2)
/SS
8
PIC16F724/727/
PIC16LF724/727
VCAP
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
CLKIN/OSC1/RA7
13
28
RD5/CPS13
VCAP(3)/CLKOUT/OSC2/RA6
14
27
RD4/CPS12
T1CKI/T1OSO/RC0
15
26
RC7/RX/DT
CCP2(1)/T1OSI/RC1
16
25
RC6/TX/CK
CCP1/RC2
SCL/SCK/RC3
17
24
RC5/SDO
18
23
CPS8/RD0
19
22
RC4/SDI/SDA
RD3/CPS11
CPS9/RD1
20
21
RD2/CPS10
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F724/727 devices only.
2007-2015 Microchip Technology Inc.
DS40001341F-page 5
PIC16(L)F722/3/4/6/7
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
NC
Pin Diagrams – 44-PIN TQFP (PIC16F724/727/PIC16LF724/727)
PIC16F724/727/
PIC16LF724/727
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
RA6/OSC2/CLKOUT/VCAP(3)
RA7/OSC1/CLKIN
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP(3)
RA4/CPS6/T0CKI
NC
NC
CPS4/AN11/RB4
T1G/CPS5/AN13/RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
CPS15/RD7
VSS
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
CCP2(1)/CPS3/AN9/RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F724/727 devices only.
DS40001341F-page 6
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
PIC16F724/727/
PIC16LF724/727
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
RA6/OSC2/CLKOUT/VCAP(3)
RA7/OSC1/CLKIN
VSS
VSS
NC
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP(3)
RA4/CPS6/T0CKI
CCP2(1)/CPS3/AN9/RB3
NC
CPS4/AN11/RB4
T1G/CPS5/AN13/RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
CPS15/RD7
VSS
VDD
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T1CKI
Pin Diagrams – 44-PIN QFN (PIC16F724/727/PIC16LF724/727)
Note 1:CCP2 pin location may be selected as RB3 or RC1.
2: SS pin location may be selected as RA5 or RA0.
3: PIC16F724/727 devices only.
2007-2015 Microchip Technology Inc.
DS40001341F-page 7
PIC16(L)F722/3/4/6/7
40/44-PIN PDIP/TQFP/QFN SUMMARY (PIC16F724/727/PIC16LF724/727)
TABLE 2:
I/O
40-Pin
PDIP
44-Pin
TQFP
44-Pin
QFN
A/D
Cap
Sensor
Timers
CCP
AUSART
SSP
RA0
2
19
19
AN0
—
—
—
—
SS(3)
—
—
VCAP(4)
RA1
3
20
20
AN1
—
—
—
—
—
—
—
—
RA2
4
21
21
AN2
—
—
—
—
—
—
—
—
RA3
5
22
22
AN3/VREF
—
—
—
—
—
—
—
—
RA4
6
23
23
—
CPS6
T0CKI
—
—
—
—
—
—
RA5
7
24
24
AN4
CPS7
—
—
—
SS(3)
—
—
VCAP(4)
RA6
14
31
33
—
—
—
—
—
—
—
—
OSC2/CLKOUT/VCAP(4)
RA7
13
30
32
—
—
—
—
—
—
—
—
OSC1/CLKIN
RB0
33
8
9
AN12
CPS0
—
—
—
—
IOC/INT
Y
—
RB1
34
9
10
AN10
CPS1
—
—
—
—
IOC
Y
—
—
Interrupt Pull-Up
Basic
RB2
35
10
11
AN8
CPS2
—
—
—
—
IOC
Y
RB3
36
11
12
AN9
CPS3
—
CCP2(2)
—
—
IOC
Y
—
RB4
37
14
14
AN11
CPS4
—
—
—
—
IOC
Y
—
RB5
38
15
15
AN13
CPS5
T1G
—
—
—
IOC
Y
—
RB6
39
16
16
—
—
—
—
—
—
IOC
Y
ICSPCLK/ICDCLK
RB7
40
17
17
—
—
—
—
—
—
IOC
Y
ICSPDAT/ICDDAT
RC0
15
32
34
—
—
T1OSO/
T1CKI
—
—
—
—
—
—
—
RC1
16
35
35
—
—
T1OSI
CCP2(2)
—
—
—
—
RC2
17
36
36
—
—
—
CCP1
—
—
—
—
—
RC3
18
37
37
—
—
—
—
—
SCK/SCL
—
—
—
RC4
23
42
42
—
—
—
—
SDI/SDA
—
—
—
RC5
24
43
43
—
—
—
—
SDO
—
—
—
RC6
25
44
44
—
—
—
—
TX/CK
—
—
—
—
RC7
26
1
1
—
—
—
—
RX/DT
—
—
—
—
RD0
19
38
38
—
CPS8
—
—
—
—
—
—
—
RD1
20
39
39
—
CPS9
—
—
—
—
—
—
—
RD2
21
40
40
—
CPS10
—
—
—
—
—
—
—
RD3
22
41
41
—
CPS11
—
—
—
—
—
—
—
RD4
27
2
2
—
CPS12
—
—
—
—
—
—
—
RD5
28
3
3
—
CPS13
—
—
—
—
—
—
—
RD6
29
4
4
—
CPS14
—
—
—
—
—
—
—
RD7
30
5
5
—
CPS15
—
—
—
—
—
—
—
RE0
8
25
25
AN5
—
—
—
—
—
—
—
—
RE1
9
26
26
AN6
—
—
—
—
—
—
—
—
RE2
10
27
27
AN7
—
—
—
—
—
—
—
—
RE3
1
18
18
—
—
—
—
—
—
—
Y(1)
MCLR/VPP
—
11,32
7,28
7,8,28
—
—
—
—
—
—
—
—
VDD
—
12,13
6,29
6,30,31
—
—
—
—
—
—
—
—
VSS
Note
1:
2:
3:
4:
Note:
Pull-up enabled only with external MCLR configuration.
RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
PIC16F722/3/4/6/7 devices only.
The PIC16F722/3/4/6/7 devices have an internal low dropout voltage regulator. An external capacitor must
be connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF722/3/4/6/7 devices do not have the
voltage regulator and therefore no external capacitor is required.
DS40001341F-page 8
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
Table of Contents
Device Overview ................................................................................................................................................................................. 11
Memory Organization .......................................................................................................................................................................... 17
Resets ................................................................................................................................................................................................. 30
Interrupts ............................................................................................................................................................................................. 40
Low Dropout (LDO) Voltage Regulator ............................................................................................................................................... 49
I/O Ports .............................................................................................................................................................................................. 50
Oscillator Module ................................................................................................................................................................................ 85
Device Configuration ........................................................................................................................................................................... 91
Analog-to-Digital Converter (ADC) Module ......................................................................................................................................... 94
Fixed Voltage Reference .................................................................................................................................................................. 104
Timer0 Module .................................................................................................................................................................................. 105
Timer1 Module with Gate Control ..................................................................................................................................................... 108
Timer2 Module .................................................................................................................................................................................. 120
Capacitive Sensing Module .............................................................................................................................................................. 122
Capture/Compare/PWM (CCP) Module ............................................................................................................................................ 128
Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .................................................................... 138
SSP Module Overview ...................................................................................................................................................................... 159
Program Memory Read ..................................................................................................................................................................... 181
Power-Down Mode (Sleep) ............................................................................................................................................................... 184
In-Circuit Serial Programming™ (ICSP™) ........................................................................................................................................ 186
Instruction Set Summary ................................................................................................................................................................... 187
Development Support ....................................................................................................................................................................... 196
Electrical Specifications .................................................................................................................................................................... 200
DC and AC Characteristics Graphs and Charts ................................................................................................................................ 228
Packaging Information ...................................................................................................................................................................... 263
Appendix A: Data Sheet Revision History ......................................................................................................................................... 277
Appendix B: Migrating From Other PIC® Devices ............................................................................................................................ 277
The Microchip Website ..................................................................................................................................................................... 278
Customer Change Notification Service ............................................................................................................................................. 278
Customer Support ............................................................................................................................................................................. 278
Product Identification System ........................................................................................................................................................... 279
2007-2015 Microchip Technology Inc.
DS40001341F-page 9
PIC16(L)F722/3/4/6/7
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS40001341F-page 10
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
1.0
DEVICE OVERVIEW
The PIC16(L)F722/3/4/6/7 devices are covered by this
data sheet. They are available in 28/40/44-pin packages. Figure 1-1 shows a block diagram of the
PIC16F722/723/726/PIC16LF722/723/726
devices
and Figure 1-2 shows a block diagram of the
PIC16F724/727/PIC16LF724/727 devices. Table 1-1
shows the pinout descriptions.
2007-2015 Microchip Technology Inc.
DS40001341F-page 11
PIC16(L)F722/3/4/6/7
FIGURE 1-1:
PIC16F722/723/726/PIC16LF722/723/726 BLOCK DIAGRAM
PORTA
Configuration
13
Program Counter
Flash
Program
Memory
Program
Bus
8 Level Stack
(13-bit)
14
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
8
Data Bus
RAM
PORTB
9
RAM Addr
Addr MUX
Instruction
Instruction Reg
reg
7
Direct Addr
8
Indirect
Addr
FSR
FSR Reg
reg
STATUS
STATUS Reg
reg
PORTC
8
3
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode
Decodeand
&
Control
OSC2/CLKOUT
Timing
Generation
MUX
PORTE
8
RE3
Watchdog
Timer
Brown-out
Reset
LDO(1)
Regulator
Internal
Oscillator
Block
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
ALU
Power-on
Reset
OSC1/CLKIN
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
W
W Reg
reg
CCP1
CCP1
MCLR VDD
VSS
CCP2
CCP2
T1OSI
T1OSO
Timer1
32 kHz
Oscillator
TX/CK RX/DT
T0CKI
Timer0
VREF
T1G
SDI/ SCK/
SDO SDA SCL
SS
T1CKI
Timer1
Timer2
AUSART
AUSART
Synchronous
Serial Port
Analog-To-Digital Converter
Capacitive Sensing Module
AN0 AN1 AN2 AN3 AN4 AN8 AN9 AN10 AN11 AN12 AN13
CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS6 CPS7
Note
1:
PIC16F722/723/726 only.
DS40001341F-page 12
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 1-2:
PIC16F724/727/PIC16LF724/727 BLOCK DIAGRAM
PORTA
Configuration
13
Program Counter
Flash
Program
Memory
Program
Bus
8 Level Stack
(13-bit)
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
8
Data Bus
RAM
14
PORTB
9
RAM Addr
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Addr MUX
Instruction
Instruction Reg
reg
7
Direct Addr
8
Indirect
Addr
FSR reg
Reg
FSR
STATUS
STATUS Reg
reg
8
3
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode
Decodeand
&
Control
OSC2/CLKOUT
Timing
Generation
MUX
PORTD
8
Watchdog
Timer
Brown-out
Reset
LDO(1)
Regulator
Internal
Oscillator
Block
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
ALU
Power-on
Reset
OSC1/CLKIN
PORTC
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
W Reg
CCP1
CCP1
PORTE
RE0
MCLR VDD
T1OSI
T1OSO
T0CKI
Timer0
VREF
VSS
RE1
CCP2
CCP2
RE3
Timer1
32 kHz
Oscillator
T1G
RE2
TX/CK RX/DT
SDI/ SCK/
SDO SDA SCL SS
AUSART
Synchronous
Serial Port
T1CKI
Timer1
Timer2
Analog-To-Digital Converter
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13
Capacitive Sensing Module
CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS6 CPS7 CPS8 CPS9 CPS10 CPS11 CPS12 CPS13 CPS14 CPS15
Note
1:
PIC16F724/727 only.
2007-2015 Microchip Technology Inc.
DS40001341F-page 13
PIC16(L)F722/3/4/6/7
TABLE 1-1:
PIC16(L)F722/3/4/6/7 PINOUT DESCRIPTION
Name
RA0/AN0/SS/VCAP
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/CPS6/T0CKI
RA5/AN4/CPS7/SS/VCAP
RA6/OSC2/CLKOUT/VCAP
RA7/OSC1/CLKIN
RB0/AN12/CPS0/INT
RB1/AN10/CPS1
RB2/AN8/CPS2
RB3/AN9/CPS3/CCP2
Function
Input
Type
Output
Type
RA0
TTL
CMOS
General purpose I/O.
AN0
AN
—
A/D Channel 0 input.
SS
ST
—
VCAP
Power
Power
Slave Select input.
Filter capacitor for Voltage Regulator (PIC16F72X only).
RA1
TTL
CMOS
General purpose I/O.
AN1
AN
—
A/D Channel 1 input.
RA2
TTL
CMOS
General purpose I/O.
AN2
AN
—
A/D Channel 2 input.
RA3
TTL
CMOS
General purpose I/O.
AN3
AN
—
A/D Channel 3 input.
A/D Voltage Reference input.
VREF
AN
—
RA4
TTL
CMOS
CPS6
AN
—
Capacitive sensing input 6.
T0CKI
ST
—
Timer0 clock input.
RA5
TTL
CMOS
General purpose I/O.
AN4
AN
—
A/D Channel 4 input.
CPS7
AN
—
Capacitive sensing input 7.
SS
ST
—
Slave Select input.
VCAP
Power
Power
RA6
TTL
CMOS
General purpose I/O.
OSC2
—
XTAL
Crystal/Resonator (LP, XT, HS modes).
CLKOUT
—
CMOS
FOSC/4 output.
VCAP
Power
Power
Filter capacitor for Voltage Regulator (PIC16F72X only).
RA7
TTL
CMOS
OSC1
XTAL
—
Crystal/Resonator (LP, XT, HS modes).
CLKIN
CMOS
—
External clock input (EC mode).
RC oscillator connection (RC mode).
CLKIN
ST
—
RB0
TTL
CMOS
General purpose I/O.
Filter capacitor for Voltage Regulator (PIC16F72X only).
General purpose I/O.
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
AN12
AN
—
CPS0
AN
—
Capacitive sensing input 0.
INT
ST
—
External interrupt.
RB1
TTL
CMOS
A/D Channel 12 input.
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
AN10
AN
—
A/D Channel 10 input.
CPS1
AN
—
Capacitive sensing input 1.
RB2
TTL
CMOS
AN8
AN
—
A/D Channel 8 input.
Capacitive sensing input 2.
CPS2
AN
—
RB3
TTL
CMOS
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
AN9
AN
—
CPS3
AN
—
Capacitive sensing input 3.
CCP2
ST
CMOS
Capture/Compare/PWM2.
Legend: AN = Analog input or output
TTL = TTL compatible input
HV = High Voltage
DS40001341F-page 14
Description
A/D Channel 9 input.
CMOS = CMOS compatible input or output
OD
ST
= Schmitt Trigger input with CMOS levels I2C
XTAL = Crystal levels
= Open Drain
= Schmitt Trigger input with I2C
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 1-1:
PIC16(L)F722/3/4/6/7 PINOUT DESCRIPTION (CONTINUED)
Name
Function
Input
Type
Output
Type
RB4
TTL
CMOS
RB4/AN11/CPS4
Description
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
AN11
AN
—
A/D Channel 11 input.
CPS4
AN
—
Capacitive sensing input 4.
RB5
TTL
CMOS
AN13
AN
—
CPS5
AN
—
Capacitive sensing input 5.
T1G
ST
—
Timer1 Gate input.
RB6
TTL
CMOS
RB5/AN13/CPS5/T1G
RB6/ICSPCLK/ICDCLK
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
A/D Channel 13 input.
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
ICSPCLK
ST
—
Serial Programming Clock.
ICDCLK
ST
—
In-Circuit Debug Clock.
RB7
TTL
CMOS
ICSPDAT
ST
CMOS
ICDDAT
ST
—
RC0
ST
CMOS
General purpose I/O.
T1OSO
XTAL
XTAL
Timer1 oscillator connection.
RB7/ICSPDAT/ICDDAT
RC0/T1OSO/T1CKI
General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
ICSP™ Data I/O.
In-Circuit Data I/O.
T1CKI
ST
—
RC1
ST
CMOS
General purpose I/O.
T1OSI
XTAL
XTAL
Timer1 oscillator connection.
CCP2
ST
CMOS
Capture/Compare/PWM2.
RC2
ST
CMOS
General purpose I/O.
CCP1
ST
CMOS
Capture/Compare/PWM1.
General purpose I/O.
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Timer1 clock input.
RC3
ST
CMOS
SCK
ST
CMOS
SPI clock.
SCL
I2C
OD
I2C clock.
RC4
ST
CMOS
General purpose I/O.
SDI
ST
—
SPI data input.
SDA
I2C
OD
I2C data input/output.
RC5
ST
CMOS
General purpose I/O.
SDO
—
CMOS
SPI data output.
RC6
ST
CMOS
General purpose I/O.
TX
—
CMOS
USART asynchronous transmit.
CK
ST
CMOS
USART synchronous clock.
RC7
ST
CMOS
General purpose I/O.
RX
ST
—
DT
ST
CMOS
USART synchronous data.
RD0
ST
CMOS
General purpose I/O.
CPS8
AN
—
RD0/CPS8
RD1/CPS9
RD1
ST
CMOS
CPS9
AN
—
RD2
ST
CMOS
CPS10
AN
—
RD2/CPS10
Legend: AN = Analog input or output
TTL = TTL compatible input
HV = High Voltage
2007-2015 Microchip Technology Inc.
USART asynchronous input.
Capacitive sensing input 8.
General purpose I/O.
Capacitive sensing input 9.
General purpose I/O.
Capacitive sensing input 10.
CMOS = CMOS compatible input or output
OD
ST
= Schmitt Trigger input with CMOS levels I2C
XTAL = Crystal levels
= Open Drain
= Schmitt Trigger input with I2C
DS40001341F-page 15
PIC16(L)F722/3/4/6/7
TABLE 1-1:
PIC16(L)F722/3/4/6/7 PINOUT DESCRIPTION (CONTINUED)
Name
RD3/CPS11
RD4/CPS12
RD5/CPS13
RD6/CPS14
RD7/CPS15
RE0/AN5
RE1/AN6
RE2/AN7
RE3/MCLR/VPP
Function
Input
Type
Output
Type
RD3
ST
CMOS
CPS11
AN
—
RD4
ST
CMOS
CPS12
AN
—
RD5
ST
CMOS
CPS13
AN
—
RD6
ST
CMOS
CPS14
AN
—
RD7
ST
CMOS
CPS15
AN
—
RE0
ST
CMOS
General purpose I/O.
AN5
AN
—
A/D Channel 5 input.
RE1
ST
CMOS
General purpose I/O.
AN6
AN
—
A/D Channel 6 input.
RE2
ST
CMOS
General purpose I/O.
AN7
AN
—
A/D Channel 7 input.
RE3
TTL
—
General purpose input.
Description
General purpose I/O.
Capacitive sensing input 11.
General purpose I/O.
Capacitive sensing input 12.
General purpose I/O.
Capacitive sensing input 13.
General purpose I/O.
Capacitive sensing input 14.
General purpose I/O.
Capacitive sensing input 15.
MCLR
ST
—
Master Clear with internal pull-up.
VPP
HV
—
Programming voltage.
VDD
VDD
Power
—
Positive supply.
VSS
VSS
Power
—
Ground reference.
Legend: AN = Analog input or output
TTL = TTL compatible input
HV = High Voltage
Note:
CMOS = CMOS compatible input or output
OD
ST
= Schmitt Trigger input with CMOS levels I2C
XTAL = Crystal levels
= Open Drain
= Schmitt Trigger input with I2C
The PIC16F722/3/4/6/7 devices have an internal low dropout voltage regulator. An external capacitor must
be connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF722/3/4/6/7 devices do not have the
voltage regulator and therefore no external capacitor is required.
DS40001341F-page 16
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
2.0
MEMORY ORGANIZATION
2.1
Program Memory Organization
The PIC16(L)F722/3/4/6/7 has a 13-bit program
counter capable of addressing a 2K x 14 program
memory
space
for
the
PIC16F722/LF722
(0000h-07FFh), a 4K x 14 program memory space for
the
PIC16F723/LF723
and
PIC16F724/LF724
(0000h-0FFFh) and an 8K x 14 program memory space
for the PIC16F726/LF726 and PIC16F727/LF727
(0000h-1FFFh). Accessing a location above the
memory boundaries for the PIC16F722/LF722 will
cause a wrap-around within the first 2K x 14 program
memory space. Accessing a location above the
memory boundaries for the PIC16F723/LF723 and
PIC16F724/LF724 will cause a wrap-around within the
first 4K x 14 program memory space. The Reset vector
is at 0000h and the interrupt vector is at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F722/LF722
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F723/LF723 AND
PIC16F724/LF724
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
On-chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Page 1
PC
CALL, RETURN
RETFIE, RETLW
0FFFh
1000h
13
Wraps to Page 0
17FFh
1800h
Stack Level 1
Stack Level 2
Wraps to Page 1
1FFFh
Stack Level 8
On-chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Wraps to Page 0
0FFFh
1000h
Wraps to Page 0
17FFh
1800h
Wraps to Page 0
1FFFh
2007-2015 Microchip Technology Inc.
DS40001341F-page 17
PIC16(L)F722/3/4/6/7
FIGURE 2-3:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F726/LF726 AND
PIC16F727/LF727
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
On-chip
Program
Memory
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
RP1
RP0
0
0
Bank 0 is selected
0
1
Bank 1 is selected
1
0
Bank 2 is selected
1
1
Bank 3 is selected
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
2.2.1
Page 1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
1FFFh
Data Memory Organization
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 128 x 8 bits in the
PIC16F722/LF722, 192 x 8 bits in the PIC16F723/LF723
and PIC16F724/LF724, and 368 x 8 bits in the
PIC16F726/LF726 and PIC16F727/LF727. Each
register is accessed either directly or indirectly through
the File Select Register (FSR), (Refer to Section 2.5
“Indirect Addressing, INDF and FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (refer to Table 2-1).
These registers are static RAM.
The Special Function Registers can be classified into
two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
DS40001341F-page 18
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 2-4:
PIC16F722/LF722 SPECIAL FUNCTION REGISTERS
File Address
Indirect addr.(*)
00h
Indirect addr.(*)
80h
Indirect addr.(*)
100h
Indirect addr.(*)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
104h
FSR
04h
FSR
84h
05h
TRISA
85h
105h
FSR
ANSELA
184h
PORTA
PORTB
06h
TRISB
86h
106h
ANSELB
186h
PORTC
07h
TRISC
87h
107h
187h
188h
08h
88h
CPSCON0
108h
185h
189h
PORTE
09h
TRISE
89h
CPSCON1
109h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
PMDATL
10Ch
PMCON1
18Ch
PIR2
0Dh
PIE2
8Dh
PMADRL
10Dh
Reserved
18Dh
TMR1L
0Eh
PCON
8Eh
PMDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
T1GCON
8Fh
PMADRH
10Fh
Reserved
T1CON
10h
OSCCON
90h
110h
190h
18Fh
TMR2
11h
OSCTUNE
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
SSPBUF
13h
SSPADD/SSPMSK 93h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
CCPR1L
15h
WPUB
95h
115h
195h
CCPR1H
16h
IOCB
96h
116h
196h
CCP1CON
17h
97h
117h
197h
RCSTA
18h
TXSTA
98h
118h
198h
TXREG
19h
SPBRG
99h
119h
199h
RCREG
1Ah
9Ah
11Ah
19Ah
CCPR2L
1Bh
9Bh
11Bh
19Bh
CCPR2H
1Ch
APFCON
9Ch
11Ch
19Ch
CCP2CON
1Dh
FVRCON
9Dh
11Dh
19Dh
ADRES
1Eh
9Eh
11Eh
19Eh
ADCON0
1Fh
9Fh
11Fh
19Fh
A0h
120h
1A0h
EFh
16Fh
1EFh
F0h
170h
1F0h
ADCON1
20h
General
Purpose
Register
32 Bytes
General
Purpose
Register
96 Bytes
BFh
C0h
Accesses
70h-7Fh
7Fh
Bank 0
Legend:
*
Accesses
70h-7Fh
FFh
Bank 1
Accesses
70h-7Fh
17Fh
Bank 2
1FFh
Bank 3
= Unimplemented data memory locations, read as ‘0’.
= Not a physical register.
2007-2015 Microchip Technology Inc.
DS40001341F-page 19
PIC16(L)F722/3/4/6/7
FIGURE 2-5:
PIC16F723/LF723 AND PIC16F724/LF724 SPECIAL FUNCTION REGISTERS
File Address
Indirect addr.(*)
00h
Indirect addr.(*)
80h
Indirect addr.(*)
100h
Indirect addr.(*)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
104h
FSR
04h
FSR
84h
05h
TRISA
85h
105h
FSR
ANSELA
184h
PORTA
PORTB
06h
TRISB
86h
106h
ANSELB
186h
PORTC
07h
TRISC
87h
107h
PORTD(1)
08h
TRISD(1)
88h
CPSCON0
185h
187h
108h
ANSELD(1)
109h
ANSELE(1)
189h
10Ah
PCLATH
18Ah
188h
PORTE
09h
TRISE
89h
CPSCON1
PCLATH
0Ah
PCLATH
8Ah
PCLATH
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
PMDATL
10Ch
PMCON1
18Ch
PIR2
0Dh
PIE2
8Dh
PMADRL
10Dh
Reserved
18Dh
TMR1L
0Eh
PCON
8Eh
PMDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
T1GCON
8Fh
PMADRH
10Fh
Reserved
T1CON
10h
OSCCON
90h
110h
190h
18Fh
TMR2
11h
OSCTUNE
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
SSPBUF
13h
SSPADD/SSPMSK 93h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
CCPR1L
15h
WPUB
95h
115h
195h
CCPR1H
16h
IOCB
96h
116h
196h
CCP1CON
17h
97h
117h
197h
RCSTA
18h
TXSTA
98h
118h
198h
TXREG
19h
SPBRG
99h
119h
199h
RCREG
1Ah
9Ah
11Ah
19Ah
CCPR2L
1Bh
9Bh
11Bh
19Bh
CCPR2H
1Ch
APFCON
9Ch
11Ch
19Ch
CCP2CON
1Dh
FVRCON
9Dh
11Dh
19Dh
ADRES
1Eh
9Eh
11Eh
19Eh
ADCON0
1Fh
9Fh
11Fh
19Fh
A0h
General Purpose 120h
Register
16 Bytes
12Fh
130h
1A0h
ADCON1
20h
General
Purpose
Register
80 Bytes
General
Purpose
Register
96 Bytes
EFh
Accesses
70h-7Fh
Bank 1
1EFh
16Fh
Accesses
70h-7Fh
FFh
7Fh
Bank 0
F0h
170h
Accesses
70h-7Fh
17Fh
Bank 2
1F0h
1FFh
Bank 3
Legend:
= Unimplemented data memory locations, read as ‘0’.
* = Not a physical register.
Note 1: PORTD, TRISD, ANSELD and ANSELE are not implemented on the PIC16F723/LF723, read as ‘0’
DS40001341F-page 20
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 2-6:
PIC16F726/LF726 AND PIC16F727/LF727 SPECIAL FUNCTION REGISTERS
File Address
Indirect addr.(*)
00h
Indirect addr.(*)
80h
Indirect addr.(*)
100h
Indirect addr.(*)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
104h
184h
FSR
04h
FSR
84h
PORTA
05h
TRISA
85h
105h
FSR
ANSELA
PORTB
06h
TRISB
86h
106h
ANSELB
PORTC
07h
TRISC
87h
107h
PORTD(1)
08h
TRISD(1)
88h
CPSCON0
108h
ANSELD(1)
PORTE
09h
TRISE
89h
CPSCON1
109h
ANSELE(1)
189h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
PMDATL
10Ch
PMCON1
18Ch
PIR2
0Dh
PIE2
8Dh
PMADRL
10Dh
Reserved
18Dh
TMR1L
0Eh
PCON
8Eh
PMDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
T1GCON
8Fh
PMADRH
10Fh
Reserved
T1CON
10h
OSCCON
90h
TMR2
11h
OSCTUNE
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
186h
187h
110h
SSPADD/SSPMSK 93h
185h
188h
18Fh
190h
SSPBUF
13h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
195h
CCPR1L
15h
WPUB
95h
115h
CCPR1H
16h
IOCB
96h
116h
CCP1CON
17h
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
SPBRG
99h
RCREG
1Ah
General
Purpose
Register
16 Bytes
9Ah
117h
118h
119h
General
Purpose
Register
16 Bytes
11Ah
196h
197h
198h
199h
19Ah
CCPR2L
1Bh
9Bh
11Bh
19Bh
CCPR2H
1Ch
APFCON
9Ch
11Ch
19Ch
CCP2CON
1Dh
FVRCON
9Dh
11Dh
19Dh
ADRES
1Eh
9Eh
11Eh
19Eh
ADCON0
1Fh
9Fh
11Fh
19Fh
A0h
120h
1A0h
ADCON1
20h
General
Purpose
Register
80 Bytes
General
Purpose
Register
96 Bytes
EFh
Accesses
70h-7Fh
Bank 0
*
Note 1:
F0h
Bank 1
General
Purpose
Register
80 Bytes
16Fh
Accesses
70h-7Fh
FFh
7Fh
Legend:
General
Purpose
Register
80 Bytes
170h
1EFh
Accesses
70h-7Fh
17Fh
Bank 2
1F0h
1FFh
Bank 3
= Unimplemented data memory locations, read as ‘0’,
= Not a physical register
PORTD, TRISD, ANSELD and ANSELE are not implemented on the PIC16F726/LF726, read as ‘0’
2007-2015 Microchip Technology Inc.
DS40001341F-page 21
PIC16(L)F722/3/4/6/7
TABLE 2-1:
Address
PIC16(L)F722/3/4/6/7 SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 0
00h(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
29,37
01h
TMR0
Timer0 Module Register
xxxx xxxx
105,37
02h(2)
PCL
Program Counter (PC) Least Significant Byte
03h(2)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0000 0000
28,37
0001 1xxx
25,37
04h(2)
FSR
xxxx xxxx
29,37
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
51,37
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
60,37
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
70,37
08h(3)
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
77,37
09h
PORTE
—
—
—
—
RE3
RE2(3)
RE1(3)
RE0(3)
---- xxxx
81,37
0Ah(1, 2)
PCLATH
—
—
—
---0 0000
28,37
0Bh(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
44,37
0Ch
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
47,37
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF
---- ---0
48,37
Indirect Data Memory Address Pointer
Write Buffer for the upper 5 bits of the Program Counter
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
113,37
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
113,37
10h
T1CON
TMR1CS1 TMR1CS0 T1CKPS1
11h
TMR2
Timer2 Module Register
T1CKPS0
T1OSCEN
T1SYNC
—
TMR1ON
0000 00-0
117,37
0000 0000
120,37
-000 0000
121,37
xxxx xxxx
161,37
0000 0000
178,37
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
xxxx xxxx
130,37
16h
CCPR1H
Capture/Compare/PWM Register (MSB)
xxxx xxxx
130,37
17h
CCP1CON
18h
RCSTA
19h
TXREG
1Ah
—
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
129,37
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
148,37
USART Transmit Data Register
0000 0000
147,37
RCREG
USART Receive Data Register
0000 0000
145,37
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx
130,37
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx
130,37
1Dh
CCP2CON
--00 0000
129,37
1Eh
ADRES
xxxx xxxx
100,37
1Fh
ADCON0
--00 0000
99,37
Legend:
Note
1:
2:
3:
4:
5:
6:
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
A/D Result Register
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
Accessible only when SSPM = 1001.
Accessible only when SSPM 1001.
This bit is always ‘1’ as RE3 is input-only.
DS40001341F-page 22
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 2-1:
Address
PIC16(L)F722/3/4/6/7 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 1
80h(2)
INDF
81h
OPTION_REG
82h(2)
PCL
83h(2)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
xxxx xxxx
29,37
PSA
PS2
PS1
PS0
1111 1111
26,37
0000 0000
28,37
TO
PD
Z
DC
C
0001 1xxx
25,37
T0SE
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
84h(2)
FSR
xxxx xxxx
29,37
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
51,37
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
60,37
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
70,37
88h(3)
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
78,37
89h
TRISE
—
—
—
—
TRISE3(6)
TRISE2(3)
TRISE1(3)
TRISE0(3)
---- 1111
81,37
8Ah
PCLATH
—
—
—
---0 0000
28,37
8Bh(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
44,37
8Ch
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
45,37
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
46,37
(1, 2)
Indirect Data Memory Address Pointer
Write Buffer for the upper 5 bits of the Program Counter
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq
27,38
8Fh
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
118,38
90h
OSCCON
—
—
IRCF1
IRCF0
ICSL
ICSS
—
—
--10 qq--
87,38
91h
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
88,38
92h
PR2
Timer2 Period Register
1111 1111
120,38
93h
SSPADD(5)
Synchronous Serial Port (I2C mode) Address Register
0000 0000
169,38
93h
SSPMSK(4)
Synchronous Serial Port (I2C mode) Address Mask Register
94h
SSPSTAT
95h
96h
97h
1111 1111
180,38
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
179,38
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
61,38
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
61,38
—
98h
TXSTA
99h
SPBRG
Unimplemented
—
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
147,38
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
149,38
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
APFCON
9Dh
FVRCON
9Eh
—
9Fh
ADCON1
Legend:
Note
1:
2:
3:
4:
5:
6:
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
50,38
FVRRDY
FVREN
—
—
—
—
ADFVR1
ADFVR0
q0-- --00
104,38
Unimplemented
—
ADCS2
ADCS1
ADCS0
—
—
ADREF1
ADREF0
—
—
0000 --00
100,38
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
Accessible only when SSPM = 1001.
Accessible only when SSPM 1001.
This bit is always ‘1’ as RE3 is input-only.
2007-2015 Microchip Technology Inc.
DS40001341F-page 23
PIC16(L)F722/3/4/6/7
TABLE 2-1:
Address
PIC16(L)F722/3/4/6/7 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 2
100h(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
29,37
101h
TMR0
Timer0 Module Register
xxxx xxxx
105,37
102h(2)
PCL
Program Counter’s (PC) Least Significant Byte
103h(2)
STATUS
104h(2)
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
0000 0000
28,37
0001 1xxx
25,37
xxxx xxxx
29,37
105h
—
Unimplemented
—
—
106h
—
Unimplemented
—
—
107h
—
Unimplemented
—
—
0--- 0000
126,38
---- 0000
127,38
---0 0000
28,37
108h
CPSCON0
CPSON
—
—
109h
CPSCON1
—
—
—
—
—
—
GIE
PEIE
T0IE
10Ah(1, 2) PCLATH
—
CPSRNG1 CPSRNG0
—
CPSCH3
CPSCH2
CPSOUT
T0XCS
CPSCH1
CPSCH0
Write Buffer for the upper 5 bits of the Program Counter
10Bh(2)
INTCON
10Ch
PMDATL
Program Memory Read Data Register Low Byte
10Dh
PMADRL
Program Memory Read Address Register Low Byte
10Eh
PMDATH
—
—
10Fh
PMADRH
—
—
INTE
RBIE
T0IF
INTF
RBIF
Program Memory Read Data Register High Byte
—
Program Memory Read Address Register High Byte
0000 000x
44,37
xxxx xxxx
181,38
xxxx xxxx
181,38
--xx xxxx
181,38
---x xxxx
181,38
Bank 3
180h(2)
INDF
181h
OPTION_REG
182h(2)
PCL
183h(2)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
xxxx xxxx
29,37
PSA
PS2
PS1
PS0
1111 1111
26,37
0000 0000
28,37
TO
PD
Z
DC
C
0001 1xxx
25,37
T0SE
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
184h(2)
FSR
185h
ANSELA
186h
ANSELB
187h
—
188h
ANSELD
ANSD7
ANSD6
ANSD5
189h(3)
ANSELE
—
—
—
18Ah(1, 2) PCLATH
—
—
—
Indirect Data Memory Address Pointer
xxxx xxxx
29,37
—
—
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
52,38
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
61,38
Unimplemented
—
—
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111
78,38
—
—
ANSE2
ANSE1
ANSE0
---- -111
82,38
---0 0000
28,37
Write Buffer for the upper 5 bits of the Program Counter
18Bh(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
44,37
18Ch
PMCON1
Reserved
—
—
—
—
—
—
RD
1--- ---0
182,38
18Dh
—
Unimplemented
—
—
18Eh
—
Unimplemented
—
—
18Fh
—
Unimplemented
—
—
Legend:
Note
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
Accessible only when SSPM = 1001.
Accessible only when SSPM 1001.
This bit is always ‘1’ as RE3 is input-only.
DS40001341F-page 24
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1:
R/W-0
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 21.0
“Instruction Set Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
STATUS: STATUS REGISTER
R/W-0
IRP
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
R/W-x
R/W-x
Z
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5
RP: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry out from the Most Significant bit of the result occurred
0 = No carry out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
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2.2.2.2
OPTION register
Note:
The OPTION register, shown in Register 2-2, is a
readable and writable register, which contains various
control bits to configure:
•
•
•
•
Timer0/WDT prescaler
External RB0/INT interrupt
Timer0
Weak pull-ups on PORTB
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting the PSA bit of the
OPTION_REG register to ‘1’. Refer to
Section 11.1.3
“Software
Programmable Prescaler”.
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual bits in the WPUB register
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS: Prescaler Rate Select bits
DS40001341F-page 26
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
2.2.2.3
PCON Register
The Power Control (PCON) register contains flag bits
(refer to Table 3-2) to differentiate between a:
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-3.
REGISTER 2-3:
PCON: POWER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-q
R/W-q
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
q = Value depends on condition
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
Note 1:
Set BOREN = 01 in the Configuration Word register for this bit to control the BOR.
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2.3
PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The high byte (PC) is not
directly readable or writable and comes from
PCLATH. On any Reset, the PC is cleared. Figure 2-7
shows the two situations for the loading of the PC. The
upper example in Figure 2-7 shows how the PC is
loaded on a write to PCL (PCLATH PCH).
The lower example in Figure 2-7 shows how the PC is
loaded during a CALL or GOTO instruction
(PCLATH PCH).
FIGURE 2-7:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
2.4
Program Memory Paging
All devices are capable of addressing a continuous 8K
word block of program memory. The CALL and GOTO
instructions provide only 11 bits of address to allow
branching within any 2K program memory page. When
doing a CALL or GOTO instruction, the upper two bits of
the address are provided by PCLATH. When
doing a CALL or GOTO instruction, the user must ensure
that the page select bits are programmed so that the
desired program memory page is addressed. If a return
from a CALL instruction (or interrupt) is executed, the
entire 13-bit PC is POPed off the stack. Therefore,
manipulation of the PCLATH bits is not required
for the RETURN instructions (which POPs the address
from the stack).
GOTO, CALL
2
PCLATH
11
OPCODE
Note:
The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH
register for any subsequent subroutine
calls or GOTO instructions.
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556, Implementing a Table Read
(DS00556).
2.3.2
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
EXAMPLE 2-1:
STACK
All devices have an 8-level x 13-bit wide hardware
stack (refer to Figures 2-1 and 2-3). The stack space is
not part of either program or data space and the Stack
Pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL instruction is executed or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
DS40001341F-page 28
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
ORG 500h
PAGESEL SUB_P1 ;Select page 1
;(800h-FFFh)
CALL
SUB1_P1 ;Call subroutine in
:
;page 1 (800h-FFFh)
:
ORG
900h
;page 1 (800h-FFFh)
SUB1_P1
:
:
RETURN
;called subroutine
;page 1 (800h-FFFh)
;return to
;Call subroutine
;in page 0
;(000h-7FFh)
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
2.5
EXAMPLE 2-2:
Indirect Addressing, INDF and
FSR Registers
MOVLW
MOVWF
BANKISEL
NEXT CLRF
INCF
BTFSS
GOTO
CONTINUE
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-8.
INDIRECT ADDRESSING
020h
FSR
020h
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
A simple program to clear RAM location 020h-02Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-8:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1
RP0
Bank Select
6
From Opcode
Indirect Addressing
0
7
IRP
Bank Select
Location Select
00
01
10
File Select Register
0
Location Select
11
00h
180h
Data
Memory
7Fh
1FFh
Bank 0
Note:
Bank 1
Bank 2
Bank 3
For memory map detail, refer to Figures 2-4 and 2-5.
2007-2015 Microchip Technology Inc.
DS40001341F-page 29
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3.0
RESETS
The PIC16(L)F722/3/4/6/7 differentiates between various kinds of Reset:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Reset (BOR)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
•
•
•
•
•
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. TO and PD bits are set or cleared differently
in different Reset situations, as indicated in Table 3-3.
These bits are used in software to determine the nature
of the Reset.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 23.0 “Electrical
Specifications” for pulse-width specifications.
Power-on Reset (POR)
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
MCLRE
MCLR/VPP
Sleep
WDT
Module
WDT
Time-out
Reset
POR
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
OSC1/
CLKIN
PWRT
WDTOSC
11-bit Ripple Counter
Enable PWRT
Enable OST
Note
1:
DS40001341F-page 30
Refer to the Configuration Word Register 1 (Register 8-1).
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 3-1:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset or LDO Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during Sleep or interrupt wake-up from Sleep
TABLE 3-2:
Condition
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
0000h
000u uuuu
---- --uu
MCLR Reset during Sleep
0000h
0001 0uuu
---- --uu
WDT Reset
0000h
0000 1uuu
---- --uu
WDT Wake-up
PC + 1
uuu0 0uuu
---- --uu
0000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Condition
Brown-out Reset
Interrupt Wake-up from Sleep
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
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3.1
MCLR
3.3
The PIC16(L)F722/3/4/6/7 has a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a Reset does not drive the
MCLR pin low.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RE3/MCLR pin
becomes an external Reset input. In this mode, the
RE3/MCLR pin has a weak pull-up to VDD. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
The Power-up Timer provides a fixed 64 ms (nominal)
time out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
oscillator. For more information, see Section 7.3
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
• VDD variation
• Temperature variation
• Process variation
See DC parameters for details
“Electrical Specifications”).
Note:
FIGURE 3-2:
RECOMMENDED MCLR
CIRCUIT
3.4
VDD
®
PIC MCU
R1
10 k
MCLR
C1
0.1 F
Power-on Reset (POR)
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for VDD is required. See
Section 23.0 “Electrical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOR (see Section 3.5
“Brown-Out Reset (BOR)”).
(Section 23.0
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
Watchdog Timer (WDT)
The WDT has the following features:
• Shares an 8-bit prescaler with Timer0
• Time-out period is from 17 ms to 2.2 seconds,
nominal
• Enabled by a Configuration bit
WDT is cleared under certain conditions described in
Table 3-1.
3.4.1
3.2
Power-up Timer (PWRT)
WDT OSCILLATOR
The WDT derives its time base from 31 kHz internal
oscillator.
Note:
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting (DS00607).
DS40001341F-page 32
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3.4.2
WDT CONTROL
The WDTE bit is located in the Configuration Word
Register 1. When set, the WDT runs continuously.
The PSA and PS bits of the OPTION register
control the WDT period. See Section 11.0 “Timer0
Module” for more information.
FIGURE 3-1:
WATCHDOG TIMER BLOCK DIAGRAM
T1GSS = 11
TMR1GE
From TMR0
Clock Source
WDTE
Low-Power
WDT OSC
0
Divide by
512
Postscaler
1
8
PS
TO TMR0
PSA
0
1
WDT Reset
To T1G
WDTE
TABLE 3-1:
WDT STATUS
Conditions
WDTE = 0
WDT
Cleared
CLRWDT Command
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
2007-2015 Microchip Technology Inc.
Cleared until the end of OST
DS40001341F-page 33
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3.5
Brown-Out Reset (BOR)
If VDD falls below VBOR for greater than parameter
(TBOR) (see Section 23.0 “Electrical Specifications”), the brown-out situation will reset the device.
This will occur regardless of VDD slew rate. A Reset is
not ensured to occur if VDD falls below VBOR for more
than TBOR.
Brown-out Reset is enabled by programming the
BOREN bits in the Configuration register. The
brown-out trip point is selectable from two trip points
via the BORV bit in the Configuration register.
Between the POR and BOR, complete voltage range
coverage for execution protection can be
implemented.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
Two bits are used to enable the BOR. When
BOREN = 11, the BOR is always enabled. When
BOREN = 10, the BOR is enabled, but disabled during
Sleep. When BOREN = 0X, the BOR is disabled.
FIGURE 3-3:
Note:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
64 ms(1)
VDD
Internal
Reset
VBOR
< 64 ms
64 ms(1)
VDD
Internal
Reset
Note 1:
When erasing Flash program memory, the
BOR is forced to enabled at the minimum
BOR setting to ensure that any code protection circuitry is operating properly.
VBOR
64 ms(1)
64 ms delay only if PWRTE bit is programmed to ‘0’.
DS40001341F-page 34
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3.6
Time-out Sequence
3.7
On power-up, the time-out sequence is as follows: first,
PWRT time out is invoked after POR has expired, then
OST is activated after the PWRT time out has expired.
The total time out will vary based on oscillator
configuration and PWRTE bit status. For example, in
EC mode with PWRTE bit = 1 (PWRT disabled), there
will be no time out at all. Figure 3-4, Figure 3-5 and
Figure 3-6 depict time-out sequences.
The Power Control (PCON) register has two Status bits
to indicate what type of Reset that last occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN = 00 in the Configuration Word register).
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 3-5). This is useful for testing purposes or
to synchronize more than one PIC16(L)F722/3/4/6/7
device operating in parallel.
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
Table 3-3 shows the Reset conditions for some special
registers.
TABLE 3-2:
Power Control (PCON) Register
For more information, see Section 3.5 “Brown-Out
Reset (BOR)”.
TIME OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
TPWRT + 1024 •
TOSC
1024 • TOSC
TPWRT + 1024 •
TOSC
1024 • TOSC
1024 • TOSC
TPWRT
—
TPWRT
—
—
Oscillator Configuration
XT, HS,
LP(1)
RC, EC, INTOSC
Note 1:
LP mode with T1OSC disabled.
TABLE 3-3:
RESET BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
u
1
1
Power-on Reset
1
0
1
1
Brown-out Reset
u
u
0
u
WDT Reset
u
u
0
0
WDT Wake-up
u
u
u
u
MCLR Reset during normal operation
u
u
1
0
MCLR Reset during Sleep
Condition
Legend: u = unchanged, x = unknown
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FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
FIGURE 3-6:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
DS40001341F-page 36
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TABLE 3-4:
Register
W
INITIALIZATION CONDITION FOR REGISTERS
Address
Power-on Reset/
Brown-out Reset(1)
MCLR Reset/
WDT Reset
Wake-up from Sleep through
Interrupt/Time out
—
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h/80h/
100h/180h
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0
01h/101h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h/
102h/182h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h/
103h/183h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h/
104h/184h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTB
06h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTC
07h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTD(6)
08h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTE
09h
---- xxxx
---- xxxx
---- uuuu
PCLATH
0Ah/8Ah/
10Ah/18Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh/
10Bh/18Bh
0000 000x
0000 000x
uuuu uuuu(2)
PIR1
0Ch
0000 0000
0000 0000
uuuu uuuu(2)
PIR2
0Dh
---- ---0
---- ---0
---- ---u
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
0000 00-0
uuuu uu-u
uuuu uu-u
TMR2
11h
0000 0000
0000 0000
uuuu uuuu
T2CON
12h
-000 0000
-000 0000
-uuu uuuu
SSPBUF
13h
xxxx xxxx
xxxx xxxx
uuuu uuuu
SSPCON
14h
0000 0000
0000 0000
uuuu uuuu
CCPR1L
15h
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR1H
16h
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP1CON
17h
--00 0000
--00 0000
--uu uuuu
RCSTA
18h
0000 000x
0000 000x
uuuu uuuu
TXREG
19h
0000 0000
0000 0000
uuuu uuuu
RCREG
1Ah
0000 0000
0000 0000
uuuu uuuu
CCPR2L
1Bh
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR2H
1Ch
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP2CON
1Dh
--00 0000
--00 0000
--uu uuuu
ADRES
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
1Fh
--00 0000
--00 0000
--uu uuuu
81h/181h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
1111 1111
1111 1111
uuuu uuuu
TRISB
86h
1111 1111
1111 1111
uuuu uuuu
TRISC
87h
1111 1111
1111 1111
uuuu uuuu
TRISD(6)
88h
1111 1111
1111 1111
uuuu uuuu
TRISE
89h
---- 1111
---- 1111
---- uuuu
PIE1
8Ch
0000 0000
0000 0000
uuuu uuuu
PIE2
8Dh
---- ---0
---- ---0
---- ---u
OPTION_REG
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 3-5 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
PIC16F724/727/PIC16LF724/727 only.
2007-2015 Microchip Technology Inc.
DS40001341F-page 37
PIC16(L)F722/3/4/6/7
TABLE 3-4:
Register
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address
Power-on Reset/
Brown-out Reset(1)
MCLR Reset/
WDT Reset
Wake-up from Sleep through
Interrupt/Time out
PCON
8Eh
---- --qq
---- --uu(1,5)
---- --uu
T1GCON
8Fh
0000 0x00
uuuu uxuu
uuuu uxuu
OSCCON
90h
--10 qq--
--10 qq--
--uu qq--
OSCTUNE
91h
--00 0000
--uu uuuu
--uu uuuu
PR2
92h
1111 1111
1111 1111
uuuu uuuu
SSPADD
93h
0000 0000
0000 0000
uuuu uuuu
SSPMSK
93h
1111 1111
1111 1111
uuuu uuuu
SSPSTAT
94h
0000 0000
0000 0000
uuuu uuuu
WPUB
95h
1111 1111
1111 1111
uuuu uuuu
IOCB
96h
0000 0000
0000 0000
uuuu uuuu
TXSTA
98h
0000 -010
0000 -010
uuuu -uuu
SPBRG
99h
0000 0000
0000 0000
uuuu uuuu
APFCON
9Ch
---- --00
---- --00
---- --uu
FVRCON
9Dh
q000 --00
q000 --00
uuuu --uu
ADCON1
9Fh
-000 --00
-000 --00
-uuu --uu
CPSCON0
108h
0--- 0000
0--- 0000
u--- uuuu
CPSCON1
109h
---- 0000
---- 0000
---- uuuu
PMDATL
10Ch
xxxx xxxx
xxxx xxxx
uuuu uuuu
PMADRL
10Dh
xxxx xxxx
xxxx xxxx
uuuu uuuu
PMDATH
10Eh
--xx xxxx
--xx xxxx
--uu uuuu
PMADRH
10Fh
---x xxxx
---x xxxx
---u uuuu
ANSELA
185h
--11 1111
--11 1111
--uu uuuu
ANSELB
186h
--11 1111
--11 1111
--uu uuuu
ANSELD(6)
188h
1111 1111
1111 1111
uuuu uuuu
ANSELE
189h
---- -111
---- -111
---- -uuu
PMCON1
18Ch
1--- ---0
1--- ---0
u--- ---u
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 3-5 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
PIC16F724/727/PIC16LF724/727 only.
DS40001341F-page 38
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 3-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
0000h
000u uuuu
---- --uu
MCLR Reset during Sleep
0000h
0001 0uuu
---- --uu
WDT Reset
0000h
0000 uuuu
---- --uu
WDT Wake-up
PC + 1
uuu0 0uuu
---- --uu
Brown-out Reset
0000h
0001 1xxx
---- --10
uuu1 0uuu
---- --uu
Condition
(1)
Interrupt Wake-up from Sleep
Legend:
Note 1:
TABLE 3-6:
Name
STATUS
PCON
Legend:
Note 1:
PC + 1
u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt
vector (0004h) after execution of PC + 1.
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR,
BOR
Value on
all other
Resets(1)
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
—
—
—
—
—
—
POR
BOR
---- --qq
---- --uu
u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by Resets.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2007-2015 Microchip Technology Inc.
DS40001341F-page 39
PIC16(L)F722/3/4/6/7
4.0
INTERRUPTS
The PIC16(L)F722/3/4/6/7 device family features an
interruptible core, allowing certain events to preempt
normal program flow. An Interrupt Service Routine
(ISR) is used to determine the source of the interrupt
and act accordingly. Some interrupts can be configured
to wake the MCU from Sleep mode.
The PIC16(L)F722/3/4/6/7 device family has 12
interrupt sources, differentiated by corresponding
interrupt enable and flag bits:
•
•
•
•
•
•
•
•
•
•
•
•
Timer0 Overflow Interrupt
External Edge Detect on INT Pin Interrupt
PORTB Change Interrupt
Timer1 Gate Interrupt
A/D Conversion Complete Interrupt
AUSART Receive Interrupt
AUSART Transmit Interrupt
SSP Event Interrupt
CCP1 Event Interrupt
Timer2 Match with PR2 Interrupt
Timer1 Overflow Interrupt
CCP2 Event Interrupt
A block diagram of the interrupt logic is shown in
Figure 4-1.
FIGURE 4-1:
INTERRUPT LOGIC
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2
IOCB2
IOC-RB3
IOCB3
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
SSPIF
SSPIE
TXIF
TXIE
RCIF
RCIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
ADIF
ADIE
TMR1GIF
TMR1GIE
Wake-up (If in Sleep mode)(1)
T0IF
T0IE
Interrupt to CPU
INTF
INTE
RBIF
RBIE
PEIE
GIE
CCP1IF
CCP1IE
CCP2IF
CCP2IE
DS40001341F-page 40
Note 1:
Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See Section 19.1
“Wake-up from Sleep”.
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
4.1
Operation
interrupt that occurs while executing the ISR will be
recorded through its Interrupt Flag, but will not cause
the processor to redirect to the interrupt vector.
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
The RETFIE instruction exits the ISR by popping the
previous address from the stack and setting the GIE bit.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 and PIE2 registers)
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual Interrupt Flag bits are set,
regardless of the state of any other
enable bits.
The INTCON, PIR1 and PIR2 registers record
individual interrupts via Interrupt Flag bits. Interrupt
Flag bits will be set, regardless of the status of the GIE,
PEIE and individual Interrupt Enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• PC is loaded with the interrupt vector 0004h
4.2
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three instruction cycles. For asynchronous
interrupts, the latency is three to four instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.
The ISR determines the source of the interrupt by
polling the Interrupt Flag bits. The Interrupt Flag bits
must be cleared before exiting the ISR to avoid
repeated interrupts. Because the GIE bit is cleared, any
FIGURE 4-2:
Interrupt Latency
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag
(INTCON)
Interrupt Latency (2)
(5)
GIE bit
(INTCON)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC – 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
—
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT is available only in INTOSC and RC Oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 23.0 “Electrical Specifications”.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
2007-2015 Microchip Technology Inc.
DS40001341F-page 41
PIC16(L)F722/3/4/6/7
4.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 19.0
“Power-Down Mode (Sleep)” for more details.
4.4
Since most instructions modify the W register, it must
be saved immediately upon entering the ISR. The
SWAPF instruction is used when saving and restoring
the W and STATUS registers because it will not affect
any bits in the STATUS register. It is useful to place
W_TEMP in shared memory because the ISR cannot
predict which bank will be selected when the interrupt
occurs.
The processor will branch to the interrupt vector by
loading the PC with 0004h. The PCLATH register will
remain unchanged. This requires the ISR to ensure
that the PCLATH register is set properly before using
an instruction that causes PCLATH to be loaded into
the PC. See Section 2.3 “PCL and PCLATH” for
details on PC operation.
INT Pin
The external interrupt, INT pin, causes an
asynchronous, edge-triggered interrupt. The INTEDG bit
of the OPTION register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the INTCON register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector. This interrupt is
disabled by clearing the INTE bit of the INTCON register.
4.5
Context Saving
When an interrupt occurs, only the return PC value is
saved to the stack. If the ISR modifies or uses an
instruction that modifies key registers, their values
must be saved at the beginning of the ISR and restored
when the ISR completes. This prevents instructions
following the ISR from using invalid data. Examples of
key registers include the W, STATUS, FSR and
PCLATH registers.
Note:
The microcontroller does not normally
require saving the PCLATH register.
However, if computed GOTO’s are used,
the PCLATH register must be saved at the
beginning of the ISR and restored when
the ISR is complete to ensure correct
program flow.
The code shown in Example 4-1 can be used to do the
following.
•
•
•
•
•
•
•
Save the W register
Save the STATUS register
Save the PCLATH register
Execute the ISR program
Restore the PCLATH register
Restore the STATUS register
Restore the W register
DS40001341F-page 42
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
EXAMPLE 4-1:
SAVING W, STATUS AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
W_TEMP
STATUS,W
BANKSEL
MOVWF
MOVF
MOVWF
:
:(ISR)
:
BANKSEL
MOVF
MOVWF
SWAPF
STATUS_TEMP
STATUS_TEMP
PCLATH,W
PCLATH_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
4.5.1
;Copy W to W_TEMP register
;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
;Select regardless of current bank
;Copy status to bank zero STATUS_TEMP register
;Copy PCLATH to W register
;Copy W register to PCLATH_TEMP
;Insert user code here
STATUS_TEMP
PCLATH_TEMP,W
PCLATH
STATUS_TEMP,W
;Select regardless of current bank
;
;Restore PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
INTCON REGISTER
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTB change and
external RB0/INT/SEG0 pin interrupts.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
2007-2015 Microchip Technology Inc.
DS40001341F-page 43
PIC16(L)F722/3/4/6/7
REGISTER 4-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE(1)
T0IF(2)
INTF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: PORTB Change Interrupt Enable bit(1)
1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt
bit 2
T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: PORTB Change Interrupt Flag bit
1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in
software)
0 = None of the PORTB general purpose I/O pins have changed state
Note 1:
2:
The appropriate bits in the IOCB register must also be set.
T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
DS40001341F-page 44
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
4.5.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 4-2.
REGISTER 4-2:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enable the Timer1 Gate Acquisition complete interrupt
0 = Disable the Timer1 Gate Acquisition complete interrupt
bit 6
ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
2007-2015 Microchip Technology Inc.
x = Bit is unknown
DS40001341F-page 45
PIC16(L)F722/3/4/6/7
4.5.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 4-3.
REGISTER 4-3:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
DS40001341F-page 46
x = Bit is unknown
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
4.5.4
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 4-4.
REGISTER 4-4:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Timer1 Gate is inactive
0 = Timer1 Gate is active
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
2007-2015 Microchip Technology Inc.
DS40001341F-page 47
PIC16(L)F722/3/4/6/7
4.5.5
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.
REGISTER 4-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
TABLE 4-1:
Name
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIR2
—
—
—
—
—
—
—
CCP2IF
---- ---0
---- ---0
OPTION_REG
Legend:
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.
DS40001341F-page 48
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
5.0
LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F722/3/4/6/7 devices differ from the
PIC16LF722/3/4/6/7 devices due to an internal Low
Dropout (LDO) voltage regulator. The PIC16F722/3/4/
6/7 devices contain an internal LDO, while the
PIC16LF722/3/4/6/7 ones do not.
The lithography of the die allows a maximum operating
voltage of 3.6V on the internal digital logic. In order to
continue to support 5.0V designs, a LDO voltage
regulator is integrated on the die. The LDO voltage
regulator allows for the internal digital logic to operate
at 3.2V, while I/O’s operate at 5.0V (VDD).
The LDO voltage regulator requires an external bypass
capacitor for stability. One of three pins, denoted as
VCAP, can be configured for the external bypass
capacitor. It is recommended that the capacitor be a
ceramic cap between 0.1 to 1.0 µF. The VCAP pin is not
intended to supply power to external loads. An external
voltage regulator should be used if this functionality is
required. In addition, external devices should not
supply power to the VCAP pin.
On power-up, the external capacitor will look like a
large load on the LDO voltage regulator. To prevent
erroneous operation, the device is held in Reset while
a constant current source charges the external
capacitor. After the cap is fully charged, the device is
released from Reset. For more information, refer to
Section 23.0 “Electrical Specifications”.
See Configuration Word 2 register (Register 8-2) for
VCAP enable bits.
2007-2015 Microchip Technology Inc.
DS40001341F-page 49
PIC16(L)F722/3/4/6/7
6.0
I/O PORTS
There are as many as 35 general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
6.1
Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 6-1. For this device family, the
following functions can be moved between different
pins.
• SS (Slave Select)
• CCP2
REGISTER 6-1:
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
SSSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’.
bit 1
SSSEL: SS Input Pin Selection bit
0 = SS function is on RA5/AN4/CPS7/SS/VCAP
1 = SS function is on RA0/AN0/SS/VCAP
bit 0
CCP2SEL: CCP2 Input/Output Pin Selection bit
0 = CCP2 function is on RC1/T1OSI/CCP2
1 = CCP2 function is on RB3/CCP2
DS40001341F-page 50
x = Bit is unknown
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
6.2
PORTA and the TRISA Registers
TRISA register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 6-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 6-1 shows how to
initialize PORTA.
Note:
The ANSELA register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
EXAMPLE 6-1:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
Reading the PORTA register (Register 6-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch.
PORTA
PORTA
ANSELA
ANSELA
TRISA
0Ch
TRISA
INITIALIZING PORTA
;
;Init PORTA
;
;digital I/O
;
;Set RA as inputs
;and set RA
;as outputs
The TRISA register (Register 6-3) controls the PORTA
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
REGISTER 6-2:
PORTA: PORTA REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
RA: PORTA I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 6-3:
TRISA: PORTA TRI-STATE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
TRISA: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
2007-2015 Microchip Technology Inc.
DS40001341F-page 51
PIC16(L)F722/3/4/6/7
6.2.1
ANSELA REGISTER
The ANSELA register (Register 6-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
REGISTER 6-4:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
ANSA: Analog Select between Analog or Digital Function on pins RA, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001341F-page 52
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
6.2.2
PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the A/D Converter (ADC), refer to the
appropriate section in this data sheet.
6.2.2.1
RA0/AN0/SS/VCAP
6.2.2.6
Figure 6-4 shows the diagram for this pin. This pin is
configurable to function as one of the following:
•
•
•
•
•
Figure 6-1 shows the diagram for this pin. This pin is
configurable to function as one of the following:
•
•
•
•
a general purpose I/O
an analog input for the ADC
a slave select input for the SSP(1)
a Voltage Regulator Capacitor pin (PIC16F72X
only)
Note:
6.2.2.2
SS pin location may be selected as RA5
or RA0.
RA1/AN1
Figure 6-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
6.2.2.3
RA2/AN2
Figure 6-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
RA5/AN4/CPS7/SS/VCAP
a general purpose I/O
an analog input for the ADC
a capacitive sensing input
a slave select input for the SSP(1)
a Voltage Regulator Capacitor pin (PIC16F72X
only)
Note:
6.2.2.7
SS pin location may be selected as RA5
or RA0.
RA6/OSC2/CLKOUT/VCAP
Figure 6-5 shows the diagram for this pin. This pin is
configurable to function as one of the following:
•
•
•
•
a general purpose I/O
a crystal/resonator connection
a clock output
a Voltage Regulator Capacitor pin (PIC16F72X
only)
6.2.2.8
RA7/OSC1/CLKIN
Figure 6-6 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a crystal/resonator connection
• a clock input
• a general purpose I/O
• an analog input for the ADC
6.2.2.4
RA3/AN3/VREF
Figure 6-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• a voltage reference input for the ADC
6.2.2.5
RA4/CPS6/T0CKI
Figure 6-3 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a capacitive sensing input
• a clock input for Timer0
The Timer0 clock input function works independently
of any TRIS register setting. Effectively, if TRISA4 = 0,
the PORTA4 register bit will output to the pad and
Clock Timer0 at the same time.
2007-2015 Microchip Technology Inc.
DS40001341F-page 53
PIC16(L)F722/3/4/6/7
FIGURE 6-1:
BLOCK DIAGRAM OF RA0
PIC16F72X only
To Voltage Regulator
VCAPEN = 00
VDD
Data Bus
D
WR
PORTA
Q
I/O Pin
CK Q
D
WR
TRISA
VSS
Q
CK Q
RD
TRISA
ANSA0
RD
PORTA
To SSP SS Input
To A/D Converter
DS40001341F-page 54
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 6-2:
RA BLOCK DIAGRAM
VDD
Data Bus
D
WR
PORTA
Q
I/O Pin
CK Q
D
WR
TRISA
VSS
Q
CK Q
RD
TRISA
ANSAx
RD
PORTA
To A/D Converter
FIGURE 6-3:
BLOCK DIAGRAM OF RA4
VDD
Data Bus
D
WR
PORTA
I/O Pin
CK Q
D
WR
TRISA
Q
Q
VSS
CK Q
RD
TRISA
ANSA4
RD
PORTA
To Timer0 Clock MUX
To Cap Sensor
2007-2015 Microchip Technology Inc.
DS40001341F-page 55
PIC16(L)F722/3/4/6/7
FIGURE 6-4:
BLOCK DIAGRAM OF RA5
PIC16F72X only
To Voltage Regulator
VCAPEN = 01
VDD
Data Bus
D
WR
PORTA
Q
I/O Pin
CK Q
D
WR
TRISA
VSS
Q
CK Q
RD
TRISA
ANSA5
RD
PORTA
To SSP SS Input
To A/D Converter
To Cap Sensor
DS40001341F-page 56
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 6-5:
BLOCK DIAGRAM OF RA6
PIC16F72X only
To Voltage Regulator
VCAPEN = 10
CLKOUT(1)
Enable
Data Bus
FOSC/4
1
Q
0
D
WR
PORTA
Oscillator
Circuit
VDD
RA7/OSC1
I/O Pin
CK Q
VSS
D
WR
TRISA
Q
CK Q
RD
TRISA
FOSC = LP or XT or HS
(00X OR 010)
RD
PORTA
Note 1: CLKOUT Enable = 1 When FOSC = RC or INTOSC (No I/O Selected).
FIGURE 6-6:
BLOCK DIAGRAM OF RA7
Oscillator
Circuit
RA6/OSC2
Data Bus
VDD
I/O Pin
D
WR
PORTA
CK Q
D
WR
TRISA
Q
Q
VSS
CK Q
RD
TRISA
OSC = INTOSC or
INTOSCIO
RD
PORTA
2007-2015 Microchip Technology Inc.
DS40001341F-page 57
PIC16(L)F722/3/4/6/7
TABLE 6-1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
0000 0000
-000 --00
Name
ADCON1
—
ADCS2
ADCS1
ADCS0
—
—
ADREF1
ADREF0
-000 --00
ANSELA
—
—
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
--11 1111
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
---- --00
CPSCON0
CPSON
—
—
—
CPSCON1
—
—
—
—
CONFIG2(1)
OPTION_REG
PORTA
SSPCON
TRISA
Legend:
Note 1:
—
—
RBPU
INTEDG
VCAPEN1 VCAPEN0
T0CS
T0SE
CPSRNG1 CPSRNG0
CPSCH3
CPSCH2
CPSOUT
T0XCS
0--- 0000
0--- 0000
CPSCH1
CPSCH0
---- 0000
---- 0000
—
—
—
—
—
—
PSA
PS2
PS1
PS0
1111 1111
1111 1111
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
xxxx xxxx
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
PIC16F72X only.
DS40001341F-page 58
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
6.3
PORTB and TRISB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISB
(Register 6-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-2 shows how to initialize PORTB.
Reading the PORTB register (Register 6-5) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
The TRISB register (Register 6-6) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’. Example 6-2 shows how to initialize PORTB.
EXAMPLE 6-2:
INITIALIZING PORTB
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
PORTB
PORTB
ANSELB
ANSELB
TRISB
B’11110000’
MOVWF
TRISB
Note:
;
;Init PORTB
;Make RB digital
;
;Set RB as inputs
;and RB as outputs
;
The ANSELB register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
6.3.1
ANSELB REGISTER
The ANSELB register (Register 6-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELB bits has no affect on digital
output functions. A pin with TRIS clear and ANSELB
set will still operate as a digital output, but the Input
mode will be analog. This can cause unexpected
behavior
when
executing
read-modify-write
instructions on the affected port.
6.3.2
WEAK PULL-UPS
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB enable or
disable each pull-up (see Register 6-7). Each weak
pull-up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RBPU bit of the OPTION register.
6.3.3
INTERRUPT-ON-CHANGE
All of the PORTB pins are individually configurable as an
interrupt-on-change pin. Control bits IOCB enable
or disable the interrupt function for each pin. Refer to
Register 6-8. The interrupt-on-change feature is
disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present value
is compared with the old value latched on the last read
of PORTB to determine which bits have changed or
mismatched the old value. The ‘mismatch’ outputs of
the last read are OR’d together to set the PORTB
Change Interrupt flag bit (RBIF) in the INTCON register.
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear the flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After these Resets, the RBIF flag will
continue to be set if a mismatch is present.
Note:
2007-2015 Microchip Technology Inc.
When a pin change occurs at the same
time as a read operation on PORTB, the
RBIF flag will always be set. If multiple
PORTB pins are configured for the
interrupt-on-change, the user may not be
able to identify which pin changed state.
DS40001341F-page 59
PIC16(L)F722/3/4/6/7
REGISTER 6-5:
PORTB: PORTB REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
RB: PORTB I/O Pin bit
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 6-6:
TRISB: PORTB TRI-STATE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
TRISB: PORTB Tri-State Control bit
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
DS40001341F-page 60
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PIC16(L)F722/3/4/6/7
REGISTER 6-7:
WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
2:
x = Bit is unknown
WPUB: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
REGISTER 6-8:
IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
IOCB: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
REGISTER 6-9:
ANSELB: PORTB ANALOG SELECT REGISTER
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
ANSB: Analog Select between Analog or Digital Function on Pins RB, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
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6.3.4
PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the SSP, I2C or interrupts, refer to the appropriate
section in this data sheet.
6.3.4.1
RB0/AN12/CPS0/INT
Figure 6-7 shows the diagram for this pin. This pin is
configurable to function as one of the following:
•
•
•
•
a general purpose I/O
an analog input for the ADC
a capacitive sensing input
an external edge triggered interrupt
6.3.4.2
RB1/AN10/CPS1
Figure 6-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• a capacitive sensing input
6.3.4.3
6.3.4.6
RB5/AN13/CPS5/T1G
Figure 6-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
•
•
•
•
a general purpose I/O
an analog input for the ADC
a capacitive sensing input
a Timer1 gate input
6.3.4.7
RB6/ICSPCLK
Figure 6-11 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• In-Circuit Serial Programming clock
6.3.4.8
RB7/ICSPDAT
Figure 6-12 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• In-Circuit Serial Programming data
RB2/AN8/CPS2
Figure 6-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• a capacitive sensing input
6.3.4.4
RB3/AN9/CPS3/CCP2
Figure 6-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
•
•
•
•
a general purpose I/O
an analog input for the ADC
a capacitive sensing input
a Capture 2 input, Compare 2 output, and PWM2
output
Note:
6.3.4.5
CCP2 pin location may be selected as
RB3 or RC1.
RB4/AN11/CPS4
Figure 6-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• a capacitive sensing input
DS40001341F-page 62
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PIC16(L)F722/3/4/6/7
FIGURE 6-7:
BLOCK DIAGRAM OF RB0
Data Bus
D
WR
WPUB
CK
Q
VDD
Q
Weak
D
WR
PORTB
Q
I/O Pin
CK Q
D
WR
TRISB
VDD
RBPU
RD
WPUB
VSS
Q
CK Q
RD
TRISB
ANSB0
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q
Q3
D
EN
Interrupt-onChange
RD PORTB
To External Interrupt Logic
To A/D Converter
To Cap Sensor
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FIGURE 6-8:
BLOCK DIAGRAM OF RB4, RB
Data Bus
D
WR
WPUB
CK
Q
Q
D
VDD
Q
I/O Pin
CK Q
D
WR
TRISB
Weak
RBPU
RD
WPUB
WR
PORTB
VDD
VSS
Q
CK Q
RD
TRISB
ANSB
RD
PORTB
D
WR
IOCB
Q
CK Q
Q
D
EN
RD
IOCB
Q
D
Q3
To A/D Converter
To Cap Sensor
EN
Interrupt-onChange
RD PORTB
DS40001341F-page 64
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PIC16(L)F722/3/4/6/7
FIGURE 6-9:
BLOCK DIAGRAM OF RB3
Data Bus
D
WR
WPUB
CK
Q
Q
Weak
CCP2OUT
Enable
VDD
RBPU
RD
WPUB
CCP2OUT
D
WR
PORTB
VDD
Q
1
0
I/O Pin
CK Q
VSS
D
WR
TRISB
Q
CK Q
RD
TRISB
ANSB
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q
Q3
D
EN
Interrupt-onChange
RD PORTB
To CCP2(1)
To A/D Converter
To Cap Sensor
Note 1:
CCP2 input is controlled by CCP2SEL in the APFCON register.
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PIC16(L)F722/3/4/6/7
FIGURE 6-10:
BLOCK DIAGRAM OF RB5
Data Bus
D
WR
WPUB
CK
Q
Q
Weak
CCP2OUT
Enable
VDD
RBPU
RD
WPUB
CCP2OUT
D
WR
PORTB
VDD
Q
1
0
I/O Pin
CK Q
VSS
D
WR
TRISB
Q
CK Q
RD
TRISB
ANSB
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q
Q3
D
EN
Interrupt-onChange
RD PORTB
To Timer1 Gate
To A/D Converter
To Cap Sensor
DS40001341F-page 66
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PIC16(L)F722/3/4/6/7
FIGURE 6-11:
BLOCK DIAGRAM OF RB6
ICSP™ MODE
DEBUG
Data Bus
D
WR
WPUB
CK
Q
VDD
Q
Weak
VDD
RBPU
PORT_ICDCLK
RD
WPUB
1
D
WR
PORTB
Q
0
D
WR
TRISB
I/O Pin
CK Q
VSS
Q
0
CK Q
1
RD
TRISB
TRIS_ICDCLK
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q
Q3
D
EN
Interrupt-onChange
RD PORTB
ICSPCLK
2007-2015 Microchip Technology Inc.
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PIC16(L)F722/3/4/6/7
FIGURE 6-12:
BLOCK DIAGRAM OF RB7
ICSP™ MODE
DEBUG
Data Bus
D
WR
WPUB
CK
Q
VDD
Q
Weak
VDD
RBPU
PORT_ICDDAT
RD
WPUB
1
D
WR
PORTB
Q
0
D
WR
TRISB
I/O Pin
CK Q
VSS
Q
0
CK Q
1
RD
TRISB
TRIS_ICDDAT
RD
PORTB
D
WR
IOCB
Q
CK Q
Q
D
EN
RD
IOCB
Q
Q3
D
EN
Interrupt-onChange
RD PORTB
ICSPDAT_IN
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PIC16(L)F722/3/4/6/7
TABLE 6-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
---- --00
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
CPSCON0
CPSON
—
—
—
CPSOUT
T0XCS
0--- 0000
0--- 0000
CPSCON1
—
—
—
—
CPSCH1
CPSCH0
---- 0000
---- 0000
0000 000X
INTCON
CPSRNG1 CPSRNG0
CPSCH3
CPSCH2
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
0000 0000
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
PORTB
T1GCON
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
xxxx xxxx
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
uuuu uxuu
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
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DS40001341F-page 69
PIC16(L)F722/3/4/6/7
6.4
PORTC and TRISC Registers
PORTC is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISC
(Register 6-11). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-3 shows how to initialize PORTC.
Reading the PORTC register (Register 6-10) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
REGISTER 6-10:
The TRISC register (Register 6-11) controls the PORTC
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
EXAMPLE 6-3:
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTC
PORTC
PORTC
TRISC
B‘00001100’
TRISC
;
;Init PORTC
;
;Set RC as inputs
;and set RC
;as outputs
The location of the CCP2 function is controlled by the
CCP2SEL bit in the APFCON register (refer to
Register 6-1)
PORTC: PORTC REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
RC: PORTC General Purpose I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
REGISTER 6-11:
TRISC: PORTC TRI-STATE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
TRISC: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
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6.4.1
RC0/T1OSO/T1CKI
6.4.8
RC7/RX/DT
Figure 6-13 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 6-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a Timer1 oscillator output
• a Timer1 clock input
• a general purpose I/O
• an asynchronous serial input
• a synchronous serial data I/O
6.4.2
RC1/T1OSI/CCP2
Figure 6-14 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a Timer1 oscillator input
• a Capture 2 input, Compare 2 output, and PWM2
output
Note:
6.4.3
CCP2 pin location may be selected as
RB3 or RC1.
RC2/CCP1
Figure 6-15 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a Capture 1 input, Compare 1 output, and PWM1
output
6.4.4
RC3/SCK/SCL
Figure 6-16 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a SPI clock
• an I2C clock
6.4.5
RC4/SDI/SDA
Figure 6-17 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a SPI data input
• an I2C data I/O
6.4.6
RC5/SDO
Figure 6-18 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• a SPI data output
6.4.7
RC6/TX/CK
Figure 6-19 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an asynchronous serial output
• a synchronous clock I/O
2007-2015 Microchip Technology Inc.
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PIC16(L)F722/3/4/6/7
FIGURE 6-13:
BLOCK DIAGRAM OF RC0
Oscillator
Circuit
Data Bus
VDD
RC1/T1OSI
D
WR
PORTC
Q
I/O Pin
CK Q
D
WR
TRISC
VSS
Q
CK Q
RD
TRISC
T1OSCEN
RD
PORTC
To Timer1 CLK Input
FIGURE 6-14:
BLOCK DIAGRAM OF RC1
CCP2OUT
Enable
Oscillator
Circuit
Data Bus
CCP2OUT
D
WR
PORTC
Q
1
0
I/O Pin
CK Q
D
WR
TRISC
VDD
RC0/T1OSO
Q
VSS
CK Q
RD
TRISC
T1OSCEN
RD
PORTC
To CCP2(1) Input
Note 1:
CCP2 input is controlled by CCP2SEL in the APFCON register.
DS40001341F-page 72
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PIC16(L)F722/3/4/6/7
FIGURE 6-15:
BLOCK DIAGRAM OF RC2
CCP1OUT
Enable
VDD
Data Bus
CCP1OUT
D
WR
PORTC
Q
1
0
I/O Pin
CK Q
D
WR
TRISC
VSS
Q
CK Q
RD
TRISC
RD
PORTC
To CCP1 Input
FIGURE 6-16:
BLOCK DIAGRAM OF RC3
SSPM = SPI MODE
SCK_MASTER
1
Data Bus
VDD
SSPEN
0
1
D
WR
PORTC
Q
0
(2)
I/O Pin
CK Q
VSS
SCL
D
WR
TRISC
Q
CK Q
RD
TRISC
To SSP SPI
Clock Input
1
0
RD
PORTC
0
1
SSPEN
SSPM = I2C MODE
To SSP I2C
SCL Input
I2C(1)
Note 1:
2:
I2C Schmitt Trigger has special input levels.
I2C Slew Rate limiting controlled by SMP bit of SSPSTAT register.
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PIC16(L)F722/3/4/6/7
FIGURE 6-17:
BLOCK DIAGRAM OF RC4
SSPEN
SSPM = I2C MODE
VDD
Data Bus
1
D
WR
PORTC
Q
0
(2)
I/O Pin
CK Q
VSS
D
WR
TRISC
Q
CK Q
RD
TRISC
To SSP SPI
Data Input
1
0
RD
PORTC
0
1
SDA FROM SSP
To SSP I2C
SDA Input
I2C(1)
Note 1:
2:
I2C Schmitt Trigger has special input levels.
I2C Slew Rate limiting controlled by SMP bit of SSPSTAT register.
FIGURE 6-18:
BLOCK DIAGRAM OF RC5
SSPEN
SSPM = SPI MODE
VDD
Data Bus
SDO
D
WR
PORTC
Q
1
0
I/O Pin
CK Q
VSS
D
WR
TRISC
Q
SDO
EN
CK Q
RD
TRISC
RD
PORTC
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PIC16(L)F722/3/4/6/7
FIGURE 6-19:
BLOCK DIAGRAM OF RC6
SYNC
USART_TX
0
USART_CK
1
VDD
1
Data Bus
D
WR
PORTC
Q
0
I/O Pin
CK Q
D
WR
TRISC
VSS
Q
CK Q
RD
TRISC
RD
PORTC
SPEN
TXEN
0
CSRC
1
SYNC
To USART
Sync Clock Input
FIGURE 6-20:
BLOCK DIAGRAM OF RC7
SPEN
SYNC
VDD
Data Bus
USART_DT
D
WR
PORTC
Q
1
0
I/O Pin
CK Q
D
WR
TRISC
Q
VSS
CK Q
RD
TRISC
RD
PORTC
SPEN
SYNC
TXEN
SREN
CREN
To USART Data Input
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TABLE 6-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7
Bit 6
APFCON
—
—
—
—
—
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP2CON
Bit 5
Bit 4
Bit 3
Bit 2
Value on
POR, BOR
Value on all
other
Resets
Bit 1
Bit 0
—
SSSEL
CCP2SEL
---- --00
---- --00
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
xxxx xxxx
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1SYNC
—
TMR1ON
0000 00-0
uuuu uu-u
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
T1CKPS0 T1OSCEN
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Port C.
DS40001341F-page 76
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PIC16(L)F722/3/4/6/7
6.5
EXAMPLE 6-4:
PORTD and TRISD Registers
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTD is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISD
(Register 6-13). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 6-4 shows how to initialize PORTD.
Reading the PORTD register (Register 6-12) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch.
Note:
PORTD is available on PIC16F724/LF724
and PIC16F727/LF727 only.
The TRISD register (Register 6-13) controls the
PORTD pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISD register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
REGISTER 6-12:
6.5.1
INITIALIZING PORTD
PORTD
PORTD
ANSELD
ANSELD
TRISD
B‘00001100’
TRISD
;
;Init PORTD
;Make PORTD digital
;
;Set RD as inputs
;and set RD
;as outputs
ANSELD REGISTER
The ANSELD register (Register 6-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELD bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELD bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELD register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
PORTD: PORTD REGISTER(1)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
RD: PORTD General Purpose I/O Pin bits
1 = Port pin is > VIH
0 = Port pin is < VIL
PORTD is not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
2007-2015 Microchip Technology Inc.
DS40001341F-page 77
PIC16(L)F722/3/4/6/7
TRISD: PORTD TRI-STATE REGISTER(1)
REGISTER 6-13:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
TRISD: PORTD Tri-State Control bits
1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output
Note 1:
TRISD is not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
ANSELD: PORTD ANALOG SELECT REGISTER(2)
REGISTER 6-14:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ANSD: Analog Select between Analog or Digital Function on Pins RD, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSELD register is not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’.
6.5.4
Note:
6.5.2
x = Bit is unknown
RD2/CPS10
PORTD is available on PIC16F724/LF724
and PIC16F727/LF727 only.
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
RD0/CPS8
• a general purpose I/O
• a capacitive sensing input
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.5
RD3/CPS11
• a general purpose I/O
• a capacitive sensing input
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.3
• a general purpose I/O
• a capacitive sensing input
RD1/CPS9
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
• a general purpose I/O
• a capacitive sensing input
DS40001341F-page 78
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
6.5.6
RD4/CPS12
6.5.8
RD6/CPS14
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
• a general purpose I/O
• a capacitive sensing input
• a general purpose I/O
• a capacitive sensing input
6.5.7
6.5.9
RD5/CPS13
RD7/CPS15
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
• a general purpose I/O
• a capacitive sensing input
• a general purpose I/O
• a capacitive sensing input
FIGURE 6-21:
BLOCK DIAGRAM OF RD
VDD
Data Bus
D
WR
PORTD
Q
I/O Pin
CK Q
D
WR
TRISD
VSS
Q
CK Q
RD
TRISD
ANSD
RD
PORTD
To Cap Sensor
Note:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
TABLE 6-4:
Name
PORTD is available on PIC16F724/LF724 and PIC16F727/LF727 only.
Bit 7
Bit 6
ANSELD
ANSD7
ANSD6
CPSCON0
CPSON
—
CPSCON1
Bit 5
Bit 4
ANSD5 ANSD4
—
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111 1111 1111
—
CPSRNG1
CPSRNG0
CPSOUT
T0XCS
0--- 0000 0--- 0000
—
—
—
—
CPSCH3
CPSCH2
CPSCH1
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx xxxx xxxx
TRISD
TRISD7
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111 1111 1111
TRISD6 TRISD5 TRISD4
CPSCH0 ---- 0000 ---- 0000
Legend:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
Note 1: These registers are not implemented on the PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
2007-2015 Microchip Technology Inc.
DS40001341F-page 79
PIC16(L)F722/3/4/6/7
6.6
PORTE and TRISE Registers
PORTE is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 6-5 shows how to initialize PORTE.
Reading the PORTE register (Register 6-15) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. RE3 reads ‘0’ when
MCLRE = 1.
Note:
RE and TRISE are not
implemented on the PIC16F722/723/726/
PIC16LF722/723/726. Read as ‘0’.
The TRISE register (Register 6-16) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
Note:
The ANSELE register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
EXAMPLE 6-5:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTE
PORTE
PORTE
ANSELE
ANSELE
TRISE
B‘00001100’
TRISE
DS40001341F-page 80
;
;Init PORTE
;
;digital I/O
;
;Set RE as an input
;and set RE
;as outputs
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 6-15:
U-0
PORTE: PORTE REGISTER
U-0
—
U-0
—
—
U-0
—
R-x
R/W-x
R/W-x
R/W-x
RE3
RE2(1)
(1)
RE0(1)
RE1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RE: PORTE I/O Pin bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1:
x = Bit is unknown
RE are not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’.
REGISTER 6-16:
U-0
TRISE: PORTE TRI-STATE REGISTER
U-0
—
U-0
—
—
U-0
R-1
R/W-1
R/W-1
R/W-1
—
TRISE3
TRISE2(1)
TRISE1(1)
TRISE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3
TRISE3: RE3 Port Tri-state Control bit
This bit is always ‘1’ as RE3 is an input only
bit 2-0
TRISE: RE Tri-State Control bits(1)
1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
Note 1:
x = Bit is unknown
TRISE are not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’.
2007-2015 Microchip Technology Inc.
DS40001341F-page 81
PIC16(L)F722/3/4/6/7
REGISTER 6-17:
U-0
ANSELE: PORTE ANALOG SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
R/W-1
R/W-1
R/W-1
—
ANSE2(2)
ANSE1(2)
ANSE0(2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
ANSE: Analog Select between Analog or Digital Function on Pins RE, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSELE register is not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’
TABLE 6-5:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ANSELE
—
—
—
—
—
ANSE2
ANSE1
ANSE0
---- -111
---- -111
PORTE
—
—
—
—
RE3
RE2
RE1
RE0
---- xxxx
---- xxxx
TRISE
—
—
—
—
TRISE1(1)
TRISE0(1)
---- 1111
---- 1111
Legend:
Note 1:
2:
TRISE3(2) TRISE2(1)
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE
These registers are not implemented on the PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
This bit is always ‘1’ as RE3 is input only.
DS40001341F-page 82
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
6.6.1
RE0/AN5(1)
Figure 6-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
Note 1: RE0/AN5 is available on
PIC16F724/LF724 and
PIC16F727/LF727 only.
6.6.2
RE1/AN6(1)
Figure 6-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
Note 1: RE0/AN5 is available on
PIC16F724/LF724 and
PIC16F727/LF727 only.
6.6.3
RE2/AN7(1)
Figure 6-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
Note 1: RE0/AN5 is available on
PIC16F724/LF724 and
PIC16F727/LF727 only.
6.6.4
RE3/MCLR/VPP
Figure 6-23 shows the diagram for this pin. This pin is
configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset with weak pull-up
• a programming voltage reference input
2007-2015 Microchip Technology Inc.
DS40001341F-page 83
PIC16(L)F722/3/4/6/7
FIGURE 6-22:
BLOCK DIAGRAM OF RE
VDD
Data Bus
D
WR
PORTE
I/O Pin
CK Q
D
WR
TRISE
Q
VSS
Q
CK Q
RD
TRISE
ANSE
RD
PORTE
To A/D Converter
Note:
RE are not implemented on PIC16F722/723/726/PIC16LF722/723/726.
FIGURE 6-23:
BLOCK DIAGRAM OF RE3
VDD
ICSP™ Mode Detect
Weak
In-Circuit Serial Programming™ mode
High-Voltage
Detect
I/O Pin
MCLR Circuit
MCLR
Pulse Filter
VSS
Data Bus
RD
TRISE
VSS
RD
PORTE
Power for Programming Flash
DS40001341F-page 84
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
7.0
OSCILLATOR MODULE
7.1
Overview
Clock source modes are configured by the FOSC bits
in Configuration Word 1 (CONFIG1). The oscillator
module can be configured for one of eight modes of
operation.
The oscillator module has a wide variety of clock sources
and selection features that allow it to be used in a wide
range of applications while maximizing performance and
minimizing power consumption. Figure 7-1 illustrates a
block diagram of the oscillator module.
1.
2.
3.
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system can be configured to use an internal calibrated
high-frequency oscillator as clock source, with a choice
of selectable speeds via software.
4.
5.
6.
7.
8.
RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
INTOSC – Internal oscillator with FOSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
EC – External clock with I/O on OSC2/CLKOUT.
HS – High Gain Crystal or Ceramic Resonator
mode.
XT – Medium Gain Crystal or Ceramic
Resonator Oscillator mode.
LP – Low-Power Crystal mode.
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 7-1:
FOSC
(Configuration Word 1)
External Oscillator
OSC2
Sleep
LP, XT, HS, RC, EC
MUX
OSC1
Internal Oscillator
IRCF
(OSCCON Register)
500 kHz
INTOSC
16 MHz/500 kHz
1
Postscaler
8 MHz/250 kHz
4 MHz/125 kHz
2 MHz/62.5 kHz
11
10
MUX
MUX
0
32x
PLL
System Clock
(CPU and Peripherals)
01
00
PLLEN
(Configuration Word 1)
2007-2015 Microchip Technology Inc.
DS40001341F-page 85
PIC16(L)F722/3/4/6/7
7.2
Clock Source Modes
Clock source modes can be classified as external or
internal.
• Internal clock source (INTOSC) is contained
within the oscillator module and derived from a
500 kHz high precision oscillator. The oscillator
module has eight selectable output frequencies,
with a maximum internal frequency of 16 MHz.
• External clock modes rely on external circuitry for
the clock source. Examples are: oscillator
modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
The system clock can be selected between external or
internal clock sources via the FOSC bits of the
Configuration Word 1.
7.3
Internal Clock Modes
The oscillator module has eight output frequencies
derived from a 500 kHz high precision oscillator. The
IRCF bits of the OSCCON register select the
postscaler applied to the clock source dividing the
frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the
Configuration Word 1 locks the internal clock source to
16 MHz before the postscaler is selected by the IRCF
bits. The PLLEN bit must be set or cleared at the time
of programming; therefore, only the upper or low four
clock source frequencies are selectable in software.
7.3.1
INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is programmed using the oscillator selection
or the FOSC bits in the CONFIG1 register. See
Section 8.0 “Device Configuration” for more
information.
7.3.2
FREQUENCY SELECT BITS (IRCF)
The output of the 500 kHz INTOSC and 16 MHz
INTOSC, with Phase-Locked Loop enabled, connect to
a postscaler and multiplexer (see Figure 7-1). The
Internal Oscillator Frequency Select bits (IRCF) of the
OSCCON register select the frequency output of the
internal oscillator. Depending upon the PLLEN bit, one
of four frequencies of two frequency sets can be
selected via software:
If PLLEN = 1, frequency selection is as follows:
•
•
•
•
16 MHz
8 MHz (default after Reset)
4 MHz
2 MHz
If PLLEN = 0, frequency selection is as follows:
•
•
•
•
500 kHz
250 kHz (default after Reset)
125 kHz
62.5 kHz
Note:
Following any Reset, the IRCF bits
of the OSCCON register are set to ‘10’ and
the frequency selection is set to 8 MHz or
250 kHz. The user can modify the IRCF
bits to select a different frequency.
There is no start-up delay before a new frequency
selected in the IRCF bits takes effect. This is because
the old and new frequencies are derived from INTOSC
via the postscaler and multiplexer.
Start-up delay specifications are located in the
Table 23-2
in
Section 23.0
“Electrical
Specifications”.
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In
INTOSCIO
mode,
OSC1/CLKIN
and
OSC2/CLKOUT are available for general purpose I/O.
DS40001341F-page 86
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
7.4
Oscillator Control
The Oscillator Control (OSCCON) register (Figure 7-1)
displays the status and allows frequency selection of the
internal oscillator (INTOSC) system clock. The
OSCCON register contains the following bits:
• Frequency selection bits (IRCF)
• Status Locked bits (ICSL)
• Status Stable bits (ICSS)
REGISTER 7-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
U-0
R/W-1
R/W-0
R-q
R-q
U-0
U-0
—
—
IRCF1
IRCF0
ICSL
ICSS
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
q = Value depends on condition
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
IRCF: Internal Oscillator Frequency Select bits
When PLLEN = 1 (16 MHz INTOSC)
11 = 16 MHz
10 = 8 MHz (POR value)
01 = 4 MHz
00 = 2 MHz
When PLLEN = 0 (500 kHz INTOSC)
11 = 500 kHz
10 = 250 kHz (POR value)
01 = 125 kHz
00 = 62.5 kHz
bit 3
ICSL: Internal Clock Oscillator Status Locked bit (2% Stable)
1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) is in lock
0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet locked
bit 2
ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable)
1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy
0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy
bit 1-0
Unimplemented: Read as ‘0’
2007-2015 Microchip Technology Inc.
DS40001341F-page 87
PIC16(L)F722/3/4/6/7
7.5
Oscillator Tuning
The INTOSC is factory calibrated but can be adjusted
in software by writing to the OSCTUNE register
(Register 7-2).
REGISTER 7-2:
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: Frequency Tuning bits
01 1111 = Maximum frequency
01 1110 =
•
•
•
00 0001 =
00 0000 = Oscillator module is running at the factory-calibrated frequency.
11 1111 =
•
•
•
10 0000 = Minimum frequency
DS40001341F-page 88
2007-2015 Microchip Technology Inc.
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7.6
External Clock Modes
7.6.1
OSCILLATOR START-UP TIMER (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations on the OSC1 pin before the device is
released from Reset. This occurs following a Power-on
Reset (POR) and when the Power-up Timer (PWRT)
has expired (if configured), or a wake-up from Sleep.
During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.
7.6.2
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 7-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
Clock from
Ext. System
PIC® MCU
I/O
7.6.3
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 7-3 and Figure 7-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
FIGURE 7-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 7-2 shows the pin
connections for EC mode.
Note 1:
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
OSC2/CLKOUT(1)
Alternate pin functions are described in
Section 6.1 “Alternate Pin Function”.
LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 7-3). The mode selects a low,
medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is best suited
to drive resonators with a low drive level specification, for
example, tuning fork type crystals.
2007-2015 Microchip Technology Inc.
PIC® MCU
OSC1/CLKIN
C1
To Internal
Logic
Quartz
Crystal
C2
RS(1)
RF(2)
Sleep
OSC2/CLKOUT
Note 1:
A series resistor (RS) may be required for
quartz crystals with low drive level.
2:
The value of RF varies with the Oscillator mode
selected.
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices (DS00826)
• AN849, Basic PIC® Oscillator Design
(DS00849)
• AN943, Practical PIC® Oscillator
Analysis and Design (DS00943)
• AN949, Making Your Oscillator Work
(DS00949).
DS40001341F-page 89
PIC16(L)F722/3/4/6/7
FIGURE 7-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
FIGURE 7-5:
EXTERNAL RC MODES
VDD
PIC® MCU
REXT
PIC® MCU
OSC1/CLKIN
Internal
Clock
OSC1/CLKIN
CEXT
C1
To Internal
Logic
RP(3)
C2 Ceramic
RS(1)
Resonator
RF(2)
VSS
Sleep
FOSC/4 or
I/O(2)
OSC2/CLKOUT
Recommended values: 10 k REXT 100 k, 20 pF, 2-5V
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
Note 1:
2: The value of RF varies with the Oscillator mode
selected.
2:
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
7.6.4
Alternate pin functions are described in
Section 6.1 “Alternate Pin Function”.
Output depends upon RC or RCIO clock mode.
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
EXTERNAL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
In RC mode, the RC circuit connects to OSC1.
OSC2/CLKOUT outputs the RC oscillator frequency
divided by 4. This signal may be used to provide a clock
for external circuitry, synchronization, calibration, test
or other application requirements. Figure 7-5 shows
the external RC mode connections.
TABLE 7-1:
OSC2/CLKOUT(1)
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
POR, BOR
Value on
all other
Resets(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG1(1)
—
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
—
—
OSCCON
—
—
IRCF1
IRCF0
ICSL
ICSS
—
—
--10 qq--
--10 qq--
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
--uu uuuu
OSCTUNE
Legend:
Note 1:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources.
See Configuration Word 1 (Register 8-1) for operation of all bits.
DS40001341F-page 90
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
8.0
DEVICE CONFIGURATION
8.1
Device Configuration consists of Configuration Word 1
and Configuration Word 2 registers, Code Protection
and Device ID.
REGISTER 8-1:
—
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1
register at 2007h and Configuration Word 2 register at
2008h. These registers are only accessible during
programming.
CONFIG1: CONFIGURATION WORD REGISTER 1
—
R/P-1
R/P-1
U-1(4)
R/P-1
R/P-1
R/P-1
DEBUG
PLLEN
—
BORV
BOREN1
BOREN0
bit 15
bit 8
U-1(4)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
—
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 13
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger
bit 12
PLLEN: INTOSC PLL Enable bit
0 = INTOSC Frequency is 500 kHz
1 = INTOSC Frequency is 16 MHz (32x)
bit 11
Unimplemented: Read as ‘1’
bit 10
BORV: Brown-out Reset Voltage selection bit
0 = Brown-out Reset Voltage (VBOR) set to 2.5 V nominal
1 = Brown-out Reset Voltage (VBOR) set to 1.9 V nominal
bit 9-8
BOREN: Brown-out Reset Selection bits(1)
0x = BOR disabled (Preconditioned State)
10 = BOR enabled during operation and disabled in Sleep
11 = BOR enabled
bit 7
Unimplemented: Read as ‘1’
bit 6
CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5
MCLRE: RE3/MCLR pin function select bit(3)
1 = RE3/MCLR pin function is MCLR
0 = RE3/MCLR pin function is digital input, MCLR internally tied to VDD
Note 1:
2:
3:
4:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire program memory will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
MPLAB® X IDE masks unimplemented Configuration bits to ‘0’.
2007-2015 Microchip Technology Inc.
DS40001341F-page 91
PIC16(L)F722/3/4/6/7
REGISTER 8-1:
CONFIG1: CONFIGURATION WORD REGISTER 1 (CONTINUED)
bit 4
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0
FOSC: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on
RA7/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on
RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1:
2:
3:
4:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire program memory will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
MPLAB® X IDE masks unimplemented Configuration bits to ‘0’.
REGISTER 8-2:
CONFIG2: CONFIGURATION WORD REGISTER 2
—
—
U-1(1)
U-1(1)
U-1(1)
U-1(1)
U-1(1)
U-1(1)
—
—
—
—
—
—
bit 15
bit 8
U-1(1)
U-1(1)
R/P-1
R/P-1
U-1(1)
U-1(1)
U-1(1)
U-1(1)
—
—
VCAPEN1
VCAPEN0
—
—
—
—
bit 7
bit 0
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 13-6
Unimplemented: Read as ‘1’
bit 5-4
VCAPEN: Voltage Regulator Capacitor Enable bits
For the PIC16LF72X:
These bits are ignored. All VCAP pin functions are disabled.
For the PIC16F72X:
00 = VCAP functionality is enabled on RA0
01 = VCAP functionality is enabled on RA5
10 = VCAP functionality is enabled on RA6
11 = All VCAP functions are disabled (not recommended)
bit 3-0
Unimplemented: Read as ‘1’
Note 1:
x = Bit is unknown
MPLAB® X IDE masks unimplemented Configuration bits to ‘0’.
DS40001341F-page 92
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
8.2
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note:
8.3
The entire Flash program memory will be
erased when the code protection is turned
off. See the “PIC16(L)F72X Memory
Programming Specification” (DS41332)
for more information.
User ID
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are readable and writable during Program/Verify mode. Only
the Least Significant seven bits of the ID locations are
reported when using MPLAB IDE. See the
“PIC16(L)F72X Memory Programming Specification”
(DS41332) for more information.
2007-2015 Microchip Technology Inc.
DS40001341F-page 93
PIC16(L)F722/3/4/6/7
9.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 8-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 8-bit binary result via successive
approximation and stores the conversion result into the
ADC result register (ADRES). Figure 9-1 shows the
block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 9-1:
ADC BLOCK DIAGRAM
AVDD
ADREF = 0x
ADREF = 11
VREF+
AN0
0000
AN1
0001
AN2
0010
AN3
0011
AN4
0100
AN5
0101
AN6
0110
AN7
0111
AN8
1000
AN9
1001
AN10
1010
AN11
1011
AN12
1100
AN13
1101
Reserved
1110
FVREF
1111
ADREF = 10
ADC
8
GO/DONE
ADRES
ADON
VSS
CHS
DS40001341F-page 94
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
9.1
ADC Configuration
When configuring and using the ADC, the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
9.1.1
For correct conversion, the appropriate TAD
specification must be met. Refer to the A/D conversion
requirements
in
Section 23.0
“Electrical
Specifications” for more information. Table 9-1 gives
examples of appropriate ADC clock selections.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to Section 6.0
“I/O Ports” for more information.
Note:
9.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.
9.1.3
ADC VOLTAGE REFERENCE
The ADREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be either VDD, an external
voltage source or the internal Fixed Voltage Reference.
The negative voltage reference is always connected to
the ground reference. See Section 10.0 “Fixed
Voltage Reference” for more details on the Fixed
Voltage Reference.
9.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 8-bit conversion requires 10 TAD periods
as shown in Figure 9-2.
2007-2015 Microchip Technology Inc.
DS40001341F-page 95
PIC16(L)F722/3/4/6/7
TABLE 9-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
100
200 ns
(2)
250 ns
(2)
(2)
1.0 s
4.0 s
400 ns
(2)
0.5 s
1.0 s
2.0 s
8.0 s(3)
Fosc/4
(2)
500 ns
Fosc/8
001
Fosc/16
101
800 ns
1.0 s
2.0 s
4.0 s
16.0 s(3)
Fosc/32
010
1.6 s
2.0 s
4.0 s
8.0 s(3)
32.0 s(3)
Fosc/64
110
3.2 s
4.0 s
16.0 s
64.0 s(3)
FRC
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
Legend:
Note 1:
2:
3:
4:
8.0 s
(3)
(3)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
Shaded cells are outside of recommended range.
The FRC source has a typical TAD time of 1.6 s for VDD.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 9-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
Tcy to TAD
TAD0
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
DS40001341F-page 96
ADRES register is loaded,
GO/DONE bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
9.1.5
INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
9.2.3
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRES register will be updated with the partially
complete Analog-to-Digital conversion sample.
Incomplete bits will match the last bit converted.
Note:
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the
Interrupt Service Routine.
Please refer to Section 9.1.5 “Interrupts” for more
information.
9.2
9.2.1
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
9.2.2
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 9.2.6 “A/D Conversion
Procedure”.
TERMINATING A CONVERSION
9.2.4
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
9.2.5
SPECIAL EVENT TRIGGER
The Special Event Trigger of the CCP module allows
periodic ADC measurements without software
intervention. When this trigger occurs, the GO/DONE
bit is set by hardware and the Timer1 counter resets to
zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
Refer to Section 15.0 “Capture/Compare/PWM
(CCP) Module” for more information.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRES register with new conversion
result
2007-2015 Microchip Technology Inc.
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9.2.6
A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 9-1:
A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL
ADCON1
;
MOVLW
B’01110000’ ;ADC Frc clock,
;VDD reference
MOVWF
ADCON1
;
BANKSEL
TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL
ANSELA
;
BSF
ANSELA,0
;Set RA0 to analog
BANKSEL
ADCON0
;
MOVLW
B’00000001’;AN0, On
MOVWF
ADCON0
;
CALL
SampleTime ;Acquisiton delay
BSF
ADCON0,GO ;Start conversion
BTFSC
ADCON0,GO ;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL
ADRES
;
MOVF
ADRES,W
;Read result
MOVWF
RESULT
;store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 9.3 “A/D Acquisition
Requirements”.
DS40001341F-page 98
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
9.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
REGISTER 9-1:
ADCON0: A/D CONTROL REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHS: Analog Channel Select bits
0000 = AN0
0001 = AN1
0010 = AN2
0011 = AN3
0100 = AN4
0101 = AN5
0110 = AN6
0111 = AN7
1000 = AN8
1001 = AN9
1010 = AN10
1011 = AN11
1100 = AN12
1101 = AN13
1110 = Reserved
1111 = Fixed Voltage Reference (FVREF)
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
2007-2015 Microchip Technology Inc.
DS40001341F-page 99
PIC16(L)F722/3/4/6/7
REGISTER 9-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
—
ADCS2
ADCS1
ADCS0
—
—
ADREF1
ADREF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCS: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from a dedicated RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock supplied from a dedicated RC oscillator)
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
ADREF: Voltage Reference Configuration bits
0x = VREF is connected to VDD
10 = VREF is connected to external VREF (RA3/AN3)
11 = VREF is connected to internal Fixed Voltage Reference
REGISTER 9-3:
x = Bit is unknown
ADRES: ADC RESULT REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ADRES: ADC Result Register bits
8-bit conversion result.
DS40001341F-page 100
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
9.3
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 9-3. The source impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 9-3. The maximum recommended impedance for analog sources is 10 k. As the source
EQUATION 9-1:
Assumptions:
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(or changed), an A/D acquisition must be done before
the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This
equation assumes that 1/2 LSb error is used (256 steps
for the ADC). The 1/2 LSb error is the maximum error
allowed for the ADC to meet its specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C + Temperature - 25°C 0.05µs/°C
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 – -------------------------n+1
2
–1
;[1] VCHOLD charged to within 1/2 lsb
–TC
----------
RC
V AP P LI ED 1 – e = V CHOLD
;[2] VCHOLD charge response to VAPPLIED
– Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 – e = V A PP LIE D 1 – -------------------------n+1
2
–1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD R IC + R SS + R S ln(1/511)
= – 10pF 1k + 7k + 10k ln(0.001957)
= 1.12 µs
Therefore:
T ACQ = 2ΜS + 1.12 ΜS + 50°C- 25°C 0.05ΜS /°C
= 4.42 ΜS
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
2007-2015 Microchip Technology Inc.
DS40001341F-page 101
PIC16(L)F722/3/4/6/7
FIGURE 9-3:
ANALOG INPUT MODEL
VDD
Rs
VA
VT 0.6V
ANx
CPIN
5 pF
VT 0.6V
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
CHOLD = 10 pF
VSS/VREF-
Legend: CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
6V
5V
VDD 4V
3V
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
= Interconnect Resistance
RIC
RSS
= Resistance of Sampling Switch
SS
= Sampling Switch
VT
= Threshold Voltage
RSS
5 6 7 8 9 10 11
Sampling Switch
(k)
Note 1: Refer to Section 23.0 “Electrical Specifications”.
FIGURE 9-4:
ADC TRANSFER FUNCTION
Full-Scale Range
FFh
FEh
FDh
ADC Output Code
FCh
1 LSB ideal
FBh
Full-Scale
Transition
04h
03h
02h
01h
00h
Analog Input Voltage
1 LSB ideal
VSS
DS40001341F-page 102
Zero-Scale
Transition
VREF
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 9-2:
Name
SUMMARY OF ASSOCIATED ADC REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ADCON1
—
ADCS2
ADCS1
ADCS0
—
—
ADREF1
ADREF0
-000 --00
-000 --00
ANSELA
—
—
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
--11 1111
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
ANSELE
—
—
—
—
—
ANSE2
ANSE1
ANSE0
---- -111
---- -111
ADRES
CCP2CON
A/D Result Register Byte
—
—
FVRCON
FVRRDY
FVREN
—
—
INTCON
GIE
PEIE
T0IE
INTE
PIE1
TMR1GIE
ADIE
RCIE
TXIE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
TRISA
TRISA7
TRISA6
TRISA5
TRISB
TRISB7
TRISB6
TRISB5
—
—
—
—
TRISE
Legend:
DC2B1
DC2B0
CCP2M3
xxxx xxxx
uuuu uuuu
--00 0000
--00 0000
CCP2M2
CCP2M1
CCP2M0
—
—
ADFVR1
ADFVR0
q0-- --00
q0-- --00
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISE3
TRISE2
TRISE1
TRISE0
---- 1111
---- 1111
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC
module.
2007-2015 Microchip Technology Inc.
DS40001341F-page 103
PIC16(L)F722/3/4/6/7
10.0
FIXED VOLTAGE REFERENCE
This device contains an internal voltage regulator. To
provide a reference for the regulator, a band gap
reference is provided. This band gap is also user
accessible via an A/D converter channel.
User level band gap functions are controlled by the
FVRCON register, which is shown in Register 10-1.
REGISTER 10-1:
FVRCON: FIXED VOLTAGE REFERENCE REGISTER
R-q
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
FVRRDY
FVREN
—
—
—
—
ADFVR1
ADFVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
q = Value depends on condition
bit 7
FVRRDY(1): Fixed Voltage Reference Ready Flag bit
0 = Fixed Voltage Reference output is not active or stable
1 = Fixed Voltage Reference output is ready for use
bit 6
FVREN(2): Fixed Voltage Reference Enable bit
0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 5-2
Unimplemented: Read as ‘0’
bit 1-0
ADFVR: A/D Converter Fixed Voltage Reference Selection bits
00 = A/D Converter Fixed Voltage Reference Peripheral output is off.
01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)
10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
Note 1:
2:
FVRRDY is always ‘1’ for the PIC16F72X devices.
Fixed Voltage Reference output cannot exceed VDD.
DS40001341F-page 104
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
11.0
TIMER0 MODULE
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
The Timer0 module is an 8-bit timer/counter with the
following features:
•
•
•
•
•
•
Note:
8-bit timer/counter register (TMR0)
8-bit prescaler (shared with Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
TMR0 can be used to gate Timer1
11.1.2
Timer0 Operation
8-Bit Counter mode using the T0CKI pin is selected by
setting the T0CS bit in the OPTION register to ‘1’ and
resetting the T0XCS bit in the CPSCON0 register to ‘0’.
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
11.1.1
8-Bit Counter mode using the Capacitive Sensing
Oscillator (CPSOSC) signal is selected by setting the
T0CS bit in the OPTION register to ‘1’ and setting the
T0XCS bit in the CPSCON0 register to ‘1’.
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the T0CS bit of the OPTION
register.
FIGURE 11-1:
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin or the
Capacitive Sensing Oscillator (CPSOSC) signal.
Figure 11-1 is a block diagram of the Timer0 module.
11.1
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
The rising or falling transition of the incrementing edge
for either input source is determined by the T0SE bit in
the OPTION register.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FOSC/4
Data Bus
T0XCS
0
8
T0CKI
1
0
Sync
2 TCY
1
0
Cap. Sensing
Oscillator
1
Set Flag bit T0IF
on Overflow
0
T0SE
T0CS
8-bit
Prescaler
PSA
Overflow to Timer1
1
T1GSS = 11
TMR0
TMR1GE
PSA
8
WDTE
Low-Power
WDT OSC
PS
Divide by
512
1
WDT
Time-out
0
PSA
2007-2015 Microchip Technology Inc.
DS40001341F-page 105
PIC16(L)F722/3/4/6/7
11.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are
selectable via the PS bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
Note:
11.1.4
When the prescaler is assigned to WDT, a
CLRWDT instruction will clear the prescaler
along with the WDT.
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit can only
be cleared in software. The Timer0 interrupt enable is
the T0IE bit of the INTCON register.
Note:
11.1.5
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 23.0 “Electrical
Specifications”.
DS40001341F-page 106
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 11-1:
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin or CPSOSC signal
0 = Internal instruction cycle clock (FOSC/4)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS: Prescaler Rate Select bits
BIT VALUE
TMR0 RATE
WDT RATE
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
000
001
010
011
100
101
110
111
TABLE 11-1:
Name
CPSCON0
OPTION_REG
TMR0
TRISA
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
INTCON
x = Bit is unknown
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CPSRNG1 CPSRNG0
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0--- 0000
CPSON
—
—
—
CPSOUT
T0XCS
0--- 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
xxxx xxxx
uuuu uuuu
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
Timer0 Module Register
TRISA7
TRISA6
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
2007-2015 Microchip Technology Inc.
DS40001341F-page 107
PIC16(L)F722/3/4/6/7
12.0
TIMER1 MODULE WITH GATE
CONTROL
•
•
•
•
•
The Timer1 module is a 16-bit timer/counter with the
following features:
•
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
3-bit prescaler
Dedicated LP oscillator circuit
Synchronous or asynchronous operation
Multiple Timer1 gate (count enable) sources
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
FIGURE 12-1:
Selectable Gate Source Polarity
Gate Toggle mode
Gate Single-pulse mode
Gate Value Status
Gate Event Interrupt
Figure 12-1 is a block diagram of the Timer1 module.
TIMER1 BLOCK DIAGRAM
T1GSS
T1G
00
From Timer0
Overflow
01
From Timer2
Match PR2
10
From WDT
Overflow
11
T1GSPM
0
T1G_IN
T1GVAL
0
Single Pulse
TMR1ON
T1GPOL
D
Q
CK
R
Q
1
Q1
Acq. Control
1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
det
Set
TMR1GIF
T1GTM
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
TMR1(2)
TMR1H
EN
TMR1L
T1CLK
Q
Synchronized
clock input
0
D
1
TMR1CS
T1OSO/T1CKI
OUT
T1OSC
T1OSI
Cap. Sensing
Oscillator
T1SYNC
11
Synchronize(3)
Prescaler
1, 2, 4, 8
1
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS
FOSC/2
Internal
Clock
Sleep input
T1CKI
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
DS40001341F-page 108
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
12.1
Timer1 Operation
12.2
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 12-2 displays the clock source selections.
12.2.1
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and
increments on every selected edge of the external
source.
12.2.2
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI or the
capacitive sensing oscillator signal. Either of these
external clock sources can be synchronized to the
microcontroller system clock or they can run
asynchronously.
Timer1
Operation
TMR1GE
0
0
Off
0
1
Off
1
0
Always On
1
1
Count Enabled
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
TIMER1 ENABLE
SELECTIONS
TMR1ON
INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 12-1 displays the Timer1 enable
selections.
TABLE 12-1:
Clock Source Selection
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR reset
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON= 1) when T1CKI
is low.
TABLE 12-2:
CLOCK SOURCE SELECTIONS
TMR1CS1
TMR1CS0
T1OSCEN
0
1
x
System Clock (FOSC)
0
0
x
Instruction Clock (FOSC/4)
1
1
x
Capacitive Sensing Oscillator
1
0
0
External Clocking on T1CKI Pin
1
0
1
Oscillator Circuit on T1OSI/T1OSO Pins
2007-2015 Microchip Technology Inc.
Clock Source
DS40001341F-page 109
PIC16(L)F722/3/4/6/7
12.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
12.4
Timer1 Oscillator
A dedicated low-power 32.768 kHz oscillator circuit is
built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
12.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
The oscillator circuit is enabled by setting the
T1OSCEN bit of the T1CON register. The oscillator will
continue to run during Sleep.
Note:
12.5
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 12.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
DS40001341F-page 110
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
12.6
12.6.2.1
Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 Gate
circuitry. This is also referred to as Timer1 Gate Count
Enable.
Timer1 Gate can also be driven by multiple selectable
sources.
12.6.1
TIMER1 GATE COUNT ENABLE
The Timer1 Gate is enabled by setting the TMR1GE bit
of the T1GCON register. The polarity of the Timer1
Gate is configured using the T1GPOL bit of the
T1GCON register.
When Timer1 Gate (T1G) input is active, Timer1 will
increment on the rising edge of the Timer1 clock
source. When Timer1 Gate input is inactive, no
incrementing will occur and Timer1 will hold the current
count. See Figure 12-3 for timing details.
TABLE 12-3:
TIMER1 GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G
0
0
Counts
0
1
Holds Count
1
0
Holds Count
1
1
Counts
12.6.2
Timer1 Operation
TIMER1 GATE SOURCE
SELECTION
The Timer1 Gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 12-4:
T1GSS
TIMER1 GATE SOURCES
Timer1 Gate Source
00
Timer1 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
Timer2 match PR2
(TMR2 increments to match PR2)
11
Count Enabled by WDT Overflow
(Watchdog Time-out interval expired)
2007-2015 Microchip Technology Inc.
T1G Pin Gate Operation
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
Gate circuitry.
12.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 Gate circuitry.
12.6.2.3
Timer2 Match Gate Operation
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be
generated and internally supplied to the Timer1 Gate
circuitry.
12.6.2.4
Watchdog Overflow Gate Operation
The Watchdog Timer oscillator, prescaler and counter
will be automatically turned on when TMR1GE = 1 and
T1GSS selects the WDT as a gate source for Timer1
(T1GSS = 11). TMR1ON does not factor into the
oscillator, prescaler and counter enable. See
Table 12-5.
The PSA and PS bits of the OPTION register still
control what time-out interval is selected. Changing the
prescaler during operation may result in a spurious
capture.
Enabling the Watchdog Timer oscillator does not
automatically enable a Watchdog Reset or Wake-up
from Sleep upon counter overflow.
Note:
When using the WDT as a gate source for
Timer1, operations that clear the Watchdog
Timer (CLRWDT, SLEEP instructions) will
affect the time interval being measured for
capacitive sensing. This includes waking
from Sleep. All other interrupts that might
wake the device from Sleep should be
disabled to prevent them from disturbing
the measurement period.
As the gate signal coming from the WDT counter will
generate different pulse widths depending on if the
WDT is enabled, when the CLRWDT instruction is
executed, and so on, Toggle mode must be used. A
specific sequence is required to put the device into the
correct state to capture the next WDT counter interval.
DS40001341F-page 111
PIC16(L)F722/3/4/6/7
TABLE 12-5:
WDT/TIMER1 GATE INTERACTION
WDTE
TMR1GE = 1
and
T1GSS = 11
WDT Oscillator
Enable
WDT Reset
Wake-up
WDT Available for
T1G Source
1
N
Y
Y
Y
N
1
Y
Y
Y
Y
Y
0
Y
Y
N
N
Y
0
N
N
N
N
N
12.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 12-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
12.6.4
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/DONE bit. See Figure 12-5 for
timing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See Figure 12-6 for
timing details.
12.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
12.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
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12.7
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
•
•
•
•
TMR1ON bit of the T1CON register
TMR1IE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
12.8
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
•
•
•
•
•
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
T1SYNC bit of the T1CON register must be set
TMR1CS bits of the T1CON register must be
configured
• T1OSCEN bit of the T1CON register must be
configured
• TMR1GIE bit of the T1GCON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
12.9
CCP Capture/Compare Time Base
The CCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For
more
information,
see
Section 15.0
“Capture/Compare/PWM (CCP) Module”.
12.10 CCP Special Event Trigger
When the CCP is configured to trigger a special event,
the trigger will clear the TMR1H:TMR1L register pair.
This special event does not cause a Timer1 interrupt.
The CCP module may still be configured to generate a
CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized to the FOSC/4 to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
For more information, see Section 9.2.5 “Special
Event Trigger”.
FIGURE 12-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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FIGURE 12-3:
TIMER1 GATE COUNT ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1
N
FIGURE 12-4:
N+1
N+2
N+3
N+4
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1
N
DS40001341F-page 114
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 12-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
N
Cleared by software
2007-2015 Microchip Technology Inc.
N+1
N+2
Set by hardware on
falling edge of T1GVAL
Cleared by
software
DS40001341F-page 115
PIC16(L)F722/3/4/6/7
FIGURE 12-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
DS40001341F-page 116
N
Cleared by software
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
N+4
Cleared by
software
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
12.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 12-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 12-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
—
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
TMR1CS: Timer1 Clock Source Select bits
11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)
10 = Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: LP Oscillator Enable Control bit
1 = Dedicated Timer1 oscillator circuit enabled
0 = Dedicated Timer1 oscillator circuit disabled
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1X
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
x = Bit is unknown
TMR1CS = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 1X.
bit 1
Unimplemented: Read as ‘0’
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 Gate flip-flop
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12.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 12-2, is used to control Timer1 Gate.
REGISTER 12-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R/W-0
R/W-0
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled.
0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared
Timer1 gate flip flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single Pulse Mode bit
1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS: Timer1 Gate Source Select bits
00 = Timer1 Gate pin
01 = Timer0 Overflow output
10 = TMR2 Match PR2 output
11 = Watchdog Timer scaler overflow
Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON
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TABLE 12-6:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
CCP2CON
INTCON
PORTB
xxxx xxxx
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
—
TMR1ON
0000 00-0
uuuu uu-u
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
uuuu uxuu
T1CON
TMR1CS1 TMR1CS0
T1GCON
TMR1GE
Legend:
x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
T1GPOL
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13.0
TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
•
•
•
•
•
8-bit timer register (TMR2)
8-bit period register (PR2)
Interrupt on TMR2 match with PR2
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
See Figure 13-1 for a block diagram of Timer2.
13.1
The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescaler is then used to
increment the TMR2 register.
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
Note:
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
TMR2 is not cleared when T2CON is
written.
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented.
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
TMR2
Output
FOSC/4
Prescaler
1:1, 1:4, 1:16
2
TMR2
Sets Flag
bit TMR2IF
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
T2CKPS
PR2
4
TOUTPS
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REGISTER 13-1:
T2CON: TIMER2 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
TABLE 13-1:
x = Bit is unknown
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Value on
POR, BOR
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
0000 0000
0000 0000
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PR2
Timer2 Module Period Register
TMR2
Holding Register for the 8-bit TMR2 Register
T2CON
Legend:
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
0000 0000
-000 0000
-000 0000
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
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14.0
CAPACITIVE SENSING
MODULE
sensing module. The capacitive sensing module
requires software and at least one timer resource to
determine the change in frequency. Key features of this
module include:
The capacitive sensing module allows for an interaction
with an end user without a mechanical interface. In a
typical application, the capacitive sensing module is
attached to a pad on a printed circuit board (PCB), which
is electrically isolated from the end user. When the end
user places their finger over the PCB pad, a capacitive
load is added, causing a frequency shift in the capacitive
FIGURE 14-1:
•
•
•
•
•
Analog MUX for monitoring multiple inputs
Capacitive sensing oscillator
Multiple timer resources
Software control
Operation during Sleep
CAPACITIVE SENSING BLOCK DIAGRAM
Timer0 Module
Set
T0IF
T0CS
T0XCS
FOSC/4
T0CKI
0
TMR0
0
Overflow
1
1
CPSCH(2)
CPSON(3)
CPS0
CPS1
CPS2
CPS3
Timer1 Module
CPS4
CPSON
T1CS
CPS5
CPS6
CPS8(1)
CPS9
FOSC
Capacitive
Sensing
Oscillator
CPS7
(1)
CPSOSC
CPS10(1)
CPS11(1)
FOSC/4
CPSCLK
CPSOUT
EN
T1OSC/
T1CKI
TMR1H:TMR1L
T1GSEL
CPSRNG
CPS12(1)
T1G
CPS13(1)
Timer1 Gate
Control Logic
CPS14(1)
CPS15(1)
Watchdog Timer Module
Timer2 Module
WDT
Event
TMR2
Overflow
WDT Overflow
Scaler
LP WDT
OSC
Postscaler
Set
TMR2IF
PS
Note 1: Channels CPS are implemented on PIC16F724/727/PIC16LF724/727 only.
2: CPSCH3 is not implemented on PIC16F722/723/726/PIC16LF722/723/726.
3: If CPSON = 0, disabling capacitive sensing, no channel is selected.
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14.1
Analog MUX
14.4.1
TIMER0
The capacitive sensing module can monitor up to 16
inputs. The capacitive sensing inputs are defined as
CPS. To determine if a frequency change has
occurred the user must:
To select Timer0 as the timer resource for the capacitive
sensing module:
• Select the appropriate CPS pin by setting the
CPSCH bits of the CPSCON1 register
• Set the corresponding ANSEL bit
• Set the corresponding TRIS bit
• Run the software algorithm
When Timer0 is chosen as the timer resource, the
capacitive sensing oscillator will be the clock source for
Timer0. Refer to Section 11.0 “Timer0 Module” for
additional information.
Selection of the CPSx pin while the module is enabled
will cause the capacitive sensing oscillator to be on the
CPSx pin. Failure to set the corresponding ANSEL and
TRIS bits can cause the capacitive sensing oscillator to
stop, leading to false frequency readings.
14.2
Capacitive Sensing Oscillator
The capacitive sensing oscillator consists of a constant
current source and a constant current sink, to produce
a triangle waveform. The CPSOUT bit of the
CPSCON0 register shows the status of the capacitive
sensing oscillator, whether it is a sinking or sourcing
current. The oscillator is designed to drive a capacitive
load (single PCB pad) and at the same time, be a clock
source to either Timer0 or Timer1. The oscillator has
three different current settings as defined by
CPSRNG of the CPSCON0 register. The different
current settings for the oscillator serve two purposes:
• Maximize the number of counts in a timer for a
fixed time base
• Maximize the count differential in the timer during
a change in frequency
14.3
Timer resources
To measure the change in frequency of the capacitive
sensing oscillator, a fixed time base is required. For the
period of the fixed time base, the capacitive sensing
oscillator is used to clock either Timer0 or Timer1. The
frequency of the capacitive sensing oscillator is equal
to the number of counts in the timer divided by the
period of the fixed time base.
14.4
• Set the T0XCS bit of the CPSCON0 register
• Clear the T0CS bit of the OPTION register
14.4.2
TIMER1
To select Timer1 as the timer resource for the
capacitive sensing module, set the TMR1CS of
the T1CON register to ‘11’. When Timer1 is chosen as
the timer resource, the capacitive sensing oscillator will
be the clock source for Timer1. Because the Timer1
module has a gate control, developing a time base for
the frequency measurement can be simplified using
either:
• The Timer0 overflow flag
• The Timer2 overflow flag
• The WDT overflow flag
It is recommend that one of these flags, in conjunction
with the toggle mode of the Timer1 Gate, is used to
develop the fixed time base required by the software
portion of the capacitive sensing module. Refer to
Section 12.0 “Timer1 Module with Gate Control” for
additional information.
TABLE 14-1:
TIMER1 ENABLE FUNCTION
TMR1ON
TMR1GE
Timer1 Operation
0
0
Off
0
1
Off
1
0
On
1
1
Count Enabled by input
Fixed Time Base
To measure the frequency of the capacitive sensing
oscillator, a fixed time base is required. Any timer
resource or software loop can be used to establish the
fixed time base. It is up to the end user to determine the
method in which the fixed time base is generated.
Note:
The fixed time base can not be generated
by timer resource the capacitive sensing
oscillator is clocking.
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14.5
Software Control
The software portion of the capacitive sensing module
is required to determine the change in frequency of the
capacitive sensing oscillator. This is accomplished by
the following:
• Setting a fixed time base to acquire counts on
Timer0 or Timer1
• Establishing the nominal frequency for the
capacitive sensing oscillator
• Establishing the reduced frequency for the
capacitive sensing oscillator due to an additional
capacitive load
• Set the frequency threshold
14.5.1
NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
To determine the nominal frequency of the capacitive
sensing oscillator:
14.5.3
FREQUENCY THRESHOLD
The frequency threshold should be placed midway
between the value of nominal frequency and the
reduced frequency of the capacitive sensing oscillator.
Refer to Application Note AN1103, Software Handling
for Capacitive Sensing (DS01103) for more detailed
information the software required for capacitive
sensing module.
Note:
For more information on general
Capacitive Sensing refer to Application
Notes:
• AN1101, Introduction to Capacitive
Sensing (DS01101)
• AN1102, Layout and Physical Design
Guidelines for Capacitive Sensing
(DS01102).
• Remove any extra capacitive load on the selected
CPSx pin
• At the start of the fixed time base, clear the timer
resource
• At the end of the fixed time base save the value in
the timer resource
The value of the timer resource is the number of
oscillations of the capacitive sensing oscillator for the
given time base. The frequency of the capacitive
sensing oscillator is equal to the number of counts on
in the timer divided by the period of the fixed time base.
14.5.2
REDUCED FREQUENCY
(ADDITIONAL CAPACITIVE LOAD)
The extra capacitive load will cause the frequency of the
capacitive sensing oscillator to decrease. To determine
the reduced frequency of the capacitive sensing
oscillator:
• Add a typical capacitive load on the selected
CPSx pin
• Use the same fixed-time base as the nominal
frequency measurement
• At the start of the fixed-time base, clear the timer
resource
• At the end of the fixed-time base save the value in
the timer resource
The value of the timer resource is the number of
oscillations of the capacitive sensing oscillator with an
additional capacitive load. The frequency of the
capacitive sensing oscillator is equal to the number of
counts on in the timer divided by the period of the fixed
time base. This frequency should be less than the
value obtained during the nominal frequency
measurement.
40001341F-page 124
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
14.6
Operation during Sleep
The capacitive sensing oscillator will continue to run as
long as the module is enabled, independent of the part
being in Sleep. In order for the software to determine if
a frequency change has occurred, the part must be
awake. However, the part does not have to be awake
when the timer resource is acquiring counts. One way
to acquire the Timer1 counts while in Sleep is to have
Timer1 gated with the overflow of the Watchdog Timer.
This can be accomplished using the following steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Configure the Watchdog Time-out overflow as
the Timer1’s gate source T1GSS = 11.
Set Timer1 Gate to toggle mode by setting the
T1GTM bit of the T1GCON register.
Set the TMR1GE bit of the T1GCON register.
Set TMR1ON bit of the T1CON register.
Enable capacitive sensing module with the
appropriate current settings and pin selection.
Clear Timer1.
Put the part to Sleep.
On the first WDT overflow, the capacitive sensing oscillator will begin to increment Timer1.
Then put the part to Sleep.
On the second WDT overflow Timer1 will stop
incrementing. Then run the software routine to
determine if a frequency change has occurred.
Refer to Section 12.0 “Timer1 Module with Gate
Control” for additional information.
Note 1: When using the WDT to set the interval
on Timer1, any other source that wakes
the part up early will cause the WDT
overflow to be delayed, affecting the
value captured by Timer1.
2: Timer0 does not operate when in Sleep,
and therefore cannot be used for
capacitive sense measurements in
Sleep.
2007-2015 Microchip Technology Inc.
40001341F-page 125
PIC16(L)F722/3/4/6/7
REGISTER 14-1:
CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R-0
R/W-0
CPSON
—
—
—
CPSRNG1
CPSRNG0
CPSOUT
T0XCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CPSON: Capacitive Sensing Module Enable bit
1 = Capacitive sensing module is operating
0 = Capacitive sensing module is shut off and consumes no operating current
bit 6-4
Unimplemented: Read as ‘0’
bit 3-2
CPSRNG: Capacitive Sensing Oscillator Range bits
00 = Oscillator is Off.
01 = Oscillator is in low range. Charge/discharge current is nominally 0.1 µA.
10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2 µA.
11 = Oscillator is in high range. Charge/discharge current is nominally 18 µA.
bit 1
CPSOUT: Capacitive Sensing Oscillator Status bit
1 = Oscillator is sourcing current (Current flowing out the pin)
0 = Oscillator is sinking current (Current flowing into the pin)
bit 0
T0XCS: Timer0 External Clock Source Select bit
If T0CS = 1
The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:
1 = Timer0 Clock Source is the capacitive sensing oscillator
0 = Timer0 Clock Source is the T0CKI pin
If T0CS = 0
Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4.
40001341F-page 126
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 14-2:
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0
U-0
U-0
U-0
R/W-0(2)
R/W-0
R/W-0
R/W-0
—
—
—
—
CPSCH3
CPSCH2
CPSCH1
CPSCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
CPSCH: Capacitive Sensing Channel Select bits
If CPSON = 0:
These bits are ignored. No channel is selected.
If CPSON = 1:
0000 = channel 0, (CPS0)
0001 = channel 1, (CPS1)
0010 = channel 2, (CPS2)
0011 = channel 3, (CPS3)
0100 = channel 4, (CPS4)
0101 = channel 5, (CPS5)
0110 = channel 6, (CPS6)
0111 = channel 7, (CPS7)
1000 = channel 8, (CPS8(1))
1001 = channel 9, (CPS9(1))
1010 = channel 10, (CPS10(1))
1011 = channel 11, (CPS11(1))
1100 = channel 12, (CPS12(1))
1101 = channel 13, (CPS13(1))
1110 = channel 14, (CPS14(1))
1111 = channel 15, (CPS15(1))
Note 1:
2:
These channels are not implemented on the PIC16F722/723/726/PIC16LF722/723/726.
This bit is not implemented on PIC16F722/723/726/PIC16LF722/723/726, Read as ‘0’
TABLE 14-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Bit 7
Bit 6
Bit 5
ANSELA
—
—
ANSA5
ANSELB
—
—
ANSB5
ANSELD
ANSD7
ANSD6
ANSD5
OPTION_REG
RBPU
INTEDG
T0CS
TMR1GIE
ADIE
RCIE
PIE1
x = Bit is unknown
Bit 4
Value on
POR, BOR
Value on
all other
Resets
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
--11 1111
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111
1111 1111
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
—
TMR1ON
0000 00-0
0000 00-0
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
1111 1111
Legend:
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module.
2007-2015 Microchip Technology Inc.
40001341F-page 127
PIC16(L)F722/3/4/6/7
15.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events. In Capture mode, the peripheral allows the
timing of the duration of an event. The Compare mode
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate a pulse-width modulated signal of
varying frequency and duty cycle.
TABLE 15-1:
CCP MODE – TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
The timer resources used by the module are shown in
Table 15-1.
Additional information on CCP modules is available in
the Application Note AN594, Using the CCP Modules
(DS00594).
TABLE 15-2:
CCP1 Mode
INTERACTION OF TWO CCP MODULES
CCP2 Mode
Interaction
Capture
Capture
Same TMR1 time base
Capture
Compare
Same TMR1 time base(1, 2)
Compare
Compare
Same TMR1 time base(1, 2)
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges will be aligned.
PWM
Capture
None
PWM
Compare
None
Note 1:
2:
Note:
If CCP2 is configured as a Special Event Trigger, CCP1 will clear Timer1, affecting the value captured on
the CCP2 pin.
If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1,
affecting the value captured on the CCP1 pin.
CCPRx and CCPx throughout this
document refer to CCPR1 or CCPR2 and
CCP1 or CCP2, respectively
DS40001341F-page 128
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 15-1:
CCPxCON: CCPx CONTROL REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM: CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCPxIF bit of the PIRx register is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit of the PIRx register is set)
1001 = Compare mode, clear output on match (CCPxIF bit of the PIRx register is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set of the PIRx register,
CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit of the PIRx register is set, TMR1 is reset
and A/D conversion(1) is started if the ADC module is enabled. CCPx pin is unaffected.)
11xx = PWM mode.
Note 1: A/D conversion start feature is available only on CCP2.
2007-2015 Microchip Technology Inc.
DS40001341F-page 129
PIC16(L)F722/3/4/6/7
15.1
15.1.3
Capture Mode
In Capture mode, CCPRxH:CCPRxL captures the
16-bit value of the TMR1 register when an event occurs
on pin CCPx. An event is defined as one of the
following and is configured by the CCPxM bits of
the CCPxCON register:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
15.1.1
CCPx PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 15-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCPxIF
(PIRx register)
CCPx
CCPRxH
and
Edge Detect
CCPRxL
Capture
Enable
TMR1H
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode or when
Timer1 is clocked at FOSC, the capture operation may
not work.
DS40001341F-page 130
15.1.4
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
Mode. In order for Capture Mode to recognize the trigger event on the CCPx pin,
Timer1 must be clocked from the Instruction Clock (FOSC/4) or from an external
clock source.
CCP PRESCALER
There are four prescaler settings specified by the
CCPxM bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler (refer to Example 15-1).
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON
CLRF
MOVLW
MOVWF
15.1.5
TMR1L
CCPxCON
System Clock (FOSC)
15.1.2
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in operating mode.
Note:
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value (refer to Figure 15-1).
SOFTWARE INTERRUPT
;Set Bank bits to point
;to CCP1CON
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; move value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock
source.
If Timer1 is clocked by FOSC/4, then Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
If Timer1 is clocked by an external clock source, then
Capture mode will operate as defined in Section 15.1
“Capture Mode”.
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 15-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
---- --00
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
CCPRxL
Capture/Compare/PWM Register X Low Byte
xxxx xxxx
uuuu uuuu
CCPRxH
Capture/Compare/PWM Register X High Byte
xxxx xxxx
uuuu uuuu
INTCON
PIE1
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIR2
—
—
—
—
—
—
—
CCP2IF
---- ---0
---- ---0
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
—
TMR1ON
0000 00-0
uuuu uu-u
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
0000 0x00
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TRISB
TRISC
Legend:
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture.
2007-2015 Microchip Technology Inc.
DS40001341F-page 131
PIC16(L)F722/3/4/6/7
15.2
Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCPx module may:
•
•
•
•
•
Toggle the CCPx output
Set the CCPx output
Clear the CCPx output
Generate a Special Event Trigger
Generate a Software Interrupt
15.2.3
The action on the pin is based on the value of the
CCPxM control bits of the CCPxCON register.
All Compare modes can generate an interrupt.
FIGURE 15-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPxCON
Mode Select
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPRxH CCPRxL
CCPx
Q
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
Special Event Trigger
Special Event Trigger will:
• Clear TMR1H and TMR1L registers.
• NOT set interrupt flag bit TMR1IF of the PIR1 register.
• Set the GO/DONE bit to start the ADC conversion
(CCP2 only).
15.2.1
Note:
CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
15.2.2
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
TIMER1 MODE SELECTION
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
DS40001341F-page 132
SOFTWARE INTERRUPT MODE
When Software Interrupt mode is chosen
(CCPxM = 1010), the CCPxIF bit in the PIRx
register is set and the CCPx module does not assert
control of the CCPx pin (refer to the CCPxCON
register).
15.2.4
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCPxM = 1011), the CCPx module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
(CCP2 only)
The CCPx module does not assert control of the CCPx
pin in this mode (refer to the CCPxCON register).
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. This
allows the CCPRxH, CCPRxL register pair to
effectively provide a 16-bit programmable period
register for Timer1.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. For the Compare operation of the
TMR1 register to the CCPRx register to
occur, Timer1 must be clocked from the
Instruction Clock (FOSC/4) or from an
external clock source.
15.2.5
COMPARE DURING SLEEP
The Compare Mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 15-4:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Bit 7
Bit 6
Bit 5
Bit 4
ADCON0
—
—
CHS3
CHS2
ANSELB
—
—
ANSB5
ANSB4
APFCON
—
—
—
—
CCP1CON
—
—
DC1B1
CCP2CON
—
—
DC2B1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GO/DONE
ADON
--00 0000
--00 0000
ANSB1
ANSB0
--11 1111
--11 1111
—
SSSEL
CCP2SEL
---- --00
---- --00
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
Bit 3
Bit 2
Bit 1
CHS1
CHS0
ANSB3
ANSB2
—
DC1B0
DC2B0
CCPRxL
Capture/Compare/PWM Register X Low Byte
xxxx xxxx
uuuu uuuu
CCPRxH
Capture/Compare/PWM Register X High Byte
xxxx xxxx
uuuu uuuu
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
—
—
—
—
—
—
—
CCP2IF
---- ---0
---- ---0
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
—
TMR1ON
0000 00-0
uuuu uu-u
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
0000 0x00
uuuu uuuu
PIR2
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Compare.
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15.3
PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers:
•
•
•
•
The PWM output (Figure 15-4) has a time base
(period) and a time that the output stays high (duty
cycle).
FIGURE 15-4:
PR2
T2CON
CCPRxL
CCPxCON
CCP PWM OUTPUT
Period
Pulse Width
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCPx pin.
TMR2 = PR2
TMR2 = CCPRxL:CCPxCON
TMR2 = 0
Figure 15-3 shows a simplified block diagram of PWM
operation.
15.3.1
Figure 15-4 shows a typical waveform of the PWM
signal.
In PWM mode, the CCPx pin is multiplexed with the
PORT data latch. The user must configure the CCPx
pin as an output by clearing the associated TRIS bit.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, refer to Section 15.3.8
“Setup for PWM Operation”.
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCPxCON
CCPx PIN CONFIGURATION
Either RC1 or RB3 can be selected as the CCP2 pin.
Refer to Section 6.1 “Alternate Pin Function” for
more information.
Note:
Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
Duty Cycle Registers
CCPRxL
CCPRxH(2) (Slave)
CCPx
R
Comparator
TMR2
(1)
Q
S
TRIS
Comparator
PR2
Note 1:
2:
Clear Timer2,
toggle CCPx pin and
latch duty cycle
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPRxH is a read-only register.
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15.3.2
PWM PERIOD
EQUATION 15-2:
PULSE WIDTH
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 15-1.
Pulse Width = CCPRxL:CCPxCON
EQUATION 15-1:
Note: TOSC = 1/FOSC
PWM PERIOD
PWM Period = PR2 + 1 4 T OSC
(TMR2 Prescale Value)
Note:
TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
Note:
15.3.3
The
Timer2
postscaler
(refer
to
Section 13.1 “Timer2 Operation”) is not
used in the determination of the PWM
frequency.
T OSC (TMR2 Prescale Value)
EQUATION 15-3:
DUTY CYCLE RATIO
CCPRxL:CCPxCON
Duty Cycle Ratio = ----------------------------------------------------------------------4 PR2 + 1
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
of the prescaler, to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (refer to
Figure 15-3).
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to multiple registers: CCPRxL register and DCxB
bits of the CCPxCON register. The CCPRxL contains
the eight MSbs and the DCxB bits of the
CCPxCON register contain the two LSbs. CCPRxL and
DCxB bits of the CCPxCON register can be written
to at any time. The duty cycle value is not latched into
CCPRxH until after the period completes (i.e., a match
between PR2 and TMR2 registers occurs). While using
the PWM, the CCPRxH register is read-only.
Equation 15-2 is used to calculate the PWM pulse
width.
Equation 15-3 is used to calculate the PWM duty cycle
ratio.
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15.3.4
PWM RESOLUTION
EQUATION 15-4:
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 15-4.
TABLE 15-5:
1.22 kHz
Timer Prescale (1, 4, 16)
PR2 Value
4.88 kHz
PR2 Value
1
1
1
1
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
OPERATION IN SLEEP MODE
4.
5.
•
•
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency.
Refer to Section 7.0 “Oscillator Module” for
additional details.
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
2.
3.
208.3 kHz
4
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
1.
156.3 kHz
0xFF
Maximum Resolution (bits)
15.3.8
78.12 kHz
16
Timer Prescale (1, 4, 16)
15.3.7
19.53 kHz
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
15.3.6
If the pulse-width value is greater than the
period, the assigned PWM pin(s) will
remain unchanged.
0xFF
Maximum Resolution (bits)
15.3.5
Note:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
TABLE 15-6:
PWM RESOLUTION
•
6.
•
•
Load the CCPRxL register and the DCxBx bits of
the CCPxCON register, with the PWM duty cycle
value.
Configure and start Timer2:
Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
Configure the T2CKPS bits of the T2CON
register with the Timer2 prescale value.
Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
Enable PWM output pin:
Wait until Timer2 overflows, TMR2IF bit of the
PIR1 register is set. See Note below.
Enable the PWM pin (CCPx) output driver(s) by
clearing the associated TRIS bit(s).
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
Disable the PWM pin (CCPx) output driver(s) by
setting the associated TRIS bit(s).
Load the PR2 register with the PWM period value.
Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
DS40001341F-page 136
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TABLE 15-7:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSELB
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
---- --00
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
CCPRxL
Capture/Compare/PWM Register X Low Byte
xxxx xxxx
uuuu uuuu
CCPRxH
Capture/Compare/PWM Register X High Byte
xxxx xxxx
uuuu uuuu
PR2
Timer2 Period Register
1111 1111
1111 1111
-000 0000
T2CON
TMR2
TRISB
TRISC
Legend:
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
Timer2 Module Register
0000 0000
0000 0000
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
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16.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The AUSART module includes the following capabilities:
•
•
•
•
•
•
•
•
•
•
The
Addressable
Universal
Synchronous
Asynchronous Receiver Transmitter (AUSART)
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communications Interface (SCI), can be configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 16-1:
Full-duplex asynchronous transmit and receive
Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Sleep operation
Block diagrams of the AUSART transmitter and
receiver are shown in Figure 16-1 and Figure 16-2.
AUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
TX/CK
MSb
LSb
(8)
0
Pin Buffer
and Control
TRMT
SPEN
• • •
Transmit Shift Register (TSR)
TXEN
Baud Rate Generator
FOSC
÷n
TX9
n
+1
SPBRG
DS40001341F-page 138
Multiplier
x4
SYNC
1
x16 x64
0
0
BRGH
x
1
0
TX9D
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 16-2:
AUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
RX/DT
Baud Rate Generator
+1
SPBRG
RSR Register
MSb
Pin Buffer
and Control
Data
Recovery
FOSC
Multiplier
x4
x16 x64
SYNC
1
0
0
BRGH
x
1
0
Stop
OERR
(8)
•••
7
1
LSb
0 START
RX9
÷n
n
FERR
RX9D
RCREG Register
FIFO
8
Data Bus
RCIF
RCIE
Interrupt
The operation of the AUSART module is controlled
through two registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
These registers are detailed in Register 16-1 and
Register 16-2, respectively.
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16.1
AUSART Asynchronous Mode
The AUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH Mark state which
represents a ‘1’ data bit, and a VOL Space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the Mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit Baud Rate
Generator is used to derive standard baud rate
frequencies from the system oscillator. Refer to
Table 16-5 for examples of baud rate Configurations.
The AUSART transmits and receives the LSb first. The
AUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
16.1.1
AUSART ASYNCHRONOUS
TRANSMITTER
The AUSART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
16.1.1.1
Enabling the Transmitter
The AUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other AUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the AUSART. Clearing the SYNC
bit of the TXSTA register configures the AUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the AUSART and automatically
configures the TX/CK I/O pin as an output.
DS40001341F-page 140
Note 1: When the SPEN bit is set the RX/DT I/O
pin is automatically configured as an input,
regardless of the state of the
corresponding TRIS bit and whether or not
the AUSART receiver is enabled. The RX/
DT pin data can be read via a normal
PORT read but PORT latch data output is
precluded.
2: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
16.1.1.2
Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
16.1.1.3
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the AUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
2007-2015 Microchip Technology Inc.
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16.1.1.4
TSR Status
16.1.1.6
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
Note:
16.1.1.5
The TSR register is not mapped in data
memory, so it is not available to the user.
1.
2.
3.
4.
Transmitting 9-Bit Characters
The AUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
AUSART will shift nine bits out for each character
transmitted. The TX9D bit of the TXSTA register is the
ninth, and Most Significant, data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXREG.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXREG is written.
5.
6.
7.
Asynchronous Transmission Set-up:
Initialize the SPBRG register and the BRGH bit to
achieve the desired baud rate (Refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9
control bit. A set ninth data bit will indicate that
the eight Least Significant data bits are an
address when the receiver is set for address
detection.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXREG register. This
will start the transmission.
A special 9-bit Address mode is available for use with
multiple receivers. Refer to Section 16.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 16-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
BRG Output
(Shift Clock)
TX/CK pin
TXIF bit
(Transmit Buffer
Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
Word 1
Transmit Shift Reg
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FIGURE 16-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK pin
Word 2
Start bit
TXIF bit
(Transmit Buffer
Empty Flag)
bit 0
bit 1
Word 1
1 TCY
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
INTCON
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
TABLE 16-1:
Name
Word 1
Transmit Shift Reg.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
0000 -010
0000 -010
TXREG
TXSTA
Legend:
AUSART Transmit Data Register
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
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PIC16(L)F722/3/4/6/7
16.1.2
AUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 16-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character First-In
First-Out (FIFO) memory. The FIFO buffering allows
reception of two complete characters and the start of a
third character before software must start servicing the
AUSART receiver. The FIFO and RSR registers are not
directly accessible by software. Access to the received
data is via the RCREG register.
16.1.2.1
Enabling the Receiver
The AUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other AUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the AUSART. Clearing the SYNC bit
of the TXSTA register configures the AUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the AUSART and automatically
configures the RX/DT I/O pin as an input.
Note:
When the SPEN bit is set the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or
not the AUSART transmitter is enabled.
The PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
16.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. Refer to Section 16.1.2.4 “Receive
Framing Error” for more information on framing
errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the AUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
Note:
16.1.2.3
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition
is
cleared.
Refer
to
Section 16.1.2.5 “Receive Overrun
Error” for more information on overrun
errors.
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the AUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE interrupt enable bit of the PIE1 register
• PEIE peripheral interrupt enable bit of the
INTCON register
• GIE global interrupt enable bit of the INTCON
register
The RCIF interrupt flag bit of the PIR1 register will be
set when there is an unread character in the FIFO,
regardless of the state of interrupt enable bits.
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16.1.2.4
Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the AUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
16.1.2.5
16.1.2.7
Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit of the PIR1 register. All other characters will be
ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
setting the AUSART by clearing the SPEN bit of the
RCSTA register.
16.1.2.6
Receiving 9-bit Characters
The AUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the AUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
DS40001341F-page 144
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
16.1.2.8
1.
2.
3.
4.
5.
6.
7.
8.
9.
Asynchronous Reception Set-up:
16.1.2.9
Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Enable reception by setting the CREN bit.
The RCIF interrupt flag bit of the PIR1 register
will be set when a character is transferred from
the RSR to the receive buffer. An interrupt will be
generated if the RCIE bit of the PIE1 register
was also set.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register.
If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
FIGURE 16-5:
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
2. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
4. Enable 9-bit reception by setting the RX9 bit.
5. Enable address detection by setting the ADDEN
bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit of the PIR1 register
will be set when a character with the ninth bit set
is transferred from the RSR to the receive buffer.
An interrupt will be generated if the RCIE interrupt enable bit of the PIE1 register was also set.
8. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
9-bit Address Detection Mode Set-up
bit 1
Rcv Shift
Reg
Rcv Buffer Reg
bit 7/8 Stop
bit
Start
bit
Word 1
RCREG
bit 0
bit 7/8 Stop
bit
Start
bit
bit 7/8 Stop
bit
Word 2
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
2007-2015 Microchip Technology Inc.
DS40001341F-page 145
PIC16(L)F722/3/4/6/7
TABLE 16-2:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RCREG
AUSART Receive Data Register
INTCON
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
TXSTA
Legend:
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.
DS40001341F-page 146
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 16-1:
R/W-0
CSRC
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
TX9
TXEN(1)
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: AUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as ‘0’
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1:
x = Bit is unknown
SREN/CREN overrides TXEN in Synchronous mode.
2007-2015 Microchip Technology Inc.
DS40001341F-page 147
PIC16(L)F722/3/4/6/7
REGISTER 16-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SPEN: Serial Port Enable bit(1)
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
Synchronous mode:
Must be set to ‘0’
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure
TRISx = 1.
DS40001341F-page 148
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
16.2
EXAMPLE 16-1:
AUSART Baud Rate Generator
(BRG)
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of
9600, and Asynchronous mode with SYNC = 0 and BRGH
= 0 (as seen in Table 16-3):
The Baud Rate Generator (BRG) is an 8-bit timer that
is dedicated to the support of both the asynchronous
and synchronous AUSART operation.
F OS C
Desired Baud Rate = --------------------------------------64 SPBRG + 1
The SPBRG register determines the period of the free
running baud rate timer. In Asynchronous mode the
multiplier of the baud rate period is determined by the
BRGH bit of the TXSTA register. In Synchronous mode,
the BRGH bit is ignored.
Solving for SPBRG:
F OS C
SPBRG = --------------------------------------------------------- – 1
64 Desired Baud Rate
Table 16-3 contains the formulas for determining the
baud rate. Example 16-1 provides a sample calculation
for determining the baud rate and baud rate error.
16000000
= ------------------------ – 1
64 9600
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 16-3. It may be
advantageous to use the high baud rate (BRGH = 1), to
reduce the baud rate error.
= 25.042 = 25
16000000
Actual Baud Rate = --------------------------64 25 + 1
= 9615
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures that
the BRG does not wait for a timer overflow before
outputting the new baud rate.
Actual Baud Rate – Desired Baud Rate
% Error = -------------------------------------------------------------------------------------------------- 100
Desired Baud Rate
9615 – 9600
= ------------------------------ 100 = 0.16%
9600
TABLE 16-3:
BAUD RATE FORMULAS
Configuration Bits
AUSART Mode
Baud Rate Formula
0
Asynchronous
FOSC/[64 (n+1)]
1
Asynchronous
FOSC/[16 (n+1)]
x
Synchronous
FOSC/[4 (n+1)]
SYNC
BRGH
0
0
1
Legend:
x = Don’t care, n = value of SPBRG register
TABLE 16-4:
Name
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0000 000x
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
Legend:
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
2007-2015 Microchip Technology Inc.
DS40001341F-page 149
PIC16(L)F722/3/4/6/7
TABLE 16-5:
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0
BAUD
RATE
FOSC = 20.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 18.432 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 16.0000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
—
—
—
—
—
—
—
—
—
—
—
—
1200
1221
1.73
255
1200
0.00
239
1201
0.08
207
1200
0.00
143
2400
2404
0.16
129
2400
0.00
119
2403
0.16
103
2400
0.00
71
9600
9470
-1.36
32
9600
0.00
29
9615
0.16
25
9600
0.00
17
10417
10417
0.00
29
10286
-1.26
27
10416
-0.01
23
10165
-2.42
16
19.2k
19.53k
1.73
15
19.20k
0.00
14
19.23k
0.16
12
19.20k
0.00
8
57.6k
—
—
—
57.60k
0.00
7
—
—
—
57.60k
0.00
2
115.2k
—
—
—
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 0
BAUD
RATE
FOSC = 8.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 4.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 3.6864 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
—
—
—
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
—
—
—
9600
9615
0.16
12
—
—
—
9600
0.00
5
—
—
—
10417
10417
0.00
11
10417
0.00
5
—
—
—
—
—
—
19.2k
—
—
—
—
—
—
19.20k
0.00
2
—
—
—
57.6k
—
—
—
—
—
—
57.60k
0.00
0
—
—
—
115.2k
—
—
—
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 1
BAUD
RATE
FOSC = 20.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 18.432 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 16.0000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
—
—
—
—
—
—
—
—
—
—
—
—
1200
—
—
—
—
—
—
—
—
—
—
—
—
2400
—
—
—
—
—
—
—
—
—
—
—
—
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.82k
-1.36
21
57.60k
0.00
19
58.8k
2.12
16
57.60k
0.00
11
115.2k
113.64k
-1.36
10
115.2k
0.00
9
—
—
—
115.2k
0.00
5
DS40001341F-page 150
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 16-5:
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 1
BAUD
RATE
FOSC = 8.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 4.000 MHz
Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 3.6864 MHz
Actual
Rate
FOSC = 1.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
—
—
—
—
—
—
—
1202
—
0.16
—
207
—
1200
—
0.00
—
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
—
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
—
—
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
5
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
—
—
—
57.6k
55556
-3.55
8
—
—
—
57.60k
0.00
3
—
—
—
115.2k
—
—
—
—
—
—
115.2k
0.00
1
—
—
—
2007-2015 Microchip Technology Inc.
DS40001341F-page 151
PIC16(L)F722/3/4/6/7
16.3
AUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The AUSART can operate as either a master or slave
device.
16.3.1.2
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are
automatically enabled when the AUSART is configured
for synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character, the new character data is held in
the TXREG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
Start and Stop bits are not used in synchronous
transmissions.
16.3.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the AUSART
for Synchronous Master operation:
•
•
•
•
•
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
16.3.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device
configured as a master transmits the clock on the TX/
CK line. The TX/CK pin output driver is automatically
enabled when the AUSART is configured for
synchronous transmit or receive operation. Serial data
bits change on the leading edge to ensure they are
valid at the trailing edge of each clock. One clock cycle
is generated for each data bit. Only as many clock
cycles are generated as there are data bits.
DS40001341F-page 152
Synchronous Master Transmission
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
16.3.1.3
Synchronous Master Transmission
Setup:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize the SPBRG register and the BRGH bit
to achieve the desired baud rate (refer to
Section 16.2 “AUSART Baud Rate Generator
(BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
Disable Receive mode by clearing bits SREN
and CREN.
Enable Transmit mode by setting the TXEN bit.
If 9-bit transmission is desired, set the TX9 bit.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
Start transmission by loading data to the TXREG
register.
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 16-6:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
‘1’
‘1’
Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 16-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 16-6:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TRISC
TXREG
TXSTA
Legend:
AUSART Transmit Data Register
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 0000
0000 0000
0000 -010
0000 -010
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.
2007-2015 Microchip Technology Inc.
DS40001341F-page 153
PIC16(L)F722/3/4/6/7
16.3.1.4
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
AUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit of the PIR1 register
is set and the character is automatically transferred to
the two character receive FIFO. The Least Significant
eight bits of the top character in the receive FIFO are
available in RCREG. The RCIF bit remains set as long
as there are unread characters in the receive FIFO.
16.3.1.5
Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The TX/
CK pin output driver is automatically disabled when the
device is configured for synchronous slave transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One data bit is transferred for each clock cycle.
Only as many clock cycles should be received as there
are data bits.
16.3.1.6
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register.
DS40001341F-page 154
16.3.1.7
Receiving 9-bit Characters
The AUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set, the AUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
Address detection in Synchronous modes is not
supported, therefore, the ADDEN bit of the RCSTA
register must be cleared.
16.3.1.8
Synchronous Master Reception
Setup:
1.
Initialize the SPBRG register for the appropriate
baud rate. Set or clear the BRGH bit, as
required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set bit RX9.
6. Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit RCIF of the PIR1 register will be
set when reception of a character is complete.
An interrupt will be generated if the RCIE
interrupt enable bit of the PIE1 register was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit, which
resets the AUSART.
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 16-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
Write to
bit SREN
SREN bit
CREN bit ‘0’
‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 16-7:
Name
INTCON
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
RCREG
AUSART Receive Data Register
PIE1
0000 0000
0000 0000
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
0000 000X
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
TXSTA
Legend:
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
2007-2015 Microchip Technology Inc.
DS40001341F-page 155
PIC16(L)F722/3/4/6/7
16.3.2
SYNCHRONOUS SLAVE MODE
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the AUSART
for Synchronous slave operation:
•
•
•
•
•
1.
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
2.
3.
4.
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
16.3.2.1
5.
16.3.2.2
1.
AUSART Synchronous Slave
Transmit
2.
3.
The operation of the Synchronous Master and Slave
modes are identical (refer to Section 16.3.1.2
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
4.
5.
6.
7.
8.
TABLE 16-8:
Name
INTCON
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Synchronous Slave Transmission
Setup:
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start transmission by writing the Least
Significant eight bits to the TXREG register.
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
0000 000X
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
0000 -010
0000 -010
RCSTA
TRISC
TXREG
TXSTA
Legend:
AUSART Transmit Data Register
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
DS40001341F-page 156
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
16.3.2.3
AUSART Synchronous Slave
Reception
16.3.2.4
The operation of the Synchronous Master and Slave
modes is identical (Section 16.3.1.4 “Synchronous
Master Reception”), with the following exceptions:
1.
2.
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
3.
4.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE interrupt enable bit
of the PIE1 register is set, the interrupt generated will
wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
5.
6.
7.
8.
9.
TABLE 16-9:
Name
INTCON
Synchronous Slave Reception
Setup:
Set the SYNC and SPEN bits and clear the
CSRC bit.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
Set the CREN bit to enable reception.
The RCIF bit of the PIR1 register will be set
when reception is complete. An interrupt will be
generated if the RCIE bit of the PIE1 register
was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register.
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
Resets
Value on
POR, BOR
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
RCREG
AUSART Receive Data Register
PIE1
0000 0000
0000 0000
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
0000 000X
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
Legend:
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
2007-2015 Microchip Technology Inc.
DS40001341F-page 157
PIC16(L)F722/3/4/6/7
16.4
AUSART Operation During Sleep
The AUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
16.4.1
SYNCHRONOUS RECEIVE DURING
SLEEP
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception
(refer to Section 16.3.2.4 “Synchronous Slave
Reception Setup:”).
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
• The RCIF interrupt flag must be cleared by
reading RCREG to unload any pending
characters in the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
16.4.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Transmission
(refer to Section 16.3.2.2 “Synchronous Slave
Transmission Setup:”).
• The TXIF interrupt flag must be cleared by writing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON
register.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE global
interrupt enable bit is also set then the Interrupt Service
Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the GIE global
interrupt enable bit of the INTCON register is also set,
then the Interrupt Service Routine at address 0004h
will be called.
DS40001341F-page 158
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
17.0
SSP MODULE OVERVIEW
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other
peripherals or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift
registers, display drivers, A/D converters, etc. The SSP
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
17.1
A typical SPI connection between microcontroller
devices is shown in Figure 17-1. Addressing of more
than one slave device is accomplished via multiple
hardware slave select lines. External hardware and
additional I/O pins must be used to support multiple
slave select addressing. This prevents extra overhead
in software for communication.
For SPI communication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
SPI Mode
The SPI mode allows eight bits of data to be
synchronously
transmitted
and
received,
simultaneously. The SSP module can be operated in
one of two SPI modes:
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
• Master mode
• Slave mode
SPI is a full-duplex protocol, with all communication
being bidirectional and initiated by a master device. All
clocking is provided by the master device and all bits
are transmitted, MSb first. Care must be taken to
ensure that all devices on the SPI bus are setup to
allow all controllers to send and receive data at the
same time.
FIGURE 17-1:
TYPICAL SPI MASTER/SLAVE CONNECTION
SPI Slave SSPM = 010x
SPI Master SSPM = 00xx
SDO
SDI
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
General I/O
2007-2015 Microchip Technology Inc.
Shift Register
(SSPSR)
MSb
SCK
Processor 1
SDO
Serial Clock
Slave Select
(optional)
LSb
SCK
SS
Processor 2
DS40001341F-page 159
PIC16(L)F722/3/4/6/7
FIGURE 17-2:
SPI MODE BLOCK
DIAGRAM
Internal
Data Bus
Read
Write
SSPBUF Reg
SSPSR Reg
SDI
bit 0
Shift
Clock
bit 7
SDO
SS
Control
Enable
RA5/SS
RA0/SS
SSSEL
2
Clock Select
Edge
Select
2
Edge
Select
Prescaler
4, 16, 64
SCK
TRISx
TMR2
Output
FOSC
4
SSPM
DS40001341F-page 160
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
17.1.1
MASTER MODE
In Master mode, data transfer can be initiated at any
time because the master controls the SCK line. Master
mode determines when the slave (Figure 17-1,
Processor 2) transmits data via control of the SCK line.
17.1.1.1
Master Mode Operation
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
register shifts the data in and out of the device, MSb
first. The SSPBUF register holds the data that is written
out of the master until the received data is ready. Once
the eight bits of data have been received, the byte is
moved to the SSPBUF register. The Buffer Full Status
bit, BF of the SSPSTAT register, and the SSP Interrupt
Flag bit, SSPIF of the PIR1 register, are then set.
Any write to the SSPBUF register during
transmission/reception of data will be ignored and the
Write Collision Detect bit, WCOL of the SSPCON
register, will be set. User software must clear the WCOL
bit so that it can be determined if the following write(s)
to the SSPBUF register completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data is written to the SSPBUF. The BF bit of the
SSPSTAT register is set when SSPBUF has been
loaded with the received data (transmission is
complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. The SSP interrupt may be used to
determine when the transmission/reception is
complete and the SSPBUF must be read and/or
written. If interrupts are not used, then software polling
can be done to ensure that a write collision does not
occur. Example 17-1 shows the loading of the SSPBUF
(SSPSR) for data transmission.
Note:
17.1.1.2
The SSPSR is not directly readable or
writable and can only be accessed by
addressing the SSPBUF register.
Enabling Master I/O
To enable the serial port, the SSPEN bit of the
SSPCON register, must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON register and then set the SSPEN bit. If a
Master mode of operation is selected in the SSPM bits
of the SSPCON register, the SDI, SDO and SCK pins
will be assigned as serial port pins.
17.1.1.3
Master Mode Setup
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is loaded with a byte
value. If the master is only going to receive, SDO output
could be disabled (programmed and used as an input).
The SSPSR register will continue to shift in the signal
present on the SDI pin at the programmed clock rate.
When initializing SPI Master mode operation, several
options need to be specified. This is accomplished by
programming the appropriate control bits in the
SSPCON and SSPSTAT registers. These control bits
allow the following to be specified:
•
•
•
•
•
SCK as clock output
Idle state of SCK (CKP bit)
Data input sample phase (SMP bit)
Output data on rising/falling edge of SCK (CKE bit)
Clock bit rate
In Master mode, the SPI clock rate (bit rate) is user
selectable to be one of the following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 TCY)
FOSC/64 (or 16 TCY)
(Timer2 output)/2
This allows a maximum data rate of 5 Mbps
(at FOSC = 20 MHz).
Figure 17-3 shows the waveforms for Master mode.
The clock polarity is selected by appropriately programming the CKP bit of the SSPCON register. When the
CKE bit is set, the SDO data is valid before there is a
clock edge on SCK. The sample time of the input data
is shown based on the state of the SMP bit and can
occur at the middle or end of the data output time. The
time when the SSPBUF is loaded with the received
data is shown.
17.1.1.4
Sleep in Master Mode
In Master mode, all module clocks are halted and the
transmission/reception will remain in their current state,
paused, until the device wakes from Sleep. After the
device wakes up from Sleep, the module will continue
to transmit/receive data.
For these pins to function as serial port pins, they must
have their corresponding data direction bits set or
cleared in the associated TRIS register as follows:
• SDI configured as input
• SDO configured as output
• SCK configured as output
2007-2015 Microchip Technology Inc.
DS40001341F-page 161
PIC16(L)F722/3/4/6/7
FIGURE 17-3:
SPI MASTER MODE WAVEFORM
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
EXAMPLE 17-1:
LOOP
BANKSEL
BTFSS
GOTO
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
LOADING THE SSPBUF (SSPSR) REGISTER
SSPSTAT
SSPSTAT, BF
LOOP
SSPBUF
SSPBUF, W
RXDATA
TXDATA, W
SSPBUF
DS40001341F-page 162
;
;Has data been received(transmit complete)?
;No
;
;WREG reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
17.1.2
SLAVE MODE
For any SPI device acting as a slave, the data is
transmitted and received as external clock pulses
appear on SCK pin. This external clock must meet the
minimum high and low times as specified in the
electrical specifications.
17.1.2.1
Slave Mode Operation
The SSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready.
The slave has no control as to when data will be
clocked in or out of the device. All data that is to be
transmitted, to a master or another slave, must be
loaded into the SSPBUF register before the first clock
pulse is received.
Once eight bits of data have been received:
• Received byte is moved to the SSPBUF register
• BF bit of the SSPSTAT register is set
• SSPIF bit of the PIR1 register is set
Any write to the SSPBUF register during
transmission/reception of data will be ignored and the
Write Collision Detect bit, WCOL of the SSPCON
register, will be set. User software must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed
successfully.
The user’s firmware must read SSPBUF, clearing the
BF flag, or the SSPOV bit of the SSPCON register will
be set with the reception of the next byte and
communication will be disabled.
A SPI module transmits and receives at the same time,
occasionally
causing
dummy
data
to
be
transmitted/received. It is up to the user to determine
which data is to be used and what can be discarded.
2007-2015 Microchip Technology Inc.
17.1.2.2
Enabling Slave I/O
To enable the serial port, the SSPEN bit of the
SSPCON register must be set. If a Slave mode of
operation is selected in the SSPM bits of the SSPCON
register, the SDI, SDO, SCK pins will be assigned as
serial port pins.
For these pins to function as serial port pins, they must
have their corresponding data direction bits set or
cleared in the associated TRIS register as follows:
• SDI configured as input
• SDO configured as output
• SCK configured as input
Optionally, a fourth pin, Slave Select (SS) may be used
in Slave mode. Slave Select may be configured to
operate on one of the following pins via the SSSEL bit in
the APFCON register.
• RA5/AN4/SS
• RA0/AN0/SS
Upon selection of a Slave Select pin, the appropriate
bits must be set in the ANSELA and TRISA registers.
Slave Select must be set as an input by setting the
corresponding bit in TRISA, and digital I/O must be
enabled on the SS pin by clearing the corresponding bit
of the ANSELA register.
17.1.2.3
Slave Mode Setup
When initializing the SSP module to SPI Slave mode,
compatibility must be ensured with the master device.
This is done by programming the appropriate control
bits of the SSPCON and SSPSTAT registers. These
control bits allow the following to be specified:
•
•
•
•
SCK as clock input
Idle state of SCK (CKP bit)
Data input sample phase (SMP bit)
Output data on rising/falling edge of SCK (CKE bit)
Figure 17-4 and Figure 17-5 show example waveforms
of Slave mode operation.
DS40001341F-page 163
PIC16(L)F722/3/4/6/7
FIGURE 17-4:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
bit 7
SDI
(SMP = 0)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 6
bit 7
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS40001341F-page 164
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
17.1.2.4
Slave Select Operation
The SS pin allows Synchronous Slave mode operation.
The SPI must be in Slave mode with SS pin control
enabled (SSPM = 0100). The associated TRIS bit
for the SS pin must be set, making SS an input.
Note:
In Slave Select mode, when:
• SS = 0, The device operates as specified in
Section 17.1.2 “Slave Mode”.
• SS = 1, The SPI module is held in Reset and the
SDO pin will be tri-stated.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPM = 0100),
the SPI module will reset if the SS pin is
driven high.
2: If the SPI is used in Slave mode with CKE
set, the SS pin control must be enabled.
FIGURE 17-6:
When the SPI module resets, the bit counter is cleared
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit. Figure 17-6
shows the timing waveform for such a synchronization
event.
17.1.2.5
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
Sleep in Slave Mode
While in Sleep mode, the slave can transmit/receive
data. The SPI Transmit/Receive Shift register operates
asynchronously to the device on the externally supplied
clock source. This allows the device to be placed in
Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have
been received, the SSP Interrupt Flag bit will be set and
if enabled, will wake the device from Sleep.
SLAVE SELECT SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
SSPSR must be reinitialized by writing to
the SSPBUF register before the data can
be clocked out of the slave again.
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
2007-2015 Microchip Technology Inc.
DS40001341F-page 165
PIC16(L)F722/3/4/6/7
REGISTER 17-1:
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of
overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the
overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register.
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins(1)
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0
SSPM: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
Note 1:
When enabled, these pins must be properly configured as input or output.
DS40001341F-page 166
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 17-2:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
bit 6
CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1 = Data stable on rising edge of SCK
0 = Data stable on falling edge of SCK
SPI mode, CKP = 1:
1 = Data stable on falling edge of SCK
0 = Data stable on rising edge of SCK
bit 5
D/A: Data/Address bit
Used in I2C mode only.
bit 4
P: Stop bit
Used in I2C mode only.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write Information bit
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
2007-2015 Microchip Technology Inc.
x = Bit is unknown
DS40001341F-page 167
PIC16(L)F722/3/4/6/7
TABLE 17-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
--11 1111
ANSELA
—
—
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
APFCON
—
—
—
—
—
—
SSSEL
CCP2SEL
---- --00
---- --00
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PIR1
TMR1GIF
0000 0000
0000 0000
PR2
Timer2 Period Register
1111 1111
1111 1111
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
1111 1111
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
Legend:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
DS40001341F-page 168
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
I2C Mode
17.2
FIGURE 17-8:
The SSP module, in I2C mode, implements all slave
functions, except general call support. It provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the I2C Standard mode
specifications:
VDD
Data is sampled on the rising edge and shifted out on
the falling edge of the clock. This ensures that the SDA
signal is valid during the SCL high time. The SCL clock
input must have minimum high and low times for proper
operation. Refer to Section 23.0 “Electrical
Specifications”.
I2C MODE BLOCK
DIAGRAM
FIGURE 17-7:
Internal
Data Bus
Read
Write
SSPBUF Reg
SCL
VDD
Slave 1
Master
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
Start and Stop bit interrupts enabled to support
firmware Master mode
• Address masking
•
•
•
Two pins are used for data transfer; the SCL pin (clock
line) and the SDA pin (data line). The user must
configure the two pin’s data direction bits as inputs in
the appropriate TRIS register. Upon enabling I2C
mode, the I2C slew rate limiters in the I/O pads are
controlled by the SMP bit of SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of SSPCON register.
TYPICAL I2C
CONNECTIONS
SDA
SDA
SCL
SCL
Slave 2
SDA
SCL
(optional)
The SSP module has six registers for I2C operation.
They are:
•
•
•
•
SSP Control (SSPCON) register
SSP Status (SSPSTAT) register
Serial Receive/Transmit Buffer (SSPBUF) register
SSP Shift Register (SSPSR), not directly
accessible
• SSP Address (SSPADD) register
• SSP Address Mask (SSPMSK) register
17.2.1
HARDWARE SETUP
Selection of I2C mode, with the SSPEN bit of the
SSPCON register set, forces the SCL and SDA pins to
be open drain, provided these pins are programmed as
inputs by setting the appropriate TRISC bits. The SSP
module will override the input state with the output data,
when required, such as for Acknowledge and
slave-transmitter sequences.
Shift
Clock
Note:
SSPSR Reg
SDA
LSb
MSb
Pull-up resistors must be provided
externally to the SCL and SDA pins for
proper operation of the I2C module
SSPMSK Reg
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
2007-2015 Microchip Technology Inc.
DS40001341F-page 169
PIC16(L)F722/3/4/6/7
17.2.2
START AND STOP CONDITIONS
During times of no data transfer (Idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through external pull-up resistors. The Start and Stop
conditions determine the start and stop of data transmission. The Start condition is defined as a high-to-low
transition of the SDA line while SCL is high. The Stop
condition is defined as a low-to-high transition of the
SDA line while SCL is high.
Figure 17-9 shows the Start and Stop conditions. A
master device generates these conditions for starting
and terminating data transfer. Due to the definition of
the Start and Stop conditions, when data is being
transmitted, the SDA line can only change state when
the SCL line is low.
FIGURE 17-9:
17.2.3
ACKNOWLEDGE
After the valid reception of an address or data byte, the
hardware automatically will generate the Acknowledge
(ACK) pulse and load the SSPBUF register with the
received value currently in the SSPSR register. There
are certain conditions that will cause the SSP module
not to generate this ACK pulse. They include any or all
of the following:
• The Buffer Full bit, BF of the SSPSTAT register,
was set before the transfer was received.
• The SSP Overflow bit, SSPOV of the SSPCON
register, was set before the transfer was received.
• The SSP Module is being operated in Firmware
Master mode.
In such a case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 17-2 shows the results of when a data
transfer byte is received, given the status of bits BF and
SSPOV. Flag bit BF is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
START AND STOP CONDITIONS
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
TABLE 17-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
BF
0
1
1
0
Note 1:
Stop
Condition
SSPOV
SSPSR SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
0
Yes
Yes
Yes
0
No
No
Yes
1
No
No
Yes
1
No
No
Yes
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
DS40001341F-page 170
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
17.2.4
ADDRESSING
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the eight bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock line (SCL).
17.2.4.1
7-bit Addressing
In 7-bit Addressing mode (Figure 17-10), the value of
register SSPSR is compared to the value of
register SSPADD. The address is compared on
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
• The SSPSR register value is loaded into the
SSPBUF register.
• The BF bit is set.
• An ACK pulse is generated.
• SSP interrupt flag bit, SSPIF of the PIR1 register,
is set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
17.2.4.2
10-bit Addressing
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 17-11). The five Most
Significant bits (MSbs) of the first address byte specify
if it is a 10-bit address. The R/W bit of the SSPSTAT
register must specify a write so the slave device will
receive the second address byte. For a 10-bit address,
the first byte would equal ‘1111 0 A9 A8 0’, where
A9 and A8 are the two MSbs of the address.
2007-2015 Microchip Technology Inc.
The sequence of events for 10-bit address is as follows
for reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Load SSPADD register with high byte of address.
Receive first (high) byte of address (bits SSPIF,
BF and UA of the SSPSTAT register are set).
Read the SSPBUF register (clears bit BF).
Clear the SSPIF flag bit.
Update the SSPADD register with second (low)
byte of address (clears UA bit and releases the
SCL line).
Receive low byte of address (bits SSPIF, BF and
UA are set).
Update the SSPADD register with the high byte
of address. If match releases SCL line, this will
clear bit UA.
Read the SSPBUF register (clears bit BF).
Clear flag bit SSPIF.
If data is requested by the master, once the slave has
been addressed:
1.
2.
3.
4.
5.
Receive repeated Start condition.
Receive repeat of high byte address with
R/W = 1, indicating a read.
BF bit is set and the CKP bit is cleared, stopping
SCL and indicating a read request.
SSPBUF is written, setting BF, with the data to
send to the master device.
CKP is set in software, releasing the SCL line.
17.2.4.3
Address Masking
The Address Masking register (SSPMSK) is only
accessible while the SSPM bits of the SSPCON
register are set to ‘1001’. In this register, the user can
select which bits of a received address the hardware
will compare when determining an address match. Any
bit that is set to a zero in the SSPMSK register, the
corresponding bit in the received address byte and
SSPADD register are ignored when determining an
address match. By default, the register is set to all
ones, requiring a complete match of a 7-bit address or
the lower eight bits of a 10-bit address.
DS40001341F-page 171
PIC16(L)F722/3/4/6/7
17.2.5
RECEPTION
When the R/W bit of the received address byte is clear,
the master will write data to the slave. If an address
match occurs, the received address is loaded into the
SSPBUF register. An address byte overflow will occur
if that loaded address is not read from the SSPBUF
before the next complete byte is received.
An SSP interrupt is generated for each data transfer byte.
The BF, R/W and D/A bits of the SSPSTAT register are
used to determine the status of the last received byte.
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 17-10:
R/W = 0
ACK
Receiving Address
A7 A6 A5 A4 A3 A2 A1
SDA
SCL
S
1
2
3
SSPIF
BF
4
5
6
7
Receiving Data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
8
9
1
2
3
4
5
6
7
8
9
Receiving Data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
Cleared in software
9
P
Bus Master
sends Stop
condition
SSPBUF register is read
SSPOV
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
DS40001341F-page 172
2007-2015 Microchip Technology Inc.
2007-2015 Microchip Technology Inc.
CKP
UA
SSPOV
BF
SSPIF
1
SCL
S
1
SDA
3
1
4
1
5
0
6
7
8
9
UA is set indicating
that the SSPADD needs to
be updated
SSPBUF is written
with contents of SSPSR
Cleared in software
2
1
2
4
5
6
7
Cleared in software
3
UA is set indicating
that SSPADD needs to
be updated
Cleared by hardware
when SSPADD is updated
with low byte of address
8
A6 A5 A4 A3 A2 A1 A0
Dummy read of SSPBUF
to clear BF flag
1
A7
Receive Second Byte of Address
9
ACK
1
4
5
6
7
Cleared in software
3
8
Cleared by hardware when
SSPADD is updated with high
byte of address
2
D7 D6 D5 D4 D3 D2 D1 D0
Receive Data Byte
Clock is held low until
update of SSPADD has
taken place
9
ACK
Receive Data Byte
1
2
4
5
6
7
Cleared in software
3
8
D7 D6 D5 D4 D3 D2 D1 D0
P
Bus master
sends Stop
condition
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
FIGURE 17-11:
R/W ACK
A9 A8 0
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC16(L)F722/3/4/6/7
I2C SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
DS40001341F-page 173
PIC16(L)F722/3/4/6/7
17.2.6
TRANSMISSION
When the R/W bit of the received address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set and the slave will respond to
the master by reading out data. After the address match,
an ACK pulse is generated by the slave hardware and
the SCL pin is held low (clock is automatically stretched)
until the slave is ready to respond. See Section 17.2.7
“Clock Stretching”. The data the slave will transmit
must be loaded into the SSPBUF register, which sets
the BF bit. The SCL line is released by setting the CKP
bit of the SSPCON register.
Following the eighth falling clock edge, control of the
SDA line is released back to the master so that the
master can acknowledge or not acknowledge the
response. If the master sends a not acknowledge, the
slave’s transmission is complete and the slave must
monitor for the next Start condition. If the master
acknowledges, control of the bus is returned to the
slave to transmit another byte of data. Just as with the
previous byte, the clock is stretched by the slave, data
must be loaded into the SSPBUF and CKP must be set
to release the clock line (SCL).
An SSP interrupt is generated for each transferred data
byte. The SSPIF flag bit of the PIR1 register initiates an
SSP interrupt, and must be cleared by software before
the next byte is transmitted. The BF bit of the SSPSTAT
register is cleared on the falling edge of the eighth
received clock pulse. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 17-12:
Receiving Address
SDA
SCL
A7
S
A6
1
2
Data in
sampled
R/W
A5
A4
A3
A2
A1
3
4
5
6
7
8
ACK
Transmitting Data
ACK
9
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
Cleared in software
SSPIF
BF
Dummy read of SSPBUF
to clear BF flag
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS40001341F-page 174
2007-2015 Microchip Technology Inc.
2007-2015 Microchip Technology Inc.
CKP
UA
BF
SSPIF
1
SCL
S
1
2
1
4
1
5
0
6
7
A9 A8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
8
9
ACK
R/W = 0
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address.
6
A6 A5 A4 A3 A2 A1
8
A0
Receive Second Byte of Address
Dummy read of SSPBUF
to clear BF flag
A7
9
ACK
Clock is held low until
update of SSPADD has
taken place
2
3
1
4
1
Cleared in software
1
1
5
0
6
7
A9 A8
Cleared by hardware when
SSPADD is updated with high
byte of address.
Dummy read of SSPBUF
to clear BF flag
Sr
1
Receive First Byte of Address
Bus Master
sends Restarts
condition
8
9
ACK
R/W = 1
4
5
6
Cleared in software
3
Write of SSPBUF
2
9
P
Completion of
data transmission
clears BF flag
8
ACK
CKP is automatically cleared in hardware holding SCL low
CKP is set in software, initiates transmission
7
D4 D3 D2 D1 D0
Dummy read of SSPBUF
to clear BF flag
1
D7 D6 D5
Transmitting Data Byte
Clock is held low until
CKP is set to ‘1’
Bus Master
sends Stop
condition
FIGURE 17-13:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC16(L)F722/3/4/6/7
I2C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)
DS40001341F-page 175
PIC16(L)F722/3/4/6/7
17.2.7
CLOCK STRETCHING
2
During any SCL low phase, any device on the I C bus
may hold the SCL line low and delay, or pause, the
transmission of data. This “stretching” of a transmission
allows devices to slow down communication on the
bus. The SCL line must be constantly sampled by the
master to ensure that all devices on the bus have
released SCL for more data.
Stretching usually occurs after an ACK bit of a
transmission, delaying the first bit of the next byte. The
SSP module hardware automatically stretches for two
conditions:
• After a 10-bit address byte is received (update
SSPADD register)
• Anytime the CKP bit of the SSPCON register is
cleared by hardware
The module will hold SCL low until the CKP bit is set.
This allows the user slave software to update SSPBUF
with data that may not be readily available. In 10-bit
addressing modes, the SSPADD register must be
updated after receiving the first and second address
bytes. The SSP module will hold the SCL line low until
the SSPADD has a byte written to it. The UA bit of the
SSPSTAT register will be set, along with SSPIF,
indicating an address update is needed.
17.2.8
FIRMWARE MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and Stop conditions. The Stop (P) and Start (S) bits of
the SSPSTAT register are cleared from a Reset or
when the SSP module is disabled (SSPEN cleared).
The Stop (P) and Start (S) bits will toggle based on the
Start and Stop conditions. Control of the I2C bus may
be taken when the P bit is set or the bus is Idle and both
the S and P bits are clear.
Refer to Application Note AN554, Software
Implementation of I2C™ Bus Master (DS00554) for more
information.
17.2.9
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allow the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the SSP
module is disabled. The Stop (P) and Start (S) bits will
toggle based on the Start and Stop conditions. Control
of the I2C bus may be taken when the P bit of the
SSPSTAT register is set or when the bus is Idle, and
both the S and P bits are clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the Stop condition occurs.
In Multi-Master operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRIS bits). There are two stages
where this arbitration of the bus can be lost. They are
the Address Transfer and Data Transfer stages.
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address
transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data
transfer stage, the device will need to re-transfer the
data at a later time.
Refer to Application Note AN578, Use of the SSP
Module in the I2C™ Multi-Master Environment
(DS00578) for more information.
In Firmware Master mode, the SCL and SDA lines are
manipulated by setting/clearing the corresponding TRIS
bit(s). The output level is always low, irrespective of the
value(s) in the corresponding PORT register bit(s).
When transmitting a ‘1’, the TRIS bit must be set (input)
and a ‘0’, the TRIS bit must be clear (output).
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt will occur if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Firmware Master Mode of operation can be done with
either the Slave mode Idle (SSPM = 1011), or
with either of the Slave modes in which interrupts are
enabled. When both master and slave functionality is
enabled, the software needs to differentiate the
source(s) of the interrupt.
DS40001341F-page 176
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
17.2.10
CLOCK SYNCHRONIZATION
When the CKP bit is cleared, the SCL output is held low
once it is sampled low. therefore, the CKP bit will not
stretch the SCL line until an external I2C master device
has already asserted the SCL line low. The SCL output
will remain low until the CKP bit is set and all other
devices on the I2C bus have released SCL. This
ensures that a write to the CKP bit will not violate the
minimum
high
time
requirement
for
SCL
(Figure 17-14).
FIGURE 17-14:
17.2.11
SLEEP OPERATION
While in Sleep mode, the I2C module can receive
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON
2007-2015 Microchip Technology Inc.
DS40001341F-page 177
PIC16(L)F722/3/4/6/7
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE)
REGISTER 17-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
1 = Release control of SCL
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM: Synchronous Serial Port Mode Select bits
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = Reserved
1001 = Load SSPMSK register at SSPADD SFR Address(1)
1010 = Reserved
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register.
2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.
DS40001341F-page 178
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 17-4:
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: SPI Data Input Sample Phase bit
1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard Mode (100 kHz and 1 MHz).
0 = Slew Rate Control (limiting) enabled. Operating in I2C Fast Mode (400 kHz).
bit 6
CKE: SPI Clock Edge Select bit
This bit must be maintained clear. Used in SPI mode only.
bit 5
D/A: DATA/ADDRESS bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2
R/W: READ/WRITE bit Information
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit or ACK bit.
1 = Read
0 = Write
bit 1
UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit:
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
2007-2015 Microchip Technology Inc.
DS40001341F-page 179
PIC16(L)F722/3/4/6/7
REGISTER 17-5:
SSPMSK: SSP MASK REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
MSK: Mask bits
1 = The received address bit n is compared to SSPADD to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0
MSK: Mask bit for I2C Slave Mode, 10-bit Address
I2C Slave Mode, 10-bit Address (SSPM = 0111):
1 = The received address bit ‘0’ is compared to SSPADD to detect I2C address match
0 = The received address bit ‘0’ is not used to detect I2C address match
All other SSP modes: this bit has no effect.
SSPADD: SSP I2C ADDRESS REGISTER
REGISTER 17-6:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADD: Address bits
Received address
TABLE 17-7:
Name
INTCON
PIR1
PIE1
SSPBUF
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
Synchronous Serial Port (I C mode) Address Register
(2)
SSPMSK
SSPSTAT
Note 1:
2:
Bit 7
2
SSPADD
TRISC
REGISTERS ASSOCIATED WITH I2C OPERATION
Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON
Legend:
x = Bit is unknown
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
1111 1111
1111 1111
R/W
UA
BF
0000 0000
0000 0000
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
2
Synchronous Serial Port (I C mode) Address Mask Register
SMP(1)
CKE(1)
D/A
TRISC7
TRISC6
TRISC5
P
S
TRISC4 TRISC3
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in I2C
mode.
Maintain these bits clear in I2C mode.
Accessible only when SSPM = 1001.
DS40001341F-page 180
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
18.0
PROGRAM MEMORY READ
The Flash program memory is readable during normal
operation over the full VDD range of the device. To read
data from Program Memory, five Special Function
Registers (SFRs) are used:
•
•
•
•
•
PMCON1
PMDATL
PMDATH
PMADRL
PMADRH
The value written to the PMADRH:PMADRL register
pair determines which program memory location is
read. The read operation will be initiated by setting the
RD bit of the PMCON1 register. The program memory
flash controller takes two instructions to complete the
read, causing the second instruction after the setting
the RD bit will be ignored. To avoid conflict with
program execution, it is recommended that the two
instructions following the setting of the RD bit are NOP.
When the read completes, the result is placed in the
PMDATLH:PMDATL
register
pair.
Refer
to
Example 18-1 for sample code.
Note:
Required
Sequence
EXAMPLE 18-1:
Code-protect does not effect the CPU
from performing a read operation on the
program memory. For more information,
refer to Section 8.2 “Code Protection”.
PROGRAM MEMORY READ
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BANKSEL
BSF
NOP
NOP
PMADRL
;
MS_PROG_ADDR, W ;
PMADRH
;MS Byte of Program Address to read
LS_PROG_ADDR, W ;
PMADRL
;LS Byte of Program Address to read
PMCON1
;
PMCON1, RD
;Initiate Read
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
PMDATL
PMDATL, W
LOWPMBYTE
PMDATH, W
HIGHPMBYTE
2007-2015 Microchip Technology Inc.
;Any instructions here are ignored as program
;memory is read in second cycle after BSF
;
;W = LS Byte of Program Memory Read
;
;W = MS Byte of Program Memory Read
;
DS40001341F-page 181
PIC16(L)F722/3/4/6/7
REGISTER 18-1:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
R-1
U-0
U-0
U-0
U-0
U-0
U-0
R/S-0
Reserved
—
—l
—
—
—
—
RD
bit 7
bit 0
Legend:
S = Setable bit, cleared in hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Reserved: Read as ‘1’. Maintain this bit set.
bit 6-1
Unimplemented: Read as ‘0’
bit 0
RD: Read Control bit
1 = Initiates an program memory read (The RD is cleared in hardware; the RD bit can only be set (not
cleared) in software).
0 = Does not initiate a program memory read
REGISTER 18-2:
PMDATH: PROGRAM MEMORY DATA HIGH REGISTER
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
PMD13
PMD12
PMD11
PMD10
PMD9
PMD8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMD: The value of the program memory word pointed to by PMADRH and PMADRL after a
program memory read command.
REGISTER 18-3:
PMDATL: PROGRAM MEMORY DATA LOW REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PMD7
PMD6
PMD5
PMD4
PMD3
PMD2
PMD1
PMD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
PMD: The value of the program memory word pointed to by PMADRH and PMADRL after a
program memory read command.
DS40001341F-page 182
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
REGISTER 18-4:
PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
PMA12
PMA11
PMA10
PMA9
PMA8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
PMA: Program Memory Read Address bits
REGISTER 18-5:
x = Bit is unknown
PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PMA7
PMA6
PMA5
PMA4
PMA3
PMA2
PMA1
PMA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMA: Program Memory Read Address bits
TABLE 18-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ
Bit 7
Bit 6
Bit 5
PMCON1
Reserved
—
—
PMADRH
—
—
—
PMADRL
PMDATH
PMDATL
Legend:
x = Bit is unknown
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
RD
Program Memory Read Address Register High Byte
Program Memory Read Address Register Low Byte
—
—
Program Memory Read Data Register High Byte
Program Memory Read Data Register Low Byte
Value on
POR, BOR
Value on all
other Resets
1--- ---0
1--- ---0
---x xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
--xx xxxx
xxxx xxxx
xxxx xxxx
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Program Memory
Read.
2007-2015 Microchip Technology Inc.
DS40001341F-page 183
PIC16(L)F722/3/4/6/7
19.0
POWER-DOWN MODE (SLEEP)
The following peripheral interrupts can wake the device
from Sleep:
The Power-down mode is entered by executing a
SLEEP instruction.
1.
If the Watchdog Timer is enabled:
2.
•
•
•
•
•
•
3.
4.
5.
6.
7.
WDT will be cleared but keeps running.
PD bit of the STATUS register is cleared.
TO bit of the STATUS register is set.
Oscillator driver is turned off.
Timer1 oscillator is unaffected
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or highimpedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS, with no external
circuitry drawing current from the I/O pin. I/O pins that
are high-impedance inputs should be pulled high or low
externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level when
external MCLR is enabled.
Note:
TMR1 Interrupt. Timer1 must be operating as an
asynchronous counter.
USART Receive Interrupt (Synchronous Slave
mode only)
A/D conversion (when A/D clock source is RC)
Interrupt-on-change
External Interrupt from INT pin
Capture event on CCP1 or CCP2
SSP Interrupt in SPI or I2C Slave mode
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
A Reset generated by a WDT time out
does not drive MCLR pin low.
Note:
19.1
Wake-up from Sleep
The device can wake up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from RB0/INT pin, PORTB change or a
peripheral interrupt.
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
DS40001341F-page 184
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
19.2
Wake-up Using Interrupts
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
FIGURE 19-1:
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON reg.)
Interrupt Latency (3)
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
PC + 1
Inst(PC) = Sleep
Inst(PC - 1)
PC + 2
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
TABLE 19-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
0000 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 0000
0000 0000
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIR2
—
—
—
—
—
—
—
CCP2IF
---- ---0
---- ---0
INTCON
Legend:
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.
2007-2015 Microchip Technology Inc.
DS40001341F-page 185
PIC16(L)F722/3/4/6/7
20.0
IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
The device is placed into Program/Verify mode by
holding the ICSPCLK and ICSPDAT pins low then
raising the voltage on MCLR/VPP from 0v to VPP. In
Program/Verify mode the program memory, User IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data and
the ISCPCLK pin is the clock input. For more information
on ICSP, refer to the “PIC16(L)F72x Memory
Programming Specification” (DS41332).
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
FIGURE 20-1:
Note:
The ICD 2 produces a VPP voltage greater
than the maximum VPP specification of the
PIC16(L)F722/3/4/6/7. When using this
programmer, an external circuit, such as
the AC164112 MPLAB ICD 2 VPP voltage
limiter, is required to keep the VPP voltage
within the device specifications.
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
10k
VPP
MCLR/VPP
GND
VSS
Data
ICSPDAT
Clock
ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
DS40001341F-page 186
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
21.0
INSTRUCTION SET SUMMARY
The PIC16(L)F722/3/4/6/7 instruction set is highly
orthogonal and is comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
TABLE 21-1:
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 21-1, while the various opcode
fields are summarized in Table 21-1.
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0. It is
the recommended form of use for
compatibility with all Microchip software tools.
d
Table 21-2 lists the instructions recognized by the
MPASMTM assembler.
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
C
Carry bit
DC
Z
Digit carry bit
Zero bit
PD
Power-down bit
FIGURE 21-1:
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution time of 1 s. All
instructions are executed within a single instruction
cycle, unless a conditional test is true, or the program
counter is changed as a result of an instruction. When
this occurs, the execution takes two instruction cycles,
with the second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
21.1
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
GENERAL FORMAT FOR
INSTRUCTIONS
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
For example, a CLRF PORTB instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the
unintended consequence of clearing the condition that
set the RBIF flag.
2007-2015 Microchip Technology Inc.
DS40001341F-page 187
PIC16(L)F722/3/4/6/7
TABLE 21-2:
PIC16(L)F722/3/4/6/7 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1:
2:
3:
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS40001341F-page 188
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
21.2
Instruction Descriptions
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register
are added to the 8-bit literal ‘k’
and the result is placed in the
W register.
k
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 127
0b7
Operation:
0 (f)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[ label ] BSF
f,b
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d 0,1
Operands:
0 f 127
0b7
Operation:
(W) + (f) (destination)
Operation:
1 (f)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
Description:
Bit ‘b’ in register ‘f’ is set.
ANDLW
AND literal with W
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BTFSC f,b
Operands:
0 k 255
Operands:
Operation:
(W) .AND. (k) (W)
0 f 127
0b7
Status Affected:
Z
Operation:
skip if (f) = 0
Description:
The contents of W register are
AND’ed with the 8-bit literal ‘k’.
The result is placed in the W register.
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2-cycle instruction.
ANDWF
f,d
k
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
Operation:
(W) .AND. (f) (destination)
f,d
Status Affected:
Z
Description:
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
2007-2015 Microchip Technology Inc.
f,b
DS40001341F-page 189
PIC16(L)F722/3/4/6/7
BTFSS
Bit Test f, Skip if Set
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
0b VDD)20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin............................................................................................... 25 mA
Maximum current sunk by all ports(2), -40°C TA +85°C for industrial ........................................................ 200 mA
Maximum current sunk by all ports(2), -40°C TA +125°C for extended ........................................................ 90 mA
Maximum current sourced by all ports(2), 40°C TA +85°C for industrial ................................................... 140 mA
Maximum current sourced by all ports(2), -40°C TA +125°C for extended................................................... 65 mA
Note 1:
Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS40001341F-page 200
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
23.1
DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Industrial, Extended)
PIC16LF722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param.
No.
D001
Sym.
VDD
D001
D002*
VDR
D002*
D003
Min.
Typ†
Max.
Units
PIC16LF722/3/4/6/7
1.8
1.8
2.3
2.5
—
—
—
—
3.6
3.6
3.6
3.6
V
V
V
V
FOSC 16 MHz: HFINTOSC, EC
FOSC 4 MHz
FOSC 20 MHz, EC
FOSC 20 MHz, HS
PIC16F722/3/4/6/7
1.8
1.8
2.3
2.5
—
—
—
—
5.5
5.5
5.5
5.5
V
V
V
V
FOSC 16 MHz: HFINTOSC, EC
FOSC 4 MHz
FOSC 20 MHz, EC
FOSC 20 MHz, HS
PIC16LF722/3/4/6/7
1.5
—
—
V
Device in Sleep mode
PIC16F722/3/4/6/7
1.7
—
—
V
Device in Sleep mode
—
1.6
—
V
RAM Data Retention Voltage(1)
Power-on Reset Release Voltage
VPORR*
Power-on Reset Rearm Voltage
SVDD
Conditions
Supply Voltage
VPOR*
VFVR
D004*
Characteristic
PIC16LF722/3/4/6/7
—
0.8
—
V
Device in Sleep mode
PIC16F722/3/4/6/7
—
1.7
—
V
Device in Sleep mode
-8
-8
-8
—
—
—
6
6
6
%
%
%
VFVR = 1.024V, VDD 2.5V
VFVR = 2.048V, VDD 2.5V
VFVR = 4.096V, VDD 4.75V;
-40 TA85°C
-8
-8
-8
—
—
—
6
6
6
%
%
%
VFVR = 1.024V, VDD 2.5V
VFVR = 2.048V, VDD 2.5V
VFVR = 4.096V, VDD 4.75V;
-40 TA125°C
0.05
—
—
V/ms
Fixed Voltage Reference Voltage,
Initial Accuracy
VDD Rise Rate to ensure internal
Power-on Reset signal
See Section 3.2 “Power-on Reset
(POR)” for details.
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2007-2015 Microchip Technology Inc.
DS40001341F-page 201
PIC16(L)F722/3/4/6/7
FIGURE 23-1:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
DS40001341F-page 202
TPOR(3)
When NPOR is low, the device is held in Reset.
TPOR 1 s typical.
TVLOW 2.7 s typical.
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
23.2
DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Industrial, Extended)
PIC16LF722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics
Conditions
Min.
Typ†
Max.
Units
VDD
Note
Supply Current (IDD)(1, 2)
LDO Regulator
D009
D010
D010
D011
D011
D011
D011
D012
D012
—
350
—
A
—
HS, EC OR INTOSC/INTOSCIO (8-16 MHZ)
Clock modes with all VCAP pins disabled
—
50
—
A
—
All VCAP pins disabled
—
30
—
A
—
VCAP enabled on RA0, RA5 or RA6
—
5
—
A
—
LP Clock mode and Sleep (requires FVR and
BOR to be disabled)
—
7.0
12
A
1.8
—
9.0
14
A
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C TA +85°C
—
11
20
A
1.8
—
14
22
A
3.0
—
15
24
A
5.0
—
7.0
12
A
1.8
—
9.0
18
A
3.0
—
11
21
A
1.8
—
14
25
A
3.0
—
15
27
A
5.0
—
110
150
A
1.8
—
150
215
A
3.0
—
120
175
A
1.8
—
180
250
A
3.0
—
240
300
A
5.0
—
230
300
A
1.8
—
400
600
A
3.0
—
250
350
A
1.8
—
420
650
A
3.0
—
500
750
A
5.0
D013
—
125
180
A
1.8
—
230
270
A
3.0
D013
—
150
205
A
1.8
—
225
320
A
3.0
—
250
410
A
5.0
Note 1:
2:
3:
4:
5:
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40°C TA +85°C
FOSC = 32 kHz
LP Oscillator mode
-40°C TA +125°C
FOSC = 32 kHz
LP Oscillator mode (Note 4)
-40°C TA +125°C
FOSC = 1 MHz
XT Oscillator mode
FOSC = 1 MHz
XT Oscillator mode (Note 5)
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode (Note 5)
FOSC = 1 MHz
EC Oscillator mode
FOSC = 1 MHz
EC Oscillator mode (Note 5)
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
FVR and BOR are disabled.
0.1 F capacitor on VCAP (RA0).
2007-2015 Microchip Technology Inc.
DS40001341F-page 203
PIC16(L)F722/3/4/6/7
23.2
DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Industrial, Extended) (Continued)
PIC16LF722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device
Characteristics
Conditions
Min.
Typ†
Max.
Units
VDD
Note
Supply Current (IDD)(1, 2)
D014
D014
D015
D015
D016
D016
—
290
330
A
1.8
—
460
500
A
3.0
—
300
430
A
1.8
—
450
655
A
3.0
—
500
730
A
5.0
—
100
130
A
1.8
—
120
150
A
3.0
—
115
195
A
1.8
—
135
200
A
3.0
—
150
220
A
5.0
—
650
800
A
1.8
—
1000
1200
A
3.0
—
625
850
A
1.8
—
1000
1200
A
3.0
—
1100
1500
A
5.0
D017
—
1.0
1.2
mA
1.8
—
1.5
1.85
mA
3.0
D017
—
1
1.2
mA
1.8
—
1.5
1.7
mA
3.0
—
1.7
2.1
mA
5.0
—
210
240
A
1.8
—
340
380
A
3.0
—
225
320
A
1.8
—
360
445
A
3.0
D018
D018
D019
D019
Note 1:
2:
3:
4:
5:
—
410
650
A
5.0
—
1.6
1.9
mA
3.0
—
2.0
2.8
mA
3.6
—
1.6
2
mA
3.0
—
1.9
3.2
mA
5.0
FOSC = 4 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode (Note 5)
FOSC = 500 kHz
MFINTOSC mode
FOSC = 500 kHz
MFINTOSC mode (Note 5)
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode (Note 5)
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode (Note 5)
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
FOSC = 20 MHz
HS Oscillator mode
FOSC = 20 MHz
HS Oscillator mode (Note 5)
The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k
FVR and BOR are disabled.
0.1 F capacitor on VCAP (RA0).
DS40001341F-page 204
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
23.3
DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Power-Down)
PIC16LF722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device Characteristics
Power-down Base Current
Min.
Typ†
Conditions
Max.
+85°C
Max.
+125°C
Units
0.7
3.9
A
VDD
D020
—
0.02
—
0.08
1.0
4.3
A
3.0
D020
—
4.3
10.2
17
A
1.8
—
5
10.5
18
A
3.0
—
5.5
11.8
21
A
5.0
—
0.5
1.7
4.1
A
1.8
—
0.8
2.5
4.8
A
3.0
—
6
13.5
18
A
1.8
—
6.5
14.5
19
A
3.0
D021
D021
D021A
D021A
1.8
—
7.5
16
22
A
5.0
—
8.5
14
19
A
1.8
—
8.5
14
20
A
3.0
—
23
44
48
A
1.8
—
25
45
55
A
3.0
—
26
60
70
A
5.0
D022
—
—
—
—
A
1.8
—
7.5
12
22
A
3.0
D022
—
—
—
—
A
1.8
—
23
42
49
A
3.0
—
25
46
50
A
5.0
—
0.6
2
—
A
1.8
—
1.8
3.0
—
A
3.0
—
4.5
11.1
—
A
1.8
—
6
12.5
—
A
3.0
—
7
13.5
—
A
5.0
D026
D026
†
Note 1:
2:
3:
4:
5:
Note
(IPD)(2)
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
LPWDT Current (Note 1)
LPWDT Current (Note 1)
FVR current (Note 1. Note 3)
FVR current (Note 1, Note 3,
Note 5)
BOR Current (Note 1, Note 3)
BOR Current (Note 1, Note 3,
Note 5)
T1OSC Current (Note 1)
T1OSC Current (Note 1)
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
Fixed Voltage Reference is automatically enabled whenever the BOR is enabled
A/D oscillator source is FRC
0.1 F capacitor on VCAP (RA0).
2007-2015 Microchip Technology Inc.
DS40001341F-page 205
PIC16(L)F722/3/4/6/7
23.3
DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Power-Down) (Continued)
PIC16LF722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
PIC16F722/3/4/6/7
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Device Characteristics
Min.
Power-down Base Current (IPD)
D027
D027
Typ†
Conditions
Max.
+85°C
Max.
+125°C
Units
VDD
Note
A/D Current (Note 1, Note 4), no
conversion in progress
(2)
—
0.06
0.7
5.0
A
1.8
—
0.08
1.0
5.5
A
3.0
—
6
10.7
18
A
1.8
—
7
10.6
20
A
3.0
—
7.2
11.9
22
A
5.0
D027A
—
250
400
—
A
1.8
—
250
400
—
A
3.0
D027A
—
280
430
—
A
1.8
—
280
430
—
A
3.0
—
280
430
—
A
5.0
—
2.2
3.2
14.4
A
1.8
—
3.3
4.4
15.6
A
3.0
—
6.5
13
21
A
1.8
—
8
14
23
A
3.0
D028
D028
D028A
D028A
D028B
D028B
†
Note 1:
2:
3:
4:
5:
—
8
14
25
A
5.0
—
4.2
6
17
A
1.8
—
6
7
18
A
3.0
—
8.5
15.5
23
A
1.8
—
11
17
24
A
3.0
—
11
18
27
A
5.0
—
12
14
25
A
1.8
—
32
35
44
A
3.0
—
16
20
31
A
1.8
—
36
41
50
A
3.0
—
42
49
58
A
5.0
A/D Current (Note 1, Note 4), no
conversion in progress
A/D Current (Note 1, Note 4),
conversion in progress
A/D Current (Note 1, Note 4,
Note 5), conversion in progress
Cap Sense Low Power
Oscillator mode
Cap Sense Low Power
Oscillator mode
Cap Sense Medium Power
Oscillator mode
Cap Sense Medium Power
Oscillator mode
Cap Sense High Power
Oscillator mode
Cap Sense High Power
Oscillator mode
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
Fixed Voltage Reference is automatically enabled whenever the BOR is enabled
A/D oscillator source is FRC
0.1 F capacitor on VCAP (RA0).
DS40001341F-page 206
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
23.4
DC Characteristics: PIC16(L)F722/3/4/6/7-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Min.
Typ†
Max.
Units
—
—
with Schmitt Trigger buffer
with I2C levels
Conditions
—
0.8
V
4.5V VDD 5.5V
—
0.15 VDD
V
1.8V VDD 4.5V
—
—
0.2 VDD
V
2.0V VDD 5.5V
—
—
0.3 VDD
V
Input Low Voltage
I/O PORT:
D030
with TTL buffer
D030A
D031
D032
MCLR, OSC1 (RC mode)(1)
—
—
0.2 VDD
V
D033A
OSC1 (HS mode)
—
—
0.3 VDD
V
—
—
2.0
—
—
V
4.5V VDD 5.5V
0.25 VDD +
0.8
—
—
V
1.8V VDD 4.5V
with Schmitt Trigger buffer
0.8 VDD
—
—
V
2.0V VDD 5.5V
with I2C levels
0.7 VDD
—
—
V
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
D042
MCLR
0.8 VDD
—
—
V
D043A
OSC1 (HS mode)
0.7 VDD
—
—
V
D043B
OSC1 (RC mode)
0.9 VDD
—
—
V
(Note 1)
IIL
Input Leakage Current(2)
D060
I/O ports
—
±5
± 125
nA
±5
± 1000
nA
VSS VPIN VDD, Pin at highimpedance, 85°C
125°C
D061
MCLR(3)
—
± 50
± 200
nA
VSS VPIN VDD, 85°C
25
25
100
140
200
300
A
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
—
—
0.6
V
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
VDD - 0.7
—
—
V
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
—
—
15
pF
—
—
50
pF
IPUR
PORTB Weak Pull-up Current
D070*
VOL
D080
Output Low Voltage(4)
I/O ports
VOH
D090
Output High Voltage(4)
I/O ports
Capacitive Loading Specs on Output Pins
D101*
COSC2 OSC2 pin
D101A* CIO
All I/O pins
In XT, HS and LP modes when
external clock is used to drive
OSC1
Program Flash Memory
Legend:
*
†
Note 1:
2:
3:
4:
TBD = To Be Determined
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
2007-2015 Microchip Technology Inc.
DS40001341F-page 207
PIC16(L)F722/3/4/6/7
23.4
DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Continued)
DC CHARACTERISTICS
Param
No.
D130
Sym.
Min.
Typ†
Max.
Units
Conditions
Cell Endurance
100
1k
—
E/W
Temperature during programming:
10°C TA 40°C
VDD for Read
VMIN
—
—
V
Voltage on MCLR/VPP during
Erase/Program
8.0
—
9.0
V
Temperature during programming:
10°C TA 40°C
VDD for Bulk Erase
2.7
3
—
V
Temperature during programming:
10°C TA 40°C
VPEW
VDD for Write or Row Erase
2.7
—
—
V
VMIN = Minimum operating voltage
VMAX = Maximum operating
voltage
IPPPGM
Current on MCLR/VPP during
Erase/Write
—
—
5.0
mA
Temperature during programming:
10°C TA 40°C
IDDPGM Current on VDD during Erase/
Write
—
5.0
mA
Temperature during programming:
10°C TA 40°C
2.8
ms
Temperature during programming:
10°C TA 40°C
—
Year
EP
D131
D132
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
D133
TPEW
Erase/Write cycle time
—
D134
TRETD
Characteristic Retention
40
—
Provided no other specifications
are violated
VCAP Capacitor Charging
D135
Charging current
—
200
—
A
D135A
Source/sink capability when
charging complete
—
0.0
—
mA
Legend:
*
†
Note 1:
2:
3:
4:
TBD = To Be Determined
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
DS40001341F-page 208
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
23.5
Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No.
TH01
TH02
TH03
TH04
TH05
Sym.
Characteristic
JA
Thermal Resistance Junction to Ambient
JC
TJMAX
PD
Thermal Resistance Junction to Case
Maximum Junction Temperature
Power Dissipation
PINTERNAL Internal Power Dissipation
Typ.
Units
Conditions
60
C/W
28-pin SPDIP package
80
C/W
28-pin SOIC package
90
C/W
28-pin SSOP package
27.5
C/W
28-pin UQFN 4x4mm package
27.5
C/W
28-pin QFN 6x6mm package
47.2
C/W
40-pin PDIP package
46
C/W
44-pin TQFP package
24.4
C/W
44-pin QFN 8x8mm package
31.4
C/W
28-pin SPDIP package
24
C/W
28-pin SOIC package
24
C/W
28-pin SSOP package
24
C/W
28-pin UQFN 4x4mm package
28-pin QFN 6x6mm package
24
C/W
24.7
C/W
40-pin PDIP package
14.5
C/W
44-pin TQFP package
20
C/W
44-pin QFN 8x8mm package
150
C
—
W
PD = PINTERNAL + PI/O
—
W
PINTERNAL = IDD x VDD(1)
TH06
PI/O
I/O Power Dissipation
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07
PDER
Derated Power
—
W
PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
2007-2015 Microchip Technology Inc.
DS40001341F-page 209
PIC16(L)F722/3/4/6/7
23.6
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 23-2:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
DS40001341F-page 210
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
23.7
AC Characteristics: PIC16F72X-I/E
FIGURE 23-3:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
PIC16F722/3/4/6/7 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
FIGURE 23-4:
VDD (V)
5.5
3.6
2.5
2.3
2.0
1.8
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 23-1 for each Oscillator mode’s supported frequencies.
2007-2015 Microchip Technology Inc.
DS40001341F-page 211
PIC16(L)F722/3/4/6/7
PIC16LF722/3/4/6/7 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
VDD (V)
FIGURE 23-5:
3.6
2.5
2.3
2.0
1.8
0
4
16
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 23-1 for each Oscillator mode’s supported frequencies.
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
FIGURE 23-6:
125
+ 5%
Temperature (°C)
85
60
± 2%
25
0
-20
+ 5%
-40
1.8
2.0
2.5
3.0 3.3(2) 3.5
4.0
4.5
5.0
5.5
VDD (V)
Note 1: This chart covers both regulator enabled and regulator disabled states.
2: Regulator Nominal voltage
DS40001341F-page 212
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 23-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
No.
OS01
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
External CLKIN Period(1)
Oscillator Period(1)
OS03
TCY
Instruction Cycle Time(1)
OS04*
TosH,
TosL
External CLKIN High,
External CLKIN Low
TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
OS05*
Min.
Typ†
Max.
Units
Conditions
DC
—
37
kHz
DC
—
4
MHz
XT Oscillator mode
DC
—
20
MHz
HS Oscillator mode
DC
—
20
MHz
EC Oscillator mode
—
32.768
—
kHz
LP Oscillator mode
0.1
—
4
MHz
XT Oscillator mode
1
—
20
MHz
HS Oscillator mode
DC
—
4
MHz
RC Oscillator mode
27
—
s
LP Oscillator mode
250
—
ns
XT Oscillator mode
50
—
ns
HS Oscillator mode
50
—
ns
EC Oscillator mode
—
30.5
—
s
LP Oscillator mode
250
—
10,000
ns
XT Oscillator mode
LP Oscillator mode
50
—
1,000
ns
HS Oscillator mode
250
—
—
ns
RC Oscillator mode
200
TCY
DC
ns
TCY = 4/FOSC
2
—
—
s
LP oscillator
100
—
—
ns
XT oscillator
20
—
—
ns
HS oscillator
0
—
ns
LP oscillator
0
—
ns
XT oscillator
0
—
ns
HS oscillator
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2007-2015 Microchip Technology Inc.
DS40001341F-page 213
PIC16(L)F722/3/4/6/7
TABLE 23-2:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
No.
OS08
Sym.
Characteristic
HFOSC
Internal Calibrated HFINTOSC
Frequency(2)
OS08A MFOSC
Internal Calibrated MFINTOSC
Frequency(2)
OS10*
Freq.
Tolerance
Min.
Typ†
Max.
Units
2%
—
16.0
—
MHz
0°C TA +85°C,
VDD V
5%
—
16.0
—
MHz
-40°C TA +125°C
2%
—
500
—
kHz
0°C TA +85°C
VDD V
-40°C TA +125°C
5%
—
500
10
kHz
TIOSC ST HFINTOSC Wake-up from Sleep
Start-up Time
—
—
5
8
s
MFINTOSC Wake-up from Sleep
Start-up Time
—
—
20
30
s
Conditions
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
FIGURE 23-7:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS16
OS13
OS18
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
DS40001341F-page 214
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 23-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
OS11
TosH2ckL
Fosc to CLKOUT (1)
—
—
70
ns
VDD = 3.3-5.0V
OS12
TosH2ckH
Fosc to CLKOUT (1)
—
—
72
ns
VDD = 3.3-5.0V
(1)
OS13
TckL2ioV
CLKOUT to Port out valid
OS14
TioV2ckH
Port input valid before CLKOUT(1)
OS15
TosH2ioV
OS16
TosH2ioI
OS17
—
—
20
ns
TOSC + 200 ns
—
—
ns
Fosc (Q1 cycle) to Port out valid
—
50
70*
ns
VDD = 3.3-5.0V
Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
50
—
—
ns
VDD = 3.3-5.0V
TioV2osH
Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
20
—
—
ns
OS18
TioR
Port output rise time(2)
—
—
40
15
72
32
ns
VDD = 2.0V
VDD = 3.3-5.0V
OS19
TioF
Port output fall time(2)
—
—
28
15
55
30
ns
VDD = 2.0V
VDD = 3.3-5.0V
OS20*
Tinp
INT pin input high or low time
25
—
—
ns
OS21*
Trbp
PORTB interrupt-on-change new input level
time
TCY
—
—
ns
*
†
Note 1:
2:
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
Includes OSC2 in CLKOUT mode.
FIGURE 23-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
2007-2015 Microchip Technology Inc.
DS40001341F-page 215
PIC16(L)F722/3/4/6/7
FIGURE 23-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
DS40001341F-page 216
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 23-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
5
—
—
—
—
s
s
VDD = 3.3-5V, -40°C to +85°C
VDD = 3.3-5V
31
TWDTLP Low Power Watchdog Timer Timeout Period (No Prescaler)
10
18
27
ms
VDD = 3.3V-5V
32
TOST
Oscillator Start-up Timer Period(1), (2)
—
1024
—
Tosc (Note 3)
33*
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.0
s
35
VBOR
Brown-out Reset Voltage
2.38
1.80
2.5
1.9
2.73
2.11
V
36*
VHYST
Brown-out Reset Hysteresis
0
25
50
mV
-40°C to +85°C
37*
TBORDC Brown-out Reset DC Response
Time
1
3
5
10
s
VDD VBOR, -40°C to +85°C
VDD VBOR
*
†
Note 1:
2:
3:
4:
BORV=2.5V
BORV=1.9V
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
By design.
Period of the slower clock.
To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 23-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
2007-2015 Microchip Technology Inc.
DS40001341F-page 217
PIC16(L)F722/3/4/6/7
TABLE 23-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
40*
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
No Prescaler
TT0L
T0CKI Low Pulse Width
No Prescaler
Max.
Units
0.5 TCY + 20
—
—
ns
10
—
—
ns
With Prescaler
41*
Typ†
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
With Prescaler
42*
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler
Time
Synchronous, with Prescaler
0.5 TCY + 20
—
—
ns
15
—
—
ns
Asynchronous
30
—
—
ns
Synchronous, No Prescaler
0.5 TCY + 20
—
—
ns
Synchronous, with Prescaler
15
—
—
ns
Asynchronous
30
—
—
ns
Greater of:
30 or TCY + 40
N
—
—
ns
TT1L
46*
T1CKI Low
Time
47*
TT1P
T1CKI Input Synchronous
Period
48
FT1
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
Asynchronous
*
†
60
—
—
ns
32.4
32.768
33.1
kHz
2 TOSC
—
7 TOSC
—
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync mode
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 23-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCPx
(Capture mode)
CC01
CC02
CC03
Note:
Refer to Figure 23-2 for load conditions.
TABLE 23-6:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
Sym.
No.
CC01* TccL
CC02* TccH
CC03* TccP
*
†
Characteristic
CCPx Input Low Time
CCPx Input High Time
CCPx Input Period
Min.
Typ†
Max.
Units
No Prescaler
0.5TCY + 20
—
—
ns
With Prescaler
20
—
—
ns
No Prescaler
0.5TCY + 20
—
—
ns
With Prescaler
20
—
—
ns
3TCY + 40
N
—
—
ns
Conditions
N = prescale value (1, 4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS40001341F-page 218
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 23-7:
PIC16F722/3/4/6/7 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
AD01
NR
Resolution
—
—
8
AD02
EIL
Integral Error
—
—
±1.7
AD03
EDL
Differential Error
—
—
±1
AD04
EOFF Offset Error
—
—
±2.2
LSb VREF = 3.0V
AD05
EGN
LSb VREF = 3.0V
AD06
VREF Reference Voltage(3)
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
Gain Error
bit
LSb VREF = 3.0V
LSb No missing codes
VREF = 3.0V
—
—
±1.5
1.8
—
VDD
VSS
—
VREF
V
—
—
50
k
V
Can go higher if external 0.01F capacitor is
present on input pin.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
TABLE 23-8:
PIC16F722/3/4/6/7 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
No.
Sym.
AD130* TAD
AD131
TCNV
AD132* TACQ
Characteristic
Min.
Typ†
Max.
Units
Conditions
A/D Clock Period
1.0
—
9.0
s
TOSC-based
A/D Internal RC Oscillator
Period
1.0
2.0
6.0
s
ADCS = 11 (ADRC mode)
Conversion Time (not including
Acquisition Time)(1)
—
10.5
—
TAD
Set GO/DONE bit to conversion
complete
Acquisition Time
—
1.0
—
s
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
2007-2015 Microchip Technology Inc.
DS40001341F-page 219
PIC16(L)F722/3/4/6/7
FIGURE 23-12:
PIC16F722/3/4/6/7 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
7
A/D Data
6
5
4
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 23-13:
PIC16F722/3/4/6/7 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
7
A/D Data
6
5
4
OLD_DATA
ADRES
3
2
1
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS40001341F-page 220
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 23-14:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121
US121
DT
US122
US120
Note:
TABLE 23-9:
Refer to Figure 23-2 for load conditions.
USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
No.
Symbol
US120
TCKH2DTV
SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V
US121
TCKRF
Clock out rise time and fall time
(Master mode)
US122
TDTRF
Data-out rise time and fall time
FIGURE 23-15:
Characteristic
Min.
Max.
Units
—
80
ns
1.8-5.5V
—
100
ns
3.0-5.5V
—
45
ns
1.8-5.5V
—
50
ns
3.0-5.5V
—
45
ns
1.8-5.5V
—
50
ns
Conditions
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
US125
DT
US126
Note: Refer to Figure 23-2 for load conditions.
TABLE 23-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
No.
Symbol
Characteristic
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK (DT hold time)
US126 TCKL2DTL
Data-hold after CK (DT hold time)
2007-2015 Microchip Technology Inc.
Min.
Max.
Units
10
—
ns
15
—
ns
Conditions
DS40001341F-page 221
PIC16(L)F722/3/4/6/7
FIGURE 23-16:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP70
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 23-2 for load conditions.
FIGURE 23-17:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SDO
MSb
bit 6 - - - - - -1
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 23-2 for load conditions.
DS40001341F-page 222
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 23-18:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
MSb
SDO
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 23-2 for load conditions.
FIGURE 23-19:
SS
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SP83
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
SDO
MSb
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 23-2 for load conditions.
2007-2015 Microchip Technology Inc.
DS40001341F-page 223
PIC16(L)F722/3/4/6/7
TABLE 23-11: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min.
Typ†
Max.
Units
TCY
—
—
ns
—
—
ns
SP70*
TSSL2SCH,
TSSL2SCL
SS to SCK or SCK input
SP71*
TSCH
SCK input high time (Slave mode)
TCY + 20
SP72*
TSCL
SCK input low time (Slave mode)
TCY + 20
—
—
ns
SP73*
TDIV2SCH,
TDIV2SCL
Setup time of SDI data input to SCK edge
100
—
—
ns
SP74*
TSCH2DIL,
TSCL2DIL
Hold time of SDI data input to SCK edge
100
—
—
ns
SP75*
TDOR
SDO data output rise time
—
10
25
ns
—
25
50
ns
SP76*
TDOF
SDO data output fall time
—
10
25
ns
SP77*
TSSH2DOZ
SS to SDO output high-impedance
10
—
50
ns
SP78*
TSCR
SCK output rise time
(Master mode)
3.0-5.5V
—
10
25
ns
1.8-5.5V
—
25
50
ns
—
10
25
ns
—
—
50
ns
3.0-5.5V
1.8-5.5V
SP79*
TSCF
SCK output fall time (Master mode)
SP80*
TSCH2DOV,
TSCL2DOV
SDO data output valid after SCK
edge
SP81*
TDOV2SCH,
TDOV2SCL
SDO data output setup to SCK edge
SP82*
TSSL2DOV
SDO data output valid after SS edge
SP83*
TSCH2SSH,
TSCL2SSH
SS after SCK edge
*
†
3.0-5.5V
1.8-5.5V
—
—
145
ns
Tcy
—
—
ns
—
—
50
ns
1.5TCY + 40
—
—
ns
Conditions
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 23-20:
I2C BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Start
Condition
Stop
Condition
Note: Refer to Figure 23-2 for load conditions.
DS40001341F-page 224
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 23-12: I2C BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol
Characteristic
SP90*
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
SP93
THD:STO Stop condition
Start condition
Typ
4700
—
Max. Units
—
Setup time
400 kHz mode
600
—
—
Start condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
Stop condition
100 kHz mode
4700
—
—
Setup time
Hold time
*
100 kHz mode
Min.
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
400 kHz mode
600
—
—
Conditions
ns
Only relevant for Repeated
Start condition
ns
After this period, the first
clock pulse is generated
ns
ns
These parameters are characterized but not tested.
FIGURE 23-21:
I2C BUS DATA TIMING
SP103
SP100
SP102
SP101
SCL
SP90
SP106
SP107
SP92
SP91
SDA
In
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 23-2 for load conditions.
2007-2015 Microchip Technology Inc.
DS40001341F-page 225
PIC16(L)F722/3/4/6/7
TABLE 23-13: I2C BUS DATA REQUIREMENTS
Param.
No.
SP100*
Symbol
THIGH
Characteristic
Clock high time
Min.
Max.
Units
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1.5TCY
—
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
SSP Module
SP101*
TLOW
Clock low time
1.5TCY
—
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1CB
300
ns
—
250
ns
20 + 0.1CB
250
ns
SSP Module
SP102*
SP103*
TR
TF
SDA and SCL rise
time
SDA and SCL fall time 100 kHz mode
400 kHz mode
SP106*
THD:DAT
Data input hold time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
—
ns
SP107*
TSU:DAT
Data input setup time
100 kHz mode
250
400 kHz mode
100
—
ns
SP109*
TAA
Output valid from
clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
Bus free time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
—
400
pF
SP110*
SP111
*
Note 1:
2:
TBUF
CB
Bus capacitive loading
Conditions
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL
line is released.
DS40001341F-page 226
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
TABLE 23-14: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
No.
CS01
CS02
CS03
Symbol
ISRC
ISNK
VCHYST
Characteristic
Current Source
Current Sink
Cap Hysteresis
Min.
Typ†
Max.
Units
High
—
-5.8
-6
A
Medium
—
-1.1
-3.2
A
Low
—
-0.2
-0.9
A
High
—
6.6
6
A
Medium
—
1.3
3.2
A
Low
—
0.24
0.9
A
High
—
525
—
mV
Medium
—
375
—
mV
Low
—
280
—
mV
Conditions
-40, -85°C
-40, -85°C
VCTH-VCTL
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 23-22:
CAP SENSE OSCILLATOR
VCTH
VCTL
ISRC
Enabled
2007-2015 Microchip Technology Inc.
ISNK
Enabled
DS40001341F-page 227
PIC16(L)F722/3/4/6/7
24.0
DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
FIGURE 24-1:
PIC16F722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1 µF
2,200.00
5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
2,000.00
1,800.00
3.6V
3V
1,600.00
2.5V
IDD (µA)
1,400.00
1,200.00
1,000.00
1.8V
800.00
600.00
400.00
200.00
0.00
1 MHz
4 MHz
8 MHz
12 MHz
16 MHz
20 MHz
VDD (V)
FIGURE 24-2:
PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, EC MODE
2,400
2,200
2,000
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.6V
3.3V
1,800
3V
IDD (µA)
1,600
2.5V
1,400
1,200
2V
1,000
1.8V
800
600
400
200
0
1 MHz
4 MHz
8 MHz
12 MHz
16 MHz
20 MHz
FOSC
DS40001341F-page 228
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-3:
PIC16F722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1 µF
2,000
1,800
5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.6V
3V
1,600
1,400
2.5V
IDD (µA)
1,200
1,000
1.8V
800
600
400
200
0
1 MHz
4 MHz
8 MHz
12 MHz
16 MHz
20 MHz
FOSC
FIGURE 24-4:
PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, EC MODE
2,200
2,000
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.6V
1,800
3.3V
3V
1,600
IDD (µA)
1,400
2.5V
1,200
2V
1,000
1.8V
800
600
400
200
0
1 MHz
4 MHz
8 MHz
12 MHz
16 MHz
20 MHz
FOSC
2007-2015 Microchip Technology Inc.
DS40001341F-page 229
PIC16(L)F722/3/4/6/7
FIGURE 24-5:
PIC16F722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE,
VCAP = 0.1 µF
600
500
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
4 MHz
IDD (µA)
400
300
1 MHz
200
100
0
1.8
2
2.5
3
3.3
3.6
4.2
4.5
5
VDD (V)
FIGURE 24-6:
PIC16LF722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE
500
450
4 MHz
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
400
350
IDD (µA)
300
250
200
150
1 MHz
100
50
0
1.8
2
2.5
3
3.3
3.6
VDD (V)
DS40001341F-page 230
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-7:
PIC16F722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE,
VCAP = 0.1 µF
450
400
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
4 MHz
350
IDD (µA)
300
250
200
150
1 MHz
100
50
0
1.8
2
2.5
3
3.3
3.6
4.2
4.5
5
VDD (V)
PIC16LF722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE
FIGURE 24-8:
450
400
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
4 MHz
350
IDD (µA)
300
250
200
150
1 MHz
100
50
0
1.8
2
2.5
3
3.3
3.6
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 231
PIC16(L)F722/3/4/6/7
FIGURE 24-9:
PIC16F722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1 µF
2.4
2.2
2
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
5V
4.5V
3.6V
1.8
3V
1.6
IDD (mA)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
4 MHz
6 MHz
8 MHz
10 MHz
13 MHz
16 MHz
20 MHz
Fosc
FIGURE 24-10:
PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE
2.50
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.6V
2.00
3.3V
3V
1.50
IDD (mA)
2.5V
1.00
0.50
0.00
4 MHz
6 MHz
8 MHz
10 MHz
13 MHz
16 MHz
20 MHz
Fosc
DS40001341F-page 232
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-11:
2.00
PIC16F722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1 µF
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
5V
4.5V
3.6V
3V
IDD (mA)
1.50
1.00
0.50
0.00
4 MHz
6 MHz
8 MHz
10 MHz
13 MHz
16 MHz
20 MHz
Fosc
FIGURE 24-12:
PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, HS MODE
2.50
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
2.00
3.6V
3.3V
3V
IDD (mA)
1.50
2.5V
1.00
0.50
0.00
4 MHz
6 MHz
8 MHz
10 MHz
13 MHz
16 MHz
20 MHz
Fosc
2007-2015 Microchip Technology Inc.
DS40001341F-page 233
PIC16(L)F722/3/4/6/7
FIGURE 24-13:
PIC16F722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1 µF
600
500
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
4 MHz
IDD (µA)
400
300
1 MHz
200
100
0
1.8
2
2.5
3
3.3
3.6
4.2
4.5
5
VDD (V)
FIGURE 24-14:
PIC16LF722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE
600
500
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
4 MHz
IDD (µA)
400
300
1 MHz
200
100
0
1.8
2
2.5
3
3.3
3.6
VDD (V)
DS40001341F-page 234
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-15:
PIC16F722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1 µF
600
500
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
4 MHz
IDD (µA)
400
300
1 MHz
200
100
0
1.8
2
2.5
3
3.3
3.6
4.2
4.5
5
VDD (V)
FIGURE 24-16:
PIC16LF722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, XT MODE
600
500
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
4 MHz
IDD (µA)
400
300
1 MHz
200
100
0
1.8
2
2.5
3
3.3
3.6
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 235
PIC16(L)F722/3/4/6/7
FIGURE 24-17:
PIC16F722/3/4/6/7 IDD vs. VDD, LP MODE, VCAP = 0.1 µF
20.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
17.5
IDD (µA)
32 kHz Maximum
15.0
VDD (V)
32 kHz Typical
12.5
10.0
1.8
3
5
VDD (V)
FIGURE 24-18:
PIC16LF722/3/4/6/7 IDD vs. VDD, LP MODE
30
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
25
32 kHz Maximum
IDD (µA)
20
15
32 kHz Typical
10
5
1.8
3
3.3
3.6
VDD (V)
DS40001341F-page 236
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-19:
PIC16F722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE,
VCAP = 0.1 µF
210
200
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
5V
190
180
3.6V
IDD (µA)
170
2.5V
160
150
1.8V
140
130
120
110
62.5 kHz
125 kHz
250 kHz
500 kHz
FOSC
FIGURE 24-20:
PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE
170
160
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.6V
IDD (µA)
150
3V
2.5V
140
130
1.8V
120
110
100
62.5 KHz
125 KHz
250 KHz
500 KHz
FOSC
2007-2015 Microchip Technology Inc.
DS40001341F-page 237
PIC16(L)F722/3/4/6/7
FIGURE 24-21:
PIC16F722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP =1µF
2,000
1,800
5V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.6V
1,600
2.5V
1,400
IDD (µA)
1,200
1.8V
1,000
800
600
400
200
0
2 MHz
4 MHz
8 MHz
16 MHz
FOSC
FIGURE 24-22:
PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE
2,250
2,000
s
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.6V
1,750
3V
1,500
IDD (µA)
2.5V
1,250
1.8V
1,000
750
500
250
0
2 MHz
4 MHz
8 MHz
16 MHz
FOSC
DS40001341F-page 238
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-23:
PIC16F722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP =0.1µF
160
150
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
5V
IDD (µA)
140
3.6V
130
2.5V
120
1.8V
110
100
90
80
62.5 kHz
125 kHz
250 kHz
500 kHz
FOSC
FIGURE 24-24:
PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
140
130
3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3V
120
2.5V
IDD (µA)
110
100
1.8V
90
80
70
62.5 kHz
125 kHz
250 kHz
500 kHz
FOSC
2007-2015 Microchip Technology Inc.
DS40001341F-page 239
PIC16(L)F722/3/4/6/7
FIGURE 24-25:
PIC16F722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE,
VCAP = 0.1 µF
2,000
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1,800
1,600
5V
3.6V
1,400
2.5V
IDD (µA)
1,200
1,000
1.8V
800
600
400
200
0
2 MHz
4 MHz
8 MHz
16 MHz
FOSC
FIGURE 24-26:
PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE
2,000
1,800
3.6V
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1,600
3V
1,400
IDD (µA)
2.5V
1,200
1,000
1.8V
800
600
400
200
0
2 MHz
4 MHz
8 MHz
16 MHz
VDD (V)
DS40001341F-page 240
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-27:
PIC16F722/3/4/6/7 MAXIMUM BASE IPD vs. VDD, VCAP = 0.1 µF
25
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
20
125°C
IPD (µA)
15
85°C
10
5
0
1.8V
2V
3V
3.6V
4V
5V
5.5V
VDD (V)
FIGURE 24-28:
PIC16LF722/3/4/6/7 MAXIMUM BASE IPD vs. VDD
7
6
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
125°C
IPD (µA)
5
4
3
2
85°C
1
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 241
PIC16(L)F722/3/4/6/7
FIGURE 24-29:
PIC16F722/3/4/6/7 TYPICAL BASE IPD vs. VDD, VCAP = 0.1 µF
8
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
7
6
IPD (µA)
25°C
5
4
3
2
1.8V
2V
3V
3.6V
4V
5V
5.5V
VDD (V)
FIGURE 24-30:
PIC16LF722/3/4/6/7 TYPICAL BASE IPD vs. VDD
250
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
200
25°C
IPD (nA)
150
100
50
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
DS40001341F-page 242
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-31:
PIC16F722/3/4/6/7 FIXED VOLTAGE REFERENCE IPD vs. VDD, VCAP = 0.1 µF
70
60
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
50
Max. 85°C
IPD (µA)
40
30
Typ. 25°C
20
10
0
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
PIC16LF722/3/4/6/7 FIXED VOLTAGE REFERENCE IPD vs. VDD
FIGURE 24-32:
25
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
20
15
IPD (µA)
Max. 85°C
10
Typ. 25°C
5
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 243
PIC16(L)F722/3/4/6/7
FIGURE 24-33:
PIC16F722/3/4/6/7 BOR IPD vs. VDD, VCAP = 0.1 µF
70
60
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
50
IPD (µA)
40
Max. 85°C
30
Typ. 25°C
20
10
0
2V
3V
3.6V
5V
5.5V
VDD (V)
FIGURE 24-34:
PIC16LF722/3/4/6/7 BOR IPD vs. VDD
30
25
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
IPD (µA)
20
15
Max. 85°C
10
Typ. 25°C
5
0
2V
2.5V
3V
3.6V
VDD (V)
DS40001341F-page 244
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-35:
PIC16F722/3/4/6/7 CAP SENSE HIGH POWER IPD vs. VDD, VCAP = 0.1 µF
70
60
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
Max. 85°C
50
Typ. 25°C
IPD (µA)
40
30
20
10
0
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
PIC16LF722/3/4/6/7 CAP SENSE HIGH POWER IPD vs. VDD
FIGURE 24-36:
60
50
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
Max. 85°C
40
IPD (µA)
Typ. 25°C
30
20
10
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 245
PIC16(L)F722/3/4/6/7
FIGURE 24-37:
PIC16F722/3/4/6/7 CAP SENSE MEDIUM POWER IPD vs. VDD, VCAP = 0.1 µF
30
25
Max. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
20
IPD (µA)
Max. 85°C
15
Typ. 25°C
10
5
0
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
FIGURE 24-38:
PIC16LF722/3/4/6/7 CAP SENSE MEDIUM POWER IPD vs. VDD
20
18
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
16
14
IPD (µA)
12
10
8
Max. 85°C
6
Typ. 25°C
4
2
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
DS40001341F-page 246
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-39:
PIC16F722/3/4/6/7 CAP SENSE LOW POWER IPD vs. VDD, VCAP = 0.1 µF
30
25
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
IPD (µA)
20
Max. 85°C
15
10
Typ. 25°C
5
0
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
FIGURE 24-40:
PIC16LF722/3/4/6/7 CAP SENSE LOW POWER IPD vs. VDD
18
16
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
14
12
IPD (µA)
10
8
6
Max. 85°C
4
Typ. 25°C
2
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 247
PIC16(L)F722/3/4/6/7
FIGURE 24-41:
PIC16F722/3/4/6/7 T1OSC 32 KHZ IPD vs. VDD, VCAP = 0.1 µF
16
14
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 85°C
12
IPD (µA)
10
Typ. 25° C
8
6
4
2
0
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
PIC16LF722/3/4/6/7 T1OSC 32 kHz IPD vs. VDD
FIGURE 24-42:
4.0
3.5
Max. 85°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.0
2.5
IPD (µA)
Typ.
2.0
1.5
1.0
0.5
0.0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
DS40001341F-page 248
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-43:
PIC16F722/3/4/6/7 TYPICAL ADC IPD vs. VDD, VCAP = 0.1 µF
7.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Typ. 25°C
7.0
IPD (µA)
6.5
6.0
5.5
5.0
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
FIGURE 24-44:
PIC16LF722/3/4/6/7 TYPICAL ADC IPD vs. VDD
250
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Typ. 25°C
200
IPD (nA)
150
100
50
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 249
PIC16(L)F722/3/4/6/7
FIGURE 24-45:
PIC16F722/3/4/6/7 ADC IPD vs. VDD, VCAP = 0.1 µF
25
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
IPD (µA)
20
15
Max. 85°C
10
5
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
FIGURE 24-46:
PIC16LF722/3/4/6/7 ADC IPD vs. VDD
8
7
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
6
IPD (µA)
5
4
3
2
Max. 85°C
1
0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
DS40001341F-page 250
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-47:
PIC16F722/3/4/6/7 WDT IPD vs. VDD, VCAP = 0.1 µF
18
16
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 85°C
14
12
IPD (µA)
10
Typ. 25°C
8
6
4
2
0
1.8V
2V
3V
3.6V
5V
5.5V
VDD (V)
FIGURE 24-48:
PIC16LF722/3/4/6/7 WDT IPD vs. VDD
3.5
3.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. 85°C
2.5
IPD (µA)
2.0
1.5
Typ. 25°C
1.0
0.5
0.0
1.8V
2V
2.5V
3V
3.6V
VDD (V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 251
PIC16(L)F722/3/4/6/7
FIGURE 24-49:
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
1.8
1.6
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
1.4
Max. -40°
VIN (V)
1.2
Typ. 25°
1
Min. 125°
0.8
0.6
0.4
1.8
3.6
5.5
VDD (V)
FIGURE 24-50:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
3.5
3.0
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
VIHMax. -40°C
2.5
VIN (V)
2.0
1.5
VIHMin. 125°C
1.0
0.5
0.0
1.8
3.6
5.5
VDD (V)
DS40001341F-page 252
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-51:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
3.0
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
2.5
VIL Max. -40°C
VIN (V)
2.0
1.5
1.0
VIL Min. 125°C
0.5
0.0
1.8
3.6
5.5
VDD (V)
FIGURE 24-52:
VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V
5.6
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
5.5
VOH (V)
5.4
5.3
Max. -40°
Typ. 25°
5.2
Min. 125°
5.1
5
-0.2
-1.0
-1.8
-2.6
-3.4
-4.2
-5.0
IOH (mA)
2007-2015 Microchip Technology Inc.
DS40001341F-page 253
PIC16(L)F722/3/4/6/7
FIGURE 24-53:
VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V
3.8
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
3.6
3.4
VOH (V)
Max. -40°
3.2
Typ. 25°
3
Min. 125°
2.8
2.6
-0.2
-1.0
-1.8
-2.6
-3.4
-4.2
-5.0
IOH (mA)
VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V
FIGURE 24-54:
2
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
1.8
1.6
Max. -40°
1.4
VOH (V)
1.2
Typ. 25°
1
0.8
0.6
Min. 125°
0.4
0.2
0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
IOH (mA)
DS40001341F-page 254
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-55:
VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V
0.5
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
0.45
0.4
0.35
Max. 125°
VOL (V)
0.3
0.25
0.2
Typ. 25°
0.15
0.1
Min. -40°
0.05
0
5.0
6.0
7.0
8.0
9.0
10.0
IOL (mA)
FIGURE 24-56:
VOL vs. IOL OVER TEMPERATURE, VDD = 3.6V
0.9
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
0.8
0.7
0.6
Max. 125°
VOL (V)
0.5
0.4
Typ. 25°
0.3
0.2
Min. -40°
0.1
0
4.0
5.0
2007-2015 Microchip Technology Inc.
6.0
7.0
IOL (mA)
8.0
9.0
10.0
DS40001341F-page 255
PIC16(L)F722/3/4/6/7
FIGURE 24-57:
VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V
1.2
1
Maximum: Mean + 3 (-40°C to 125°C)
Typical: Mean @25°C
Minimum: Mean - 3 (-40°C to 125°C)
0.8
VOL (V)
Max. 125°
0.6
0.4
0.2
Min. -40°
0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
IOL (mA)
FIGURE 24-58:
PIC16F722/3/4/6/7 PWRT PERIOD
105
95
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. -40°C
TIME (ms)
85
75
Typ. 25°C
65
Min. 125°C
55
45
1.8V
2V
2.2V
2.4V
3V
3.6V
4V
4.5V
5V
5.5V
VDD
DS40001341F-page 256
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-59:
PIC16F722/3/4/6/7 WDT TIME-OUT PERIOD
24.00
22.00
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Max. -40°C
20.00
TIME (ms)
18.00
Typ. 25°C
16.00
14.00
Min. 125°C
12.00
10.00
1.8V
2V
2.2V
2.4V
3V
3.6V
4V
4.5V
5V
VDD
FIGURE 24-60:
PIC16F722/3/4/6/7 HFINTOSC WAKE-UP FROM SLEEP START-UP TIME
6.0
5.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
5.0
4.5
Max.
TIME (us)
4.0
3.5
3.0
Typ.
2.5
2.0
1.5
1.0
1.8V
2V
3V
3.6V
4V
4.5V
5V
5.5V
VDD
2007-2015 Microchip Technology Inc.
DS40001341F-page 257
PIC16(L)F722/3/4/6/7
FIGURE 24-61:
PIC16F722/3/4/6/7 A/D INTERNAL RC OSCILLATOR PERIOD
6.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
5.0
Period (µs)
4.0
3.0
Max.
Min.
2.0
1.0
0.0
1.8V
3.6V
5.5V
VDD(V)
FIGURE 24-62:
PIC16F722/3/4/6/7 CAP SENSE OUTPUT CURRENT, POWER MODE = HIGH
20000
Min. Sink -40°C
15000
Typ. Sink 25°C
Current (nA)
10000
Max. Sink 85°C
5000
0
Min. Source 85°C
-5000
Typ. Source 25°C
-10000
Max. Source -40°C
-15000
1.8
2
2.5
3
3.2
3.6
4
4.5
5
5.5
VDD(V)
DS40001341F-page 258
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-63:
PIC16F722/3/4/6/7 CAP SENSE OUTPUT CURRENT, POWER MODE = MEDIUM
3000
Max. Sink -40°C
2000
Typ. Sink 25°C
1000
Current (nA)
Min. Sink 85°C
0
Min. Source 85°C
-1000
Typ. Source 25°C
-2000
Max. Source -40°C
-3000
1.8
2
2.5
3
3.2
3.6
4
4.5
5
5.5
VDD(V)
FIGURE 24-64:
PIC16F722/3/4/6/7 CAP SENSE OUTPUT CURRENT, POWER MODE = LOW
600
Max. Sink 85°C
400
Typ. Sink 25°C
200
Min. Sink -40°C
Current (nA)
0
Min. Source 85°C
-200
Typ. Source 25°C
-400
-600
Max. Source -40°C
-800
1.8
2
2.5
3
3.2
3.6
4
4.5
5
5.5
VDD(V)
2007-2015 Microchip Technology Inc.
DS40001341F-page 259
PIC16(L)F722/3/4/6/7
FIGURE 24-65:
PIC16F722/3/4/6/7 CAP SENSOR HYSTERESIS, POWER MODE = HIGH
700
Max. 125°C
Max. 85°C
600
mV
Typ. 25°C
500
Min. 0°C
Min. -40°C
400
300
1.8
2.0
2.5
3.0
3.2
3.6
4.0
4.5
5.0
5.5
VDD(V)
FIGURE 24-66:
PIC16F722/3/4/6/7 CAP SENSOR HYSTERESIS, POWER MODE = MEDIUM
550
500
Max. 125°C
mV
450
Max. 85°C
400
Typ. 25°C
350
Min. 0°C
300
Min. -40°C
250
1.8
2.0
2.5
3.0
3.2
3.6
4.0
4.5
5.0
5.5
VDD(V)
DS40001341F-page 260
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
FIGURE 24-67:
PIC16F722/3/4/6/7 CAP SENSOR HYSTERESIS, POWER MODE = LOW
450
Max. 125°C
400
Max. 85°C
mV
350
300
Typ. 25°C
250
Min. 0°C
200
Min -40°C
150
1.8
2.0
2.5
3.0
3.2
3.6
4.0
4.5
5.0
5.5
VDD(V)
FIGURE 24-68:
TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V
1.5
Percent Change (%)
1
0.5
0
-0.5
-1
-1.5
1.8
2.5
3
3.6
4.2
5.5
Voltage
2007-2015 Microchip Technology Inc.
DS40001341F-page 261
PIC16(L)F722/3/4/6/7
FIGURE 24-69:
TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C
1.5
1
Percent Change (%)
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-40
0
45
85
125
Temperature (°C)
DS40001341F-page 262
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
25.0
PACKAGING INFORMATION
25.1
Package Marking Information
28-Lead SPDIP
Example
PIC16F722
-I/SP e3
0810017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Example
28-Lead QFN/UQFN
16F722
-I/ML e3
0810017
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
PIC16F724
-I/P e3
0810017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC® designator (e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2007-2015 Microchip Technology Inc.
DS40001341F-page 263
PIC16(L)F722/3/4/6/7
Package Marking Information (Continued)
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
DS40001341F-page 264
Example
PIC16F724
-I/ML e3
0810017
Example
PIC16F722
-I/SO e3
0810017
Example
PIC16F722
-I/SS e3
0810017
Example
PIC16F727
-I/PT e3
0810017
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
25.2
Package Details
The following sections give the technical details of the packages.
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DS40001341F-page 268
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
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DS40001341F-page 274
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2007-2015 Microchip Technology Inc.
DS40001341F-page 275
PIC16(L)F722/3/4/6/7
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001341F-page 276
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (12/2007)
Original release.
APPENDIX B:
MIGRATING FROM
OTHER PIC®
DEVICES
This discusses some of the issues in migrating from
other PIC® devices to the PIC16F72X family of
devices.
Revision B (08/2008)
Electrical Specification updates; Package Drawings;
miscellaneous updates.
Revision C (04/2009)
B.1
PIC16F77 to PIC16F72X
TABLE B-1:
FEATURE COMPARISON
Feature
PIC16F77
PIC16F727
Max. Operating Speed
20 MHz
20 MHz
8K
8K
Revised data sheet title; Revised Low-Power Features
section; Revised Section 6.2.2.4 RA3/AN3/VREF;
Revised Figure 16-8 Synchronous Reception.
Max. Program
Memory (Words)
Max. SRAM (Bytes)
368
368
Revision D (07/2009)
A/D Resolution
8-bit
8-bit
Timers (8/16-bit)
2/1
2/1
Oscillator Modes
4
8
Removed the Preliminary Label; Updated the
“Electrical Characteristics” section; Added charts in the
“Char. Data” section; Deleted “Based 8-Bit CMOS”
from title; Updated the “Special Microcontroller
Features” section and the “Peripheral Features”
section; Changed the title of the “Low Power Features”
section into “Extreme Low-Power Management
PIC16LF72X with nanoWatt XLP” and updated this
section; Inserted new section – “Analog Features”
(page 1); Changed the title of the “Peripheral Features”
section into “Peripheral Highlights” and updated the
section.
Brown-out Reset
Y
Y
Internal Pull-ups
RB
RB
Interrupt-on-change
RB
RB
0
0
Comparator
USART
Y
Y
Extended WDT
N
N
Software Control
Option of WDT/BOR
N
N
INTOSC Frequencies
None
500 kHz 16 MHz
N
N
Revision E (10/2009)
Added paragraph to section 5.0 (LDO Voltage
Regulator); Updated the Electrical Specifications
section (Added another absolute Maximum Rating;
Updated section 23.1 and Table 23-4); Updated the Pin
Diagrams with the UQFN package; Updated Table 1,
adding UQFN; Updated section 23.5 (Thermal
Considerations); Updated the Packaging Information
section adding the UQFN Package; Updated the
Product Identification System section.
Clock Switching
Revision F (12/2015)
Updated Table 2; Updated 23.1, 23.3 and 9.2.4
Sections; Updated Figure 23-9; Other minor
corrections.
2007-2015 Microchip Technology Inc.
DS40001341F-page 277
PIC16(L)F722/3/4/6/7
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the website
at: http://www.microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration
instructions.
DS40001341F-page 278
2007-2015 Microchip Technology Inc.
PIC16(L)F722/3/4/6/7
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
X
/XX
XXX
Tape and Reel
Option
Temperature
Range
Package
Pattern
PART NO.
Device
Examples:
a)
b)
Device:
PIC16F722, PIC16LF722, PIC16F722T, PIC16LF722T(1)
PIC16F723, PIC16LF723, PIC16F723T, PIC16LF723T(1)
PIC16F724, PIC16LF724, PIC16F724T, PIC16LF724T(1)
PIC16F726, PIC16LF726, PIC16F726T, PIC16LF726T(1)
PIC16F727, PIC16LF727, PIC16F727T, PIC16LF727T(1)
Tape and Reel
Option:
I
E
MV
Temperature
Range:
I
E
Package:
ML
P
PT
SO
SP
SS
=
=
=
-40C to +85C
-40C to +125C
Micro Lead Frame (UQFN)
= -40C to +85C
= -40C to +125C
=
=
=
=
=
=
PIC16F722-E/SP 301 = Extended Temp.,
skinny PDIP package, QTP pattern #301
PIC16F722-I/SO = Industrial Temp., SOIC
package
(Industrial)
(Extended)
Micro Lead Frame (QFN)
Plastic DIP
TQFP (Thin Quad Flatpack)
SOIC
Skinny Plastic DIP
SSOP
2007-2015 Microchip Technology Inc.
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
DS40001341F-page 279
PIC16(L)F722/3/4/6/7
NOTES:
DS40001341F-page 280
2007-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0042-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2007-2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS40001341F-page 281
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
07/14/15
DS40001341F-page 282
2007-2015 Microchip Technology Inc.
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