PIC16F870/871
28/40-Pin, 8-Bit CMOS FLASH Microcontrollers
• PIC16F870
• PIC16F871
Microcontroller Core Features:
• High performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of FLASH Program Memory
128 x 8 bytes of Data Memory (RAM)
64 x 8 bytes of EEPROM Data Memory
• Pinout compatible to the PIC16CXXX 28 and
40-pin devices
• Interrupt capability (up to 11 sources)
• Eight level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low power, high speed CMOS FLASH/EEPROM
technology
• Fully static design
• In-Circuit Serial Programming(ICSP)via
two pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low power consumption:
- < 1.6 mA typical @ 5V, 4 MHz
- 20 A typical @ 3V, 32 kHz
- < 1 A typical standby current
2000-2013 Microchip Technology Inc.
Pin Diagram
PDIP
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16F871
Devices Included in this Data Sheet:
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5
RC4
RD3/PSP3
RD2/PSP2
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• One Capture, Compare, PWM module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
DS30569C-page 1
PIC16F870/871
Pin Diagrams
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5
RC4
6
5
4
3
2
1
44
43
42
41
40
PLCC
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
MCLR/VPP/THV
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
PIC16F870
DIP, SOIC, SSOP
18
19
20
21
22
23
24
25
26
27
282
PIC16F871
39
38
37
36
35
34
33
32
31
30
9
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
44
43
42
41
40
39
38
37
36
35
34
TQFP
7
8
9
10
11
12
13
14
15
16
17
RC1/T1OSI
RC2/CCP1
RC3
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4
RC5
RC6/TX/CK
NC
RC6/TX/CK
RC5
RC4
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3
RC2/CCP1
RC1/T1OSI
NC
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CK1
NC
PIC16F871
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4
RA4/T0CKI
NC
NC
RB4
RB5
RB6/PGC
RB7/PGD
MCLR/VPP/THV
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
DS30569C-page 2
2000-2013 Microchip Technology Inc.
PIC16F870/871
Key Features
PICmicroTM Mid-Range MCU Family Reference Manual
(DS33023)
PIC16F870
PIC16F871
Operating Frequency
DC - 20 MHz
DC - 20 MHz
RESETS (and Delays)
POR, BOR (PWRT, OST)
POR, BOR (PWRT, OST)
FLASH Program Memory (14-bit words)
2K
2K
Data Memory (bytes)
128
128
EEPROM Data Memory
64
64
Interrupts
10
11
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
3
3
Timers
Capture/Compare/PWM modules
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Instruction Set
2000-2013 Microchip Technology Inc.
1
1
USART
USART
—
PSP
5 input channels
8 input channels
35 Instructions
35 Instructions
DS30569C-page 3
PIC16F870/871
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization ................................................................................................................................................................. 11
3.0 Data EEPROM and Flash Program Memory.............................................................................................................................. 27
4.0 I/O Ports ..................................................................................................................................................................................... 33
5.0 Timer0 Module ........................................................................................................................................................................... 45
6.0 Timer1 Module ........................................................................................................................................................................... 49
7.0 Timer2 Module ........................................................................................................................................................................... 53
8.0 Capture/Compare/PWM Modules .............................................................................................................................................. 55
9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................ 61
10.0 Analog-to-Digital (A/D) Converter Module .................................................................................................................................. 79
11.0 Special Features of the CPU ...................................................................................................................................................... 87
12.0 Instruction Set Summary .......................................................................................................................................................... 103
13.0 Development Support............................................................................................................................................................... 111
14.0 Electrical Characteristics .......................................................................................................................................................... 117
15.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 137
16.0 Packaging Information.............................................................................................................................................................. 149
Appendix A: Revision History............................................................................................................................................................. 157
Appendix B: Device Differences......................................................................................................................................................... 157
Appendix C: Conversion Considerations ........................................................................................................................................... 158
Appendix D: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 158
Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 159
Index .................................................................................................................................................................................................. 161
On-Line Support................................................................................................................................................................................. 167
Systems Information and Upgrade Hot Line ...................................................................................................................................... 167
Reader Response .............................................................................................................................................................................. 168
PIC16F870/871 Product Identification System .................................................................................................................................. 169
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS30569C-page 4
2000-2013 Microchip Technology Inc.
PIC16F870/871
1.0
DEVICE OVERVIEW
There are two devices (PIC16F870 and PIC16F871)
covered by this data sheet. The PIC16F870 device
comes in a 28-pin package and the PIC16F871 device
comes in a 40-pin package. The 28-pin device does not
have a Parallel Slave Port implemented.
This document contains device specific information.
Additional information may be found in the PICmicroTM
Mid-Range
MCU
Family
Reference Manual
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this data
sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
FIGURE 1-1:
The following two figures are device block diagrams
sorted by pin number: 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.
PIC16F870 BLOCK DIAGRAM
Device
Program FLASH
Data Memory
Data EEPROM
PIC16F870
2K
128 Bytes
64 Bytes
13
FLASH
Program
Memory
14
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
RAM
File
Registers
8 Level Stack
(13-bit)
Program
Bus
8
Data Bus
Program Counter
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
MUX
ALU
PORTC
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
RC5
RC6/TX/CK
RC7/RX/DT
8
W reg
Low-Voltage
Programming
MCLR
Timer0
Timer1
Data EEPROM
CCP1
Note 1:
VDD, VSS
Timer2
10-bit A/D
USART
Higher order bits are from the STATUS register.
2000-2013 Microchip Technology Inc.
DS30569C-page 5
PIC16F870/871
FIGURE 1-2:
PIC16F871 BLOCK DIAGRAM
Device
Program FLASH
Data Memory
Data EEPROM
PIC16F871
2K
128 Bytes
64 Bytes
13
Program
Memory
14
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4
RAM
File
Registers
8 Level Stack
(13-bit)
Program
Bus
8
Data Bus
Program Counter
FLASH
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
Oscillator
Start-up Timer
Power-on
Reset
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
RC5
RC6/TX/CK
RC7/RX/DT
MUX
ALU
8
Watchdog
Timer
Brown-out
Reset
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
PORTD
W reg
RD7/PSP7:RD0/PSP0
In-Circuit
Debugger
Low-Voltage
Programming
PORTE
RE0/RD/AN5
RE1/WR/AN6
MCLR
Timer0
Timer1
Data EEPROM
CCP1
Note 1:
VDD, VSS
Timer2
Parallel Slave Port
RE2/CS/AN7
10-bit A/D
USART
Higher order bits are from the STATUS register.
DS30569C-page 6
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 1-1:
PIC16F870 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
OSC1/CLKI
9
9
I
OSC2/CLKO
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. In RC mode, the OSC2 pin outputs
CLKO, which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP/THV
1
1
I/P
ST
Master Clear (Reset) input or programming voltage input or High
Voltage Test mode control. This pin is an active low RESET to the
device.
Pin Name
Buffer
Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA0/AN0
2
2
I/O
TTL
RA0 can also be analog input 0.
RA1/AN1
3
3
I/O
TTL
RA1 can also be analog input 1.
RA2/AN2/VREF-
4
4
I/O
TTL
RA2 can also be analog input 2 or negative analog reference
voltage.
RA3/AN3/VREF+
5
5
I/O
TTL
RA3 can also be analog input 3 or positive analog reference
voltage.
RA4/T0CKI
6
6
I/O
ST/OD
RA4 can also be the clock input to the Timer0 module. Output
is open drain type.
RA5/AN4
7
7
I/O
TTL
RA5 can also be analog input 4.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
21
21
I/O
TTL/ST(1)
RB1
22
22
I/O
TTL
RB2
23
23
I/O
TTL
RB3/PGM
24
24
I/O
TTL/ST(1)
RB4
25
25
I/O
TTL
RB5
26
26
I/O
TTL
RB6/PGC
27
27
I/O
TTL/ST(2)
Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming clock.
RB7/PGD
28
28
I/O
TTL/ST(2)
Interrupt-on-change pin or In-Circuit Debugger pin. Serial
programming data.
RC0/T1OSO/T1CKI
11
11
I/O
ST
RC0 can also be the Timer1 oscillator output or Timer1 clock
input.
RC1/T1OSI
12
12
I/O
ST
RC1 can also be the Timer1 oscillator input.
RC2/CCP1
13
13
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3
14
14
I/O
ST
RC4
15
15
I/O
ST
RC5
16
16
I/O
ST
RC6/TX/CK
17
17
I/O
ST
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
8, 19
P
—
Ground reference for logic and I/O pins.
VDD
20
20
P
—
Positive supply for logic and I/O pins.
RB0 can also be the external interrupt pin.
RB3 can also be the low voltage programming input.
Interrupt-on-change pin.
Interrupt-on-change pin.
PORTC is a bi-directional I/O port.
Legend:
Note 1:
2:
3:
I = input
O = output
I/O = input/output
P = power
OD = Open Drain
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2000-2013 Microchip Technology Inc.
DS30569C-page 7
PIC16F870/871
TABLE 1-2:
PIC16F871 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
OSC1/CLKI
13
14
30
I
ST/CMOS(4)
OSC2/CLKO
14
15
31
O
—
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP/THV
1
2
18
I/P
ST
Master Clear (Reset) input or programming voltage input or
High Voltage Test mode control. This pin is an active low
RESET to the device.
RA0/AN0
2
3
19
I/O
TTL
RA0 can also be analog input 0.
RA1/AN1
3
4
20
I/O
TTL
RA1 can also be analog input 1.
RA2/AN2/VREF-
4
5
21
I/O
TTL
RA2 can also be analog input 2 or negative analog
reference voltage.
RA3/AN3/VREF+
5
6
22
I/O
TTL
RA3 can also be analog input 3 or positive analog
reference voltage.
RA4/T0CKI
6
7
23
I/O
ST
RA4 can also be the clock input to the Timer0
timer/counter. Output is open drain type.
RA5/AN4
7
8
24
I/O
TTL
Pin Name
Description
Oscillator crystal input/external clock source input.
PORTA is a bi-directional I/O port.
RA5 can also be analog input 4.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
33
36
8
I/O
TTL/ST(1)
RB1
34
37
9
I/O
TTL
RB2
35
38
10
I/O
TTL
RB3/PGM
36
39
11
I/O
TTL/ST(1)
RB4
37
41
14
I/O
TTL
RB5
38
42
15
I/O
TTL
RB6/PGC
39
43
16
I/O
TTL/ST
(2)
Interrupt-on-change pin or In-Circuit Debugger pin.
Serial programming clock.
RB7/PGD
40
44
17
I/O
TTL/ST(2)
Interrupt-on-change pin or In-Circuit Debugger pin.
Serial programming data.
RB0 can also be the external interrupt pin.
RB3 can also be the low voltage programming input.
Interrupt-on-change pin.
Interrupt-on-change pin.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
15
16
32
I/O
ST
RC0 can also be the Timer1 oscillator output or a Timer1
clock input.
RC1/T1OSI
16
18
35
I/O
ST
RC1 can also be the Timer1 oscillator input.
RC2/CCP1
17
19
36
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3
18
20
37
I/O
ST
RC4
23
25
42
I/O
ST
RC5
24
26
43
I/O
ST
RC6/TX/CK
25
27
44
I/O
ST
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Legend:
Note 1:
2:
3:
4:
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS30569C-page 8
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 1-2:
Pin Name
PIC16F871 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
PORTD is a bi-directional I/O port or parallel slave port when
interfacing to a microprocessor bus.
RD0/PSP0
19
21
38
I/O
ST/TTL(3)
RD1/PSP1
20
22
39
I/O
ST/TTL(3)
RD2/PSP2
21
23
40
I/O
ST/TTL(3)
RD3/PSP3
22
24
41
I/O
ST/TTL(3)
RD4/PSP4
27
30
2
I/O
ST/TTL(3)
RD5/PSP5
28
31
3
I/O
ST/TTL(3)
RD6/PSP6
29
32
4
I/O
ST/TTL(3)
RD7/PSP7
30
33
5
I/O
ST/TTL(3)
RE0/RD/AN5
8
9
25
I/O
ST/TTL
(3)
RE0 can also be read control for the parallel slave port, or
analog input 5.
RE1/WR/AN6
9
10
26
I/O
ST/TTL(3)
RE1 can also be write control for the parallel slave port, or
analog input 6.
RE2/CS/AN7
10
11
27
I/O
ST/TTL(3)
RE2 can also be select control for the parallel slave port,
or analog input 7.
PORTE is a bi-directional I/O port.
VSS
12,31
13,34
6,29
P
—
Ground reference for logic and I/O pins.
VDD
11,32
12,35
7,28
P
—
Positive supply for logic and I/O pins.
NC
—
1,17,28,
40
12,13,
33,34
—
These pins are not internally connected. These pins should be
left unconnected.
Legend:
Note 1:
2:
3:
4:
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2000-2013 Microchip Technology Inc.
DS30569C-page 9
PIC16F870/871
NOTES:
DS30569C-page 10
2000-2013 Microchip Technology Inc.
PIC16F870/871
2.0
MEMORY ORGANIZATION
The PIC16F870/871 devices have three memory
blocks. The Program Memory and Data Memory have
separate buses, so that concurrent access can occur,
and is detailed in this section. The EEPROM data
memory block is detailed in Section 3.0.
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS)
and RP0 (STATUS) are the bank select bits.
Additional information on device memory may be found
in the PICmicroTM Mid-Range MCU Family Reference
Manual (DS33023).
2.1
Program Memory Organization
The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have
2K x 14 words of FLASH program memory. Accessing
a location above the physically implemented address
will cause a wraparound.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1:
PIC16F870/871 PROGRAM
MEMORY MAP AND STACK
Bank
00
0
01
1
10
2
11
3
Note:
EEPROM Data Memory description can
be found in Section 3.0 of this Data Sheet.
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or
indirectly through the File Select Register FSR.
13
CALL, RETURN
RETFIE, RETLW
RP
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1
PC
Data Memory Organization
Stack Level 1
Stack Level 2
Stack Level 8
On-Chip
Program
Memory
RESET Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
1FFFh
2000-2013 Microchip Technology Inc.
DS30569C-page 11
PIC16F870/871
FIGURE 2-2:
PIC16F870/871 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(2)
PORTE(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Register
File
Address
Indirect addr.(*)
80h
OPTION_REG 81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
88h
TRISD(2)
(2)
TRISE
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
8Fh
90h
91h
PR2
92h
93h
94h
95h
96h
97h
TXSTA
98h
SPBRG
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
General
Purpose
Register
A0h
32 Bytes
BFh
C0h
96 Bytes
7Fh
Bank 0
accesses
70h-7Fh
Bank 1
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
120h
accesses
A0h - BFh
accesses
20h-7Fh
EFh
F0h
File
Address
File
Address
1BFh
1C0h
accesses
70h-7Fh
FFh
Bank 2
16Fh
170h
17Fh
accesses
70h-7Fh
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as '0'.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
2: These registers are not implemented on the PIC16F870.
DS30569C-page 12
2000-2013 Microchip Technology Inc.
PIC16F870/871
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
Address
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS(2)
Bank 0
00h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
02h(4)
PCL
Program Counter's (PC) Least Significant Byte
03h(4)
STATUS
IRP
RP1
RP0
TO
0000 0000 0000 0000
PD
Z
DC
C
0001 1xxx 000q quuu
04h(4)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h(5)
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
09h(5)
PORTE
—
—
—
0Ah(1,4)
PCLATH
—
—
—
Indirect Data Memory Address Pointer
—
—
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
—
—
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
---- -xxx ---- -uuu
---0 0000 ---0 0000
0Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
PIR1
PSPIF(3)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000 0000 -000
0Dh
PIR2
—
—
—
EEIF
—
—
—
—
---0 ---- ---0 ----
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
11h
TMR2
12h
T2CON
—
—
T1CKPS1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON --00 0000 --uu uuuu
TOUTPS3 TOUTPS2 TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Module’s Register
—
0000 000x 0000 000u
0000 0000 0000 0000
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
17h
CCP1CON
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
CCP1M0 --00 0000 --00 0000
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH
1Fh
ADCON0
Legend:
Note 1:
2:
3:
4:
5:
RX9D
A/D Result Register High Byte
ADCS1
ADCS0
CHS2
0000 000x 0000 000x
xxxx xxxx uuuu uuuu
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter.
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
2000-2013 Microchip Technology Inc.
DS30569C-page 13
PIC16F870/871
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS(2)
Bank 1
80h(4)
INDF
81h
OPTION_REG
82h(4)
PCL
83h(4)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PS2
PS1
PS0
1111 1111 1111 1111
PD
Z
DC
C
0001 1xxx 000q quuu
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
0000 0000 0000 0000
PSA
0000 0000 0000 0000
84h(4)
FSR
85h
TRISA
86h
TRISB
PORTB Data Direction Register
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h(5)
TRISD
PORTD Data Direction Register
1111 1111 1111 1111
89h(5)
TRISE
IBF
OBF
IBOV
8Ah(1,4)
PCLATH
—
—
—
Indirect Data Memory Address Pointer
—
—
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
PSPMODE
—
PORTE Data Direction Bits
0000 -111 0000 -111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
8Bh(4)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
8Ch
PIE1
PSPIE(3)
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000 0000 -000
8Dh
PIE2
—
—
—
EEIE
—
—
—
—
---0 ---- ---0 ----
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
0000 000x 0000 000u
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
PR2
Timer2 Period Register
1111 1111 1111 1111
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
99h
SPBRG
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
ADRESL
9Fh
ADCON1
Legend:
Note 1:
2:
3:
4:
5:
Baud Rate Generator Register
0000 -010 0000 -010
0000 0000 0000 0000
A/D Result Register Low Byte
ADFM
—
—
xxxx xxxx uuuu uuuu
—
PCFG3
PCFG2
PCFG1
PCFG0
0--- 0000
0--- 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter.
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
DS30569C-page 14
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS(2)
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
101h
TMR0
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
102h(4)
PCL
Program Counter's (PC) Least Significant Byte
103h(4)
STATUS
104h(4)
FSR
IRP
RP1
RP0
0000 0000 0000 0000
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
105h
—
106h
PORTB
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
—
Unimplemented
—
—
10Ah(1,4)
PCLATH
Unimplemented
—
PORTB Data Latch when written: PORTB pins when read
—
—
—
GIE
PEIE
T0IE
—
xxxx xxxx uuuu uuuu
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
10Bh(4)
INTCON
10Ch
EEDATA
EEPROM Data Register
xxxx xxxx uuuu uuuu
10Dh
EEADR
EEPROM Address Register
xxxx xxxx uuuu uuuu
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
INTE
RBIE
T0IF
INTF
RBIF
EEPROM Data Register High Byte
—
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
EEPROM Address Register High Byte
xxxx xxxx uuuu uuuu
Bank 3
180h(4)
INDF
181h
OPTION_REG
182h(4)
PCL
183h(4)
STATUS
184h(4)
FSR
185h
Addressing this location uses contents of FSR to address data memory (not a physical register)
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TRISB
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
TO
Indirect Data Memory Address Pointer
—
186h
RBPU
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
Unimplemented
—
PORTB Data Direction Register
—
1111 1111 1111 1111
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
18Ah(1,4)
PCLATH
18Bh(4)
18Ch
18Dh
EECON2
18Eh
18Fh
Legend:
Note 1:
2:
3:
4:
5:
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
EECON1
EEPGD
—
—
—
WRERR
WREN
WR
RD
x--- x000 x--- u000
---0 0000 ---0 0000
EEPROM Control Register2 (not a physical register)
---- ---- ---- ----
—
Reserved maintain clear
0000 0000 0000 0000
—
Reserved maintain clear
0000 0000 0000 0000
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter.
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
2000-2013 Microchip Technology Inc.
DS30569C-page 15
PIC16F870/871
2.2.2.1
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1:
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see the
“Instruction Set Summary”.
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7-6
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 1 (80h - FFh)
10 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes.
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
DS30569C-page 16
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2000-2013 Microchip Technology Inc.
PIC16F870/871
2.2.2.2
OPTION_REG Register
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External
INT interrupt, TMR0 and the weak pull-ups on PORTB.
Note:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
REGISTER 2-2:
OPTION_REG REGISTER (ADDRESS: 81h,181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 17
PIC16F870/871
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
DS30569C-page 18
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2000-2013 Microchip Technology Inc.
PIC16F870/871
2.2.2.4
PIE1 Register
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
Note:
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS: 8Ch)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
PSPIE(1)
ADIE
RCIE
TXIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 19
PIC16F870/871
2.2.2.5
PIR1 Register
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt bits are clear prior to enabling an
interrupt.
REGISTER 2-5:
PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0
R/W-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
PSPIF(1)
ADIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear.
Legend:
DS30569C-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2000-2013 Microchip Technology Inc.
PIC16F870/871
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS: 8Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIE
—
—
—
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
bit 4
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE write interrupt
0 = Disable EE write interrupt
bit 3-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 21
PIC16F870/871
2.2.2.7
PIR2 Register
The PIR2 register contains the flag bit for the EEPROM
write operation interrupt.
.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS: 0Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIF
—
—
—
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3-0
Unimplemented: Read as '0'
Legend:
DS30569C-page 22
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2000-2013 Microchip Technology Inc.
PIC16F870/871
2.2.2.8
PCON Register
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
Note:
BOR is unknown on POR. It must be set
by the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred. The BOR
status bit is a don’t care and is not
predictable if the brown-out circuit is disabled (by clearing the BOREN bit in the
configuration word).
REGISTER 2-8:
PCON REGISTER (ADDRESS: 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-1
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
bit 7-2
Unimplemented: Read as '0'
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 23
PIC16F870/871
2.3
PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The upper bits (PC) are
not readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-3 shows the two situations
for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL
(PCLATH PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
ALU
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO,CALL
2
PCLATH
11
Opcode
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
application note, “Implementing a Table Read"
(AN556).
2.3.2
STACK
The PIC16FXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event
of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
DS30569C-page 24
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt
address.
2.4
Program Memory Paging
The PIC16FXXX architecture is capable of addressing
a continuous 8K word block of program memory. The
CALL and GOTO instructions provide 11 bits of the
address, which allows branches within any 2K program
memory page. Therefore, the 8K words of program
memory are broken into four pages. Since the
PIC16F872 has only 2K words of program memory or
one page, additional code is not required to ensure that
the correct page is selected before a CALL or GOTO
instruction is executed. The PCLATH bits should
always be maintained as zeros. If a return from a CALL
instruction (or interrupt) is executed, the entire 13-bit
PC is popped off the stack. Manipulation of the
PCLATH is not required for the return instructions.
2.5
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select register, FSR. Reading the INDF register itself indirectly
(FSR = 0) will read 00h. Writing to the INDF register
indirectly results in a no operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS), as shown in Figure 2-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
movlw
movwf
NEXT
clrf
incf
btfss
goto
CONTINUE
:
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
2000-2013 Microchip Technology Inc.
PIC16F870/871
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
RP1: RP0
6
Bank Select
Location Select
0
IRP
7
Bank Select
00
01
10
FSR Register
0
Location Select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory(1)
Bank 0
Note 1:
Bank 1
Bank 2
Bank 3
For register file map detail see Figure 2-2.
2000-2013 Microchip Technology Inc.
DS30569C-page 25
PIC16F870/871
NOTES:
DS30569C-page 26
2000-2013 Microchip Technology Inc.
PIC16F870/871
3.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The Data EEPROM and FLASH Program Memory are
readable and writable during normal operation over the
entire VDD range. A bulk erase operation may not be
issued from user code (which includes removing code
protection). The data memory is not directly mapped in
the register file space. Instead, it is indirectly addressed
through the Special Function Registers (SFR).
There are six SFRs used to read and write the program
and data EEPROM memory. These registers are:
•
•
•
•
•
•
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. The
registers EEDATH and EEADRH are not used for data
EEPROM access. The PIC16F870/871 devices have
64 bytes of data EEPROM with an address range from
0h to 3Fh.
The value written to program memory does not need to
be a valid instruction. Therefore, up to 14-bit numbers
can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that
forms an invalid instruction results in a NOP.
3.1
EEADR
The address registers can address up to a maximum of
256 bytes of data EEPROM or up to a maximum of
8K words of program FLASH. However, the
PIC16F870/871 have 64 bytes of data EEPROM and
2K words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the EEADRH register and
the LSByte is written to the EEADR register. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register.
On the PIC16F870/871 devices, the upper two bits of
the EEADR must always be cleared to prevent inadvertent access to the wrong location in data EEPROM.
This also applies to the program memory. The upper
five MSbits of EEADRH must always be clear during
program FLASH access.
3.2
EECON1 and EECON2 Registers
The EEPROM data memory is rated for high erase/
write cycles. The write time is controlled by an on-chip
timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to the
specifications for exact limits.
The EECON1 register is the control register for configuring and initiating the access. The EECON2 register is
not a physically implemented register, but is used
exclusively in the memory write sequence to prevent
inadvertent writes.
The program memory allows word reads and writes.
Program memory access allows for checksum calculation and calibration table storage. A byte or word write
automatically erases the location and writes the new
data (erase before write). Writing to program memory
will cease operation until the write is complete. The program memory cannot be accessed during the write,
therefore code cannot execute. During the write operation, the oscillator continues to clock the peripherals,
and therefore, they continue to operate. Interrupt
events will be detected and essentially “queued” until
the write is completed. When the write completes, the
next instruction in the pipeline is executed and the
branch to the interrupt vector address will occur.
There are many bits used to control the read and write
operations to EEPROM data and FLASH program
memory. The EEPGD bit determines if the access will
be a program or data memory access. When clear, any
subsequent operations will work on the EEPROM data
memory. When set, all subsequent operations will
operate in the program memory.
When interfacing to the program memory block, the
EEDATH:EEDATA registers form a two-byte word,
which holds the 14-bit data for read/write. The
EEADRH:EEADR registers form a two-byte word,
which holds the 13-bit address of the FLASH location
being accessed. The PIC16F870/871 devices have
2K words of program FLASH with an address range
from 0h to 7FFh. The unused upper bits in both the
EEDATH and EEDATA registers all read as ‘0’s.
2000-2013 Microchip Technology Inc.
Read operations only use one additional bit, RD, which
initiates the read operation from the desired memory
location. Once this bit is set, the value of the desired
memory location will be available in the data registers.
This bit cannot be cleared by firmware. It is automatically cleared at the end of the read operation. For
EEPROM data memory reads, the data will be available in the EEDATA register in the very next instruction
cycle after the RD bit is set. For program memory
reads, the data will be loaded into the
EEDATH:EEDATA registers, following the second
instruction after the RD bit is set.
DS30569C-page 27
PIC16F870/871
Write operations have two control bits, WR and WREN,
and two status bits, WRERR and EEIF. The WREN bit
is used to enable or disable the write operation. When
WREN is clear, the write operation will be disabled.
Therefore, the WREN bit must be set before executing
a write operation. The WR bit is used to initiate the write
operation. It also is automatically cleared at the end of
the write operation. The interrupt flag EEIF is used to
determine when the memory write completes. This flag
must be cleared in software before setting the WR bit.
For EEPROM data memory, once the WREN bit and
the WR bit have been set, the desired memory address
in EEADR will be erased, followed by a write of the data
in EEDATA. This operation takes place in parallel with
the microcontroller continuing to execute normally.
When the write is complete, the EEIF flag bit will be set.
For program memory, once the WREN bit and the WR
bit have been set, the microcontroller will cease to exe-
REGISTER 3-1:
cute instructions. The desired memory location pointed
to by EEADRH:EEADR will be erased. Then, the data
value in EEDATH:EEDATA will be programmed. When
complete, the EEIF flag bit will be set and the
microcontroller will continue to execute code.
The WRERR bit is used to indicate when the
PIC16F870/871 devices have been reset during a write
operation. WRERR should be cleared after Power-on
Reset. Thereafter, it should be checked on any other
RESET. The WRERR bit is set when a write operation
is interrupted by a MCLR Reset, or a WDT Time-out
Reset, during normal operation. In these situations, following a RESET, the user should check the WRERR bit
and rewrite the memory location, if set. The contents of
the data registers, address registers and EEPGD bit
are not affected by either MCLR Reset, or WDT
Time-out Reset, during normal operation.
EECON1 REGISTER (ADDRESS: 18Ch)
R/W-x
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
(This bit cannot be changed while a read or write operation is in progress.)
bit 6-4
Unimplemented: Read as '0'
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during
normal operation)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.)
0 = Does not initiate an EEPROM read
Legend:
DS30569C-page 28
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
2000-2013 Microchip Technology Inc.
PIC16F870/871
3.3
Reading the EEPROM Data
Memory
Reading EEPROM data memory only requires that the
desired address to access be written to the EEADR
register and clear the EEPGD bit. After the RD bit is set,
data will be available in the EEDATA register on the
very next instruction cycle. EEDATA will hold this value
until another read operation is initiated or until it is
written by firmware.
The steps to reading the EEPROM data memory are:
1.
2.
3.
4.
Write the address to EEDATA. Make sure that
the address is not larger than the memory size
of the PIC16F870/871 devices.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the RD bit to start the read operation.
Read the data from the EEDATA register.
EXAMPLE 3-1:
EEPROM DATA READ
BSF
BCF
MOVF
MOVWF
BSF
BCF
BSF
BCF
STATUS,
STATUS,
ADDR, W
EEADR
STATUS,
EECON1,
EECON1,
STATUS,
RP1
RP0
MOVF
EEDATA, W
RP0
EEPGD
RD
RP0
;
;Bank 2
;Write address
;to read from
;Bank 3
;Point to Data memory
;Start read operation
;Bank 2
The steps to write to EEPROM data memory are:
1.
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the PIC16F870/871 devices.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
• Write AAh to EECON2 in two steps (first to
W, then to EECON2)
• Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
;W = EEDATA
EXAMPLE 3-2:
3.4
Writing to the EEPROM Data
Memory
There are many steps in writing to the EEPROM data
memory. Both address and data values must be written
to the SFRs. The EEPGD bit must be cleared, and the
WREN bit must be set, to enable writes. The WREN bit
should be kept clear at all times, except when writing to
the EEPROM data. The WR bit can only be set if the
WREN bit was set in a previous operation (i.e., they
both cannot be set in the same operation). The WREN
bit should then be cleared by firmware after the write.
Clearing the WREN bit before the write actually
completes will not terminate the write in progress.
Writes to EEPROM data memory must also be prefaced with a special sequence of instructions that prevent inadvertent write operations. This is a sequence of
five instructions that must be executed without interruptions. The firmware should verify that a write is not in
progress before starting another cycle.
2000-2013 Microchip Technology Inc.
EEPROM DATA WRITE
BSF STATUS, RP1 ;
BSF STATUS, RP0 ;Bank 3
BTFSC EECON1, WR
;Wait for
GOTO $-1
;write to finish
BCF STATUS, RP0 ;Bank 2
MOVF ADDR, W
;Address to
MOVWF EEADR
;write to
MOVF VALUE, W
;Data to
MOVWF EEDATA
;write
BSF STATUS, RP0 ;Bank 3
BCF EECON1, EEPGD ;Point to Data memory
BSF EECON1, WREN ;Enable writes
;Only disable interrupts
BCF INTCON, GIE ;if already enabled,
;otherwise discard
MOVLW 0x55
;Write 55h to
MOVWF EECON2
;EECON2
MOVLW 0xAA
;Write AAh to
MOVWF EECON2
;EECON2
BSF EECON1, WR
;Start write operation
;Only enable interrupts
BSF INTCON, GIE ;if using interrupts,
;otherwise discard
BCF EECON1, WREN ;Disable writes
DS30569C-page 29
PIC16F870/871
3.5
Reading the FLASH Program
Memory
3.6
Writing to the FLASH Program
Memory
Reading FLASH program memory is much like that of
EEPROM data memory, only two NOP instructions must
be inserted after the RD bit is set. These two instruction
cycles that the NOP instructions execute, will be used by
the microcontroller to read the data out of program
memory and insert the value into the EEDATH:EEDATA
registers. Data will be available following the second
NOP instruction. EEDATH and EEDATA will hold their
value until another read operation is initiated, or until
they are written by firmware.
Writing to FLASH program memory is unique, in that
the microcontroller does not execute instructions while
programming is taking place. The oscillator continues
to run and all peripherals continue to operate and
queue interrupts, if enabled. Once the write operation
completes (specification D133), the processor begins
executing code from where it left off. The other important difference when writing to FLASH program memory is that the WRT configuration bit, when clear,
prevents any writes to program memory (see Table 3-1).
The steps to reading the FLASH program memory are:
Just like EEPROM data memory, there are many steps
in writing to the FLASH program memory. Both address
and data values must be written to the SFRs. The
EEPGD bit must be set, and the WREN bit must be set
to enable writes. The WREN bit should be kept clear at
all times, except when writing to the FLASH program
memory. The WR bit can only be set if the WREN bit
was set in a previous operation (i.e., they both cannot
be set in the same operation). The WREN bit should
then be cleared by firmware after the write. Clearing the
WREN bit before the write actually completes will not
terminate the write in progress.
1.
2.
3.
4.
5.
Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the
memory size of the PIC16F870/871 devices.
Set the EEPGD bit to point to FLASH program
memory.
Set the RD bit to start the read operation.
Execute two NOP instructions to allow the
microcontroller to read out of program memory.
Read the data from the EEDATH:EEDATA
registers.
EXAMPLE 3-3:
BSF
BCF
MOVF
MOVWF
MOVF
MOVWF
BSF
BSF
BSF
NOP
NOP
BCF
MOVF
MOVWF
MOVF
MOVWF
FLASH PROGRAM READ
STATUS, RP1
STATUS, RP0
ADDRL, W
EEADR
ADDRH,W
EEADRH
STATUS, RP0
EECON1, EEPGD
EECON1, RD
STATUS, RP0
EEDATA, W
DATAL
EEDATH,W
DATAH
;
;Bank 2
;Write the
;address bytes
;for the desired
;address to read
;Bank 3
;Point to Program memory
;Start read operation
;Required two NOPs
;
;Bank 2
;DATAL = EEDATA
;
;DATAH = EEDATH
;
Writes to program memory must also be prefaced with
a special sequence of instructions that prevent inadvertent write operations. This is a sequence of five
instructions that must be executed without interruption
for each byte written. These instructions must then be
followed by two NOP instructions to allow the microcontroller to setup for the write operation. Once the write is
complete, the execution of instructions starts with the
instruction after the second NOP.
The steps to write to program memory are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
DS30569C-page 30
Write the address to EEADRH:EEADR. Make
sure that the address is not larger than the
memory size of the PIC16F870/871 devices.
Write the 14-bit data value to be programmed in
the EEDATH:EEDATA registers.
Set the EEPGD bit to point to FLASH program
memory.
Set the WREN bit to enable program operations.
Disable interrupts (if enabled).
Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
• Write AAh to EECON2 in two steps (first to W,
then to EECON2)
• Set the WR bit
Execute two NOP instructions to allow the
microcontroller to setup for write operation.
Enable interrupts (if using interrupts).
Clear the WREN bit to disable program
operations.
2000-2013 Microchip Technology Inc.
PIC16F870/871
At the completion of the write cycle, the WR bit is
cleared and the EEIF interrupt flag bit is set. (EEIF
must be cleared by firmware.) Since the microcontroller
does not execute instructions during the write cycle, the
firmware does not necessarily have to check either
EEIF, or WR, to determine if the write had finished.
EXAMPLE 3-4:
FLASH PROGRAM WRITE
BSF
BCF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
BSF
BSF
BSF
STATUS, RP1
STATUS, RP0
ADDRL, W
EEADR
ADDRH, W
EEADRH
VALUEL, W
EEDATA
VALUEH, W
EEDATH
STATUS, RP0
EECON1, EEPGD
EECON1, WREN
BCF
INTCON, GIE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
0x55
EECON2
0xAA
EECON2
EECON1, WR
BSF
INTCON, GIE
BCF
EECON1, WREN
3.7
;
;Bank 2
;Write address
;of desired
;program memory
;location
;Write value to
;program at
;desired memory
;location
;Bank 3
;Point to Program memory
;Enable writes
;Only disable interrupts
;if already enabled,
;otherwise discard
;Write 55h to
;EECON2
;Write AAh to
;EECON2
;Start write operation
;Two NOPs to allow micro
;to setup for write
;Only enable interrupts
;if using interrupts,
;otherwise discard
;Disable writes
Write Verify
The PIC16F870/871 devices do not automatically verify the value written during a write operation. Depending on the application, good programming practice may
dictate that the value written to memory be verified
against the original value. This should be used in applications where excessive writes can stress bits near the
specified endurance limits.
2000-2013 Microchip Technology Inc.
3.8
Protection Against Spurious
Writes
There are conditions when the device may not want to
write to the EEPROM data memory or FLASH program
memory. To protect against these spurious write conditions, various mechanisms have been built into the
PIC16F870/871 devices. On power-up, the WREN bit
is cleared and the Power-up Timer (if enabled)
prevents writes.
The write initiate sequence and the WREN bit together,
help prevent any accidental writes during brown-out,
power glitches, or firmware malfunction.
3.9
Operation While Code Protected
The PIC16F870/871 devices have two code protect
mechanisms, one bit for EEPROM data memory and
two bits for FLASH program memory. Data can be read
and written to the EEPROM data memory, regardless
of the state of the code protection bit, CPD. When code
protection is enabled and CPD cleared, external
access via ICSP is disabled, regardless of the state of
the program memory code protect bits. This prevents
the contents of EEPROM data memory from being read
out of the device.
The state of the program memory code protect bits,
CP0 and CP1, do not affect the execution of instructions out of program memory. The PIC16F870/871
devices can always read the values in program memory, regardless of the state of the code protect bits.
However, the state of the code protect bits and the
WRT bit will have different effects on writing to program
memory. Table 4-1 shows the effect of the code protect
bits and the WRT bit on program memory.
Once code protection has been enabled for either
EEPROM data memory or FLASH program memory,
only a full erase of the entire device will disable code
protection.
DS30569C-page 31
PIC16F870/871
3.10
FLASH Program Memory Write
Protection
The configuration word contains a bit that write protects
the FLASH program memory, called WRT. This bit can
only be accessed when programming the
PIC16F870/871 devices via ICSP. Once write protection is enabled, only an erase of the entire device will
disable it. When enabled, write protection prevents any
writes to FLASH program memory. Write protection
does not affect program memory reads.
TABLE 3-1:
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
Configuration Bits
Internal
Read
Memory Location
Internal
Write
ICSP Read ICSP Write
CP1
CP0
WRT
0
0
x
All program memory
Yes
No
No
No
0
1
0
Unprotected areas
Yes
No
Yes
No
0
1
0
Protected areas
Yes
No
No
No
0
1
1
Unprotected areas
Yes
Yes
Yes
No
0
1
1
Protected areas
Yes
No
No
No
1
0
0
Unprotected areas
Yes
No
Yes
No
1
0
0
Protected areas
Yes
No
No
No
1
0
1
Unprotected areas
Yes
Yes
Yes
No
1
0
1
Protected areas
Yes
No
No
No
1
1
0
All program memory
Yes
No
Yes
Yes
1
1
1
All program memory
Yes
Yes
Yes
Yes
TABLE 3-2:
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
Address
10Dh
EEADR
10Fh
EEADRH
10Ch
EEDATA
10Eh
EEDATH
—
—
18Ch
EECON1
EEPGD
—
18Dh
EECON2 EEPROM Control Register2 (not a physical register)
Legend:
Note 1:
EEPROM Address Register, Low Byte
—
—
—
EEPROM Address, High Byte
EEPROM Data Register, Low Byte
EEPROM Data Register, High Byte
—
—
WRERR
WREN
WR
RD
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
x--- x000
x--- u000
—
—
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.
Shaded cells are not used during FLASH/EEPROM access.
These bits are reserved; always maintain these bits clear.
DS30569C-page 32
2000-2013 Microchip Technology Inc.
PIC16F870/871
4.0
I/O PORTS
FIGURE 4-1:
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PIC® Mid-Range MCU Family Reference Manual
(DS33023).
4.1
Data
Bus
D
Q
VDD
WR
Port
Q
CK
P
Data Latch
PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
D
WR
TRIS
N
Q
VSS
Analog
Input
Mode
Q
CK
TRIS Latch
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register 1).
Note:
On a Power-on Reset, these pins are
configured as analog inputs and read as
'0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 4-1:
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
STATUS, RP0
0x06
ADCON1
0xCF
TRISA
Q
;
;Bank0
;Initialize PORTA by
;clearing output
;data latches
;Select Bank 1
;Configure all pins
;as digital inputs
;Value used to
;initialize data
;direction
;Set RA as
;inputs
;RA as outputs
;TRISA are
;always read as '0'.
2000-2013 Microchip Technology Inc.
D
EN
RD PORT
To A/D Converter
Note 1:
I/O pins have protection diodes to VDD and VSS.
FIGURE 4-2:
Data
Bus
WR
PORT
BLOCK DIAGRAM OF
RA4/T0CKI PIN
D
Q
CK
Q
N
Data Latch
WR
TRIS
INITIALIZING PORTA
STATUS, RP0
STATUS, RP1
PORTA
TTL
Input
Buffer
RD TRIS
Reading the PORTA register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore,
a write to a port implies that the port pins are read, the
value is modified and then written to the port data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
I/O pin(1)
D
Q
CK
Q
I/O pin(1)
VSS
Schmitt
Trigger
Input
Buffer
TRIS Latch
RD TRIS
Q
D
ENEN
RD PORT
TMR0 Clock Input
Note 1:
I/O pin has protection diodes to VSS only.
DS30569C-page 33
PIC16F870/871
TABLE 4-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit0
TTL
Input/output or analog input.
RA1/AN1
bit1
TTL
Input/output or analog input.
RA2/AN2
bit2
TTL
Input/output or analog input.
RA3/AN3/VREF
bit3
TTL
Input/output or analog input or VREF.
RA4/T0CKI
bit4
ST
Input/output or external clock input for Timer0. Output is open drain type.
RA5/AN4
bit5
TTL
Input/output or analog input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1 ADFM
Legend:
—
Value on
all other
RESETS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --0u 0000
PORTA Data Direction Register
—
—
--11 1111 --11 1111
PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
DS30569C-page 34
2000-2013 Microchip Technology Inc.
PIC16F870/871
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Three pins of PORTB are multiplexed with the Low
Voltage Programming function: RB3/PGM, RB6/PGC
and RB7/PGD. The alternate functions of these pins
are described in the Special Features Section.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
Data Bus
WR Port
Weak
P Pull-up
Data Latch
D
Q
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
RB0/INT is discussed in detail in Section 11.10.1.
FIGURE 4-4:
I/O
BLOCK DIAGRAM OF
RB7:RB4 PINS
pin(1)
CK
VDD
RBPU(2)
TRIS Latch
D
Q
WR TRIS
a)
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION_REG).
VDD
RBPU(2)
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
TTL
Input
Buffer
CK
Weak
P Pull-up
Data Latch
Data Bus
D
Q
I/O pin(1)
WR Port
CK
TRIS Latch
RD TRIS
D
Q
WR TRIS
RD Port
TTL
Input
Buffer
CK
EN
RB0/INT
RB3/PGM
RD TRIS
Schmitt Trigger
Buffer
Note 1:
2:
Q
D
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG).
Four of PORTB’s pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON).
2000-2013 Microchip Technology Inc.
Latch
Q
RD Port
From other
RB7:RB4 pins
D
EN
RD Port
Set RBIF
ST
Buffer
Q
Q1
D
RD Port
EN
Q3
RB7:RB6 in Serial Programming Mode
Note 1:
2:
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG).
DS30569C-page 35
PIC16F870/871
TABLE 4-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
(1)
Function
RB0/INT
bit0
TTL/ST
RB1
bit1
TTL
RB2
bit2
TTL
RB3/PGM
bit3
TTL/ST(1)
RB4
bit4
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6/PGC
bit6
TTL/ST(2)
Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD
bit7
TTL/ST(2)
Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.
Internal software programmable weak pull-up. Serial programming data.
Legend:
Note 1:
2:
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
TTL = TTL input, ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 4-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
06h, 106h
PORTB
86h, 186h
TRISB
81h, 181h
OPTION_REG
Legend:
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
T0SE
PSA
PS2
PS1
PS0
PORTB Data Direction Register
RBPU
INTEDG
T0CS
1111 1111 1111 1111
1111 1111 1111 1111
x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30569C-page 36
2000-2013 Microchip Technology Inc.
PIC16F870/871
4.3
FIGURE 4-5:
PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
WR
PORT
PORTC is multiplexed with several peripheral functions
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
VDD
0
D
Q
P
1
CK
Q
Data Latch
WR
TRIS
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
the destination should be avoided. The user should
refer to the corresponding peripheral section for the
correct TRIS bit settings.
D
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
Vss
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
EN
RD
PORT
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between
port data and peripheral output.
3: Peripheral OE (Output Enable) is only activated
if Peripheral Select is active.
TABLE 4-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI
bit1
ST
Input/output port pin or Timer1 oscillator input.
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3
bit3
ST
Input/output port pin.
RC4
bit4
ST
Input/output port pin.
RC5
bit5
ST
Input/output port pin.
RC6/TX/CK
bit6
ST
Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive or
Synchronous Data.
Legend:
ST = Schmitt Trigger input
TABLE 4-6:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
07h
PORTC
87h
TRISC
Legend:
x = unknown, u = unchanged
PORTC Data Direction Register
2000-2013 Microchip Technology Inc.
DS30569C-page 37
PIC16F870/871
4.4
FIGURE 4-6:
PORTD and TRISD Registers
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
This section is not applicable to the PIC16F870.
Data
Bus
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or
output.
WR
Port
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE). In this mode, the input buffers
are TTL.
D
Q
I/O pin(1)
CK
Data Latch
D
WR
TRIS
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRIS
Q
D
ENEN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 4-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
RD0/PSP0
bit0
ST/TTL(1)
Input/output port pin or parallel slave port bit0.
RD1/PSP1
bit1
ST/TTL
(1)
Input/output port pin or parallel slave port bit1.
RD2/PSP2
bit2
ST/TTL
(1)
Input/output port pin or parallel slave port bit2.
RD3/PSP3
bit3
ST/TTL(1)
Input/output port pin or parallel slave port bit3.
RD4/PSP4
bit4
ST/TTL(1)
Input/output port pin or parallel slave port bit4.
RD5/PSP5
bit5
ST/TTL(1)
Input/output port pin or parallel slave port bit5.
RD6/PSP6
bit6
ST/TTL(1)
Input/output port pin or parallel slave port bit6.
RD7/PSP7
bit7
ST/TTL(1)
Input/output port pin or parallel slave port bit7.
Legend:
Note 1:
ST = Schmitt Trigger input, TTL = TTL input
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-8:
Address
Function
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
08h
PORTD
88h
TRISD
89h
TRISE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
0000 -111
0000 -111
PORTD Data Direction Register
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
DS30569C-page 38
2000-2013 Microchip Technology Inc.
PIC16F870/871
4.5
PORTE and TRISE Register
This section is not applicable to the PIC16F870.
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE) is set. In
this mode, the user must make sure that the
TRISE bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
FIGURE 4-7:
Data
Bus
WR
PORT
On a Power-on Reset, these pins are
configured as analog inputs.
2000-2013 Microchip Technology Inc.
Q
I/O pin(1)
CK
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
Note:
D
Data Latch
Register 4-1 shows the TRISE register, which also
controls the parallel slave port operation.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
Q
D
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
DS30569C-page 39
PIC16F870/871
REGISTER 4-1:
TRISE REGISTER (ADDRESS: 89h)
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
—
Bit2
Bit1
Bit0
bit 7
bit 0
bit 7
Parallel Slave Port Status/Control Bits
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3
Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2
Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1
Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0
Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Legend:
DS30569C-page 40
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 4-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/RD/AN5
bit0
ST/TTL(1)
Input/output port pin or read control input in Parallel Slave Port mode or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected.)
RE1/WR/AN6
bit1
ST/TTL(1)
Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected).
RE2/CS/AN7
bit2
ST/TTL(1)
Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend:
Note 1:
ST = Schmitt Trigger input, TTL = TTL input
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-10:
Addr
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
9Fh
ADCON1
ADFM
—
—
—
PCFG3
Legend:
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
RE2
RE1
RE0
---- -xxx
---- -uuu
0000 -111
0000 -111
--0- 0000
--0- 0000
PORTE Data Direction Bits
PCFG2
PCFG1
PCFG0
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
2000-2013 Microchip Technology Inc.
DS30569C-page 41
PIC16F870/871
4.6
Parallel Slave Port
FIGURE 4-8:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
The Parallel Slave Port is not implemented on the
PIC16F870.
PORTD operates as an 8-bit wide Parallel Slave Port or
microprocessor port when control bit PSPMODE
(TRISE) is set. In Slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE)
must be configured as inputs (set). The A/D port configuration bits PCFG3:PCFG0 (ADCON1) must be
set to configure pins RE2:RE0 as digital I/O.
There are actually two 8-bit latches. One for data output and one for data input. The user writes 8-bit data to
the PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, the TRISD register is ignored, since the
microprocessor is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 4-9). The interrupt flag bit, PSPIF
(PIR1), is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
Data Bus
D
WR
Port
Q
RDx
pin
CK
TTL
Q
RD
Port
D
ENEN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note: I/O pin has protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE) is cleared immediately (Figure 4-10), indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1).
DS30569C-page 42
2000-2013 Microchip Technology Inc.
PIC16F870/871
FIGURE 4-9:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
FIGURE 4-10:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 4-11:
Address
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
08h
PORTD
09h
PORTE
89h
TRISE
0Ch
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RE1
RE0
Port Data Latch when written: Port pins when read
RE2
Value on:
POR, BOR
Value on
all other
RESETS
xxxx xxxx
uuuu uuuu
---- -xxx
---- -uuu
—
—
—
—
—
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
0000 -111
0000 -111
PSPIF ADIF
RCIF
TXIF
—
CCP1IF TMR2IF
TMR1IF
0000 0000
0000 0000
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
—
—
PCFG3
PCFG2
--0- 0000
--0- 0000
8Ch
PIE1
PSPIE ADIE
9Fh
ADCON1
ADFM
Legend:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
—
2000-2013 Microchip Technology Inc.
PCFG1
PCFG0
DS30569C-page 43
PIC16F870/871
NOTES:
DS30569C-page 44
2000-2013 Microchip Technology Inc.
PIC16F870/871
5.0
TIMER0 MODULE
Counter mode is selected by setting bit T0CS
(OPTION_REG). In Counter mode, Timer0 will
increment either on every rising, or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Additional information on the Timer0 module is available in the PIC® Mid-Range MCU Family Reference
Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON). The interrupt can be masked by
clearing bit T0IE (INTCON). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKO (= FOSC/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 Reg
T0SE
T0CS
Set Flag Bit T0IF
on Overflow
PSA
PRESCALER
0
Watchdog
Timer
1
M
U
X
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG).
2000-2013 Microchip Technology Inc.
DS30569C-page 45
PIC16F870/871
5.2
Using Timer0 with an External
Clock
5.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 5-1).
The PSA and PS2:PS0 bits (OPTION_REG)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
Note:
REGISTER 5-1:
Prescaler
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the
prescaler count, but will not change the
prescaler assignment.
OPTION_REG REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU
bit 6
INTEDG
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
Note:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
To avoid an unintended device RESET, the instruction sequence shown in the PIC® Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0
to the WDT. This sequence must be followed even if the WDT is disabled.
DS30569C-page 46
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 5-1:
Address
01h,101h
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
0Bh,8Bh,
INTCON
10Bh,18Bh
81h,181h
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 Module’s Register
GIE
PEIE
T0IE
Value on:
POR, BOR
Value on
all other
RESETS
xxxx xxxx uuuu uuuu
INTE RBIE
OPTION_REG RBPU INTEDG T0CS T0SE
PSA
T0IF
INTF
RBIF 0000 000x 0000 000u
PS2
PS1
PS0
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by Timer0.
2000-2013 Microchip Technology Inc.
DS30569C-page 47
PIC16F870/871
NOTES:
DS30569C-page 48
2000-2013 Microchip Technology Inc.
PIC16F870/871
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit, TMR1IF (PIR1). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1).
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON).
REGISTER 6-1:
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 8.0). Register 6-1 shows the Timer1
control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC value is
ignored, and these pins read as ‘0’.
Additional information on timer modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
U-0
—
—
R/W-0
R/W-0
T1CKPS1 T1CKPS0
R/W-0
T1OSCEN
R/W-0
R/W-0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
R/W-0
T1SYNC TMR1CS TMR1ON
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 49
PIC16F870/871
6.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON), has no effect, since the internal clock is
always in sync.
FIGURE 6-1:
6.2
Timer1 Counter Operation
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
TIMER1 INCREMENTING EDGE
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI, when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN
is cleared.
FIGURE 6-2:
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
0
TMR1
TMR1H
Synchronized
Clock Input
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS1:T1CKPS0
Q Clock
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS30569C-page 50
2000-2013 Microchip Technology Inc.
PIC16F870/871
6.4
Timer1 Operation in
Asynchronous Counter Mode
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
If control bit T1SYNC (T1CON) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt-on-overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer
(Section 6.4.1).
Osc Type
In Asynchronous Counter mode, Timer1 cannot be
used as a time base for capture or compare operations.
32.768 kHz
Epson C-001R32.768K-A
± 20 PPM
100 kHz
Epson C-2 100.00 KC-P
± 20 PPM
200 kHz
STD XTL 200.000 kHz
± 20 PPM
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PIC® Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in
Asynchronous mode.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON). The oscillator is a low power oscillator, rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
LP
Freq.
C1
C2
32 kHz
33 pF
33 pF
100 kHz
15 pF
15 pF
200 kHz
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
Note 1:
2:
6.6
Higher capacitance increases the stability
of oscillator, but also increases the start-up
time.
Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for
appropriate values of external components.
Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPRH:CCPRL register
pair effectively becomes the period register for Timer1.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
2000-2013 Microchip Technology Inc.
DS30569C-page 51
PIC16F870/871
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 special
event trigger.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
Address
Name
0Bh,8Bh,
INTCON
10Bh, 18Bh
0Ch
DS30569C-page 52
—
—
TMR1IF 0000 -000 0000 -000
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
2000-2013 Microchip Technology Inc.
PIC16F870/871
7.0
TIMER2 MODULE
Register 7-1 shows the Timer2 control register.
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
RESET.
Additional information on timer modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
FIGURE 7-1:
The input clock (FOSC/4) has a prescale option of 1:1,
1:4,
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON).
Sets Flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
Output(1)
RESET
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
Postscaler
1:1 to 1:16
EQ
4
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF (PIR1)).
TMR2 Reg
Prescaler
1:1, 1:4, 1:16
2
Comparator
PR2 Reg
FOSC/4
T2CKPS1:
T2CKPS0
T2OUTPS3:
T2OUTPS0
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON), to minimize power consumption.
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 53
PIC16F870/871
7.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
Reset, or BOR)
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
TMR2 is not cleared when T2CON is written.
TABLE 7-1:
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name
0Bh,8Bh, INTCON
10Bh,18Bh
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF 0000 -000 0000 -000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE 0000 -000 0000 -000
11h
TMR2
Timer2 Module’s Register
12h
T2CON
92h
PR2
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569C-page 54
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
1111 1111 1111 1111
2000-2013 Microchip Technology Inc.
PIC16F870/871
8.0
CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
Additional information on CCP modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023) and in application note AN594, “Using the
CCP Modules” (DS00594).
TABLE 8-1:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Table 8-1 shows the resources and interactions of the
CCP module. In the following sections, the operation of
a CCP module is described.
8.1
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
REGISTER 8-1:
CCP1CON REGISTER REGISTER (ADDRESS: 17h/1Dh)
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3
R/W-0
R/W-0
CCP1M2 CCP1M1
R/W-0
CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M3:CCP1M0: CCP1 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected);
CCP1resets TMR1, and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 55
PIC16F870/871
8.2
8.2.2
Capture Mode
TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the
following:
Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
•
•
•
•
8.2.3
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
The type of event is configured by control bits
CCP1M3:CCP1M0 (CCP1CON). When a capture is made, the interrupt request flag bit CCP1IF
(PIR1) is set. The interrupt flag must be cleared in
software. If another capture occurs before the value in
register CCPR1 is read, the old captured value is
overwritten by the new value.
8.2.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC bit.
Note:
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
FIGURE 8-1:
RC2/CCP1
pin
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
1, 4, 16
Set Flag bit CCP1IF
(PIR1)
CCPR1H
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in Operating mode.
8.2.4
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
CLRF
MOVLW
CCPR1L
Capture
Enable
TMR1H
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
MOVWF
and
Edge Detect
SOFTWARE INTERRUPT
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
; Turn CCP module off
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; move value and CCP ON
CCP1CON
; Load CCP1CON with this
; value
TMR1L
CCP1CON
Qs
DS30569C-page 56
2000-2013 Microchip Technology Inc.
PIC16F870/871
8.3
8.3.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1),
and set bit GO/DONE (ADCON0).
Special Event Trigger
RC2/CCP1
pin
CCPR1H CCPR1L
S
R
TRISC
Output Enable
8.3.1
Output
Logic
Match
CCP1CON
Mode Select
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
8.3.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair, and starts an A/D conversion (if A/D
module is enabled). This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Note:
Set Flag bit CCP1IF
(PIR1)
Q
Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.3.3
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON). At the
same time, interrupt flag bit CCP1IF is set.
TIMER1 MODE SELECTION
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Comparator
TMR1H
TMR1L
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
2000-2013 Microchip Technology Inc.
DS30569C-page 57
PIC16F870/871
8.4
8.4.1
PWM Mode (PWM)
In Pulse Width Modulation mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC bit must be cleared to make the CCP1 pin
an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.4.3.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON
CCPR1L
8.4.2
CCPR1H (Slave)
RC2/CCP1
R
Comparator
TMR2
Q
(Note 1)
S
TRISC
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1:
The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time
base.
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4:
PWM OUTPUT
Period
PWM PERIOD
The Timer2 postscaler (see Section 7.1) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitch-free PWM operation.
When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
Resolution
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
Note:
=
(
FOSC
log FPWM
log(2)
)
bits
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = PR2
DS30569C-page 58
2000-2013 Microchip Technology Inc.
PIC16F870/871
8.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
TABLE 8-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 8-3:
4.88 kHz
19.53 kHz
78.12kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFFh
0xFFh
0xFFh
0x3Fh
0x1Fh
0x17h
10
10
10
8
7
6.5
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
0Bh,8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
TMR2IF
Address
0Ch
PIR1
PSPIF(1) ADIF
RCIF
TXIF
—
CCP1IF
8Ch
PIE1
PSPIE(1) ADIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
17h
CCP1CON
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
The PSP is not implemented on the PIC16F870; always maintain these bits clear.
—
—
—
—
2000-2013 Microchip Technology Inc.
TMR1IF 0000 -000 0000 -000
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP1Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
DS30569C-page 59
PIC16F870/871
TABLE 8-4:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
0Bh,8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF 0000 -000 0000 -000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE 0000 -000 0000 -000
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 Module’s Register
0000 0000 0000 0000
92h
PR2
Timer2 Module’s Period Register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1 CCP1M0 --00 0000 --00 0000
17h
CCP1CON
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569C-page 60
2000-2013 Microchip Technology Inc.
PIC16F870/871
9.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous - Master (half-duplex)
• Synchronous - Slave (half-duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured
as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A
integrated circuits, serial EEPROMs, etc.
REGISTER 9-1:
Bit SPEN (RCSTA) and bits TRISC have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT
as
the
Universal
Synchronous
Asynchronous Receiver Transmitter.
The USART module also has a multi-processor
communication capability using 9-bit address
detection.
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as '0'
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of Transmit Data, can be parity bit
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 61
PIC16F870/871
REGISTER 9-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when
RSR is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware)
Legend:
DS30569C-page 62
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2000-2013 Microchip Technology Inc.
PIC16F870/871
9.1
USART Baud Rate Generator
(BRG)
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 9-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
9.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 9-1. From this, the error in
baud rate can be determined.
TABLE 9-1:
SAMPLING
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
N/A
Legend:
X = value in SPBRG (0 to 255)
TABLE 9-2:
Address
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
18h
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
99h
SPBRG
0000 0000
0000 0000
Legend:
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Baud Rate Generator Register
2000-2013 Microchip Technology Inc.
DS30569C-page 63
PIC16F870/871
TABLE 9-3:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
BAUD
RATE
(K)
KBAUD
%
ERROR
FOSC = 16 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
FOSC = 10 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
-
-
-
-
-
-
-
-
-
1.2
1.221
1.75
255
1.202
0.17
207
1.202
0.17
129
2.4
2.404
0.17
129
2.404
0.17
103
2.404
0.17
64
9.6
9.766
1.73
31
9.615
0.16
25
9.766
1.73
15
19.2
19.531
1.72
15
19.231
0.16
12
19.531
1.72
7
28.8
31.250
8.51
9
27.778
3.55
8
31.250
8.51
4
33.6
34.722
3.34
8
35.714
6.29
6
31.250
6.99
4
57.6
62.500
8.51
4
62.500
8.51
3
52.083
9.58
2
HIGH
1.221
-
255
0.977
-
255
0.610
-
255
LOW
312.500
-
0
250.000
-
0
156.250
-
0
FOSC = 4 MHz
BAUD
RATE
(K)
KBAUD
FOSC = 3.6864 MHz
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
0.300
0
207
0.3
0
191
1.2
1.202
0.17
51
1.2
0
47
2.4
2.404
0.17
25
2.4
0
23
9.6
8.929
6.99
6
9.6
0
5
19.2
20.833
8.51
2
19.2
0
2
28.8
31.250
8.51
1
28.8
0
1
33.6
-
-
-
-
-
-
57.6
62.500
8.51
0
57.6
0
0
HIGH
0.244
-
255
0.225
-
255
LOW
62.500
-
0
57.6
-
0
DS30569C-page 64
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 9-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
FOSC = 16 MHz
BAUD
RATE
(K)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
-
-
1.2
-
-
2.4
-
FOSC = 10 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
-
-
-
-
-
-
-
-
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
-
-
-
-
-
-
-
-
-
2.441
1.71
255
9.6
9.615
0.16
129
9.615
0.16
103
9.615
0.16
64
19.2
19.231
0.16
64
19.231
0.16
51
19.531
1.72
31
28.8
29.070
0.94
42
29.412
2.13
33
28.409
1.36
21
33.6
33.784
0.55
36
33.333
0.79
29
32.895
2.10
18
57.6
59.524
3.34
20
58.824
2.13
16
56.818
1.36
10
HIGH
4.883
-
255
3.906
-
255
2.441
-
255
LOW
1250.000
-
0
1000.000
0
625.000
-
0
FOSC = 4 MHz
BAUD
RATE
(K)
KBAUD
FOSC = 3.6864 MHz
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
-
-
-
-
-
-
1.2
1.202
0.17
207
1.2
0
191
2.4
2.404
0.17
103
2.4
0
95
9.6
9.615
0.16
25
9.6
0
23
19.2
19.231
0.16
12
19.2
0
11
28.8
27.798
3.55
8
28.8
0
7
33.6
35.714
6.29
6
32.9
2.04
6
57.6
62.500
8.51
3
57.6
0
3
HIGH
0.977
-
255
0.9
-
255
LOW
250.000
-
0
230.4
-
0
2000-2013 Microchip Technology Inc.
DS30569C-page 65
PIC16F870/871
9.2
USART Asynchronous Mode
enabled/disabled by setting/clearing enable bit TXIE
( PIE1). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA),
shows the status of the TSR register. Status bit TRMT
is a read only bit, which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR
register is empty.
In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and
receives the LSb first. The transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA).
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 9-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 9-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
The USART Asynchronous module consists of the
following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
9.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 9-1. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1) is set. This interrupt can be
FIGURE 9-1:
In order to select 9-bit transmission, transmit bit TX9
(TXSTA) should be set and the ninth bit should be
written to TX9D (TXSTA). The ninth bit must be
written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS30569C-page 66
2000-2013 Microchip Technology Inc.
PIC16F870/871
When setting up an Asynchronous Transmission,
follow these steps:
5.
1.
6.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 9.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
2.
3.
4.
FIGURE 9-2:
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
7.
8.
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 9-3:
Bit 7/8
STOP Bit
Word 1
Transmit Shift Reg
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Bit 7/8
Word 1
Transmit Shift Reg.
STOP Bit START Bit
Word 2
Bit 0
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
TABLE 9-5:
Address
Bit 1
Word 1
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0Ch
PIR1
18h
RCSTA
19h
TXREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
USART Transmit Register
0000 0000
0000 0000
PSPIE(1)
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
2000-2013 Microchip Technology Inc.
DS30569C-page 67
PIC16F870/871
9.2.2
USART ASYNCHRONOUS
RECEIVER
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA) will be
set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register in
order not to lose the old FERR and RX9D information.
The receiver block diagram is shown in Figure 9-4. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter, operating at x16 times the baud
rate; whereas, the main receive serial shifter operates
at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA).
The heart of the receiver is the Receive (Serial) Shift
register (RSR). After sampling the STOP bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
FIGURE 9-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
OERR
FERR
CREN
FOSC
SPBRG
Baud Rate Generator
64
or
16
RSR Register
MSb
STOP (8)
7
1
LSb
0 START
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
Interrupt
RCREG Register
8
RCIF
Data Bus
RCIE
FIGURE 9-5:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
FIFO
ASYNCHRONOUS RECEPTION
START
bit
bit0
bit1
bit7/8 STOP
bit
START
bit
bit0
Word 1
RCREG
bit7/8 STOP
bit
START
bit
bit7/8
STOP
bit
Word 2
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS30569C-page 68
2000-2013 Microchip Technology Inc.
PIC16F870/871
When setting up an Asynchronous Reception, follow
these steps:
1.
2.
3.
4.
5.
6.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 9.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
TABLE 9-6:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
—
-000 0000
-000 0000
SPEN
RX9
SREN
CREN
—
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 -000
0000 -000
0000 -010
0000 -010
0000 0000
0000 0000
18h
RCSTA
1Ah
RCREG USART Receive Register
8Ch
PIE1
98h
TXSTA
PSPIE(1)
ADIE
RCIE
TXIE
—
CSRC
TX9
TXEN
SYNC
—
Baud Rate Generator Register
CCP1IF TMR2IF TMR1IF
FERR
OERR
RX9D
CCP1IE TMR2IE TMR1IE
BRGH
TRMT
TX9D
99h
SPBRG
Legend:
Note 1:
x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
2000-2013 Microchip Technology Inc.
DS30569C-page 69
PIC16F870/871
9.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
When setting up an Asynchronous Reception with
Address Detect enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired, set
bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 9-6:
• Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable
bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer, and interrupt the
CPU.
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
64
Baud Rate Generator
RSR Register
MSb
or
16
STOP (8)
7
1
LSb
0 START
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
ADDEN
Enable
Load of
RX9
ADDEN
RSR
Receive
Buffer
8
RX9D
RCREG Register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
DS30569C-page 70
2000-2013 Microchip Technology Inc.
PIC16F870/871
FIGURE 9-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START
bit
bit0
RC7/RX/DT (pin)
bit1
bit8
STOP
bit
START
bit
bit0
bit8
STOP
bit
Load RSR
Bit8 = 0, Data Byte
Word 1
RCREG
Bit8 = 1, Address Byte
Read
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN = 1.
FIGURE 9-8:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START
bit
bit0
RC7/RX/DT (pin)
bit1
bit8
STOP
bit
START
bit
bit0
bit8
STOP
bit
Load RSR
Bit8 = 1, Address Byte
Word 1
RCREG
Bit8 = 0, Data Byte
Read
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
because ADDEN was not updated and still = 0.
TABLE 9-7:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
8Ch
PIE1
98h
TXSTA
99h
Legend:
Note 1:
SPBRG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000
0000 -000
SPEN
RX9
SREN
CREN ADDEN
FERR
OERR
RX9D
USART Receive Register
PSPIE(1)
ADIE
RCIE
TXIE
—
CSRC
TX9
TXEN
SYNC
—
Baud Rate Generator Register
0000 000x
0000 000x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 -000
BRGH
TRMT
TX9D
0000 -000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
2000-2013 Microchip Technology Inc.
DS30569C-page 71
PIC16F870/871
9.3
USART Synchronous
Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA). In
addition, enable bit SPEN (RCSTA) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA).
9.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hiimpedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from HiImpedance Receive mode to transmit and start driving.
To avoid this, bit TXEN should be cleared.
The USART transmitter block diagram is shown in
Figure 9-6. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
In order to select 9-bit transmission, the TX9
(TXSTA) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock
(Figure 9-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 9-10). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally, when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
8.
DS30569C-page 72
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 9.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 9-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
SPEN
RX9
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
18h
RCSTA
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
SPBRG
Legend:
Note 1:
CCP1IE TMR2IE TMR1IE
BRGH
TRMT
TX9D
Baud Rate Generator Register
0000 0000
0000 0000
0000 -000
0000 -000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
FIGURE 9-9:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin
bit 0
bit 1
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit 2
bit 7
bit 0
bit 1
bit 7
Word 2
Word 1
RC6/TX/CK pin
Write to
TXREG reg
Write Word1
TXIF bit
(Interrupt Flag)
Write Word2
TRMT bit
'1'
TXEN bit
'1'
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 9-10:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
2000-2013 Microchip Technology Inc.
DS30569C-page 73
PIC16F870/871
9.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA), or enable bit CREN (RCSTA). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read only bit, which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double-buffered register (i.e., it is a twodeep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG, in
order not to lose the old RX9D information.
DS30569C-page 74
When setting up a Synchronous Master Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 9.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 9-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
SPEN
RX9
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
USART Receive Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
SPBRG
Legend:
Note 1:
CCP1IE TMR2IE TMR1IE
BRGH
TRMT
TX9D
Baud Rate Generator Register
0000 0000
0000 0000
0000 -000
0000 -000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
FIGURE 9-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
2000-2013 Microchip Technology Inc.
DS30569C-page 75
PIC16F870/871
9.4
USART Synchronous Slave Mode
When setting up a Synchronous Slave Transmission,
follow these steps:
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA).
9.4.1
1.
2.
3.
USART SYNCHRONOUS SLAVE
TRANSMIT
4.
5.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP mode.
6.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
7.
a)
b)
c)
d)
e)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the
interrupt vector (0004h).
TABLE 9-10:
Address
8.
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
—
SPEN
RX9
SREN
CREN
ADDEN
0Ch
PIR1
18h
RCSTA
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
Legend:
Note 1:
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
SPBRG
Baud Rate Generator Register
CCP1IF TMR2IF TMR1IF 0000 -000
FERR
OERR
RX9D
0000 000x
0000 -000
0000 000x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 -000
0000 -000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
DS30569C-page 76
2000-2013 Microchip Technology Inc.
PIC16F870/871
9.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
When setting up a Synchronous Slave Reception,
follow these steps:
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
1.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
2.
3.
4.
5.
6.
7.
8.
9.
TABLE 9-11:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
18h
RCSTA
1Ah
RCREG
USART Receive Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
Legend:
Note 1:
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
SPBRG
TMR1IF 0000 -000 0000 -000
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
Baud Rate Generator Register
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear.
2000-2013 Microchip Technology Inc.
DS30569C-page 77
PIC16F870/871
NOTES:
DS30569C-page 78
2000-2013 Microchip Technology Inc.
PIC16F870/871
10.0
ANALOG-TO-DIGITAL (A/D)
CONVERTER MODULE
The A/D module has four registers. These registers
are:
The Analog-to-Digital (A/D) Converter module has five
inputs for the 28-pin devices and eight for the other
devices.
The analog input charges a sample and hold capacitor.
The output of the sample and hold capacitor is the input
into the converter. The converter then generates a digital result of this analog level via successive approximation. The A/D conversion of the analog input signal
results in a corresponding 10-bit digital number. The
A/D module has high and low voltage reference input
that is software selectable to some combination of VDD,
VSS, RA2, or RA3.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D clock must be derived from the
A/D’s internal RC oscillator.
REGISTER 10-1:
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register0 (ADCON0)
A/D Control Register1 (ADCON1)
The ADCON0 register, shown in Register 10-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 10-2, configures the functions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage
reference), or as digital I/O.
Additional information on using the A/D module can be
found in the PIC® Mid-Range MCU Family Reference
Manual (DS33023).
ADCON0 REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 0
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits
000 = Channel 0, (RA0/AN0)
010 = Channel 2, (RA2/AN2)
011 = Channel 3, (RA3/AN3)
100 = Channel 4, (RA5/AN4)
101 = Channel 5, (RE0/AN5)(1)
110 = Channel 6, (RE1/AN6)(1)
111 = Channel 7, (RE2/AN7)(1)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
Unimplemented: Read as '0'
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
Note 1: These channels are not available on the PIC16F870 device.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2000-2013 Microchip Technology Inc.
x = Bit is unknown
DS30569C-page 79
PIC16F870/871
REGISTER 10-2:
ADCON1 REGISTER (ADDRESS: 9Fh)
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
bit 6-4
Unimplemented: Read as '0'
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3: AN7(1) AN6(1) AN5(1)
RE2
RE1
RE0
PCFG0
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
VREF+
VREF-
CHAN/
Refs(2)
0000
A
A
A
A
A
A
A
A
VDD
VSS
8/0
0001
A
A
A
A
VREF+
A
A
A
RA3
VSS
7/1
0010
D
D
D
A
A
A
A
A
VDD
VSS
5/0
0011
D
D
D
A
VREF+
A
A
A
RA3
VSS
4/1
0100
D
D
D
D
A
D
A
A
VDD
VSS
3/0
0101
D
D
D
D
VREF+
D
A
A
RA3
VSS
2/1
011x
D
D
D
D
D
D
D
D
VDD
VSS
0/0
1000
A
A
A
A
VREF+
VREF-
A
A
RA3
RA2
6/2
6/0
1001
D
D
A
A
A
A
A
A
VDD
VSS
1010
D
D
A
A
VREF+
A
A
A
RA3
VSS
5/1
1011
D
D
A
A
VREF+
VREF-
A
A
RA3
RA2
4/2
1100
D
D
D
A
VREF+
VREF-
A
A
RA3
RA2
3/2
1101
D
D
D
D
VREF+
VREF-
A
A
RA3
RA2
2/2
1110
D
D
D
D
D
D
D
A
VDD
VSS
1/0
1111
D
D
D
D
VREF+
VREF-
D
A
RA3
RA2
1/2
A = Analog input
D = Digital I/O
Note 1: These channels are not available on the PIC16F870 device.
2: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0) is cleared
and the A/D interrupt flag bit ADIF is set. The block
diagram of the A/D module is shown in Figure 10-1.
x = Bit is unknown
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
DS30569C-page 80
2000-2013 Microchip Technology Inc.
PIC16F870/871
These steps should be followed for doing an A/D
Conversion:
1.
2.
3.
4.
Configure the A/D module:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
FIGURE 10-1:
5.
6.
7.
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
(with interrupts enabled); OR
• Waiting for the A/D interrupt
Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
100
RA5/AN4
VAIN
011
(Input Voltage)
RA3/AN3/VREF+
010
RA2/AN2/VREF-
A/D
Converter
001
RA1/AN1
VDD
000
RA0/AN0
VREF+
(Reference
Voltage)
PCFG3:PCFG0
VREF(Reference
Voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on the PIC16F870 device.
2000-2013 Microchip Technology Inc.
DS30569C-page 81
PIC16F870/871
10.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 10-2. The maximum recommended impedance for analog sources is 10 k. As
the impedance is decreased, the acquisition time may
EQUATION 10-1:
TACQ
TC
TACQ
be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time,
Equation 10-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
ACQUISITION TIME
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120 pF (1 k + 7 k + 10 k) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25C)(0.05 s/C)
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 10-2:
ANALOG INPUT MODEL
VDD
RS
VA
ANx
CPIN
5 pF
VT = 0.6V
VT = 0.6V
RIC 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
= 120 pF
I LEAKAGE
± 500 nA
VSS
Legend CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
DS30569C-page 82
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
2000-2013 Microchip Technology Inc.
PIC16F870/871
10.2
Selecting the A/D Conversion
Clock
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12 TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The four possible options for TAD
are:
•
•
•
•
Table 10-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
2 TOSC
8 TOSC
32 TOSC
Internal A/D module RC oscillator (2-6 s)
TABLE 10-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Note 1:
2:
3:
10.3
Maximum Device Frequency
Operation
ADCS1:ADCS0
Max.
2 TOSC
00
1.25 MHz
8 TOSC
01
5 MHz
32 TOSC
10
20 MHz
RC(1, 2, 3)
11
(Note 1)
The RC source has a typical TAD time of 4 s, but can vary between 2-6 s.
When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
For extended voltage devices (LC), please refer to the Electrical Characteristics (Section 14.1 and 14.2).
Configuring Analog Port Pins
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
2000-2013 Microchip Technology Inc.
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to consume current that is out of the device
specifications.
DS30569C-page 83
PIC16F870/871
10.4
A/D Conversions
acquisition is started. After this 2 TAD wait, acquisition
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2 TAD wait is required before the next
FIGURE 10-3:
In Figure 10-3, after the GO bit is set, the first time
segment has a minimum of TCY and a maximum of TAD.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b9
b8
b7
b6
b5
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
10.4.1
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion of
the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D For-
FIGURE 10-4:
mat Select bit (ADFM) controls this justification.
Figure 10-4 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’. When an A/D
result will not overwrite these locations (A/D disable),
these registers may be used as two general purpose
8-bit registers.
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 0
ADFM = 1
7
0
2107
7
0765
0000 00
0000 00
ADRESH
ADRESL
10-bit Result
Right Justified
DS30569C-page 84
0
ADRESH
ADRESL
10-bit Result
Left Justified
2000-2013 Microchip Technology Inc.
PIC16F870/871
10.5
A/D Operation During SLEEP
Turning off the A/D places the A/D module in its lowest
current consumption state.
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
Note:
10.6
Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. All A/D input pins are
configured as analog inputs.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
TABLE 10-2:
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the conversion to occur during SLEEP, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
REGISTERS/BITS ASSOCIATED WITH A/D
Value on
MCLR,
WDT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh,8Bh,
INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF TMR1IF 0000 -000 0000 -000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE TMR1IE 0000 -000 0000 -000
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx uuuu uuuu
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
ADCS0 CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
—
PCFG3
PCFG2
PCFG1
PCFG0
--0- 0000
1Fh
ADCON0
ADCS1
9Fh
ADCON1
ADFM
—
85h
TRISA
—
—
PORTA Data Direction Register
--11 1111 --11 1111
05h
PORTA
—
—
PORTA Data Latch when written: PORTA pins when read
--0x 0000 --0u 0000
89h(1)
TRISE
IBF
OBF
IBOV
PSPMODE
—
09h(1)
PORTE
—
—
—
—
—
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
These registers/bits are not available on the 28-pin devices.
2000-2013 Microchip Technology Inc.
—
PORTE Data Direction bits
RE2
RE1
RE0
--0- 0000
0000 -111 0000 -111
---- -xxx ---- -uuu
DS30569C-page 85
PIC16F870/871
NOTES:
DS30569C-page 86
2000-2013 Microchip Technology Inc.
PIC16F870/871
11.0
SPECIAL FEATURES OF THE
CPU
The PIC16F870/871 devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
Power Saving Operating modes and offer code
protection. These are:
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
• Low Voltage In-Circuit Serial Programming
• In-Circuit Debugger
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up, or through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits is used to
select various options.
Additional information on special features is available
in the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
11.1
Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. The erased, or unprogrammed
value of the configuration word is 3FFFh. These bits
are mapped in program memory location 2007h.
It is important to note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
PIC16F870/871 devices have a Watchdog Timer,
which can be shut-off only through configuration bits. It
runs off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
2000-2013 Microchip Technology Inc.
DS30569C-page 87
PIC16F870/871
REGISTER 11-1:
CP1
CP0
CONFIGURATION WORD (ADDRESS 2007h)(1)
DEBUG
—
WRT CPD LVP
BOREN
CP1
CP0
PWRTEN WDTEN FOSC1 FOSC0
bit 13
bit 0
(2)
bit 13-12,
bit 5-4
CP1:CP0: FLASH Program Memory Code Protection bits
11 = Code protection off
10 = Not supported
01 = Not supported
00 = Code protection on
bit 11
DEBUG: In-Circuit Debugger Mode
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10
Unimplemented: Read as ‘1’
bit 9
WRT: FLASH Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8
CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EEPROM memory code protected
bit 7
LVP: Low Voltage In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6
BOREN: Brown-out Reset Enable bit(3)
1 = BOR enabled
0 = BOR disabled
bit 3
PWRTEN: Power-up Timer Enable bit(3)
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit
PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
DS30569C-page 88
2000-2013 Microchip Technology Inc.
PIC16F870/871
11.2
FIGURE 11-2:
Oscillator Configurations
11.2.1
OSCILLATOR TYPES
The PIC16F870/871 can be operated in four different
Oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these
four modes:
•
•
•
•
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
LP
XT
HS
RC
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
11.2.2
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKI and OSC2/CLKO pins
to establish oscillation (Figure 11-1). The PIC16F870/
871 oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may give a frequency
out of the crystal manufacturers specifications. When in
XT, LP or HS modes, the device can have an external
clock source to drive the OSC1/CLKI pin (Figure 11-2).
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
C1(1)
OSC1
XTAL
RF(3)
OSC2
C2(1)
Note 1:
2:
3:
Rs
(2)
PIC16F870/871
OSC2
Open
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
FIGURE 11-1:
OSC1
Clock from
Ext. System
To
Internal
Logic
SLEEP
TABLE 11-1:
CERAMIC RESONATORS
Ranges Tested:
Mode
Freq.
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
These values are for design guidance only.
See notes following Table 11-2.
Resonators Used:
455 kHz
Panasonic EFO-A455K04B
0.3%
2.0 MHz
Murata Erie CSA2.00MG
0.5%
4.0 MHz
Murata Erie CSA4.00MG
0.5%
8.0 MHz
Murata Erie CSA8.00MT
0.5%
16.0 MHz
Murata Erie CSA16.00MX
0.5%
All resonators used did not have built-in capacitors.
PIC16F870/871
See Table 11-1 and Table 11-2 for
recommended values of C1 and C2.
A series resistor (Rs) may be required for
AT strip cut crystals.
RF varies with the crystal chosen.
2000-2013 Microchip Technology Inc.
DS30569C-page 89
PIC16F870/871
TABLE 11-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq.
Cap. Range
C1
Cap. Range
C2
LP
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
XT
HS
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
These values are for design guidance only.
See notes following this table.
11.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used. Figure 11-3 shows how the R/C
combination is connected to the PIC16F870/871.
FIGURE 11-3:
RC OSCILLATOR MODE
VDD
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
CEXT
VSS
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the
start-up time.
REXT
OSC1
Internal
Clock
PIC16F870/871
FOSC/4
OSC2/CLKO
Recommended values: 3 k REXT 100 k
CEXT > 20pF
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PIC® devices,
oscillator performance should be verified.
DS30569C-page 90
2000-2013 Microchip Technology Inc.
PIC16F870/871
11.3
RESET
The PIC16F870/871 differentiates between various
kinds of RESET:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Brown-out Reset (BOR)
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
FIGURE 11-4:
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situations, as indicated in Table 11-4. These bits are used in
software to determine the nature of the RESET. See
Table 11-6 for a full description of RESET states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 11-4.
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR
WDT
Module
WDT
SLEEP
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BOREN
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2000-2013 Microchip Technology Inc.
DS30569C-page 91
PIC16F870/871
11.4
Power-on Reset (POR)
11.7
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start-up conditions. For additional information, refer to
Application Note, AN007, “Power-up Trouble Shooting”
(DS00007).
The configuration bit, BOREN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100 S), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72 ms). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR with the
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
11.8
11.5
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an
acceptable level. A configuration bit is provided to
enable/disable the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
11.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a delay of
1024 oscillator cycles (from OSC1 input) after the
PWRT delay is over (if PWRT is enabled). This helps to
ensure that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or Wake-up from
SLEEP.
Brown-out Reset (BOR)
Time-out Sequence
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR Reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F870/871 device operating in
parallel.
Table 11-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 11-6
shows the RESET conditions for all the registers.
11.9
Power Control/Status Register
(PCON)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see if
bit BOR cleared, indicating a BOR occurred. When the
Brown-out Reset is disabled, the state of the BOR bit is
unpredictable and is, therefore, not valid at any time.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
TABLE 11-3:
Oscillator
Configuration
XT, HS, LP
RC
DS30569C-page 92
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Brown-out
Wake-up from SLEEP
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
—
72 ms
—
PWRTEN = 0
PWRTEN = 1
72 ms + 1024 TOSC
72 ms
2000-2013 Microchip Technology Inc.
PIC16F870/871
TABLE 11-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
1
Legend:
x = don’t care, u = unchanged
TABLE 11-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
Condition
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
Legend:
Note 1:
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
u = unchanged, x = unknown, - = unimplemented bit, read as '0'
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 11-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
INDF
TMR0
PIC16F870 PIC16F871
PIC16F870 PIC16F871
PIC16F870 PIC16F871
xxxx xxxx
N/A
xxxx xxxx
uuuu uuuu
N/A
uuuu uuuu
uuuu uuuu
N/A
uuuu uuuu
PCL
PIC16F870 PIC16F871
0000h
0000h
PC + 1(2)
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
PIC16F870
PIC16F870
PIC16F870
PIC16F870
PIC16F870
PIC16F870
PIC16F870
PIC16F870
Register
PIC16F871
PIC16F871
PIC16F871
PIC16F871
PIC16F871
PIC16F871
PIC16F871
PIC16F871
0001
xxxx
--0x
xxxx
xxxx
xxxx
------0
1xxx
xxxx
0000
xxxx
xxxx
xxxx
-xxx
0000
000q
uuuu
--0u
uuuu
uuuu
uuuu
------0
quuu(3)
uuuu
0000
uuuu
uuuu
uuuu
-uuu
0000
uuuq
uuuu
--uu
uuuu
uuuu
uuuu
------u
quuu(3)
uuuu
uuuu
uuuu
uuuu
uuuu
-uuu
uuuu
INTCON
PIC16F870 PIC16F871
0000 000x
0000 000u
uuuu uuuu(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for RESET value for specific condition.
2000-2013 Microchip Technology Inc.
DS30569C-page 93
PIC16F870/871
TABLE 11-6:
Register
PIR1
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
PIC16F871
r000 -000
r000 -000
ruuu -uuu(1)
PIC16F870 PIC16F871
0000 -000
0000 -000
uuuu -uuu(1)
Devices
PIC16F870
Wake-up via WDT or
Interrupt
PIC16F870 PIC16F871
---0 ------0 ------u ----(1)
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
--00 0000
--uu uuuu
--uu uuuu
PIC16F870 PIC16F871
0000 0000
0000 0000
uuuu uuuu
PIC16F870 PIC16F871
-000 0000
-000 0000
-uuu uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
--00 0000
--00 0000
--uu uuuu
PIC16F870 PIC16F871
0000 000x
0000 000x
uuuu uuuu
PIC16F870 PIC16F871
0000 0000
0000 0000
uuuu uuuu
PIC16F870 PIC16F871
0000 0000
0000 0000
uuuu uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
0000 00-0
0000 00-0
uuuu uu-u
PIC16F870 PIC16F871
1111 1111
1111 1111
uuuu uuuu
PIC16F870 PIC16F871
--11 1111
--11 1111
--uu uuuu
PIC16F870 PIC16F871
1111 1111
1111 1111
uuuu uuuu
PIC16F870 PIC16F871
1111 1111
1111 1111
uuuu uuuu
PIC16F870 PIC16F871
1111 1111
1111 1111
uuuu uuuu
PIC16F870 PIC16F871
0000 -111
0000 -111
uuuu -uuu
PIC16F870 PIC16F871
r000 -000
r000 -000
ruuu -uuu
PIC16F870 PIC16F871
0000 0000
0000 0000
uuuu uuuu
PIC16F870 PIC16F871
---0 ------0 ------u ---PIC16F870 PIC16F871
---- --qq
---- --uu
---- --uu
PIC16F870 PIC16F871
1111 1111
1111 1111
1111 1111
PIC16F870 PIC16F871
0000 -010
0000 -010
uuuu -uuu
PIC16F870 PIC16F871
0000 0000
0000 0000
uuuu uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
0--- 0000
0--- 0000
u--- uuuu
PIC16F870 PIC16F871
0--- 0000
0--- 0000
u--- uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIC16F870 PIC16F871
x--- x000
u--- u000
u--- uuuu
PIC16F870 PIC16F871
---- ------- ------- ---u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved, maintain clear
One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
See Table 11-5 for RESET value for specific condition.
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
ADRESH
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
PCON
PR2
TXSTA
SPBRG
ADRESL
ADCON1
EEDATA
EEADR
EEDATH
EEADRH
EECON1
EECON2
Legend:
Note 1:
2:
3:
DS30569C-page 94
2000-2013 Microchip Technology Inc.
PIC16F870/871
FIGURE 11-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 11-6:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 11-7:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
2000-2013 Microchip Technology Inc.
DS30569C-page 95
PIC16F870/871
FIGURE 11-8:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
11.10 Interrupts
The PIC16F870/871 family has up to 14 sources of
interrupt. The Interrupt Control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit, or the GIE bit.
A global interrupt enable bit, GIE (INTCON),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in special
function registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function
register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or GIE bit.
The RB0/INT pin interrupt, the RB port change
interrupt, and the TMR0 overflow interrupt flags are
contained in the INTCON register.
DS30569C-page 96
2000-2013 Microchip Technology Inc.
PIC16F870/871
FIGURE 11-9:
INTERRUPT LOGIC
EEIF
EEIE
PSPIF
PSPIE
ADIF
ADIE
Wake-up (If in SLEEP mode)
T0IF
T0IE
INTF
INTE
RCIF
RCIE
TXIF
TXIE
Interrupt to CPU
RBIF
RBIE
PEIE
CCP1IF
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
The following table shows which devices have which interrupts.
Device
T0IF
INTF
RBIF
PSPIF
ADIF
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
EEIF
PIC18F870
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC18F871
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
11.10.1
INT INTERRUPT
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.13 for details on SLEEP
mode.
2000-2013 Microchip Technology Inc.
11.10.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit T0IF (INTCON). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON) (Section 5.0).
11.10.3
PORTB INTCON CHANGE
An input change on PORTB sets flag bit RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON)
(Section 4.2).
DS30569C-page 97
PIC16F870/871
11.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
For the PIC16F870/871 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 0x20 in bank 0, it must
also be defined at 0xA0 in bank 1). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
EXAMPLE 11-1:
Since the upper 16 bytes of each bank are common in
the PIC16F870/871 devices, temporary holding registers W_TEMP, STATUS_TEMP, and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for context save and restore. The same code shown in
Example 11-1 can be used.
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Copy
;Swap
;bank
;Save
;Only
;Save
;Page
W to TEMP register
status to be saved into W
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
required if using pages 1, 2 and/or 3
PCLATH into W
zero, regardless of current page
;(Insert user code here)
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
DS30569C-page 98
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
2000-2013 Microchip Technology Inc.
PIC16F870/871
11.12 Watchdog Timer (WDT)
WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO
pins of the device has been stopped, for example, by
execution of a SLEEP instruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation
(Watchdog Timer Wake-up). The TO bit in the STATUS
register will be cleared upon a Watchdog Timer
time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTEN (Section 11.1).
FIGURE 11-10:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
WDT Timer
1
Postscaler
M
U
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 11-7:
Address
2007h
81h,181h
Legend:
Note 1:
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Config. bits
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
(1)
BOREN(1)
CP1
CP0
RBPU
INTEDG
T0CS
T0SE
Bit 3
Bit 2
PWRTEN(1) WDTEN
PSA
PS2
Bit 1
Bit 0
FOSC1
FOSC0
PS1
PS0
Shaded cells are not used by the Watchdog Timer.
See Register 11-1 for operation of these bits.
2000-2013 Microchip Technology Inc.
DS30569C-page 99
PIC16F870/871
11.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS) is cleared, the
TO (STATUS) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (VIHMC).
11.13.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or
peripheral interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
11.13.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
8.
9.
PSP read or write (PIC16F874/877 only).
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
SSP (START/STOP) bit detect interrupt.
SSP transmit or receive in Slave mode
(SPI/I2C).
USART RX or TX (Synchronous Slave mode).
A/D conversion (when A/D clock source is RC).
EEPROM write operation completion
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
DS30569C-page 100
2000-2013 Microchip Technology Inc.
PIC16F870/871
FIGURE 11-11:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKO(4)
INT pin
INTF Flag
(INTCON)
Interrupt Latency(2)
GIE bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
2:
3:
4:
PC
PC+1
Inst(PC) = SLEEP
Inst(PC - 1)
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Osc mode.
GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
CLKO is not available in these Osc modes, but shown here for timing reference.
11.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is programmed to a '0', the In-Circuit Debugger functionality
is enabled. This function allows simple debugging functions when used with MPLAB® ICD. When the microcontroller has this feature enabled, some of the
resources are not available for general use. Table 11-8
shows which features are consumed by the
background debugger.
TABLE 11-8:
DEBUGGER RESOURCES
I/O pins
RB6, RB7
Stack
1 level
Program Memory
Address 0000h must be NOP
11.15 Program Verification/Code
Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 Least Significant bits of the ID
location are used.
Last 100h words
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.
2000-2013 Microchip Technology Inc.
DS30569C-page 101
PIC16F870/871
11.17
In-Circuit Serial Programming
PIC16F870/871 microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom
firmware to be programmed.
When using ICSP, the part must be supplied at 4.5V to
5.5V, if a bulk erase will be executed. This includes
reprogramming of the code protect, both from an onstate to off-state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This means calibration values, unique user IDs, or user
code can be reprogrammed or added.
For complete details of serial programming, please
refer to the EEPROM Memory Programming
Specification for the PIC16F87X (DS39025).
11.18 Low Voltage ICSP Programming
The LVP bit of the configuration word enables low voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP, using a VDD
source in the operating voltage range. This only means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter Programming mode, VDD must be applied
to the RB3/PGM pin, provided the LVP bit is set. The
LVP bit defaults to on (‘1’) from the factory.
Note 1: The High Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low Voltage ICSP mode, the
RB3 pin can no longer be used as a
general purpose I/O pin.
3: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
4: RB3 should not be allowed to float if LVP
is enabled. An external pull-down device
should be used to default the device to
normal Operating mode. If RB3 floats
high, the PIC16F870/871 devices will
enter Programming mode.
5: LVP mode is enabled by default on all
devices shipped from Microchip. It can be
disabled by clearing the LVP bit in the
CONFIG register.
6: Disabling LVP will provide maximum
compatibility to other PIC16CXXX
devices.
If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to 0, only the High Voltage Programming mode is available and only High Voltage Programming mode can be
used to program the device.
When using low voltage ICSP, the part must be supplied
at 4.5V to 5.5V, if a bulk erase will be executed. This
includes reprogramming of the code protect bits from an
on-state to off-state. For all other cases of low voltage
ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique
user IDs, or user code can be reprogrammed or added.
DS30569C-page 102
2000-2013 Microchip Technology Inc.
PIC16F870/871
12.0
INSTRUCTION SET SUMMARY
Each PIC16F870/871 instruction is a 14-bit word,
divided into an OPCODE, which specifies the instruction type, and one or more operands, which further
specify the operation of the instruction. The
PIC16F870/871 instruction set summary in Table 12-2
lists byte-oriented, bit-oriented, and literal and control operations. Table 12-1 shows the opcode field
descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the address of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 12-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles,
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 s. If a conditional test is true, or the
program counter is changed as a result of an
instruction, the instruction execution time is 2 s.
Table 12-2 lists the instructions recognized by the
MPASMTM assembler.
Figure 12-1 shows the general formats that the
instructions can have.
Note:
To maintain upward compatibility with
future PIC16F870/871 products, do not
use the OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 12-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
0
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
A description of each instruction is available in the PIC®
Mid-Range MCU Family Reference Manual (DS33023).
2000-2013 Microchip Technology Inc.
DS30569C-page 103
PIC16F870/871
TABLE 12-2:
PIC16F870/871 INSTRUCTION SET
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1:
2:
3:
Note:
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Additional information on the mid-range instruction set is available in the PIC® Mid-Range MCU Family Reference Manual (DS33023).
DS30569C-page 104
2000-2013 Microchip Technology Inc.
PIC16F870/871
12.1
Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] BCF
Operands:
0 k 255
Operands:
0 f 127
0b7
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Operation:
0 (f)
Description:
The contents of the W register
are added to the eight-bit literal 'k'
and the result is placed in the W
register.
Status Affected:
None
Description:
Bit 'b' in register 'f' is cleared.
ADDWF
Add W and f
BSF
Bit Set f
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BSF
Operands:
0 f 127
d
Operands:
0 f 127
0b7
Operation:
(W) + (f) (destination)
Operation:
1 (f)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0, the result
is stored in the W register. If 'd' is
1, the result is stored back in
register 'f'.
Description:
Bit 'b' in register 'f' is set.
ANDLW
AND Literal with W
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BTFSS f,b
Operands:
0 k 255
Operands:
Operation:
(W) .AND. (k) (W)
0 f 127
0b
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