PIC16F87XA
28/40/44-Pin Enhanced Flash Microcontrollers
Devices Included in this Data Sheet:
• PIC16F873A
• PIC16F874A
Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital
Converter (A/D)
• Brown-out Reset (BOR)
• Analog Comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs are externally accessible
• PIC16F876A
• PIC16F877A
High-Performance RISC CPU:
• Only 35 single-word instructions to learn
• All single-cycle instructions except for program
branches, which are two-cycle
• Operating speed: DC – 20 MHz clock input
DC – 200 ns instruction cycle
• Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
• Pinout compatible to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers
Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Data EEPROM Retention > 40 years
• Self-reprogrammable under software control
• In-Circuit Serial Programming™ (ICSP™)
via two pins
• Single-supply 5V In-Circuit Serial Programming
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options
• In-Circuit Debug (ICD) via two pins
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during Sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• Synchronous Serial Port (SSP) with SPI
(Master mode) and I2C™(Master/Slave)
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
• Parallel Slave Port (PSP) – 8 bits wide with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
CMOS Technology:
• Low-power, high-speed Flash/EEPROM
technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
Program Memory
Device
MSSP
Data
EEPROM
10-bit
CCP
Timers
SRAM
I/O
USART
Comparators
# Single Word
(Bytes)
A/D (ch) (PWM) SPI Master
8/16-bit
Bytes
(Bytes)
2
Instructions
I C
PIC16F873A
7.2K
4096
192
128
22
5
2
Yes
Yes
Yes
2/1
2
PIC16F874A
7.2K
4096
192
128
33
8
2
Yes
Yes
Yes
2/1
2
PIC16F876A 14.3K
8192
368
256
22
5
2
Yes
Yes
Yes
2/1
2
PIC16F877A 14.3K
8192
368
256
33
8
2
Yes
Yes
Yes
2/1
2
2001-2013 Microchip Technology Inc.
DS39582C-page 1
PIC16F87XA
Pin Diagrams
28-Pin PDIP, SOIC, SSOP
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RA1/AN1
RA0/AN0
MCLR/VPP
RB7/PGD
RB6/PGC
RB5
RB4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIC16F873A/876A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
28
27
26
25
24
23
22
28-Pin QFN
1
2
3
4
5
6
7
PIC16F873A
PIC16F876A
21
20
19
18
17
16
15
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
PIC16F874A
PIC16F877A
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2/CLKO
OSC1/CLKI
VSS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
RB3/PGM
NC
RB4
RB5
RB6/PGC
RB7/PGD
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
VDD
RB0/INT
RB1
RB2
44
43
42
41
40
39
38
37
36
35
34
44-Pin QFN
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
8
9
10
11
12
13
14
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO
DS39582C-page 2
2001-2013 Microchip Technology Inc.
PIC16F87XA
Pin Diagrams (Continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7/PGD
RB6/PGC
RB5
RB4
NC
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
PIC16F874A/877A
40-Pin PDIP
PIC16F874A
PIC16F877A
39
38
37
36
35
34
33
32
31
30
9
18
19
20
21
22
23
24
25
26
27
282
7
8
9
10
11
12
13
14
15
16
17
RB3/PGM
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CK1
NC
6
5
4
3
2
1
44
43
42
41
40
44-Pin PLCC
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP
PIC16F874A
PIC16F877A
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
OSC2/CLKO
OSC1/CLKI
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/C2OUT
RA4/T0CKI/C1OUT
NC
NC
RB4
RB5
RB6/PGC
RB7/PGD
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3/PGM
2001-2013 Microchip Technology Inc.
DS39582C-page 3
PIC16F87XA
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................ 15
3.0 Data EEPROM and Flash Program Memory ............................................................................................................................ 33
4.0 I/O Ports.................................................................................................................................................................................... 41
5.0 Timer0 Module .......................................................................................................................................................................... 53
6.0 Timer1 Module .......................................................................................................................................................................... 57
7.0 Timer2 Module .......................................................................................................................................................................... 61
8.0 Capture/Compare/PWM Modules ............................................................................................................................................. 63
9.0 Master Synchronous Serial Port (MSSP) Module..................................................................................................................... 71
10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................ 111
11.0 Analog-to-Digital Converter (A/D) Module .............................................................................................................................. 127
12.0 Comparator Module ................................................................................................................................................................ 135
13.0 Comparator Voltage Reference Module ................................................................................................................................. 141
14.0 Special Features of the CPU .................................................................................................................................................. 143
15.0 Instruction Set Summary......................................................................................................................................................... 159
16.0 Development Support ............................................................................................................................................................. 167
17.0 Electrical Characteristics......................................................................................................................................................... 173
18.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 197
19.0 Packaging Information ............................................................................................................................................................ 209
Appendix A: Revision History ............................................................................................................................................................ 219
Appendix B: Device Differences........................................................................................................................................................ 219
Appendix C: Conversion Considerations........................................................................................................................................... 220
Index ................................................................................................................................................................................................. 221
On-Line Support................................................................................................................................................................................ 229
Systems Information and Upgrade Hot Line ..................................................................................................................................... 229
Reader Response ............................................................................................................................................................................. 230
PIC16F87XA Product Identification System...................................................................................................................................... 231
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS39582C-page 4
2001-2013 Microchip Technology Inc.
PIC16F87XA
1.0
DEVICE OVERVIEW
This document contains device specific information
about the following devices:
•
•
•
•
PIC16F873A
PIC16F874A
PIC16F876A
PIC16F877A
PIC16F873A/876A devices are available only in 28-pin
packages, while PIC16F874A/877A devices are available in 40-pin and 44-pin packages. All devices in the
PIC16F87XA family share common architecture with
the following differences:
The available features are summarized in Table 1-1.
Block diagrams of the PIC16F873A/876A and
PIC16F874A/877A devices are provided in Figure 1-1
and Figure 1-2, respectively. The pinouts for these
device families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the PIC® MidRange Reference Manual (DS33023), which may be
obtained from your local Microchip Sales Representative
or downloaded from the Microchip web site. The Reference Manual should be considered a complementary
document to this data sheet and is highly recommended
reading for a better understanding of the device architecture and operation of the peripheral modules.
• The PIC16F873A and PIC16F874A have one-half
of the total on-chip memory of the PIC16F876A
and PIC16F877A
• The 28-pin devices have three I/O ports, while the
40/44-pin devices have five
• The 28-pin devices have fourteen interrupts, while
the 40/44-pin devices have fifteen
• The 28-pin devices have five A/D input channels,
while the 40/44-pin devices have eight
• The Parallel Slave Port is implemented only on
the 40/44-pin devices
TABLE 1-1:
PIC16F87XA DEVICE FEATURES
Key Features
PIC16F873A
PIC16F874A
PIC16F876A
PIC16F877A
Operating Frequency
DC – 20 MHz
DC – 20 MHz
DC – 20 MHz
DC – 20 MHz
Resets (and Delays)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
Flash Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
192
192
368
368
EEPROM Data Memory (bytes)
128
128
256
256
Interrupts
14
15
14
15
I/O Ports
Ports A, B, C
Ports A, B, C, D, E
Ports A, B, C
Ports A, B, C, D, E
3
3
3
3
Timers
Capture/Compare/PWM modules
Serial Communications
Parallel Communications
10-bit Analog-to-Digital Module
Analog Comparators
Instruction Set
Packages
2001-2013 Microchip Technology Inc.
2
2
2
2
MSSP, USART
MSSP, USART
MSSP, USART
MSSP, USART
—
PSP
—
PSP
5 input channels
8 input channels
5 input channels
8 input channels
2
2
2
2
35 Instructions
35 Instructions
35 Instructions
35 Instructions
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin PLCC
44-pin TQFP
44-pin QFN
DS39582C-page 5
PIC16F87XA
FIGURE 1-1:
PIC16F873A/876A BLOCK DIAGRAM
13
Flash
Program
Memory
Program
Bus
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RAM
File
Registers
8 Level Stack
(13-bit)
14
8
Data Bus
Program Counter
RAM Addr(1)
9
Addr MUX
Instruction reg
Direct Addr
7
Indirect
Addr
8
PORTB
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
FSR reg
Status reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
In-Circuit
Debugger
MUX
ALU
8
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
W reg
Low-Voltage
Programming
MCLR
VDD, VSS
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1,2
Synchronous
Serial Port
USART
Comparator
Voltage
Reference
Device
Program Flash
Data Memory
Data EEPROM
PIC16F873A
4K words
192 Bytes
128 Bytes
PIC16F876A
8K words
368 Bytes
256 Bytes
Note 1: Higher order bits are from the Status register.
DS39582C-page 6
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 1-2:
PIC16F874A/877A BLOCK DIAGRAM
13
Flash
Program
Memory
Program
Bus
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/C2OUT
RAM
File
Registers
8 Level Stack
(13-bit)
14
8
Data Bus
Program Counter
RAM Addr(1)
PORTB
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
Addr MUX
Instruction reg
Direct Addr
7
Indirect
Addr
8
FSR reg
Status reg
8
PORTC
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MUX
ALU
8
W reg
PORTD
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
In-Circuit
Debugger
Low-Voltage
Programming
PORTE
MCLR
RE0/RD/AN5
VDD, VSS
RE1/WR/AN6
RE2/CS/AN7
Timer0
Timer1
Timer2
10-bit A/D
Data EEPROM
CCP1,2
Synchronous
Serial Port
USART
Parallel
Slave Port
Comparator
Voltage
Reference
Device
Program Flash
Data Memory
Data EEPROM
PIC16F874A
4K words
192 Bytes
128 Bytes
PIC16F877A
8K words
368 Bytes
256 Bytes
Note 1: Higher order bits are from the Status register.
2001-2013 Microchip Technology Inc.
DS39582C-page 7
PIC16F87XA
TABLE 1-2:
PIC16F873A/876A PINOUT DESCRIPTION
Pin Name
OSC1/CLKI
OSC1
PDIP, SOIC,
SSOP Pin#
QFN
Pin#
9
6
I/O/P
Type
I
CLKI
I
OSC2/CLKO
OSC2
10
7
Buffer
Type
ST/CMOS(3) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode; otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
—
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
ST
Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active low Reset
to the device.
Programming voltage input.
O
O
CLKO
MCLR/VPP
MCLR
1
26
I
VPP
Description
P
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
RA1/AN1
RA1
AN1
3
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREFCVREF
4
RA3/AN3/VREF+
RA3
AN3
VREF+
5
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6
RA5/AN4/SS/C2OUT
RA5
AN4
SS
C2OUT
7
Legend:
Note 1:
2:
3:
27
TTL
I/O
I
28
Digital I/O.
Analog input 0.
TTL
I/O
I
1
Digital I/O.
Analog input 1.
TTL
I/O
I
I
O
2
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
TTL
I/O
I
I
3
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
ST
I/O
I
O
4
Digital I/O – Open-drain when configured as output.
Timer0 external clock input.
Comparator 1 output.
TTL
I/O
I
I
O
Digital I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS39582C-page 8
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 1-2:
PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)
Pin Name
PDIP, SOIC,
SSOP Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT
RB0
INT
21
RB1
22
TTL/ST(1)
18
I/O
I
Digital I/O.
External interrupt.
19
I/O
TTL
Digital I/O.
I/O
TTL
Digital I/O.
RB2
23
20
RB3/PGM
RB3
PGM
24
21
TTL
I/O
I
Digital I/O.
Low-voltage (single-supply) ICSP programming enable pin.
RB4
25
22
I/O
TTL
Digital I/O.
RB5
26
23
I/O
TTL
Digital I/O.
RB6/PGC
RB6
PGC
27
24
RB7/PGD
RB7
PGD
28
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12
RC2/CCP1
RC2
CCP1
13
RC3/SCK/SCL
RC3
SCK
SCL
14
RC4/SDI/SDA
RC4
SDI
SDA
15
RC5/SDO
RC5
SDO
16
RC6/TX/CK
RC6
TX
CK
17
RC7/RX/DT
RC7
RX
DT
18
TTL/ST(2)
I/O
I
Digital I/O.
In-circuit debugger and ICSP programming clock.
TTL/ST(2)
25
I/O
I/O
Digital I/O.
In-circuit debugger and ICSP programming data.
PORTC is a bidirectional I/O port.
VSS
VDD
Legend:
Note 1:
2:
3:
8
ST
I/O
O
I
9
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
ST
I/O
I
I/O
10
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
ST
I/O
I/O
11
Digital I/O.
Capture1 input, Compare1 output, PWM1 output.
ST
I/O
I/O
I/O
12
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
ST
I/O
I
I/O
13
Digital I/O.
SPI data in.
I2C data I/O.
ST
I/O
O
14
Digital I/O.
SPI data out.
ST
I/O
O
I/O
15
Digital I/O.
USART asynchronous transmit.
USART1 synchronous clock.
ST
I/O
I
I/O
Digital I/O.
USART asynchronous receive.
USART synchronous data.
8, 19
5, 6
P
—
Ground reference for logic and I/O pins.
20
17
P
—
Positive supply for logic and I/O pins.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc.
DS39582C-page 9
PIC16F87XA
TABLE 1-3:
PIC16F874A/877A PINOUT DESCRIPTION
Pin Name
OSC1/CLKI
OSC1
PDIP
Pin#
13
PLCC TQFP
Pin# Pin#
14
30
QFN
Pin#
I/O/P
Type
32
I
CLKI
I
OSC2/CLKO
OSC2
14
15
31
33
Buffer
Type
ST/CMOS(4) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode;
otherwise CMOS.
External clock source input. Always associated
with pin function OSC1 (see OSC1/CLKI,
OSC2/CLKO pins).
—
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal
Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which
has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
ST
Master Clear (input) or programming voltage (output).
Master Clear (Reset) input. This pin is an active
low Reset to the device.
Programming voltage input.
O
CLKO
O
1
MCLR/VPP
MCLR
2
18
18
I
VPP
Description
P
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
RA1/AN1
RA1
AN1
3
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
4
RA3/AN3/VREF+
RA3
AN3
VREF+
5
RA4/T0CKI/C1OUT
RA4
6
3
19
19
4
20
20
TTL
5
21
21
Digital I/O.
Analog input 1.
TTL
I/O
I
I
O
6
22
22
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
Comparator VREF output.
TTL
I/O
I
I
7
23
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
ST
23
Digital I/O – Open-drain when configured as
output.
Timer0 external clock input.
Comparator 1 output.
I/O
I
O
RA5/AN4/SS/C2OUT
RA5
AN4
SS
C2OUT
Note 1:
2:
3:
Digital I/O.
Analog input 0.
I/O
I
T0CKI
C1OUT
Legend:
TTL
I/O
I
7
8
24
24
TTL
I/O
I
I
O
Digital I/O.
Analog input 4.
SPI slave select input.
Comparator 2 output.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS39582C-page 10
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 1-3:
Pin Name
PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
PDIP
Pin#
PLCC TQFP
Pin# Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
36
8
TTL/ST(1)
9
RB0/INT
RB0
INT
33
RB1
34
37
9
10
I/O
TTL
Digital I/O.
RB2
35
38
10
11
I/O
TTL
Digital I/O.
11
12
I/O
I
RB3/PGM
RB3
PGM
36
RB4
37
41
14
14
I/O
TTL
Digital I/O.
RB5
38
42
15
15
I/O
TTL
Digital I/O.
RB6/PGC
RB6
PGC
39
43
16
16
RB7/PGD
RB7
PGD
40
Legend:
Note 1:
2:
3:
39
Digital I/O.
External interrupt.
TTL
I/O
I
Digital I/O.
Low-voltage ICSP programming enable pin.
TTL/ST(2)
I/O
I
44
17
Digital I/O.
In-circuit debugger and ICSP programming clock.
TTL/ST(2)
17
I/O
I/O
Digital I/O.
In-circuit debugger and ICSP programming data.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc.
DS39582C-page 11
PIC16F87XA
TABLE 1-3:
PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
Pin Name
PDIP
Pin#
PLCC TQFP
Pin# Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16
RC2/CCP1
RC2
CCP1
17
RC3/SCK/SCL
RC3
SCK
18
16
32
34
I/O
O
I
18
35
35
ST
19
36
36
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
ST
I/O
I/O
20
37
37
Digital I/O.
Capture1 input, Compare1 output, PWM1 output.
ST
I/O
I/O
Digital I/O.
Synchronous serial clock input/output for SPI
mode.
Synchronous serial clock input/output for I2C
mode.
I/O
RC4/SDI/SDA
RC4
SDI
SDA
23
RC5/SDO
RC5
SDO
24
RC6/TX/CK
RC6
TX
CK
25
RC7/RX/DT
RC7
RX
DT
26
Note 1:
2:
3:
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
I/O
I
I/O
SCL
Legend:
ST
25
42
42
ST
I/O
I
I/O
26
43
43
Digital I/O.
SPI data in.
I2C data I/O.
ST
I/O
O
27
44
44
Digital I/O.
SPI data out.
ST
I/O
O
I/O
29
1
1
Digital I/O.
USART asynchronous transmit.
USART1 synchronous clock.
ST
I/O
I
I/O
Digital I/O.
USART asynchronous receive.
USART synchronous data.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS39582C-page 12
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 1-3:
Pin Name
PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)
PDIP
Pin#
PLCC TQFP
Pin# Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port or Parallel Slave
Port when interfacing to a microprocessor bus.
RD0/PSP0
RD0
PSP0
19
RD1/PSP1
RD1
PSP1
20
RD2/PSP2
RD2
PSP2
21
RD3/PSP3
RD3
PSP3
22
RD4/PSP4
RD4
PSP4
27
RD5/PSP5
RD5
PSP5
28
RD6/PSP6
RD6
PSP6
29
RD7/PSP7
RD7
PSP7
30
21
38
ST/TTL(3)
38
Digital I/O.
Parallel Slave Port data.
I/O
I/O
22
39
ST/TTL(3)
39
Digital I/O.
Parallel Slave Port data.
I/O
I/O
23
40
ST/TTL(3)
40
Digital I/O.
Parallel Slave Port data.
I/O
I/O
24
41
ST/TTL(3)
41
Digital I/O.
Parallel Slave Port data.
I/O
I/O
30
2
ST/TTL(3)
2
Digital I/O.
Parallel Slave Port data.
I/O
I/O
31
3
ST/TTL(3)
3
Digital I/O.
Parallel Slave Port data.
I/O
I/O
32
4
ST/TTL(3)
4
Digital I/O.
Parallel Slave Port data.
I/O
I/O
33
5
ST/TTL(3)
5
Digital I/O.
Parallel Slave Port data.
I/O
I/O
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8
RE1/WR/AN6
RE1
WR
AN6
9
RE2/CS/AN7
RE2
CS
AN7
10
9
25
ST/TTL(3)
25
I/O
I
I
10
26
Digital I/O.
Read control for Parallel Slave Port.
Analog input 5.
ST/TTL(3)
26
Digital I/O.
Write control for Parallel Slave Port.
Analog input 6.
I/O
I
I
11
27
ST/TTL(3)
27
Digital I/O.
Chip select control for Parallel Slave Port.
Analog input 7.
I/O
I
I
VSS
12, 31 13, 34
6, 29
6, 30,
31
P
—
Ground reference for logic and I/O pins.
VDD
11, 32 12, 35
7, 28
7, 8,
28, 29
P
—
Positive supply for logic and I/O pins.
13
—
—
These pins are not internally connected. These pins
should be left unconnected.
NC
Legend:
Note 1:
2:
3:
—
1, 17, 12,13,
28, 40 33, 34
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc.
DS39582C-page 13
PIC16F87XA
NOTES:
DS39582C-page 14
2001-2013 Microchip Technology Inc.
PIC16F87XA
2.0
MEMORY ORGANIZATION
There are three memory blocks in each of the
PIC16F87XA devices. The program memory and data
memory have separate buses so that concurrent
access can occur and is detailed in this section. The
EEPROM data memory block is detailed in Section 3.0
“Data EEPROM and Flash Program Memory”.
Additional information on device memory may be found
in the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
2.1
Program Memory Organization
The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x 14 bit program
memory space. The PIC16F876A/877A devices have
8K words x 14 bits of Flash program memory, while
PIC16F873A/874A devices have 4K words x 14 bits.
Accessing a location above the physically implemented
address will cause a wraparound.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-2:
FIGURE 2-1:
PIC16F876A/877A
PROGRAM MEMORY MAP
AND STACK
PIC16F873A/874A
PROGRAM MEMORY MAP
AND STACK
PC
PC
13
CALL, RETURN
RETFIE, RETLW
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 1
Stack Level 2
Stack Level 2
Stack Level 8
Stack Level 8
Reset Vector
Interrupt Vector
0000h
Interrupt Vector
0004h
0000h
0005h
0004h
0005h
On-Chip
07FFh
Program
Memory
Page 0
0800h
Page 0
07FFh
0800h
Page 1
0FFFh
Page 1
On-Chip
Program
Memory
Reset Vector
0FFFh
1000h
1000h
Page 2
17FFh
1800h
Page 3
1FFFh
1FFFh
2001-2013 Microchip Technology Inc.
DS39582C-page 15
PIC16F87XA
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (Status) and
RP0 (Status) are the bank select bits.
RP1:RP0
Bank
00
0
01
1
10
2
11
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
Note:
2.2.1
The EEPROM data memory description can
be found in Section 3.0 “Data EEPROM
and Flash Program Memory” of this data
sheet.
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or
indirectly, through the File Select Register (FSR).
DS39582C-page 16
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 2-3:
PIC16F876A/877A REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
Indirect addr.(*)
OPTION_REG
General
Purpose
Register
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(1)
TRISE(1)
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
CMCON
CVRCON
ADRESL
ADCON1
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
General
Purpose
Register
16 Bytes
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)
General
Purpose
Register
16 Bytes
General
Purpose
Register
General
Purpose
Register
80 Bytes
80 Bytes
80 Bytes
7Fh
EFh
F0h
accesses
70h-7Fh
accesses
70h - 7Fh
17Fh
FFh
Bank 1
16Fh
170h
Bank 2
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
accesses
70h-7Fh
*
Note 1:
2:
Indirect addr.(*)
A0h
96 Bytes
Bank 0
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
File
Address
File
Address
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as ‘0’.
Not a physical register.
These registers are not implemented on the PIC16F876A.
These registers are reserved; maintain these registers clear.
2001-2013 Microchip Technology Inc.
DS39582C-page 17
PIC16F87XA
FIGURE 2-4:
PIC16F873A/874A REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD(1)
TRISE(1)
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
CMCON
CVRCON
ADRESL
ADCON1
General
Purpose
Register
96 Bytes
96 Bytes
7Fh
*
Note 1:
2:
DS39582C-page 18
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(2)
Reserved(2)
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
120h
A0h
General
Purpose
Register
Bank 0
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
File
Address
File
Address
accesses
20h-7Fh
1EFh
1F0h
16Fh
170h
17Fh
FFh
Bank 1
accesses
A0h - FFh
Bank 2
1FFh
Bank 3
Unimplemented data memory locations, read as ‘0’.
Not a physical register.
These registers are not implemented on the PIC16F873A.
These registers are reserved; maintain these registers clear.
2001-2013 Microchip Technology Inc.
PIC16F87XA
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
Address
Name
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral features section.
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR, BOR on page:
Bank 0
00h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
01h
TMR0
Timer0 Module Register
xxxx xxxx 55, 150
02h(3)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 30, 150
03h(3)
STATUS
04h(3)
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
0001 1xxx 22, 150
xxxx xxxx 31, 150
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx 45, 150
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx 47, 150
08h(4)
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx 48, 150
09h(4)
PORTE
—
—
—
0Ah(1,3)
PCLATH
—
—
—
0Bh(3)
INTCON
0Ch
PIR1
—
—
PORTA Data Latch when written: PORTA pins when read
—
—
RE2
RE1
--0x 0000 43, 150
RE0
Write Buffer for the upper 5 bits of the Program Counter
RBIF
---- -xxx 49, 150
---0 0000 30, 150
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
PSPIF(3)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 26, 150
0000 000x 24, 150
—
CMIF
—
EEIF
BCLIF
—
—
CCP2IF -0-0 0--0 28, 150
0Dh
PIR2
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 60, 150
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 60, 150
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
17h
CCP1CON
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 118, 150
1Ah
RCREG
USART Receive Data Register
0000 0000 118, 150
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx 63, 150
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
1Dh
CCP2CON
1Eh
ADRESH
1Fh
ADCON0
Legend:
Note
1:
2:
3:
4:
5:
—
—
T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
TMR1CS TMR1ON --00 0000 57, 150
TMR2ON
T2CKPS1 T2CKPS0 -000 0000 61, 150
Timer2 Module Register
—
0000 0000 62, 150
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
xxxx xxxx 79, 150
SSPM2
CCP1X
CCP1Y
CCP1M3
CCP1M2
SPEN
RX9
SREN
CREN
ADDEN
FERR
CCP2X
ADCS0
CHS2
82, 82,
150
CCP1M1 CCP1M0 --00 0000 64, 150
OERR
RX9D
0000 000x 112, 150
xxxx xxxx 63, 150
CCP2Y
CCP2M3
CCP2M2
CHS1
CHS0
GO/DONE
CCP2M1 CCP2M0 --00 0000 64, 150
A/D Result Register High Byte
ADCS1
0000 0000
xxxx xxxx 63, 150
—
—
SSPM0
xxxx xxxx 63, 150
—
—
SSPM1
xxxx xxxx 133, 150
—
ADON
0000 00-0 127, 150
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose
contents are transferred to the upper byte of the program counter.
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
2001-2013 Microchip Technology Inc.
DS39582C-page 19
PIC16F87XA
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR, BOR on page:
Bank 1
80h(3)
INDF
81h
OPTION_REG
82h(3)
PCL
83h(3)
STATUS
84h(3)
FSR
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
0000 0000 30, 150
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
1111 1111 23, 150
0001 1xxx 22, 150
xxxx xxxx 31, 150
PORTA Data Direction Register
--11 1111 43, 150
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111 45, 150
87h
TRISC
PORTC Data Direction Register
1111 1111 47, 150
88h(4)
TRISD
PORTD Data Direction Register
89h(4)
TRISE
8Ah(1,3)
PCLATH
—
—
—
8Bh(3)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
8Ch
PIE1
PSPIE(2)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 25, 151
8Dh
PIE2
—
CMIE
—
EEIE
BCLIE
—
—
CCP2IE -0-0 0--0 27, 151
8Eh
PCON
—
—
—
—
—
—
POR
IBF
OBF
IBOV
1111 1111 48, 151
PSPMODE
—
PORTE Data Direction bits
0000 -111 50, 151
Write Buffer for the upper 5 bits of the Program Counter
RBIF
BOR
---0 0000 30, 150
0000 000x 24, 150
---- --qq 29, 151
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
SSPCON2
GCEN
92h
PR2
Timer2 Period Register
1111 1111 62, 151
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000 79, 151
94h
SSPSTAT
SMP
ACKSTAT
CKE
ACKDT
D/A
ACKEN
P
RCEN
S
PEN
R/W
RSEN
UA
SEN
BF
0000 0000 83, 151
0000 0000 79, 151
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
99h
SPBRG
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111 135, 151
9Dh
CVRCON
CVREN
CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
000- 0000 141, 151
9Eh
ADRESL
9Fh
ADCON1
—
PCFG3
PCFG2
PCFG1
PCFG0
Legend:
Note
1:
2:
3:
4:
5:
Baud Rate Generator Register
0000 -010 111, 151
0000 0000 113, 151
A/D Result Register Low Byte
ADFM
ADCS2
—
xxxx xxxx 133, 151
00-- 0000 128, 151
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose
contents are transferred to the upper byte of the program counter.
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
DS39582C-page 20
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR, BOR on page:
Bank 2
100h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
101h
TMR0
Timer0 Module Register
xxxx xxxx 55, 150
102h(3)
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 30, 150
103h(3)
STATUS
104h(3)
FSR
105h
—
106h
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
PORTB
0001 1xxx 22, 150
xxxx xxxx 31, 150
Unimplemented
—
PORTB Data Latch when written: PORTB pins when read
—
xxxx xxxx 45, 150
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
—
Unimplemented
—
—
10Ah(1,3) PCLATH
10Bh(3)
INTCON
—
—
—
GIE
PEIE
TMR0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
TMR0IF
INTF
RBIF
---0 0000 30, 150
0000 000x 24, 150
10Ch
EEDATA
EEPROM Data Register Low Byte
xxxx xxxx 39, 151
10Dh
EEADR
EEPROM Address Register Low Byte
xxxx xxxx 39, 151
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
EEPROM Data Register High Byte
--xx xxxx 39, 151
—(5)
---- xxxx 39, 151
—
EEPROM Address Register High Byte
Bank 3
180h(3)
INDF
181h
OPTION_REG
182h(3)
PCL
183h(3)
STATUS
184h(3)
FSR
185h
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
IRP
RP1
RP0
TO
PD
Z
DC
C
TRISB
1111 1111 23, 150
0000 0000 30, 150
Indirect Data Memory Address Pointer
—
186h
RBPU
Program Counter (PC) Least Significant Byte
0001 1xxx 22, 150
xxxx xxxx 31, 150
Unimplemented
—
PORTB Data Direction Register
—
1111 1111 45, 150
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
18Ah(1,3) PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 30, 150
18Bh(3)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 24, 150
18Ch
EECON1
EEPGD
—
—
—
WRERR
WREN
WR
RD
x--- x000 34, 151
18Dh
EECON2
EEPROM Control Register 2 (not a physical register)
---- ---- 39, 151
18Eh
—
Reserved; maintain clear
0000 0000
—
18Fh
—
Reserved; maintain clear
0000 0000
—
Legend:
Note
1:
2:
3:
4:
5:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose
contents are transferred to the upper byte of the program counter.
Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’.
Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.
2001-2013 Microchip Technology Inc.
DS39582C-page 21
PIC16F87XA
2.2.2.1
Status Register
The Status register contains the arithmetic status of the
ALU, the Reset status and the bank select bits for data
memory.
The Status register can be the destination for any
instruction, as with any other register. If the Status register is the destination for an instruction that affects the
Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
Status register as destination may be different than
intended.
REGISTER 2-1:
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the Status register as
000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Status register because these instructions do not affect
the Z, C or DC bits from the Status register. For other
instructions not affecting any status bits, see
Section 15.0 “Instruction Set Summary”.
Note:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(for borrow, the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high, or low order bit of the source register.
Legend:
DS39582C-page 22
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
2.2.2.2
OPTION_REG Register
Note:
The OPTION_REG Register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external
INT interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
x = Bit is unknown
When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are
enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3
and ensure the proper operation of the device
2001-2013 Microchip Technology Inc.
DS39582C-page 23
PIC16F87XA
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of its
corresponding enable bit or the global
enable bit, GIE (INTCON). User software
should ensure the appropriate interrupt flag
bits are clear prior to enabling an interrupt.
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
Legend:
DS39582C-page 24
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
2.2.2.4
PIE1 Register
Note:
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
(1)
PSPIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 7
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 25
PIC16F87XA
2.2.2.5
PIR1 Register
Note:
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of its
corresponding enable bit or the global
enable bit, GIE (INTCON). User software
should ensure the appropriate interrupt bits
are clear prior to enabling an interrupt.
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
PSPIF
bit 7
(1)
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 0
bit 7
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are:
• SPI – A transmission/reception has taken place.
• I2C Slave – A transmission/reception has taken place.
• I2C Master
- A transmission/reception has taken place.
- The initiated Start condition was completed by the SSP module.
- The initiated Stop condition was completed by the SSP module.
- The initiated Restart condition was completed by the SSP module.
- The initiated Acknowledge condition was completed by the SSP module.
- A Start condition occurred while the SSP module was Idle (multi-master system).
- A Stop condition occurred while the SSP module was Idle (multi-master system).
0 = No SSP interrupt condition has occurred
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
- n = Value at POR
DS39582C-page 26
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
2.2.2.6
PIE2 Register
Note:
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt, the SSP bus collision
interrupt, EEPROM write operation interrupt and the
comparator interrupt.
REGISTER 2-6:
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
PIE2 REGISTER (ADDRESS 8Dh)
U-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
CMIE
—
EEIE
BCLIE
—
—
CCP2IE
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disable the comparator interrupt
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
bit 3
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
bit 2-1
Unimplemented: Read as ‘0’
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 27
PIC16F87XA
2.2.2.7
PIR2 Register
Note:
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt, EEPROM
write operation interrupt and the comparator interrupt.
REGISTER 2-7:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
PIR2 REGISTER (ADDRESS 0Dh)
U-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
CMIF
—
EEIF
BCLIF
—
—
CCP2IF
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
CMIF: Comparator Interrupt Flag bit
1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
bit 5
Unimplemented: Read as ‘0’
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP when configured for I2C Master mode
0 = No bus collision has occurred
bit 2-1
Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused.
Legend:
DS39582C-page 28
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
2.2.2.8
PCON Register
Note:
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8:
BOR is unknown on Power-on Reset. It
must be set by the user and checked on
subsequent Resets to see if BOR is clear,
indicating a brown-out has occurred. The
BOR status bit is a “don’t care” and is not
predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the
configuration word).
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-1
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 29
PIC16F87XA
2.3
PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register which is a readable
and writable register. The upper bits (PC) are
not readable, but are indirectly writable through the
PCLATH register. On any Reset, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the
figure shows how the PC is loaded on a write to PCL
(PCLATH PCH). The lower example in the
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH PCH).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
ALU
PCLATH
PCH
12
11 10
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW and RETFIE instructions
or the vectoring to an interrupt address.
2.4
Program Memory Paging
All PIC16F87XA devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALL instruction
(or interrupt) is executed, the entire 13-bit PC is popped
off the stack. Therefore, manipulation of the
PCLATH bits is not required for the RETURN
instructions (which POPs the address from the stack).
Note:
PCL
8
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
0
7
PC
GOTO,CALL
2
PCLATH
11
Opcode
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
application note, AN556, “Implementing a Table Read”
(DS00556).
2.3.2
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
EXAMPLE 2-1:
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3
CALL SUB1_P1
:
:
ORG 0x900
STACK
The PIC16F87XA family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POP’ed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH register for any subsequent subroutine calls or
GOTO instructions.
;Select page 1
;(800h-FFFh)
;Call subroutine in
;page 1 (800h-FFFh)
;page 1 (800h-FFFh)
SUB1_P1
:
:
RETURN
;called subroutine
;page 1 (800h-FFFh)
;return to
;Call subroutine
;in page 0
;(000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS39582C-page 30
2001-2013 Microchip Technology Inc.
PIC16F87XA
2.5
Indirect Addressing, INDF and
FSR Registers
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-2:
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly
(FSR = 0) will read 00h. Writing to the INDF register
indirectly results in a no operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(Status) as shown in Figure 2-6.
FIGURE 2-6:
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
NEXT
Bank Select
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
CONTINUE
:
;yes continue
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
6
Indirect Addressing
From Opcode
0
IRP
7
Bank Select
Location Select
00
01
10
FSR Register
0
Location Select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory(1)
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: For register file map detail, see Figure 2-3.
2001-2013 Microchip Technology Inc.
DS39582C-page 31
PIC16F87XA
NOTES:
DS39582C-page 32
2001-2013 Microchip Technology Inc.
PIC16F87XA
3.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The data EEPROM and Flash program memory is readable and writable during normal operation (over the full
VDD range). This memory is not directly mapped in the
register file space. Instead, it is indirectly addressed
through the Special Function Registers. There are six
SFRs used to read and write this memory:
•
•
•
•
•
•
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data EEPROM
(depending on the device), with an address range from
00h to FFh. On devices with 128 bytes, addresses from
80h to FFh are unimplemented and will wraparound to
the beginning of data EEPROM memory. When writing
to unimplemented locations, the on-chip charge pump
will be turned off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14-bit data for read/write and the EEADR
and EEADRH registers form a two-byte word that holds
the 13-bit address of the program memory location
being accessed. These devices have 4 or 8K words of
program Flash, with an address range from 0000h to
0FFFh for the PIC16F873A/874A and 0000h to 1FFFh
for the PIC16F876A/877A. Addresses above the range
of the respective device will wraparound to the
beginning of program memory.
The EEPROM data memory allows single-byte read and
write. The Flash program memory allows single-word
reads and four-word block writes. Program memory
write operations automatically perform an erase-beforewrite on blocks of four words. A byte write in data
EEPROM memory automatically erases the location
and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory.
Depending on the settings of the write-protect bits, the
device may or may not be able to write certain blocks
of the program memory; however, reads of the program
memory are allowed. When code-protected, the device
programmer can no longer access data or program
memory; this does NOT inhibit internal reads or writes.
2001-2013 Microchip Technology Inc.
3.1
EEADR and EEADRH
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register. When selecting a program address value, the MSByte of the
address is written to the EEADRH register and the
LSByte is written to the EEADR register.
If the device contains less memory than the full address
reach of the address register pair, the Most Significant
bits of the registers are not implemented. For example,
if the device has 128 bytes of data EEPROM, the Most
Significant bit of EEADR is not implemented on access
to data EEPROM.
3.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Control bit, EEPGD, determines if the access will be a
program or data memory access. When clear, as it is
when reset, any subsequent operations will operate on
the data memory. When set, any subsequent
operations will operate on the program memory.
Control bits, RD and WR, initiate read and write or
erase, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at completion of the read or write operation. The inability to
clear the WR bit in software prevents the accidental,
premature termination of a write operation.
The WREN bit, when set, will allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR or a WDT Time-out Reset during normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
Interrupt flag bit, EEIF in the PIR2 register, is set when
the write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
Note:
The self-programming mechanism for Flash
program memory has been changed. On
previous PIC16F87X devices, Flash programming was done in single-word erase/
write cycles. The newer PIC18F87XA
devices use a four-word erase/write
cycle. See Section 3.6 “Writing to Flash
Program Memory” for more information.
DS39582C-page 33
PIC16F87XA
REGISTER 3-1:
EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
operation)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
Legend:
DS39582C-page 34
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
3.3
Reading Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD control bit (EECON1) and then set control bit RD
(EECON1). The data is available in the very next
cycle in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1.
2.
3.
4.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the RD bit to start the read operation.
Read the data from the EEDATA register.
EXAMPLE 3-1:
DATA EEPROM READ
BSF
BCF
MOVF
MOVWF
BSF
BCF
STATUS,RP1
STATUS,RP0
DATA_EE_ADDR,W
EEADR
STATUS,RP0
EECON1,EEPGD
BSF
BCF
MOVF
EECON1,RD
STATUS,RP0
EEDATA,W
;
;
;
;
;
;
;
;
;
;
Bank 2
Data Memory
Address to read
Bank 3
Point to Data
memory
EE Read
Bank 2
W = EEDATA
The steps to write to EEPROM data memory are:
1.
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first
to W, then to EECON2)
• Write AAh to EECON2 in two steps (first
to W, then to EECON2)
• Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
EXAMPLE 3-2:
3.4
Writing to Data EEPROM Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data to
the EEDATA register. Then the user must follow a
specific write sequence to initiate the write for each byte.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
2001-2013 Microchip Technology Inc.
Required
Sequence
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
DATA EEPROM WRITE
BSF
BSF
BTFSC
GOTO
BCF
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
STATUS,RP1
STATUS,RP0
EECON1,WR
$-1
STATUS, RP0
DATA_EE_ADDR,W
EEADR
DATA_EE_DATA,W
EEDATA
STATUS,RP0
EECON1,EEPGD
BSF
EECON1,WREN
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
BSF
BCF
INTCON,GIE
EECON1,WREN
;
;Wait for write
;to complete
;Bank 2
;Data Memory
;Address to write
;Data Memory Value
;to write
;Bank 3
;Point to DATA
;memory
;Enable writes
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit to
;begin write
;Enable INTs.
;Disable writes
DS39582C-page 35
PIC16F87XA
3.5
Reading Flash Program Memory
To read a program memory location, the user must write
two bytes of the address to the EEADR and EEADRH
registers, set the EEPGD control bit (EECON1) and
then set control bit RD (EECON1). Once the read
control bit is set, the program memory Flash controller
will use the next two instruction cycles to read the data.
This causes these two instructions immediately follow-
EXAMPLE 3-3:
Required
Sequence
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BSF
ing the “BSF EECON1,RD” instruction to be ignored.
The data is available in the very next cycle in the
EEDATA and EEDATH registers; therefore, it can be
read as two bytes in the following instructions. EEDATA
and EEDATH registers will hold this value until another
read or until it is written to by the user (during a write
operation).
FLASH PROGRAM READ
STATUS, RP1
STATUS, RP0
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADR
STATUS, RP0
EECON1, EEPGD
EECON1, RD
;
;
;
;
;
;
;
;
;
Bank 2
MS Byte of Program Address to read
LS Byte of Program Address to read
Bank 3
Point to PROGRAM memory
EE Read
;
NOP
NOP
; Any instructions here are ignored as program
; memory is read in second cycle after BSF EECON1,RD
;
BCF
MOVF
MOVWF
MOVF
MOVWF
DS39582C-page 36
STATUS, RP0
EEDATA, W
DATAL
EEDATH, W
DATAH
; Bank 2
; W = LS Byte of Program EEDATA
;
; W = MS Byte of Program EEDATA
;
2001-2013 Microchip Technology Inc.
PIC16F87XA
3.6
Writing to Flash Program Memory
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT1:WRT0 of
the device configuration word (Register 14-1). Flash
program memory must be written in four-word blocks. A
block consists of four words with sequential addresses,
with a lower boundary defined by an address, where
EEADR = 00. At the same time, all block writes to
program memory are done as erase and write operations. The write operation is edge-aligned and cannot
occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 3-1). This is accomplished
by first writing the destination address to EEADR and
EEADRH and then writing the data to EEDATA and
EEDATH. After the address and data have been set up,
then the following sequence of events must be
executed:
1.
2.
3.
Set the EEPGD control bit (EECON1).
Write 55h, then AAh, to EECON2 (Flash
programming sequence).
Set the WR control bit (EECON1).
All four buffer register locations MUST be written to with
correct data. If only one, two or three words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the program location(s) not being written and loads it into the
EEDATA and EEDATH registers. Then the sequence of
events to transfer data to the buffer registers must be
executed.
FIGURE 3-1:
To transfer data from the buffer registers to the program
memory, the EEADR and EEADRH must point to the last
location in the four-word block (EEADR = 11).
Then the following sequence of events must be
executed:
1.
2.
3.
Set the EEPGD control bit (EECON1).
Write 55h, then AAh, to EECON2 (Flash
programming sequence).
Set control bit WR (EECON1) to begin the
write operation.
The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (00,01,10,11).
When the write is performed on the last word
(EEADR = 11), the block of four words are
automatically erased and the contents of the buffer
registers are written into the program memory.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
which the erase takes place (i.e., the last word of the
four-word block). This is not Sleep mode as the clocks
and peripherals will continue to run. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 write instruction. If the
sequence is performed to any other location, the action
is ignored.
BLOCK WRITES TO FLASH PROGRAM MEMORY
7
5
0
0 7
EEDATH
EEDATA
6
8
14
14
First word of block
to be written
14
EEADR = 00
EEADR = 10
EEADR = 01
Buffer Register
Buffer Register
Buffer Register
Four words of
Flash are erased,
then all buffers
are transferred
to Flash
automatically
after this word
is written
14
EEADR = 11
Buffer Register
Program Memory
2001-2013 Microchip Technology Inc.
DS39582C-page 37
PIC16F87XA
An example of the complete four-word write sequence
is shown in Example 3-4. The initial address is loaded
into the EEADRH:EEADR register pair; the four words
of data are loaded using indirect addressing.
EXAMPLE 3-4:
;
;
;
;
;
;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following:
1. A valid starting address (the least significant bits = ‘00’)is loaded in ADDRH:ADDRL
2. The 8 bytes of data are loaded, starting at the address in DATADDR
3. ADDRH, ADDRL and DATADDR are all located in shared data memory 0x70 - 0x7f
Required
Sequence
LOOP
BSF
BCF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
INCF
MOVF
MOVWF
INCF
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
STATUS,RP1
STATUS,RP0
ADDRH,W
EEADRH
ADDRL,W
EEADR
DATAADDR,W
FSR
INDF,W
EEDATA
FSR,F
INDF,W
EEDATH
FSR,F
STATUS,RP0
EECON1,EEPGD
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
NOP
BCF
BSF
BCF
INCF
MOVF
ANDLW
XORLW
BTFSC
GOTO
DS39582C-page 38
EECON1,WREN
INTCON,GIE
STATUS,RP0
EEADR,F
EEADR,W
0x03
0x03
STATUS,Z
LOOP
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Bank 2
Load initial address
Load initial data address
Load first data byte into lower
Next byte
Load second data byte into upper
Bank 3
Point to program memory
Enable writes
Disable interrupts (if using)
Start of required write sequence:
Write 55h
Write AAh
Set WR bit to begin write
Any instructions here are ignored as processor
halts to begin write sequence
processor will stop here and wait for write complete
after write processor continues with 3rd instruction
Disable writes
Enable interrupts (if using)
Bank 2
Increment address
Check if lower two bits of address are ‘00’
Indicates when four words have been programmed
Exit if more than four words,
Continue if less than four words
2001-2013 Microchip Technology Inc.
PIC16F87XA
3.7
Protection Against Spurious Write
3.8
There are conditions when the device should not write
to the data EEPROM or Flash program memory. To
protect against spurious writes, various mechanisms
have been built-in. On power-up, WREN is cleared.
Also, the Power-up Timer (72 ms duration) prevents an
EEPROM write.
When the data EEPROM is code-protected, the microcontroller can read and write to the EEPROM normally.
However, all external access to the EEPROM is
disabled. External write access to the program memory
is also disabled.
When program memory is code-protected, the microcontroller can read and write to program memory normally,
as well as execute instructions. Writes by the device may
be selectively inhibited to regions of the memory depending on the setting of bits WR1:WR0 of the configuration
word (see Section 14.1 “Configuration Bits” for additional information). External access to the memory is also
disabled.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
TABLE 3-1:
Address
Operation During Code-Protect
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND
FLASH PROGRAM MEMORIES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets
10Ch
EEDATA
EEPROM/Flash Data Register Low Byte
xxxx xxxx uuuu uuuu
10Dh
EEADR
EEPROM/Flash Address Register Low Byte
xxxx xxxx uuuu uuuu
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
—
18Ch
EECON1
EEPGD
—
—
18Dh
EECON2
EEPROM Control Register 2 (not a physical register)
0Dh
PIR2
—
CMIF
—
EEIF
BCLIF
—
—
CCP2IF
-0-0 0--0 -0-0 0--0
8Dh
PIE2
—
CMIE
—
EEIE
BCLIE
—
—
CCP2IE
-0-0 0--0 -0-0 0--0
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM or Flash program memory.
2001-2013 Microchip Technology Inc.
EEPROM/Flash Data Register High Byte
xxxx xxxx ---0 q000
EEPROM/Flash Address Register High Byte
—
WRERR
WREN
WR
xxxx xxxx ---- ---RD
x--- x000 ---0 q000
---- ---- ---- ----
DS39582C-page 39
PIC16F87XA
NOTES:
DS39582C-page 40
2001-2013 Microchip Technology Inc.
PIC16F87XA
4.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PIC® Mid-Range Reference Manual (DS33023).
4.1
PORTA and the TRISA Register
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open-drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and the analog VREF input for both the A/D converters
and the comparators. The operation of each pin is
selected by clearing/setting the appropriate control bits
in the ADCON1 and/or CMCON registers.
Note:
EXAMPLE 4-1:
INITIALIZING PORTA
BCF
BCF
CLRF
STATUS, RP0
STATUS, RP1
PORTA
BSF
MOVLW
MOVWF
MOVLW
STATUS, RP0
0x06
ADCON1
0xCF
MOVWF
TRISA
FIGURE 4-1:
Data
Bus
WR
PORTA
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BLOCK DIAGRAM OF
RA3:RA0 PINS
Data Latch
D
Q
VDD
CK
Q
P
I/O pin(1)
TRIS Latch
D
WR
TRISA
CK
N
Q
VSS
Analog
Input
Mode
Q
RD
TRISA
On a Power-on Reset, these pins are configured as analog inputs and read as ‘0’.
The comparators are in the off (digital)
state.
The TRISA register controls the direction of the port
pins even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Bank0
Initialize PORTA by
clearing output
data latches
Select Bank 1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA as inputs
RA as outputs
TRISAare always
read as '0'.
TTL
Input
Buffer
Q
D
EN
RD PORTA
To A/D Converter or Comparator
Note 1: I/O pins have protection diodes to VDD and VSS.
2001-2013 Microchip Technology Inc.
DS39582C-page 41
PIC16F87XA
FIGURE 4-2:
BLOCK DIAGRAM OF RA4/T0CKI PIN
CMCON = x01 or 011
C1OUT
Data Latch
D
Q
Data Bus
WR PORTA
CK
1
Q
TRIS Latch
D
Q
WR TRISA
CK
I/O pin(1)
N
0
VSS
Schmitt
Trigger
Input
Buffer
Q
RD TRISA
Q
D
ENEN
RD PORTA
TMR0 Clock Input
Note 1: I/O pin has protection diodes to VSS only.
FIGURE 4-3:
BLOCK DIAGRAM OF RA5 PIN
CMCON = 011 or 101
C2OUT
Data Bus
WR PORTA
Data Latch
D
Q
CK
Q
VDD
1
P
0
TRIS Latch
D
Q
WR TRISA
CK
I/O pin(1)
N
Analog
IIP Mode
Q
VSS
TTL
Input
Buffer
RD TRISA
Q
D
ENEN
RD PORTA
A/D Converter or SS Input
Note 1: I/O pin has protection diodes to VDD and VSS.
DS39582C-page 42
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 4-1:
PORTA FUNCTIONS
Name
RA0/AN0
Bit#
Buffer
bit 0
TTL
Function
Input/output or analog input.
RA1/AN1
bit 1
TTL
Input/output or analog input.
RA2/AN2/VREF-/CVREF
bit 2
TTL
Input/output or analog input or VREF- or CVREF.
RA3/AN3/VREF+
bit 3
TTL
Input/output or analog input or VREF+.
RA4/T0CKI/C1OUT
bit 4
ST
Input/output or external clock input for Timer0 or comparator output.
Output is open-drain type.
RA5/AN4/SS/C2OUT
bit 5
TTL
Input/output or analog input or slave select input for synchronous serial
port or comparator output.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0u 0000
05h
PORTA
—
—
85h
TRISA
—
—
9Ch
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
9Dh
CVRCON
CVREN CVROE
CVRR
—
CVR3
CVR2
9Fh
ADCON1
—
—
PCFG3
PCFG2
Legend:
Note:
ADFM
ADCS2
PORTA Data Direction Register
--11 1111
--11 1111
CM0
0000 0111
0000 0111
CVR1
CVR0
000- 0000
000- 0000
PCFG1
PCFG0
00-- 0000
00-- 0000
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.
2001-2013 Microchip Technology Inc.
DS39582C-page 43
PIC16F87XA
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
Three pins of PORTB are multiplexed with the In-Circuit
Debugger and Low-Voltage Programming function:
RB3/PGM, RB6/PGC and RB7/PGD. The alternate
functions of these pins are described in Section 14.0
“Special Features of the CPU”.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 4-4:
BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
Data Bus
Weak
P Pull-up
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt-on-mismatch feature, together with software configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the application
note, AN552, “Implementing Wake-up on Key Stroke”
(DS00552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION_REG).
RB0/INT is discussed in detail in Section 14.11.1 “INT
Interrupt”.
Data Latch
D
FIGURE 4-5:
Q
BLOCK DIAGRAM OF
RB7:RB4 PINS
I/O pin(1)
WR Port
CK
VDD
TRIS Latch
D
WR TRIS
RBPU(2)
Q
TTL
Input
Buffer
CK
Data Bus
Weak
P Pull-up
Data Latch
D
Q
I/O pin(1)
WR Port
CK
RD TRIS
Q
TRIS Latch
D
Q
D
RD Port
WR TRIS
EN
RB0/INT
RB3/PGM
ST
Buffer
RD TRIS
Schmitt Trigger
Buffer
Latch
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG).
Four of the PORTB pins, RB7:RB4, have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB port change
interrupt with flag bit RBIF (INTCON).
DS39582C-page 44
TTL
Input
Buffer
CK
Q
D
RD Port
EN
Q1
Set RBIF
Q
D
RD Port
From other
RB7:RB4 pins
EN
Q3
RB7:RB6
In Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG).
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 4-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
RB0/INT
bit 0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software programmable
weak pull-up.
RB1
bit 1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit 2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3/PGM
bit 3
TTL
Input/output pin or programming pin in LVP mode. Internal software
programmable weak pull-up.
RB4
bit 4
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
bit 5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6/PGC
bit 6
TTL/ST(2)
Input/output pin (with interrupt-on-change) or in-circuit debugger pin.
Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD
bit 7
TTL/ST(2)
Input/output pin (with interrupt-on-change) or in-circuit debugger pin.
Internal software programmable weak pull-up. Serial programming data.
(3)
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode or in-circuit debugger.
3: Low-Voltage ICSP Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
TABLE 4-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
06h, 106h PORTB
86h, 186h TRISB
Value on:
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx uuuu uuuu
PORTB Data Direction Register
81h, 181h OPTION_REG RBPU
INTEDG
T0CS T0SE
1111 1111 1111 1111
PSA
PS2
PS1
PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
2001-2013 Microchip Technology Inc.
DS39582C-page 45
PIC16F87XA
4.3
PORTC and the TRISC Register
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
When the I2C module is enabled, the PORTC
pins can be configured with normal I2C levels, or with
SMBus levels, by using the CKE bit (SSPSTAT).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as the
destination, should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 4-6:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC,
RC
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
WR Port
D
CK
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC
Port/Peripheral Select(2)
Peripheral Data Out
Data Bus
WR Port
D
CK
0
VDD
Q
Q
P
1
Data Latch
D
WR TRIS
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
RD TRIS
Peripheral
OE(3)
Schmitt
Trigger
Q
D
EN
RD Port
0
Schmitt
Trigger
with
SMBus
Levels
SSP Input
1
CKE
SSPSTAT
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port data
and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
VDD
0
Q
Q
FIGURE 4-7:
P
1
Data Latch
D
WR TRIS
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
RD TRIS
Peripheral
OE(3)
Schmitt
Trigger
Q
D
EN
RD Port
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral Select signal selects between port
data and peripheral output.
3: Peripheral OE (Output Enable) is only activated if
Peripheral Select is active.
DS39582C-page 46
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 4-5:
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit 0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2
bit 1
ST
Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1
bit 2
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
bit 3
ST
RC3 can also be the synchronous serial clock for both SPI and
I2C modes.
RC4/SDI/SDA
bit 4
ST
RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).
RC5/SDO
bit 5
ST
Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK
bit 6
ST
Input/output port pin or USART asynchronous transmit or
synchronous clock.
RC7/RX/DT
bit 7
ST
Input/output port pin or USART asynchronous receive or
synchronous data.
Legend: ST = Schmitt Trigger input
TABLE 4-6:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
07h
PORTC
87h
TRISC
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
PORTC Data Direction Register
1111 1111 1111 1111
Legend: x = unknown, u = unchanged
2001-2013 Microchip Technology Inc.
DS39582C-page 47
PIC16F87XA
4.4
FIGURE 4-8:
PORTD and TRISD Registers
Note:
PORTD and TRISD are not implemented
on the 28-pin devices.
Data
Bus
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configurable as an input
or output.
WR
Port
PORTD can be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit, PSPMODE (TRISE). In this mode, the
input buffers are TTL.
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
WR
TRIS
Schmitt
Trigger
Input
Buffer
CK
RD
TRIS
Q
D
ENEN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 4-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
Function
RD0/PSP0
bit 0
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 0.
RD1/PSP1
bit 1
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 1.
RD2/PSP2
bit2
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 2.
RD3/PSP3
bit 3
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 3.
RD4/PSP4
bit 4
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 4.
RD5/PSP5
bit 5
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 5.
RD6/PSP6
bit 6
ST/TTL
(1)
Input/output port pin or Parallel Slave Port bit 6.
RD7/PSP7
bit 7
ST/TTL(1)
Input/output port pin or Parallel Slave Port bit 7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-8:
Address
08h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
88h
TRISD
89h
TRISE
PORTD Data Direction Register
IBF
OBF IBOV PSPMODE
1111 1111 1111 1111
—
PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
DS39582C-page 48
2001-2013 Microchip Technology Inc.
PIC16F87XA
4.5
PORTE and TRISE Register
Note:
PORTE and TRISE are not implemented
on the 28-pin devices.
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7) which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
The PORTE pins become the I/O control inputs for the
microprocessor port when bit PSPMODE (TRISE) is
set. In this mode, the user must make certain that the
TRISE bits are set and that the pins are configured
as digital inputs. Also, ensure that ADCON1 is configured for digital I/O. In this mode, the input buffers are
TTL.
FIGURE 4-9:
Data
Bus
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
Data Latch
D
Q
WR
Port
I/O pin(1)
CK
TRIS Latch
D
WR
TRIS
RD
TRIS
Q
PORTE pins are multiplexed with analog inputs. When
selected for analog input, these pins will read as ‘0’s.
Note:
Schmitt
Trigger
Input
Buffer
CK
Register 4-1 shows the TRISE register which also
controls the Parallel Slave Port operation.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Q
D
ENEN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
On a Power-on Reset, these pins are
configured as analog inputs and read as ‘0’.
TABLE 4-9:
Name
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
PORTE FUNCTIONS
Bit#
bit 0
bit 1
bit 2
Buffer Type
Function
ST/TTL(1)
I/O port pin or read control input in Parallel Slave Port mode or analog input:
RD
1 = Idle
0 = Read operation. Contents of PORTD register are output to PORTD
I/O pins (if chip selected).
ST/TTL(1)
I/O port pin or write control input in Parallel Slave Port mode or analog input:
WR
1 = Idle
0 = Write operation. Value of PORTD I/O pins is latched into PORTD
register (if chip selected).
ST/TTL(1)
I/O port pin or chip select control input in Parallel Slave Port mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
2001-2013 Microchip Technology Inc.
DS39582C-page 49
PIC16F87XA
TABLE 4-10:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
9Fh
ADCON1
ADFM
ADCS2
—
—
PCFG3
Legend:
Value on
all other
Resets
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
RE2
RE1
RE0
---- -xxx ---- -uuu
PORTE Data Direction bits
PCFG2
PCFG1
PCFG0
0000 -111 0000 -111
00-- 0000 00-- 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
REGISTER 4-1:
TRISE REGISTER (ADDRESS 89h)
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
—
Bit 2
Bit 1
Bit 0
bit 7
bit 0
Parallel Slave Port Status/Control Bits:
bit 7
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in
software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = PORTD functions in Parallel Slave Port mode
0 = PORTD functions in general purpose I/O mode
bit 3
Unimplemented: Read as ‘0’
PORTE Data Direction Bits:
bit 2
Bit 2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1
Bit 1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0
Bit 0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
Legend:
DS39582C-page 50
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
4.6
Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F873A or PIC16F876A.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port, when control bit PSPMODE
(TRISE) is set. In Slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD/AN5, and WR control input
pin, RE1/WR/AN6.
The PSP can directly interface to an 8-bit
microprocessor data bus. The external microprocessor
can read or write the PORTD latch as an 8-bit latch.
Setting bit PSPMODE enables port pin RE0/RD/AN5 to
be the RD input, RE1/WR/AN6 to be the WR input and
RE2/CS/AN7 to be the CS (Chip Select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE) must be configured
as inputs (set). The A/D port configuration bits,
PCFG3:PCFG0 (ADCON1), must be set to
configure pins RE2:RE0 as digital I/O.
There are actually two 8-bit latches: one for data output
and one for data input. The user writes 8-bit data to the
PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, the TRISD register is ignored since the external
device is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 4-11). The interrupt flag bit, PSPIF
(PIR1), is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1).
FIGURE 4-10:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
D
WR
Port
Q
RDx pin
CK
TTL
Q
RD Port
D
ENEN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note 1: I/O pins have protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE) is cleared
immediately (Figure 4-12), indicating that the PORTD
latch is waiting to be read by the external bus. When
either the CS or RD pin becomes high (level triggered),
the interrupt flag bit PSPIF is set on the Q4 clock cycle,
following the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
2001-2013 Microchip Technology Inc.
DS39582C-page 51
PIC16F87XA
FIGURE 4-11:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
FIGURE 4-12:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD
IBF
OBF
PSPIF
TABLE 4-11:
Address
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
Resets
08h
PORTD
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh
ADCON1
ADFM
ADCS2
—
—
PCFG3
PCFG2
Legend:
Note 1:
Port Data Latch when written; Port pins when read
Value on:
POR, BOR
xxxx xxxx uuuu uuuu
RE2
RE1
RE0
PORTE Data Direction bits
TMR2IF
PCFG1
---- -xxx ---- -uuu
0000 -111 0000 -111
TMR1IF 0000 0000 0000 0000
PCFG0 00-- 0000 00-- 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A; always maintain these bits clear.
DS39582C-page 52
2001-2013 Microchip Technology Inc.
PIC16F87XA
5.0
TIMER0 MODULE
Counter mode is selected by setting bit T0CS
(OPTION_REG). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed in detail in Section 5.2 “Using Timer0 with
an External Clock”.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 5.3
“Prescaler” details the operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is
available in the PIC® Mid-Range MCU Family Reference Manual (DS33023).
5.1
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit TMR0IF (INTCON). The interrupt can be
masked by clearing bit TMR0IE (INTCON). Bit
TMR0IF must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the timer is shut-off during
Sleep.
Timer mode is selected by clearing bit T0CS
(OPTION_REG). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 5-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKO (= FOSC/4)
Data Bus
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
Sync
2
Cycles
TMR0 Reg
T0SE
T0CS
Set Flag bit TMR0IF
on Overflow
PSA
PRESCALER
0
Watchdog
Timer
1
M
U
X
8-bit Prescaler
8
8-to-1 MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG).
2001-2013 Microchip Technology Inc.
DS39582C-page 53
PIC16F87XA
5.2
Using Timer0 with an External
Clock
Timer0 module means that there is no prescaler for the
Watchdog Timer and vice versa. This prescaler is not
readable or writable (see Figure 5-1).
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.3
The PSA and PS2:PS0 bits (OPTION_REG)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
Note:
Prescaler
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
REGISTER 5-1:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
OPTION_REG REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU
bit 6
INTEDG
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
1:2
000
1:1
1:4
001
1:2
1:8
010
1:4
1 : 16
011
1:8
1 : 32
100
1 : 16
1 : 64
101
1 : 32
1 : 128
110
1 : 64
111
1 : 256
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
DS39582C-page 54
x = Bit is unknown
To avoid an unintended device Reset, the instruction sequence shown in the PIC®
Mid-Range MCU Family Reference Manual (DS33023) must be executed when
changing the prescaler assignment from Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 5-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Name
01h,101h
TMR0
0Bh,8Bh,
10Bh,18Bh
INTCON
81h,181h
Legend:
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Timer0 Module Register
Value on
all other
Resets
xxxx xxxx uuuu uuuu
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
2001-2013 Microchip Technology Inc.
DS39582C-page 55
PIC16F87XA
NOTES:
DS39582C-page 56
2001-2013 Microchip Technology Inc.
PIC16F87XA
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit, TMR1IF (PIR1). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit, TMR1IE (PIE1).
Timer1 can operate in one of two modes:
• As a Timer
• As a Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON).
REGISTER 6-1:
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON).
Timer1 also has an internal “Reset input”. This Reset
can be generated by either of the two CCP modules
(Section 8.0 “Capture/Compare/PWM Modules”).
Register 6-1 shows the Timer1 Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC value is
ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
—
—
R/W-0
R/W-0
T1CKPS1 T1CKPS0
R/W-0
T1OSCEN
R/W-0
R/W-0
R/W-0
T1SYNC TMR1CS TMR1ON
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 prescale value
10 = 1:4 prescale value
01 = 1:2 prescale value
00 = 1:1 prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 57
PIC16F87XA
6.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON), has no effect since the internal clock is
always in sync.
FIGURE 6-1:
6.2
Timer1 Counter Operation
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
TIMER1 INCREMENTING EDGE
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI when
bit T1OSCEN is cleared.
FIGURE 6-2:
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not
increment even if the external clock is present since the
synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
0
TMR1
TMR1H
Synchronized
Clock Input
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(2)
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS1:T1CKPS0
Q Clock
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS39582C-page 58
2001-2013 Microchip Technology Inc.
PIC16F87XA
6.4
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt-on-overflow which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer.
In Asynchronous Counter mode, Timer1 cannot be
used as a time base for capture or compare operations.
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
TABLE 6-1:
Osc Type
Freq.
C1
C2
LP
32 kHz
33 pF
33 pF
100 kHz
15 pF
15 pF
200 kHz
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz
Epson C-001R32.768K-A
± 20 PPM
100 kHz
Epson C-2 100.00 KC-P
± 20 PPM
STD XTL 200.000 kHz
± 20 PPM
200 kHz
Note 1:
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers while the
register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PIC® Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in
Asynchronous mode.
6.5
Timer1 Oscillator
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
2:
6.6
Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 or CCP2 module is configured in Compare
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Note:
The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit, TMR1IF (PIR1).
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON). The oscillator is a low-power oscillator, rated up to 200 kHz. It
will continue to run during Sleep. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for
Timer1.
2001-2013 Microchip Technology Inc.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1 or CCP2, the write will
take precedence.
DS39582C-page 59
PIC16F87XA
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other Reset, except by the CCP1 and
CCP2 special event triggers.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
TABLE 6-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
0Bh,8Bh,
INTCON
10Bh, 18Bh
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
DS39582C-page 60
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
2001-2013 Microchip Technology Inc.
PIC16F87XA
7.0
TIMER2 MODULE
Register 7-1 shows the Timer2 Control register.
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device
Reset.
Additional information on timer modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
FIGURE 7-1:
The input clock (FOSC/4) has a prescale option of
1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON).
Sets Flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
Output(1)
Reset
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
Postscaler
1:1 to 1:16
EQ
4
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit,
TMR2IF (PIR1)).
TMR2 Reg
Prescaler
1:1, 1:4, 1:16
2
Comparator
PR2 Reg
FOSC/4
T2CKPS1:
T2CKPS0
T2OUTPS3:
T2OUTPS0
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON), to minimize power consumption.
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 postscale
0001 = 1:2 postscale
0010 = 1:3 postscale
•
•
•
1111 = 1:16 postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 61
PIC16F87XA
7.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (POR, MCLR Reset, WDT
Reset or BOR)
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate the
shift clock.
TMR2 is not cleared when T2CON is written.
TABLE 7-1:
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name
0Bh, 8Bh, INTCON
10Bh, 18Bh
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
11h
TMR2
Timer2 Module’s Register
12h
T2CON
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h
PR2
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582C-page 62
Timer2 Period Register
1111 1111 1111 1111
2001-2013 Microchip Technology Inc.
PIC16F87XA
8.0
CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1 except where noted.
CCP2 Module:
Capture/Compare/PWM Register 2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Additional information on CCP modules is available in
the PIC® Mid-Range MCU Family Reference Manual
(DS33023) and in application note AN594, “Using the
CCP Module(s)” (DS00594).
TABLE 8-1:
CCP1 Module:
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
TABLE 8-2:
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Capture
CCP MODE – TIMER
RESOURCES REQUIRED
Capture
Interaction
Same TMR1 time base
Capture
Compare
The compare should be configured for the special event trigger which clears TMR1
Compare
Compare
The compare(s) should be configured for the special event trigger which clears TMR1
PWM
PWM
PWM
Capture
None
The PWMs will have the same frequency and update rate (TMR2 interrupt)
PWM
Compare
None
2001-2013 Microchip Technology Inc.
DS39582C-page 63
PIC16F87XA
REGISTER 8-1:
CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1
resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is
enabled)
11xx = PWM mode
Legend:
DS39582C-page 64
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
8.1
8.1.2
Capture Mode
TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the
following:
Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
•
•
•
•
8.1.3
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
The type of event is configured by control bits,
CCP1M3:CCP1M0 (CCPxCON). When a capture is made, the interrupt request flag bit, CCP1IF
(PIR1), is set. The interrupt flag must be cleared in
software. If another capture occurs before the value in
register CCPR1 is read, the old captured value is
overwritten by the new value.
8.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC bit.
Note:
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
Capture condition.
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
1, 4, 16
RC2/CCP1
pin
CCPR1H
and
Edge Detect
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
8.1.4
CCPR1L
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 8-1:
CLRF
MOVLW
Set Flag bit CCP1IF
(PIR1)
SOFTWARE INTERRUPT
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
; Turn CCP module off
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; move value and CCP ON
CCP1CON
; Load CCP1CON with this
; value
Capture
Enable
TMR1H
TMR1L
CCP1CON
Qs
2001-2013 Microchip Technology Inc.
DS39582C-page 65
PIC16F87XA
8.2
8.2.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1)
and set bit GO/DONE (ADCON0).
Set Flag bit CCP1IF
(PIR1)
RC2/CCP1
pin
CCPR1H CCPR1L
S
R
TRISC
Output Enable
8.2.1
Output
Logic
Match
CCP1CON
Mode Select
Comparator
TMR1H
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
8.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Special Event Trigger
Q
Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON). At the
same time, interrupt flag bit CCP1IF is set.
TIMER1 MODE SELECTION
Note:
The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1).
TMR1L
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
DS39582C-page 66
2001-2013 Microchip Technology Inc.
PIC16F87XA
8.3
8.3.1
PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3 “Setup
for PWM Operation”.
FIGURE 8-3:
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
PWM PERIOD
CCP1CON
The Timer2 postscaler (see Section 7.1
“Timer2 Prescaler and Postscaler”) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
CCPR1L
8.3.2
CCPR1H (Slave)
RC2/CCP1
R
Comparator
TMR2
Q
(Note 1)
S
TRISC
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1: The 8-bit timer is concatenated with 2-bit internal Q
clock, or 2 bits of the prescaler, to create 10-bit time
base.
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4:
PWM OUTPUT
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
PWM Duty Cycle =(CCPR1L:CCP1CON) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitch-free PWM
operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the following formula.
Period
EQUATION 8-1:
Duty Cycle
Resolution =
TMR2 = PR2
FOSC
log FPWM
log(2)
(
)
bits
TMR2 = Duty Cycle
TMR2 = PR2
2001-2013 Microchip Technology Inc.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
DS39582C-page 67
PIC16F87XA
8.3.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISC bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
3.
4.
5.
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 8-4:
4.88 kHz
19.53 kHz
78.12kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFFh
0xFFh
0xFFh
0x3Fh
0x1Fh
0x17h
10
10
10
8
7
5.5
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
0Bh,8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
—
—
—
—
—
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh
PIE2
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
—
—
T1CON
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
17h
CCP1CON
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
1Dh
CCP2CON
Legend:
Note 1:
—
—
—
—
CCP2IE ---- ---0 ---- ---0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
10h
15h
—
—
CCP1X
CCP2X
CCP1Y
CCP2Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
The PSP is not implemented on 28-pin devices; always maintain these bits clear.
DS39582C-page 68
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 8-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
0Bh,8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
TMR1IF 0000 0000 0000 0000
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 Module’s Register
0000 0000 0000 0000
92h
PR2
Timer2 Module’s Period Register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
17h
CCP1CON
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
1Dh
CCP2CON
Legend:
Note 1:
—
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
—
—
CCP1X
CCP2X
CCP1Y
CCP2Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc.
DS39582C-page 69
PIC16F87XA
NOTES:
DS39582C-page 70
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.0
9.1
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
FIGURE 9-1:
Internal
Data Bus
Read
Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
SSPSR reg
RC4/SDI/SDA
RC5/SDO
The I2C interface supports the following modes in
hardware:
RA5/AN4/
SS/C2OUT
Shift
Clock
bit0
Peripheral OE
SS Control
Enable
• Master mode
• Multi-Master mode
• Slave mode
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
TMR2 Output
2
2
Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Write
SSPBUF reg
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
9.2
MSSP BLOCK DIAGRAM
(SPI MODE)
Edge
Select
RC3/SCK/SCL
Prescaler TOSC
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
Additional details are provided under the individual
sections.
Note:
9.3
SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/C2OUT
When the SPI is in Slave mode with SS pin
control enabled (SSPCON = 0100),
the state of the SS pin can affect the state
read back from the TRISC bit. The
Peripheral OE signal from the SSP module in PORTC controls the state that is
read back from the TRISC bit (see
Section 4.3 “PORTC and the TRISC
Register” for information on PORTC). If
Read-Modify-Write instructions, such as
BSF, are performed on the TRISC register
while the SS pin is high, this will cause the
TRISC bit to be set, thus disabling the
SDO output.
Figure 9-1 shows the block diagram of the MSSP
module when operating in SPI mode.
2001-2013 Microchip Technology Inc.
DS39582C-page 71
PIC16F87XA
9.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register (SSPCON)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPCON and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON register is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 9-1:
SSPSTAT: MSSP STATUS REGISTER (SPI MODE) (ADDRESS 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON1).
bit 5
D/A: Data/Address bit
Used in I2C mode only.
bit 4
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write bit information
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
DS39582C-page 72
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
REGISTER 9-2:
SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. (Must be
cleared in software.)
0 = No overflow
Note:
bit 5
In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 73
PIC16F87XA
9.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON and SSPSTAT).
These control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
EXAMPLE 9-1:
LOOP
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit, WCOL
(SSPCON), will be set. User software must clear
the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 9-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
LOADING THE SSPBUF (SSPSR) REGISTER
BTFSS
BRA
MOVF
SSPSTAT, BF
LOOP
SSPBUF, W
;Has data been received(transmit complete)?
;No
;WREG reg = contents of SSPBUF
MOVWF
RXDATA
;Save in user RAM, if data is meaningful
MOVF
MOVWF
TXDATA, W
SSPBUF
;W reg = contents of TXDATA
;New data to xmit
DS39582C-page 74
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.3.3
ENABLING SPI I/O
9.3.4
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC bit cleared
• SCK (Master mode) must have TRISC bit
cleared
• SCK (Slave mode) must have TRISC bit set
• SS must have TRISC bit set
TYPICAL CONNECTION
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 9-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer
(SSPBUF)
LSb
2001-2013 Microchip Technology Inc.
Shift Register
(SSPSR)
MSb
SCK
PROCESSOR 1
SDO
Serial Clock
LSb
SCK
PROCESSOR 2
DS39582C-page 75
PIC16F87XA
9.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON). This then, would give
waveforms for SPI communication as shown in
FIGURE 9-3:
Figure 9-3, Figure 9-5 and Figure 9-6, where the MSB
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the
following:
•
•
•
•
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 9-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 7
bit 0
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
DS39582C-page 76
Next Q4 Cycle
after Q2
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
the SS pin goes high, the SDO pin is no longer driven
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable, depending on the application.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON = 0100),
the SPI module will reset if the SS pin is set
to VDD.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
2: If the SPI is used in Slave Mode with CKE
set, then the SS pin control must be
enabled.
9.3.7
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON = 04h). The pin must not be driven low
for the SS pin to function as an input. The data latch
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
FIGURE 9-4:
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
2001-2013 Microchip Technology Inc.
Next Q4 Cycle
after Q2
DS39582C-page 77
PIC16F87XA
FIGURE 9-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
bit 7
SDI
(SMP = 0)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 Cycle
after Q2
SSPSR to
SSPBUF
FIGURE 9-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 6
bit 7
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS39582C-page 78
Next Q4 Cycle
after Q2
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.3.8
SLEEP OPERATION
9.3.10
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 9-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 9-1:
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
9.3.9
EFFECTS OF A RESET
SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0
1
0, 1
0
0
1, 0
1
1
1, 1
1
0
There is also a SMP bit which controls when the data is
sampled.
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 9-2:
BUS MODE COMPATIBILITY
REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
INTCON
GIE/
GIEH
PEIE/
GIEL
Bit 5
Bit 4
TMR0IE INT0IE
Value on
all other
Resets
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPCON
TRISA
SSPSTAT
WCOL
—
SMP
SSPOV SSPEN
CKP
SSPM3
SSPM2
SSPM1 SSPM0 0000 0000 0000 0000
PORTA Data Direction Register
CKE
D/A
P
--11 1111 --11 1111
S
R/W
UA
BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc.
DS39582C-page 79
PIC16F87XA
9.4
I2C Mode
9.4.1
The MSSP module in I 2C mode fully implements all
master and slave functions (including general call support) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC bits.
FIGURE 9-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
Shift
Clock
SSPSR reg
RC4/SDI/
SDA
LSb
MSb
Match Detect
Addr Match
DS39582C-page 80
•
•
•
•
MSSP Control Register (SSPCON)
MSSP Control Register 2 (SSPCON2)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPADD reg
Start and
Stop bit Detect
The MSSP module has six registers for I2C operation.
These are:
SSPADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
SSPBUF reg
RC3/SCK/SCL
REGISTERS
Set, Reset
S, P bits
(SSPSTAT reg)
2001-2013 Microchip Technology Inc.
PIC16F87XA
REGISTER 9-3:
SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
bit 3
S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
bit 2
R/W: Read/Write bit information (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note:
This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Idle mode.
bit 1
UA: Update Address (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data Transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 81
PIC16F87XA
REGISTER 9-4:
SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for
a transmission to be started. (Must be cleared in software.)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be
cleared in software.)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. (Must be
cleared in software.)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables the serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be properly configured as input or output.
bit 4
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In Master mode:
Unused in this mode.
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
DS39582C-page 82
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
REGISTER 9-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) (ADDRESS 91h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master mode only)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is enabled for slave transmit only (PIC16F87X compatibility)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
x = Bit is unknown
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
2001-2013 Microchip Technology Inc.
DS39582C-page 83
PIC16F87XA
9.4.2
OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON).
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow
one of the following I 2C modes to be selected:
I2C Master mode, clock = OSC/4 (SSPADD + 1)
I 2C Slave mode (7-bit address)
I 2C Slave mode (10-bit address)
I 2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I 2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I 2C Firmware Controlled Master mode, slave is
Idle
•
•
•
•
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
9.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I 2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
9.4.3.1
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR is compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1.
2.
3.
4.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
MSSP Interrupt Flag bit, SSPIF (PIR1), is
set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit address is as follows, with steps 7 through 9 for
the slave-transmitter:
1.
2.
3.
4.
5.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The buffer full bit, BF (SSPSTAT), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON), was set
before the transfer was received.
Addressing
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
DS39582C-page 84
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.4.3.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the No Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT) is
set or bit SSPOV (SSPCON) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
If SEN is enabled (SSPCON = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data transfer. The clock must be released by setting bit CKP
(SSPCON). See Section 9.4.4 “Clock Stretching”
for more detail.
9.4.3.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is loaded
into the SSPBUF register. The ACK pulse will be sent on
the ninth bit and pin RC3/SCK/SCL is held low regardless of SEN (see Section 9.4.4 “Clock Stretching” for
more detail). By stretching the clock, the master will be
unable to assert another clock pulse until the slave is
done preparing the transmit data. The transmit data
must be loaded into the SSPBUF register, which also
loads the SSPSR register. Then pin RC3/SCK/SCL
should be enabled by setting bit CKP (SSPCON).
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 9-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
2001-2013 Microchip Technology Inc.
DS39582C-page 85
DS39582C-page 86
CKP
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
(CKP does not reset to ‘0’ when SEN = 0)
SSPOV (SSPCON)
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
A7
7
A1
8
9
ACK
R/W = 0
1
D7
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
SSPBUF is read
2
D6
6
D2
7
D1
8
D0
9
ACK
1
D7
2
D6
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
FIGURE 9-8:
SDA
PIC16F87XA
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
2001-2013 Microchip Technology Inc.
2001-2013 Microchip Technology Inc.
1
CKP
2
A6
Data in
sampled
BF (SSPSTAT)
SSPIF (PIR1)
S
A7
3
A5
4
A4
5
A3
6
A2
Receiving Address
7
A1
8
R/W = 1
9
ACK
SCL held low
while CPU
responds to SSPIF
1
D7
3
D5
4
D4
5
D3
6
D2
CKP is set in software
SSPBUF is written in software
Cleared in software
2
D6
Transmitting Data
7
8
D0
9
ACK
From SSPIF ISR
D1
1
D7
4
D4
5
D3
6
D2
CKP is set in software
7
8
D0
9
ACK
From SSPIF ISR
D1
Transmitting Data
Cleared in software
3
D5
SSPBUF is written in software
2
D6
P
FIGURE 9-9:
SCL
SDA
PIC16F87XA
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39582C-page 87
DS39582C-page 88
2
1
4
1
5
0
7
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
6
A9 A8
8
9
(CKP does not reset to ‘0’ when SEN = 0)
UA (SSPSTAT)
SSPOV (SSPCON)
CKP
3
1
Cleared in software
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
1
ACK
R/W = 0
A7
2
4
A4
5
A3
6
8
9
A0 ACK
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware
when SSPADD is updated
with low byte of address
7
A2 A1
Cleared in software
3
A5
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
1
D7
4
5
6
Cleared in software
3
7
8
9
1
2
4
5
6
Cleared in software
3
D3 D2
Receive Data Byte
D1 D0 ACK D7 D6 D5 D4
Cleared by hardware when
SSPADD is updated with high
byte of address
2
D3 D2
Receive Data Byte
D6 D5 D4
Clock is held low until
update of SSPADD has
taken place
7
8
D1 D0
9
P
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 9-10:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC16F87XA
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
2001-2013 Microchip Technology Inc.
2001-2013 Microchip Technology Inc.
2
CKP (SSPCON)
UA (SSPSTAT)
BF (SSPSTAT)
(PIR1)
SSPIF
1
S
SCL
1
4
1
5
0
6
7
A9 A8
UA is set indicating that
the SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
3
1
Receive First Byte of Address
1
8
9
ACK
1
3
4
5
Cleared in software
2
7
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address
6
A6 A5 A4 A3 A2 A1
8
A0
Receive Second Byte of Address
Dummy read of SSPBUF
to clear BF flag
A7
9
ACK
2
3
1
4
1
Cleared in software
1
1
5
0
6
8
9
ACK
R/W=1
1
2
4
5
6
CKP is set in software
9
P
Completion of
data transmission
clears BF flag
8
ACK
Bus master
terminates
transfer
CKP is automatically cleared in hardware holding SCL low
7
D4 D3 D2 D1 D0
Cleared in software
3
D7 D6 D5
Transmitting Data Byte
Clock is held low until
CKP is set to ‘1’
Write of SSPBUF
BF flag is clear
initiates transmit
at the end of the
third address sequence
7
A9 A8
Cleared by hardware when
SSPADD is updated with high
byte of address
Dummy read of SSPBUF
to clear BF flag
Sr
1
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
FIGURE 9-11:
SDA
R/W = 0
Clock is held low until
update of SSPADD has
taken place
PIC16F87XA
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
DS39582C-page 89
PIC16F87XA
9.4.4
CLOCK STRETCHING
Both 7 and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
9.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON register is
automatically cleared, forcing the SCL output to be
held low. The CKP bit being cleared to ‘0’ will assert
the SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 9-13).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
9.4.4.2
9.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the ninth
clock, if the BF bit is clear. This occurs regardless of the
state of the SEN bit.
The user’s ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 9-9).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
9.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 9-11).
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address, with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by reading the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching, on the basis of the
state of the BF bit, only occurs during a
data sequence, not an address sequence.
DS39582C-page 90
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.4.4.5
Clock Synchronization and the
CKP Bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the SCL line
until an external I2C master device has already
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I2C
bus have deasserted SCL. This ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 9-12).
FIGURE 9-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON
2001-2013 Microchip Technology Inc.
DS39582C-page 91
DS39582C-page 92
CKP
SSPOV (SSPCON)
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
A7
2
A6
3
4
A4
5
A3
Receiving Address
A5
6
A2
7
A1
8
9
ACK
R/W = 0
3
4
D4
5
D3
Receiving Data
D5
Cleared in software
2
D6
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
SSPBUF is read
1
D7
6
D2
7
D1
9
ACK
1
D7
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
8
D0
CKP
written
to ‘1’ in
software
2
D6
Clock is held low until
CKP is set to ‘1’
3
4
D4
5
D3
Receiving Data
D5
6
D2
7
D1
8
D0
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
9
ACK
Clock is not held low
because ACK = 1
FIGURE 9-13:
SDA
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
PIC16F87XA
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
2001-2013 Microchip Technology Inc.
2001-2013 Microchip Technology Inc.
2
1
UA (SSPSTAT)
SSPOV (SSPCON)
CKP
3
1
4
1
5
0
6
7
A9 A8
UA is set indicating that
SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR
Cleared in software
BF (SSPSTAT)
(PIR1)
SSPIF
1
SCL
S
1
8
9
ACK
R/W = 0
A7
2
4
A4
5
A3
6
8
A0
9
ACK
Note: An update of the SSPADD register
before the falling edge of the ninth clock
will have no effect on UA and UA will
remain set.
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
of ninth clock
7
A2 A1
Cleared in software
3
A5
Dummy read of SSPBUF
to clear BF flag
1
A6
Receive Second Byte of Address
2
4
5
6
Cleared in software
3
D3 D2
7
9
Note: An update of the SSPADD register
before the falling edge of the ninth clock
will have no effect on UA, and UA will
remain set.
8
ACK
1
4
5
6
Cleared in software
3
CKP written to ‘1’
in software
2
D3 D2
Receive Data Byte
D7 D6 D5 D4
Clock is held low until
CKP is set to ‘1’
D1 D0
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
of ninth clock
Dummy read of SSPBUF
to clear BF flag
1
D7 D6 D5 D4
Receive Data Byte
Clock is held low until
update of SSPADD has
taken place
7
8
9
Bus master
terminates
transfer
P
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D1 D0
ACK
Clock is not held low
because ACK = 1
FIGURE 9-14:
SDA
Receive First Byte of Address
Clock is held low until
update of SSPADD has
taken place
PIC16F87XA
I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
DS39582C-page 93
PIC16F87XA
9.4.5
GENERAL CALL ADDRESS
SUPPORT
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually determines
which device will be the slave addressed by the master.
The exception is the general call address which can
address all devices. When this address is used, all
devices should, in theory, respond with an Acknowledge.
When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 9-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 9-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to general call address.
After ACK, set interrupt.
R/W = 0
ACK D7
General Call Address
SDA
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
SCL
S
1
2
3
4
5
6
7
8
9
1
9
SSPIF
BF (SSPSTAT)
Cleared in software
SSPBUF is read
SSPOV (SSPCON)
‘0’
GCEN (SSPCON2)
‘1’
DS39582C-page 94
2001-2013 Microchip Technology Inc.
PIC16F87XA
MASTER MODE
Note:
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I 2C bus may be taken when the P bit is set or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I 2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write to the SSPBUF register, initiating
transmission of data/address.
Configure the I2C port to receive data.
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
FIGURE 9-16:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condition is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
•
•
•
•
•
Start condition
Stop condition
Data transfer byte transmitted/received
Acknowledge transmit
Repeated Start
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
SSPM3:SSPM0
SSPADD
Internal
Data Bus
Read
Write
SSPBUF
Baud
Rate
Generator
Shift
Clock
SDA
SDA In
SCL In
Bus Collision
2001-2013 Microchip Technology Inc.
LSb
Start bit, Stop bit,
Acknowledge
Generate
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
Clock Cntl
SCL
Receive Enable
SSPSR
MSb
Clock Arbitrate/WCOL Detect
(hold off clock source)
9.4.6
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
DS39582C-page 95
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9.4.6.1
I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning
and end of transmission.
The baud rate generator used for the SPI mode operation is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 9.4.7 “Baud Rate Generator” for more detail.
DS39582C-page 96
A typical transmit sequence would go as follows:
1.
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2).
2. SSPIF is set. The MSSP module will wait the
required Start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2).
12. Interrupt is generated once the Stop condition is
complete.
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.4.7
BAUD RATE GENERATOR
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 9-17). When a write occurs to
SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
FIGURE 9-17:
Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 9-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPM3:SSPM0
Reload
SCL
Control
CLKO
Reload
BRG Down Counter
FOSC/4
I2C CLOCK RATE W/BRG
TABLE 9-3:
Note 1:
SSPADD
FCY
FCY*2
BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz
20 MHz
19h
400 kHz(1)
10 MHz
20 MHz
20h
312.5 kHz
10 MHz
20 MHz
3Fh
100 kHz
4 MHz
8 MHz
0Ah
400 kHz(1)
4 MHz
8 MHz
0Dh
308 kHz
4 MHz
8 MHz
28h
100 kHz
1 MHz
2 MHz
03h
333 kHz(1)
1 MHz
2 MHz
0Ah
100 kHz
1 MHz
2 MHz
00h
1 MHz(1)
I2C
I2C
The
interface does not conform to the 400 kHz
specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2001-2013 Microchip Technology Inc.
DS39582C-page 97
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9.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 9-18:
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 9-17).
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
DS39582C-page 98
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.4.8
I2C MASTER MODE START
CONDITION TIMING
9.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
To initiate a Start condition, the user sets the Start condition enable bit, SEN (SSPCON2). If the SDA and
SCL pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPADD and
starts its count. If SCL and SDA are both sampled high
when the Baud Rate Generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the Start condition and
causes the S bit (SSPSTAT) to be set. Following
this, the Baud Rate Generator is reloaded with the contents of SSPADD and resumes its count. When
the Baud Rate Generator times out (TBRG), the SEN bit
(SSPCON2) will be automatically cleared by hardware, the Baud Rate Generator is suspended, leaving
the SDA line held low and the Start condition is
complete.
Note:
WCOL Status Flag
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
If at the beginning of the Start condition,
the SDA and SCL pins are already sampled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
FIGURE 9-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT)
Write to SEN bit occurs here
SDA = 1,
SCL = 1
TBRG
At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
TBRG
Write to SSPBUF occurs here
1st Bit
SDA
2nd Bit
TBRG
SCL
TBRG
S
2001-2013 Microchip Technology Inc.
DS39582C-page 99
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9.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After
the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
A Repeated Start condition occurs when the RSEN bit
(SSPCON2) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the
contents of SSPADD and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
9.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t
occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 9-20:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT)
Write to SSPCON2
occurs here,
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG
TBRG
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
1st Bit
SDA
Falling edge of ninth clock,
end of Xmit
SCL
Write to SSPBUF occurs here
TBRG
TBRG
Sr = Repeated Start
DS39582C-page 100
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.4.10
I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification, parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification,
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time, if an
address match occurred or if data was received properly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 9-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2).
Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
9.4.10.1
9.4.10.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does Not Acknowledge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
9.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After the
falling edge of the eighth clock, the receive enable flag
is automatically cleared, the contents of the SSPSR are
loaded into the SSPBUF, the BF flag bit is set, the
SSPIF flag bit is set and the Baud Rate Generator is
suspended from counting, holding SCL low. The MSSP
is now in Idle state, awaiting the next command. When
the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge
bit at the end of reception by setting the Acknowledge
Sequence Enable bit, ACKEN (SSPCON2).
9.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
9.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
9.4.11.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
BF Status Flag
In Transmit mode, the BF bit (SSPSTAT) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.
9.4.10.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
2001-2013 Microchip Technology Inc.
DS39582C-page 101
DS39582C-page 102
S
R/W
PEN
SEN
BF (SSPSTAT)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
3
4
5
Cleared in software
2
6
7
8
After Start condition, SEN cleared by hardware
SSPBUF written
1
9
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W.
Start transmit.
A7
Transmit Address to Slave
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
SSPBUF is written in software
Cleared in software service routine
from SSP interrupt
2
D6
Transmitting Data or Second Half
of 10-bit Address
From Slave, clear ACKSTAT bit SSPCON2
P
Cleared in software
9
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 9-21:
SEN = 0
Write SSPCON2 SEN = 1
Start condition begins
PIC16F87XA
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
2001-2013 Microchip Technology Inc.
2001-2013 Microchip Technology Inc.
S
ACKEN
SSPOV
BF
(SSPSTAT)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
SCL
SDA
1
2
4
5
6
Cleared in software
3
7
8
9
2
3
5
6
7
8
9
Receiving Data from Slave
2
3
4
5
6
7
8
9
ACK is not sent
ACK
Cleared in software
Set SSPIF interrupt
at end of Acknowledge
sequence
SSPOV is set because
SSPBUF is still full
Cleared in
software
Data shifted in on falling edge of CLK Set SSPIF at end
of receive
1
D0
P
Bus master
terminates
transfer
Set P bit
(SSPSTAT)
and SSPIF
Set SSPIF interrupt
at end of Acknowledge sequence
PEN bit = 1
written here
Set ACKEN, start Acknowledge sequence,
SDA = ACKDT = 1
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Set SSPIF interrupt
at end of receive
4
Cleared in software
1
ACK
RCEN = 1, start
next receive
ACK from master
SDA = ACKDT = 0
FIGURE 9-22:
Master configured as a receiver
by programming SSPCON2 (RCEN = 1)
SEN = 0
Write to SSPBUF occurs here,
RCEN cleared
start XMIT
automatically
ACK from Slave
Transmit Address to Slave
Receiving Data from Slave
R/W = 1
A7 A6 A5 A4 A3 A2 A1
ACK D7 D6 D5 D4 D3 D2 D1
D0
Write to SSPCON2 (SEN = 1),
begin Start condition
Write to SSPCON2
to start Acknowledge sequence,
SDA = ACKDT (SSPCON2) = 0
PIC16F87XA
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS39582C-page 103
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9.4.12
ACKNOWLEDGE SEQUENCE
TIMING
9.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and
counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT) is
set. A TBRG later, the PEN bit is cleared and the SSPIF
bit is set (Figure 9-24).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the baud rate generator is turned off and the
MSSP module then goes into Idle mode (Figure 9-23).
9.4.12.1
9.4.13.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t
occur).
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 9-23:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
TBRG
SDA
SCL
TBRG
ACK
D0
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 9-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT) is set.
Write to SSPCON2,
set PEN
Falling edge of
9th clock
TBRG
SCL
SDA
PEN bit (SSPCON2) is cleared by
hardware and the SSPIF bit is set
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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PIC16F87XA
9.4.14
SLEEP OPERATION
9.4.17
2
While in Sleep mode, the I C module can receive
addresses or data and when an address match or complete byte transfer occurs, wake the processor from
Sleep (if the MSSP interrupt is enabled).
9.4.15
EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
9.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit (SSPSTAT) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is at
the expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its Idle state (Figure 9-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the SSPCON2 register
are cleared. When the user services the bus collision
Interrupt Service Routine and if the I2C bus is free, the
user can resume communication by asserting a Start
condition.
The Master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register or
the bus is Idle and the S and P bits are cleared.
FIGURE 9-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
SDA line pulled low
by another source
SDA released
by master
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master. Bus collision has occurred.
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
2001-2013 Microchip Technology Inc.
DS39582C-page 105
PIC16F87XA
9.4.17.1
Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a)
b)
SDA or SCL are sampled low at the beginning of
the Start condition (Figure 9-26).
SCL is sampled low before SDA is asserted low
(Figure 9-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 9-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0 and during this time, if the SCL pin is
sampled as ‘0’, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 9-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 9-26:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus collision because the two masters must be
allowed to arbitrate the first address following the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SEN
BCLIF
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
DS39582C-page 106
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 9-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
SSPIF
‘0’
‘0’
FIGURE 9-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
Set SSPIF
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
SDA = 0, SCL = 1,
set SSPIF
2001-2013 Microchip Technology Inc.
Interrupts cleared
in software
DS39582C-page 107
PIC16F87XA
9.4.17.2
Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(Figure 9-30).
A low level is sampled on SDA when SCL goes
from low level to high level.
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 9-29). If SDA is sampled high, the BRG is
FIGURE 9-29:
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
If at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
S
‘0’
SSPIF
‘0’
FIGURE 9-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
RSEN
S
‘0’
SSPIF
DS39582C-page 108
2001-2013 Microchip Technology Inc.
PIC16F87XA
9.4.17.3
Bus Collision During a Stop
Condition
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 9-31). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 9-32).
Bus collision occurs during a Stop condition if:
a)
b)
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 9-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG
TBRG
TBRG
SDA sampled
low after TBRG,
set BCLIF
SDA
SCL
SDA asserted low
PEN
BCLIF
P
‘0’
SSPIF
‘0’
FIGURE 9-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
Assert SDA
SCL goes low before SDA goes high,
set BCLIF
SCL
PEN
BCLIF
P
‘0’
SSPIF
‘0’
2001-2013 Microchip Technology Inc.
DS39582C-page 109
PIC16F87XA
NOTES:
DS39582C-page 110
2001-2013 Microchip Technology Inc.
PIC16F87XA
10.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 10-1:
Bit SPEN (RCSTA) and bits TRISC have to be
set in order to configure pins RC6/TX/CK and RC7/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter.
The USART module also has a multi-processor
communication capability using 9-bit address detection.
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as ‘0’
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of Transmit Data, can be Parity bit
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 111
PIC16F87XA
REGISTER 10-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when RSR
is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware)
Legend:
DS39582C-page 112
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F87XA
10.1
USART Baud Rate Generator
(BRG)
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16 (X + 1)) equation can reduce the
baud rate error in some cases.
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
10.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1:
SAMPLING
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64 (X + 1))
(Synchronous) Baud Rate = FOSC/(4 (X + 1))
Baud Rate = FOSC/(16 (X + 1))
N/A
Legend: X = value in SPBRG (0 to 255)
TABLE 10-2:
Address
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Value on
all other
Resets
Bit 2
Bit 1
—
BRGH
TRMT
FERR
OERR RX9D 0000 000x 0000 000x
98h
TXSTA
CSRC
TX9
TXEN SYNC
18h
RCSTA
SPEN
RX9
SREN CREN ADDEN
99h
SPBRG Baud Rate Generator Register
Bit 0
Value on:
POR, BOR
Bit 3
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
2001-2013 Microchip Technology Inc.
DS39582C-page 113
PIC16F87XA
TABLE 10-3:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
BAUD
RATE
(K)
%
ERROR
KBAUD
FOSC = 16 MHz
SPBRG
value
(decimal)
%
ERROR
KBAUD
FOSC = 10 MHz
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
-
-
-
-
-
-
-
-
-
1.2
1.221
1.75
255
1.202
0.17
207
1.202
0.17
129
2.4
2.404
0.17
129
2.404
0.17
103
2.404
0.17
64
9.6
9.766
1.73
31
9.615
0.16
25
9.766
1.73
15
19.2
19.531
1.72
15
19.231
0.16
12
19.531
1.72
7
28.8
31.250
8.51
9
27.778
3.55
8
31.250
8.51
4
33.6
34.722
3.34
8
35.714
6.29
6
31.250
6.99
4
57.6
62.500
8.51
4
62.500
8.51
3
52.083
9.58
2
HIGH
1.221
-
255
0.977
-
255
0.610
-
255
LOW
312.500
-
0
250.000
-
0
156.250
-
0
FOSC = 4 MHz
BAUD
RATE
(K)
KBAUD
FOSC = 3.6864 MHz
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
0.300
0
207
0.3
0
191
1.2
1.202
0.17
51
1.2
0
47
2.4
2.404
0.17
25
2.4
0
23
9.6
8.929
6.99
6
9.6
0
5
19.2
20.833
8.51
2
19.2
0
2
28.8
31.250
8.51
1
28.8
0
1
33.6
-
-
-
-
-
-
57.6
62.500
8.51
0
57.6
0
0
HIGH
0.244
-
255
0.225
-
255
LOW
62.500
-
0
57.6
-
0
TABLE 10-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
FOSC = 16 MHz
BAUD
RATE
(K)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
-
-
1.2
-
-
2.4
-
FOSC = 10 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
-
-
-
-
-
-
-
-
KBAUD
%
ERROR
SPBRG
value
(decimal)
-
-
-
-
-
-
-
-
-
-
2.441
1.71
255
9.6
9.615
0.16
129
9.615
0.16
103
9.615
0.16
64
19.2
19.231
0.16
64
19.231
0.16
51
19.531
1.72
31
28.8
29.070
0.94
42
29.412
2.13
33
28.409
1.36
21
33.6
33.784
0.55
36
33.333
0.79
29
32.895
2.10
18
57.6
59.524
3.34
20
58.824
2.13
16
56.818
1.36
10
HIGH
4.883
-
255
3.906
-
255
2.441
-
255
LOW
1250.000
-
0
1000.000
0
625.000
-
0
FOSC = 4 MHz
BAUD
RATE
(K)
KBAUD
FOSC = 3.6864 MHz
%
ERROR
SPBRG
value
(decimal)
KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3
-
-
-
-
-
-
1.2
1.202
0.17
207
1.2
0
191
2.4
2.404
0.17
103
2.4
0
95
9.6
9.615
0.16
25
9.6
0
23
19.2
19.231
0.16
12
19.2
0
11
28.8
27.798
3.55
8
28.8
0
7
33.6
35.714
6.29
6
32.9
2.04
6
57.6
62.500
8.51
3
57.6
0
3
HIGH
0.977
-
255
0.9
-
255
LOW
250.000
-
0
230.4
-
0
DS39582C-page 114
2001-2013 Microchip Technology Inc.
PIC16F87XA
10.2
USART Asynchronous Mode
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA),
shows the status of the TSR register. Status bit TRMT
is a read-only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR
register is empty.
In this mode, the USART uses standard Non-Returnto-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip, dedicated, 8-bit Baud Rate
Generator can be used to derive standard baud rate
frequencies from the oscillator. The USART transmits
and receives the LSb first. The transmitter and receiver
are functionally independent but use the same data
format and baud rate. The baud rate generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA). Parity is not
supported by the hardware but can be implemented in
software (and stored as the ninth data bit).
Asynchronous mode is stopped during Sleep.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA).
Transmission is enabled by setting enable bit, TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data
and the Baud Rate Generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to high-impedance.
The USART Asynchronous module consists of the
following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
10.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit, TXIF (PIR1), is set. This interrupt can be
FIGURE 10-1:
In order to select 9-bit transmission, transmit bit TX9
(TXSTA) should be set and the ninth bit should be
written to TX9D (TXSTA). The ninth bit must be
written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
2001-2013 Microchip Technology Inc.
DS39582C-page 115
PIC16F87XA
When setting up an Asynchronous Transmission,
follow these steps:
5.
1.
6.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
2.
3.
4.
FIGURE 10-2:
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
7.
8.
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Bit 1
Word 1
Bit 7/8
Stop Bit
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 10-3:
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 1
Transmit Shift Reg.
Stop Bit
Start Bit
Word 2
Bit 0
Word 2
Transmit Shift Reg.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
Bit 7/8
This timing diagram shows two consecutive transmissions.
TABLE 10-5:
Address
Bit 1
Word 1
PIR1
18h
RCSTA
19h
TXREG
8Ch
PIE1
98h
TXSTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
USART Transmit Register
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
SSPIE CCP1IE
—
BRGH
TMR2IE
TMR1IE
0000 0000
0000 0000
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
99h
SPBRG Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582C-page 116
2001-2013 Microchip Technology Inc.
PIC16F87XA
10.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter, operating at x16 times the
baud rate; whereas the main receive serial shifter
operates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA).
The heart of the receiver is the Receive (Serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit, RCIF (PIR1), is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit, RCIE
(PIE1). Flag bit RCIF is a read-only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
FIGURE 10-4:
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte, if the RCREG register is
still full, the Overrun Error bit, OERR (RCSTA), will
be set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhibited and no further data will be received. It is, therefore,
essential to clear error bit OERR if it is set. Framing
error bit, FERR (RCSTA), is set if a Stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register in
order not to lose the old FERR and RX9D information.
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
Baud Rate Generator
64
or
16
RSR Register
MSb
Stop (8)
7
1
LSb
0
Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
2001-2013 Microchip Technology Inc.
DS39582C-page 117
PIC16F87XA
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX (pin)
bit 1
bit 7/8 Stop
bit
Rcv Shift
Reg
Rcv Buffer Reg
Start
bit
bit 7/8
bit 0
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
Stop
bit
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
When setting up an Asynchronous Reception, follow
these steps:
1.
2.
3.
4.
5.
6.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
TABLE 10-6:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
18h
RCSTA
1Ah
RCREG USART Receive Register
8Ch
PIE1
98h
TXSTA
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
OERR
RX9D
SSPIE CCP1IE TMR2IE TMR1IE
—
BRGH
TRMT
TX9D
99h
SPBRG
Legend:
Note 1:
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582C-page 118
Baud Rate Generator Register
FERR
2001-2013 Microchip Technology Inc.
PIC16F87XA
10.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
When setting up an Asynchronous Reception with
address detect enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
FIGURE 10-6:
• Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be read into the receive buffer and interrupt the
CPU.
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
Baud Rate Generator
64
or
16
RSR Register
MSb
Stop
(8)
7
1
LSb
0
Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
ADDEN
Enable
Load of
RX9
ADDEN
RSR
Receive
Buffer
8
RX9D
RCREG Register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
2001-2013 Microchip Technology Inc.
DS39582C-page 119
PIC16F87XA
FIGURE 10-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
Start
bit
RC7/RX/DT
(pin)
bit 0
bit 1
bit 8
Stop
bit
Start
bit
bit 0
bit 8
Stop
bit
Load RSR
Bit 8 = 0, Data Byte
Word 1
RCREG
Bit 8 = 1, Address Byte
Read
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
FIGURE 10-8:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
Start
bit bit 0
RC7/RX/DT
(pin)
bit 1
bit 8
Stop
bit
Start
bit
bit 0
bit 8
Stop
bit
Load RSR
Bit 8 = 1, Address Byte
Word 1
RCREG
Bit 8 = 0, Data Byte
Read
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
TABLE 10-7:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG
Legend:
Note 1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
0000 000x
0000 000x
CREN ADDEN
FERR
OERR
RX9D
USART Receive Register
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CSRC
TX9
TXEN
SYNC
—
Baud Rate Generator Register
CCP1IE TMR2IE TMR1IE
BRGH
TRMT
TX9D
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582C-page 120
2001-2013 Microchip Technology Inc.
PIC16F87XA
10.3
USART Synchronous
Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA). In
addition, enable bit, SPEN (RCSTA), is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit, CSRC (TXSTA).
10.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-6. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA),
shows the status of the TSR register. TRMT is a readonly bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty. The
TSR is not mapped in data memory so it is not available
to the user.
Transmission is enabled by setting enable bit, TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is
stable around the falling edge of the synchronous clock
(Figure 10-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-10). This is advantageous when slow
baud rates are selected since the BRG is kept in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty so a transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
2001-2013 Microchip Technology Inc.
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to highimpedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a high-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from HighImpedance Receive mode to transmit and start driving.
To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
DS39582C-page 121
PIC16F87XA
TABLE 10-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
18h
RCSTA
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
SPBRG
Legend:
Note 1:
BRGH
TRMT
TX9D
Baud Rate Generator Register
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
FIGURE 10-9:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2Q3 Q4Q1Q2Q3 Q4Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
Word 1
Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4
bit 7
bit 0
bit 1
Word 2
bit 7
RC6/TX/CK
pin
Write to
TXREG reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
‘1’
‘1’
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 10-10:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
DS39582C-page 122
2001-2013 Microchip Technology Inc.
PIC16F87XA
10.3.2
USART SYNCHRONOUS MASTER
RECEPTION
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCSTA), or enable bit, CREN (RCSTA). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit, RCIF
(PIR1), is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit, RCIE
(PIE1). Flag bit RCIF is a read-only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double-buffered register (i.e., it is a twodeep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then Overrun Error bit, OERR
(RCSTA), is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
TABLE 10-9:
Address
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG
Legend:
Note 1:
When setting up a Synchronous Master Reception:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
USART Receive Register
(1)
PSPIE
CSRC
ADIE
RCIE
TXIE
SSPIE
TX9
TXEN
SYNC
—
Baud Rate Generator Register
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
2001-2013 Microchip Technology Inc.
DS39582C-page 123
PIC16F87XA
FIGURE 10-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK
pin
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
10.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit, CSRC (TXSTA).
10.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
2.
3.
4.
5.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
6.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
7.
a)
b)
c)
d)
e)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
DS39582C-page 124
8.
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SPEN
RX9
SREN
CREN
ADDEN
0Ch
PIR1
18h
RCSTA
19h
TXREG
USART Transmit Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CSRC
TX9
TXEN
SYNC
—
98h
TXSTA
99h
SPBRG
Legend:
Note 1:
10.4.2
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
BRGH
TRMT
TX9D
Baud Rate Generator Register
0000 -010 0000 -010
0000 0000 0000 0000
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
When setting up a Synchronous Slave Reception,
follow these steps:
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don't care” in Slave mode.
1.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
2.
3.
4.
5.
6.
7.
8.
9.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
R0IF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
USART Receive Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
SPBRG
Legend:
Note 1:
TMR1IF 0000 0000 0000 0000
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
Baud Rate Generator Register
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.
2001-2013 Microchip Technology Inc.
DS39582C-page 125
PIC16F87XA
NOTES:
DS39582C-page 126
2001-2013 Microchip Technology Inc.
PIC16F87XA
11.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has four registers. These registers are:
The Analog-to-Digital (A/D) Converter module has five
inputs for the 28-pin devices and eight for the 40/44-pin
devices.
The conversion of an analog input signal results in a
corresponding 10-bit digital number. The A/D module
has high and low-voltage reference input that is software selectable to some combination of VDD, VSS, RA2
or RA3.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D clock must be derived from
the A/D’s internal RC oscillator.
REGISTER 11-1:
ADCS1
bit 7
bit 5-3
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the functions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be the voltage
reference) or as digital I/O.
Additional information on using the A/D module can be
found in the PIC® Mid-Range MCU Family Reference
Manual (DS33023).
ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0
bit 7-6
•
•
•
•
R/W-0
R/W-0
ADCS0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
GO/DONE
—
R/W-0
ADON
bit 0
ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
ADCON1
ADCON0
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
Clock Conversion
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (AN0)
001 = Channel 1 (AN1)
010 = Channel 2 (AN2)
011 = Channel 3 (AN3)
100 = Channel 4 (AN4)
101 = Channel 5 (AN5)
110 = Channel 6 (AN6)
111 = Channel 7 (AN7)
Note:
bit 2
bit 1
bit 0
The PIC16F873A/876A devices only implement A/D channels 0 through 4; the
unimplemented selections are reserved. Do not select any unimplemented
channels with these devices.
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A/D conversion not in progress
Unimplemented: Read as ‘0’
ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 127
PIC16F87XA
REGISTER 11-2:
ADCON1 REGISTER (ADDRESS 9Fh)
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bit 6
ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in shaded area and in bold)
ADCON1
ADCON0
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
00
01
10
11
00
01
10
11
0
0
0
0
1
1
1
1
Clock Conversion
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG
AN7
AN6
AN5
AN4
0000
A
A
A
A
A
A
A
A
0001
A
A
A
A
VREF+
A
A
A
0010
D
D
D
A
A
A
A
A
0011
D
D
D
A
VREF+
A
A
A
0100
D
D
D
D
A
D
A
A
0101
D
D
D
D
VREF+
D
A
A
011x
D
D
D
D
D
D
D
D
1000
A
A
A
A
VREF+
VREF-
A
A
1001
D
D
A
A
A
A
A
A
1010
D
D
A
A
VREF+
A
A
A
AN3
AN2
AN1
AN0
VREF+
VREF-
C/R
VDD
VSS
8/0
AN3
VSS
7/1
VDD
VSS
5/0
AN3
VSS
4/1
VDD
VSS
3/0
AN3
VSS
2/1
—
—
0/0
AN3
AN2
6/2
VDD
VSS
6/0
AN3
VSS
5/1
1011
D
D
A
A
VREF+
VREF-
A
A
AN3
AN2
4/2
1100
D
D
D
A
VREF+
VREF-
A
A
AN3
AN2
3/2
1101
D
D
D
D
VREF+
VREF-
A
A
AN3
AN2
2/2
1110
D
D
D
D
D
D
D
A
VDD
VSS
1/0
1111
D
D
D
D
VREF+
VREF-
D
A
AN3
AN2
1/2
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
DS39582C-page 128
x = Bit is unknown
On any device Reset, the port pins that are multiplexed with analog functions (ANx)
are forced to be an analog input.
2001-2013 Microchip Technology Inc.
PIC16F87XA
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D Result
register pair, the GO/DONE bit (ADCON0) is cleared
and the A/D interrupt flag bit ADIF is set. The block
diagram of the A/D module is shown in Figure 11-1.
2.
3.
4.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
5.
To determine sample time, see Section 11.1 “A/D
Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be started.
6.
To do an A/D Conversion, follow these steps:
1.
Configure the A/D module:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 11-1:
7.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
(interrupts disabled); OR
• Waiting for the A/D interrupt
Read
A/D
Result
register
pair
(ADRESH:ADRESL), clear bit ADIF if required.
For the next conversion, go to step 1 or step 2
as required. The A/D conversion time per bit is
defined as TAD.
A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
100
RA5/AN4
VAIN
011
(Input Voltage)
A/D
Converter
RA3/AN3/VREF+
010
RA2/AN2/VREF001
RA1/AN1
VDD
000
RA0/AN0
VREF+
(Reference
Voltage)
PCFG3:PCFG0
VREF(Reference
Voltage)
VSS
PCFG3:PCFG0
Note 1: Not available on 28-pin devices.
2001-2013 Microchip Technology Inc.
DS39582C-page 129
PIC16F87XA
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch
impedance (RSS) directly affect the time required to
charge the capacitor CHOLD. The sampling switch
(RSS) impedance varies over the device voltage (VDD);
see Figure 11-2. The maximum recommended
impedance for analog sources is 2.5 k. As the
impedance is decreased, the acquisition time may be
EQUATION 11-1:
TACQ
TC
TACQ
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
ACQUISITION TIME
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120 pF (1 k + 7 k + 10 k) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25C)(0.05 s/C)
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 2.5 k. This is required to meet the pin
leakage specification.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD
RS
VA
ANx
CPIN
5 pF
VT = 0.6V
VT = 0.6V
Sampling
Switch
RIC 1K SS RSS
CHOLD
= DAC Capacitance
= 120 pF
ILEAKAGE
± 500 nA
VSS
Legend: CPIN
= input capacitance
= threshold voltage
VT
ILEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
DS39582C-page 130
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
2001-2013 Microchip Technology Inc.
PIC16F87XA
11.2
Selecting the A/D Conversion
Clock
11.3
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires a minimum 12 TAD per 10-bit
conversion. The source of the A/D conversion clock is
software selected. The seven possible options for TAD
are:
•
•
•
•
•
•
•
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal A/D module RC oscillator (2-6 s)
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins configured as digital inputs will convert an analog
input. Analog levels on a digitally configured input will not affect the conversion
accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins) may cause the input buffer to consume current that is out of the device
specifications.
Table 11-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 11-1:
Configuring Analog Port Pins
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (F))
AD Clock Source (TAD)
Maximum Device Frequency
Note 1:
2:
3:
Operation
ADCS2:ADCS1:ADCS0
2 TOSC
000
1.25 MHz
4 TOSC
100
2.5 MHz
8 TOSC
001
5 MHz
16 TOSC
101
10 MHz
32 TOSC
010
20 MHz
64 TOSC
110
20 MHz
RC(1, 2, 3)
x11
(Note 1)
The RC source has a typical TAD time of 4 s but can vary between 2-6 s.
When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for Sleep operation.
For extended voltage devices (LF), please refer to Section 17.0 “Electrical Characteristics”.
2001-2013 Microchip Technology Inc.
DS39582C-page 131
PIC16F87XA
11.4
A/D Conversions
is aborted, the next acquisition on the selected channel
is automatically started. The GO/DONE bit can then be
set to start the conversion.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
FIGURE 11-3:
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of TCY and a maximum of TAD.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b9
b8
b7
b6
b5
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
11.4.1
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 11-4:
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general
purpose 8-bit registers.
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 0
ADFM = 1
7
0
2107
7
0765
0000 00
0000 00
ADRESH
ADRESL
10-bit Result
Right Justified
DS39582C-page 132
0
ADRESH
ADRESL
10-bit Result
Left Justified
2001-2013 Microchip Technology Inc.
PIC16F87XA
11.5
A/D Operation During Sleep
Note:
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
11.6
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the conversion to occur during Sleep, ensure the
SLEEP instruction immediately follows the
instruction that sets the GO/DONE bit.
Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers is
not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
TABLE 11-2:
REGISTERS/BITS ASSOCIATED WITH A/D
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Value on
POR, BOR MCLR, WDT
0Bh,8Bh,
INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE TMR1IE 0000 0000 0000 0000
1Eh
ADRESH A/D Result Register High Byte
9Eh
ADRESL A/D Result Register Low Byte
1Fh
ADCON0
ADCS1 ADCS0
9Fh
ADCON1
ADFM
ADCS2
85h
TRISA
—
—
PORTA Data Direction Register
05h
PORTA
—
—
PORTA Data Latch when written: PORTA pins when read
89h(1)
TRISE
IBF
OBF
IBOV
PSPMODE
—
09h(1)
PORTE
—
—
—
—
—
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
These registers are not available on 28-pin devices.
2001-2013 Microchip Technology Inc.
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
—
—
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
00-- 0000
--11 1111 --11 1111
--0x 0000 --0u 0000
PORTE Data Direction bits
RE2
RE1
RE0
0000 -111 0000 -111
---- -xxx ---- -uuu
DS39582C-page 133
PIC16F87XA
NOTES:
DS39582C-page 134
2001-2013 Microchip Technology Inc.
PIC16F87XA
12.0
COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed
with I/O port pins RA0 through RA3, while the outputs
are multiplexed to pins RA4 and RA5. The on-chip voltage reference (Section 13.0 “Comparator Voltage
Reference Module”) can also be an input to the
comparators.
REGISTER 12-1:
The CMCON register (Register 12-1) controls the comparator input and output multiplexers. A block diagram
of the various comparator configurations is shown in
Figure 12-1.
CMCON REGISTER
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4
C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RA3/AN3
C2 VIN- connects to RA2/AN2
0 = C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2
CM2:CM0: Comparator Mode bits
Figure 12-1 shows the Comparator modes and CM2:CM0 bit settings.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 135
PIC16F87XA
12.1
Comparator Configuration
There are eight modes of operation for the comparators. The CMCON register is used to select these
modes. Figure 12-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
FIGURE 12-1:
RA3/AN3
RA1/AN1
RA2/AN2
VIN-
A
VIN+
A
VINVIN+
RA0/AN0
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
RA3/AN3
A
VIN-
A
VIN+
RA3/AN3
RA1/AN1
RA2/AN2
RA0/AN0
C1
D
VIN-
D
VIN+
D
VIN-
D
VIN+
C1
Off (Read as ‘0’)
C2
Off (Read as ‘0’)
Two Independent Comparators with Outputs
CM2:CM0 = 011
Two Independent Comparators
CM2:CM0 = 010
RA0/AN0
Comparator interrupts should be disabled
during a Comparator mode change.
Otherwise, a false interrupt may occur.
Comparators Off (POR Default Value)
CM2:CM0 = 111
A
A
Note:
COMPARATOR I/O OPERATING MODES
Comparators Reset
CM2:CM0 = 000
RA0/AN0
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 17.0 “Electrical Characteristics”.
C1OUT
RA3/AN3
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
RA4/T0CKI/C1OUT
RA1/AN1
RA2/AN2
A
A
VINVIN+
C2
C2OUT
RA1/AN1
RA2/AN2
A
VIN-
A
VIN+
RA5/AN4/SS/C2OUT
Two Common Reference Comparators
CM2:CM0 = 100
RA0/AN0
RA3/AN3
A
Two Common Reference Comparators with Outputs
CM2:CM0 = 101
VIN-
A
VIN+
A
VIN-
D
VIN+
RA0/AN0
C1
C1OUT
RA3/AN3
A
VIN-
A
VIN+
C1
C1OUT
C2
C2OUT
RA4/T0CKI/C1OUT
RA1/AN1
RA2/AN2
C2
C2OUT
RA1/AN1
RA2/AN2
A
VIN-
D
VIN+
RA5/AN4/SS/C2OUT
One Independent Comparator with Output
CM2:CM0 = 001
RA0/AN0
RA3/AN3
A
VIN-
A
VIN+
RA0/AN0
C1
C1OUT
RA4/T0CKI/C1OUT
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 110
RA3/AN3
RA1/AN1
RA2/AN2
C2
A
A
CIS = 0
CIS = 1
VINVIN+
C1
C1OUT
C2
C2OUT
A
A
CIS = 0
CIS = 1
VINVIN+
Off (Read as ‘0’)
CVREF From Comparator
VREF Module
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON) is the Comparator Input Switch.
DS39582C-page 136
2001-2013 Microchip Technology Inc.
PIC16F87XA
12.2
12.3.2
Comparator Operation
INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 12-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 12-2 represent
the uncertainty due to input offsets and response time.
The comparator module also allows the selection of an
internally generated voltage reference for the comparators. Section 13.0 “Comparator Voltage Reference
Module” contains a detailed description of the Comparator Voltage Reference module that provides this signal.
The internal reference signal is used when comparators
are in mode, CM = 110 (Figure 12-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
12.3
12.4
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 12-2).
FIGURE 12-2:
SINGLE COMPARATOR
Response time is the minimum time, after selecting a
new reference voltage or input source, before the comparator output has a valid level. If the internal reference
is changed, the maximum delay of the internal voltage
reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the
comparators should be used (Section 17.0 “Electrical
Characteristics”).
12.5
VIN+
+
VIN-
–
Output
VIN
VIN–
VIN
+
VIN+
Comparator Response Time
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA4 and RA5
I/O pins. When enabled, multiplexors in the output path
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 12-3 shows the
comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
Output
Output
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON).
12.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2001-2013 Microchip Technology Inc.
Note 1: When reading the Port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a digital input may cause the input buffer to
consume more current than is specified.
3: RA4 is an open collector I/O pin. When
used as an output, a pull-up resistor is
required.
DS39582C-page 137
PIC16F87XA
FIGURE 12-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
CxINV
To RA4 or
RA5 Pin
Bus
Data
Q
Read CMCON
Set
CMIF
bit
D
EN
Q
From
Other
Comparator
D
EN
CL
Read CMCON
Reset
12.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it (‘0’). Since it is
also possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
DS39582C-page 138
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of CMCON will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
2001-2013 Microchip Technology Inc.
PIC16F87XA
12.7
Comparator Operation During
Sleep
12.9
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current as shown in the comparator specifications. To minimize power consumption
while in Sleep mode, turn off the comparators,
CM = 111, before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
12.8
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 12-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.
Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the
Comparator Off mode, CM = 111. This ensures
compatibility to the PIC16F87X devices.
FIGURE 12-4:
ANALOG INPUT MODEL
VDD
VT = 0.6 V
RS < 10K
RIC
AIN
VA
CPIN
5 pF
VT = 0.6 V
ILEAKAGE
±500 nA
VSS
Legend:
CPIN
VT
ILEAKAGE
RIC
RS
VA
2001-2013 Microchip Technology Inc.
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
DS39582C-page 139
PIC16F87XA
TABLE 12-1:
Address
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
9Ch
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111 0000 0111
9Dh
CVRCON CVREN
CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
000- 0000 000- 0000
PEIE/
GIEL
TMR0IE
INTIE
RBIE
TMR0IF
INTIF
RBIF
0000 000x 0000 000u
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE/
GIEH
0Dh
PIR2
—
CMIF
—
—
BCLIF
LVDIF
TMR3IF CCP2IF
-0-- 0000 -0-- 0000
8Dh
PIE2
—
CMIE
—
—
BCLIE
LVDIE
TMR3IE CCP2IE
-0-- 0000 -0-- 0000
05h
PORTA
—
—
RA5
RA4
RA3
RA2
85h
TRISA
—
—
Legend:
PORTA Data Direction Register
RA1
RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
DS39582C-page 140
2001-2013 Microchip Technology Inc.
PIC16F87XA
13.0
COMPARATOR VOLTAGE
REFERENCE MODULE
The Comparator Voltage Reference Generator is a
16-tap resistor ladder network that provides a fixed
voltage reference when the comparators are in mode
‘110’. A programmable register controls the function of
the reference generator. Register 13-1 lists the bit
functions of the CVRCON register.
As shown in Figure 13-1, the resistor ladder is segmented to provide two ranges of CVREF values and has
a power-down function to conserve power when the
reference is not being used. The comparator reference
REGISTER 13-1:
supply voltage (also referred to as CVRSRC) comes
directly from VDD. It should be noted, however, that the
voltage at the top of the ladder is CVRSRC – VSAT,
where VSAT is the saturation voltage of the power
switch transistor. This reference will only be as
accurate as the values of CVRSRC and VSAT.
The output of the reference generator may be connected to the RA2/AN2/VREF-/CVREF pin. This can be
used as a simple D/A function by the user if a very highimpedance load is used. The primary purpose of this
function is to provide a test path for testing the
reference generator function.
CVRCON CONTROL REGISTER (ADDRESS 9Dh)
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1 = CVREF voltage level is output on RA2/AN2/VREF-/CVREF pin
0 = CVREF voltage level is disconnected from RA2/AN2/VREF-/CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.75 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4
Unimplemented: Read as ‘0’
bit 3-0
CVR3:CVR0: Comparator VREF Value Selection bits 0 VR3:VR0 15
When CVRR = 1:
CVREF = (VR/ 24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (VR3:VR0/ 32) (CVRSRC)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39582C-page 141
PIC16F87XA
FIGURE 13-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages
CVREN
8R
R
R
R
R
8R
CVRR
RA2/AN2/VREF-/CVREF
CVROE
CVREF
Input to
Comparator
TABLE 13-1:
Address
CVR3
CVR2
CVR1
CVR0
16:1 Analog MUX
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Name
Bit 7
Bit 6
Bit 5
9Dh
CVRCON CVREN CVROE CVRR
9Ch
CMCON
Value on
all other
Resets
Bit 3
Bit 2
Bit 1
—
CVR3
CVR2
CVR1
CVR0 000- 0000 000- 0000
CIS
CM2
CM1
CM0
C2OUT C1OUT C2INV C1INV
Bit 0
Value on
POR
Bit 4
0000 0111 0000 0111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
DS39582C-page 142
2001-2013 Microchip Technology Inc.
PIC16F87XA
14.0
SPECIAL FEATURES OF THE
CPU
All PIC16F87XA devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code
protection. These are:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
• Low-Voltage In-Circuit Serial Programming
• In-Circuit Debugger
Sleep mode is designed to offer a very low current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits is used to
select various options.
Additional information on special features is available
in the PIC® Mid-Range MCU Family Reference Manual
(DS33023).
14.1
Configuration Bits
The configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’) to select various
device configurations. The erased or unprogrammed
value of the Configuration Word register is 3FFFh.
These bits are mapped in program memory location
2007h.
It is important to note that address 2007h is beyond the
user program memory space which can be accessed
only during programming.
PIC16F87XA devices have a Watchdog Timer which
can be shut-off only through configuration bits. It runs
off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in
Reset while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
2001-2013 Microchip Technology Inc.
DS39582C-page 143
PIC16F87XA
REGISTER 14-1:
R/P-1
U-0
CP
—
CONFIGURATION WORD (ADDRESS 2007h)(1)
R/P-1
R/P-1
R/P-1 R/P-1 R/P-1
DEBUG WRT1 WRT0
CPD
LVP
R/P-1
U-0
U-0
BOREN
—
—
R/P-1
R/P-1
R/P-1
R/P-1
PWRTEN WDTEN FOSC1 FOSC0
bit 13
bit0
bit 13
CP: Flash Program Memory Code Protection bit
1 = Code protection off
0 = All program memory code-protected
bit 12
Unimplemented: Read as ‘1’
bit 11
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10-9
WRT1:WRT0 Flash Program Memory Write Enable bits
For PIC16F876A/877A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write-protected; 0100h to 1FFFh may be written to by EECON control
01 = 0000h to 07FFh write-protected; 0800h to 1FFFh may be written to by EECON control
00 = 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control
For PIC16F873A/874A:
11 = Write protection off; all program memory may be written to by EECON control
10 = 0000h to 00FFh write-protected; 0100h to 0FFFh may be written to by EECON control
01 = 0000h to 03FFh write-protected; 0400h to 0FFFh may be written to by EECON control
00 = 0000h to 07FFh write-protected; 0800h to 0FFFh may be written to by EECON control
bit 8
CPD: Data EEPROM Memory Code Protection bit
1 = Data EEPROM code protection off
0 = Data EEPROM code-protected
bit 7
LVP: Low-Voltage (Single-Supply) In-Circuit Serial Programming Enable bit
1 = RB3/PGM pin has PGM function; low-voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5-4
Unimplemented: Read as ‘1’
bit 3
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
Note 1: The erased (unprogrammed) value of the Configuration Word is 3FFFh.
DS39582C-page 144
2001-2013 Microchip Technology Inc.
PIC16F87XA
14.2
FIGURE 14-2:
Oscillator Configurations
14.2.1
OSCILLATOR TYPES
The PIC16F87XA can be operated in four different
oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKI and OSC2/CLKO pins
to establish oscillation (Figure 14-1). The PIC16F87XA
oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out
of the crystal manufacturer’s specifications. When in
XT, LP or HS modes, the device can have an external
clock source to drive the OSC1/CLKI pin (Figure 14-2).
C1(1)
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
OSC1
XTAL
OSC2
C2(1)
Rs(2)
To
Internal
Logic
RF(3)
PIC16F87XA
OSC2
Open
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
FIGURE 14-1:
OSC1
Clock from
Ext. System
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
Resistor/Capacitor
14.2.2
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC CONFIGURATION)
TABLE 14-1:
CERAMIC RESONATORS
Ranges Tested:
Mode
Freq.
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
These values are for design guidance only.
See notes following Table 14-2.
Resonators Used:
2.0 MHz
Murata Erie CSA2.00MG
0.5%
4.0 MHz
Murata Erie CSA4.00MG
0.5%
8.0 MHz
Murata Erie CSA8.00MT
0.5%
16.0 MHz
Murata Erie CSA16.00MX
0.5%
All resonators used did not have built-in capacitors.
Sleep
PIC16F87XA
Note 1: See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
2: A series resistor (Rs) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
2001-2013 Microchip Technology Inc.
DS39582C-page 145
PIC16F87XA
TABLE 14-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
Crystal
Freq.
Cap. Range
C1
Cap. Range
C2
LP
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
XT
HS
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
These values are for design guidance only.
See notes following this table.
14.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used. Figure 14-3 shows how the R/C
combination is connected to the PIC16F87XA.
FIGURE 14-3:
RC OSCILLATOR MODE
VDD
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
REXT
OSC1
CEXT
Internal
Clock
PIC16F87XA
VSS
FOSC/4
OSC2/CLKO
Recommended values:
3 k REXT 100 k
CEXT > 20 pF
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PIC® devices,
oscillator performance should be verified.
DS39582C-page 146
2001-2013 Microchip Technology Inc.
PIC16F87XA
14.3
Reset
The PIC16F87XA differentiates between various kinds
of Reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset (during normal operation)
WDT Wake-up (during Sleep)
Brown-out Reset (BOR)
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brownout Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differently in different Reset situations as indicated in
Table 14-4. These bits are used in software to determine the nature of the Reset. See Table 14-6 for a full
description of Reset states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 14-4.
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
FIGURE 14-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
Sleep
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BODEN
S
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
R
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT
Enable OST
Note 1:
This is a separate oscillator from the RC oscillator of the CLKI pin.
2001-2013 Microchip Technology Inc.
DS39582C-page 147
PIC16F87XA
14.4
MCLR
14.6
PIC16F87XA devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
differs from previous devices of this family. Voltages
applied to the pin that exceed its specification can
result in both Resets and current consumption outside
of device specification during the Reset event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an RCR
network, as shown in Figure 14-5, is suggested.
FIGURE 14-5:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC16F87XA
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in Reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable or
disable the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See
Section 17.0 “Electrical Characteristics” for details
(TPWRT, parameter #33).
14.7
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a delay of
1024 oscillator cycles (from OSC1 input) after the
PWRT delay is over (if PWRT is enabled). This helps to
ensure that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
R1(1)
MCLR
R2(2)
14.8
Brown-out Reset (BOR)
C1
Note 1:
2:
14.5
R1 < 40 k is recommended to make
sure that the voltage drop across R does
not violate the device’s electrical
specification.
R2 > than 1K will limit any current
flowing into MCLR from the external
capacitor C, in the event of MCLR/VPP
breakdown due to Electrostatic
Discharge (ESD) or Electrical
Overstress (EOS).
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V-1.7V). To take
advantage of the POR, tie the MCLR pin to VDD
through an RC network, as described in Section 14.4
“MCLR”. A maximum rise time for VDD is specified.
See Section 17.0 “Electrical Characteristics” for
details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating conditions are met. Brown-out Reset may be used to meet
the start-up conditions. For additional information, refer
to application note, AN607, “Power-up Trouble
Shooting” (DS00607).
DS39582C-page 148
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100 S), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a Reset may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in Reset for
TPWRT (parameter #33, about 72 mS). If VDD should
fall below VBOR during TPWRT, the Brown-out Reset
process will restart when VDD rises above VBOR with
the Power-up Timer Reset. The Power-up Timer is
always enabled when the Brown-out Reset circuit is
enabled, regardless of the state of the PWRT
configuration bit.
14.9
Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of Reset.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution
immediately. This is useful for testing purposes or to
synchronize more than one PIC16F87XA device
operating in parallel.
Table 14-5 shows the Reset conditions for the Status,
PCON and PC registers, while Table 14-6 shows the
Reset conditions for all the registers.
2001-2013 Microchip Technology Inc.
PIC16F87XA
14.10 Power Control/Status Register
(PCON)
When the Brown-out Reset is disabled, the state of the
BOR bit is unpredictable and is, therefore, not valid at
any time.
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
Bit 1 is the Power-on Reset Status bit, POR. It is
cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on
Reset.
Bit 0 is the Brown-out Reset Status bit, BOR. The BOR
bit is unknown on a Power-on Reset. It must then be set
by the user and checked on subsequent Resets to see if
it has been cleared, indicating that a BOR has occurred.
TABLE 14-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Brown-out
Wake-up from
Sleep
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
RC
72 ms
—
72 ms
—
TABLE 14-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during Sleep or Interrupt Wake-up from Sleep
Legend: x = don’t care, u = unchanged
TABLE 14-5:
RESET CONDITIONS FOR SPECIAL REGISTERS
Program
Counter
Status
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during Sleep
000h
0001 0uuu
---- --uu
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
Condition
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from Sleep
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2001-2013 Microchip Technology Inc.
DS39582C-page 149
PIC16F87XA
TABLE 14-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset
Wake-up via WDT or
Interrupt
W
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
73A
74A
76A
77A
N/A
N/A
N/A
TMR0
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
73A
74A
76A
77A
0000 0000
0000 0000
PC + 1(2)
STATUS
73A
74A
76A
77A
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
73A
74A
76A
77A
--0x 0000
--0u 0000
--uu uuuu
PORTB
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE
73A
74A
76A
77A
---- -xxx
---- -uuu
---- -uuu
PCLATH
73A
74A
76A
77A
---0 0000
---0 0000
---u uuuu
INTCON
73A
74A
76A
77A
0000 000x
0000 000u
uuuu uuuu(1)
73A
74A
76A
77A
r000 0000
r000 0000
ruuu uuuu(1)
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu(1)
PIR2
73A
74A
76A
77A
-0-0 0--0
-0-0 0--0
-u-u u--u(1)
TMR1L
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
73A
74A
76A
77A
--00 0000
--uu uuuu
--uu uuuu
TMR2
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
T2CON
73A
74A
76A
77A
-000 0000
-000 0000
-uuu uuuu
SSPBUF
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
PIR1
SSPCON
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
CCPR1L
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
73A
74A
76A
77A
--00 0000
--00 0000
--uu uuuu
RCSTA
73A
74A
76A
77A
0000 000x
0000 000x
uuuu uuuu
TXREG
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
RCREG
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
CCPR2L
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
ADRESH
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
73A
74A
76A
77A
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
73A
74A
76A
77A
1111 1111
1111 1111
uuuu uuuu
TRISA
73A
74A
76A
77A
--11 1111
--11 1111
--uu uuuu
TRISB
73A
74A
76A
77A
1111 1111
1111 1111
uuuu uuuu
TRISC
73A
74A
76A
77A
1111 1111
1111 1111
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition,
r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-5 for Reset value for specific condition.
DS39582C-page 150
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 14-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset
Wake-up via WDT or
Interrupt
TRISD
73A
74A
76A
77A
1111 1111
1111 1111
uuuu uuuu
TRISE
73A
74A
76A
77A
0000 -111
0000 -111
uuuu -uuu
73A
74A
76A
77A
r000 0000
r000 0000
ruuu uuuu
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
PIE1
PIE2
73A
74A
76A
77A
-0-0 0--0
-0-0 0--0
-u-u u--u
PCON
73A
74A
76A
77A
---- --qq
---- --uu
---- --uu
SSPCON2
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
PR2
73A
74A
76A
77A
1111 1111
1111 1111
1111 1111
SSPADD
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
73A
74A
76A
77A
--00 0000
--00 0000
--uu uuuu
TXSTA
73A
74A
76A
77A
0000 -010
0000 -010
uuuu -uuu
SPBRG
73A
74A
76A
77A
0000 0000
0000 0000
uuuu uuuu
CMCON
73A
974
76A
77A
0000 0111
0000 0111
uuuu uuuu
CVRCON
73A
74A
76A
77A
000- 0000
000- 0000
uuu- uuuu
ADRESL
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
73A
74A
76A
77A
00-- 0000
00-- 0000
uu-- uuuu
EEDATA
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATH
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADRH
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
uuuu uuuu
EECON1
73A
74A
76A
77A
x--- x000
u--- u000
u--- uuuu
EECON2
73A
74A
76A
77A
---- ----
---- ----
---- ----
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition,
r = reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-5 for Reset value for specific condition.
FIGURE 14-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
2001-2013 Microchip Technology Inc.
DS39582C-page 151
PIC16F87XA
FIGURE 14-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 14-8:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK)
FIGURE 14-9:
5V
VDD
1V
0V
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
DS39582C-page 152
2001-2013 Microchip Technology Inc.
PIC16F87XA
14.11 Interrupts
The PIC16F87XA family has up to 15 sources of
interrupt. The Interrupt Control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 14-10:
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Registers, PIR1 and PIR2. The
corresponding interrupt enable bits are contained in
Special Function Registers, PIE1 and PIE2, and the
peripheral interrupt enable bit is contained in Special
Function Register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two-cycle instructions. Individual
interrupt flag bits are set regardless of the status of their
corresponding mask bit, PEIE bit or GIE bit.
INTERRUPT LOGIC
EEIF
EEIE
PSPIF(1)
PSPIE(1)
ADIF
ADIE
TMR0IF
TMR0IE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
INTF
INTE
Wake-up (If in Sleep mode)
Interrupt to CPU
RBIF
RBIE
PEIE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
BCLIF
BCLIE
CMIF
CMIE
Note 1:
PSP interrupt is implemented only on PIC16F874A/877A devices.
2001-2013 Microchip Technology Inc.
DS39582C-page 153
PIC16F87XA
14.11.1
INT INTERRUPT
14.12 Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG) is set or
falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit, INTF
(INTCON), is set. This interrupt can be disabled by
clearing enable bit, INTE (INTCON). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT
interrupt can wake-up the processor from Sleep if bit
INTE was set prior to going into Sleep. The status of
global interrupt enable bit, GIE, decides whether or not
the processor branches to the interrupt vector following
wake-up. See Section 14.14 “Power-down Mode
(Sleep)” for details on Sleep mode.
14.11.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit, TMR0IF (INTCON). The interrupt can be
enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON). See Section 5.0 “Timer0
Module”.
14.11.3
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W register and Status
register). This will have to be implemented in software.
For the PIC16F873A/874A devices, the register
W_TEMP must be defined in both Banks 0 and 1 and
must be defined at the same offset from the bank base
address (i.e., If W_TEMP is defined at 0x20 in Bank 0,
it must also be defined at 0xA0 in Bank 1). The registers, PCLATH_TEMP and STATUS_TEMP, are only
defined in Bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F876A/877A devices, temporary holding registers, W_TEMP, STATUS_TEMP and PCLATH_TEMP,
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for context save and restore. The same code shown in
Example 14-1 can be used.
PORTB INTCON CHANGE
An input change on PORTB sets flag bit, RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON). See
Section 4.2 “PORTB and the TRISB Register”.
EXAMPLE 14-1:
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Copy
;Swap
;bank
;Save
;Only
;Save
;Page
W to TEMP register
status to be saved into W
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
required if using pages 1, 2 and/or 3
PCLATH into W
zero, regardless of current page
;(Insert user code here)
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
DS39582C-page 154
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
2001-2013 Microchip Technology Inc.
PIC16F87XA
14.13 Watchdog Timer (WDT)
WDT time-out period values may be found in
Section 17.0 “Electrical Characteristics” under
parameter #31. Values for the WDT prescaler (actually
a postscaler but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
The Watchdog Timer is a free running, on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKI pin. That means that
the WDT will run even if the clock on the OSC1/CLKI
and OSC2/CLKO pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT and prevent it from
timing out and generating a device Reset
condition.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the Status register
will be cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared but the
prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit, WDTE (Section 14.1 “Configuration
Bits”).
FIGURE 14-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
1
WDT Timer
Postscaler
M
U
X
8
8-to-1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note:
TABLE 14-7:
Address
PSA and PS2:PS0 are bits in the OPTION_REG register.
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
2007h
Config. bits
81h, 181h
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 14-1 for operation of these bits.
2001-2013 Microchip Technology Inc.
DS39582C-page 155
PIC16F87XA
14.14 Power-down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (Status) is cleared, the
TO (Status) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external
circuitry is drawing current from the I/O pin, powerdown the A/D and disable external clocks. Pull all I/O
pins that are high-impedance inputs, high or low
externally, to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The
contribution from on-chip pull-ups on PORTB should
also be considered.
The MCLR pin must be at a logic high level (VIHMC).
14.14.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was enabled).
Interrupt from INT pin, RB port change or
peripheral interrupt.
External MCLR Reset will cause a device Reset. All other
events are considered a continuation of program execution and cause a “wake-up”. The TO and PD bits in the
Status register can be used to determine the cause of
device Reset. The PD bit, which is set on power-up, is
cleared when Sleep is invoked. The TO bit is cleared if a
WDT time-out occurred and caused wake-up.
The following peripheral interrupts can wake the device
from Sleep:
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
14.14.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT
instruction should be executed before a SLEEP
instruction.
1.
2.
PSP read or write (PIC16F874/877 only).
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
5. SSP (Start/Stop) bit detect interrupt.
6. SSP transmit or receive in Slave mode (SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
9. EEPROM write operation completion.
10. Comparator output changes state.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
DS39582C-page 156
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 14-12:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKO(4)
INT pin
INTF Flag
(INTCON)
Interrupt Latency(2)
GIE bit
(INTCON)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
Instruction
Fetched
Inst(PC) = Sleep
Inst(PC + 1)
Inst(PC + 2)
Instruction
Executed
Inst(PC - 1)
Sleep
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode.
3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = 0, execution will continue in-line.
4: CLKO is not available in these oscillator modes but shown here for timing reference.
14.15 In-Circuit Debugger
When the DEBUG bit in the configuration word is programmed to a ‘0’, the in-circuit debugger functionality is
enabled. This function allows simple debugging
functions when used with MPLAB® ICD. When the
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 14-8
shows which features are consumed by the
background debugger.
TABLE 14-8:
DEBUGGER RESOURCES
I/O pins
Stack
Program Memory
RB6, RB7
1 level
Address 0000h must be NOP
14.16 Program Verification/Code
Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
14.17 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
Last 100h words
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB-0x1EF
To use the in-circuit debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7
and RB6. This will interface to the in-circuit debugger
module available from Microchip or one of the third
party development tool companies.
2001-2013 Microchip Technology Inc.
DS39582C-page 157
PIC16F87XA
14.18
In-Circuit Serial Programming
PIC16F87XA microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
When using ICSP, the part must be supplied at 4.5V to
5.5V if a bulk erase will be executed. This includes
reprogramming of the code-protect, both from an on
state to an off state. For all other cases of ICSP, the part
may be programmed at the normal operating voltages.
This means calibration values, unique user IDs or user
code can be reprogrammed or added.
For complete details of serial programming, please
refer to the “PIC16F87XA Flash Memory Programming
Specification” (DS39589).
14.19 Low-Voltage (Single-Supply)
ICSP Programming
The LVP bit of the configuration word enables lowvoltage ICSP programming. This mode allows the
microcontroller to be programmed via ICSP using a
VDD source in the operating voltage range. This only
means that VPP does not have to be brought to VIHH but
can instead be left at the normal operating voltage. In
this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose
I/O pin. During programming, VDD is applied to the
MCLR pin. To enter Programming mode, VDD must be
applied to the RB3/PGM provided the LVP bit is set.
The LVP bit defaults to on (‘1’) from the factory.
Note 1: The High-Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low-Voltage ICSP mode, the
RB3 pin can no longer be used as a
general purpose I/O pin.
3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
4: RB3 should not be allowed to float if LVP
is enabled. An external pull-down device
should be used to default the device to
normal operating mode. If RB3 floats
high, the PIC16F87XA device will enter
Programming mode.
5: LVP mode is enabled by default on all
devices shipped from Microchip. It can be
disabled by clearing the LVP bit in the
CONFIG register.
6: Disabling LVP will provide maximum
compatibility to other PIC16CXXX
devices.
If Low-Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to ‘0’, only the High-Voltage Programming mode is
available and only High-Voltage Programming mode
can be used to program the device.
When using low-voltage ICSP, the part must be supplied
at 4.5V to 5.5V if a bulk erase will be executed. This
includes reprogramming of the code-protect bits from an
on state to an off state. For all other cases of low-voltage
ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique
user IDs or user code can be reprogrammed or added.
DS39582C-page 158
2001-2013 Microchip Technology Inc.
PIC16F87XA
15.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode which specifies the instruction type and one or
more operands which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 15-1, while the various opcode
fields are summarized in Table 15-1.
Table 15-2 lists the instructions recognized by the
MPASM™ Assembler. A complete description of each
instruction is also available in the PIC® Mid-Range MCU
Family Reference Manual (DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the bit affected by the operation, while ‘f’ represents the address of the file in which
the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven-bit constant or literal value
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles with the
second cycle executed as a NOP.
Note:
To maintain upward compatibility with
future PIC16F87XA products, do not use
the OPTION and TRIS instructions.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag
would be cleared.
TABLE 15-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
FIGURE 15-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
0
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
15.1
READ-MODIFY-WRITE
OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
2001-2013 Microchip Technology Inc.
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
DS39582C-page 159
PIC16F87XA
TABLE 15-2:
PIC16F87XA INSTRUCTION SET
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1:
2:
3:
Note:
k
k
k
k
k
k
k
k
k
Add Literal and W
AND Literal with W
Call Subroutine
Clear Watchdog Timer
Go to Address
Inclusive OR Literal with W
Move Literal to W
Return from Interrupt
Return with Literal in W
Return from Subroutine
Go into Standby mode
Subtract W from Literal
Exclusive OR Literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Additional information on the mid-range instruction set is available in the PIC® Mid-Range MCU Family Reference Manual (DS33023).
DS39582C-page 160
2001-2013 Microchip Technology Inc.
PIC16F87XA
15.2
Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] BCF
Operands:
0 k 255
Operands:
0 f 127
0b7
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Operation:
0 (f)
Description:
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
ADDWF
Add W and f
BSF
Bit Set f
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BSF
Operands:
0 f 127
d
Operands:
0 f 127
0b7
Operation:
(W) + (f) (destination)
Operation:
1 (f)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
Description:
Bit ‘b’ in register ‘f’ is set.
ANDLW
AND Literal with W
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BTFSS f,b
Operands:
0 k 255
Operands:
Operation:
(W) .AND. (k) (W)
0 f 127
0b VDD) 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byPORTA, PORTB and PORTE (combined) (Note 3) ....................................................200 mA
Maximum current sourced by PORTA, PORTB and PORTE (combined) (Note 3)...............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than
pulling this pin directly to VSS.
3: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2001-2013 Microchip Technology Inc.
DS39582C-page 173
PIC16F87XA
FIGURE 17-1:
PIC16F87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)
6.0V
5.5V
5.0V
PIC16F87XA
Voltage
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
20 MHz
Frequency
FIGURE 17-2:
PIC16LF87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
4.5V
4.0V
PIC16LF87XA
3.5V
3.0V
2.5V
2.0V
4 MHz
10 MHz
Frequency
FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
Note 2: FMAX has a maximum frequency of 10 MHz.
DS39582C-page 174
2001-2013 Microchip Technology Inc.
PIC16F87XA
17.1
DC Characteristics:
PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial)
PIC16LF873A/874A/876A/877A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
VDD
Characteristic/
Device
Min
Typ†
Max
Units
Conditions
2.0
—
5.5
V
All configurations
(DC to 10 MHz)
4.0
—
5.5
V
All configurations
5.5
V
BOR enabled, FMAX = 14 MHz(7)
Supply Voltage
D001
16LF87XA
D001
16F87XA
D001A
VBOR
D002
VDR
RAM Data Retention
Voltage(1)
—
1.5
—
V
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
V
D004
SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
—
—
D005
VBOR
Brown-out Reset
Voltage
3.65
4.0
4.35
See Section 14.5 “Power-on
Reset (POR)” for details
V/ms See Section 14.5 “Power-on
Reset (POR)” for details
V
BODEN bit in configuration word
enabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2001-2013 Microchip Technology Inc.
DS39582C-page 175
PIC16F87XA
17.1
DC Characteristics:
PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/876A/877A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
IDD
Characteristic/
Device
Min
Typ†
Max
Units
Conditions
Supply Current(2,5)
D010
16LF87XA
—
0.6
2.0
mA
XT, RC osc configurations,
FOSC = 4 MHz, VDD = 3.0V
D010
16F87XA
—
1.6
4
mA
XT, RC osc configurations,
FOSC = 4 MHz, VDD = 5.5V
16LF87XA
—
20
35
A
LP osc configuration,
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
16F87XA
—
7
15
mA
HS osc configuration,
FOSC = 20 MHz, VDD = 5.5V
—
85
200
A
BOR enabled, VDD = 5.0V
D010A
D013
D015
IBOR
Brown-out
Reset Current(6)
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS39582C-page 176
2001-2013 Microchip Technology Inc.
PIC16F87XA
17.1
DC Characteristics:
PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
PIC16LF873A/874A/876A/877A
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
PIC16F873A/874A/876A/877A
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
IPD
Characteristic/
Device
Min
Typ†
Max
Units
Conditions
—
7.5
30
A
VDD = 3.0V, WDT enabled,
-40C to +85C
—
10.5
42
A
60
A
VDD = 4.0V, WDT enabled,
-40C to +85C
VDD = 4.0V, WDT enabled,
-40C to +125C (extended)
Power-down Current(3,5)
D020
16LF87XA
D020
16F87XA
D021
16LF87XA
—
0.9
5
A
VDD = 3.0V, WDT disabled,
0C to +70C
D021
16F87XA
—
1.5
16
A
20
A
VDD = 4.0V, WDT disabled,
-40C to +85C
VDD = 4.0V, WDT disabled,
-40C to +125C (extended)
D021A
16LF87XA
0.9
5
A
VDD = 3.0V, WDT disabled,
-40C to +85C
D021A
16F87XA
1.5
19
A
VDD = 4.0V, WDT disabled,
-40C to +85C
85
200
A
BOR enabled, VDD = 5.0V
D023
IBOR
Brown-out
Reset Current(6)
—
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading, switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from
characterization and is for design guidance only. This is not tested.
6: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2001-2013 Microchip Technology Inc.
DS39582C-page 177
PIC16F87XA
17.2
DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC specification
(Section 17.1)
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Min
Typ†
Max
Units
Conditions
VSS
—
0.15 VDD
V
For entire VDD range
VSS
—
0.8V
V
4.5V VDD 5.5V
VSS
—
0.2 VDD
V
VSS
—
0.2 VDD
V
Input Low Voltage
I/O ports:
D030
with TTL buffer
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, OSC1 (in RC mode)
D033
OSC1 (in XT and LP modes)
VSS
—
0.3V
V
OSC1 (in HS mode)
VSS
—
0.3 VDD
V
with Schmitt Trigger buffer
VSS
—
0.3 VDD
V
For entire VDD range
with SMBus
-0.5
—
0.6
V
For VDD = 4.5 to 5.5V
2.0
—
VDD
V
4.5V VDD 5.5V
0.25 VDD
—
VDD
V
For entire VDD range
0.8 VDD
—
VDD
V
For entire VDD range
0.8 VDD
—
VDD
V
Ports RC3 and RC4:
D034
D034A
VIH
(Note 1)
—
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
—
+ 0.8V
D041
with Schmitt Trigger buffer
D042
MCLR
D042A
OSC1 (in XT and LP modes)
D043
1.6V
—
VDD
V
OSC1 (in HS mode)
0.7 VDD
—
VDD
V
(Note 1)
OSC1 (in RC mode)
0.9 VDD
—
VDD
V
0.7 VDD
—
VDD
V
For entire VDD range
1.4
—
5.5
V
For VDD = 4.5 to 5.5V
50
250
400
A
VDD = 5V, VPIN = VSS,
-40°C TO +85°C
Ports RC3 and RC4:
D044
with Schmitt Trigger buffer
D044A
with SMBus
D070
IPURB
PORTB Weak Pull-up Current
IIL
Input Leakage Current(2, 3)
D060
I/O ports
—
—
1
A
VSS VPIN VDD,
pin at high-impedance
D061
MCLR, RA4/T0CKI
—
—
5
A
VSS VPIN VDD
D063
OSC1
—
—
5
A
VSS VPIN VDD, XT, HS
and LP osc configuration
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87XA be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS39582C-page 178
2001-2013 Microchip Technology Inc.
PIC16F87XA
17.2
DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended)
PIC16LF873A/874A/876A/877A (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC specification
(Section 17.1)
DC CHARACTERISTICS
Param
No.
Sym
VOL
Characteristic
Min
Typ†
Max
Units
Conditions
Output Low Voltage
D080
I/O ports
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
D083
OSC2/CLKO (RC osc config)
—
—
0.6
V
IOL = 1.6 mA, VDD = 4.5V,
-40C to +85C
VOH
Output High Voltage
D090
I/O ports(3)
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
D092
OSC2/CLKO (RC osc config)
VDD – 0.7
—
—
V
IOH = -1.3 mA, VDD = 4.5V,
-40C to +85C
—
—
8.5
V
RA4 pin
—
—
15
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1
—
—
—
—
50
400
pF
pF
D150*
VOD
Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
D101
D102
CIO
CB
All I/O pins and OSC2 (RC mode)
SCL, SDA (I2C mode)
Data EEPROM Memory
D120
ED
Endurance
100K
1M
—
D121
VDRW
VDD for read/write
VMIN
—
5.5
E/W -40C to +85C
V
D122
TDEW
Erase/write cycle time
—
4
8
ms
E/W -40C to +85C
Using EECON to read/write,
VMIN = min. operating voltage
Program Flash Memory
D130
EP
Endurance
10K
100K
—
D131
VPR
VDD for read
VMIN
—
5.5
V
VMIN = min. operating voltage
VDD for erase/write
VMIN
—
5.5
V
Using EECON to read/write,
VMIN = min. operating voltage
—
4
8
ms
D132A
D133
TPEW
Erase/Write cycle time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC16F87XA be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2001-2013 Microchip Technology Inc.
DS39582C-page 179
PIC16F87XA
TABLE 17-1:
COMPARATOR SPECIFICATIONS
Operating Conditions:
Param
No.
D300
3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Sym
VIOFF
Characteristics
Min
Typ
Max
Units
—
± 5.0
± 10
mV
Input Offset Voltage
D301
VICM
Input Common Mode Voltage*
0
-
VDD – 1.5
V
D302
CMRR
Common Mode Rejection Ratio*
55
-
—
dB
300
300A
TRESP
Response Time*(1)
—
150
400
600
ns
ns
301
TMC2OV
Comparator Mode Change to
Output Valid*
—
—
10
s
*
Note 1:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions:
Sym
3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated)
4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated)
Characteristics
Min
Typ
Max
Units
VDD/24
—
VDD/32
LSb
D310
VRES
Resolution
D311
VRAA
Absolute Accuracy
—
—
—
—
1/2
1/2
LSb
LSb
D312
VRUR
Unit Resistor Value (R)*
—
2k
—
TSET
Time*(1)
—
—
10
s
310
*
Note 1:
PIC16F87XA
PIC16LF87XA
These parameters are characterized but not tested.
Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 17-2:
Spec
No.
Comments
Settling
Comments
Low Range (VRR = 1)
High Range (VRR = 0)
These parameters are characterized but not tested.
Settling time measured while VRR = 1 and VR transitions from ‘0000’ to ‘1111’.
DS39582C-page 180
2001-2013 Microchip Technology Inc.
PIC16F87XA
17.3
Timing Parameter Symbology
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKO
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
Data input hold
STA
Start condition
FIGURE 17-3:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
High
Low
High
Low
SU
Setup
STO
Stop condition
LOAD CONDITIONS
Load Condition 2
Load Condition 1
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL
= 464
CL
= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports,
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices.
2001-2013 Microchip Technology Inc.
DS39582C-page 181
PIC16F87XA
FIGURE 17-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
4
3
4
2
CLKO
TABLE 17-3:
Param
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Symbol
FOSC
Characteristic
External CLKI Frequency
(Note 1)
Oscillator Frequency
(Note 1)
1
TOSC
External CLKI Period
(Note 1)
Oscillator Period
(Note 1)
Min
Typ†
Max
Units
Conditions
DC
—
1
MHz XT and RC Osc mode
DC
—
20
MHz HS Osc mode
DC
—
32
kHz
DC
—
4
MHz RC Osc mode
0.1
—
4
MHz XT Osc mode
4
5
—
—
20
200
MHz HS Osc mode
kHz LP Osc mode
1000
—
—
ns
LP Osc mode
XT and RC Osc mode
50
—
—
ns
HS Osc mode
5
—
—
s
LP Osc mode
250
—
—
ns
RC Osc mode
250
—
1
s
XT Osc mode
100
—
250
ns
HS Osc mode
50
—
250
ns
HS Osc mode
31.25
—
—
s
LP Osc mode
2
TCY
Instruction Cycle Time
(Note 1)
200
TCY
DC
ns
TCY = 4/FOSC
3
TOSL,
TOSH
External Clock in (OSC1) High or
Low Time
100
—
—
ns
XT oscillator
4
TOSR,
TOSF
External Clock in (OSC1) Rise or
Fall Time
2.5
—
—
s
LP oscillator
15
—
—
ns
HS oscillator
—
—
25
ns
XT oscillator
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time
limit is “DC” (no clock) for all devices.
DS39582C-page 182
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 17-5:
CLKO AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKO
13
19
14
12
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-4:
Param
No.
CLKO AND I/O TIMING REQUIREMENTS
Symbol
Characteristic
Min
Typ†
Max
—
75
200
Units Conditions
10*
TOSH2CKL OSC1 to CLKO
11*
TOSH2CKH OSC1 to CLKO
—
75
200
ns
(Note 1)
12*
TCKR
CLKO Rise Time
—
35
100
ns
(Note 1)
13*
TCKF
CLKO Fall Time
—
35
100
ns
(Note 1)
14*
TCKL2IOV
CLKO to Port Out Valid
—
—
0.5 TCY + 20
ns
(Note 1)
15*
TIOV2CKH Port In Valid before CLKO
16*
TCKH2IOI
Port In Hold after CLKO
17*
TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid
18*
TOSH2IOI
19*
TIOV2OSH Port Input Valid to OSC1 (I/O in setup time)
20*
TIOR
21*
TIOF
OSC1 (Q2 cycle) to Port Input
Invalid (I/O in hold time)
Port Output Rise Time
Port Output Fall Time
ns
TOSC + 200
—
—
ns
(Note 1)
0
—
—
ns
(Note 1)
—
100
255
ns
Standard (F)
100
—
—
ns
Extended (LF)
200
—
—
ns
0
—
—
ns
Standard (F)
—
10
40
ns
Extended (LF)
—
—
145
ns
Standard (F)
—
10
40
ns
Extended (LF)
—
—
145
ns
22††*
TINP
INT pin High or Low Time
TCY
—
—
ns
23††*
TRBP
RB7:RB4 Change INT High or Low Time
TCY
—
—
ns
*
†
††
Note 1:
(Note 1)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
These parameters are asynchronous events not related to any internal clock edges.
Measurements are taken in RC mode where CLKO output is 4 x TOSC.
2001-2013 Microchip Technology Inc.
DS39582C-page 183
PIC16F87XA
FIGURE 17-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note: Refer to Figure 17-3 for load conditions.
FIGURE 17-7:
BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 17-5:
Param
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
—
—
s
VDD = 5V, -40°C to +85°C
31*
TWDT
Watchdog Timer Time-out Period
(no prescaler)
7
18
33
ms
VDD = 5V, -40°C to +85°C
32
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
TPWRT
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +85°C
34
TIOZ
I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
s
TBOR
Brown-out Reset Pulse Width
100
—
—
s
35
*
†
VDD VBOR (D005)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS39582C-page 184
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 17-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or TMR1
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-6:
Param
No.
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Symbol
Characteristic
40*
TT0H
T0CKI High Pulse Width
41*
TT0L
T0CKI Low Pulse Width
42*
TT0P
T0CKI Period
45*
TT1H
46*
TT1L
47*
TT1P
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
T1CKI High
Time
Synchronous, Prescaler = 1
Synchronous,
Standard(F)
Prescaler = 2, 4, 8 Extended(LF)
Asynchronous
Standard(F)
Extended(LF)
T1CKI Low Time Synchronous, Prescaler = 1
Synchronous,
Standard(F)
Prescaler = 2, 4, 8 Extended(LF)
Asynchronous
Standard(F)
Extended(LF)
T1CKI Input
Synchronous
Standard(F)
Period
Extended(LF)
Asynchronous
48
Min
Typ†
Max
Units
Conditions
0.5 TCY + 20
10
0.5 TCY + 20
10
TCY + 40
Greater of:
20 or TCY + 40
N
0.5 TCY + 20
15
25
30
50
0.5 TCY + 20
15
25
30
50
Greater of:
30 or TCY + 40
N
Greater of:
50 or TCY + 40
N
60
100
DC
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Must also meet
parameter 42
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Must also meet
parameter 47
Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
Standard(F)
—
—
ns
Extended(LF)
—
—
ns
FT1
Timer1 Oscillator Input Frequency Range
—
200
kHz
(oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1 Delay from External Clock Edge to Timer Increment
2 TOSC
— 7 TOSC —
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2001-2013 Microchip Technology Inc.
DS39582C-page 185
PIC16F87XA
FIGURE 17-9:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-7:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
Symbol
No.
50*
TCCL
Characteristic
CCP1 and CCP2
Input Low Time
No Prescaler
With Prescaler
51*
TCCH
CCP1 and CCP2
Input High Time
Min
Standard(F)
Extended(LF)
0.5 TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5 TCY + 20
—
—
ns
Standard(F)
10
—
—
ns
Extended(LF)
20
—
—
ns
3 TCY + 40
N
—
—
ns
—
10
25
ns
No Prescaler
With Prescaler
Typ† Max Units
52*
TCCP
CCP1 and CCP2 Input Period
53*
TCCR
CCP1 and CCP2 Output Rise Time
Standard(F)
Extended(LF)
—
25
50
ns
54*
TCCF
CCP1 and CCP2 Output Fall Time
Standard(F)
—
10
25
ns
Extended(LF)
—
25
45
ns
*
†
Conditions
N = prescale value
(1, 4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS39582C-page 186
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 17-10:
PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-8:
Param
No.
PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY)
Symbol
Characteristic
Min
Typ†
Max
Units
62
TDTV2WRH
Data In Valid before WR or CS (setup time)
20
—
—
ns
63*
TWRH2DTI
WR or CS to Data–in Invalid
(hold time)
Standard(F)
20
—
—
ns
Extended(LF)
35
—
—
ns
64
TRDL2DTV
RD and CS to Data–out Valid
—
—
80
ns
TRDH2DTI
RD or CS to Data–out Invalid
10
—
30
ns
65
*
†
Conditions
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2001-2013 Microchip Technology Inc.
DS39582C-page 187
PIC16F87XA
FIGURE 17-11:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
Bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
Bit 6 - - - -1
LSb In
74
73
Note: Refer to Figure 17-3 for load conditions.
FIGURE 17-12:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
Bit 6 - - - - - -1
LSb
Bit 6 - - - -1
LSb In
75, 76
SDI
MSb In
74
Note: Refer to Figure 17-3 for load conditions.
DS39582C-page 188
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 17-13:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
Bit 6 - - - - - -1
77
75, 76
SDI
MSb In
LSb In
Bit 6 - - - -1
74
73
Note: Refer to Figure 17-3 for load conditions.
FIGURE 17-14:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
Bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
77
Bit 6 - - - -1
LSb In
74
Note: Refer to Figure 17-3 for load conditions.
2001-2013 Microchip Technology Inc.
DS39582C-page 189
PIC16F87XA
TABLE 17-9:
Param
No.
70*
SPI MODE REQUIREMENTS
Symbol
TSSL2SCH,
TSSL2SCL
Characteristic
SS to SCK or SCK Input
Min
Typ†
Max
Units
TCY
—
—
ns
71*
TSCH
SCK Input High Time (Slave mode)
TCY + 20
—
—
ns
72*
TSCL
SCK Input Low Time (Slave mode)
TCY + 20
—
—
ns
73*
TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge
100
—
—
ns
74*
TSCH2DIL,
TSCL2DIL
Hold Time of SDI Data Input to SCK Edge
100
—
—
ns
75*
TDOR
SDO Data Output Rise Time
—
—
10
25
25
50
ns
ns
76*
TDOF
SDO Data Output Fall Time
—
10
25
ns
77*
TSSH2DOZ
SS to SDO Output High-Impedance
10
—
50
ns
78*
TSCR
SCK Output Rise Time
(Master mode)
Standard(F)
Extended(LF)
—
—
10
25
25
50
ns
ns
—
10
25
ns
Standard(F)
Extended(LF)
—
—
—
—
50
145
ns
TCY
—
—
ns
—
—
50
ns
1.5 TCY + 40
—
—
ns
Standard(F)
Extended(LF)
79*
TSCF
SCK Output Fall Time (Master mode)
80*
TSCH2DOV,
TSCL2DOV
SDO Data Output Valid after
SCK Edge
81*
TDOV2SCH,
TDOV2SCL
SDO Data Output Setup to SCK Edge
82*
TSSL2DOV
SDO Data Output Valid after SS Edge
83*
TSCH2SSH,
TSCL2SSH
SS after SCK Edge
*
†
Conditions
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
I2C BUS START/STOP BITS TIMING
FIGURE 17-15:
SCL
93
91
90
92
SDA
Start
Condition
Stop
Condition
Note: Refer to Figure 17-3 for load conditions.
DS39582C-page 190
2001-2013 Microchip Technology Inc.
PIC16F87XA
TABLE 17-10: I2C BUS START/STOP BITS REQUIREMENTS
Param
No.
90
Symbol
TSU:STA
Characteristic
Min
Typ
Max
Units
ns
Only relevant for Repeated Start
condition
ns
After this period, the first clock pulse
is generated
Start condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
4000
—
—
91
THD:STA
Start condition
100 kHz mode
Hold time
400 kHz mode
600
—
—
92
TSU:STO
Stop condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
Stop condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
93
THD:STO
FIGURE 17-16:
Conditions
ns
ns
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 17-3 for load conditions.
2001-2013 Microchip Technology Inc.
DS39582C-page 191
PIC16F87XA
TABLE 17-11: I2C BUS DATA REQUIREMENTS
Param
No.
100
Sym
THIGH
Characteristic
Clock High Time
Min
Max
Units
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
0.5 TCY
—
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
0.5 TCY
—
SSP Module
101
TLOW
Clock Low Time
SSP Module
102
103
TR
TF
SDA and SCL Rise
Time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
SDA and SCL Fall
Time
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
CB is specified to be from 10 to
400 pF
Only relevant for Repeated Start
condition
90
TSU:STA
Start Condition Setup
Time
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
91
THD:STA
Start Condition Hold
Time
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
100 kHz mode
0
—
ns
106
THD:DAT
Data Input Hold Time
0
0.9
s
107
TSU:DAT
Data Input Setup Time 100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
—
s
400 kHz mode
92
TSU:STO
Stop Condition Setup
Time
100 kHz mode
4.7
400 kHz mode
0.6
—
s
109
TAA
Output Valid from
Clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
TBUF
Bus Free Time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
CB
Bus Capacitive Loading
—
400
pF
110
Note 1:
2:
Conditions
Cb is specified to be from 10 to
400 pF
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free before
a new transmission can start
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement
that, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, TR MAX. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification),
before the SCL line is released.
DS39582C-page 192
2001-2013 Microchip Technology Inc.
PIC16F87XA
FIGURE 17-17:
RC6/TX/CK
pin
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol
120
Characteristic
TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
121
TCKRF
122
TDTRF
Min
Typ† Max Units Conditions
Standard(F)
—
—
80
ns
Extended(LF)
—
—
100
ns
Clock Out Rise Time and Fall Time
(Master mode)
Standard(F)
—
—
45
ns
Extended(LF)
—
—
50
ns
Data Out Rise Time and Fall Time
Standard(F)
—
—
45
ns
Extended(LF)
—
—
50
ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 17-18:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
125
TDTV2CKL
SYNC RCV (MASTER & SLAVE)
Data Setup before CK (DT setup time)
15
—
—
ns
126
TCKL2DTL
Data Hold after CK (DT hold time)
15
—
—
ns
Conditions
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2001-2013 Microchip Technology Inc.
DS39582C-page 193
PIC16F87XA
TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL)
PIC16LF873A/874A/876A/877A (INDUSTRIAL)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10-bits
bit
VREF = VDD = 5.12V,
VSS VAIN VREF
A03
EIL
Integral Linearity Error
—
—
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