PIC16LC72-04I/SS

PIC16C72 SERIES 8-Bit CMOS Microcontrollers with A/D Converter Devices included: Pin Diagrams • PIC16C72 SDIP, SOIC, SSOP, Windowed Side Brazed Ceramic • PIC16CR72 Microcontroller Core Features:  1998-2013 Microchip Technology Inc. •1 28 RB7 RA0/AN0 2 27 RB6 RA1/AN1 3 26 RB5 RA2/AN2 4 25 RB4 RA3/AN3/VREF 5 24 RB3 RA4/T0CKI 6 23 RB2 RA5/SS/AN4 VSS 7 8 22 21 RB1 RB0/INT OSC1/CLKIN MCLR/VPP • High-performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) • Interrupt capability • Eight level deep hardware stack • Direct, indirect, and relative addressing modes • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code-protection • Power saving SLEEP mode • Selectable oscillator options • Low-power, high-speed CMOS technology • Fully static design • Wide operating voltage range: - 2.5V to 6.0V (PIC16C72) - 2.5V to 5.5V (PIC16CR72) • High Sink/Source Current 25/25 mA • Commercial, Industrial and Extended temperature ranges • Low-power consumption: - < 2 mA @ 5V, 4 MHz - 15 A typical @ 3V, 32 kHz - < 1 A typical standby current 9 20 VDD OSC2/CLKOUT 10 19 VSS RC0/T1OSO/T1CKI 11 18 RC7 RC1/T1OSI 12 17 RC6 RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA PIC16C72 PIC16CR72 Peripheral Features: • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture, Compare, PWM (CCP) module - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit • 8-bit 5-channel analog-to-digital converter • Synchronous Serial Port (SSP) with SPI and I2C • Brown-out detection circuitry for Brown-out Reset (BOR) Preliminary DS39016B-page 1 PIC16C72 Series Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 3 2.0 Memory Organization ................................................................................................................................................................... 5 3.0 I/O Ports ..................................................................................................................................................................................... 19 4.0 Timer0 Module ........................................................................................................................................................................... 25 5.0 Timer1 Module ........................................................................................................................................................................... 27 6.0 Timer2 Module ........................................................................................................................................................................... 31 7.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 33 8.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 39 9.0 Analog-to-Digital Converter (A/D) Module .................................................................................................................................. 53 10.0 Special Features of the CPU ...................................................................................................................................................... 59 11.0 Instruction Set Summary ............................................................................................................................................................ 73 12.0 Development Support................................................................................................................................................................. 75 13.0 Electrical Characteristics - PIC16C72 Series ............................................................................................................................. 77 14.0 DC and AC Characteristics Graphs and Tables - PIC16C72 ..................................................................................................... 97 15.0 DC and AC Characteristics Graphs and Tables - PIC16CR72 ................................................................................................ 107 16.0 Packaging Information.............................................................................................................................................................. 109 Appendix A: What’s New in this Data Sheet .................................................................................................................................. 115 Appendix B: What’s Changed in this Data Sheet ........................................................................................................................... 115 Appendix C: Device Differences..................................................................................................................................................... 115 Index .................................................................................................................................................................................................. 117 On-Line Support................................................................................................................................................................................. 121 Reader Response .............................................................................................................................................................................. 122 PIC16C72 Series Product Identification System................................................................................................................................ 125 Sales and Support.............................................................................................................................................................................. 125 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. Key Reference Manual Features Operating Frequency Resets Program Memory - (14-bit words) Data Memory - RAM (8-bit bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications 8-Bit A/D Converter Instruction Set (No. of Instructions) DS39016B-page 2 PIC16C72 DC - 20MHz POR, PWRT, OST, BOR 2K (EPROM) 128 8 PortA, PortB, PortC Timer0, Timer1, Timer2 1 Basic SSP 5 channels 35 Preliminary PIC16CR72 DC - 20MHz POR, PWRT, OST, BOR 2K (ROM) 128 8 PortA, PortB, PortC Timer0, Timer1, Timer2 1 SSP 5 channels 35  1998-2013 Microchip Technology Inc. PIC16C72 Series 1.0 DEVICE OVERVIEW The program memory contains 2K words which translate to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes. This document contains device-specific information for the operation of the PIC16C72 device. Additional information may be found in the PIC® Mid-Range MCU Reference Manual (DS33023) which may be downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. There are also 22 I/O pins that are user-configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: • • • • • • • The PIC16C72 belongs to the Mid-Range family of the PIC devices. A block diagram of the device is shown in Figure 1-1. External interrupt Change on PORTB interrupt Timer0 clock input Timer1 clock/oscillator Capture/Compare/PWM A/D converter SPI/I2C Table 1-1 details the pinout of the device with descriptions and details for each pin. FIGURE 1-1: PIC16C72/CR72 BLOCK DIAGRAM 13 Program Bus PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/SS/AN4 RAM File Registers 128 x 8 8 Level Stack (13-bit) 14 8 Data Bus Program Counter EPROM/ ROM Program Memory 2K x 14 RAM Addr(1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 8 RB0/INT Indirect Addr RB7:RB1 FSR reg STATUS reg 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode & Control ALU Power-on Reset Timing Generation MCLR W reg VDD, VSS Timer0 Timer1 Timer2 A/D Synchronous Serial Port CCP1 Note 1: RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 8 Watchdog Timer Brown-out Reset OSC1/CLKIN OSC2/CLKOUT MUX PORTC Higher order bits are from the STATUS register.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 3 PIC16C72 Series TABLE 1-1 PIC16C72/CR72 PINOUT DESCRIPTION Pin# I/O/P Type OSC1/CLKIN 9 I OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. RA0/AN0 2 I/O TTL RA0 can also be analog input0. RA1/AN1 3 I/O TTL RA1 can also be analog input1. RA2/AN2 4 I/O TTL RA2 can also be analog input2. RA3/AN3/VREF 5 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/SS/AN4 7 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. Pin Name Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. PORTA is a bi-directional I/O port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 I/O TTL/ST(1) RB1 22 I/O TTL RB2 23 I/O TTL RB3 24 I/O TTL RB4 25 I/O TTL Interrupt on change pin. RB5 26 I/O TTL Interrupt on change pin. RB6 27 I/O TTL/ST(2) RB7 28 I/O TTL/ST(2) RB0 can also be the external interrupt pin. Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6 17 I/O ST RC7 18 I/O ST VSS 8, 19 P — Ground reference for logic and I/O pins. VDD 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. DS39016B-page 4 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 2.0 MEMORY ORGANIZATION FIGURE 2-1: There are two memory blocks in PIC16C72 Series devices. These are the program memory and the data memory. Each block has its own bus, so that access to both blocks can occur during the same oscillator cycle. PC CALL, RETURN RETFIE, RETLW The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. 13 Stack Level 1 Stack Level 8 Additional information on device memory may be found in the PIC® Mid-Range Reference Manual, DS33023. Reset Vector 0000h Interrupt Vector 0004h 0005h Program Memory Organization PIC16C72 Series devices have a 13-bit program counter capable of addressing a 2K x 14 program memory space. The address range for this program memory is 0000h - 07FFh. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h. User Memory Space 2.1 PROGRAM MEMORY MAP AND STACK On-chip Program Memory 07FFh 0800h 1FFFh  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 5 PIC16C72 Series 2.2 Data Memory Organization FIGURE 2-2: The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1* RP0 = 00  = 01  = 10  = 11  * File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h (STATUS) Bank0 Bank1 Bank2 (not implemented) Bank3 (not implemented) Maintain this bit clear to ensure upward compatibility with future products. Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another bank for code reduction and quicker access (ex; the STATUS register is in Bank 0 and Bank 1). 2.2.1 REGISTER FILE MAP GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indirectly through the File Select Register FSR (Section 2.5). File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC INDF(1) OPTION PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIR1 PCLATH INTCON PIE1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON PCON ADRES ADCON0 General Purpose Register 7Fh PR2 SSPADD SSPSTAT ADCON1 General Purpose Register 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BFh C0h FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. DS39016B-page 6 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature. The special function registers can be classified into two TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu PCL Program Counter's (PC) Least Significant Byte 02h (1) IRP(4) RP1(4) 0000 0000 0000 0000 03h(1) STATUS 04h(1) FSR 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu RP0 TO PD Z DC C Indirect data memory address pointer — — 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 0Dh — Write Buffer for the upper 5 bits of the Program Counter Unimplemented ---0 0000 ---0 0000 — — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON 11h TMR2 — — T1CKPS1 T1CKPS0 T1OSCEN TMR1CS TMR1ON 12h T2CON SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register (LSB) 16h CCPR1H Capture/Compare/PWM Register (MSB) 17h CCP1CON — 1Eh ADRES 1Fh ADCON0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV — — SSPEN CCP1X CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu CCP1Y xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 Unimplemented ADCS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu --00 0000 --00 0000 — A/D Result Register ADCS1 --00 0000 --uu uuuu 0000 0000 0000 0000 13h 18h-1Dh T1SYNC Timer2 module’s register — xxxx xxxx uuuu uuuu CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear. 5: SSPSTAT are not implemented on the PIC16C72, read as '0'.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 7 PIC16C72 Series TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets (3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG 82h(1) PCL 83h (1) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte STATUS IRP (4) (4) RP1 RP0 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h 89h Indirect data memory address pointer — — Unimplemented — Unimplemented 8Ah(1,2) PCLATH — 8Bh(1) INTCON 8Ch PIE1 8Dh 8Eh — — PCON xxxx xxxx uuuu uuuu PORTA Data Direction Register --11 1111 --11 1111 Write Buffer for the upper 5 bits of the PC — — — — — — GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 — — — — POR BOR ---- --qq ---- --uu ---0 0000 ---0 0000 Unimplemented — — — — 8Fh — Unimplemented — — 90h — Unimplemented — — — — 91h — Unimplemented 92h PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT SMP(5) CKE(5) 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF 0000 0000 0000 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — ---- -000 ---- -000 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear. 5: SSPSTAT are not implemented on the PIC16C72, read as '0'. DS39016B-page 8 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 2.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." The STATUS register, shown in Figure 2-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. Note 1: These devices do not use bits IRP and RP1 (STATUS). Maintain these bits clear to ensure upward compatibility with future products. Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 2-3: R/W-0 IRP STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC bit7 bit 7: R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. For devices with only Bank0 and Bank1, the IRP bit is reserved. Always maintain this bit clear. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 9 PIC16C72 Series 2.2.2.2 OPTION_REG REGISTER Note: The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 2-4: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. OPTION_REG REGISTER (ADDRESS 81h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit7 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 DS39016B-page 10 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 2.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 2-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON REGISTER (ADDRESS 0Bh, 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 11 PIC16C72 Series 2.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. FIGURE 2-6: Bit PEIE (INTCON) must be set to enable any peripheral interrupt. PIE1 REGISTER (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39016B-page 12 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 2.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts. FIGURE 2-7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1 REGISTER (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 13 PIC16C72 Series 2.2.2.6 PCON REGISTER Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. FIGURE 2-8: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word). PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS39016B-page 14 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 2.3 PCL and PCLATH The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register. FIGURE 2-9: Figure 2-9 shows the four situations for the loading of the PC. Example 1 shows how the PC is loaded on a write to PCL (PCLATH  PCH). Example 2 shows how the PC is loaded during a GOTO instruction (PCLATH  PCH). Example 3 shows how the PC is loaded during a CALL instruction (PCLATH  PCH), with the PC loaded (PUSHed) onto the Top of Stack. Finally, example 4 shows how the PC is loaded during one of the return instructions where the PC is loaded (POPed) from the Top of Stack. LOADING OF PC IN DIFFERENT SITUATIONS Situation 1 - Instruction with PCL as destination PCH STACK (13-bits x 8) Top of STACK PCL 12 8 7 0 PC 5 8 PCLATH ALU result PCLATH STACK (13-bits x 8) Situation 2 - GOTO Instruction PCH 12 11 10 Top of STACK PCL 8 0 7 PC 2 11 PCLATH Opcode PCLATH Situation 3 - CALL Instruction STACK (13-bits x 8) 13 Top of STACK PCH 12 11 10 PCL 8 7 0 PC 2 11 PCLATH Opcode PCLATH Situation 4 - RETURN, RETFIE, or RETLW Instruction 13 STACK (13-bits x 8) Top of STACK PCH 12 11 10 PCL 8 7 0 PC 11 Opcode PCLATH Note: PCLATH is not updated with the contents of PCH.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 15 PIC16C72 Series 2.3.1 2.4 STACK The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). An example of the overwriting of the stack is shown in Figure 2-10. Program Memory Paging The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH bits are not required for the return instructions (which POPs the address from the stack). Note: PIC16C72 Series devices ignore paging bit PCLATH. The use of PCLATH as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products. FIGURE 2-10: STACK MODIFICATION STACK Push1 Push9 Push2 Push10 Push3 Push4 Push5 Push6 Push7 Push8 DS39016B-page 16 Top of STACK Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 2.5 Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. EXAMPLE 2-1: A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. EXAMPLE 2-2: INDIRECT ADDRESSING • • • • Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h • Increment the value of the FSR register by one (FSR = 06) • A read of the INDR register now will return the value of 0Ah. movlw movwf clrf incf btfss goto NEXT HOW TO CLEAR RAM USING INDIRECT ADDRESSING 0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next CONTINUE : ;YES, continue FIGURE 2-11: DIRECT/INDIRECT ADDRESSING Direct Addressing RP1:RP0 6 Indirect Addressing from opcode 0 IRP 7 FSR register 0 (2) (2) bank select bank select location select 00 00h 01 80h 10 100h location select 11 180h not used (3) (3) Data Memory(1) 7Fh Bank 0 FFh 17Fh Bank 1 1FFh Bank 2 Bank 3 Note 1: For register file map detail see Figure 2-2. 2: Maintain RP1 and IRP as clear for upward compatibility with future products. 3: Not implemented.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 17 PIC16C72 Series NOTES: DS39016B-page 18 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 3.0 I/O PORTS FIGURE 3-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PIC® Mid-Range MCU Reference Manual, DS33023. 3.1 Data bus BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS D Q VDD WR Port Q CK PORTA and the TRISA Register Data Latch PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin. D WR TRIS Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). On a Power-on Reset, these pins are configured as analog inputs and read as '0'. N Q I/O pin(1) VSS Analog input mode Q CK TRIS Latch Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Note: P TTL input buffer RD TRIS Q D EN RD PORT To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 3-2: The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. Data bus WR PORT BLOCK DIAGRAM OF RA4/ T0CKI PIN D Q CK Q N I/O pin(1) Data Latch EXAMPLE 3-1: INITIALIZING PORTA BCF CLRF STATUS, RP0 PORTA BSF MOVLW STATUS, RP0 0xCF MOVWF TRISA ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Select Bank 1 Value used to initialize data direction Set RA as inputs RA as outputs TRISA are always read as '0'. WR TRIS D Q CK Q VSS Schmitt Trigger input buffer TRIS Latch RD TRIS Q D EN EN RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 19 PIC16C72 Series TABLE 3-1 PORTA FUNCTIONS Name Bit# Buffer RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI bit0 bit1 bit2 bit3 bit4 TTL TTL TTL TTL ST Function Input/output or analog input Input/output or analog input Input/output or analog input Input/output or analog input or VREF Input/output or external clock input for Timer0 Output is open drain type RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address Name Bit 7 Bit 6 05h PORTA — — 85h TRISA — — 9Fh ADCON1 — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 ---- -000 ---- -000 PORTA Data Direction Register — — — PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS39016B-page 20 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin. EXAMPLE 3-1: BCF CLRF BSF MOVLW MOVWF INITIALIZING PORTB STATUS, RP0 PORTB STATUS, RP0 0xCF TRISB ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Select Bank 1 Value used to initialize data direction Set RB as inputs RB as outputs RB as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. FIGURE 3-3: WR Port Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. b) A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. FIGURE 3-4: Data bus weak P pull-up WR Port Data Latch D Q CK BLOCK DIAGRAM OF RB7:RB4 PINS weak P pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q I/O pin(1) WR TRIS TRIS Latch D Q WR TRIS a) RBPU(2) VDD Data bus This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: VDD BLOCK DIAGRAM OF RB3:RB0 PINS RBPU(2) Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON). TTL Input Buffer CK TTL Input Buffer CK RD TRIS Q RD TRIS RD Port Latch D EN RD Port Q EN Q D RD Port EN RB0/INT RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION).  1998-2013 Microchip Technology Inc. Q1 Set RBIF D From other RB7:RB4 pins Schmitt Trigger Buffer ST Buffer Q3 RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION). Preliminary DS39016B-page 21 PIC16C72 Series TABLE 3-3 PORTB FUNCTIONS Name Bit# Buffer RB0/INT bit0 TTL/ST(1) Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Input/output pin (with interrupt on change). Internal software programmable RB6 bit6 TTL/ST(2) weak pull-up. Serial programming clock. Input/output pin (with interrupt on change). Internal software programmable RB7 bit7 TTL/ST(2) weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name 06h, 106h PORTB 86h, 186h TRISB 81h, 181h OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111 PORTB Data Direction Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS39016B-page 22 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 3.3 PORTC and the TRISC Register FIGURE 3-5: PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin. PORTC is multiplexed with several peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. EXAMPLE 3-1: INITIALIZING PORTC BCF CLRF STATUS, RP0 PORTC BSF MOVLW STATUS, RP0 0xCF MOVWF TRISC ; ; ; ; ; ; ; ; ; ; ; Select Bank 0 Initialize PORTC by clearing output data latches Select Bank 1 Value used to initialize data direction Set RC as inputs RC as outputs RC as inputs  1998-2013 Microchip Technology Inc. PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT D VDD 0 Q P 1 CK Q Data Latch WR TRIS D CK I/O pin(1) Q Q N TRIS Latch VSS Schmitt Trigger RD TRIS Peripheral OE(3) RD PORT Peripheral input Q D EN Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. Preliminary DS39016B-page 23 PIC16C72 Series TABLE 3-5 PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend: ST = Schmitt Trigger input TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC 1111 1111 1111 1111 PORTC Data Direction Register Legend: x = unknown, u = unchanged. DS39016B-page 24 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the PIC® Mid-Range MCU Reference Manual, DS33023. The Timer0 module timer/counter has the following features: • • • • • • 4.2 8-bit timer/counter Readable and writable Internal or external clock select Edge select for external clock 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. Figure 4-1 is a simplified block diagram of the Timer0 module. Additional information on timer modules is available in the PIC® Mid-Range MCU Reference Manual, DS33023. 4.1 The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG) determine the prescaler assignment and prescale ratio. Timer0 Operation Timer0 can operate as a timer or as a counter. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Timer mode is selected by clearing bit T0CS (OPTION_REG). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable. Counter mode is selected by setting bit T0CS (OPTION_REG). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in below. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. Note: When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. FIGURE 4-1: Prescaler Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 1 1 Programmable Prescaler RA4/T0CKI pin 0 8 Sync with Internal clocks TMR0 PSout (2 cycle delay) T0SE 3 PS2, PS1, PS0 PSA T0CS Set interrupt flag bit T0IF on overflow Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 25 PIC16C72 Series 4.2.1 4.3 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. Note: The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON). The interrupt can be masked by clearing bit T0IE (INTCON). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. To avoid an unintended device RESET, a specific instruction sequence (shown in the PIC® Mid-Range MCU Reference Manual, DS3023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. FIGURE 4-2: Timer0 Interrupt BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus CLKOUT (=Fosc/4) 0 RA4/T0CKI pin 8 M U X 1 M U X 0 1 SYNC 2 Cycles TMR0 reg T0SE T0CS 0 1 Watchdog Timer Set flag bit T0IF on Overflow PSA 8-bit Prescaler M U X 8 8 - to - 1MUX PS2:PS0 PSA 1 0 WDT Enable bit MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG). TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0 Address Name 01h,101h TMR0 0Bh,8Bh, 10Bh,18Bh INTCON 81h,181h OPTION_REG 85h TRISA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 module’s register GIE PEIE RBPU INTEDG — — Value on: POR, BOR Value on all other resets xxxx xxxx uuuu uuuu T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 --11 1111 --11 1111 PORTA Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. DS39016B-page 26 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 5.0 TIMER1 MODULE 5.1 The Timer1 module timer/counter has the following features: • 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L) • Readable and writable (Both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • Reset from CCP module trigger Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON). Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON). Figure 5-2 is a simplified block diagram of the Timer1 module. Additional information on timer modules is available in the PIC® Mid-Range MCU Reference Manual, DS33023. FIGURE 5-1: Timer1 Operation In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC value is ignored. Timer1 also has an internal “reset input”. This reset can be generated by the CCP module (Section 7.0). T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC R/W-0 R/W-0 TMR1CS TMR1ON bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 27 PIC16C72 Series FIGURE 5-2: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow TMR1H Synchronized clock input 0 TMR1 TMR1L 1 TMR1ON on/off T1SYNC T1OSC RC0/T1OSO/T1CKI RC1/T1OSI 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Synchronize Prescaler 1, 2, 4, 8 det 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39016B-page 28 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 5.2 5.3 Timer1 Oscillator A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1). 5.4 The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. TABLE 5-1 Freq C1 C2 LP 32 kHz 100 kHz 200 kHz 33 pF 15 pF 15 pF 33 pF 15 pF 15 pF Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1). Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A  20 PPM 100 kHz Epson C-2 100.00 KC-P  20 PPM 200 kHz STD XTL 200.000 kHz  20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. TABLE 5-2 Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Timer1 Interrupt In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1. REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented, read as '0'.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 29 PIC16C72 Series NOTES: DS39016B-page 30 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 6.0 TIMER2 MODULE 6.2 The Timer2 module timer has the following features: • • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (Both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register, shown in Figure 6-2. Timer2 can be shut off by clearing control bit TMR2ON (T2CON) to minimize power consumption. Figure 6-1 is a simplified block diagram of the Timer2 module. The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset. 6.3 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock. FIGURE 6-1: Sets flag bit TMR2IF Additional information on timer modules is available in the PIC® Mid-Range MCU Reference Manual, DS33023. 6.1 Timer2 Interrupt TIMER2 BLOCK DIAGRAM TMR2 output (1) Reset Postscaler 1:1 to 1:16 EQ TMR2 reg Comparator Prescaler 1:1, 1:4, 1:16 FOSC/4 2 Timer2 Operation 4 PR2 reg Timer2 can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1)). The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device reset (Power-on Reset, MCLR reset, Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 31 PIC16C72 Series FIGURE 6-2: U-0 — T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 TABLE 6-1 Address Bit 7 0Bh,8Bh INTCON 0Ch PIR1 8Ch PIE1 11h TMR2 12h T2CON 92h PR2 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Name Legend: 2: R/W-0 T2CKPS1 T2CKPS0 Bit 3 Bit 2 Bit 1 Value on: POR, BOR Bit 5 Bit 4 GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 Timer2 module’s register — Bit 0 Value on all other resets Bit 6 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 Timer2 Period Register x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. These bits are unimplemented, read as '0'. DS39016B-page 32 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 7.0 CAPTURE/COMPARE/PWM (CCP) MODULE Additional information on the CCP module is available in the PIC® Mid-Range MCU Reference Manual, DS33023. The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes. TABLE 7-1 Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. FIGURE 7-1: U-0 — bit7 U-0 — CCP MODE - TIMER RESOURCE CCP Mode Timer Resource Capture Compare PWM Timer1 Timer1 Timer2 CCP1CON REGISTER (ADDRESS 17h) R/W-0 R/W-0 R/W-0 CCP1X CCP1Y CCP1M3 R/W-0 CCP1M2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 33 PIC16C72 Series 7.1 Capture Mode 7.1.4 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON). When a capture is made, the interrupt request flag bit CCP1IF (PIR1) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 7.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. FIGURE 7-2: CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. EXAMPLE 7-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW CCP1CON NEW_CAPT_PS MOVWF CCP1CON ;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value CAPTURE MODE OPERATION BLOCK DIAGRAM Prescaler  1, 4, 16 Set flag bit CCP1IF (PIR1) RC2/CCP1 Pin CCPR1H and edge detect CCPR1L Capture Enable TMR1H TMR1L CCP1CON Q’s 7.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 7.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode. DS39016B-page 34 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 7.2 7.2.1 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • driven High • driven Low • remains Unchanged The user must configure the RC2/CCP1 pin as an output by clearing the TRISC bit. Note: 7.2.2 The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON). At the same time, interrupt flag bit CCP1IF is set. FIGURE 7-3: CCP PIN CONFIGURATION COMPARE MODE OPERATION BLOCK DIAGRAM TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 7.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1), and set bit GO/DONE (ADCON0) which starts an A/D conversion 7.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated which may be used to initiate an action. Special Event Trigger Set flag bit CCP1IF (PIR1) CCPR1H CCPR1L Q S Output Logic match RC2/CCP1 R Pin TRISC Output Enable CCP1CON Mode Select Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. Comparator TMR1H TMR1L The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). Note: TABLE 7-2 Address The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1). REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Bit 6 Bit 5 Bit 4 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — — Bit 2 Bit 1 Bit 0 Value on all other resets Bit 7 — Bit 3 Value on: POR, BOR Name RBIF 0000 000x 0000 000u T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits/registers are unimplemented, read as '0'.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 35 PIC16C72 Series 7.3 PWM Mode 7.3.1 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 7-4 shows a simplified block diagram of the CCP module in PWM mode. For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3. FIGURE 7-4: SIMPLIFIED PWM BLOCK DIAGRAM The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is latched from CCPR1L into CCPR1H Note: CCP1CON Duty cycle registers CCPR1L 7.3.2 CCPR1H (Slave) R Comparator Q RC2/CCP1 TMR2 (Note 1) S Clear Timer, CCP1 pin and latch D.C. PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base. A PWM output (Figure 7-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 7-5: PWM OUTPUT The Timer2 postscaler (see Section 6.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON) • Tosc • (TMR2 prescale value) TRISC Comparator PWM PERIOD CCPR1L and CCP1CON can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: Period log = Duty Cycle ( FOSC FPWM ) bits log(2) TMR2 = PR2 TMR2 = Duty Cycle Note: TMR2 = PR2 DS39016B-page 36 Preliminary If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared.  1998-2013 Microchip Technology Inc. PIC16C72 Series For an example PWM period and duty cycle calculation, see the PIC® Mid-Range MCU Reference Manual (DS33023). 7.3.3 SET-UP FOR PWM OPERATION 3. 4. 5. Make the CCP1 pin an output by clearing the TRISC bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON bits. TABLE 7-3 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 7-4 Address 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 5.5 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC 11h 92h 12h T2CON 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON RBIF 0000 000x 0000 000u PORTC Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 module’s register 0000 0000 0000 0000 PR2 Timer2 module’s period register 1111 1111 1111 1111 — — TOUTPS TOUTPS TOUTPS TOUTPS 3 2 1 0 — CCP1X CCP1Y TMR2O N T2CKPS T2CKPS -000 0000 -000 0000 1 0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: These bits/registers are unimplemented, read as '0'.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 37 PIC16C72 Series NOTES: DS39016B-page 38 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 8.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 8.1 SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SSP module in I2C mode works the same in all PIC16C72 series devices that have an SSP module. However the SSP Module in SPI mode has differences between the PIC16C72 and the PIC16CR72 device. The register definitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C72 and the PIC16CR72 device. The default reset values of both the SPI modules is the same regardless of the device: 8.2 SPI Mode for PIC16C72 .................................. 40 8.3 SPI Mode for PIC16CR72 ............................... 43 8.4 SSP I2C Operation .......................................... 47 For an I2C Overview, refer to the PIC® Mid-Range MCU Reference Manual (DS33023). Also, refer to Application Note AN578, “Use of the SSP Module in the I 2C Multi-Master Environment.”  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 39 PIC16C72 Series 8.2 SPI Mode for PIC16C72 This section contains register definitions and operational characteristics of the SPI module on the PIC16C72 device only. FIGURE 8-1: U-0 — bit7 U-0 — Additional information on SPI operation may be found in the PIC® Mid-Range MCU Reference Manual, DS33023. SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) (PIC16C72) R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS39016B-page 40 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series FIGURE 8-2: R/W-0 WCOL bit7 SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16C72) R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Detect bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge. 0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge. In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master operation, clock = Fosc/4 0001 = SPI master operation, clock = Fosc/16 0010 = SPI master operation, clock = Fosc/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master operation (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled 8.2.1 OPERATION OF SSP MODULE IN SPI MODE - PIC16C72  1998-2013 Microchip Technology Inc. A block diagram of the SSP Module in SPI Mode is shown in Figure 8-3. Preliminary DS39016B-page 41 PIC16C72 Series FIGURE 8-3: The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) • Serial Data In (SDI) • Serial Clock (SCK) RC5/SDO RC4/SDI/SDA RC3/SCK/SCL SSP BLOCK DIAGRAM (SPI MODE) Internal data bus Read Additionally a fourth pin may be used when in a slave mode of operation: • Slave Select (SS) SSPBUF reg RA5/SS/AN4 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON). These control bits allow the following to be specified: SSPSR reg RC4/SDI/SDA • Master Operation (SCK is the clock output) • Slave Mode (SCK is the clock input) • Clock Polarity (Output/Input data on the Rising/ Falling edge of SCK) • Clock Rate (master operation only) • Slave Select Mode (Slave mode only) shift clock bit0 RC5/SDO SS Control Enable RA5/SS/AN4 Edge Select To enable the serial port, SSP enable bit SSPEN (SSPCON) must be set. To reset or reconfigure SPI mode, clear enable bit SSPEN, re-initialize SSPCON register, and then set enable bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed. That is: 2 Clock Select SSPM3:SSPM0 TMR2 output 2 4 Edge Select • SDI must have TRISC set • SDO must have TRISC cleared • SCK (master operation) must have TRISC cleared • SCK (Slave mode) must have TRISC set • SS must have TRISA set (if implemented) TABLE 8-1 Write RC3/SCK/ SCL Prescaler TCY 4, 16, 64 TRISC REGISTERS ASSOCIATED WITH SPI OPERATION Value on: POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0000 000x 0000 000u PIR1 (1) 8Ch PIE1 (1) 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON 85h TRISA — — 94h SSPSTAT — — 0Ch WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 PORTA Data Direction Register D/A P S R/W 0000 0000 0000 0000 --11 1111 --11 1111 UA BF --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: These bits are unimplemented, read as '0'. DS39016B-page 42 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 8.3 SPI Mode for PIC16CR72 This section contains register definitions and operational characteristics of the SPI module on the PIC16CR72 device only. FIGURE 8-4: R/W-0 R/W-0 SMP CKE Additional information on SPI operation may be found in the PIC® Mid-Range MCU Reference Manual, DS33023. SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) (PIC16CR72) R-0 R-0 R-0 R-0 R-0 R-0 D/A P S R/W UA BF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode bit 6: CKE: SPI Clock Edge Select CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 43 PIC16C72 Series FIGURE 8-5: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16CR72) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master operation, clock = FOSC/4 0001 = SPI master operation, clock = FOSC/16 0010 = SPI master operation, clock = FOSC/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master operation (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled 8.3.1 OPERATION OF SSP MODULE IN SPI MODE - PIC16CR72 DS39016B-page 44 A block diagram of the SSP Module in SPI Mode is shown in Figure 8-6. Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) • Serial Data In (SDI) • Serial Clock (SCK) FIGURE 8-6: SSP BLOCK DIAGRAM (SPI MODE)(PIC16CR72) Internal data bus RC5/SDO RC4/SDI/SDA RC3/SCK/SCL Read Write SSPBUF reg Additionally a fourth pin may be used when in a slave mode of operation: • Slave Select (SS) RA5/SS/AN4 SSPSR reg When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON) and SSPSTAT. These control bits allow the following to be specified: • • • • Master Operation (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock Edge (Output data on rising/falling edge of SCK) • Clock Rate (master operation only) • Slave Select Mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN (SSPCON) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: RC4/SDI/SDA shift clock bit0 RC5/SDO SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TMR2 output 2 Prescaler TCY 4, 16, 64 TRISC • SDI must have TRISC set • SDO must have TRISC cleared • SCK (master operation) must have TRISC cleared • SCK (Slave mode) must have TRISC set • SS must have TRISA set Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON = 0100) the SPI module will reset if the SS pin is set to VDD. Note: If the SPI is used in Slave Mode with CKE = '1', then the SS pin control must be enabled.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 45 PIC16C72 Series TABLE 8-2 REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16CR72) Value on: POR, BOR Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0000 000x 0000 000u PIR1 (1) 8Ch PIE1 (1) 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL 85h TRISA 94h SSPSTAT 0Ch SSPOV SSPEN — — SMP CKE CKP SSPM3 SSPM2 SSPM1 SSPM0 PORTA Data Direction Register D/A P S R/W 0000 0000 0000 0000 --11 1111 --11 1111 UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Always maintain these bits clear. DS39016B-page 46 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 8.4 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON). FIGURE 8-7: SSPBUF reg When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. SSPSR reg MSb LSb Match detect Addr Match Set, Reset S, P bits (SSPSTAT reg) The SSP module has five registers for I2C operation. These are the: • • • • SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible • SSP Address Register (SSPADD)  1998-2013 Microchip Technology Inc. There are certain conditions that will cause the SSP module not to give this ACK pulse. These are if either (or both): a) SSPADD reg Start and Stop bit detect SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs (TRISC set). The SSP module will override the input state with the output data when required (slave-transmitter). Write shift clock RC4/ SDI/ SDA Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. 8.4.1 Internal data bus RC3/SCK/SCL • I 2C Slave mode (7-bit address) • I 2C Slave mode (10-bit address) • I 2C Slave mode (7-bit address), with start and stop bit interrupts enabled • I 2C Slave mode (10-bit address), with start and stop bit interrupts enabled • I 2C Firmware controlled master operation, slave is idle Additional information on SSP I2C operation may be found in the PIC® Mid-Range MCU Reference Manual, DS33023. SSP BLOCK DIAGRAM (I2C MODE) Read The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow one of the following I 2C modes to be selected: b) The buffer full bit BF (SSPSTAT) was set before the transfer was received. The overflow bit SSPOV (SSPCON) was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1) is set. Table 8-3 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101. Preliminary DS39016B-page 47 PIC16C72 Series 8.4.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1) is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal TABLE 8-3 ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. 2. 3. 4. 5. 6. 7. 8. 9. Receive first (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV SSPSR  SSPBUF Generate ACK Pulse 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes DS39016B-page 48 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 8.4.1.2 RECEPTION When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT) is set or bit SSPOV (SSPCON) is set. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 8-8: Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. S 1 2 3 4 5 6 7 SSPIF (PIR1) BF (SSPSTAT) 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 Cleared in software 9 P Bus Master terminates transfer SSPBUF register is read SSPOV (SSPCON) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 49 PIC16C72 Series 8.4.1.3 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 8-9). I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) FIGURE 8-9: Receiving Address SDA SCL A7 S As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP. A6 1 2 Data in sampled R/W = 1 A5 A4 A3 A2 A1 3 4 5 6 7 Transmitting Data ACK 8 9 D7 1 SCL held low while CPU responds to SSPIF ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P cleared in software SSPIF (PIR1) BF (SSPSTAT) SSPBUF is written in software From SSP interrupt service routine CKP (SSPCON) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) DS39016B-page 50 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 8.4.2 8.4.3 MASTER OPERATION MULTI-MASTER OPERATION In multi-master operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. Master operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear. In master operation, the SCL and SDA lines are manipulated in firmware by clearing the corresponding TRISC bit(s). The output level is always low, irrespective of the value(s) in PORTC. So when transmitting data, a '1' data bit must have the TRISC bit set (input) and a '0' data bit must have the TRISC bit cleared (output). The same scenario is true for the SCL line with the TRISC bit. In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC). There are two stages where this arbitration can be lost, these are: The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): • Address Transfer • Data Transfer • START condition • STOP condition • Data transfer byte transmitted/received When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. Master operation can be done with either the slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. For more information on master operation, see AN578 - Use of the SSP Module in the of I2C Multi-Master Environment. For more information on master operation, see AN554 - Software Implementation of I2C Bus Master. REGISTERS ASSOCIATED WITH I2C OPERATION TABLE 8-4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other resets 0Bh, 8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN 0000 0000 0000 0000 94h SSPSTAT SMP(2) CKE(2) 0000 0000 0000 0000 87h TRISC 1111 1111 1111 1111 D/A CKP P SSPM3 SSPM2 SSPM1 SSPM0 S PORTC Data Direction register R/W UA BF Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: These bits are unimplemented, read as '0'. 2: The SMP and CKE bits are implemented on the PIC16CR72 only. On the PIC16C72, these two bits are unimplemented, read as '0'.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 51 PIC16C72 Series NOTES: DS39016B-page 52 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 9.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE Additional information on the A/D module is available in the PIC® Mid-Range MCU Reference Manual, DS33023. The analog-to-digital (A/D) converter module has five inputs for the PIC16C72/R72. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s positive supply voltage (VDD) or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. FIGURE 9-1: The A/D module has three registers. These registers are: • A/D Result Register (ADRES) • A/D Control Register 0 (ADCON0) • A/D Control Register 1 (ADCON1) A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The ADCON0 register, shown in Figure 9-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 9-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O. ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 ADCS1 ADCS0 bit7 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 — R/W-0 ADON bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an internal RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 53 PIC16C72 Series FIGURE 9-2: U-0 — bit7 ADCON1 REGISTER (ADDRESS 9Fh) U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D VREF VDD RA3 VDD RA3 VDD RA3 GND A = Analog input D = Digital I/O DS39016B-page 54 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 9-3. 2. 3. 4. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. 5. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 9.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. OR 6. 7. Configure the A/D module: • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) FIGURE 9-3: Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit Wait the required acquisition time. Start conversion: • Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared • Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. A/D BLOCK DIAGRAM CHS2:CHS0 100 RA5/AN4 VAIN 011 (Input voltage) RA3/AN3/VREF 010 RA2/AN2 A/D Converter 001 RA1/AN1 VDD 000 RA0/AN0 000 or 010 or 100 VREF (Reference voltage) 001 or 011 or 101 PCFG2:PCFG0  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 55 PIC16C72 Series 9.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. FIGURE 9-4: To calculate the minimum acquisition time, TACQ, see the PIC® Mid-Range MCU Reference Manual, DS33023. This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. ANALOG INPUT MODEL VDD Rs ANx CPIN 5 pF VA Sampling Switch VT = 0.6V VT = 0.6V RIC  1k SS RSS CHOLD = DAC capacitance = 51.2 pF I leakage  500 nA VSS Legend CPIN = input capacitance = threshold voltage VT I leakage = leakage current at the pin due to various junctions RIC SS CHOLD DS39016B-page 56 = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) Preliminary 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch ( k )  1998-2013 Microchip Technology Inc. PIC16C72 Series 9.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • 2TOSC 8TOSC 32TOSC Internal RC oscillator Table 9-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. The ADCON1, TRISA, and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins), may cause the input buffer to consume current that is out of the devices specification. TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Operation ADCS1:ADCS0 2TOSC 00 8TOSC 01 32TOSC Configuring Analog Port Pins The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. TABLE 9-1 9.3 10 Device Frequency 20 MHz 100 ns(2) ns(2) 400 1.6 s 5 MHz ns(2) 400 1.6 s 6.4 s 1.25 MHz 333.33 kHz 1.6 s 6 s 6.4 s 24 s(3) 25.6 s(3) 96 s(3) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1) 2 - 6 s(1,4) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. RC(5) Legend: Note 1: 2: 3: 4: 11  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 57 PIC16C72 Series 9.4 Note: 9.5 A/D Conversions GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion). The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Use of the CCP Trigger An A/D conversion can be started by the “special event trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the TABLE 9-2 If the A/D module is not enabled (ADON is cleared), then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter. REGISTERS/BITS ASSOCIATED WITH A/D Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 xxxx xxxx uuuu uuuu CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 8Ch PIE1 1Eh ADRES A/D Result Register 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 9Fh ADCON1 — — 05h PORTA — — 85h TRISA — — — RA5 — RA4 RA3 RA2 PORTA Data Direction Register RA1 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. DS39016B-page 58 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 10.0 SPECIAL FEATURES OF THE CPU ble. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. The PIC16C72 series has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. • Oscillator selection • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • SLEEP • Code protection • ID locations • In-Circuit Serial Programming™ Additional information on special features is available in the PIC® Mid-Range MCU Family Reference Manual, DS33023. 10.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The PIC16CXXX family has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is sta- The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming. FIGURE 10-1: CONFIGURATION WORD FOR PIC16C72/R72 CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE bit13 WDTE FOSC1 FOSC0 bit0 bit 13-8 5-4: CP1:CP0: Code Protection bits (2) 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Register:CONFIG Address2007h Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 59 PIC16C72 Series 10.2 Oscillator Configurations 10.2.1 OSCILLATOR TYPES TABLE 10-1 Ranges Tested: The PIC16CXXX family can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 10.2.2 Mode XT 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz TABLE 10-2 Osc Type C2(1) Note1: 2: 3: LP XT To internal logic PIC16CXXX FIGURE 10-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 PIC16CXXX Open DS39016B-page 60 OSC2  0.3%  0.5%  0.5%  0.5%  0.5% CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Cap. Range C1 Cap. Range C2 33 pF 32 kHz 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 15 pF 4 MHz 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes at bottom of page. See Table 10-1 and Table 10-2 for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen. Clock from ext. system HS SLEEP RS(2) Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX All resonators used did not have built-in capacitors. OSC1 OSC2 OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF Resonators Used: FIGURE 10-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) RF(3) OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF These values are for design guidance only. See notes at bottom of page. In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 10-2). The PIC16CXXX family oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 10-3). XTAL Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz HS CRYSTAL OSCILLATOR/CERAMIC RESONATORS C1(1) CERAMIC RESONATORS Crystals Used 32 kHz Epson C-001R32.768K-A ± 20 PPM 200 kHz STD XTL 200.000KHz ± 20 PPM 1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM 20 MHz EPSON CA-301 20.000M-C ± 30 PPM Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 10-1). 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 10.2.3 RC OSCILLATOR 10.3 For timing insensitive applications the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 10-4 shows how the R/C combination is connected to the PIC16CXXX family. FIGURE 10-4: RC OSCILLATOR MODE VDD Rext OSC1 Cext Internal clock PIC16CXXX VSS Fosc/4 Recommended values: OSC2/CLKOUT 3 k  Rext  100 k Cext > 20pF  1998-2013 Microchip Technology Inc. Reset The PIC16CXXX family differentiates between various kinds of reset: • • • • • Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (normal operation) Brown-out Reset (BOR) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 10-5. The PIC16C72/CR72 have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Preliminary DS39016B-page 61 PIC16C72 Series FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset S BODEN OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. DS39016B-page 62 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 10.4 10.5 Power-On Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. For a slow rise time, see Figure 10-6. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the startup conditions. FIGURE 10-6: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) D The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. 10.6 R R1 MCLR C PIC16CXXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device’s electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).  1998-2013 Microchip Technology Inc. Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 10.7 VDD Power-up Timer (PWRT) Brown-Out Reset (BOR) A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for greater than parameter #35, the brown-out situation will reset the chip. A reset may not occur if VDD falls below 4.0V for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will now be invoked and will keep the chip in RESET an additional 72 ms. If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Preliminary DS39016B-page 63 PIC16C72 Series 10.8 Time-out Sequence 10.9 On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 10-7, Figure 10-8, Figure 10-9 and Figure 10-10 depict timeout sequences on power-up. Power Control/Status Register (PCON) The Power Control/Status Register, PCON has up to two bits, depending upon the device. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR cleared, indicating a BOR occurred. The BOR bit is a "Don’t Care" bit and is not necessarily predictable if the Brown-out Reset circuitry is disabled (by clearing bit BODEN in the Configuration Word). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 10-9). This is useful for testing purposes or to synchronize more than one PIC16CXXX family device operating in parallel. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. Table 10-5 shows the reset conditions for some special function registers, while Table 10-6 shows the reset conditions for all the registers. TABLE 10-3 TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration Power-up Brown-out Wake-up from SLEEP PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — TABLE 10-4 STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 x x Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 10-5 RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu PC + 1 uuu0 0uuu ---- --uu 000h 0001 1uuu ---- --u0 PC + 1(1) uuu1 0uuu ---- --uu Condition WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). DS39016B-page 64 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series TABLE 10-6 Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu 0000h 0000h PC + 1(2) W PCL (3) uuuq quuu(3) STATUS 0001 1xxx FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA --0x 0000 --0u 0000 --uu uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PORTC xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu(1) PIR1 -0-- 0000 -0-- 0000 -u-- uuuu(1) TMR1L xxxx xxxx uuuu uuuu uuuu uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu T1CON --00 0000 --uu uuuu --uu uuuu TMR2 0000 0000 0000 0000 uuuu uuuu T2CON -000 0000 -000 0000 -uuu uuuu SSPBUF xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 0000 0000 0000 0000 uuuu uuuu CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON --00 0000 --00 0000 --uu uuuu ADRES xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION 1111 1111 1111 1111 uuuu uuuu TRISA --11 1111 --11 1111 --uu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu TRISC 1111 1111 1111 1111 uuuu uuuu PIE1 -0-- 0000 -0-- 0000 -u-- uuuu PCON ---- --0u ---- --uu ---- --uu PR2 1111 1111 1111 1111 1111 1111 SSPADD 0000 0000 0000 0000 uuuu uuuu SSPSTAT --00 0000 --00 0000 --uu uuuu ADCON1 ---- -000 ---- -000 ---- -uuu 000q quuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 10-5 for reset value for specific condition.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 65 PIC16C72 Series FIGURE 10-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39016B-page 66 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series FIGURE 10-10: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 67 PIC16C72 Series 10.10 Interrupts For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit The PIC16C72/CR72 has 8 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. 10.10.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 10.13 for details on SLEEP mode. A global interrupt enable bit, GIE (INTCON) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. 10.10.2 TMR0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set flag bit T0IF (INTCON). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON). (Section 4.0) The peripheral interrupt flags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON. 10.10.3 PORTB INTCON CHANGE An input change on PORTB sets flag bit RBIF (INTCON). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON). (Section 3.2) When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. FIGURE 10-11: INTERRUPT LOGIC T0IF T0IE Wake-up (If in SLEEP mode) INTF INTE ADIF ADIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE RBIF RBIE Interrupt to CPU Clear GIE bit PEIE GIE TMR2IF TMR2IE DS39016B-page 68 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 10.11 The example: Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, i.e., W register and STATUS register. This will have to be implemented in software. Example 10-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). a) b) c) d) e) Stores the W register. Stores the STATUS register in bank 0. Executes the ISR code. Restores the STATUS register (and bank select bit). Restores the W register. EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to W_TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :Interrupt Service Routine (ISR) - user defined : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 69 PIC16C72 Series 10.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. . The WDT can be permanently disabled by clearing configuration bit WDTE (Section 10.1). FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 4-2) 0 WDT Timer Postscaler M U X 1 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure 4-2) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION register. FIGURE 10-13: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name 2007h Config. bits 81h,181h OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 10-1 for operation of these bits. DS39016B-page 70 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 10.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS) is cleared, the TO (STATUS) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 10.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or some Peripheral Interrupts. External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in slave mode (SPI/I2C). CCP capture mode interrupt. A/D conversion (when A/D clock source is RC). Special event trigger (Timer1 in asynchronous mode using an external clock).  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 71 PIC16C72 Series Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 10.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. • If the interrupt occurs before the execution of a FIGURE 10-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON) Interrupt Latency (Note 2) GIE bit (INTCON) Processor in SLEEP INSTRUCTION FLOW PC Instruction fetched Instruction executed Note 1: 2: 3: 4: 10.14 PC Inst(PC) = SLEEP Inst(PC - 1) PC+1 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) 10.15 PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference. Program Verification/Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: PC+2 Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. DS39016B-page 72 For ROM devices, these values are submitted along with the ROM code. 10.16 In-Circuit Serial Programming™ PIC16CXXX family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSP™) Guide, DS30277. Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 73 PIC16C72 Series DS39016B-page 74 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 11.0 INSTRUCTION SET SUMMARY Each PIC16CXXX family instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXXX family instruction set summary in Table 11-2 lists byteoriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. Table 11-2 lists the instructions recognized by the MPASM assembler. Figure 11-1 shows the general formats that the instructions can have. Note: All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. FIGURE 11-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) OPCODE FIELD DESCRIPTIONS Field Description f Register file address (0x00 to 0x7F) Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label General x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 13 PC Literal and control operations Time-out bit Power-down bit 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 Program Counter TO 8 OPCODE Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 PD 0 b = 3-bit bit address f = 7-bit file register address W d 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. TABLE 11-1 To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions. 11 OPCODE 10 0 k (literal) k = 11-bit immediate value The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations A description of each instruction is available in the PIC® Mid-Range MCU Family Reference Manual, DS33023. All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 75 PIC16C72 Series TABLE 11-2 Mnemonic, Operands PIC16CXXX INSTRUCTION SET Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z Z Z Z Z Z Z Z C C C,DC,Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 01 01 01 01 1,2 1,2 3 3 LITERAL AND CONTROL OPERATIONS 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 C,DC,Z Z TO,PD Z TO,PD C,DC,Z Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS39016B-page 76 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 12.0 DEVELOPMENT SUPPORT 12.1 Development Tools The PICmicr microcontrollers are supported with a full range of hardware and software development tools: • PICMASTER/PICMASTER CEReal-Time In-Circuit Emulator • ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator • PRO MATE II Universal Programmer • PICSTART Plus Entry-Level Prototype Programmer • PICDEM-1 Low-Cost Demonstration Board • PICDEM-2 Low-Cost Demonstration Board • PICDEM-3 Low-Cost Demonstration Board • MPASM Assembler • MPLABSIM Software Simulator • MPLAB-C17 (C Compiler) • Fuzzy Logic Development System (fuzzyTECHMP) A description of each development tool is available in the Midrange Reference Manual, DS33023. 12.2 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 77 PIC16C72 Series NOTES: DS39016B-page 78 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 13.0 ELECTRICAL CHARACTERISTICS - PIC16C72 SERIES Absolute Maximum Ratings † Parameter Ambient temperature under bias Storage temperature PIC16C72 PIC16CR72 -55 to +125°C -55 to +125°C -65°C to +150°C -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS -0.3 to +7.5V TBD Voltage on MCLR with respect to VSS (Note 1) -0.3 to +14V TBD Voltage on RA4 with respect to Vss -0.3 to +14V TBD Total power dissipation (Note 2) 1.0W 1.0W Maximum current out of VSS pin 300 mA 300 mA Maximum current into VDD pin 250 mA 250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA 20 mA Maximum output current sunk by any I/O pin 25 mA 25 mA Maximum output current sourced by any I/O pin 25 mA 25 mA Maximum current sunk by PORTA and PORTB (combined) 200 mA 200 mA Maximum current sourced by PORTA and PORTB (combined) 200 mA 200 mA Maximum current sunk by PORTC 200 mA 200 mA Maximum current sourced by PORTC 200 mA 200 mA 1. 2. Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD - VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 79 PIC16C72 Series TABLE 13-1 OSC CROSS REFERENCE OF DEVICE SPECS (PIC16C72) FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C72-04 PIC16C72-10 PIC16C72-20 PIC16LC72-04 JW Devices RC VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 6.0V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V Not recommended for use in HS mode IDD: 20 mA max. at 5.5V HS LP IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Not recommended for use in LP mode Not recommended for use in LP mode VDD: 4.5V to 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 6.0V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. TABLE 13-2 OSC CROSS REFERENCE OF DEVICE SPECS (PIC16CR72) FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16CR72-04 PIC16CR72-10 PIC16CR72-20 PIC16LCR72-04 JW Devices RC VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. XT VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 A typ. at 4V Freq: 4 MHz max. VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3.0V IPD: 5.0 A max. at 3V Freq: 4 MHz max. VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V Not recommended for use in HS mode IDD: 20 mA max. at 5.5V HS LP IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. VDD: 4.0V to 5.5V IDD: 52.5 A typ. at 32 kHz, 4.0V IPD: 0.9 A typ. at 4.0V Freq: 200 kHz max. Not recommended for use in LP mode Not recommended for use in LP mode VDD: 4.5V to 5.5V IPD: 1.5 A typ. at 4.5V Freq: 20 MHz max. VDD: 2.5V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. VDD: 2.5V to 5.5V IDD: 48 A max. at 32 kHz, 3.0V IPD: 5.0 A max. at 3.0V Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. DS39016B-page 80 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 13.1 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym PIC16C72 PIC16CR72 Min Typ† Max Min Typ† Max Units Conditions D001 D001A Supply Voltage VDD 4.0 4.5 - 6.0 5.5 4.0 4.5 - 5.5 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - - 1.5 - V D003 VDD start voltage to ensure internal Poweron Reset Signal VPOR - VSS - - VSS - V See section on Poweron Reset for details D004* VDD rise rate to ensure internal Power-on Reset Signal SVDD 0.05 - - 0.05 - - V/ms See section on Poweron Reset for details D005 Brown-out Reset Voltage Bvdd 3.7 4.0 4.3 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 3.7 4.0 4.4 V Extended Only - 2.7 5.0 - 2.7 5.0 mA XT, RC osc FOSC = 4 MHz, VDD = 5.5V (Note 4) - 10 20 - 10 20 mA HS osc FOSC = 20 MHz, VDD = 5.5V Ibor - 350 425 - 350 425 A BOR enabled, VDD = 5.0V IPD - 10.5 42 - 10.5 42 A VDD = 4.0V, WDT enabled, -40C to +85C D021 - 1.5 16 - 1.5 16 A VDD = 4.0V, WDT disabled, -0C to +70C D021A - 1.5 19 - 1.5 19 A VDD = 4.0V, WDT disabled, -40C to +85C D021B - 2.5 19 - 2.5 19 A VDD = 4.0V, WDT disabled, -40C to +125C - 350 425 - 350 425 A BOR enabled VDD = 5.0V D010 Supply Current (Note 2,5) IDD D013 D015 Brown-out Reset Current (Note 6) D020 Power-down Current (Note 3,5) D023 * † Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Brown-out Reset Current (Note 6) Ibor XT, RC and LP osc HS osc These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 81 PIC16C72 Series 13.2 DC Characteristics: DC CHARACTERISTICS Param No. Characteristic PIC16LC72/LCR72-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Sym PIC16C72 Min PIC16CR72 Typ† Max Min Typ† Max Units Conditions LP, XT, RC (DC - 4 MHz) D001 Supply Voltage VDD 2.5 - 6.0 2.5 - 5.5 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - - 1.5 - V D003 VDD start voltage to ensure internal Poweron Reset signal VPOR - VSS - - VSS - V See section on Poweron Reset for details D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - 0.05 - - V/ms See section on Poweron Reset for details D005 Brown-out Reset Voltage Bvdd 3.7 4.0 4.3 3.7 4.0 4.3 V BODEN bit in configuration word enabled D010 Supply Current (Note 2,5) IDD - 2.0 3.8 - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) - 22.5 48 - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled Ibor - 350 425 - 350 425 A BOR enabled VDD = 5.0V IPD - 7.5 30 - 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 - 0.9 5 - 0.9 5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.9 5 - 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C - 350 425 - 350 425 A BOR enabled VDD = 5.0V D010A D015* Brown-out Reset Current (Note 6) D020 Power-down Current (Note 3,5) D023* * † Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Brown-out Reset Current (Note 6) Ibor These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS39016B-page 82 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 13.3 DC Characteristics: PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended) PIC16LC72/LCR72-04 (Commercial, Industrial) DC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Sym Min Typ† Max Units Conditions VSS - 0.15VDD V For entire VDD range Vss - 0.8V V 4.5  VDD 5.5V Input Low Voltage I/O ports D030 VIL with TTL buffer D030A D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 2.0 - VDD V 4.5  VDD 5.5V 0.25VDD + 0.8V - VDD V For entire VDD range For entire VDD range Input High Voltage I/O ports D040 VIH with TTL buffer D040A - D041 with Schmitt Trigger buffer 0.8VDD - VDD V D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - Vdd V D043 OSC1 (in RC mode) 0.9VDD - VDD V Note1 D070 PORTB weak pull-up current IPURB 50 250 †400 A VDD = 5V, VPIN = VSS IIL - - 1 A Vss VPIN VDD, Pin at hiimpedance Input Leakage Current (Notes 2, 3) D060 I/O ports D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration D080 I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C Output Low Voltage D080A D083 OSC2/CLKOUT (RC osc config) D083A * † Note 1: Note 2: Note 3: VOL These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 83 PIC16C72 Series DC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Sym Min Typ† Max Units Conditions VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C Output High Voltage D090 I/O ports (Note 3) D090A D092 OSC2/CLKOUT (RC osc config) D092A D150* Open-Drain High Voltage Vod - - 14 V RA4 pin, PIC16C72/LC72 - - TBD V RA4 pin, PIC16CR72/LCR72 COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. CIO Cb - - 50 400 pF pF Capacitive Loading Specs on Output Pins D100 OSC2 pin D101 D102 All I/O pins and OSC2 (in RC mode) SCL, SDA in I2C mode * † Note 1: Note 2: Note 3: These parameters are characterized but not tested. Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. DS39016B-page 84 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series 13.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T Time T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance AA output access High High BUF Bus free Low Low Hold SU Setup DAT DATA input hold STO STOP condition STA START condition I2C only TCC:ST (I2C specifications only) CC HD ST FIGURE 13-1: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 CL = 50 pF 15 pF  1998-2013 Microchip Technology Inc. for all pins except OSC2 for OSC2 output Preliminary DS39016B-page 85 PIC16C72 Series 13.5 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKOUT TABLE 13-3 Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Fosc Characteristic Min External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 TCY 3 TosL, TosH 4 † Note 1: TosR, TosF Typ† Max Units Conditions DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode DC — 4 MHz RC osc mode 0.1 — 4 MHz XT osc mode 4 5 — — 20 200 MHz kHz HS osc mode LP osc mode 250 — — ns XT and RC osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode 250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 50 — — 250 250 ns ns HS osc mode (-10) HS osc mode (-20) 5 — — s LP osc mode Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC External Clock in (OSC1) High or Low Time 100 — — ns XT oscillator 2.5 — — s LP oscillator 15 — — ns HS oscillator — — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator External Clock in (OSC1) Rise or Fall Time Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS39016B-page 86 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series FIGURE 13-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 13-1 for load conditions. TABLE 13-4 CLKOUT AND I/O TIMING REQUIREMENTS Parameter No. Sym 10* TosH2ckL 11* 12* 13* TckF 14* TckL2ioV 15* TioV2ckH Port in valid before CLKOUT  16* TckH2ioI Port in hold after CLKOUT  17* TosH2ioV OSC1 (Q1 cycle) to Port out valid 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Characteristic Min Typ† Max Units Conditions OSC1 to CLKOUT — 75 200 ns Note 1 TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 TckR CLKOUT rise time — 35 100 ns Note 1 CLKOUT fall time — 35 100 ns Note 1 CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 TOSC + 200 — — ns Note 1 0 — — ns Note 1 — 50 150 ns PIC16C72/CR72 100 — — ns PIC16LC72/LCR72 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C72/CR72 — 10 40 ns PIC16LC72/LCR72 — — 80 ns 21* TioF Port output fall time PIC16C72/CR72 — 10 40 ns — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns Trbp RB7:RB4 change INT high or low time TCY — — ns PIC16LC72/LCR72 23††* * † †† Note 1: These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 87 PIC16C72 Series FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 13-1 for load conditions. FIGURE 13-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 13-5 Parameter No. Sym Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40°C to +125°C 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O Hi-impedance from MCLR Low or Watchdog Timer Reset — — 2.1 s TBOR Brown-out Reset pulse width 100 — — s 35 * † RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS VDD  BVDD (D005) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS39016B-page 88 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series FIGURE 13-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 13-1 for load conditions. TABLE 13-6 Param No. TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Sym Characteristic 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse Width 42* Tt0P T0CKI Period 45* 46* 47* Tt1H Tt1L Tt1P Min No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler T1CKI High Time Synchronous, Prescaler = 1 Synchronous, PIC16C7X/CR72 Prescaler = PIC16LC7X/LCR72 2,4,8 Asynchronous PIC16C7X/CR72 PIC16LC7X/LCR72 T1CKI Low Time Synchronous, Prescaler = 1 Synchronous, PIC16C7X/CR72 Prescaler = PIC16LC7X/LCR72 2,4,8 Asynchronous PIC16C7X/CR72 PIC16LC7X/LCR72 T1CKI input Synchronous PIC16C7X/CR72 period PIC16LC7X/LCR72 48 * † Typ† Max Units Conditions 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 25 — — — — — — — — — — — — ns ns ns ns ns ns Must also meet parameter 42 — — — — — — ns ns ns Must also meet parameter 47 30 50 — — — — — — — — — — ns ns ns ns ns — — — — — — ns ns ns 0.5TCY + 20 15 25 30 50 Greater of: 30 OR TCY + 40 N Greater of: 50 OR TCY + 40 N 60 100 DC Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) Asynchronous PIC16C7X/CR72 — — ns PIC16LC7X/LCR72 — — ns Ft1 Timer1 oscillator input frequency range — 200 kHz (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc — These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 89 PIC16C72 Series FIGURE 13-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 13-1 for load conditions. TABLE 13-7 Param No. 50* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Sym TccL Characteristic CCP1 input low time Min No Prescaler With Prescaler PIC16C72/CR72 PIC16LC72/LCR72 51* TccH CCP1 input high time No Prescaler With Prescaler PIC16C72/CR72 PIC16LC72/LCR72 52* TccP CCP1 input period 53* TccR CCP1 output rise time 54* TccF CCP1 output fall time * † Typ† Max Units 0.5TCY + 20 — — ns 10 — — ns 20 — — ns 0.5TCY + 20 — — ns 10 — — ns 20 — — ns 3TCY + 40 N — — ns PIC16C72/CR72 — 10 25 ns PIC16LC72/LCR72 — 25 45 ns PIC16C72/CR72 — 10 25 ns PIC16LC72/LCR72 — 25 45 ns Conditions N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS39016B-page 90 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series FIGURE 13-8: SPI MASTER OPERATION TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSB SDO LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 13-1 for load conditions. FIGURE 13-9: SPI MASTER OPERATION TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSB BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure 13-1 for load conditions.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 91 PIC16C72 Series FIGURE 13-10: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSB SDO LSB BIT6 - - - - - -1 77 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure 13-1 for load conditions. FIGURE 13-11: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN 77 BIT6 - - - -1 LSB IN 74 Refer to Figure 13-1 for load conditions. DS39016B-page 92 Preliminary  1998-2013 Microchip Technology Inc. PIC16C72 Series TABLE 13-8 Param No. SPI SLAVE MODE REQUIREMENTS (CKE=0) - PIC16C72 Sym Characteristic Min Typ† Max Units TCY — — ns — — ns 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (slave mode) TCY + 20 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 50 — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 50 — — ns 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 13-9 Parameter No. * † Conditions SPI MODE REQUIREMENTS - PIC16CR72 Sym Characteristic Min Typ† Max Units TCY — — ns 70* TssL2scH, TssL2scL SS to SCK or SCK input 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns 74* TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — — ns 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 ns 81* TdoV2scH, TdoV2scL SDO data output setup to SCK edge TCY — — ns 82* TssL2doV SDO data output valid after SS edge — — 50 ns 83* TscH2ssH, TscL2ssH SS after SCK edge 1.5TCY + 40 — — ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 93 PIC16C72 Series FIGURE 13-12: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 13-1 for load conditions I2C BUS START/STOP BITS REQUIREMENTS TABLE 13-10 Parameter No. Sym 90 TSU:STA 91 THD:STA 92 TSU:STO 93 THD:STO DS39016B-page 94 Characteristic START condition Min 100 kHz mode 4700 Typ Max — — Setup time 400 kHz mode 600 — — START condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — STOP condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — STOP condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Preliminary Units Conditions ns Only relevant for repeated START condition ns After this period the first clock pulse is generated ns ns  1998-2013 Microchip Technology Inc. PIC16C72 Series FIGURE 13-13: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 13-1 for load conditions TABLE 13-11 Parameter No. 100 I2C BUS DATA REQUIREMENTS Sym THIGH Characteristic Clock high time Min Max Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns SSP Module 101 TLOW Clock low time SSP Module 102 103 90 91 106 107 92 109 110 TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF Cb Note 1: Note 2: SDA and SCL rise time SDA and SCL fall time 100 kHz mode Cb is specified to be from 10 to 400 pF — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 100 kHz mode 4.7 — s 400 kHz mode 0.6 — s Only relevant for repeated START condition START condition hold 100 kHz mode time 400 kHz mode 4.0 — s 0.6 — s START condition setup time Data input hold time Data input setup time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 100 kHz mode 250 — ns 400 kHz mode 100 — ns STOP condition setup 100 kHz mode time 400 kHz mode 4.7 — s 0.6 — s Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF Bus free time Bus capacitive loading After this period the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz)S I2C-bus system, but the requirement tsu;DAT  250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1998-2013 Microchip Technology Inc. Preliminary DS39016B-page 95 PIC16C72 Series TABLE 13-12 Param No. A/D CONVERTER CHARACTERISTICS: PIC16C72/CR72-04 (Commercial, Industrial, Extended) PIC16C72/CR72-10 (Commercial, Industrial, Extended) PIC16C72/CR72-20 (Commercial, Industrial, Extended) PIC16LC72/LCR72-04 (Commercial, Industrial) Sym Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 8 bits bit VREF = VDD = 5.12V, VSS  VAIN  VREF A02 EABS Total Absolute error — —