PIC16(L)F15354/55
Full-Featured 28-Pin Microcontrollers
Description
PIC16(L)F15354/55 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory
Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information
Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.
Core Features
Power-Saving Functionality
• C Compiler Optimized RISC Architecture
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Timers:
- 8-bit Timer2 with Hardware Limit Timer (HLT)
- 16-bit Timer0/1
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
• Programmable Code Protection
• DOZE mode: Ability to Run the CPU Core Slower
than the System Clock
• IDLE mode: Ability to halt CPU Core while Internal
Peripherals Continue Operating
• SLEEP mode: Lowest Power Consumption
• Peripheral Module Disable (PMD):
- Ability to disable hardware module to
minimize active power consumption of
unused peripherals
Memory
•
•
•
•
Up to 14 KB Flash Program Memory
Up to 1024 Bytes Data SRAM
Direct, Indirect and Relative Addressing modes
Memory Access Partition (MAP):
- Write protect
- Customizable Partition
• Device Information Area (DIA)
• Device Configuration Information (DCI)
• High-Endurance Flash (HEF)
- Last 128 words of Program Flash Memory
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF15354/55)
- 2.3V to 5.5V (PIC16F15354/55)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
2016-2018 Microchip Technology Inc.
eXtreme Low-Power (XLP) Features
•
•
•
•
Sleep mode: 50 nA @ 1.8V, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
- 8 A @ 32 kHz, 1.8V, typical
- 32 A/MHz @ 1.8V, typical
Digital Peripherals
• Four Configurable Logic Cells (CLC):
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Two Capture/Compare/PWM (CCP) module:
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• Four 10-Bit PWMs
• Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control and
increased frequency resolution
- Input Clock: 0 Hz < FNCO < 32 MHz
- Resolution: FNCO/220
• Two EUSART, RS-232, RS-485, LIN compatible
• Two SPI
• Two I2C, SMBus, PMBus™ compatible
DS40001853C-page 1
PIC16(L)F15354/55
Digital Peripherals (Cont.)
Flexible Oscillator Structure
• I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• High-Precision Internal Oscillator:
- Software selectable frequency range up to 32
MHz, ±1% typical
• x2/x4 PLL with Internal and External Sources
• Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
• External Oscillator Block with:
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 32 MHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if primary clock
stops
• Oscillator Start-up Timer (OST):
- Ensures stability of crystal oscillator
resources
Analog Peripherals
• Analog-to-Digital Converter (ADC):
- 10-bit with up to 43 external channels
- Operates in Sleep
• Two Comparators:
- FVR, DAC and external input pin available on
inverting and noninverting input
- Software selectable hysteresis
- Outputs available internally to other modules,
or externally through PPS
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
• Zero-Cross Detect module:
- AC high voltage zero-crossing detection for
simplifying TRIAC control
- Synchronized switching control and timing
2016-2018 Microchip Technology Inc.
DS40001853C-page 2
PIC16(L)F15354/55
5-bit DAC
Comparator
8-bit/ (with HLT) Timer
16-bit Timer
Window Watchdog Timer
CCP/10-bit PWM
CWG
NCO
CLC
Memory Access Partition
Device Information Area
Peripheral Pin Select
Peripheral Module Disable
Debug (1)
5
1
1
1
2
Y
2/4
1
1
4 Y Y
Y
Y 1/1
Y
Y
I
PIC16(L)F15323 (C)
2
3.5 224 256
12
11
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 1/1
Y
Y
I
PIC16(L)F15324 (D)
4
7
12
11
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15325 (B)
8
14 224 1024 12
11
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15344 (D)
4
7
18
17
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15345 (B)
8
14 224 1024 18
17
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/1
Y
Y
I
PIC16(L)F15354 (A)
4
7
25
24
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15355 (A)
8
14 224 1024 25
24
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15356 (E) 16
28 224 2048 25
24
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15375 (E)
8
14 224 1024 36
35
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15376 (E) 16
28 224 2048 36
35
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15385 (E)
8
14 224 1024 44
43
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
PIC16(L)F15386 (E) 16
28 224 2048 44
43
1
2
1
2
Y
2/4
1
1
4 Y Y
Y
Y 2/2
Y
Y
I
Note 1:
224 512
224 512
224 512
EUSART/ I2C-SPI
10-bit ADC
6
Zero-Cross Detect
Temperature Indicator
I/OPins
3.5 224 256
Data SRAM
(bytes)
2
Storage Area Flash (B)
PIC16(L)F15313 (C)
Device
Program Flash Memory (KB)
Program Flash Memory (KW)
PIC16(L)F153XX FAMILY TYPES
Data Sheet Index
TABLE 1:
I - Debugging integrated on chip.
Data Sheet Index:
A:
DS40001853
PIC16(L)F15354/5 Data Sheet, 28-Pin
B: DS40001865
PIC16(L)F15325/45 Data Sheet, 14/20-Pin
C: DS40001897
PIC16(L)F15313/23 Data Sheet, 8/14-Pin
D: DS40001889
PIC16(L)F15324/44 Data Sheet, 14/20-Pin
E:
PIC16(L)F15356/75/76/85/86 Data Sheet, 28/40/48-Pin
Note:
DS40001866
For other small form-factor package availability and marking information, visit www.microchip.com/
packaging or contact your local sales office.
2016-2018 Microchip Technology Inc.
DS40001853C-page 3
PIC16(L)F15354/55
TABLE 2:
PACKAGES
Device
PIC16(L)F15354
PIC16(L)F15355
SPDIP
SOIC
SSOP
UQFN (4x4)
UQFN (6x6)
2016-2018 Microchip Technology Inc.
DS40001853C-page 4
PIC16(L)F15354/55
PIN DIAGRAMS
28-PIN PDIP, SOIC, SSOP
Note 1:
2:
1
28
RB7/ICSPDAT
RA0
2
27
RB6/ICSPCLK
RA1
3
26
RB5
RA2
4
25
RB4
RA3
5
RB3
RA4
6
24
23
RA5
VSS
7
22
RB1
RB0
RA7
9
PIC16(L)F15354
PIC16(L)F15355
VPP/MCLR/RE3
8
21
RB2
20
VDD
19
VSS
RA6
10
RC0
11
18
RC7
RC1
12
17
RC6
RC2
13
16
RC5
RC3
14
15
RC4
See Table 3 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level.
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28
27
26
25
24
23
22
RA1
RA0
RE3/MCLR/VPP
28-PIN UQFN (4x4), UQFN (6x6)
1
2
3
4
5
6
7
PIC16(L)F15354
PIC16(L)F15355
Note 1:
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC1
RC2
RC3
RC4
RC5
RC6
RC0
8
9
10
11
12
13
14
RA2
RA3
RA4
RA5
VSS
RA7
RA6
See Table 3 for location of all peripheral functions.
2:
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
3:
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
2016-2018 Microchip Technology Inc.
DS40001853C-page 5
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
RA0
2
27
ANA0
―
C1IN0C2IN0-
―
―
―
―
―
―
―
―
―
CLCIN0(1)
―
IOCA0
Y
―
RA1
3
28
ANA1
―
C1IN1C2IN1-
―
―
―
―
―
―
―
―
―
CLCIN1(1)
―
IOCA1
Y
―
RA2
4
1
ANA2
—
C1IN0+
C2IN0+
―
DAC1OUT1
―
―
―
―
―
―
―
―
―
IOCA2
Y
―
RA3
5
2
ANA3
VREF+
C1IN1+
―
DAC1REF+
―
―
―
―
―
―
―
―
―
IOCA3
Y
―
RA4
6
3
ANA4
―
―
―
―
T0CKI
―
―
―
―
―
―
―
―
IOCA4
Y
―
RA5
7
4
ANA5
―
―
―
―
—
―
―
―
SS1(1)
―
―
―
―
IOCA5
Y
―
RA6
10
7
ANA6
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA6
Y
CLKOUT
OSC2
RA7
9
6
ANA7
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCA7
Y
CLKIN
OSC1
RB0
21
18
ANB0
―
C2IN1+
―
―
―
―
―
CWG1IN(1)
SS2(1)
ZCD1
―
―
―
INT(1)
IOCB0
Y
―
RB1
22
19
ANB1
―
C1IN3C2IN3-
―
―
―
―
―
―
SCK2,
SCL2(1,4)
―
―
―
―
IOCB1
Y
―
RB2
23
20
ANB2
―
―
―
―
―
―
―
―
SDA2,
SDI2(1,4)
―
―
―
―
IOCB2
Y
―
RB3
24
21
ANB3
―
C1IN2C2IN2-
―
―
―
―
―
―
―
―
―
―
―
IOCB3
Y
―
RB4
25
22
ANB4
ADACT(1)
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCB4
Y
―
―
T1G(1)
―
―
―
―
―
―
―
―
IOCB5
Y
―
(1)
CLCIN2
―
IOCB6
Y
ICSPCLK
CLCIN3(1)
―
IOCB7
Y
ICSPDAT
RB5
26
23
ANB5
―
―
―
DS40001853C-page 6
RB6
27
24
ANB6
―
―
―
―
―
―
―
―
―
―
TX2
CK2(1)
RB7
28
25
ANB7
―
―
―
DAC1OUT2
―
―
―
―
―
―
RX2
DT2(1)
Note
1:
2:
3:
4:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBus input buffer thresholds.
PIC16(L)F15354/55
28-Pin UQFN
28-PIN ALLOCATION TABLE (PIC16(L)F15354, PIC16(L)F15355)
28-Pin PDIP/SOIC/SSOP
TABLE 3:
I/O(2)
2016-2018 Microchip Technology Inc.
PIN ALLOCATION TABLES
28-Pin PDIP/SOIC/SSOP
28-Pin UQFN
ADC
Reference
Comparator
NCO
DAC
Timers
CCP
PWM
CWG
MSSP
ZCD
EUSART
CLC
CLKR
Interrupt
Pull-up
Basic
28-PIN ALLOCATION TABLE (PIC16(L)F15354, PIC16(L)F15355) (CONTINUED)
11
8
ANC0
―
―
―
―
SOSCO
T1CKI
―
―
―
―
―
―
―
―
IOCC0
Y
―
12
9
ANC1
―
―
―
―
SOSCI
CCP2(1)
―
―
―
―
―
―
―
IOCC1
Y
―
13
10
ANC2
―
―
―
―
―
CCP1(1)
―
―
―
―
―
―
―
IOCC2
Y
―
RC3
14
11
ANC3
―
―
―
―
T2IN(1)
―
―
―
SCL1,
SCK1(1,4)
―
―
―
―
IOCC3
Y
―
RC4
15
12
ANC4
―
―
―
―
―
―
―
―
SDA1,
SDI1(1,4)
―
―
―
―
IOCC4
Y
―
RC5
16
13
ANC5
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCC5
Y
―
―
―
IOCC6
Y
―
I/O(2)
2016-2018 Microchip Technology Inc.
TABLE 3:
RC0
RC1
RC2
17
14
ANC6
―
―
―
―
―
―
―
―
―
―
RC7
18
15
ANC7
―
―
―
―
―
―
―
―
―
―
RX1
DT1(1)
―
―
IOCC7
Y
―
RE3
1
26
—
―
―
―
―
―
―
―
―
―
―
―
―
―
IOCE3
Y
MCLR
VPP
VDD
20
17
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VDD
VSS
8
16
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
VSS
19
5
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
VSS
―
―
―
―
C1OUT
NCO1OUT
―
TMR0
CCP1
PWM3OUT
CWG1A
CWG2A
SDO1/2
―
DT(1,2)
CLC1OUT
CLKR
―
―
―
―
―
―
―
C2OUT
―
―
―
CCP2
PWM4OUT
CWG1B
CWG2B
SCK1/2
―
CK(1,2)
CLC2OUT
―
―
―
―
―
―
―
―
―
―
―
―
―
PWM5OUT
CWG1C
CWG2C
SCL1(3,4)
SCL2(3,4)
―
TX(1,2)
CLC3OUT
―
―
―
―
―
―
―
―
―
―
―
―
―
PWM6OUT
CWG1D
CWG2D
SDA1(3,4)
SDA2(3,4)
―
―
CLC4OUT
―
―
―
―
OUT(2)
Note
DS40001853C-page 7
1:
2:
3:
4:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or
SMBus input buffer thresholds.
PIC16(L)F15354/55
RC6
TX1
CK1(1)
PIC16(L)F15354/55
Table of Contents
1.0 Device Overview ........................................................................................................................................................................... 10
2.0 Guidelines for Getting Started with PIC16(L)F15354/55 Microcontrollers .................................................................................... 19
3.0 Enhanced Mid-Range CPU........................................................................................................................................................... 22
4.0 Memory Organization .................................................................................................................................................................... 24
5.0 Device Configuration ..................................................................................................................................................................... 75
6.0 Device Information Area ............................................................................................................................................................... 86
7.0 Device Configuration Information .................................................................................................................................................. 88
8.0 Resets ........................................................................................................................................................................................... 89
9.0 Oscillator Module (with Fail-Safe Clock Monitor) ........................................................................................................................ 100
10.0 Interrupts ................................................................................................................................................................................... 117
11.0 Power-Saving Operation Modes ............................................................................................................................................... 139
12.0 Windowed Watchdog Timer (WWDT) ....................................................................................................................................... 146
13.0 Nonvolatile Memory (NVM) Control .......................................................................................................................................... 154
14.0 /O Ports ..................................................................................................................................................................................... 172
15.0 Peripheral Pin Select (PPS) Module ......................................................................................................................................... 194
16.0 Peripheral Module Disable ........................................................................................................................................................ 203
17.0 Interrupt-On-Change ................................................................................................................................................................. 211
18.0 Fixed Voltage Reference (FVR) ................................................................................................................................................ 221
19.0 Temperature Indicator Module .................................................................................................................................................. 224
20.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 226
21.0 5-Bit Digital-to-Analog Converter (DAC1) Module ..................................................................................................................... 240
22.0 Numerically Controlled Oscillator (NCO) Module ...................................................................................................................... 245
23.0 Comparator Module .................................................................................................................................................................. 255
24.0 Zero-Cross Detection (ZCD) Module ........................................................................................................................................ 265
25.0 Timer0 Module .......................................................................................................................................................................... 271
26.0 Timer1 Module with Gate Control ............................................................................................................................................. 277
27.0 Timer2 Module With Hardware Limit Timer (HLT) .................................................................................................................... 291
28.0 Capture/Compare/PWM Modules ............................................................................................................................................. 312
29.0 Pulse-Width Modulation (PWM) ................................................................................................................................................ 323
30.0 Complementary Waveform Generator (CWG) Module ............................................................................................................. 330
31.0 Configurable Logic Cell (CLC) .................................................................................................................................................. 355
32.0 Master Synchronous Serial Port (MSSPx) Modules ................................................................................................................. 372
33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ................................................................ 423
34.0 Reference Clock Output Module ............................................................................................................................................... 451
35.0 n-Circuit Serial Programming™ (ICSP™) ................................................................................................................................. 455
36.0 Instruction Set Summary........................................................................................................................................................... 457
37.0 Electrical Specifications ............................................................................................................................................................ 470
38.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 499
39.0 Development Support ............................................................................................................................................................... 519
40.0 Packaging Information .............................................................................................................................................................. 523
2016-2018 Microchip Technology Inc.
DS40001853C-page 8
PIC16(L)F15354/55
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2016-2018 Microchip Technology Inc.
DS40001853C-page 9
PIC16(L)F15354/55
DEVICE OVERVIEW
The PIC16(L)F15354/55 are described within this data
sheet. The PIC16(L)F15354/55 devices are available in
28-pin SPDIP, SSOP, SOIC, and UQFN packages.
Figure 1-1 shows the block diagram of the
PIC16(L)F15354/55 devices. Table 1-2 shows the
pinout descriptions.
TABLE 1-1:
DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC16(L)F15354/55
1.0
Analog-to-Digital Converter
●
Digital-to-Analog Converter (DAC1)
●
Fixed Voltage Reference (FVR)
●
Numerically Controlled Oscillator (NCO1)
●
Temperature Indicator Module (TIM)
●
Zero-Cross Detect (ZCD1)
●
Reference Table 1-1 for peripherals available per device.
Capture/Compare/PWM Modules (CCP)
CCP1
●
CCP2
●
C1
●
C2
●
CLC1
●
CLC2
●
CLC3
●
CLC4
●
CWG1
●
EUSART1
●
EUSART2
●
MSSP1
●
MSSP2
●
PWM3
●
PWM4
●
PWM5
●
PWM6
●
Timer0
●
Timer1
●
Timer2
●
Comparator Module (Cx)
Configurable Logic Cell (CLC)
Complementary Waveform Generator (CWG)
Enhanced Universal Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
Master Synchronous Serial Ports (MSSP)
Pulse-Width Modulator (PWM)
Timers
2016-2017 Microchip Technology Inc.
DS40001853C-page 10
PIC16(L)F15354/55
1.1
1.1.1
Register and Bit Naming
Conventions
REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance, and control identifier.
The control registers section will show just one
instance of all the register names with an ‘x’ in the place
of the peripheral instance number. This naming
convention may also be applied to peripherals when
there is only one instance of that peripheral in the
device to maintain compatibility with other devices in
the family that contain more than one.
1.1.2
BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.1.2.1
Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an underscore
plus the name of the register in which the bit resides to
avoid naming contentions.
1.1.2.2
Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral thereby making every long bit
name unique. The long bit name for the COG1 enable
bit is the COG1 prefix, G1, appended with the enable
bit short name, EN, resulting in the unique bit name
G1EN.
Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
2016-2017 Microchip Technology Inc.
1.1.2.3
Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name MD2 and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW
ANDWF
MOVLW
IORWF
~(1