PIC16LF1704T-I/SL

PIC16(L)F1704/8 14/20-Pin 8-Bit Advanced Analog Flash Microcontrollers High-Performance RISC CPU Special Microcontroller Features • C Compiler Optimized Architecture • Only 49 Instructions • Up to 14 Kbytes Linear Program Memory Addressing • Operating Speed: - DC – 32 MHz - DC – 125 ns instruction cycle • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory • High-Endurance Flash Data Memory (HEF) - 128 bytes of nonvolatile data storage - 100k erase/write cycles • Operating Voltage Range: - 1.8V-3.6V (PIC16LF1704/8) - 2.3V-5.5V (PIC16F1704/8) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C • Power-on Reset (POR) • Low Power Brown-Out Reset (LPBOR) • Extended Watch-Dog Timer (WDT): - Programmable period from 1 ms to 256s • Programmable Code Protection • In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) via Two Pins • Enhanced Low-Voltage Programming (LVP) • Power-Saving Sleep mode Flexible Oscillator Structure • Up to 17 I/O Pins and one Input-only Pin: - High current sink/source for LED drivers - Individually programmable weak pull-ups - Interrupt-on-change pin option with edge selectable option • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated low-power 32 kHz oscillator driver • Timer2: - Up to three (TMR2/4/6) - 8-Bit Timer/Counter - 8-Bit Period Register - Prescaler and Postscaler • Capture, Compare, PWM (CCP) Module • Master Synchronous Serial Port (SSP) with SPI and I2C with: - 7-bit address masking - SMBus/PMBusTM compatibility • Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART): - RS-232, RS-485 and LIN compatible - Auto-Baud Detect - Auto-wake-up on Start • 16 MHz Internal Oscillator Block: - Accurate to ±1%, typical - Software selectable frequency range from 16 MHz to 250 kHz - PLL multiplier to 32 MHz • 31 kHz Low-Power Internal Oscillator • External Oscillator Block with: - Three crystal/resonator modes up to 20 MHz - Three external clock modes up to 20 MHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops • Two-Speed Oscillator Start-up • Oscillator Start-up Timer (OST) eXtreme Low-Power (XLP) Features • • • • Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 µA @ 32 kHz, 1.8V, typical - 32 µA/MHz @ 1.8V, typical  2013-2015 Microchip Technology Inc. Digital Peripheral Features DS40001715D-page 1 PIC16(L)F1704/8 Digital Peripheral Features (Continued) Analog Peripheral Features • Complementary Output Generator (COG): - Push-Pull, Full Bridge, and Steering modes - Dedicated Rise/Fall Input Triggers - Dedicated Deadtime Delay Counters - Dedicated Phase Delay Counters - Dedicated Blanking Delay Counters - Concurrent Auto-Shutdown Selection • Two Pulse Width Modulation (PWM) modules: - 10-bit Duty-Cycle Control • Three Configurable Logic Cell (CLC) modules: - Generate a selected function of up to four inputs - Combinational and State Logic - External or Internal input/output pins - Operation in Sleep • Peripheral Pin Select (PPS): - Digital outputs mapped to any GPIO pin - Digital inputs from any GPIO pin - CLC input multiplexing • Operational Amplifiers: - Up to two configurable op amps - Selectable internal and external channels - High/Low selectable Gain Bandwidth Product • Two High-Speed Comparators: - 60 ns response time - Low-power/High-power mode - Comparator outputs externally accessible - Software hysteresis enable • Analog-to-Digital Converter (ADC) module - 10-bit resolution, 12 channels - Auto conversion start capability - Conversion available during Sleep • 8-Bit Digital-to-Analog Converter (DAC): - Output available externally - Positive and negative reference selection - Internal connections to comparators, op amps, Fixed Voltage Reference (FVR) and ADC • Zero-Cross Detection Circuit: - Constant Voltage Output - Current Source/Sink - Interrupt on Edge Detect • Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels XLP Debug(1) PPS CLC MSSP (I2C/SPI) EUSART COG PWM CCP Timers (8/16-bit) Zero Cross Op Amp High-Speed/ Comparators 8-bit DAC 10-bit ADC (ch) I/O’s(2) High-Endurance Flash (bytes) Data SRAM (bytes) Device Program Memory Flash (words) Data Sheet Index PIC16(L)F170x Family Types PIC16(L)F1703 (3) 2048 256 128 12 8 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y PIC16(L)F1704 (1) 4096 512 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1705 (2) 8192 1024 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1707 (3) 2048 256 128 18 12 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y PIC16(L)F1708 (1) 4096 512 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1709 (2) 8192 1024 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y Note 1: 2: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header. One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001715 PIC16(L)F1704/8 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers. 2: DS40001729 PIC16(L)F1705/9 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers. 3: DS40001722 PIC16(L)F1703/7 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001715D-page 2  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 PIN DIAGRAMS VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 Note: 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 See Table 1 for the pin allocation table. 16-PIN QFN 16 15 14 13 VDD NC FIGURE 2: 1 2 3 4 5 6 7 PIC16(L)F1704 14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1704 NC VSS FIGURE 1: 1 12 RA0/ICSPDAT 2 11 RA1/ICSPCLK 3 PIC16(L)F1704 10 RA2 4 9 RC0 RC4 RC3 RC2 RC1 5 6 7 8 RA5 RA4 RA3/MCLR/VPP RC5 Note: See Table 1 for the pin allocation table.  2013-2015 Microchip Technology Inc. DS40001715D-page 3 PIC16(L)F1704/8 20-PIN PDIP, SOIC,SSOP VDD 1 RA5 2 RA4 3 VPP/MCLR/RA3 4 RC5 5 RC4 6 RC3 7 RC6 8 RC7 9 RB7 10 Note: 20 19 18 17 16 15 14 13 12 11 VSS ICSPDAT/RA0 ICSPCLK/RA1 RA2 RC0 RC1 RC2 RB4 RB5 RB6 See Table 2 for the pin allocation table. 20-PIN QFN 20 19 18 17 16 RA4 RA5 VDD VSS RA0/ICSPDAT FIGURE 4: PIC16(L)F1708 FIGURE 3: 1 15 RA1/ICSPCLK 2 14 RA2 3 PIC16(L)F1708 13 RC0 4 12 RC1 5 11 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 VPP/MCLR/RA3 RC5 RC4 RC3 RC6 Note: See Table 2 for the pin allocation table. DS40001715D-page 4  2013-2015 Microchip Technology Inc. Comparator Op Amp DAC Zero Cross Timers CCP PWM COG MSSP EUSART CLC Interrupt Pull-up 13 12 AN0 VREF- C1IN+ — DAC1OUT1 — — — — — — — — IOC Y ICSPDAT RA1 12 11 AN1 VREF+ C1IN0C2IN0- — — — — — — — — — — IOC Y ICSPCLK RA2 11 10 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1) IOC Y — RA3 4 3 — — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 2 AN3 — — — — — T1G(1) SOSCO — — — — — — IOC Y CLKOUT OSC2 RA5 2 1 — — — — — — T1CKI(1) SOSCI — — — — — CLCIN3(1) IOC Y CLKIN OSC1 RC0 10 9 AN4 — C2IN+ OPA1IN+ — — — — — — SCK(1) SCL(3) — — IOC Y — RC1 9 8 AN5 — C1IN1C2IN1- OPA1IN- — — — — — — SDI(1) SDA(3) — CLCIN2(1) IOC Y — RC2 8 7 AN6 — C1IN2C2IN2- OPA1OUT — — — — — — — — — IOC Y — RC3 7 6 AN7 — C1IN3C2IN3- OPA2OUT — — — CCP2(1) — — SS(1) — CLCIN0(1) IOC Y — RC4 6 5 — — — OPA2IN- — — — — — — — CK(1) CLCIN1(1) IOC Y — RC5 5 4 — — — OPA2IN+ — — — CCP1(1) — — — RX(1,3) — IOC Y — VDD 1 16 — — — — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — — — — VSS — — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — — — — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — — COGC SDO TX CLC3OUT — — — — — — — — — — — — — — COGD SCK — — — — — DS40001715D-page 5 Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1704/8 OUT(2) Basic ADC RA0 Reference QFN 14/16-PIN ALLOCATION TABLE (PIC16(L)F1704) PDIP/SOIC/SSOP TABLE 1: I/O(2)  2013-2015 Microchip Technology Inc. Pin Allocation Tables QFN ADC Comparator Op Amp DAC Zero Cross Timers CCP PWM COG MSSP EUSART CLC Interrupt Pull-up 19 16 AN0 VREF- C1IN+ — DAC1OUT1 — — — — — — — — IOC Y ICSPDAT RA1 18 15 AN1 VREF+ C1IN0C2IN0- — — — — — — — — — — IOC Y ICSPCLK RA2 17 14 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1) IOC Y — RA3 4 1 — — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 20 AN3 — — — — — T1G(1) SOSCO — — — — — — IOC Y CLKOUT OSC2 RA5 2 19 — — — — — — T1CKI SOSCI — — — — — CLCIN3(1) IOC Y CLKIN OSC1 RB4 13 10 AN10 — — OPA1IN- — — — — — — SDI(1) SDA(3) — — IOC Y — RB5 12 9 AN11 — — OPA1IN+ — — — — — — — RX(1,3) IOC Y — — — IOC Y — Basic PDIP/SOIC/ SSOP RA0 Reference I/O(2) 20-PIN ALLOCATION TABLE (PIC16(L)F1708)  2013-2015 Microchip Technology Inc. RB6 11 8 — — — — — — — — — — SCK(1) SCL(3) RB7 10 7 — — — — — — — — — — — CK(1) — IOC Y — RC0 16 13 AN4 — C2IN+ — — — — — — — — — — IOC Y — RC1 15 12 AN5 — C1IN1C2IN1- — — — — — — — — — CLCIN2(1) IOC Y — RC2 14 11 AN6 — C1IN2C2IN2- OPA1OUT — — — — — — — — — IOC Y — RC3 7 4 AN7 — C1IN3C2IN3- OPA2OUT — — — CCP2(1) — — — — CLCIN0(1) IOC Y — RC4 6 3 — — — — — — — — — — — — CLCIN1(1) IOC Y — RC5 5 2 — — — — — — — CCP1(1) — — — — — IOC Y — RC6 8 5 AN8 — — OPA2IN- — SS(1) — IOC Y — RC7 9 6 AN9 — — OPA2IN+ — — — — — — — — — IOC Y — VDD 1 18 — — — — — — — — — — — — — — — VDD VSS 20 17 — — — — — — — — — — — — — — — VSS — — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — — — — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — — COGC SDO TX CLC3OUT — — — — — — — — — — — — — — COGD SCK — — — — — OUT(2) Note 1: 2: 3: — — — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1704/8 DS40001715D-page 6 TABLE 2: PIC16(L)F1704/8 Table of Contents Device Overview ................................................................................................................................................................................... 9 Enhanced Mid-Range CPU ................................................................................................................................................................. 17 Memory Organization.......................................................................................................................................................................... 19 Device Configuration ........................................................................................................................................................................... 48 Resets ................................................................................................................................................................................................. 54 Oscillator Module (with Fail-Safe Clock Monitor) ................................................................................................................................ 62 Interrupts ............................................................................................................................................................................................. 80 Power-Down Mode (Sleep) ................................................................................................................................................................. 93 Watchdog Timer (WDT) ...................................................................................................................................................................... 97 Flash Program Memory Control ........................................................................................................................................................ 102 I/O Ports ............................................................................................................................................................................................ 118 Peripheral Pin Select (PPS) Module ................................................................................................................................................. 136 Interrupt-On-Change ......................................................................................................................................................................... 143 Fixed Voltage Reference (FVR) ....................................................................................................................................................... 149 Temperature Indicator Module .......................................................................................................................................................... 152 Comparator Module .......................................................................................................................................................................... 154 Pulse Width Modulation (PWM) ........................................................................................................................................................ 163 Complementary Output Generator (COG) Module ........................................................................................................................... 169 Configurable Logic Cell (CLC) .......................................................................................................................................................... 201 Analog-to-Digital Converter (ADC) Module ....................................................................................................................................... 217 Operational Amplifier (OPA) Modules ............................................................................................................................................... 231 8-Bit Digital-to-Analog Converter (DAC1) Module ............................................................................................................................. 234 Zero-Cross Detection (ZCD) Module ................................................................................................................................................ 238 Timer0 Module .................................................................................................................................................................................. 242 Timer1 Module with Gate Control ..................................................................................................................................................... 245 Timer2/4/6 Module ............................................................................................................................................................................ 256 Capture/Compare/PWM Modules ..................................................................................................................................................... 261 Master Synchronous Serial Port (MSSP) Module .............................................................................................................................. 268 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ........................................................................ 324 In-Circuit Serial Programming™ (ICSP™) ........................................................................................................................................ 355 Instruction Set Summary ................................................................................................................................................................... 357 Electrical Specifications .................................................................................................................................................................... 371 DC and AC Characteristics Graphs and Charts ................................................................................................................................ 403 Development Support ....................................................................................................................................................................... 425 Packaging Information ...................................................................................................................................................................... 429 Appendix A: Data Sheet Revision History......................................................................................................................................... 448 The Microchip Web Site .................................................................................................................................................................... 449 Customer Change Notification Service ............................................................................................................................................. 449 Customer Support ............................................................................................................................................................................. 449 Product Identification System ........................................................................................................................................................... 450  2013-2015 Microchip Technology Inc. DS40001715D-page 7 PIC16(L)F1704/8 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS40001715D-page 8  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 1.0 DEVICE OVERVIEW The PIC16(L)F1704/8 are described within this data sheet. They are available in 14-pin and 20-pin DIP packages and 16-pin and 20-pin QFN packages. Figure 1-1 shows a block diagram of the PIC16(L)F1704/8 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. Peripheral PIC16(L)F1708 DEVICE PERIPHERAL SUMMARY PIC16(L)F1704 TABLE 1-1: Analog-to-Digital Converter (ADC) ● ● Digital-to-Analog Converter (DAC) ● ● Complementary Output Generator (COG) ● ● Fixed Voltage Reference (FVR) ● ● Zero Cross Detection (ZCD) ● ● Temperature Indicator ● ● Capture/Compare/PWM (CCP/ECCP) Modules CCP1 ● ● CCP2 ● ● C1 ● ● C2 ● ● CLC1 ● ● CLC2 ● ● CLC3 ● ● Comparators Configurable Logic Cell (CLC) Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) EUSART ● ● MSSP ● ● Op Amp 1 ● ● Op Amp 2 ● ● PWM3 ● ● PWM4 ● ● Timer0 ● ● Timer1 ● ● Timer2 ● ● Master Synchronous Serial Ports Op Amp Pulse Width Modulator (PWM) Timers  2013-2015 Microchip Technology Inc. DS40001715D-page 9 PIC16(L)F1704/8 FIGURE 1-1: PIC16(L)F1704/8 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB(1) CLKOUT Timing Generation HFINTOSC/ LFINTOSC Oscillator CLKIN PORTC CPU Figure 1-1 MCLR ZCD Op Amps PWM Timer0 Timer1 Timer2 MSSP Comparators COG Temp. Indicator Note 1: 2: DS40001715D-page 10 ADC 10-Bit FVR DAC CCPs EUSART CLCs PIC16(L)F1708 only. See applicable chapters for more information on peripherals.  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 1-2: PIC16(L)F1704 PINOUT DESCRIPTION Name RA0/AN0/VREF-/C1IN+/ DAC1OUT/ICSPDAT RA1/AN1/VREF+/C1IN0-/C2IN0-/ ICSPCLK RA2/AN2/DAC1OUT2/ZCD/ T0CKI(1)/COGIN(1)/INT(1) RA3/MCLR/VPP RA4/AN3/T1G(1)/SOSCO/ OSC2/CLKOUT RA5/T1CKI(1)/SOSCI/ CLCIN3(1)/OSC1/CLKIN RC0/AN4/C2IN+/OPA1IN+/ SCK(1)/SCL(3) Function Input Type RA0 TTL/ST AN0 AN Output Type Description CMOS General purpose I/O. — ADC Channel 0 input. VREF- AN — ADC Negative Voltage Reference input. C1IN+ AN — Comparator C1 positive input. AN Digital-to-Analog Converter output. DAC1OUT — ICSPDAT ST RA1 TTL/ST AN1 AN — ADC Channel 1 input. VREF+ AN — ADC Voltage Reference input. C1IN0- AN — Comparator C2 negative input. CMOS ICSP™ Data I/O. CMOS General purpose I/O. C2IN0- AN — Comparator C3 negative input. ICSPCLK ST — Serial Programming Clock. RA2 TTL/ST AN2 AN — ADC Channel 2 input. DAC1OUT2 — AN Digital-to-Analog Converter output. ZCD — AN Zero Cross Detection Current Source/Sink. T0CKI TTL/ST — Timer0 clock input. COGIN TTL/ST — Complementary Output Generator input. INT TTL/ST — External interrupt. RA3 TTL/ST CMOS General purpose I/O. CMOS General purpose input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4 TTL/ST AN3 AN — T1G TTL/ST — SOSCO XTAL XTAL Secondary Oscillator Connection. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. CMOS General purpose I/O. RA5 TTL/ST T1CKI TTL/ST — SOSCI XTAL XTAL CLCIN3 TTL/ST — ADC Channel 3 input. Timer1 gate input. CMOS General purpose I/O. Timer1 clock input. Secondary Oscillator Connection. Configurable Logic Cell source input. OSC1 — XTAL CLKIN TTL/ST — External clock input (EC mode). Crystal/Resonator (LP, XT, HS modes). RC0 TTL/ST — General purpose I/O. AN4 AN — ADC Channel 4 input. C2IN+ AN — Comparator positive input. OPA1IN+ AN — Operational Amplifier 1 non-inverting input. SCK TTL/ST — SPI clock. SCL I2C — I2C clock. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2013-2015 Microchip Technology Inc. DS40001715D-page 11 PIC16(L)F1704/8 TABLE 1-2: PIC16(L)F1704 PINOUT DESCRIPTION (CONTINUED) Name RC1/AN5/C1IN1-/C2IN1-/ OPA1IN-/SDI(1)/SDA(3)/ CLCIN2(1) RC2/AN6/C1IN2-/C2IN2-/ OPA1OUT RC3/AN7/C1IN3-/C2IN3-/ OPA2OUT/CCP2(1)/SS(1)/ CLCIN0(1) RC4/OPA2IN-/CK(1)/CLCIN1(1) (1) RC5/OPA2IN+/CCP1 /RX (1) Function Input Type RC1 TTL/ST Output Type Description CMOS General purpose I/O. AN5 AN — ADC Channel 5 input. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. OPA1IN- AN — Operational Amplifier 1 inverting input. SDI CMOS — SPI data input. SDA I2C — I2C data input. CLCIN2 TTL/ST — Configurable Logic Cell source input. RC2 TTL/ST CMOS General purpose I/O. AN6 AN — ADC Channel 6 input. C1IN2- AN — Comparator C1 negative input. C2IN2- AN — Comparator C2 negative input. OPA1OUT — AN Operational Amplifier 1 output. RC3 TTL/ST AN7 AN — ADC Channel 7 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. AN Operational Amplifier 2 output. OPA2OUT — CCP2 TTL/ST CMOS General purpose I/O. CMOS Capture/Compare/PWM2. SS TTL/ST — Slave Select input. CLCIN0 TTLST — Configurable Logic Cell source input. RC4 TTL/ST OPA2IN- AN CK TTL/ST CLCIN1 TTL/ST CMOS General purpose I/O. — Operational Amplifier 2 inverting input. CMOS USART synchronous clock. — Configurable Logic Cell source input. RC5 TTL/ST OPA2IN+ AN CMOS General purpose I/O. CCP1 TTL/ST RX TTL/ST VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. — Operational Amplifier 2 non-inverting input. CMOS Capture/Compare/PWM1. — USART asynchronous input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001715D-page 12  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 1-2: PIC16(L)F1704 PINOUT DESCRIPTION (CONTINUED) Name OUT(2) Function Input Type Output Type C1OUT — CMOS Comparator output. C2OUT — CMOS Comparator output. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. PWM3OUT — CMOS PWM3 output. Description PWM4OUT — CMOS PWM4 output. COGA — CMOS Complementary Output Generator Output A. COGB — CMOS Complementary Output Generator Output B. COGC — CMOS Complementary Output Generator Output C. COGD — CMOS Complementary Output Generator Output D. SDA(3) — OD I2C data input/output. SDO — CMOS SPI data output. SCK — CMOS SPI clock output. SCL(3) — OD I2C clock output. TX/CK — CMOS USART asynchronous TX data/synchronous clock output. DT — CMOS USART synchronous data output. CLC1OUT — CMOS Configurable Logic Cell 1 source output. CLC2OUT — CMOS Configurable Logic Cell 2 source output. CLC3OUT — CMOS Configurable Logic Cell 3 source output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2013-2015 Microchip Technology Inc. DS40001715D-page 13 PIC16(L)F1704/8 TABLE 1-3: PIC16(L)F1708 PIN OUT DESCRIPTION Name RA0/AN0/VREF-/C1IN+/ DAC1OUT/ICSPDAT RA1/AN1/VREF+/C1IN0-/C2IN0-/ ICSPCLK RA2/AN2/DAC1OUT2/ZCD/ T0CKI(1)/COGIN(1)/INT(1) Function RA0 AN0 RA4/AN3/T1G(1)/SOSCO/ OSC2/CLKOUT RA5/T1CKI/SOSCI/ CLCIN3(1)/OSC1/CLKIN RB4/AN10/OPA1IN-/SCK(1)/ SDA(3) Output Type Description TTL/ST CMOS General purpose I/O. AN — ADC Channel 0 input. VREF- AN — ADC Negative Voltage Reference input. C1IN+ AN — Comparator C1 positive input. AN Digital-to-Analog Converter output. DAC1OUT — ICSPDAT ST RA1 CMOS ICSP™ Data I/O. TTL/ST CMOS General purpose I/O. AN1 AN — ADC Channel 1 input. VREF+ AN — ADC Voltage Reference input. C1IN0- AN — Comparator C2 negative input. C2IN0- AN — Comparator C3 negative input. ICSPCLK ST — Serial Programming Clock. RA2 AN2 TTL/ST CMOS General purpose I/O. AN — ADC Channel 2 input. Digital-to-Analog Converter output. DAC1OUT2 — AN ZCD — AN Zero-Cross Detection Current Source/Sink. T0CKI ST — Timer0 clock input. COGIN ST INT RA3/MCLR/VPP Input Type RA3 ST CMOS Complementary Output Generator input. — External interrupt. TTL/ST CMOS General purpose I/O. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4 TTL/ST CMOS General purpose I/O. AN3 AN — ADC Channel 3 input. T1G ST — Timer1 gate input. SOSCO XTAL XTAL Secondary Oscillator Connection. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — RA5 CMOS FOSC/4 output. TTL/ST CMOS General purpose I/O. T1CKI ST — SOSCI XTAL XTAL CLCIN3 ST — OSC1 — XTAL CLKIN ST — RB4 Timer1 clock input. Secondary Oscillator Connection. Configurable Logic Cell source input. Crystal/Resonator (LP, XT, HS modes). External clock input (EC mode). TTL/ST CMOS General purpose I/O. AN10 AN — ADC Channel 10 input. OPA1IN- AN — Operational Amplifier 1 inverting input. SCK ST SDA 2 I C CMOS SPI clock. OD I2C data input/output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001715D-page 14  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 1-3: PIC16(L)F1708 PIN OUT DESCRIPTION (CONTINUED) Name RB5/AN11/OPA1IN+/RX(1) Function RB5 RB7/CK(1) RC2/AN6/C1IN2-/C2IN2-/ OPA1OUT — ADC Channel 11 input. AN — Operational Amplifier 1 non-inverting input. ST — USART asynchronous input. RB6 TTL/ST CMOS General purpose I/O. SDI CMOS — SPI data input. SCL I2C OD I2C clock. RC0 RC4/CLCIN1 (1) RC7/AN9/OPA2IN+ VDD CMOS USART synchronous clock. TTL/ST CMOS General purpose I/O. AN — ADC Channel 4 input. AN — Comparator positive input. RC1 TTL/ST CMOS General purpose I/O. AN5 AN — ADC Channel 5 input. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. CLCIN2 ST — Configurable Logic Cell source input. RC2 TTL/ST CMOS General purpose I/O. AN6 AN — ADC Channel 6 input. C1IN2- AN — Comparator C1 negative input. C2IN2- AN — Comparator C2 negative input. — AN Operational Amplifier 1 output. RC3 TTL/ST CMOS General purpose I/O. AN7 AN — ADC Channel 7 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. OPA2OUT — AN Operational Amplifier 2 output. CCP2 ST CLCIN0 ST RC4 RC5 CCP1 RC6/AN8/OPA2IN-/SS(1) ST C2IN+ CLCIN1 RC5/CCP1(1) TTL/ST CMOS General purpose I/O. AN4 OPA1OUT RC3/AN7/C1IN3-/C2IN3-/ OPA2OUT/CCP2(1)/CLCIN0(1) TTL/ST CMOS General purpose I/O. AN CK RC1/AN5/C1IN1-/C2IN1-/ CLCIN2(1) Description AN11 RB7 RC0/AN4/C2IN+ Output Type OPA1IN+ RX RB6/SDI(1)/SCL(3) Input Type RC6 CMOS Capture/Compare/PWM2. — Configurable Logic Cell source input. TTL/ST CMOS General purpose I/O. ST — Configurable Logic Cell source input. TTL/ST CMOS General purpose I/O. ST CMOS Capture/Compare/PWM1. TTL/ST CMOS General purpose I/O. AN8 AN — OPA2IN- AN — Operational Amplifier 2 inverting input. SS ST — Slave Select input. RC7 ADC Channel 8 input. TTL/ST CMOS General purpose I/O. AN9 AN — OPA2IN+ AN — ADC Channel 9 input. Operational Amplifier 2 non-inverting input. VDD Power — Positive supply. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections.  2013-2015 Microchip Technology Inc. DS40001715D-page 15 PIC16(L)F1704/8 TABLE 1-3: PIC16(L)F1708 PIN OUT DESCRIPTION (CONTINUED) Name VSS OUT (2) Function Input Type Output Type VSS Power — C1OUT — CMOS Comparator output. C2OUT — CMOS Comparator output. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. PWM3OUT — CMOS PWM3 output. PWM4OUT — CMOS PWM4 output. COGA — CMOS Complementary Output Generator Output A. COGB — CMOS Complementary Output Generator Output B. COGC — CMOS Complementary Output Generator Output C. COGD — CMOS Complementary Output Generator Output D. SDA(3) — SDO — CMOS SPI data output. SCK — CMOS SPI clock output. SCL(3) I2C OD OD Description Ground reference. I2C data input/output. I2C clock output. TX/CK — CMOS USART asynchronous TX data/synchronous clock output. DT — CMOS USART synchronous data output. CLC1OUT — CMOS Configurable Logic Cell 1 source output. CLC2OUT — CMOS Configurable Logic Cell 2 source output. CLC3OUT — CMOS Configurable Logic Cell 3 source output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001715D-page 16  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 2.0 Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and FIGURE 2-1: • • • • Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Direct Addr 7 5 Indirect Addr 12 12 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W reg Internal Oscillator Block VDD  2013-2015 Microchip Technology Inc. VSS DS40001715D-page 17 PIC16(L)F1704/8 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving” for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See Section 3.6 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.7 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 31.0 “Instruction Set Summary” for more details. DS40001715D-page 18  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1704/8 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1). Note 1: The method to access Flash memory through the PMCON registers is described in Section 10.0 “Flash Program Memory Control”. The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address High-Endurance Flash Memory Address Range(1) 4,096 0FFFh 0F80h - 0FFFh PIC16(L)F1704/8 Note 1: High-endurance Flash applies to the low byte of each address in the range.  2013-2015 Microchip Technology Inc. DS40001715D-page 19 PIC16(L)F1704/8 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1704/8 PC CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. Stack Level 15 EXAMPLE 3-1: Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 On-chip Program Memory 3.1.1 07FFh 0800h Page 1 Rollover to Page 0 0FFFh 1000h constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.1.1.2 Rollover to Page 1 7FFFh Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The high directive will set bit if a label points to a location in program memory. DS40001715D-page 20  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants DW DATA0 ;First constant DW DATA1 ;Second constant DW DATA2 DW DATA3 my_function ;… LOTS OF CODE… MOVLW DATA_INDEX ADDLW LOW constants MOVWF FSR1L MOVLW HIGH constants;MSb sets automatically MOVWF FSR1H BTFSC STATUS, C ;carry from ADDLW? INCF FSR1H, f ;yes MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.2 High-Endurance Flash This device has a 128-byte section of high-endurance Program Flash Memory (PFM) in lieu of data EEPROM. This area is especially well suited for nonvolatile data storage that is expected to be updated frequently over the life of the end product. See Section 10.2 “Flash Program Memory Overview” for more information on writing data to PFM. See Section 3.1.1.2 “Indirect Read with FSR” for more information about using the FSR registers to read byte data stored in PFM.  2013-2015 Microchip Technology Inc. DS40001715D-page 21 PIC16(L)F1704/8 3.3 Data Memory Organization 3.3.1.1 STATUS Register The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): The STATUS register, shown in Register 3-1, contains: • • • • The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.7 “Indirect Addressing” for more information. Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. 3.3.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed information, see Table 3-9. TABLE 3-2: • the arithmetic status of the ALU • the Reset status For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 31.0 “Instruction Set Summary”). Note: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON DS40001715D-page 22  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 3.4 Register Definitions: Status REGISTER 3-1: U-0 STATUS: STATUS REGISTER U-0 — U-0 — R-1/q — TO R-1/q PD R/W-0/u Z R/W-0/u (1) DC R/W-0/u C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.  2013-2015 Microchip Technology Inc. DS40001715D-page 23 PIC16(L)F1704/8 3.4.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.4.2 FIGURE 3-2: 7-bit Bank Offset 0Bh 0Ch GENERAL PURPOSE RAM Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.7.2 “Linear Data Memory” for more information. 3.4.3 Memory Region 00h There are up to 80 bytes of GPR in each data memory bank. The General Purpose RAM occupies the 80 bytes after the SFR registers of selected data memory banks. 3.4.2.1 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.4.4 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Tables 3-3 through 3-8. DS40001715D-page 24  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. TABLE 3-3: PIC16(L)F1704 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) BANK 4 200h Core Registers (Table 3-2) BANK 5 280h Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h PORTA — PORTC — — PIR1 PIR2 PIR3 — TMR0 TMR1L 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h TRISA — TRISC — — PIE1 PIE2 PIE3 — OPTION_REG PCON 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h LATA — LATC — — CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA — ANSELC — — PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA — WPUC — — SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA — ODCONC — — CCPR1L CCPR1H CCP1CON — — — 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA — SLRCONC — — — — — — — — 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA — INLVLC — — IOCAP IOCAN IOCAF — — — 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh TMR1H T1CON T1GCON TMR2 PR2 T2CON — — 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh FVRCON DAC1CON0 DAC1CON1 — — ZCD1CON — — 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) — RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 — — — — — — — 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR2L CCPR2H CCP2CON — — — CCPTMRS 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — — — — — — — — 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF — — — — — 01Fh 020h — 09Fh 0A0h ADCON2 11Fh 120h — 19Fh 1A0h BAUD1CON 21Fh 220h — 29Fh 2A0h — 06Fh 070h General Purpose Register 80 Bytes 0EFh 0F0h Common RAM 70h – 7Fh 07Fh 16Fh 170h Accesses 70h – 7Fh 0FFh Legend: DS40001715D-page 25 Note 1: General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h – 7Fh 17Fh = Unimplemented data memory locations, read as ‘0’. Unimplemented on PIC16LF1704. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh General Purpose Register 80 Bytes 27Fh 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh Unimplemented Read as ‘0’ Accesses 70h – 7Fh 2FFh Unimplemented Read as ‘0’ 3EFh 3F0h Accesses 70h – 7Fh 37Fh — Accesses 70h – 7Fh 3FFh PIC16(L)F1704/8 General Purpose Register 80 Bytes 31Fh — 39Fh 320h General Purpose 3A0h Register 32Fh 16 Bytes 330h PIC16(L)1708 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) BANK 4 200h Core Registers (Table 3-2) BANK 5 280h Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h PORTA PORTB PORTC — — PIR1 PIR2 PIR3 — TMR0 TMR1L 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h TRISA TRISB TRISC — — PIE1 PIE2 PIE3 — OPTION_REG PCON 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h LATA LATB LATC — — CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA ANSELB ANSELC — — PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA WPUB WPUC — — SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA ODCONB ODCONC — — CCPR1L CCPR1H CCP1CON — — — 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA SLRCONB SLRCONC — — — — — — — — 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA INLVLB INLVLC — — IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh TMR1H T1CON T1GCON TMR2 PR2 T2CON — — 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh FVRCON DAC1CON0 DAC1CON1 — — ZCD1CON — — 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) — RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 — — — — — — — 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR2L CCPR2H CCP2CON — — — CCPTMRS 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — — — — — — — — 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF — — — — — 01Fh 020h — 09Fh 0A0h ADCON2 11Fh 120h — 19Fh 1A0h BAUD1CON 21Fh 220h — 29Fh 2A0h — General Purpose Register 80 Bytes  2013-2015 Microchip Technology Inc. 06Fh 070h General Purpose Register 80 Bytes 0EFh 0F0h Common RAM 70h – 7Fh 07Fh 16Fh 170h Accesses 70h – 7Fh 0FFh Legend: Note 1: General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h – 7Fh 17Fh = Unimplemented data memory locations, read as ‘0’. Unimplemented on PIC16LF1708. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh General Purpose Register 80 Bytes 27Fh Unimplemented Read as ‘0’ 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh 31Fh — 39Fh 320h General Purpose 3A0h Register 32Fh 16 Bytes 330h Accesses 70h – 7Fh 2FFh Unimplemented Read as ‘0’ 3EFh 3F0h Accesses 70h – 7Fh 37Fh — Accesses 70h – 7Fh 3FFh PIC16(L)F1704/8 DS40001715D-page 26 TABLE 3-4:  2013-2015 Microchip Technology Inc. TABLE 3-5: PIC16(L)F1704/8 MEMORY MAP, BANK 8-23 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h — — — — — — — — — TMR4 PR4 T4CON — — — — TMR6 PR6 T6CON — Core Registers (Table 3-2) 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h Unimplemented Read as ‘0’ 46Fh 470h — — — — — — — — — — — — — — — — — — — — DS40001715D-page 27 Unimplemented Read as ‘0’ 86Fh 870h Unimplemented Read as ‘0’ 8EFh 8F0h Accesses 70h – 7Fh 87Fh Legend: Unimplemented Read as ‘0’ 8FFh 9EFh 9F0h 96Fh 970h Accesses 70h – 7Fh Unimplemented Read as ‘0’ Accesses 70h – 7Fh 97Fh = Unimplemented data memory locations, read as ‘0’. Unimplemented Read as ‘0’ Accesses 70h – 7Fh 9FFh Core Registers (Table 3-2) B8Bh B8Ch Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ BEFh BF0h B6Fh B70h Accesses 70h – 7Fh AFFh BANK 23 B80h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh A7Fh BANK 22 B0Bh B0Ch AEFh AF0h A6Fh A70h Accesses 70h – 7Fh 7FFh B00h Core Registers (Table 3-2) Accesses 70h – 7Fh B7Fh — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ Accesses 70h – 7Fh BANK 21 A8Bh A8Ch 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7EFh 7F0h 77Fh A80h Core Registers (Table 3-2) — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh BANK 20 A0Bh A0Ch 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h 76Fh 770h 6FFh A00h Core Registers (Table 3-2) — — — — — COG1PHR COG1PHF COG1BLKR COG1BLKF COG1DBR COG1DBF COG1CON0 COG1CON1 COG1RIS COG1RSIM COG1FIS COG1FSIM COG1ASD0 COG1ASD1 COG1STR BANK 15 780h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh BANK 19 98Bh 98Ch 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h 6EFh 6F0h 67Fh 980h Core Registers (Table 3-2) — — — — — — — — — — — PWM3DCL PWM3DCH PWM3CON PWM4DCL PWM4DCH PWM4CON — — — BANK 14 700h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh BANK 18 90Bh 90Ch 88Bh 88Ch 80Bh 80Ch 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h 66Fh 670h 5FFh 900h Core Registers (Table 3-2) — — — — — — — — — — — — — — — — — — — — BANK 13 680h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh BANK 17 Core Registers (Table 3-2) 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h 5EFh 5F0h 57Fh 880h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh BANK 16 — — — — — OPA1CON — — — OPA2CON — — — — — — — — — — 56Fh 570h 4FFh 800h 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h BANK 12 600h Accesses 70h – 7Fh BFFh PIC16(L)F1704/8 Accesses 70h – 7Fh BANK 11 580h Core Registers (Table 3-2) Unimplemented Read as ‘0’ 4EFh 4F0h 47Fh BANK 10 500h PIC16(L)F1704/8 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as ‘0’ C6Fh C70h  2013-2015 Microchip Technology Inc. Legend: — — — — — — — — — — — — — — — — — — — — CEFh CF0h D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h — — — — — — — — — — — — — — — — — — — — D6Fh D70h D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh = Unimplemented data memory locations, read as ‘0’. BANK 29 E80h Core Registers (Table 3-2) BANK 30 F00h Core Registers (Table 3-2) BANK 31 F80h Core Registers (Table 3-2) Core Registers (Table 3-2) E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h See Table 3-7 for E18h register mapping E19h details E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h See Table 3-7 for E98h register mapping E99h details E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h See Table 3-7 for F18h register mapping F19h details F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-8 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h E6Fh E70h EEFh EF0h F6Fh F70h FEFh FF0h Unimplemented Read as ‘0’ DEFh DF0h D7Fh BANK 28 E00h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh CFFh BANK 27 D80h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh CFFh BANK 26 D00h Accesses 70h – 7Fh DFFh Accesses 70h – 7Fh E7Fh Accesses 70h – 7Fh EFFh Accesses 70h – 7Fh F7Fh Accesses 70h – 7Fh FFFh PIC16(L)F1704/8 DS40001715D-page 28 TABLE 3-6: PIC16(L)F1704/8 TABLE 3-7: PIC16(L)F1704/8 MEMORY MAP, BANK 28-30 Bank 28 E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E21h E22h E23h E24h E25h E26h E27h E28h E29h E2Ah E2Bh E2Ch E2Dh E2Eh E2Fh E30h E31h E32h E33h E34h E35h E36h E37h E38h E39h E3Ah E3Bh E3Ch E3Dh E3Eh E3Fh E40h — — — PPSLOCK INTPPS T0CKIPPS T1CKIPPS T1GPPS CCP1PPS CCP2PPS — COGINPPS — — — — — — — — SSPCLKPPS SSPDATPPS SSPSSPPS — RXPPS CKPPS — — CLCIN0PPS CLCIN1PPS CLCIN2PPS CLCIN3PPS — — — — — — — — — — — — — — — — — — — — Bank 29 E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h EA1h EA2h EA3h EA4h EA5h EA6h EA7h EA8h EA9h EAAh EABh EACh EADh EAEh EAFh EB0h EB1h EB2h EB3h EB4h EB5h EB6h EB7h EB8h EB9h EBAh EBBh EBCh EBDh EBEh EBFh EC0h — E6Fh Legend: Note 1: — — — — RA0PPS RA1PPS RA2PPS — RA4PPS RA5PPS — — — — — — RB4PPS(1) RB5PPS(1) RB6PPS(1) RB7PPS(1) RC0PPS RC1PPS RC2PPS RC3PPS RC4PPS RC5PPS RC6PPS(1) RC7PPS(1) — — — — — — — — — — — — — — — — — — — — — — — — Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F31h F32h F33h F34h F35h F36h F37h F38h F39h F3Ah F3Bh F3Ch F3Dh F3Eh F3Fh F40h — — EEFh — — — CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1SEL2 CLC1SEL3 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2SEL2 CLC2SEL3 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3SEL2 CLC3SEL3 CLC3GLS0 CLC3GLS1 CLC3GLS2 CLC3GLS3 — — — — — — — — — — — — — — — — — — F6Fh = Unimplemented data memory locations, read as ‘0’, Only available on PIC16(L)F1708 devices  2013-2015 Microchip Technology Inc. DS40001715D-page 29 PIC16(L)F1704/8 TABLE 3-8: PIC16(L)F1704/8 MEMORY MAP, BANK 31 Bank 31 F8Ch FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Unimplemented Read as ‘0’ STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’, DS40001715D-page 30  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 3.4.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-9 can be addressed from any Bank. TABLE 3-9: Addr Name CORE FUNCTION REGISTERS SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 ---1 1000 ---q quuu x03h or STATUS x83h — — — TO PD Z DC C x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 0000 0000 0000 x08h or BSR x88h — x09h or WREG x89h — x0Bh or INTCON x8Bh GIE Note 1: — BSR4 BSR3 BSR2 BSR1 BSR0 Working Register x0Ah or PCLATH x8Ah Legend: — Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank.  2013-2015 Microchip Technology Inc. DS40001715D-page 31 PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --uu uuuu Bank 0 — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- RC7(3) RC6(3) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu — 00Ch PORTA 00Dh PORTB(3) 00Eh PORTC 00Fh — Unimplemented — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0-00 0000 0-00 012h PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 000- 00-- 000- 00-- 013h PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF --00 -000 --00 -000 014h — Unimplemented 015h TMR0 016h 017h 018h T1CON 019h T1GCON — — Timer0 Module Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu TMR1CS TMR1GE T1GPOL T1CKPS T1GTM T1GSPM T1OSCEN T1SYNC T1GGO/ DONE T1GVAL — TMR1ON T1GSS 01Ah TMR2 Holding Register for the 8-bit TMR2 Register xxxx xxxx uuuu uuuu 01Bh PR2 Timer2 Period Register xxxx xxxx uuuu uuuu -000 0000 -000 0000 — — 01Ch T2CON 01Dh to — 01Fh — T2OUTPS TMR2ON T2CKPS Unimplemented Bank 1 — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- 08Eh TRISC TRISC7(3) TRISC6(3) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 — 08Ch TRISA (3) 08Fh — Unimplemented — 090h — Unimplemented — — 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 000- 0000 000- 0000 093h PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE --00 -000 --00 -000 094h — 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE 096h PCON STKOVF STKUNF — RWDT 097h WDTCON — — 098h OSCTUNE — — 099h OSCCON SPLLEN Unimplemented 09Ah OSCSTAT SOSCR PSA — 1111 1111 1111 1111 BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 PS RMCLR RI POR WDTPS TUN IRCF PLLR — OSTS HFIOFR — HFIOFL MFIOFR SCS LFIOFR HFIOFS --00 0000 --00 0000 0011 1-00 0011 1-00 00q0 --00 qqqq --0q 09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0 — 09Eh ADCON1 ADFM 09Fh ADCON2 Legend: Note 1: 2: 3: 4: CHS ADCS TRIGSEL GO/DONE — ADNREF — — ADON ADPREF — — -000 0000 -000 0000 0000 -000 0000 -000 0000 ---- 0000 ---- x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8. DS40001715D-page 32  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA 10Dh LATB(3) 10Eh LATC — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ---- LATC7(3) LATC6(3) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu — 10Fh — Unimplemented — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT 00-0 0100 00-0 0100 112h CM1CON1 C1INTP C1INTN 0000 0000 0000 0000 113h CM2CON0 C2ON C2OUT 00-0 0100 00-0 0100 114h CM2CON1 C2INTP C2INTN 0000 0000 0000 0000 115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00 116h BORCON SBOREN BORFS — — — — — BORRDY 1x-- ---q uu-- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR 118h DAC1CON0 DAC1EN --- DAC1OE1 DAC1OE2 DAC1PSS 119h DAC1CON1 11Ah — Unimplemented 11Bh — Unimplemented — — 0-00 --00 0-00 --00 11Ch ZCD1CON — C1POL C1ZLF C1SP C2ZLF C2SP C1PCH — C2POL C1HYS C1SYNC C1NCH C2PCH C2HYS C2SYNC C2NCH ADFVR --- DAC1NSS DAC1R ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 0q00 0000 0q00 0000 0-00 00-0 0-00 00-0 0000 0000 0000 0000 — — 11Dh — Unimplemented — — 11Eh — Unimplemented — — 11Fh — Unimplemented — — Bank 3 18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 1111 ---1 1111 18Dh ANSELB(3) — — ANSB5 ANSB4 — — — — --11 ---- --11 ---- ANSC7(3) ANSC6(3) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 18Eh ANSELC 1111 1111 1111 1111 18Fh — Unimplemented — — 190h — Unimplemented — — 191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000 192h PMADRH 1000 0000 1000 0000 193h PMDATL 194h PMDATH 195h PMCON1 196h PMCON2 197h VREGCON(4) —(1) Program Memory Address Register High Byte Program Memory Read Data Register Low Byte — — — CFGS Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD Program Memory Control Register 2 — — — 198h — Unimplemented 199h RC1REG USART Receive Data Register 19Ah TX1REG USART Transmit Data Register — — — VREGPM Reserved xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu -000 x000 -000 q000 0000 0000 0000 0000 ---- --01 ---- --01 — — 0000 0000 0000 0000 0000 0000 0000 0000 19Bh SP1BRGL BRG 0000 0000 0000 0000 19Ch SP1BRGH BRG 0000 0000 0000 0000 0000 0000 19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 19Fh BAUD1CON Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8.  2013-2015 Microchip Technology Inc. DS40001715D-page 33 PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --11 1111 Bank 4 20Ch WPUA 20Dh WPUB(3) 20Eh WPUC — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ---- WPUC7(3) WPUC6(3) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 — 20Fh — Unimplemented — 210h — Unimplemented — — 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD 0000 0000 0000 0000 213h SSP1MSK 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P 0000 0000 0000 0000 215h SSP1CON1 WCOL SSPOV SSPEN CKP 0000 0000 0000 0000 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 — — 218h — — 21Fh ADD MSK S R/W UA BF SSPM Unimplemented Bank 5 28Ch ODCONA 28Dh ODCONB(3) 28Eh ODCONC — — ODA5 ODA4 — ODA2 ODA1 ODA0 --00 -000 --00 -000 ODB7 ODB6 ODB5 ODB4 — — — — 0000 ---- 0000 ---- ODC7(3) ODC6(3) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000 — 28Fh — Unimplemented — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON — — DC1B CCP1M xxxx xxxx uuuu uuuu --00 0000 --00 0000 — — uuuu uuuu 294h — — 297h Unimplemented 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu --00 0000 --00 0000 — — 0000 0000 0000 0000 — — --00 -000 29Ah CCP2CON 29Bh — — 29Dh — — DC2B CCP2M Unimplemented 29Eh CCPTMRS 29Fh — P4TSEL P3TSEL C2TSEL C1TSEL Unimplemented Bank 6 30Ch SLRCONA 30Dh SLRCONB(3) 30Eh SLRCONC 30Fh — — 31Fh Legend: Note 1: 2: 3: 4: — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 --00 -000 SLRB7 SLRB6 SLRB5 SLRB4 — — — — 0000 ---- 0000 ---- SLRC7(3) SLRC6(3) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 0000 0000 0000 0000 — — Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8. DS40001715D-page 34  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 38Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111 INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 1111 ---- 1111 ---- 38Eh INLVLC INLVLC7(3) INLVLC6(3) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111 38Fh — Unimplemented — — 390h — Unimplemented — — 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h IOCBP(3) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ---- 395h IOCBN(3) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ---- 396h IOCBF(3) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ---- 397h IOCCP IOCCP7(3) IOCCP6(3) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IIOCCP1 IOCCP0 0000 0000 0000 0000 398h IOCCN IOCCN7(3) IOCCN6(3) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IIOCCN1 IOCCN0 0000 0000 0000 0000 399h IOCCF IOCCF7(3) IOCCF6(3) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IIOCCF1 IOCCF0 0000 0000 0000 0000 Unimplemented — — Unimplemented — — uuuu uuuu 38Dh INLVLB(3) 39Ah — — 39Fh Bank 8 40Ch — — 414h 415h TMR4 Holding Register for the Least Significant Byte of the 16-bit TMR4 Register xxxx xxxx 416h PR4 Holding Register for the Most Significant Byte of the 16-bit TMR4 Register xxxx xxxx uuuu uuuu 417h T4CON -000 0000 -000 0000 — — uuuu uuuu 418h — — 41Bh — T4OUTPS TMR4ON T4CKPS Unimplemented 41Ch TMR6 Holding Register for the Least Significant Byte of the 16-bit TMR6 Register xxxx xxxx 41Dh PR6 Holding Register for the Most Significant Byte of the 16-bit TMR6 Register xxxx xxxx uuuu uuuu -000 0000 -000 0000 Unimplemented — — Unimplemented — — Unimplemented — — 00-0 --00 00-0 --00 — — 00-0 --00 00-0 --00 — — 41Eh T6CON 41Fh — — T6OUTPS TMR6ON T6CKPS Bank 9 48Ch to — 49Fh Bank 10 50Ch — — 510h 511h OPA1CON 512h — 514h — 515h OPA2CON 516h — — 51Fh Legend: Note 1: 2: 3: 4: OPA1EN OPA1SP — OPA1UG — — OPA1PCH Unimplemented OPA2EN OPA2SP — OPA2UG — — OPA2PCH Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8.  2013-2015 Microchip Technology Inc. DS40001715D-page 35 PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — xx-- ---- uu-- ---- xxxx xxxx uuuu uuuu Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 11 D8Ch to — DADh Bank 12 60Ch to — 616h 617h PWM3DCL 618h PWM3DCH 619h PWM3CON PWM3DC — PWM3EN — — — — — — — — 0-x0 ---- u-uu ---- — — — — 00-- ---- uu-- ---- 0000 0000 uuuu uuuu 0-x0 ---- u-uu ---- Unimplemented — — Unimplemented — — PWM4DC PWM3OUT PWM3POL — 61Bh PWM4DCH 61Dh — — 61Fh — PWM3DC 61Ah PWM4DCL 61Ch PWM4CON — — PWM4DC PWM4EN — PWM4OUT PWM4POL — — — — Bank 13 68Ch to — 690h 691h COG1PHR — — COG Rising Edge Phase Counter Register --xx xxxx --uu uuuu 692h COG1PHF — — COG Falling Edge Phase Counter Register --xx xxxx --uu uuuu 693h COG1BLKR — — COG Rising Edge Blanking Counter Register --xx xxxx --uu uuuu 694h COG1BLKF — — COG Falling Edge Blanking Counter Register --xx xxxx --uu uuuu 695h COG1DBR — — COG Rising Edge Dead-band Counter Register --xx xxxx --uu uuuu 696h COG1DBF — — COG Falling Edge Dead-band Counter Register --xx xxxx --uu uuuu 697h COG1CON0 G1EN G1LD — 00-0 0000 00-0 0000 698h COG1CON1 G1RDBS G1FDBS — — G1POLD G1POLC G1POLB G1POLA 00-- 0000 00-- 0000 — G1RIS6 G1RIS5 G1RIS4 G1RIS3 G1RIS2 G1RIS1 G1RIS0 -000 0000 -000 0000 69Ah COG1RSIM — G1RSIM6 G1RSIM5 G1RSIM4 G1RSIM3 G1RSIM2 G1RSIM1 G1RSIM0 -000 0000 -000 0000 69Bh COG1FIS — -000 0000 -000 0000 699h COG1RIS G1FIS5 G1FIS4 G1FIS3 G1FIS2 G1FIS1 G1FIS0 G1FSIM5 G1FSIM4 G1FSIM3 G1FSIM2 G1FSIM1 G1FSIM0 -000 0000 -000 0000 — — 0001 01-- 0001 01-- G1AS1E G1AS0E ---- 0000 ---- 0000 G1STRA 0000 0001 0000 0001 — — — G1FSIM6 69Dh COG1ASD0 G1ASE G1ARSEN 69Eh COG1ASD1 — — G1SDATD G1MD G1FIS6 69Ch COG1FSIM 69Fh COG1STR G1CS G1SDATC G1ASDBD — G1SDATB — G1SDATA G1ASDAC G1AS3E G1STRD G1AS2E G1STRC G1STRB Bank 14-27 x0Ch/ — x8Ch — x1Fh/ x9Fh Legend: Note 1: 2: 3: 4: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8. DS40001715D-page 36  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — ---- ---0 ---- ---0 Bank 28 E0Ch — — E0Eh E0Fh Unimplemented PPSLOCK — — — E10h INTPPS — — — INTPPS ---0 0010 ---u uuuu E11h T0CKIPPS — — — T0CKIPPS ---0 0010 ---u uuuu E12h T1CKIPPS — — — T1CKIPPS ---0 0101 ---u uuuu E13h T1GPPS — — — T1GPPS ---0 0100 ---u uuuu E14h CCP1PPS — — — CCP1PPS ---1 0101 ---u uuuu E15h CCP2PPS — — — CCP2PPS ---1 0011 ---u uuuu E16h — E17h COGINPPS E18h — — E1Fh — — — — PPSLOCKED Unimplemented — — — COGINPPS Unimplemented E20h SSPCLKPPS E21h SSPDATPPS E22h SSPSSPPS E23h — — — ---0 0010 ---u uuuu — — — — — SSPCLKPPS ---1 0000(3) ---u uuuu — — — SSPCLKPPS ---0 1110(4) ---u uuuu — — — SSPDATPPS ---1 0001(3) ---u uuuu — — — SSPDATPPS ---0 1100(4) ---u uuuu — — — SSPSSPPS ---1 0011(3) ---u uuuu — — — SSPSSPPS ---1 0110(4) ---u uuuu — — — RXPPS ---1 0101(3) ---u uuuu — — — RXPPS ---0 1101(4) ---u uuuu — — — CKPPS ---1 0100(3) ---u uuuu — — — CKPPS ---0 1111(4) ---u uuuu Unimplemented — — E24h RXPPS E25h CKPPS E26h — Unimplemented E27h — Unimplemented — — E28h CLCIN0PPS — — — CLCIN0PPS ---1 0011 ---u uuuu E29h CLCIN1PPS — — — CLCIN1PPS ---1 0100 ---u uuuu E2Ah CLCIN2PPS — — — CLCIN2PPS ---1 0001 ---u uuuu CLCIN3PPS — — — CLCIN3PPS ---0 0101 ---u uuuu — — E2Bh E2Ch to — E7Fh Legend: Note 1: 2: 3: 4: — Unimplemented — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8.  2013-2015 Microchip Technology Inc. DS40001715D-page 37 PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bit 6 Bit 5 — — — — RA0PPS ---0 0000 ---u uuuu Bank 29 E8Ch — E8Fh — Unimplemented E90h RA0PPS — E91h RA1PPS — — — RA1PPS ---0 0000 ---u uuuu E92h RA2PPS — — — RA2PPS ---0 0000 ---u uuuu E93h — Unimplemented E94h RA4PPS E95h RA5PPS — — — — — RA4PPS ---0 0000 ---u uuuu — — — RA5PPS ---0 0000 ---u uuuu E96h — Unimplemented — — E97h — Unimplemented — — E98h — Unimplemented — — E99h — Unimplemented — — E9Ah — Unimplemented — — E9Bh — Unimplemented — — E9Ch (3) RB4PPS — — — RB4PPS ---0 0000 ---u uuuu E9Dh RB5PPS(3) — — — RB5PPS ---0 0000 ---u uuuu E9Eh (4) RB6PPS — — — RB6PPS ---0 0000 ---u uuuu E9Fh RB7PPS(3) — — — RB7PPS ---0 0000 ---u uuuu EA0h RC0PPS — — — RC0PPS ---0 0000 ---u uuuu EA1h RC1PPS — — — RC1PPS ---0 0000 ---u uuuu EA2h RC2PPS — — — RC2PPS ---0 0000 ---u uuuu EA3h RC3PPS — — — RC3PPS ---0 0000 ---u uuuu EA4h RC4PPS — — — RC4PPS ---0 0000 ---u uuuu EA5h RC5PPS — — — RC5PPS ---0 0000 ---u uuuu EA6h (4) RC6PPS — — — RC6PPS ---0 0000 ---u uuuu EA7h RC7PPS(4) — — — RC7PPS ---0 0000 ---u uuuu — — EA8h — EEFh — Legend: Note 1: 2: 3: 4: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8. DS40001715D-page 38  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all other Resets Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR — — — — — — — MLC3OUT MLC2OUT MLC1OUT ---- -000 ---- -000 F10h CLC1CON LC1EN — LC1OUT LC1INTP 0-x0 0000 0-00 0000 F11h LC1POL — — — LC1G1POL x--- xxxx 0--- uuuu F12h CLC1SEL0 — — — LC1D1S ---x xxxx ---u uuuu F13h CLC1SEL1 — — — LC1D2S ---x xxxx ---u uuuu F14h CLC1SEL2 — — — LC1D3S ---x xxxx ---u uuuu F15h CLC1SEL3 — — — LC1D4S ---x xxxx ---u uuuu Addr Name Bit 7 Bank 30 F0Ch — F0Eh — Unimplemented F0Fh CLCDATA CLC1POL LC1INTN LC1MODE LC1G4POL LC1G3POL LC1G2POL F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu F1Ah CLC2CON LC2EN — LC2OUT LC2INTP F1Bh CLC2POL LC2POL — — — F1Ch CLC2SEL0 — — — F1Dh CLC2SEL1 — — — F1Eh CLC2SEL2 — — F1Fh CLC2SEL3 — — LC2INTN LC2MODE 0-00 0000 0-00 0000 0--- xxxx 0--- uuuu LC2D1S ---x xxxx ---u uuuu LC2D2S ---x xxxx ---u uuuu — LC2D3S ---x xxxx ---u uuuu — LC2D4S ---x xxxx ---u uuuu LC2G4POL LC2G3POL LC2G2POL LC2G1POL F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu F24h CLC3CON LC3EN — LC3OUT LC3INTP F25h CLC3POL LC3POL — — — F26h CLC3SEL0 — — — F27h CLC3SEL1 — — — F28h CLC3SEL2 — — F29h CLC3SEL3 — — LC3INTN LC3MODE 0-00 0000 0-00 0000 0--- xxxx 0--- uuuu LC3D1S ---x xxxx ---u uuuu LC3D2S ---x xxxx ---u uuuu — LC3D3S ---x xxxx ---u uuuu — LC3D4S ---x xxxx ---u uuuu LC3G4POL LC3G3POL LC3G2POL LC3G1POL F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu F2Eh — — F6Fh Unimplemented — — Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8.  2013-2015 Microchip Technology Inc. DS40001715D-page 39 PIC16(L)F1704/8 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu Bank 31 F8Ch to — FE3h Unimplemented — FE4h STATUS_ SHAD FE5h WREG_ SHAD — — — — Z DC Working Register Shadow FE6h BSR_SHAD — FE7h PCLATH_ SHAD — — — Bank Select Register Shadow Program Counter Latch High Register Shadow C FE8h FSR0L_ SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_ SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_ SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_ SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh — Unimplemented FEDh STKPTR FEEh TOSL — Note 1: 2: 3: 4: — Current Stack Pointer Top of Stack Low byte FEFh TOSH Legend: — — Top of Stack High byte — — ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1704 only. PIC16(L)F1708 only. Unimplemented on PIC16LF1704/8. DS40001715D-page 40  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 3.5 3.5.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 3-3: If using the CALL instruction, the PCH and PCL registers are loaded with the operand of the CALL instruction. PCH is loaded with PCLATH. PC LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 14 PCH PCL 0 PCLATH PC 8 ALU Result PCL 0 4 0 11 OPCODE PC 14 PCH PCL 0 CALLW 6 PCLATH PC Instruction with PCL as Destination GOTO, CALL 6 PCLATH 0 14 7 0 PCH 8 W PCL 0 BRW PC + W 14 PCH 3.5.4 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. PCL 0 BRA 15 PC + OPCODE 3.5.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.5.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).  2013-2015 Microchip Technology Inc. DS40001715D-page 41 PIC16(L)F1704/8 3.6 3.6.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 3-1). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL DS40001715D-page 42 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1)  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL  2013-2015 Microchip Technology Inc. 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06 DS40001715D-page 43 PIC16(L)F1704/8 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.6.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.7 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory DS40001715D-page 44  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits.  2013-2015 Microchip Technology Inc. DS40001715D-page 45 PIC16(L)F1704/8 3.7.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x00 0x7F DS40001715D-page 46  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 3.7.2 3.7.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire Program Flash Memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the Program Flash Memory cannot be accomplished via the FSR/INDF interface. All instructions that access Program Flash Memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF  2013-2015 Microchip Technology Inc. 0xF6F 0xFFFF 0x7FFF DS40001715D-page 47 PIC16(L)F1704/8 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. DS40001715D-page 48  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 U-1 BOREN — bit 13 R/P-1 (1) CP R/P-1 R/P-1 MCLRE PWRTE bit 8 R/P-1 R/P-1 R/P-1 WDTE R/P-1 R/P-1 FOSC bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor and internal/external switchover are both enabled. 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 Unimplemented: Read as ‘1’ bit 7 CP: Code Protection bit(1) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled  2013-2015 Microchip Technology Inc. DS40001715D-page 49 PIC16(L)F1704/8 REGISTER 4-1: bit 2-0 Note 1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins The entire Flash program memory will be erased when the code protection is turned off during an erase. When a Bulk Erase Program Memory Command is executed, the entire Program Flash Memory and configuration memory will be erased. DS40001715D-page 50  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 LVP (1) R/P-1 DEBUG R/P-1 (2) LPBOR R/P-1 (3) BORV R/P-1 R/P-1 STVREN PLLEN bit 13 bit 8 R/P-1 U-1 U-1 U-1 U-1 R/P-1 ZCDDIS — — — — PPS1WAY R/P-1 bit 7 R/P-1 WRT bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(2) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = Brown-out Reset voltage (VBOR), low trip point selected. 0 = Brown-out Reset voltage (VBOR), high trip point selected. bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7 ZCDDIS: ZCD Disable bit 1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 = ZCD always enabled bit 6-3 Unimplemented: Read as ‘1’ bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit 1 = The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 = The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed) bit 1-0 WRT: Flash Memory Self-Write Protection bits 4 kW Flash memory 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write protected, no addresses may be modified by PMCON control Note 1: 2: 3: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. See VBOR parameter for specific trip point voltages.  2013-2015 Microchip Technology Inc. DS40001715D-page 51 PIC16(L)F1704/8 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write Protection” for more information. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F170X Memory Programming Specification” (DS41683). DS40001715D-page 52  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 4.6 Device ID and Revision ID The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device and Revision REGISTER 4-3: DEVID: DEVICE ID REGISTER R R R R R R DEV bit 13 R R bit 8 R R R R R R DEV bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared DEV: Device ID bits Device DEVID Values PIC16F1704 11 0000 0100 0011 (3043h) PIC16LF1704 11 0000 0100 0101 (3045h) PIC16F1708 11 0000 0100 0010 (3042h) PIC16LF1708 11 0000 0100 0100 (3044h) REGISTER 4-4: REVID: REVISION ID REGISTER R R R R R R REV bit 13 R R bit 8 R R R R R R REV bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared REV: Revision ID bits  2013-2015 Microchip Technology Inc. DS40001715D-page 53 PIC16(L)F1704/8 5.0 RESETS There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE VPP/MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD BOR Active(1) Brown-out Reset LPBOR Reset Note 1: R PWRT Done LFINTOSC PWRTE See Table 5-1 for BOR active conditions. DS40001715D-page 54  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 5.1.1 • • • • POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). TABLE 5-1: The Brown-out Reset module has four operating modes controlled by the BOREN bits in Configuration Words. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 5-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 5-2 for more information. BOR OPERATING MODES BOREN SBOREN Device Mode BOR Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 Instruction Execution upon: Release of POR or Wake-up from Sleep Waits for BOR ready(1) (BORRDY = 1) Waits for BOR ready (BORRDY = 1) Waits for BOR ready(1) (BORRDY = 1) Begins immediately (BORRDY = x) Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN bits. 5.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 5.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. 5.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.  2013-2015 Microchip Technology Inc. DS40001715D-page 55 PIC16(L)F1704/8 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 5.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. Register Definitions: BOR Control REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS(1) — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN = 11 (Always on) or BOREN = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN = 10 (Disabled in Sleep) or BOREN = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN bits are located in Configuration Words. DS40001715D-page 56  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 5.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.4.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 5.4.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON register and to the power control block. 5.5 MCLR 5.6 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 9.0 “Watchdog Timer (WDT)” for more information. 5.7 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table 5-4 for default conditions after a RESET instruction has occurred. 5.8 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See 3.6.2 “Overflow/Underflow Reset” for more information. 5.9 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 5-2). 5.10 TABLE 5-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 5.5.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 5.5.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.1 “PORTA Registers” for more information.  2013-2015 Microchip Technology Inc. Power-Up Timer The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 5.11 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. DS40001715D-page 57 PIC16(L)F1704/8 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC DS40001715D-page 58  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 5.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.  2013-2015 Microchip Technology Inc. DS40001715D-page 59 PIC16(L)F1704/8 5.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register 5-2. 5.14 Register Definitions: Power Control REGISTER 5-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF — R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS40001715D-page 60  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 56 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 60 STATUS — — — TO PD Z DC C 23 WDTCON — — SWDTEN 100 WDTPS Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.  2013-2015 Microchip Technology Inc. DS40001715D-page 61 PIC16(L)F1704/8 6.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 6.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL or EXTRC modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. DS40001715D-page 62 The oscillator module can be configured in one of the following clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM – External Clock Medium Power mode (0.5 MHz to 4 MHz) ECH – External Clock High-Power mode (4 MHz to 32 MHz) LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) EXTRC – External Resistor-Capacitor INTOSC – Internal oscillator (31 kHz to 32 MHz) Clock Source modes are selected by the FOSC bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The ECH, ECM, and ECL clock modes rely on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The EXTRC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these three clock sources.  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 6-1: Secondary Oscillator Timer1 Timer1 Clock Source Option for other modules SOSCO T1OSCEN Enable Oscillator SOSCI T1OSC 01 External Oscillator LP, XT, HS, RC, EC OSC2 0 Sleep 00 PRIMUX OSC1 4 x PLL 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz PLLMUX 500 kHz Source 16 MHz (HFINTOSC) 500 kHz (MFINTOSC) 31 kHz Source INTOSC SCS 31 kHz 0000 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Inputs FOSC PLLEN or SPLLEN 0 =100 1 =00 ≠100 ≠00 X 0 Outputs IRCF PRIMUX PLLMUX x 1 0 =1110 1 1 ≠1110 1 0 x 0 0 1 x 0 1 X X X X  2013-2015 Microchip Technology Inc. 1X 1111 MUX HFPLL Postscaler Internal Oscillator Block FOSC To CPU and Peripherals 1 IRCF SCS Sleep 0 1 DS40001715D-page 63 PIC16(L)F1704/8 6.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (EXTRC) mode circuits. Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 6.3 “Clock Switching” for additional information. 6.2.1 EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: • Program the FOSC bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. • Write the SCS bits in the OSCCON register to switch the system clock source to: - Secondary oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 6.3 “Clock Switching”for more information. 6.2.1.1 EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 6-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 6-2: EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN Clock from Ext. System PIC® MCU FOSC/4 or I/O(1) Note 1: 6.2.1.2 OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Words. LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 6-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 6-3 and Figure 6-4 show typical circuits for quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Words: • ECH – High power, 4-32 MHz • ECM – Medium power, 0.5-4 MHz • ECL – Low power, 0-0.5 MHz DS40001715D-page 64  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 FIGURE 6-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 6-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 To Internal Logic Quartz Crystal C2 Note 1: 2: OSC1/CLKIN RS(1) RF(2) C1 Sleep OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. RP(3) C2 Ceramic RS(1) Resonator Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949)  2013-2015 Microchip Technology Inc. To Internal Logic RF(2) Sleep OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 6.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended, unless either FSCM or Two-Speed Start-Up are enabled. In this case, code will continue to execute at the selected INTOSC frequency while the OST is counting. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 6.4 “Two-Speed Clock Start-up Mode”). DS40001715D-page 65 PIC16(L)F1704/8 6.2.1.4 4x PLL The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Table 32-9. The 4x PLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Words to a ‘1’. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored. 6.2.1.5 Secondary Oscillator The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 6.3 “Clock Switching” for more information. FIGURE 6-5: Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) PIC® MCU SOSCI C1 To Internal Logic 32.768 kHz Quartz Crystal C2 DS40001715D-page 66 SOSCO  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 6.2.1.6 External RC Mode 6.2.2 The external Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. Figure 6-6 shows the external RC mode connections. FIGURE 6-6: VDD EXTERNAL RC MODES PIC® MCU The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 6.3 “Clock Switching” for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. REXT OSC1/CLKIN Internal Clock CEXT VSS The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL that can produce one of three internal system clock sources. 1. FOSC/4 or I/O(1) OSC2/CLKOUT Recommended values: 10 k  REXT  100 k, 20 pF, 2-5V Note 1: INTERNAL CLOCK SOURCES Output depends upon CLKOUTEN bit of the Configuration Words. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance 2. 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The user also needs to take into account variation due to tolerance of external RC components used.  2013-2015 Microchip Technology Inc. DS40001715D-page 67 PIC16(L)F1704/8 6.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The HFINTOSC is enabled by: • Configure the IRCF bits of the OSCCON register for the desired HF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 6.2.2.2 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF bits of the OSCCON register for the desired HF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. DS40001715D-page 68 6.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 6-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 6.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a multiplexer (see Figure 6-1). Select 31 kHz, via software, using the IRCF bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: • Configure the IRCF bits of the OSCCON register for the desired LF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 6.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF of the OSCCON register. The postscaled output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connect to a multiplexer (see Figure 6-1). The Internal Oscillator Frequency Select bits IRCF of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: - 32 MHz (requires 4x PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF bits of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. 6.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC = 100). • The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC in Configuration Words (SCS = 00). • The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC set to use (IRCF = 1110). • The SPLLEN bit in the OSCCON register must be set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a ‘1’. Note: When using the PLLEN bit of the Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN option will not be available. The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4x PLL with the internal oscillator. The IRCF bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.  2013-2015 Microchip Technology Inc. DS40001715D-page 69 PIC16(L)F1704/8 6.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-7). If this is the case, there is a delay after the IRCF bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. IRCF bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 6-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 6-1. Start-up delay specifications are located in the oscillator tables of Section 32.0 “Electrical Specifications”. DS40001715D-page 70  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 FIGURE 6-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ MFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Oscillator Delay(1) 2-cycle Sync Running LFINTOSC IRCF 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF =0 0 System Clock Note: See Table 6-1 for more information.  2013-2015 Microchip Technology Inc. DS40001715D-page 71 PIC16(L)F1704/8 6.3 Clock Switching 6.3.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. • Default system oscillator determined by FOSC bits in Configuration Words • Timer1 32 kHz crystal oscillator • Internal Oscillator Block (INTOSC) The secondary oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 25.0 “Timer1 Module with Gate Control” for more information about the Timer1 peripheral. 6.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals. • When the SCS bits of the OSCCON register = 00, the system clock source is determined by the value of the FOSC bits in the Configuration Words. • When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 6-1. 6.3.2 6.3.4 SECONDARY OSCILLATOR READY (SOSCR) BIT The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator. 6.3.5 CLOCK SWITCHING BEFORE SLEEP When clock switching from an old clock to a new clock is requested just prior to entering Sleep mode, it is necessary to confirm that the switch is complete before the SLEEP instruction is executed. Failure to do so may result in an incomplete switch and consequential loss of the system clock altogether. Clock switching is confirmed by monitoring the clock Status bits in the OSCSTAT register. Switch confirmation can be accomplished by sensing that the ready bit for the new clock is set or the ready bit for the old clock is cleared. For example, when switching between the internal oscillator with the PLL and the internal oscillator without the PLL, monitor the PLLR bit. When PLLR is set, the switch to 32 MHz operation is complete. Conversely, when PLLR is cleared, the switch from 32 MHz operation to the selected internal clock is complete. OSCILLATOR START-UP TIMER STATUS (OSTS) BIT The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator. DS40001715D-page 72  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 6.4 6.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Words) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). • SCS (of the OSCCON register) = 00. • FOSC bits in the Configuration Words configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 6-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay Sleep/POR LFINTOSC(1) MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 cycles Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each Sleep/POR Secondary Oscillator 32 kHz-20 MHz LP, XT, HS(1) 1024 Clock Cycles (OST) Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC(1) 31 kHz 1 cycle of each Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 2 ms (approx.) Note 1: 16-32 MHz PLL inactive.  2013-2015 Microchip Technology Inc. DS40001715D-page 73 PIC16(L)F1704/8 6.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 6.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 6-8: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC bits in the Configuration Words, or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS40001715D-page 74  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 6.5 6.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Secondary Oscillator and RC). FIGURE 6-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock LFINTOSC Oscillator ÷ 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 6.5.1 FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 6-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 6.5.2 The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware. 6.5.4 Clock Failure Detected FAIL-SAFE CONDITION CLEARING RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2013-2015 Microchip Technology Inc. DS40001715D-page 75 PIC16(L)F1704/8 FIGURE 6-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS40001715D-page 76  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 6.6 Register Definitions: Oscillator Control REGISTER 6-1: R/W-0/0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-1/1 SPLLEN R/W-1/1 R/W-1/1 IRCF U-0 R/W-0/0 — R/W-0/0 SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF: Internal Oscillator Frequency Select bits 1111 = 16 MHz HF 1110 = 8 MHz or 32 MHz HF(2) 1101 = 4 MHz HF 1100 = 2 MHz HF 1011 = 1 MHz HF 1010 = 500 kHz HF(1) 1001 = 250 kHz HF(1) 1000 = 125 kHz HF(1) 0111 = 500 kHz MF (default upon Reset) 0110 = 250 kHz MF 0101 = 125 kHz MF 0100 = 62.5 kHz MF 0011 = 31.25 kHz HF(1) 0010 = 31.25 kHz MF 000x = 31 kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS: System Clock Select bits 1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC in Configuration Words Note 1: 2: Duplicate frequency derived from HFINTOSC. 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency Selection”.  2013-2015 Microchip Technology Inc. DS40001715D-page 77 PIC16(L)F1704/8 REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready If T1OSCEN = 0: 1 = Secondary clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC bits of the Configuration Words 0 = Running from an internal oscillator (FOSC = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS40001715D-page 78  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency 000001 = • • • 011110 = 011111 = Maximum frequency TABLE 6-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 Bit 5 Bit 4 OSCCON SPLLEN OSCSTAT SOSCR PLLR OSCTUNE — — PIR2 OSFIF C2IF C1IF — PIE2 OSFIE C2IE C1IE — T1CON Legend: CONFIG1 Legend: Bit 2 IRCF TMR1CS OSTS Bit 1 — HFIOFR HFIOFL Bit 0 SCS MFIOFR LFIOFR 77 HFIOFS TUN BCL1IF T1CKPS Register on Page 78 79 TMR6IF TMR4IF CCP2IF 90 BCL1IE TMR6IE T1OSCEN T1SYNC TMR4IE CCP2IE 87 — TMR1ON 253 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 6-3: Name Bit 3 SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE WDTE Bit 10/2 Bit 9/1 Bit 8/0 BOREN — FOSC Register on Page 49 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.  2013-2015 Microchip Technology Inc. DS40001715D-page 79 PIC16(L)F1704/8 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1 (TMR1IE) PIE1 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn PIEn DS40001715D-page 80 GIE  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details. The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section 7.5 “Automatic Context Saving”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.  2013-2015 Microchip Technology Inc. DS40001715D-page 81 PIC16(L)F1704/8 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Inst(PC) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC DS40001715D-page 82 PC+2 NOP NOP  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 32.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2013-2015 Microchip Technology Inc. DS40001715D-page 83 PIC16(L)F1704/8 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0 “Power-Down Mode (Sleep)” for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • • • • • W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved. DS40001715D-page 84  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: Note: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers have been cleared by software. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2013-2015 Microchip Technology Inc. DS40001715D-page 85 PIC16(L)F1704/8 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001715D-page 86  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the Timer6 to PR6 match interrupt 0 = Disables the Timer6 to PR6 match interrupt bit 1 TMR4IE: TMR4to PR4 Match Interrupt Enable bit 1 = Enables the Timer4 to PR4 match interrupt 0 = Disables the Timer4 to PR4 match interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2013-2015 Microchip Technology Inc. DS40001715D-page 87 PIC16(L)F1704/8 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 COGIE: COG Auto-Shutdown Interrupt Enable bit 1 = COG interrupt enabled 0 = COG interrupt disabled bit 4 ZCDIE: Zero-Cross Detection Interrupt Enable bit 1 = ZCD interrupt enabled 0 = ZCD interrupt disabled bit 3 Unimplemented: Read as ‘0’ bit 2 CLC3IE: CLC3 Interrupt Enable bit 1 = CLC3 interrupt enabled 0 = CLC3 interrupt disabled bit 1 CLC2IE: CLC2 Interrupt Enable bit 1 = CLC2 interrupt enabled 0 = CLC2 interrupt disabled bit 0 CLC1IE: CLC1 Interrupt Enable bit 1 = CLC1 interrupt enabled 0 = CLC1 interrupt disabled Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001715D-page 88  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2013-2015 Microchip Technology Inc. DS40001715D-page 89 PIC16(L)F1704/8 REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 TMR6IF: Timer6 to PR6 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR4IF: Timer4 to PR4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001715D-page 90  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 COGIF: COG Auto-Shutdown Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 ZCDIF: Zero-Cross Detection Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 Unimplemented: Read as ‘0’ bit 2 CLC3IF: CLC3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 CLC2IF: CLC2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CLC1IF: CLC1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2013-2015 Microchip Technology Inc. DS40001715D-page 91 PIC16(L)F1704/8 TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IF Bit 1 Bit 0 INTF IOCIF Register on Page GIE PEIE TMR0IE INTE IOCIE WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 86 PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 87 OPTION_REG PS 85 244 PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE 88 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 89 PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 90 PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF 91 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. DS40001715D-page 92  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. Timer1 and peripherals that operate from Timer1 continue operation in Sleep when the Timer1 clock source selected is: • LFINTOSC • T1CKI • Secondary oscillator ADC is unaffected, if the dedicated FRC oscillator is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: • • • • • • External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 5.12 “Determining the Cause of a Reset”. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using secondary oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 22.0 “8-Bit Digital-to-Analog Converter (DAC1) Module” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these modules.  2013-2015 Microchip Technology Inc. DS40001715D-page 93 PIC16(L)F1704/8 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared FIGURE 8-1: • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 6.4 “Two-Speed Clock Start-up Mode”. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. DS40001715D-page 94  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 8.2 Low-Power Sleep Mode The PIC16F1704/8 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1704/8 allows the user to optimize the operating current in Sleep, depending on the application requirements. A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 8.2.1 SLEEP CURRENT VS. WAKE-UP TIME In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. 8.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The Low-Power Sleep mode is intended for use only with the following peripherals: • • • • Brown-Out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer1 (with external clock source  0 ( 0 ?  (  >  1 < < 6 9"="% 9 ) 9"="% :  )* 1+ ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+21 &    %#%!  ))% !%%          ) +01 DS40001715D-page 432  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001715D-page 433 PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001715D-page 434  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54  2013-2015 Microchip Technology Inc. DS40001715D-page 435 PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001715D-page 436  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001715D-page 437 PIC16(L)F1704/8 !   " # $   %& '  (()*   "#   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 D2 D EXPOSED PAD e E2 E 2 2 1 1 b TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 6% &  9&% 7!&(  $ 99- - 7 7 7: ; ? %  : 8%  >   %" $$    0 + %% 4 , : ="% - -# ""="% - : 9%  -# ""9% ?01+ -3 1+ 0 ?0 > 1+  0 ?0 + %%="% ( 0 , ,0 + %%9% 9 ,  0 + %%% -# "" V  <     !"#$%! & '(!%&! %( %")%%%"   4  ) !%" , &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !     > <       ) +1 DS40001715D-page 438  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001715D-page 439 PIC16(L)F1704/8 +                3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54  N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 6% &  9&% 7!&(  $ 7+8- 7 7 7: ;  %  % %  < <   ""4 4  0 , 0 1 % %  0 < <  !" %  !" ="% - , , ,0  ""4="% -  0 > : 9%  > , ? % % 9 0 , 0 9" 4  >  0 ( 0 ?  (  >  1 < < 6 9"="% 9 ) 9"="% :  )* 1+ ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+2 1 &    %#%!  ))% !%%          ) +1 DS40001715D-page 440  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 +   ,-.% , /  ,,  0)   ,,/    3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 6% &  9&% 7!&(  $ L 99- - 7 7 7: ;  %  : 8%  < ?01+ <   ""4 4  ?0 0 >0 %" $$  0 < < : ="% -  > >  ""4="% - 0 0, 0? : 9%  ?  0 3 %9% 9 00 0 0 3 % % 9 0-3 9" 4   < 3 %  W W 0 >W 9"="% (  < ,>     !"#$%! & '(!%&! %( %")%%%"   &   "-"  %!"& "$   % !    "$   % !     %#"&&  " , &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !           ) +1  2013-2015 Microchip Technology Inc. DS40001715D-page 441 PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001715D-page 442  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001715D-page 443 PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001715D-page 444  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001715D-page 445 PIC16(L)F1704/8 +   " # $   %& '  (()*   "#   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54  D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 6% &  9&% 7!&(  $ 99- - 7 7 7: ;  %  : 8%  >   %" $$    0 + %% 4 , : ="% - -# ""="% - : 9%  -# ""9% 01+ -3 1+ ?  > 1+  ?  > + %%="% ( > 0 , + %%9% 9 ,  0 + %%% -# "" V  < <     !"#$%! & '(!%&! %( %")%%%"   4  ) !%" , &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !           ) +?1 DS40001715D-page 446  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54  2013-2015 Microchip Technology Inc. DS40001715D-page 447 PIC16(L)F1704/8 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (07/2013) Initial release. Revision B (09/2013) Moved Note 1 from Table 3-10 to Table 3-9; Register 4-2, Removed overbar from bit 7; Table 8-1, removed IOCBF, IOCBN, IOCBP; Register 12-3, revised bit 4-0; Revised Table 32-1, Param. D003; Revised Table 32-2, added Note 5 to D015, revised Note 5; Revised Table 32-7, OS03 Min.; Revised Table 32-17, OPA06, Min.; Revised Register 21-1, bit 6 description. Revision C (03/2015) Updated data sheet to Final status; Updated Sections 3.4.2, 8.2.2, 18.1.1, 20.1.2, 20.1.3, 21.1, 21.1.1, 22.3, 28.2.1, 29.4.2, 32.0 (“Electrical Specifications”) and 33.0 (“DC and AC Characteristics Graphs and Charts”); Updated introductory paragraph of Section 21.0; Added Sections 3.2 (“High-Endurance Flash”) and 14.3 (“FVR Buffer Stabilization Period”); Updated Tables 1, 2, 1-2, 6-1, 17-3, 19-1 and 20-3; Updated legend in Table 12-1; Updated note references and bit 2 of ADCON1 register in Table 3-10; Updated Figures 6-7, 14-1, 16-2, 18-2 through 18-6, 20-1, 21-1, 22-1, 25-1; Updated Registers 18-6, 18-7, 18-9, 20-1, 20-2, 21-1, 25-1; Other minor corrections. Revision D (10/2015) Added High-Endurance Flash Data Memory (HEF) bullet and updated XLP Features for consistency on front page. Added Section 6.3.5: Clock Switching Before Sleep. Updated PIC16(L)F170x Family Types Table. Updated Example 20-1; Section 20.2.6; and Tables 1-2 and 32-11. DS40001715D-page 448  2013-2015 Microchip Technology Inc. PIC16(L)F1704/8 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2013-2015 Microchip Technology Inc. DS40001715D-page 449 PIC16(L)F1704/8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F1704, PIC16LF1704, PIC16F1708, PIC16LF1708 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) ML P SP ST SL SO SS = = = = = = = Pattern: (Industrial) (Extended) QFN PDIP SPDIP TSSOP SOIC SOIC SSOP QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001715D-page 450 PIC16LF1704- I/P Industrial temperature PDIP package PIC16F1708- E/SS Extended temperature, SSOP package Note 1: 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office.  2013-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-888-8 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2013-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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