PIC16LF1789-I/PT

PIC16F1788/9 28-Pin 8-Bit Advanced Analog Flash Microcontroller High-Performance RISC CPU: • Only 49 Instructions • Operating Speed: - DC – 32 MHz clock input - DC – 125 ns instruction cycle • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: • Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory Memory Features: • Up to 16 KW Flash Program Memory: - Self-programmable under software control - Programmable code protection - Programmable write protection • 256 Bytes of Data EEPROM • Up to 2048 Bytes of RAM High-Performance PWM Controller: • Four Programmable Switch Mode Controller (PSMC) modules: - Digital and/or analog feedback control of PWM frequency and pulse begin/end times - 16-bit Period, Duty Cycle and Phase - 16 ns clock resolution - Supports Single PWM, Complementary, Push-Pull and 3-phase modes of operation - Dead-band control with 8-bit counter - Auto-shutdown and restart - Leading and falling edge blanking - Burst mode Extreme Low-Power Management PIC16LF1788/9 with XLP: • • • • Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Timer1 Oscillator: 500 nA @ 32 kHz Operating Current: - 8 A @ 32 kHz, 1.8V, typical - 32 A/MHz @ 1.8V, typical Analog Peripheral Features: • Analog-to-Digital Converter (ADC): - Fully differential 12-bit converter - Up to 75 ksps conversion rate - 11 single-ended channels - 5 differential channels - Positive and negative reference selection • One 8-Bit and Three 5-Bit Digital-to-Analog Converters (DAC): - Output available externally - Positive and negative reference selection - Internal connections to comparators, op amps, Fixed Voltage Reference (FVR) and ADC • Four High-Speed Comparators: - 50 ns response time @ VDD = 5V - Rail-to-rail inputs - Software selectable hysteresis - Internal connection to op amps, FVR and DAC • Up to Three Operational Amplifiers: - Rail-to-rail inputs/outputs - High/Low selectable Gain Bandwidth Product - Internal connection to DAC and FVR • Fixed Voltage Reference (FVR): - 1.024V, 2.048V and 4.096V output levels - Internal connection to ADC, comparators and DAC I/O Features: • Up to 36 I/O Pins and 1 Input-only Pin: • High Current Sink/Source for LED Drivers • Individually Programmable Interrupt-on-Change Pins • Individually Programmable Weak Pull-Ups • Individual Input Level Selection • Individually Programmable Slew Rate Control • Individually Programmable Open-Drain Outputs  2013-2015 Microchip Technology Inc. DS40001675C-page 1 PIC16(L)F1788/9 Digital Peripheral Features: General Microcontroller Features: • Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated low-power 32 kHz oscillator driver • Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two Capture/Compare/PWM modules (CCP): - 16-bit capture, maximum resolution 12.5 ns - 16-bit compare, max resolution 31.25 ns - 10-bit PWM, max frequency 32 kHz • Master Synchronous Serial Port (SSP) with SPI and I2C with: - 7-bit address masking - SMBus/PMBusTM compatibility • Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART): - RS-232, RS-485 and LIN compatible - Auto-baud detect - Auto-wake-up on start • • • • • • • • • • Power-Saving Sleep mode Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Brown-out Reset (BOR) with Selectable Trip Point Extended Watchdog Timer (WDT) In-Circuit Serial ProgrammingTM (ICSPTM) In-Circuit Debug (ICD) Enhanced Low-Voltage Programming (LVP) Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1788/9) - 2.3V to 5.5V (PIC16F1788/9) Oscillator Features: • Operate up to 32 MHz from Precision Internal Oscillator: - Factory calibrated to ±1%, typical - Software selectable frequency range from 32 MHz to 31 kHz • 31 kHz Low-Power Internal Oscillator • 32.768 kHz Timer1 Oscillator: - Available as system clock - Low-power RTC • External Oscillator Block with: - 4 crystal/resonator modes up to 32 MHz using 4x PLL - 3 external clock modes up to 32 MHz • 4x Phase-Locked Loop (PLL) • Fail-Safe Clock Monitor: - Detect and recover from external oscillator failure • Two-Speed Start-up: - Minimize latency between code execution and external oscillator start-up DS40001675C-page 2  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 PIC16(L)F1782 (1) 2048 256 256 25 11 3 2 1/0 2/1 2 2 1 1 I PIC16(L)F1783 (1) 4096 256 512 25 11 3 2 1/0 2/1 2 2 1 1 I PIC16(L)F1784 (2) 4096 256 512 36 15 4 3 1/0 2/1 3 3 1 1 I PIC16(L)F1786 (2) 8192 256 1024 25 11 4 2 1/0 2/1 3 3 1 1 I PIC16(L)F1787 (2) 8192 256 1024 36 15 4 3 1/0 2/1 3 3 1 1 I PIC16(L)F1788 (3) 16384 256 2048 25 11 4 2 1/3 2/1 4 3 1 1 I PIC16(L)F1789 (3) 16384 256 2048 36 15 4 3 1/3 2/1 4 3 1 1 I Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001579 PIC16(L)F1782/3 Data Sheet, 28-Pin Flash, 8-bit Advanced Analog MCUs. 2: DS40001637 PIC16(L)F1784/6/7 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs. 3: DS40001675 PIC16(L)F1788/9 Data Sheet, 28/40/44-Pin Flash, 8-bit Advanced Analog MCUs. Note: XLP Debug(1) MSSP (I2C/SPI) EUSART CCP Programmable Switch Mode Controllers (PSMC) Timers (8/16-bit) DAC (8/5-bit) Operational Amplifiers Comparators 12-bit ADC (ch) I/O’s(2) Data SRAM (bytes) Data EEPROM (bytes) Program Memory Flash (words) Device Data Sheet Index PIC16(L)F178X Family Types Y Y Y Y Y Y Y For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office.  2013-2015 Microchip Technology Inc. DS40001675C-page 3 PIC16(L)F1788/9 Pin Diagram – 28-Pin SPDIP, SOIC, SSOP 1 28 RB7/ICSPDAT RA0 RA1 2 27 3 RB6/ICSPCLK RB5 RA2 4 RA3 RA4 RA5 VSS 5 26 25 24 23 RA7 RA6 RC0 RC1 RC2 RC3 Note: 6 7 8 9 10 11 PIC16(L)F1788 VPP/MCLR/RE3 22 21 20 19 RB4 RB3 RB2 RB1 RB0 VDD 12 18 17 13 16 VSS RC7 RC6 RC5 14 15 RC4 See Table 1 for the location of all peripheral functions. Pin Diagram – 28-Pin QFN 28 27 26 25 24 23 22 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 QFN PIC16(L)F1788 8 9 10 11 12 13 14 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RA2 RA3 RA4 RA5 VSS RA7 RA6 Note: See Table 1 for the location of all peripheral functions. DS40001675C-page 4  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Pin Diagram – 40-Pin PDIP VPP/MCLR/RE3 1 40 RB7ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 5 36 RA4 6 35 RB2 RA5 RE0 7 34 8 33 RB1 RB0 RE1 9 32 VDD RE2 10 31 VSS VDD 11 30 RD7 VSS 12 29 RD6 RA7 13 28 RD5 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 RC2 RC3 17 18 24 23 RC5 RD0 19 22 RD3 21 RD2 RD1 Note: 20 PIC16(L)F1789 RA3 RB3 RC4 See Table 2 for the location of all peripheral functions.  2013-2015 Microchip Technology Inc. DS40001675C-page 5 PIC16(L)F1788/9 31 32 34 33 35 36 37 30 3 29 4 28 27 5 PIC16(L)F1789 6 26 7 25 8 24 23 9 20 19 18 17 16 15 14 13 22 21 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 11 10 12 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 38 RC7 1 RD4 2 39 40 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 Pin Diagram – 40-Pin UQFN (5x5) Note: See Table 2 for the location of all peripheral functions. DS40001675C-page 6  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 RC0 44 43 42 41 40 39 38 37 36 35 34 Pin Diagram – 44-Pin QFN RC7 1 33 RA6 RD4 2 32 RA7 RD5 3 31 N/C RD6 4 30 AVSS RD7 5 VSS 6 VDD 29 N/C 28 VDD 7 27 RE2 PIC16(L)F1789 19 20 21 22 RA1 RA2 RA3 RA4 RA0 23 18 11 VPP/MCLR/RE3 RB2 17 RA5 ICSPDAT/RB7 24 16 10 ICSPCLK/RB6 RB1 15 RE0 RB5 25 13 14 RE1 N/C RB4 26 9 12 8 RB3 AVDD RB0 See Table 2 for the location of all peripheral functions.  2013-2015 Microchip Technology Inc. DS40001675C-page 7 PIC16(L)F1788/9 PIC16(L)F1789 33 32 31 30 29 28 27 26 25 24 23 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 NC NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RC7 RD4 RD5 RD6 RD7 VSS VDD 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC Pin Diagram – 44-Pin TQFP Note: DS40001675C-page 8 See Table 2 for the location of all peripheral functions.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 PIN ALLOCATION TABLE 28-Pin SPDIP, SOIC, SSOP 28-Pin QFN, ADC Reference Comparator Operation Amplifiers 8-bit/ 5-bit DAC Timers PSMC CCP EUSART MSSP Interrupt Pull-up Basic 28-PIN ALLOCATION TABLE (PIC16(L)F1788) I/O TABLE 1: RA0 2 27 AN0 — C1IN0C2IN0C3IN0C4IN0- — — — — — — SS(1) IOC Y — RA1 3 28 AN1 — C1IN1C2IN1C3IN1C4IN1- OPA1OUT — — — — — — IOC Y — RA2 4 1 AN2 VREFDAC1VREF- C1IN0+ C2IN0+ C3IN0+ C4IN0+ DAC1OUT1 — — — — — IOC Y — RA3 5 2 AN3 VREF+ DAC1VREF+ DAC2VREF+ DAC3VREF+ DAC4VREF+ C1IN1+ — — — — — — — IOC Y — — RA4 6 3 — — C1OUT OPA1IN+ DAC4OUT1 T0CKI — — — — IOC Y RA5 7 4 AN4 — C2OUT OPA1IN- DAC2OUT1 — — — — SS IOC Y — RA6 10 7 — — C2OUT(1) — — — — — — — IOC Y VCAP OSC2 CLKOUT RA7 9 6 — — — — — — PSMC1CLK PSMC2CLK PSMC3CLK PSMC4CLK — — — IOC Y CLKIN OSC1 RB0 21 18 AN12 — C2IN1+ — — — CCP1(1) — — INT IOC Y — RB1 22 19 AN10 — C1IN3C2IN3C3IN3C4IN3- OPA2OUT — — PSMC1IN PSMC2IN PSMC3IN PSMC4IN — — — — IOC Y — RB2 23 20 AN8 — — OPA2IN- DAC3OUT1 — — — — — IOC Y CLKR RB3 24 21 AN9 — OPA2IN+ — — — CCP2(1) — — IOC Y — RB4 25 22 AN11 — C1IN2C2IN2C3IN2C3IN1+ — — — — — — SS(1) IOC Y — — SDO(1) IOC Y — — TX(1) CK(1) SDI(1) IOC SDA(1) Y ICSPCLK — — RX(1) DT(1) SCK(1) IOC SCL(1) Y ICSPDAT PSMC1A — — — IOC Y — RB5 26 23 AN13 — C4IN2C3OUT — — T1G — RB6 27 24 — — C4IN1+ — — — — RB7 28 25 — — — — DAC1OUT2 DAC2OUT2 DAC3OUT2 DAC4OUT2 — RC0 11 8 — — — — — T1CKI T1OSO (1) CCP3 RC1 12 9 — — — — — T1OSI PSMC1B CCP2 — — IOC Y — RC2 13 10 — — — — — — PSMC1C PSMC3B CCP1 — — IOC Y — RC3 14 11 — — — — — — PSMC1D PSMC4A — — SCK SCL IOC Y — RC4 15 12 — — — — — — PSMC1E PSMC4B — — SDI SDA IOC Y — RC5 16 13 — — — — — — PSMC1F PSMC3A — — SDO IOC Y — Note 1: Alternate pin function selected with the APFCON1 (Register 13-1) and APFCON2 (Register 13-2) registers.  2013-2015 Microchip Technology Inc. DS40001675C-page 9 PIC16(L)F1788/9 28-Pin QFN, ADC Reference Comparator Operation Amplifiers 8-bit/ 5-bit DAC Timers PSMC CCP MSSP Interrupt Pull-up Basic RC6 17 14 — — — — — — PSMC2A CCP3 TX CK — IOC Y — RC7 18 15 — — C4OUT — — — PSMC2B — RX DT — IOC Y — RE3 1 26 — — — — — — — — — — IOC Y MCLR VPP VDD 20 17 — — — — — — — — — — — — VDD VSS 8, 19 5, 16 — — — — — — — — — — — — VSS Note 1: EUSART 28-Pin SPDIP, SOIC, SSOP 28-PIN ALLOCATION TABLE (PIC16(L)F1788) (Continued) I/O TABLE 1: Alternate pin function selected with the APFCON1 (Register 13-1) and APFCON2 (Register 13-2) registers. DS40001675C-page 10  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 40-Pin PDIP 40-Pin UQFN 44-Pin TQFP 44-Pin QFN ADC Reference Comparator Op Amps 8-bit/ 5-bit DAC Timers PSMC CCP EUSART MSSP Interrupt Pull-up Basic 40/44-PIN ALLOCATION TABLE (PIC16(L)F1789) I/O TABLE 2: RA0 2 17 19 19 AN0 — C1IN0C2IN0C3IN0C4IN0- — — — — — — SS(1) IOC Y — RA1 3 18 20 20 AN1 — C1IN1C2IN1C3IN1C4IN1- OPA1OUT — — — — — — IOC Y — RA2 4 19 21 21 AN2 DAC1VREFVREF- C1IN0+ C2IN0+ C3IN0+ C4IN0+ DAC1OUT1 — — — — — IOC Y — RA3 5 20 22 22 AN3 VREF+ DAC1VREF+ DAC2VREF+ DAC3VREF+ DAC4VREF+ C1IN1+ — — — — — — — IOC Y — — RA4 6 21 23 23 — — C1OUT OPA1IN+ — T0CKI — — — — IOC Y RA5 7 22 24 24 AN4 — C2OUT OPA1IN- DAC2OUT1 — — — — SS IOC Y — RA6 14 29 31 33 — — C2OUT(1) — — — — — — — IOC Y VCAP CLKOUT OSC2 RA7 13 28 30 32 — — — — — — PSMC1CLK PSMC2CLK PSMC3CLK PSMC4CLK — — — IOC Y CLKIN OSC1 RB0 33 8 8 9 AN12 — C2IN1+ — — — PSMC1IN PSMC2IN PSMC3IN PSMC4IN CCP1(1) — — INT IOC Y — RB1 34 9 9 10 AN10 — C1IN3C2IN3C3IN3C4IN3- OPA2OUT — — — — — — IOC Y — RB2 35 10 10 11 AN8 — — OPA2IN- DAC3OUT1 — — — — — IOC Y CLKR RB3 36 11 11 12 AN9 — C1IN2C2IN2C3IN2- OPA2IN+ — — — CCP2(1) — — IOC Y — SS(1) — RB4 37 12 14 14 AN11 — C3IN1+ — — — — — — RB5 38 13 15 15 AN13 — C4IN2- — — T1G — CCP3(1) — IOC Y SDO(1) IOC Y RB6 39 14 16 16 — — C4IN1+ — — — — — — TX(1) SDA(1) IOC CK(1) SDI(1) Y ICSPCLK RB7 40 15 17 17 — — — — DAC1OUT2 DAC2OUT2DAC3OUT2DAC4OUT2 — — — RX(1) SCL(1) IOC DT(1) SCK(1) Y ICSPDAT RC0 15 30 32 34 — — — — — T1CKI T1OSO PSMC1A — — — IOC Y — — RC1 16 31 35 35 — — — — — T1OSI PSMC1B CCP2 — — IOC Y RC2 17 32 36 36 — — — — — — PSMC1C CCP1 — — IOC Y RC3 18 33 37 37 — — — — — — PSMC1D — — SCL SCK IOC Y — RC4 23 38 42 42 — — — — — — PSMC1E — — SDI SDA IOC Y — RC5 24 39 43 43 — — — — — — PSMC1F — — SDO IOC Y — RC6 25 40 44 44 — — — — — — PSMC2A — TX CK — IOC Y — RC7 26 1 1 1 — — — — — — PSMC2B — RX DT — IOC Y — RD0 19 34 38 38 — — — OPA3IN+ — — — — — — — Y — Note 1: Alternate pin function selected with the APFCON1 (Register 13-1) and APFCON2 (Register 13-2) registers.  2013-2015 Microchip Technology Inc. DS40001675C-page 11 PIC16(L)F1788/9 44-Pin QFN ADC Reference Comparator Op Amps 8-bit/ 5-bit DAC Timers PSMC CCP EUSART MSSP 35 39 39 AN21 — C1IN4C2IN4C3IN4C4IN4- OPA3OUT — — — — — — Basic 44-Pin TQFP 20 Pull-up 40-Pin UQFN RD1 Interrupt 40-Pin PDIP 40/44-PIN ALLOCATION TABLE (PIC16(L)F1789) (Continued) I/O TABLE 2: — Y — — RD2 21 36 40 40 — — — OPA3IN- DAC4OUT1 — — — — — — Y RD3 22 37 41 41 — — — — — — PSMC4A — — — — Y RD4 27 2 2 2 — — — — — — PSMC3F — — — — Y — RD5 28 3 3 3 — — — — — — PSMC3E — — — — Y — RD6 29 4 4 4 — — C3OUT — — — PSMC3D — — — — Y — RD7 30 5 5 5 — — C4OUT — — — PSMC3C — — — — Y — RE0 8 23 25 25 AN5 — — — — — PSMC4B CCP3 — — — Y — RE1 9 24 26 26 AN6 — — — — — PSMC3B — — — — Y — RE2 10 25 27 27 AN7 — — — — — PSMC3A — — — — Y — RE3 1 16 18 18 — — — — — — — — — — IOC Y MCLR VPP 7, 26 7, 28 7,8, 28 — — — — — — — — — — — — VDD 12, 6, 31 27 6, 29 6, 30 — — — — — — — — — — — — VSS VDD 11, 32 Vss Note 1: Alternate pin function selected with the APFCON1 (Register 13-1) and APFCON2 (Register 13-2) registers. DS40001675C-page 12  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Table of Contents 1.0 Device Overview ........................................................................................................................................................................... 14 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................... 25 3.0 Memory Organization .................................................................................................................................................................... 27 4.0 Device Configuration ..................................................................................................................................................................... 57 5.0 Resets ........................................................................................................................................................................................... 63 6.0 Oscillator Module (with Fail-Safe Clock Monitor) .......................................................................................................................... 71 7.0 Reference Clock Module ............................................................................................................................................................... 89 8.0 Interrupts ....................................................................................................................................................................................... 92 9.0 Power-Down Mode (Sleep) ......................................................................................................................................................... 107 10.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 111 11.0 Watchdog Timer (WDT) ............................................................................................................................................................ 112 12.0 Data EEPROM and Flash Program Memory Control ................................................................................................................ 116 13.0 I/O Ports .................................................................................................................................................................................... 130 14.0 Interrupt-On-Change ................................................................................................................................................................. 161 15.0 Fixed Voltage Reference (FVR) ................................................................................................................................................ 165 16.0 Temperature Indicator Module .................................................................................................................................................. 168 17.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 170 18.0 Operational Amplifier (OPA) Modules ....................................................................................................................................... 185 19.0 8-Bit Digital-to-Analog Converter (DAC) Module ....................................................................................................................... 189 20.0 5-bit Digital-to-Analog Converter (DAC2/3/4) Modules ............................................................................................................. 193 21.0 Comparator Module .................................................................................................................................................................. 197 22.0 Timer0 Module .......................................................................................................................................................................... 206 23.0 Timer1 Module with Gate Control ............................................................................................................................................. 209 24.0 Timer2 Module .......................................................................................................................................................................... 220 25.0 Capture/Compare/PWM Modules ............................................................................................................................................. 224 26.0 Programmable Switch Mode Control (PSMC) ........................................................................................................................... 232 27.0 Master Synchronous Serial Port (MSSP) Module ..................................................................................................................... 290 28.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ................................................................ 344 29.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 373 30.0 Instruction Set Summary ........................................................................................................................................................... 375 31.0 Electrical Specifications ............................................................................................................................................................ 389 32.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 422 33.0 Development Support ............................................................................................................................................................... 446 34.0 Packaging Information .............................................................................................................................................................. 450 Appendix A: Data Sheet Revision History ......................................................................................................................................... 470 The Microchip Website ..................................................................................................................................................................... 471 Customer Change Notification Service ............................................................................................................................................. 471 Customer Support ............................................................................................................................................................................. 471 Product Identification System ........................................................................................................................................................... 472  2013-2015 Microchip Technology Inc. DS40001675C-page 13 PIC16(L)F1788/9 1.0 DEVICE OVERVIEW The PIC16(L)F1788/9 are described within this data sheet. The block diagram of these devices are shown in Figure 1-1. The available peripherals are shown in Table 1-1, and the pin out descriptions are shown in Tables 1-2 and 1-3. PIC16(L)F1783 PIC16(L)F1784 PIC16(L)F1786 PIC16(L)F1787 PIC16(L)F1788 PIC16(L)F1789 DEVICE PERIPHERAL SUMMARY PIC16(L)F1782 TABLE 1-1: Analog-to-Digital Converter (ADC) ● ● ● ● ● ● ● Fixed Voltage Reference (FVR) ● ● ● ● ● ● ● Reference Clock Module ● ● ● ● ● ● ● Temperature Indicator ● ● ● ● ● ● ● CCP1 ● ● ● ● ● ● ● CCP2 ● ● ● ● ● ● ● ● ● ● ● ● Peripheral Capture/Compare/PWM (CCP/ECCP) Modules CCP3 Comparators C1 ● ● ● ● ● ● ● C2 ● ● ● ● ● ● ● C3 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● C4 Digital-to-Analog Converter (DAC) (8-bit DAC) D1 ● ● (5-bit DAC) D2 ● ● ● ● (5-bit DAC) D3 ● ● (5-bit DAC) D4 ● ● Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) EUSART ● ● ● ● ● ● ● MSSP ● ● ● ● ● ● ● Op Amp 1 ● ● ● ● ● ● ● Op Amp 2 ● ● ● ● ● ● Master Synchronous Serial Ports Op Amp ● Op Amp 3 ● ● ● Programmable Switch Mode Controller (PSMC) PSMC1 ● ● ● ● ● ● ● PSMC2 ● ● ● ● ● ● ● ● ● ● ● ● ● ● PSMC3 PSMC4 Timers  2013-2015 Microchip Technology Inc. Timer0 ● ● ● ● ● ● ● Timer1 ● ● ● ● ● ● ● Timer2 ● ● ● ● ● ● ● DS40001675C-page 14 PIC16(L)F1788/9 FIGURE 1-1: PIC16(L)F1788/9 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB CLKOUT Timing Generation HFINTOSC/ LFINTOSC Oscillator CLKIN PORTC CPU Figure 2-1 PORTD(1) MCLR PORTE Op Amps PSMCs Temp. Indicator Note 1: 2: DS40001675C-page 15 Timer0 ADC 12-Bit Timer1 FVR Timer2 DAC MSSP CCPs Comparators EUSART PIC16(L)F1789 only. See applicable chapters for more information on peripherals.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 1-2: PIC16(L)F1788 PINOUT DESCRIPTION Name RA0/AN0/C1IN0-/C2IN0-/ C3IN0-/C4IN0-/SS(1) Function RA0 RA2/AN2/C1IN0+/C2IN0+/ C3IN0+/C4IN0+/DAC1OUT1/ VREF-/DAC1VREF- RA5/AN4/C2OUT/OPA1IN-/ SS(1)/DAC2OUT1 TTL/ST CMOS General purpose I/O. — ADC Channel 0 input. C1IN0- AN — Comparator C1 negative input. C2IN0- AN — Comparator C2 negative input. C3IN0- AN — Comparator C3 negative input. C4IN0- AN — Comparator C4 negative input. ST — Slave Select input. RA1 TTL/ST CMOS General purpose I/O. AN1 AN — ADC Channel 1 input. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. C3IN1- AN — Comparator C3 negative input. C4IN1- AN — Comparator C4 negative input. OPA1OUT — AN Operational Amplifier 1 output. RA2 TTL/ST CMOS General purpose I/O. AN2 AN — ADC Channel 2 input. C1IN0+ AN — Comparator C1 positive input. C2IN0+ AN — Comparator C2 positive input. C3IN0+ AN — Comparator C3 positive input. C4IN0+ AN — Comparator C4 positive input. DAC1OUT1 — AN Digital-to-Analog Converter output. VREF- AN — ADC Negative Voltage Reference input. AN — Digital-to-Analog Converter negative reference. RA3 TTL/ST CMOS General purpose I/O. AN3 AN — ADC Channel 3 input. VREF+ AN — ADC Voltage Reference input. C1IN1+ AN — Comparator C1 positive input. DAC1VREF+ AN — Digital-to-Analog Converter positive reference. DAC2VREF+ AN — Digital-to-Analog Converter positive reference. DAC3VREF+ AN — Digital-to-Analog Converter positive reference. AN — Digital-to-Analog Converter positive reference. DAC4VREF+ RA4/C1OUT/OPA1IN+/T0CKI/ DAC4OUT1 Description AN DAC1VREFRA3/AN3/VREF+/C1IN1+/ DAC1VREF+/DAC2VREF+/ DAC3VREF+/DAC4VREF+ Output Type AN0 SS RA1/AN1/C1IN1-/C2IN1-/ C3IN1-/C4IN1-/OPA1OUT Input Type RA4 TTL/ST CMOS General purpose I/O. C1OUT — OPA1IN+ AN T0CKI ST — Timer0 clock input. DAC4OUT1 — AN Digital-to-Analog Converter output. RA5 AN4 CMOS Comparator C1 output. — Operational Amplifier 1 non-inverting input. TTL/ST CMOS General purpose I/O. AN — ADC Channel 4 input. C2OUT — OPA1IN- AN CMOS Comparator C2 output. — SS ST — Slave Select input. DAC2OUT1 — AN Digital-to-Analog Converter output. Operational Amplifier 1 inverting input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality.  2013-2015 Microchip Technology Inc. DS40001675C-page 16 PIC16(L)F1788/9 TABLE 1-2: PIC16(L)F1788 PINOUT DESCRIPTION (CONTINUED) Name RA6/C2OUT(1)/OSC2/ CLKOUT/VCAP RA7/PSMC1CLK/PSMC2CLK/ PSMC3CLK/PSMC4CLK/OSC1/CLKIN Function RA6 RB1/AN10/C1IN3-/C2IN3-/ C3IN3-/C4IN3-/OPA2OUT RB3/AN9/C1IN2-/C2IN2-/ C3IN2-/OPA2IN+/CCP2(1) Description TTL/ST CMOS General purpose I/O. — OSC2 — CLKOUT — VCAP Power CMOS Comparator C2 output. RA7 TTL/ST CMOS General purpose I/O. XTAL Crystal/Resonator (LP, XT, HS modes). CMOS FOSC/4 output. Power Filter capacitor for Voltage Regulator. PSMC1CLK ST — PSMC1 clock input. PSMC2CLK ST — PSMC2 clock input. PSMC3CLK ST — PSMC3 clock input. PSMC4CLK ST — PSMC4 clock input. OSC1 — XTAL ST — RB0 Crystal/Resonator (LP, XT, HS modes). External clock input (EC mode). TTL/ST CMOS General purpose I/O. AN12 AN — ADC Channel 12 input. C2IN1+ AN — Comparator C2 positive input. PSMC1IN ST — PSMC1 Event Trigger input. PSMC2IN ST — PSMC2 Event Trigger input. PSMC3IN ST — PSMC3 Event Trigger input. PSMC4IN ST — PSMC4 Event Trigger input. CCP1 ST INT ST RB1 CMOS Capture/Compare/PWM1. — External interrupt. TTL/ST CMOS General purpose I/O. AN10 AN — ADC Channel 10 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. C3IN3- AN — Comparator C3 negative input. C4IN3- AN — Comparator C4 negative input. — AN Operational Amplifier 2 output. OPA2OUT RB2/AN8/OPA2IN-/CLKR/ DAC3OUT1 Output Type C2OUT CLKIN RB0/AN12/C2IN1+/PSMC1IN/ PSMC2IN/PSMC3IN/PSMC4IN/ CCP1(1)/INT Input Type RB2 TTL/ST CMOS General purpose I/O. AN8 AN — ADC Channel 8 input. OPA2IN- AN — Operational Amplifier 2 inverting input. CLKR — DAC3OUT1 — RB3 CMOS Clock output. AN Digital-to-Analog Converter output. TTL/ST CMOS General purpose I/O. AN9 AN — ADC Channel 9 input. C1IN2- AN — Comparator C1 negative input. C2IN2- AN — Comparator C2 negative input. C3IN2- AN — Comparator C3 negative input. OPA2IN+ AN — Operational Amplifier 2 non-inverting input. CCP2 ST CMOS Capture/Compare/PWM2. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality. DS40001675C-page 17  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 1-2: PIC16(L)F1788 PINOUT DESCRIPTION (CONTINUED) Name RB4/AN11/C3IN1+/SS(1) Function RB4 RB6/C4IN1+/TX(1)/CK(1)/SDI(1)/ SDA(1)/ICSPCLK RC1/T1OSI/PSMC1B/CCP2 — ADC Channel 11 input. AN — Comparator C3 positive input. ST — Slave Select input. RB5 TTL/ST CMOS General purpose I/O. AN13 AN — ADC Channel 13 input. C4IN2- AN — Comparator C4 negative input. — Timer1 gate input. T1G ST CCP3 ST CMOS Capture/Compare/PWM3. SDO — CMOS SPI data output. C3OUT — CMOS Comparator C3 output. RB6 C4IN1+ TTL/ST CMOS General purpose I/O. AN — Comparator C4 positive input. TX — CMOS EUSART asynchronous transmit. CK ST CMOS EUSART synchronous clock. SDI ST — SPI data input. SDA I2C OD I2C data input/output. ST — Serial Programming Clock. RB7 TTL/ST CMOS General purpose I/O. DAC1OUT2 — AN Voltage Reference output. DAC2OUT2 — AN Voltage Reference output. DAC3OUT2 — AN Voltage Reference output. DAC4OUT2 — AN Voltage Reference output. RX ST — EUSART asynchronous input. DT ST CMOS EUSART synchronous data. SCK ST CMOS SPI clock. SCL I2C RC0 ST OD CMOS ICSP™ Data I/O. XTAL XTAL T1CKI ST — PSMC1A — RC1 I2C clock. TTL/ST CMOS General purpose I/O. T1OSO Timer1 Oscillator Connection. Timer1 clock input. CMOS PSMC1 output A. TTL/ST CMOS General purpose I/O. T1OSI XTAL PSMC1B — CMOS PSMC1 output B. ST CMOS Capture/Compare/PWM2. CCP2 RC2/PSMC1C/PSMC3B/CCP1 TTL/ST CMOS General purpose I/O. AN ICSPDAT RC0/T1OSO/T1CKI/PSMC1A Description AN11 ICSPCLK RB7/DAC1OUT2/DAC2OUT2/ DAC3OUT2/DAC4OUT2/RX(1)/ DT(1)/SCK(1)/SCL(1)/ICSPDAT Output Type C3IN1+ SS RB5/AN13/C4IN2-/T1G/CCP3(1) SDO(1)/C3OUT Input Type RC2 XTAL Timer1 Oscillator Connection. TTL/ST CMOS General purpose I/O. PSMC1C — CMOS PSMC1 output C. PSMC3B — CMOS PSMC3 output B. CCP1 ST CMOS Capture/Compare/PWM1. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality.  2013-2015 Microchip Technology Inc. DS40001675C-page 18 PIC16(L)F1788/9 TABLE 1-2: PIC16(L)F1788 PINOUT DESCRIPTION (CONTINUED) Name RC3/PSMC1D/PSMC4A/SCK/ SCL RC4/PSMC1E/PSMC4B/SDI/ SDA RC5/PSMC1F/PSMC3A/SDO Function RC3 RC7/C4OUT/PSMC2B/RX/DT Description TTL/ST CMOS General purpose I/O. — CMOS PSMC1 output D. PSMC4A — CMOS PSMC4 output A. SCK ST CMOS SPI clock. SCL I2C RC4 OD I2C clock. TTL/ST CMOS General purpose I/O. PSMC1E — CMOS PSMC1 output E. PSMC4B — CMOS PSMC4 output B. SDI ST — SPI data input. SDA I2C OD I2C data input/output. RC5 TTL/ST CMOS General purpose I/O. PSMC1F — CMOS PSMC1 output F. PSMC3A — CMOS PSMC3 output A. — CMOS SPI data output. RC6 TTL/ST CMOS General purpose I/O. PSMC2A — CMOS PSMC2 output A. TX — CMOS EUSART asynchronous transmit. CK ST CMOS EUSART synchronous clock. CCP3 ST CMOS Capture/Compare/PWM3. RC7 TTL/ST CMOS General purpose I/O. — CMOS Comparator C4 output. PSMC2B — CMOS PSMC2 output B. RX ST DT ST RE3 TTL/ST C4OUT RE3/MCLR/VPP Output Type PSMC1D SDO RC6/PSMC2A/TX/CK/CCP3 Input Type — EUSART asynchronous input. CMOS EUSART synchronous data. — General purpose input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality. DS40001675C-page 19  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 1-3: PIC16(L)F1789 PINOUT DESCRIPTION Name RA0/AN0/C1IN0-/C2IN0-/ C3IN0-/C4IN0-/SS(1) Function RA0 RA2/AN2/C1IN0+/C2IN0+/ C3IN0+/C4IN0+/DAC1OUT1/ VREF-/DAC1VREF- ADC Channel 0 input. C1IN0- AN — Comparator C1 negative input. C2IN0- AN — Comparator C2 negative input. C3IN0- AN — Comparator C3 negative input. C4IN0- AN — Comparator C4 negative input. ST — Slave Select input. RA1 TTL/ST CMOS General purpose I/O. AN1 AN — ADC Channel 1 input. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. C3IN1- AN — Comparator C3 negative input. C4IN1- AN — Comparator C4 negative input. OPA1OUT — AN Operational Amplifier 1 output. RA2 TTL/ST CMOS General purpose I/O. AN2 AN — ADC Channel 2 input. C1IN0+ AN — Comparator C1 positive input. C2IN0+ AN — Comparator C2 positive input. C3IN0+ AN — Comparator C3 positive input. C4IN0+ AN — Comparator C4 positive input. DAC1OUT1 — AN Digital-to-Analog Converter output. VREF- AN — ADC Negative Voltage Reference input. AN — Digital-to-Analog Converter negative reference. RA3 TTL/ST CMOS General purpose I/O. AN3 AN — ADC Channel 3 input. VREF+ AN — ADC Voltage Reference input. C1IN1+ AN — Comparator C1 positive input. DAC1VREF+ AN — Digital-to-Analog Converter positive reference. DAC2VREF+ AN — Digital-to-Analog Converter positive reference. DAC3VREF+ AN — Digital-to-Analog Converter positive reference. AN — Digital-to-Analog Converter positive reference. RA4 TTL/ST CMOS General purpose I/O. C1OUT — OPA1IN+ AN — Operational Amplifier 1 non-inverting input. ST — Timer0 clock input. T0CKI RA5/AN4/C2OUT/OPA1IN-/ SS(1)/DAC2OUT1 TTL/ST CMOS General purpose I/O. — DAC4VREF+ RA4/C1OUT/OPA1IN+/T0CKI Description AN DAC1VREFRA3/AN3/VREF+/C1IN1+/ DAC1VREF+/DAC2VREF+/ DAC3VREF+/DAC4VREF+ Output Type AN0 SS RA1/AN1/C1IN1-/C2IN1-/ C3IN1-/C4IN1-/OPA1OUT Input Type RA5 CMOS Comparator C1 output. TTL/ST CMOS General purpose I/O. AN4 AN C2OUT — — ADC Channel 4 input. OPA1IN- AN — SS ST — Slave Select input. DAC2OUT1 — AN Digital-to-Analog Converter output. CMOS Comparator C2 output. Operational Amplifier 1 inverting input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality.  2013-2015 Microchip Technology Inc. DS40001675C-page 20 PIC16(L)F1788/9 TABLE 1-3: PIC16(L)F1789 PINOUT DESCRIPTION (CONTINUED) Name RA6/C2OUT(1)/OSC2/ CLKOUT/VCAP RA7/PSMC1CLK/PSMC2CLK/ PSMC3CLK/PSMC4CLK/OSC1/CLKIN Function RA6 RB1/AN10/C1IN3-/C2IN3-/ C3IN3-/C4IN3-/OPA2OUT RB3/AN9/C1IN2-/C2IN2-/ C3IN2-/OPA2IN+/CCP2(1) Description TTL/ST CMOS General purpose I/O. — OSC2 — CLKOUT — VCAP Power CMOS Comparator C2 output. RA7 TTL/ST CMOS General purpose I/O. XTAL Crystal/Resonator (LP, XT, HS modes). CMOS FOSC/4 output. Power Filter capacitor for Voltage Regulator. PSMC1CLK ST — PSMC1 clock input. PSMC2CLK ST — PSMC2 clock input. PSMC3CLK ST — PSMC3 clock input. PSMC4CLK ST — PSMC4 clock input. OSC1 — XTAL ST — RB0 Crystal/Resonator (LP, XT, HS modes). External clock input (EC mode). TTL/ST CMOS General purpose I/O. AN12 AN — ADC Channel 12 input. C2IN1+ AN — Comparator C2 positive input. PSMC1IN ST — PSMC1 Event Trigger input. PSMC2IN ST — PSMC2 Event Trigger input. PSMC3IN ST — PSMC3 Event Trigger input. PSMC4IN ST — PSMC4 Event Trigger input. CCP1 ST INT ST RB1 CMOS Capture/Compare/PWM1. — External interrupt. TTL/ST CMOS General purpose I/O. AN10 AN — ADC Channel 10 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. C3IN3- AN — Comparator C3 negative input. C4IN3- AN — Comparator C4 negative input. — AN Operational Amplifier 2 output. OPA2OUT RB2/AN8/OPA2IN-/CLKR/ DAC3OUT1 Output Type C2OUT CLKIN RB0/AN12/C2IN1+/PSMC1IN/ PSMC2IN/PSMC3IN/PSMC4IN/ CCP1(1)/INT Input Type RB2 TTL/ST CMOS General purpose I/O. AN8 AN — ADC Channel 8 input. OPA2IN- AN — Operational Amplifier 2 inverting input. CLKR — DAC3OUT1 — RB3 CMOS Clock output. AN Digital-to-Analog Converter output. TTL/ST CMOS General purpose I/O. AN9 AN — ADC Channel 9 input. C1IN2- AN — Comparator C1 negative input. C2IN2- AN — Comparator C2 negative input. C3IN2- AN — Comparator C3 negative input. OPA2IN+ AN — Operational Amplifier 2 non-inverting input. CCP2 ST CMOS Capture/Compare/PWM2. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality. DS40001675C-page 21  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 1-3: PIC16(L)F1789 PINOUT DESCRIPTION (CONTINUED) Name RB4/AN11/C3IN1+/SS(1) Function RB4 RB7/DAC1OUT2/DAC2OUT2/ DAC3OUT2/DAC4OUT2/RX(1)/ DT(1)/SCK(1)/SCL(1)/ICSPDAT RC1/T1OSI/PSMC1B/CCP2 — ADC Channel 11 input. AN — Comparator C3 positive input. ST — Slave Select input. RB5 AN13 AN — ADC Channel 13 input. AN — Comparator C4 negative input. T1G ST — Timer1 gate input. CCP3 ST CMOS Capture/Compare/PWM3. — CMOS SPI data output. RB6 TTL/ST CMOS General purpose I/O. C4IN1+ AN TX — CMOS EUSART asynchronous transmit. CMOS EUSART synchronous clock. — Comparator C4 positive input. CK ST SDI ST — SPI data input. SDA I2C OD I2C data input/output. ICSPCLK ST — Serial Programming Clock. RB7 TTL/ST CMOS General purpose I/O. DAC1OUT2 — AN Voltage Reference output. DAC2OUT2 — AN Voltage Reference output. DAC3OUT2 — AN Voltage Reference output. DAC4OUT2 — AN Voltage Reference output. RX ST — EUSART asynchronous input. DT ST CMOS EUSART synchronous data. SCK ST CMOS SPI clock. SCL 2 RC0 I C ST XTAL T1CKI ST PSMC1A — RC1 OD I2C clock. CMOS ICSP™ Data I/O. TTL/ST CMOS General purpose I/O. T1OSO XTAL — Timer1 Oscillator Connection. Timer1 clock input. CMOS PSMC1 output A. TTL/ST CMOS General purpose I/O. XTAL XTAL Timer1 Oscillator Connection. PSMC1B — CMOS PSMC1 output B. CCP2 ST CMOS Capture/Compare/PWM2. RC2 PSMC1C CCP1 RC3/PSMC1D/SCK/SCL TTL/ST CMOS General purpose I/O. C4IN2- T1OSI RC2/PSMC1C/CCP1 TTL/ST CMOS General purpose I/O. AN ICSPDAT RC0/T1OSO/T1CKI/PSMC1A Description AN11 SDO RB6/C4IN1+/TX(1)/CK(1)/SDI(1)/ SDA(1)/ICSPCLK Output Type C3IN1+ SS RB5/AN13/C4IN2-/T1G/CCP3(1) SDO(1) Input Type RC3 TTL/ST CMOS General purpose I/O. — CMOS PSMC1 output C. ST CMOS Capture/Compare/PWM1. TTL/ST CMOS General purpose I/O. PSMC1D — CMOS PSMC1 output D. SCK ST CMOS SPI clock. SCL I2C OD I2C clock. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality.  2013-2015 Microchip Technology Inc. DS40001675C-page 22 PIC16(L)F1788/9 TABLE 1-3: PIC16(L)F1789 PINOUT DESCRIPTION (CONTINUED) Name RC4/PSMC1E/SDI/SDA RC5/PSMC1F/SDO RC6/PSMC2A/TX/CK Function RC4 RD2/OPA3IN-/DAC4OUT1 RD3/PSMC4A — — SPI data input. SDA I2C OD I2C data input/output. RC5 — CMOS PSMC1 output F. — CMOS SPI data output. RC6 RD7/C4OUT/PSMC3C RE0/AN5/CCP3/PSMC4B TTL/ST CMOS General purpose I/O. — CMOS PSMC2 output A. TX — CMOS EUSART asynchronous transmit. CK ST CMOS EUSART synchronous clock. RC7 TTL/ST CMOS General purpose I/O. — RX ST DT ST RD0 RD1 CMOS PSMC2 output B. — EUSART asynchronous input. CMOS EUSART synchronous data. TTL/ST CMOS General purpose I/O. AN — Operational Amplifier 3 non-inverting input. TTL/ST CMOS General purpose I/O. AN21 AN — ADC Channel 21 input. C1IN4- AN — Comparator C4 negative input. C2IN4- AN — Comparator C4 negative input. C3IN4- AN — Comparator C4 negative input. C4IN4- AN — Comparator C4 negative input. OPA3OUT — AN Operational Amplifier 3 output. RD2 TTL/ST CMOS General purpose I/O. OPA3IN- AN — Operational Amplifier 3 inverting input. DAC4OUT1 — AN Digital-to-Analog Converter output. RD3 RD4 RD5 PSMC3E RD6/C3OUT/PSMC3D TTL/ST CMOS General purpose I/O. SDO PSMC3F RD5/PSMC3E CMOS PSMC1 output E. PSMC1F PSMC4A RD4/PSMC3F TTL/ST CMOS General purpose I/O. ST OPA3IN+ RD1/AN21/C1IN4-/C2IN4-/ C3IN4-/C4IN4-/OPA3OUT Description SDI PSMC2B RD0/OPA3IN+ Output Type PSMC1E PSMC2A RC7/PSMC2B/RX/DT Input Type RD6 TTL/ST CMOS General purpose I/O. — CMOS PSMC4 output A. TTL/ST CMOS General purpose I/O. — CMOS PSMC3 output F. TTL/ST CMOS General purpose I/O. — CMOS PSMC3 output E. TTL/ST CMOS General purpose I/O. C3OUT — CMOS Comparator C3 output. PSMC3D — CMOS PSMC3 output D. RD7 TTL/ST CMOS General purpose I/O. C4OUT — CMOS Comparator C4 output. PSMC3C — CMOS PSMC3 output C. RE0 TTL/ST — General purpose input. AN5 AN — ADC Channel 5 input. CCP3 ST CMOS Capture/Compare/PWM3. PSMC4B — CMOS PSMC4 output B. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality. DS40001675C-page 23  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 1-3: PIC16(L)F1789 PINOUT DESCRIPTION (CONTINUED) Name RE1/AN6/PSMC3B RE2/AN7/PSMC3A Function RE1 Input Type AN6 AN — RE2 Description TTL/ST CMOS General purpose I/O. PSMC3B AN7 Output Type — ADC Channel 6 input. CMOS PSMC3 output B. TTL/ST CMOS General purpose I/O. AN — ADC Channel 7 input. PSMC3A — RE3 TTL/ST — MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. RE3/MCLR/VPP CMOS PSMC3 output A. General purpose input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open-Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two locations via software. See Register 13-1. 2: All pins have interrupt-on-change functionality.  2013-2015 Microchip Technology Inc. DS40001675C-page 24 PIC16(L)F1788/9 2.0 Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and FIGURE 2-1: • • • • Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Direct Addr 7 5 Indirect Addr 12 12 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W reg Internal Oscillator Block VDD  2013-2015 Microchip Technology Inc. VSS DS40001675C-page 25 PIC16(L)F1788/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See 8.5 “Automatic Context Saving”, for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See Section 3.5 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.6 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 30.0 “Instruction Set Summary” for more details. DS40001675C-page 26  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1788/9 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1). Note 1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section 12.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16(L)F1788/9  2013-2015 Microchip Technology Inc. Program Memory Space (Words) Last Program Memory Address 16,384 3FFFh DS40001675C-page 27 PIC16(L)F1788/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1788/9 PC CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE Stack Level 0 Stack Level 1 EXAMPLE 3-1: 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 Page 4 17FFh 1800h 1FFFh 2000h constants BRW RETLW RETLW RETLW RETLW Rollover to Page 0 Rollover to Page 7 3FFFh 4000h 7FFFh DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.1.1.2 Page 7 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. Reset Vector Page 3 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 Stack Level 15 On-chip Program Memory 3.1.1 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The high directive will set bit if a label points to a location in program memory. DS40001675C-page 28  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants DW DATA0 ;First constant DW DATA1 ;Second constant DW DATA2 DW DATA3 my_function ;… LOTS OF CODE… MOVLW DATA_INDEX ADDLW LOW constants MOVWF FSR1L MOVLW HIGH constants ;MSb is set automatically MOVWF FSR1H BTFSC STATUS,C ;carry from ADDLW? INCF FSR1H,f ;yes MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W  2013-2015 Microchip Technology Inc. DS40001675C-page 29 PIC16(L)F1788/9 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.6 “Indirect Addressing” for more information. Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. DS40001675C-page 30 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed information, see Table 3-11. TABLE 3-2: CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. 3.3 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 30.0 “Instruction Set Summary”). Note: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. Register Definitions: Status REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.  2013-2015 Microchip Technology Inc. DS40001675C-page 31 PIC16(L)F1788/9 3.3.1 SPECIAL FUNCTION REGISTER The Special Function Registers (SFR) are registers used by the application to control the desired operation of peripheral functions in the device. The SFR occupies the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of each peripheral are described in the corresponding peripheral chapters of this data sheet. 3.3.2 GENERAL PURPOSE RAM There are up to 80 bytes of General Purpose Registers (GPR) in each data memory bank. The GPR occupies the space immediately after the SFR of selected data memory banks. The number of banks selected depends on the total amount of GPR space available in the device. 3.3.2.1 FIGURE 3-2: 7-bit Bank Offset Memory Region 00h 0Bh 0Ch Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.6.2 “Linear Data Memory” for more information. 3.3.3 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh DS40001675C-page 32  2013-2015 Microchip Technology Inc. DEVICE MEMORY MAPS The memory maps for Bank 0 through Bank 31 are shown in the tables in this section. TABLE 3-3: PIC16(L)F1788 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) BANK 4 200h Core Registers (Table 3-2) BANK 5 280h Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h PORTA PORTB PORTC — PORTE PIR1 PIR2 PIR3 PIR4 TMR0 TMR1L 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h TRISA TRISB TRISC — TRISE PIE1 PIE2 PIE3 PIE4 OPTION_REG PCON 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h LATA LATB LATC — — CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA ANSELB ANSELC — — EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA WPUB WPUC — WPUE SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA ODCONB ODCONC — — CCPR1L CCPR1H CCP1CON — — — 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA SLRCONB SLRCONC — — CCPR3L CCPR3H CCP3CON — — — 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA INLVLB INLVLC — INLVLE IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh TMR1H T1CON T1GCON TMR2 PR2 T2CON — — 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh FVRCON DAC1CON0 DAC1CON1 CM4CON0 CM4CON1 APFCON2 APFCON1 CM3CON0 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) — RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 — — — — — — — 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR2L CCPR2H CCP2CON — — — — 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — — — — — — — — 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF — — — — — 01Fh 020h — 09Fh 0A0h ADCON2 11Fh 120h CM3CON1 19Fh 1A0h BAUD1CON 21Fh 220h — 29Fh 2A0h — 31Fh 320h — 39Fh 3A0h —  2013-2015 Microchip Technology Inc. General Purpose Register 80 Bytes 06Fh 070h 0EFh 0F0h Common RAM 70h – 7Fh 07Fh 1: 16Fh 170h Accesses 70h – 7Fh 0FFh Legend: Note General Purpose Register 80 Bytes General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h – 7Fh 17Fh = Unimplemented data memory locations, read as ‘0’. PIC16F1788 only. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh General Purpose Register 80 Bytes 27Fh 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh General Purpose Register 80 Bytes Accesses 70h – 7Fh 2FFh General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h – 7Fh 37Fh Accesses 70h – 7Fh 3FFh PIC16(L)F1788/9 DS40001675CDS40001579EDS40001637C-page 33 3.3.4  2013-2015 Microchip Technology Inc. TABLE 3-4: PIC16(L)F1789 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) BANK 4 200h Core Registers (Table 3-2) BANK 5 280h Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h PORTA PORTB PORTC PORTD PORTE PIR1 PIR2 PIR3 PIR4 TMR0 TMR1L 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PIE3 PIE4 OPTION_REG PCON 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h LATA LATB LATC LATD LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA ANSELB ANSELC ANSELD ANSELE EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA WPUB WPUC WPUD WPUE SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA ODCONB ODCONC ODCOND ODCONE CCPR1L CCPR1H CCP1CON — — — 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA SLRCONB SLRCONC SLRCOND SLRCONE CCPR3L CCPR3H CCP3CON — — — 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA INLVLB INLVLC INLVLD INLVLE IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh TMR1H T1CON T1GCON TMR2 PR2 T2CON — — 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh FVRCON DAC1CON0 DAC1CON1 CM4CON0 CM4CON1 APFCON2 APFCON1 CM3CON0 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) — RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 — — — — — — — 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR2L CCPR2H CCP2CON — — — — 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — — — — — — — — 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF — — — IOCEP IOCEN 01Fh 020h — 09Fh 0A0h ADCON2 11Fh 120h CM3CON1 19Fh 1A0h BAUD1CON 21Fh 220h — 29Fh 2A0h — 31Fh 320h — 39Fh 3A0h IOCEF 06Fh 070h 0EFh 0F0h Common RAM 70h – 7Fh 07Fh DS40001675C-page 34 Note 1: 16Fh 170h Accesses 70h – 7Fh 0FFh Legend: General Purpose Register 80 Bytes General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h – 7Fh 17Fh = Unimplemented data memory locations, read as ‘0’. PIC16F1789 only. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh General Purpose Register 80 Bytes 27Fh 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh General Purpose Register 80 Bytes Accesses 70h – 7Fh 2FFh General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h – 7Fh 37Fh Accesses 70h – 7Fh 3FFh PIC16(L)F1788/9 General Purpose Register 80 Bytes  2013-2015 Microchip Technology Inc. TABLE 3-5: PIC16(L)F1788/9 MEMORY MAP (BANKS 8-28) BANK 8 400h 40Bh 40Ch 41Fh 420h 46Fh 470h 47Fh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) BANK 9 480h 48Bh 48Ch 49Fh 4A0h 4EFh 4F0h 4FFh BANK 16 800h 80Bh 80Ch 81Fh 820h 86Fh 870h 87Fh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) DS40001675C-page 35 C1Fh C20h Unimplemented Read as ‘0’ General Purpose Register 80 Bytes C6Fh C70h C7Fh Legend: Common RAM (Accesses 70h – 7Fh) General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) 50Bh 50Ch 51Fh 520h 56Fh 570h 57Fh 880h 88Bh 88Ch 89Fh 8A0h 8EFh 8F0h 8FFh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) C8Bh C8Ch C9Fh CA0h CBFh CC0h CEFh CF0h CFFh Core Registers (Table 3-2) Unimplemented Read as ‘0’ 900h 90Bh 90Ch 91Fh 920h 96Fh 970h 97Fh Common RAM (Accesses 70h – 7Fh) General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) 58Bh 58Ch 59Fh 5A0h 5EFh 5F0h 5FFh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) D0Bh D0Ch Core Registers (Table 3-2) 980h 98Bh 98Ch 99Fh 9A0h 9EFh 9F0h 9FFh D7Fh Common RAM (Accesses 70h – 7Fh) = Unimplemented data memory locations, read as ‘0’ See Table 3-7 General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) 600h 60Bh 60Ch 61Fh 620h 66Fh 670h 67Fh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) D8Bh D8Ch Core Registers (Table 3-2) A00h A0Bh A0Ch A1Fh A20h A6Fh A70h A7Fh DFFh Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) 680h 68Bh 68Ch 69Fh 6A0h 6EFh 6F0h 6FFh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) E0Bh E0Ch Core Registers (Table 3-2) A80h A8Bh A8Ch A9Fh AA0h AEFh AF0h AFFh E7Fh Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) 700h 70Bh 70Ch 71Fh 720h 76Fh 770h 77Fh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) E8Bh E8Ch Core Registers (Table 3-2) B00h B0Bh B0Ch B1Fh B20h B6Fh B70h B7Fh EFFh Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) 780h 78Bh 78Ch 79Fh 7A0h 7EFh 7F0h 7FFh Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) F0Bh F0Ch Core Registers (Table 3-2) B80h B8Bh B8Ch B9Fh BA0h BEFh BF0h BFFh F7Fh Common RAM (Accesses 70h – 7Fh) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) Core Registers (Table 3-2) Unimplemented Read as ‘0’ General Purpose Register 80 Bytes Common RAM (Accesses 70h – 7Fh) BANK 31 F80h F8Bh F8Ch See Figure 3-10 F6Fh F70h Core Registers (Table 3-2) BANK 23 BANK 30 F00h See Figure 3-9 EEFh EF0h Core Registers (Table 3-2) BANK 15 BANK 22 BANK 29 E80h Unimplemented Read as ‘0’ E6Fh E70h Core Registers (Table 3-2) BANK 14 BANK 21 BANK 28 E00h Unimplemented Read as ‘0’ DEFh DF0h Core Registers (Table 3-2) BANK 13 BANK 20 BANK 27 D80h Unimplemented Read as ‘0’ D6Fh D70h Core Registers (Table 3-2) BANK 12 BANK 19 BANK 26 D00h General Purpose Register 32 Bytes Unimplemented Read as ‘0’ See Table 3-6 580h BANK 18 BANK 25 C80h Core Registers (Table 3-2) BANK 11 Core Registers (Table 3-2) See Figure 3-8 FEFh FF0h FFFh Common RAM (Accesses 70h – 7Fh) PIC16(L)F1788/9 C0Bh C0Ch Core Registers (Table 3-2) Unimplemented Read as ‘0’ 500h BANK 17 BANK 24 C00h Core Registers (Table 3-2) BANK 10 PIC16(L)F1788/9 TABLE 3-6: PIC16(L)F1788/9 MEMORY MAP (BANK 10 DETAILS) TABLE 3-8: PIC16(L)F1788/9 MEMORY MAP (BANK 31 DETAILS) BANK 31 BANK 10 F8Ch Unimplemented Read as ‘0’ FE3h 50Ch 510h 511h 512h 513h 514h OPA1CON — OPA2CON — OPA3CON(1) — — — 515h 516h 517h 518h 519h 51Ah 51Bh CLKRCON Unimplemented Read as ‘0’ FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Unimplemented Read as ‘0’ STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’. 51Fh = Unimplemented data memory locations, read as ‘0 Legend: Note 1: TABLE 3-7: PIC16(L)F1789 only. PIC16(L)F1788/9 MEMORY MAP (BANK 11 DETAILS) BANK 11 58Ch Unimplemented Read as ‘0’ 590h 591h 592h 593h 594h 595h 596h 597h DAC2CON0 DAC2CON1 DAC3CON0 DAC3CON1 DAC4CON0 DAC4CON1 Unimplemented Read as ‘0’ 59Fh Legend: = Unimplemented data memory locations, read as ‘0’. DS40001675C-page 36  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 3-9: PIC16(L)F1788/9 MEMORY MAP (BANK 29 DETAILS) BANK 29 E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h EA1h EA2h EA3h EA4h EA5h EA6h EA7h EA8h EA9h EAAh EABh EACh EADh EAEh EAFh EB0h Legend: PSMC1CON PSMC1MDL PSMC1SYNC PSMC1CLK PSMC1OEN PSMC1POL PSMC1BLNK PSMC1REBS PSMC1FEBS PSMC1PHS PSMC1DCS PSMC1PRS PSMC1ASDC PSMC1ASDL PSMC1ASDS PSMC1INT PSMC1PHL PSMC1PHH PSMC1DCL PSMC1DCH PSMC1PRL PSMC1PRH PSMC1TMRL PSMC1TMRH PSMC1DBR PSMC1DBF PSMC1BLKR PSMC1BLKF PSMC1FFA PSMC1STR0 PSMC1STR1 — BANK 29 EB1h EB2h EB3h EB4h EB5h EB6h EB7h EB8h EB9h EBAh EBBh EBCh EBDh EBEh EBFh EC0h EC1h EC2h EC3h EC4h EC5h EC6h EC7h EC8h EC9h ECAh ECBh ECCh ECDh ECEh ECFh ED0h PSMC2CON PSMC2MDL PSMC2SYNC PSMC2CLK PSMC2OEN PSMC2POL PSMC2BLNK PSMC2REBS PSMC2FEBS PSMC2PHS PSMC2DCS PSMC2PRS PSMC2ASDC PSMC2ASDL PSMC2ASDS PSMC2INT PSMC2PHL PSMC2PHH PSMC2DCL PSMC2DCH PSMC2PRL PSMC2PRH PSMC2TMRL PSMC2TMRH PSMC2DBR PSMC2DBF PSMC2BLKR PSMC2BLKF PSMC2FFA PSMC2STR0 PSMC2STR1 — BANK 29 ED1h ED2h ED3h ED4h ED5h ED6h ED7h ED8h ED9h EDAh EDBh EDCh EDDh EDEh EDFh EE0h EE1h EE2h EE3h EE4h EE5h EE6h EE7h EE8h EE9h EEAh EEBh EECh EEDh EEEh EEFh PSMC3CON PSMC3MDL PSMC3SYNC PSMC3CLK PSMC3OEN PSMC3POL PSMC3BLNK PSMC3REBS PSMC3FEBS PSMC3PHS PSMC3DCS PSMC3PRS PSMC3ASDC PSMC3ASDL PSMC3ASDS PSMC3INT PSMC3PHL PSMC3PHH PSMC3DCL PSMC3DCH PSMC3PRL PSMC3PRH PSMC3TMRL PSMC3TMRH PSMC3DBR PSMC3DBF PSMC3BLKR PSMC3BLKF PSMC3FFA PSMC3STR0 PSMC3STR1 = Unimplemented data memory locations, read as ‘0’.  2013-2015 Microchip Technology Inc. DS40001675C-page 37 PIC16(L)F1788/9 TABLE 3-10: PIC16(L)F1788/9 MEMORY MAP (BANK 30 DETAILS) BANK 30 F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F6Fh Legend: PSMC4CON PSMC4MDL PSMC4SYNC PSMC4CLK PSMC4OEN PSMC4POL PSMC4BLNK PSMC4REBS PSMC4FEBS PSMC4PHS PSMC4DCS PSMC4PRS PSMC4ASDC PSMC4ASDL PSMC4ASDS PSMC4INT PSMC4PHL PSMC4PHH PSMC4DCL PSMC4DCH PSMC4PRL PSMC4PRH PSMC4TMRL PSMC4TMRH PSMC4DBR PSMC4DBF PSMC4BLKR PSMC4BLKF PSMC4FFA PSMC4STR0 PSMC4STR1 Unimplemented Read as ‘0’ = Unimplemented data memory locations, read as ‘0’. DS40001675C-page 38  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 3.3.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-11 can be addressed from any Bank. TABLE 3-11: Addr Name CORE FUNCTION REGISTERS SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 ---1 1000 ---q quuu x03h or STATUS x83h — — — TO PD Z DC C x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 0000 0000 0000 x08h or BSR x88h — x09h or WREG x89h — BSR4 BSR3 BSR2 BSR1 BSR0 Working Register x0Ah or PCLATH x8Ah — x0Bh or INTCON x8Bh GIE Legend: — Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’.  2013-2015 Microchip Technology Inc. DS40001675C-page 39 PIC16(L)F1788/9 TABLE 3-12: Addr SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh PORTD(3) PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu — — — — RE3 RE2(3) RE1(3) RE0(3) ---- xxxx ---- uuuu TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 0000 0-00 0000 0-00 — — — CCP3IF — — — — ---0 ---- 0000 0000 PSMC4TIF PSMC3TIF PSMC2TIF PSMC1TIF PSMC4SIF PSMC3SIF PSMC2SIF 010h PORTE 011h PIR1 012h PIR2 13h PIR3 014h PIR4 PSMC1SIF 0000 0000 0000 0000 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL 016h TMR2 Holding Register for the Least Significant Byte of the 16-bit TMR2 Register 017h PR2 Holding Register for the Most Significant Byte of the 16-bit TMR2 Register 018h T2CON 01Dh to — 01Fh — T2OUTPS — TMR1ON T1GSS 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR2ON T2CKPS Unimplemented -000 0000 -000 0000 — — Bank 1 08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111 08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111 08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111 08Fh TRISD(3) PORTD Data Direction Register 090h TRISE 1111 1111 1111 1111 — —(2) TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 ---- 1111 RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 C1IE EEIE BCL1IE C4IE C3IE CCP2IE 0000 0-00 0000 0-00 — — CCP3IE — — — — ---0 ---- 0000 0000 PSMC3TIE PSMC2TIE PSMC1TIE PSMC4SIE PSMC3SIE PSMC2SIE — — — 091h PIE1 TMR1GIE ADIE 092h PIE2 OSFIE C2IE 093h PIE3 — 094h PIE4 PSMC4TIE 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA 096h PCON STKOVF STKUNF — RWDT RMCLR 097h WDTCON — — 098h OSCTUNE — — 099h OSCCON SPLLEN 09Ah OSCSTAT T1OSCR 09Bh ADRESL A/D Result Register Low 09Ch ADRESH A/D Result Register High 09Dh ADCON0 ADRMD 09Eh ADCON1 ADFM 09Fh ADCON2 Legend: Note 1: 2: 3: 4: PS RI POR WDTPS 1111 1111 1111 1111 BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 TUN IRCF PLLR PSMC1SIE 0000 0000 0000 0000 OSTS HFIOFR --00 0000 --00 0000 — HFIOFL SCS MFIOFR LFIOFR HFIOFS 0011 1-00 0011 1-00 00q0 --00 qqqq --0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CHS ADCS TRIGSEL GO/DONE — ADNREF ADON ADPREF CHSN 0000 0000 0000 0000 0000 -000 0000 -000 000- -000 000- -000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only. DS40001675C-page 40  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 3-12: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Fh LATD(3) PORTD Data Latch xxxx xxxx uuuu uuuu 110h LATE(3) — — — — — LATE2 LATE1 LATE0 ---- -111 ---- -111 111h CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT C2ZLF C2SP 114h CM2CON1 C2INTP C2INTN 115h CMOUT — — — — MC4OUT(3) MC3OUT MC2OUT MC1OUT ---- 0000 ---- 0000 116h BORCON SBOREN BORFS — — — — — BORRDY 1x-- ---q uu-- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR 118h DAC1CON0 DAC1EN --- DAC1OE1 DAC1OE2 DAC1PSS 119h DAC1CON1 C1PCH C2OE C2POL C1NCH C2PCH C2HYS 0000 0000 0000 0000 C2SYNC C2NCH 0000 0000 0000 0000 ADFVR --- DAC1NSS C4HYS C4SYNC DAC1R 11Ah CM4CON0 C4ON C4OUT 11Bh CM4CON1 C4INTP C4INTN C4OE C4POL 0000 0100 0000 0100 0q00 0000 0q00 0000 0-00 00-0 0-00 00-0 0000 0000 0000 0000 C4ZLF C4SP C4PCH C4NCH 0000 0100 0000 0100 0000 0000 0000 0000 11Ch APFCON2 — — — — — 11Dh APFCON1 C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 0000 0000 0000 0000 11Eh CM3CON0 C3ON C3OUT C3OE C3POL C3ZLF C3SP C3HYS C3SYNC 0000 0100 0000 0100 C3INTP C3INTN 11Fh CM3CON1 SSSEL C3PCH CCP3SEL C3NCH ---- -000 ---- -000 0000 0000 0000 0000 Bank 3 18Ch ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1-11 1111 1-11 1111 18Dh ANSELB — ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 -111 1111 -111 1111 18Eh ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 ANSC1 ANSC0 1111 1111 1111 1111 — — — — — ANSD2 ANSD1 ANSD0 ---- -111 ---- -111 — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111 18Fh ANSELD(3) 190h ANSELE(3) 191h EEADRL 192h EEADRH 193h EEDATL 194h EEDATH 195h EECON1 196h EECON2 197h VREGCON(4) EEPROM / Program Memory Address Register Low Byte —(2) 0000 0000 0000 0000 EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000 EEPROM / Program Memory Read Data Register Low Byte — — EEPGD CFGS xxxx xxxx uuuu uuuu EEPROM / Program Memory Read Data Register High Byte LWLO FREE --xx xxxx --uu uuuu WRERR WREN WR RD — — VREGPM Reserved EEPROM / Program Memory Control Register 2 — — — 198h — Unimplemented 199h RCREG EUSART Receive Data Register 19Ah TXREG EUSART Transmit Data Register 0000 x000 0000 q000 0000 0000 0000 0000 — ---- --01 ---- --01 — — 0000 0000 0000 0000 0000 0000 0000 0000 19Bh SPBRG BRG 19Ch SPBRGH BRG 0000 0000 0000 0000 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 19Fh BAUDCON Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only.  2013-2015 Microchip Technology Inc. DS40001675C-page 41 PIC16(L)F1788/9 TABLE 3-12: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 20Ch WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 1111 1111 1111 1111 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111 20Eh WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 20Fh WPUD(3) WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 1111 1111 1111 1111 — — — — WPUE3 WPUE2(3) WPUE1(3) WPUE0(3) ---- 1111 ---- 1111 210h WPUE 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 212h SSP1ADD xxxx xxxx uuuu uuuu ADD 213h SSP1MSK 0000 0000 0000 0000 MSK 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — — 21Fh S R/W UA BF SSPM 0000 0000 0000 0000 0000 0000 0000 0000 Unimplemented — — Bank 5 28Ch ODCONA Open-Drain Control for PORTA 0000 0000 0000 0000 28Dh ODCONB Open-Drain Control for PORTB 0000 0000 0000 0000 28Eh ODCONC Open-Drain Control for PORTC 0000 0000 0000 0000 28Fh ODCOND(3) Open-Drain Control for PORTD 290h ODCONE(3) — — 0000 0000 0000 0000 — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON 294h — — 297h — — — ODE2 ODE1 ODE0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC1B CCP1M --00 0000 --00 0000 Unimplemented — 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) 29Ah CCP2CON 29Bh — — 29Fh — ---- -000 ---- -uuu — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC2B CCP2M --00 0000 --00 0000 Unimplemented — — Bank 6 30Ch SLRCONA Slew Rate Control for PORTA 0000 0000 0000 0000 30Dh SLRCONB Slew Rate Control for PORTB 0000 0000 0000 0000 30Eh SLRCONC Slew Rate Control for PORTC 0000 0000 0000 0000 30Fh SLRCOND(3) Slew Rate Control for PORTD 310h SLRCONE(3) 311h — — 0000 0000 0000 0000 — — CCPR3L Capture/Compare/PWM Register 3 (LSB) 312h CCPR3H Capture/Compare/PWM Register 3 (MSB) 313h CCP3CON 314h — — 31Fh Legend: Note 1: 2: 3: 4: — — DC3B — SLRE2 SLRE1 SLRE0 ---- -111 ---- -111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M Unimplemented --00 0000 --00 0000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only. DS40001675C-page 42  2013-2015 Microchip Technology Inc. — PIC16(L)F1788/9 TABLE 3-12: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 38Ch INLVLA Input Type Control for PORTA 0000 0000 0000 0000 38Dh INLVLB Input Type Control for PORTB 0000 0000 0000 0000 38Eh INLVLC Input Type Control for PORTC 1111 1111 1111 1111 38Fh INLVLD(3) Input Type Control for PORTD 1111 1111 1111 1111 390h INLVLE — — — — INLVLE3 INLVLE2(3) INLVLE1(3) INLVLE0(3) ---- 1111 ---- 1111 391h IOCAP IOCAP 0000 0000 0000 0000 392h IOCAN IOCAN 0000 0000 0000 0000 393h IOCAF IOCAF 0000 0000 0000 0000 394h IOCBP IOCBP 0000 0000 0000 0000 395h IOCBN IOCBN 0000 0000 0000 0000 396h IOCBF IOCBF 0000 0000 0000 0000 397h IOCCP IOCCP 0000 0000 0000 0000 398h IOCCN IOCCN 0000 0000 0000 0000 399h IOCCF IOCCF 0000 0000 0000 0000 39Ah — — 39Ch Unimplemented — — 39Dh IOCEP — — — — IOCEP3 — — — ---- 0--- ---- 0--- 39Eh IOCEN — — — — IOCEN3 — — — ---- 0--- ---- 0--- 39Fh IOCEF — — — — IOCEF3 — — — ---- 0--- ---- 0--- Bank 8-9 40Ch or 41Fh and — 48Ch or 49Fh Unimplemented — — Unimplemented — — Bank 10 50Ch — — 510h 511h OPA1CON 512h — OPA1EN OPA1SP — — — — OPA1PCH 00-- --00 00-- --00 OPA2SP — — — — OPA2PCH 00-- --00 00-- --00 — — Unimplemented 513h OPA2CON 514h — OPA2EN — Unimplemented — 515h OPA3CON(3) OPA3EN OPA3SP — 51Ah CLKRCON CLKREN CLKROE CLKRSLR 51Bh — — 51Fh Legend: Note 1: 2: 3: 4: CLKRDC — OPA3PCH 00-- -000 00-- -000 CLKRDIV 0011 0000 0011 0000 Unimplemented — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only.  2013-2015 Microchip Technology Inc. — DS40001675C-page 43 — PIC16(L)F1788/9 TABLE 3-12: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 11-15 58Ch — — 590h Unimplemented 591h DAC2CON0 DAC2EN --- DAC2OE1 592h DAC2CON1 --- --- --- 593h DAC3CON0 DAC3EN --- DAC3OE1 594h DAC3CON1 --- --- --- 595h DAC4CON0 DAC4EN --- DAC4OE1 596h DAC4CON1 --- --- --- 597h — — 59Fh DAC2OE2 DAC2PSS --- --- DAC2R DAC3OE2 DAC3PSS --- --- DAC3R DAC4OE2 DAC4PSS 0-00 00-- 0-00 00----0 0000 ---0 0000 0-00 00-- 0-00 00----0 0000 ---0 0000 --- DAC4R --- 0-00 00-- 0-00 00----0 0000 ---0 0000 Unimplemented — — Unimplemented — — Bank 16-28 x0Ch or x8Ch to — x1Fh or x9Fh Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only. DS40001675C-page 44  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 3-12: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 29 E80h — — E90h Unimplemented E91h PSMC1CON PSMC1EN PSMC1LD P1DBFE P1DBRE P1MODE 0000 0000 0000 0000 E92h PSMC1MDL P1MDLEN P1MDLPOL P1MDLBIT — P1MSRC 000- 0000 000- 0000 E93h PSMC1SYNC P1DCPOL — P1POFST P1PRPOL E94h PSMC1CLK — — P1CPRE — P1SYNC — — 000- -000 000- -000 P1CSRC --00 --00 --00 --00 E95h PSMC1OEN — — P1OEF P1OEE P1OED P1OEC P1OEB P1OEA E96h PSMC1POL — P1INPOL P1POLF P1POLE P1POLD P1POLC P1POLB P1POLA E97h PSMC1BLNK — — — — E98h PSMCIREBS P1REBSIN — — P1REBSC4 P1REBSC3 P1REBSC2 P1REBSC1 — E99h PSMCIFEBS P1FEBSIN — — P1FEBSC4 P1FEBSC3 P1FEBSC2 P1FEBSC1 — 0--0 000- 0000 000- E9Ah PSMC1PHS P1PHSIN — — P1PHSC4 P1PHSC3 P1PHSC2 P1PHSC1 P1PHST 0--0 0000 0--0 0000 E9Bh PSMC1DCS P1DCSIN — — P1DCSC4 P1DCSC3 P1DCSC2 P1DCSC1 P1DCST 0--0 0000 0--0 0000 E9Ch PSMC1PRS P1PRSIN — — P1PRSC4 P1PRSC3 P1PRSC2 P1PRSC1 P1PRST 0--0 0000 0--0 0000 P1ASE P1ASDEN P1ARSEN — — — — P1ASDOV 000- ---0 000- ---0 E9Eh PSMC1ASDL — — P1ASDLF P1ASDLE P1ASDLD P1ASDLC P1ASDLB P1ASDLA --00 0000 --00 0000 E9Fh PSMC1ASDS P1ASDSIN — — P1ASDSC4 P1ASDSC3 P1ASDSC2 P1ASDSC1 — 0--0 000- 0--0 000- P1TOVIE P1TPHIE P1TDCIE P1TPRIE P1TOVIF P1TPHIF P1TDCIF P1TPRIF 0000 0000 0000 0000 E9Dh PSMC1ASDC EA0h PSMC1INT P1FEBM P1REBM --00 0000 --00 0000 -000 0000 -000 0000 --00 --00 --00 --00 0--0 000- 0000 000- EA1h PSMC1PHL Phase Low Count 0000 0000 0000 0000 EA2h PSMC1PHH Phase High Count 0000 0000 0000 0000 EA3h PSMC1DCL Duty Cycle Low Count 0000 0000 0000 0000 EA4h PSMC1DCH Duty Cycle High Count 0000 0000 0000 0000 EA5h PSMC1PRL Period Low Count 0000 0000 0000 0000 EA6h PSMC1PRH Period High Count 0000 0000 0000 0000 EA7h PSMC1TMRL Time base Low Counter 0000 0001 0000 0001 EA8h PSMC1TMRH Time base High Counter 0000 0000 0000 0000 EA9h PSMC1DBR Rising Edge Dead-band Counter 0000 0000 0000 0000 EAAh PSMC1DBF Falling Edge Dead-band Counter 0000 0000 0000 0000 EABh PSMC1BLKR Rising Edge Blanking Counter 0000 0000 0000 0000 EACh PSMC1BLKF Falling Edge Blanking Counter EADh PSMC1FFA 0000 0000 0000 0000 — — — — EAEh PSMC1STR0 — — P1STRF P1STRE P1STRD P1STRC P1STRB P1STRA --00 0001 --00 0001 EAFh PSMC1STR1 P1SSYNC — — — — — P1LSMEN P1HSMEN 0--- --00 0--- --00 EB0h — Legend: Note 1: 2: 3: 4: Fractional Frequency Adjust Register Unimplemented ---- 0000 ---- 0000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only.  2013-2015 Microchip Technology Inc. DS40001675C-page 45 — PIC16(L)F1788/9 TABLE 3-12: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 29 (Continued) EB1h PSMC2CON PSMC2EN PSMC2LD P2DBFE P2DBRE P2MODE 0000 0000 0000 0000 EB2h PSMC2MDL P2MDLEN P2MDLPOL P2MDLBIT — P2MSRC 000- 0000 000- 0000 EB3h PSMC2SYNC P2DCPOL — P2POFST P2PRPOL EB4h PSMC2CLK — — EB5h PSMC2OEN — — — EB6h PSMC2POL — P2INPOL — EB7h PSMC2BLNK — — EB8h PSMC2REBS P2REBSIN — — EB9h PSMC2FEBS P2FEBSIN — EBAh PSMC2PHS P2PHSIN EBBh PSMC2DCS EBCh PSMC2PRS — P2SYNC 000- -000 000- -000 — — — — — P2OEB P2OEA ---- --00 ---- --00 — — — P2POLB P2POLA -0-- --00 -0-- --00 — — P2REBSC4 P2REBSC3 P2REBSC2 P2REBSC1 — — P2FEBSC4 P2FEBSC3 P2FEBSC2 P2FEBSC1 — 0--0 000- 0--0 000- — — P2PHSC4 P2PHSC3 P2PHSC2 P2PHSC1 P2PHST 0--0 0000 0--0 0000 P2DCSIN — — P2DCSC4 P2DCSC3 P2DCSC2 P2DCSC1 P2DCST 0--0 0000 0--0 0000 P2PRSIN — — P2PRSC4 P2PRSC3 P2PRSC2 P2PRSC1 P2PRST 0--0 0000 0--0 0000 P2ASE P2ASDEN P2ARSEN — — — — P2ASDOV 000- ---0 000- ---0 EBEh PSMC2ASDL — — — — — — P2ASDLB P2ASDLA ---- --00 ---- --00 EBFh PSMC2ASDS P2ASDSIN — — P2ASDSC4 P2ASDSC3 P2ASDSC2 P2ASDSC1 — 0--0 000- 0--0 000- P2TOVIE P2TPHIE P2TDCIE P2TPRIE P2TOVIF P2TPHIF P2TDCIF P2TPRIF 0000 0000 0000 0000 EBDh PSMC2ASDC EC0h PSMC2INT P2CPRE P2FEBM P2CSRC P2REBM --00 --00 --00 --00 --00 --00 --00 --00 0--0 000- 0--0 000- EC1h PSMC2PHL Phase Low Count 0000 0000 0000 0000 EC2h PSMC2PHH Phase High Count 0000 0000 0000 0000 EC3h PSMC2DCL Duty Cycle Low Count 0000 0000 0000 0000 EC4h PSMC2DCH Duty Cycle High Count 0000 0000 0000 0000 EC5h PSMC2PRL Period Low Count 0000 0000 0000 0000 EC6h PSMC2PRH Period High Count 0000 0000 0000 0000 EC7h PSMC2TMRL Time base Low Counter 0000 0001 0000 0001 EC8h PSMC2TMRH Time base High Counter 0000 0000 0000 0000 EC9h PSMC2DBR Rising Edge Dead-band Counter 0000 0000 0000 0000 ECAh PSMC2DBF Falling Edge Dead-band Counter 0000 0000 0000 0000 ECBh PSMC2BLKR Rising Edge Blanking Counter 0000 0000 0000 0000 ECCh PSMC2BLKF Falling Edge Blanking Counter ECDh PSMC2FFA 0000 0000 0000 0000 — — — — ECEh PSMC2STR0 — — — — — — P2STRB P2STRA ---- --01 ---- --01 ECFh PSMC2STR1 P2SSYNC — — — — — P2LSMEN P2HSMEN 0--- --00 0--- --00 ED0h — Legend: Note 1: 2: 3: 4: Fractional Frequency Adjust Register Unimplemented ---- 0000 ---- 0000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only. DS40001675C-page 46  2013-2015 Microchip Technology Inc. — PIC16(L)F1788/9 TABLE 3-12: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 29 (Continued) ED1h PSMC3CON PSMC3EN PSMC3LD P3DBFE P3DBRE P3MODE 0000 0000 0000 0000 ED2h PSMC3MDL P3MDLEN P3MDLPOL P3MDLBIT — P3MSRC 000- 0000 000- 0000 ED3h PSMC3SYNC P3DCPOL — P3POFST P3PRPOL ED4h PSMC3CLK — — ED5h PSMC3OEN — — — ED6h PSMC3POL — P3INPOL — ED7h PSMC3BLNK — — ED8h PSMC3REBS P3REBSIN — — ED9h PSMC3FEBS P3FEBSIN — EDAh PSMC3PHS P3PHSIN EDBh PSMC3DCS EDCh PSMC3PRS — P3SYNC 000- -000 000- -000 — — — — — P3OEB P3OEA ---- --00 ---- --00 — — — P3POLB P3POLA -0-- --00 -0-- --00 — — P3REBSC4 P3REBSC3 P3REBSC2 P3REBSC1 — — P3FEBSC4 P3FEBSC3 P3FEBSC2 P3FEBSC1 — 0--0 000- 0--0 000- — — P3PHSC4 P3PHSC3 P3PHSC2 P3PHSC1 P3PHST 0--0 0000 0--0 0000 P3DCSIN — — P3DCSC4 P3DCSC3 P3DCSC2 P3DCSC1 P3DCST 0--0 0000 0--0 0000 P3PRSIN — — P3PRSC4 P3PRSC3 P3PRSC2 P3PRSC1 P3PRST 0--0 0000 0--0 0000 P3ASE P3ASDEN P3ARSEN — — — — P3ASDOV 000- ---0 000- ---0 EDEh PSMC3ASDL — — — — — — P3ASDLB P3ASDLA ---- --00 ---- --00 EDFh PSMC3ASDS P3ASDSIN — — P3ASDSC4 P3ASDSC3 P3ASDSC2 P3ASDSC1 — 0--0 000- 0--0 000- P3TOVIE P3TPHIE P3TDCIE P3TPRIE P3TOVIF P3TPHIF P3TDCIF P3TPRIF 0000 0000 0000 0000 EDDh PSMC3ASDC EE0h PSMC3INT P3CPRE P3FEBM P3CSRC P3REBM --00 --00 --00 --00 --00 --00 --00 --00 0--0 000- 0--0 000- EE1h PSMC3PHL Phase Low Count 0000 0000 0000 0000 EE2h PSMC3PHH Phase High Count 0000 0000 0000 0000 EE3h PSMC3DCL Duty Cycle Low Count 0000 0000 0000 0000 EE4h PSMC3DCH Duty Cycle High Count 0000 0000 0000 0000 EE5h PSMC3PRL Period Low Count 0000 0000 0000 0000 EE6h PSMC3PRH Period High Count 0000 0000 0000 0000 EE7h PSMC3TMRL Time base Low Counter 0000 0001 0000 0001 EE8h PSMC3TMRH Time base High Counter 0000 0000 0000 0000 EE9h PSMC3DBR Rising Edge Dead-band Counter 0000 0000 0000 0000 EEAh PSMC3DBF Falling Edge Dead-band Counter 0000 0000 0000 0000 EEBh PSMC3BLKR Rising Edge Blanking Counter 0000 0000 0000 0000 EECh PSMC3BLKF Falling Edge Blanking Counter EEDh PSMC3FFA 0000 0000 0000 0000 — — — — EEEh PSMC3STR0 — — — — — — P3STRB P3STRA ---- --01 ---- --01 EEFh PSMC3STR1 P3SSYNC — — — — — P3LSMEN P3HSMEN 0--- --00 0--- --00 Legend: Note 1: 2: 3: 4: Fractional Frequency Adjust Register ---- 0000 ---- 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only.  2013-2015 Microchip Technology Inc. DS40001675C-page 47 PIC16(L)F1788/9 TABLE 3-12: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 30 F0Ch — — F10h F11h Unimplemented PSMC4CON PSMC4EN PSMC4LD P4DBFE P4DBRE P4MODE 0000 0000 0000 0000 F12h PSMC4MDL P4MDLEN P4MDLPOL P4MDLBIT — P4MSRC 000- 0000 000- 0000 F13h PSMC4SYNC P4DCPOL — P4POFST P4PRPOL F14h PSMC4CLK — — F15h PSMC4OEN — — — F16h PSMC4POL — P4INPOL — F17h PSMC4BLNK — — F18h PSMC4REBS P4REBSIN — — F19h PSMC4FEBS P4FEBSIN — F1Ah PSMC4PHS P4PHSIN F1Bh PSMC4DCS F1Ch PSMC4PRS — P4SYNC 000- -000 000- -000 — — — — — P4OEB P4OEA ---- --00 ---- --00 — — — P4POLB P4POLA -0-- --00 -0-- --00 — — P4REBSC4 P4REBSC3 P4REBSC2 P4REBSC1 — — P4FEBSC4 P4FEBSC3 P4FEBSC2 P4FEBSC1 — 0--0 000- 0--0 000- — — P4PHSC4 P4PHSC3 P4PHSC2 P4PHSC1 P4PHST 0--0 0000 0--0 0000 P4DCSIN — — P4DCSC4 P4DCSC3 P4DCSC2 P4DCSC1 P4DCST 0--0 0000 0--0 0000 P4PRSIN — — P4PRSC4 P4PRSC3 P4PRSC2 P4PRSC1 P4PRST 0--0 0000 0--0 0000 P4ASE P4ASDEN P4ARSEN — — — — P4ASDOV 000- ---0 000- ---0 F1Eh PSMC4ASDL — — — — — — P4ASDLB P4ASDLA ---- --00 ---- --00 F1Fh PSMC4ASDS P4ASDSIN — — P4ASDSC4 P4ASDSC3 P4ASDSC2 P4ASDSC1 — 0--0 000- 0--0 000- P4TOVIE P4TPHIE P4TDCIE P4TPRIE P4TOVIF P4TPHIF P4TDCIF P4TPRIF 0000 0000 0000 0000 F1Dh PSMC4ASDC F20h PSMC4INT P4CPRE P4FEBM P4CSRC P4REBM --00 --00 --00 --00 --00 --00 --00 --00 0--0 000- 0--0 000- F21h PSMC4PHL Phase Low Count 0000 0000 0000 0000 F22h PSMC4PHH Phase High Count 0000 0000 0000 0000 F23h PSMC4DCL Duty Cycle Low Count 0000 0000 0000 0000 F24h PSMC4DCH Duty Cycle High Count 0000 0000 0000 0000 F25h PSMC4PRL Period Low Count 0000 0000 0000 0000 F26h PSMC4PRH Period High Count 0000 0000 0000 0000 F27h PSMC4TMRL Time base Low Counter 0000 0001 0000 0001 F28h PSMC4TMRH Time base High Counter 0000 0000 0000 0000 F29h PSMC4DBR Rising Edge Dead-band Counter 0000 0000 0000 0000 F2Ah PSMC4DBF Falling Edge Dead-band Counter 0000 0000 0000 0000 F2Bh PSMC4BLKR Rising Edge Blanking Counter 0000 0000 0000 0000 F2Ch PSMC4BLKF Falling Edge Blanking Counter F2Dh PSMC4FFA 0000 0000 0000 0000 — — — — F2Eh PSMC4STR0 — — — — — — P4STRB P4STRA ---- --01 ---- --01 F2Fh PSMC4STR1 P4SSYNC — — — — — P4LSMEN P4HSMEN 0--- --00 0--- --00 Legend: Note 1: 2: 3: 4: Fractional Frequency Adjust Register ---- 0000 ---- 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only. DS40001675C-page 48  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 3-12: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 31 F8Ch to — FE3h Unimplemented FE4h STATUS_ SHAD — — — — — Z DC FE5h WREG_SHAD Working Register Shadow FE6h BSR_SHAD — FE7h PCLATH_ SHAD — — C ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu — Bank Select Register Shadow Program Counter Latch High Register Shadow ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_ SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_ SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh — Unimplemented FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Note 1: 2: 3: 4: — — — — Current Stack Pointer Top of Stack Low byte — Top of Stack High byte xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. Unimplemented, read as ‘1’. PIC16(L)F1789 only. PIC16F1788/9 only.  2013-2015 Microchip Technology Inc. — ---1 1111 ---1 1111 DS40001675C-page 49 PIC16(L)F1788/9 3.4 3.4.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 3-3: If using the CALL instruction, the PCH and PCL registers are loaded with the operand of the CALL instruction. PCH is loaded with PCLATH. PC LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 14 PCH PCL 0 PCLATH PC 8 ALU Result PCL 0 4 0 11 OPCODE PC 14 PCH PCL 0 CALLW 6 PCLATH PC Instruction with PCL as Destination GOTO, CALL 6 PCLATH 0 14 7 0 PCH 8 W PCL 0 BRW PC + W 14 PCH 3.4.4 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. PCL 0 BRA 15 PC + OPCODE 3.4.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.4.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556). DS40001675C-page 50  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 3.5 3.5.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 3-1). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL  2013-2015 Microchip Technology Inc. 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) DS40001675C-page 51 PIC16(L)F1788/9 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL DS40001675C-page 52 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.5.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.6 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2013-2015 Microchip Technology Inc. DS40001675C-page 53 PIC16(L)F1788/9 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001675C-page 54  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x00 0x7F  2013-2015 Microchip Technology Inc. DS40001675C-page 55 PIC16(L)F1788/9 3.6.2 3.6.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF DS40001675C-page 56 0xF6F 0xFFFF 0x7FFF  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2013-2015 Microchip Technology Inc. DS40001675C-page 57 PIC16(L)F1788/9 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 R/P-1 BOREN CPD bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 8 R/P-1 R/P-1 R/P-1 WDTE R/P-1 R/P-1 FOSC bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor and internal/external switchover are both enabled. 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(1) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled DS40001675C-page 58  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 4-1: bit 2-0 Note 1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins The entire data EEPROM will be erased when the code protection is turned off during an erase.Once the Data Code Protection bit is enabled, (CPD = 0), the Bulk Erase Program Memory Command (through ICSP) can disable the Data Code Protection (CPD =1). When a Bulk Erase Program Memory Command is executed, the entire Program Flash Memory, Data EEPROM and configuration memory will be erased.  2013-2015 Microchip Technology Inc. DS40001675C-page 59 PIC16(L)F1788/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 LVP DEBUG LPBOR BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 R/P-1 U-1 U-1 U-1 — — VCAPEN — — — R/P-1 R/P-1 WRT bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(3) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(4) 1 = Brown-out Reset voltage (VBOR), low trip point selected. 0 = Brown-out Reset voltage (VBOR), high trip point selected. bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-6 Unimplemented: Read as ‘1’ bit 5 VCAPEN: Voltage Regulator Capacitor Enable bit(2) 1 = VCAP functionality is disabled on RA6 0 = VCAP functionality is enabled on RA6 bit 4-2 Unimplemented: Read as ‘1’ bit 1-0 WRT: Flash Memory Self-Write Protection bits 8 kW Flash memory (PIC16(L)F1788/9 only): 11 = Write protection off 10 = 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified by EECON control 01 = 0000h to 0FFFh write-protected, 1000h to 1FFFh may be modified by EECON control 00 = 0000h to 1FFFh write-protected, no addresses may be modified by EECON control Note 1: 2: 3: 4: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. Not implemented on “LF” devices. The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. See VBOR parameter for specific trip point voltages. DS40001675C-page 60  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write Protection” for more information. 4.3.2 DATA EEPROM PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 12.5 “User ID, Device ID and Configuration Word Access”for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F178X Memory Programming Specification” (DS41457).  2013-2015 Microchip Technology Inc. DS40001675C-page 61 PIC16(L)F1788/9 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 12.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device and Revision REGISTER 4-3: DEVID: DEVICE ID REGISTER R R R R R R DEV bit 13 R R bit 8 R R R R R R DEV bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared DEV: Device ID bits Device DEVID Values PIC16F1788 11 0000 0010 1011 (302Bh) PIC16LF1788 11 0000 0010 1101 (302Dh) PIC16F1789 11 0000 0010 1010 (302Ah) PIC16LF1789 11 0000 0010 1100 (302Ch) REGISTER 4-4: REVID: REVISION ID REGISTER R R R R R R REV bit 13 R R bit 8 R R R R R R REV bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared REV: Revision ID bits DS40001675C-page 62  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 5.0 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. RESETS There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT ICSP™ Programming Mode Exit RESET Instruction Stack Pointer MCLRE Sleep WDT Time-out Device Reset Power-on Reset VDD Brown-out Reset R PWRT Done LPBOR Reset PWRTE LFINTOSC BOR Active(1) Note 1: See Table 5-1 for BOR active conditions.  2013-2015 Microchip Technology Inc. DS40001675C-page 63 PIC16(L)F1788/9 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 5.1.1 • • • • POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). TABLE 5-1: The Brown-out Reset module has four operating modes controlled by the BOREN bits in Configuration Words. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 5-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 5-2 for more information. BOR OPERATING MODES BOREN SBOREN Device Mode BOR Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 Instruction Execution upon: Release of POR or Wake-up from Sleep Waits for BOR ready(1) (BORRDY = 1) Waits for BOR ready (BORRDY = 1) Waits for BOR ready(1) (BORRDY = 1) Begins immediately (BORRDY = x) Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN bits. 5.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 5.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. 5.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS40001675C-page 64  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 5.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. Register Definitions: BOR Control REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN = 11 (Always on) or BOREN = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN = 10 (Disabled in Sleep) or BOREN = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN bits are located in Configuration Words.  2013-2015 Microchip Technology Inc. DS40001675C-page 65 PIC16(L)F1788/9 5.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.4.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 5.4.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON register and to the power control block. 5.5 MCLR 5.6 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 11.0 “Watchdog Timer (WDT)” for more information. 5.7 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table 5-4 for default conditions after a RESET instruction has occurred. 5.8 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 5.8 “Stack Overflow/Underflow Reset” for more information. 5.9 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 5-2). 5.10 TABLE 5-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 5.5.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 5.5.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 13.11 “PORTE Registers” for more information. DS40001675C-page 66 Power-Up Timer The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 5.11 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2013-2015 Microchip Technology Inc. DS40001675C-page 67 PIC16(L)F1788/9 5.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS40001675C-page 68  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 5.13 Power Control (PCON) Register The PCON register bits are shown in Register 5-2. The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) 5.14 Register Definitions: Power Control REGISTER 5-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF — R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2013-2015 Microchip Technology Inc. DS40001675C-page 69 PIC16(L)F1788/9 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 65 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 69 STATUS — — — TO PD Z DC C 31 WDTCON — — SWDTEN 114 WDTPS Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS40001675C-page 70  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 6.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 6.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources  2013-2015 Microchip Technology Inc. The oscillator module can be configured in one of eight clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM – External Clock Medium-Power mode (0.5 MHz to 4 MHz) ECH – External Clock High-Power mode (4 MHz to 32 MHz) LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) RC – External Resistor-Capacitor (RC). INTOSC – Internal oscillator (31 kHz to 32 MHz). Clock Source modes are selected by the FOSC bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these three clock sources. DS40001675C-page 71 PIC16(L)F1788/9 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 6-1: Oscillator Timer1 Timer1 Clock Source Option for other modules T1OSO T1OSCEN Enable Oscillator T1OSI T1OSC 01 External Oscillator LP, XT, HS, RC, EC OSC2 0 Sleep 10 1 Sleep PRIMUX OSC1 PSMCMUX 0 ÷2 4 x PLL 00 01 FOSC To CPU and Peripherals 00 1 IRCF HFPLL 500 kHz Source 16 MHz (HFINTOSC) Postscaler Internal Oscillator Block 500 kHz (MFINTOSC) 31 kHz Source 31 kHz FOSC =100 =00 ≠100 PSMC 64 MHz 0000 ≠00 XXX WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules PLLEN or SPLLEN PRIMUX PSMCMUX PLLMUX 0 1 1 10 1 1 1 01 0 0 1 10 (1) 0 0 00 X X 1 XX 1 1X SCS 31 kHz (LFINTOSC) SCS INTOSC 1111 MUX 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz PLLMUX Note 1: This selection should not be made when the PSMC is using the 64 MHz clock option. DS40001675C-page 72  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 6.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 6.3 “Clock Switching” for additional information. 6.2.1 FIGURE 6-2: OSC1/CLKIN Clock from Ext. System PIC® MCU FOSC/4 or I/O(1) Note 1: EXTERNAL CLOCK (EC) MODE OPERATION OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Words. EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: • Program the FOSC bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. • Write the SCS bits in the OSCCON register to switch the system clock source to: - Timer1 oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 6.3 “Clock Switching”for more information. 6.2.1.1 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 6-2 shows the pin connections for EC mode. 6.2.1.2 LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 6-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 6-3 and Figure 6-4 show typical circuits for quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Words: • High power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low power, 0-0.5 MHz (FOSC = 101)  2013-2015 Microchip Technology Inc. DS40001675C-page 73 PIC16(L)F1788/9 FIGURE 6-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 6-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 To Internal Logic Quartz Crystal C2 Note 1: 2: OSC1/CLKIN RS(1) RF(2) C1 Sleep OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. RP(3) C2 Ceramic RS(1) Resonator Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) DS40001675C-page 74 To Internal Logic RF(2) Sleep OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 6.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended, unless either FSCM or Two-Speed Start-Up are enabled. In this case, code will continue to execute at the selected INTOSC frequency while the OST is counting. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 6.4 “Two-Speed Clock Start-up Mode”).  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 6.2.1.4 4x PLL The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Section 30.0 “Electrical Specifications”. The 4x PLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Words to a ‘1’. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored. 6.2.1.5 TIMER1 Oscillator The Timer1 oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The Timer1 oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 6.3 “Clock Switching” for more information. FIGURE 6-5: Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) QUARTZ CRYSTAL OPERATION (TIMER1 OSCILLATOR) PIC® MCU T1OSI C1 To Internal Logic 32.768 kHz Quartz Crystal C2 T1OSO  2013-2015 Microchip Technology Inc. DS40001675C-page 75 PIC16(L)F1788/9 6.2.1.6 External RC Mode 6.2.2 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. Figure 6-6 shows the external RC mode connections. FIGURE 6-6: EXTERNAL RC MODES VDD PIC® MCU The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 6.3 “Clock Switching”for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. REXT OSC1/CLKIN Internal Clock CEXT VSS The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL that can produce one of three internal system clock sources. 1. FOSC/4 or I/O(1) OSC2/CLKOUT Recommended values: 10 k  REXT  100 k, 20 pF, 2-5V Note 1: INTERNAL CLOCK SOURCES Output depends upon CLKOUTEN bit of the Configuration Words. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance 2. 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The user also needs to take into account variation due to tolerance of external RC components used. DS40001675C-page 76  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 6.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The HFINTOSC is enabled by: • Configure the IRCF bits of the OSCCON register for the desired HF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’. A fast startup oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC. The High Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 6.2.2.2 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF bits of the OSCCON register for the desired HF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running.  2013-2015 Microchip Technology Inc. 6.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 6-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 6.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a multiplexer (see Figure 6-1). Select 31 kHz, via software, using the IRCF bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: • Configure the IRCF bits of the OSCCON register for the desired LF frequency, and • FOSC = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. DS40001675C-page 77 PIC16(L)F1788/9 6.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF of the OSCCON register. The output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). The Internal Oscillator Frequency Select bits IRCF of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: - 32 MHz (requires 4x PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF bits of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. 6.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC = 100). • The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC in Configuration Words (SCS = 00). • The IRCF bits in the OSCCON register must be set to the 8 MHz or 16 MHz HFINTOSC set to use (IRCF = 111x). • The SPLLEN bit in the OSCCON register must be set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a ‘1’. Note: When using the PLLEN bit of the Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN option will not be available. The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4x PLL with the internal oscillator. The IRCF bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. DS40001675C-page 78  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 6.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-7). If this is the case, there is a delay after the IRCF bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. IRCF bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 6-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 6-1. Start-up delay specifications are located in the oscillator tables of Section 31.0 “Electrical Specifications”.  2013-2015 Microchip Technology Inc. DS40001675C-page 79 PIC16(L)F1788/9 FIGURE 6-7: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC 0 IRCF 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF =0 0 System Clock DS40001675C-page 80  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 6.3 Clock Switching 6.3.3 TIMER1 OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The Timer1 oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. • Default system oscillator determined by FOSC bits in Configuration Words • Timer1 32 kHz crystal oscillator • Internal Oscillator Block (INTOSC) The Timer1 oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 23.0 “Timer1 Module with Gate Control” for more information about the Timer1 peripheral. 6.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. • When the SCS bits of the OSCCON register = 00, the system clock source is determined by the value of the FOSC bits in the Configuration Words. • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 6-1. 6.3.2 6.3.4 TIMER1 OSCILLATOR READY (T1OSCR) BIT The user must ensure that the Timer1 oscillator is ready to be used before it is selected as a system clock source. The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. 6.3.5 CLOCK SWITCHING BEFORE SLEEP When clock switching from an old clock to a new clock is requested just prior to entering Sleep mode, it is necessary to confirm that the switch is complete before the SLEEP instruction is executed. Failure to do so may result in an incomplete switch and consequential loss of the system clock altogether. Clock switching is confirmed by monitoring the clock status bits in the OSCSTAT register. Switch confirmation can be accomplished by sensing that the Ready bit for the new clock is set or the Ready bit for the old clock is cleared. For example, when switching between the internal oscillator with the PLL and the internal oscillator without the PLL, monitor the PLLR bit. When PLLR is set the switch to 32 MHz, operation is complete. Conversely, when PLLR is cleared, the switch from 32 MHz operation to the selected internal clock is complete. OSCILLATOR START-UP TIMER STATUS (OSTS) BIT The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 oscillator.  2013-2015 Microchip Technology Inc. DS40001675C-page 81 PIC16(L)F1788/9 6.4 6.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Words) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). • SCS (of the OSCCON register) = 00. • FOSC bits in the Configuration Words configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 6-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) Sleep MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz Oscillator Warm-up Delay TWARM(2) Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each Sleep/POR Timer1 Oscillator LP, XT, HS(1) 32 kHz-20 MHz 1024 Clock Cycles (OST) Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC(1) 31 kHz 1 cycle of each Any clock source Timer1 Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32 MHz 2 ms (approx.) Note 1: 2: PLL inactive. See Section 31.0 “Electrical Specifications”. DS40001675C-page 82  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 6.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 6.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 6-8: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC bits in the Configuration Words, or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock  2013-2015 Microchip Technology Inc. DS40001675C-page 83 PIC16(L)F1788/9 6.5 6.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC). FIGURE 6-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock LFINTOSC Oscillator ÷ 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 6.5.1 FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 6-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 6.5.2 The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware. 6.5.4 Clock Failure Detected FAIL-SAFE CONDITION CLEARING RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS40001675C-page 84  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 6-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.  2013-2015 Microchip Technology Inc. DS40001675C-page 85 PIC16(L)F1788/9 6.6 Register Definitions: Oscillator Control REGISTER 6-1: R/W-0/0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 SPLLEN R/W-1/1 R/W-1/1 R/W-1/1 IRCF U-0 R/W-0/0 — R/W-0/0 SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF: Internal Oscillator Frequency Select bits 1111 = 16 MHz HF or 32 MHz HF(2) 1110 = 8 MHz or 32 MHz HF(2) 1101 = 4 MHz HF 1100 = 2 MHz HF 1011 = 1 MHz HF 1010 = 500 kHz HF(1) 1001 = 250 kHz HF(1) 1000 = 125 kHz HF(1) 0111 = 500 kHz MF (default upon Reset) 0110 = 250 kHz MF 0101 = 125 kHz MF 0100 = 62.5 kHz MF 0011 = 31.25 kHz HF(1) 0010 = 31.25 kHz MF 000x = 31 kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC in Configuration Words. Note 1: 2: Duplicate frequency derived from HFINTOSC. 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency Selection”. DS40001675C-page 86  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC bits of the Configuration Words 0 = Running from an internal oscillator (FOSC = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate  2013-2015 Microchip Technology Inc. DS40001675C-page 87 PIC16(L)F1788/9 REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency. 000001 = • • • 011110 = 011111 = Maximum frequency TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 OSCCON SPLLEN OSCSTAT T1OSCR OSCTUNE Bit 6 Bit 5 PLLR OSTS Bit 4 Bit 3 Bit 2 HFIOFR HFIOFL MFIOFR IRCF Bit 1 — Bit 0 SCS Register on Page 86 LFIOFR HFIOFS 87 — — PIE2 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 99 PIR2 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 103 T1OSCEN T1SYNC — TMR1ON 217 TMR1CS T1CON Legend: CONFIG1 Legend: Note 1: T1CKPS 88 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 6-3: Name TUN SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE Bit 10/2 Bit 9/1 BOREN WDTE FOSC Bit 8/0 CPD Register on Page 58 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. PIC16F1788/9 only. DS40001675C-page 88  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 7.0 REFERENCE CLOCK MODULE The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR). This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. The reference clock module includes the following features: • • • • • • System clock is the source Available in all oscillator configurations Programmable clock divider Output enable to a port pin Selectable duty cycle Slew rate control The reference clock module is controlled by the CLKRCON register (Register 7-1) and is enabled when setting the CLKREN bit. To output the divided clock signal to the CLKR port pin, the CLKROE bit must be set. The CLKRDIV bits enable the selection of eight different clock divider options. The CLKRDC bits can be used to modify the duty cycle of the output clock(1). The CLKRSLR bit controls slew rate limiting. 7.1 Slew Rate The slew rate limitation on the output port pin can be disabled. The slew rate limitation is removed by clearing the CLKRSLR bit in the CLKRCON register. 7.2 Effects of a Reset Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 7.3 Operation During Sleep As the reference clock module relies on the system clock as its source, and the system clock is disabled in Sleep, the module does not function in Sleep, even if an external clock source or the Timer1 clock source is configured as the system clock. The module outputs will remain in their current state until the device exits Sleep. Note 1: If the base clock rate is selected without a divider, the output clock will always have a duty cycle equal to that of the source clock, unless a 0% duty cycle is selected. If the clock divider is set to base clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock.  2013-2015 Microchip Technology Inc. DS40001675C-page 89 PIC16(L)F1788/9 7.4 Register Definition: Reference Clock Control REGISTER 7-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 CLKREN CLKROE CLKRSLR R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC R/W-0/0 R/W-0/0 CLKRDIV bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference clock module is enabled 0 = Reference clock module is disabled bit 6 CLKROE: Reference Clock Output Enable bit 1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin bit 5 CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit 1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled bit 4-3 CLKRDC: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 CLKRDIV Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1 is required. CLKOUTEN of Configuration Words = 0 will result in FOSC/4. See Section 7.3 “Operation During Sleep” for details. DS40001675C-page 90  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Name CLKRCON Legend: Bit 7 Bit 6 Bit 5 CLKREN CLKROE CLKRSLR CONFIG1 Legend: Bit 3 CLKRDC Bit 2 Bit 1 Bit 0 CLKRDIV Register on Page 90 — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. TABLE 7-2: Name Bit 4 Bits SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 — — FCMEN 7:0 CP MCLRE PWRTE WDTE1 Bit 10/2 Bit 9/1 BOREN FOSC Bit 8/0 CPD Register on Page 58 — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources.  2013-2015 Microchip Technology Inc. DS40001675C-page 91 PIC16(L)F1788/9 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 8-1. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1 (TMR1IE) PIE1 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn PIEn  2013-2015 Microchip Technology Inc. GIE DS40001675C-page 92 PIC16(L)F1788/9 8.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 8-2 and Figure 8.3 for more details. The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section 8.5 “Automatic Context Saving”.”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001675C-page 93  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 8-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Inst(PC) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC  2013-2015 Microchip Technology Inc. PC+2 NOP NOP DS40001675C-page 94 PIC16(L)F1788/9 FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 31.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001675C-page 95  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 9.0 “Power-Down Mode (Sleep)” for more details. 8.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • • • • • W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.  2013-2015 Microchip Technology Inc. DS40001675C-page 96 PIC16(L)F1788/9 8.6 Register Definitions: Interrupt Control REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: Note: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-change flags in the IOCBF register have been cleared by software. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001675C-page 97  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2013-2015 Microchip Technology Inc. DS40001675C-page 98 PIC16(L)F1788/9 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2 C4IE: Comparator C4 Interrupt Enable bit 1 = Enables the Comparator C4 Interrupt 0 = Disables the Comparator C4 Interrupt bit 1 C3IE: Comparator C3 Interrupt Enable bit 1 = Enables the Comparator C3 Interrupt 0 = Disables the Comparator C3 Interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001675C-page 99  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 8-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 — — — CCP3IE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 CCP3IE: CCP3 Interrupt Enable bit 1 = Enables the CCP3 interrupt 0 = Disables the CCP3 interrupt bit 3-0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS40001675C-page 100 PIC16(L)F1788/9 REGISTER 8-5: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMC4TIE PSMC3TIE PSMC2TIE PSMC1TIE PSMC4SIE PSMC3SIE PSMC2SIE PSMC1SIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PSMC4TIE: PSMC4 Time Base Interrupt Enable bit 1 = Enables PSMC4 time base generated interrupts 0 = Disables PSMC4 time base generated interrupts bit 6 PSMC3TIE: PSMC3 Time Base Interrupt Enable bit 1 = Enables PSMC3 time base generated interrupts 0 = Disables PSMC3 time base generated interrupts bit 5 PSMC2TIE: PSMC2 Time Base Interrupt Enable bit 1 = Enables PSMC2 time base generated interrupts 0 = Disables PSMC2 time base generated interrupts bit 4 PSMC1TIE: PSMC1 Time Base Interrupt Enable bit 1 = Enables PSMC1 time base generated interrupts 0 = Disables PSMC1 time base generated interrupts bit 3 PSMC4SIE: PSMC4 Auto-Shutdown Interrupt Enable bit 1 = Enables PSMC4 auto-shutdown interrupts 0 = Disables PSMC4 auto-shutdown interrupts bit 2 PSMC3SIE: PSMC3 Auto-Shutdown Interrupt Enable bit 1 = Enables PSMC3 auto-shutdown interrupts 0 = Disables PSMC3 auto-shutdown interrupts bit 1 PSMC2SIE: PSMC2 Auto-Shutdown Interrupt Enable bit 1 = Enables PSMC2 auto-shutdown interrupts 0 = Disables PSMC2 auto-shutdown interrupts bit 0 PSMC1SIE: PSMC1 Auto-Shutdown Interrupt Enable bit 1 = Enables PSMC1 auto-shutdown interrupts 0 = Disables PSMC1 auto-shutdown interrupts Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001675C-page 101  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 8-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: ADC Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2013-2015 Microchip Technology Inc. DS40001675C-page 102 PIC16(L)F1788/9 REGISTER 8-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 C4IF: Comparator C4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 C3IF: Comparator C3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001675C-page 103  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 8-8: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 — — — CCP3IF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 CCP3IF: CCP3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3-0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS40001675C-page 104 PIC16(L)F1788/9 REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMC4TIF PSMC3TIF PSMC2TIF PSMC1TIF PSMC4SIF PSMC3SIF PSMC2SIF PSMC1SIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PSMC4TIF: PSMC4 Time Base Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 PSMC3TIF: PSMC3 Time Base Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 PSMC2TIF: PSMC2 Time Base Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 PSMC1TIF: PSMC1 Time Base Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 PSMC4SIF: PSMC4 Auto-shutdown Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 PSMC3SIF: PSMC3 Auto-shutdown Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 PSMC2SIF: PSMC2 Auto-shutdown Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 PSMC1SIF: PSMC1 Auto-shutdown Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001675C-page 105  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 8-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IF Bit 1 Bit 0 INTF IOCIF Register on Page GIE PEIE TMR0IE INTE IOCIE WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE PIE2 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 99 PIE3 — — — CCP3IE — — — — 100 OPTION_REG PS 97 208 98 PIE4 PSMC4TIE PSMC3TIE PSMC2TIE PSMC1TIE PSMC4SIE PSMC3SIE PSMC2SIE PSMC1SIE 101 PIR1 TMR1GIF ADIF RCIF PIR2 OSFIF C2IF PIR3 — — PIR4 Legend: TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 C1IF EEIF BCL1IF C4IF C3IF CCP2IF 103 — CCP3IF — — — — 104 PSMC4TIF PSMC3TIF PSMC2TIF PSMC1TIF PSMC4SIF PSMC3SIF PSMC2SIF PSMC1SIF 105 — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.  2013-2015 Microchip Technology Inc. DS40001675C-page 106 PIC16(L)F1788/9 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. Timer1 and peripherals that operate from Timer1 continue operation in Sleep when the Timer1 clock source selected is: • LFINTOSC • T1CKI • Timer1 oscillator ADC is unaffected, if the dedicated FRC oscillator is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: • • • • • • External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 5.12 “Determining the Cause of a Reset”. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using Timer1 oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 19.0 “8-Bit Digital-to-Analog Converter (DAC) Module” and Section 15.0 “Fixed Voltage Reference (FVR)” for more information on these modules.  2013-2015 Microchip Technology Inc. DS40001675C-page 107 PIC16(L)F1788/9 9.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared. FIGURE 9-1: • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. TOST = 1024 TOSC; This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (See Section 6.4 “Two-Speed Clock Start-up Mode”). GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. DS40001675C-page 108  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 9.2 Low-Power Sleep Mode “F” devices contain an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. “F” devices allow the user to optimize the operating current in Sleep, depending on the application requirements. A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 9.2.1 SLEEP CURRENT VS. WAKE-UP TIME In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. 9.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The LDO will remain in the normal power mode when those peripherals are enabled. The Low-Power Sleep mode is intended for use with these peripherals: • • • • Brown-Out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer1 (with external clock source) Note: “LF” devices do not have a configurable Low-Power Sleep mode. “LF” devices are an unregulated device and are always in the lowest power state when in Sleep, with no wake-up time penalty. These devices have a lower maximum VDD and I/O voltage than “F” devices. See Section 31.0 “Electrical Specifications” for more information. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.  2013-2015 Microchip Technology Inc. DS40001675C-page 109 PIC16(L)F1788/9 9.3 Register Definitions: Voltage Regulator Control VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 9-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal-Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: 2: “F” devices only. See Section 31.0 “Electrical Specifications”. TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF RAIF 97 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 164 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 163 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 163 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIE2 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 99 — — — CCP3IE — — — — 100 PIE3 PIE4 PSMC4TIE PSMC3TIE PSMC2TIE PSMC1TIE PSMC4SIE PSMC3SIE PSMC2SIE PSMC1SIE PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 98 PIR2 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 103 — — — CCP3IF — — — — 104 PIR3 PIR4 PSMC4TIF PSMC3TIF PSMC2TIF PSMC1TIF PSMC4SIF PSMC3SIF PSMC2SIF PSMC1SIF STATUS — — — TO VREGCON — — — — WDTCON — — Legend: PD Z DC — — VREGPM WDTPS 101 105 C 31 Reserved 110 SWDTEN 114 — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. DS40001675C-page 110  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 10.0 On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information on the constant current rate, refer to the LDO Regulator Characteristics Table in Section 31.0 “Electrical Specifications”. LOW DROPOUT (LDO) VOLTAGE REGULATOR The “F” devices have an internal Low Dropout Regulator (LDO) which provide operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the VDD and I/O pins to operate at a higher voltage. There is no user enable/disable control available for the LDO, it is always active. The “LF” devices operate at a maximum VDD of 3.6V and does not incorporate an LDO. A device I/O pin may be configured as the LDO voltage output, identified as the VCAP pin. Although not required, an external low-ESR capacitor may be connected to the VCAP pin for additional regulator stability. The VCAPEN bit of Configuration Words determines if which pin is assigned as the VCAP pin. Refer to Table 10-1. TABLE 10-1: VCAPEN Pin 1 No VCAP 0 RA6 TABLE 10-2: Name CONFIG2 Legend: Note 1: VCAPEN SELECT BIT SUMMARY OF CONFIGURATION WORD WITH LDO Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — 7:0 — — LVP DEBUG LPBOR BORV STVREN PLLEN — VCAPEN(1) — — — WRT Register on Page 60 — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO. “F” devices only.  2013-2015 Microchip Technology Inc. DS40001675C-page 111 PIC16(L)F1788/9 11.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 11-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE = 01 SWDTEN WDTE = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE = 10 Sleep  2013-2015 Microchip Technology Inc. WDTPS DS40001675C-page 112 PIC16(L)F1788/9 11.1 Independent Clock Source 11.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Section 31.0 “Electrical Specifications” for the LFINTOSC tolerances. The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds. 11.4 11.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE bits in Configuration Words. See Table 11-1. 11.2.1 WDT IS ALWAYS ON When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. WDT protection is active during Sleep. 11.2.2 WDT IS OFF IN SLEEP WDT protection is not active during Sleep. WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged Table 11-1 for more details. TABLE 11-1: by Clearing the WDT The WDT is cleared when any of the following conditions occur: • • • • • • • Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail WDT is disabled Oscillator Start-up TImer (OST) is running See Table 11-2 for more information. When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep. 11.2.3 Time-Out Period Sleep. See WDT OPERATING MODES WDTE SWDTEN Device Mode 11 X X 10 X WDT Mode Active 11.5 Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See Section 3.0 “Memory Organization” and Status Register (Register 3-1) for more information. Awake Active Sleep 1 X 01 0 00 TABLE 11-2: X X Disabled Active Disabled Disabled WDT CLEARING CONDITIONS Conditions WDT WDTE = 00 WDTE = 01 and SWDTEN = 0 WDTE = 10 and enter Sleep CLRWDT Command Cleared Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) DS40001675C-page 113 Cleared until the end of OST Unaffected  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 11.6 Register Definitions: Watchdog Control REGISTER 11-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 WDTPS bit 7 R/W-0/0 SWDTEN bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 Note 1: = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE = 1x: This bit is ignored. If WDTE = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE = 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC.  2013-2015 Microchip Technology Inc. DS40001675C-page 114 PIC16(L)F1788/9 TABLE 11-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON SPLLEN STATUS — — WDTCON — — Bit 5 Bit 4 Bit 3 IRCF — Bit 2 Bit 1 — TO PD Bit 0 SCS Z DC WDTPS Register on Page 86 C 31 SWDTEN 114 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 11-4: Name CONFIG1 Legend: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE — WDTE Bit 10/2 Bit 9/1 BOREN FOSC Bit 8/0 CPD Register on Page 58 = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. DS40001675C-page 115  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 12.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs). There are six SFRs used to access these memories: • • • • • • EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh. When accessing the program memory block, the EEDATH:EEDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read. The EEPROM data memory allows byte read and write. An EEPROM byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. Depending on the setting of the Flash Program Memory Self Write Enable bits WRT of the Configuration Words, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. 12.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register. 12.1.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. Interrupt flag bit EEIF of the PIR2 register is set when write is complete. It must be cleared in the software. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.  2013-2015 Microchip Technology Inc. DS40001675C-page 116 PIC16(L)F1788/9 12.2 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 31.0 “Electrical Specifications”. If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. 12.2.1 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation). EXAMPLE 12-1: DATA EEPROM READ BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory ;Address to read BCF EECON1, CFGS ;Deselect Config space BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read MOVF EEDATL, W ;W = EEDATL Note: Data EEPROM can be read regardless of the setting of the CPD bit. 12.2.2 WRITING TO THE DATA EEPROM MEMORY To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set the WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. 12.2.3 PROTECTION AGAINST SPURIOUS WRITE There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out • Power Glitch • Software Malfunction 12.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Words to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. DS40001675C-page 117  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Required Sequence EXAMPLE 12-2: DATA EEPROM WRITE BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write ;Enable Interrupts ;Disable writes ;Wait for write to complete ;Done FIGURE 12-1: GIE WR GIE WREN WR FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR Flash Data PC PC + 1 INSTR (PC) INSTR(PC - 1) executed here EEADRH,EEADRL INSTR (PC + 1) BSF PMCON1,RD executed here PC +3 PC+3 EEDATH,EEDATL INSTR(PC + 1) executed here PC + 5 PC + 4 INSTR (PC + 3) Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDATL Register  2013-2015 Microchip Technology Inc. DS40001675C-page 118 PIC16(L)F1788/9 12.3 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software. Flash program memory may only be written or erased if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT of Configuration Words. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the EEDATH:EEDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. The number of data write latches may not be equivalent to the number of row locations. During programming, user software may need to fill the set of write latches and initiate a programming operation multiple times in order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. 12.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair. Clear the CFGS bit of the EECON1 register. Set the EEPGD control bit of the EECON1 register. Then, set control bit RD of the EECON1 register. 2. 3. 4. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored. The data is available in the very next cycle, in the EEDATH:EEDATL register pair; therefore, it can be read as two bytes in the following instructions. EEDATH:EEDATL register pair will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. The size of a program memory row and the number of program memory write latches may vary by device. See Table 12-1 for details. TABLE 12-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16(L)F1788/9 DS40001675C-page 119 Erase Block (Row) Size/Boundary Number of Write Latches/Boundary 32 words, EEADRL = 00000 32 words, EEADRL = 00000  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 EXAMPLE 12-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF BCF BSF NOP NOP BSF EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; ; Do not select Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 12-1) Ignored (Figure 12-1) Restore interrupts MOVF MOVWF MOVF MOVWF EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location  2013-2015 Microchip Technology Inc. DS40001675C-page 120 PIC16(L)F1788/9 12.3.2 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE, and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation. Poll the FREE bit in the EECON1 register to determine when the row erase has completed. See Example 12-4. After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. 12.3.3 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the starting address of the word(s) to be programmed. Load the write latches with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 12-2 (block writes to program memory with 32 write latches) for more details. The write latches are aligned to the address boundary defined by EEADRL as shown in Table 12-1. Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF. The following steps should be completed to load the write latches and program a block of program memory. These steps are divided into two parts. First, all write latches are loaded with data except for the last program memory location. Then, the last write latch is loaded and the programming sequence is initiated. A special DS40001675C-page 121 unlock sequence is required to load a write latch with data or initiate a Flash programming operation. This unlock sequence should not be interrupted. 1. Set the EEPGD and WREN bits of the EECON1 register. 2. Clear the CFGS bit of the EECON1 register. 3. Set the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the EEADRH:EEADRL register pair with the address of the location to be written. 5. Load the EEDATH:EEDATL register pair with the program memory data to be written. 6. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The write latch is now loaded. 7. Increment the EEADRH:EEADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is ‘0’, the write sequence will initiate the write to Flash program memory. 10. Load the EEDATH:EEDATL register pair with the program memory data to be written. 11. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The entire latch block is now written to Flash program memory. It is not necessary to load the entire write latch block with user program data. However, the entire write latch block will be written to program memory. An example of the complete write sequence for eight words is shown in Example 12-5. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 WRITE instruction.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 12-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 7 5 0 0 7 EEDATH EEDATA 8 6 Last word of block to be written First word of block to be written 14 EEADRL = 00000 14 EEADRL = 00001 14 EEADRL = 00010 Buffer Register Buffer Register 14 EEADRL = 11111 Buffer Register Buffer Register Program Memory EXAMPLE 12-4: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BSF BCF BSF BSF INTCON,GIE EEADRL ADDRL,W EEADRL ADDRH,W EEADRH EECON1,EEPGD EECON1,CFGS EECON1,FREE EECON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP 55h EECON2 0AAh EECON2 EECON1,WR NOP ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; ; ; ; Point to program memory Not configuration space Specify an erase operation Enable writes ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase Any instructions here are ignored as processor halts to begin erase sequence Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction BCF BSF EECON1,WREN INTCON,GIE  2013-2015 Microchip Technology Inc. ; Disable writes ; Enable interrupts DS40001675C-page 122 PIC16(L)F1788/9 EXAMPLE 12-5: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 0000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF INTCON,GIE EEADRH ADDRH,W EEADRH ADDRL,W EEADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ EEDATL FSR0++ EEDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO EEADRL,W 0x0F 0x0F STATUS,Z START_WRITE ; Check if lower bits of address are '000' ; Check if we're on the last of 16 addresses ; ; Exit if last of 16 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; Load initial data address Load initial data address Point to program memory Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP EEADRL,F LOOP ; Still loading latches Increment address ; Write next latches EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; NOP BCF BSF DS40001675C-page 123 EECON1,WREN INTCON,GIE Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 EXAMPLE 12-6: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 0000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF INTCON,GIE EEADRH ADDRH,W EEADRH ADDRL,W EEADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ EEDATL FSR0++ EEDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO EEADRL,W 0x0F 0x0F STATUS,Z START_WRITE ; Check if lower bits of address are '000' ; Check if we're on the last of 16 addresses ; ; Exit if last of 16 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; Load initial data address Load initial data address Point to program memory Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP EEADRL,F LOOP ; Still loading latches Increment address ; Write next latches EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; NOP BCF BSF EECON1,WREN INTCON,GIE  2013-2015 Microchip Technology Inc. Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts DS40001675C-page 124 PIC16(L)F1788/9 12.4 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. Repeat steps 6 and 7 as many times as required to reprogram the erased row. TABLE 12-2: 12.5 User ID, Device ID and Configuration Word Access Instead of accessing program memory or EEPROM data memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the EECON1 register. This is the region that would be pointed to by PC = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 12-2. When read access is initiated on an address outside the parameters listed in Table 12-2, the EEDATH:EEDATL register pair is cleared. USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function Read Access Write Access 8000h-8003h 8005h 8006h 8007h-8008h User IDs Revision ID Device ID Configuration Words 1 and 2 Yes Yes Yes No Yes No EXAMPLE 12-7: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF EEADRL PROG_ADDR_LO EEADRL EEADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF EECON1,CFGS INTCON,GIE EECON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 12-1) Ignored (See Figure 12-1) Restore interrupts MOVF MOVWF MOVF MOVWF EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS40001675C-page 125  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 12.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 12-8) to the desired value to be written. Example 12-8 shows how to verify a write to EEPROM. EXAMPLE 12-8: EEPROM WRITE VERIFY BANKSEL EEDATL MOVF EEDATL, W BSF XORWF BTFSS GOTO : ; ;EEDATL not changed ;from previous write EECON1, RD ;YES, Read the ;value written EEDATL, W ; STATUS, Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue  2013-2015 Microchip Technology Inc. DS40001675C-page 126 PIC16(L)F1788/9 12.7 Register Definitions: EEPROM and Flash Control REGISTER 12-1: R/W-x/u EEDATL: EEPROM DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 12-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDAT: Read/write value for Most Significant bits of program memory REGISTER 12-3: R/W-0/0 EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR: Specifies the Least Significant bits for program memory address or EEPROM address REGISTER 12-4: U-1 EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 —(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 Note EEADR: Specifies the Most Significant bits for program memory address or EEPROM address 1: Unimplemented, read as ‘1’. DS40001675C-page 127  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 12-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID registers 0 = Accesses Flash program or data EEPROM memory bit 5 LWLO: Load Write Latches Only bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after completion of erase). 0 = Performs a write operation on the next WR command. If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read.  2013-2015 Microchip Technology Inc. DS40001675C-page 128 PIC16(L)F1788/9 REGISTER 12-6: W-0/0 EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section 12.2.2 “Writing to the Data EEPROM Memory” for more information. TABLE 12-3: Name EECON1 SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page EEPGD CFGS LWLO FREE WRERR WREN WR RD 128 EECON2 EEPROM Control Register 2 (not a physical register) 129* EEADRL EEADRL 127 EEADRH (1) — EEADRH EEDATL 127 EEDATL 127 EEDATH — — INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF PIE2 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 99 PIR2 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 103 Legend: * 2: EEDATH 127 97 — = unimplemented location, read as ‘0’. Shaded cells are not used by data EEPROM module. Page provides register information. Unimplemented, read as ‘1’. DS40001675C-page 129  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.0 I/O PORTS FIGURE 13-1: GENERIC I/O PORT OPERATION Each port has three standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) Read LATx D Some ports may have one or more of the following additional registers. These registers are: • ANSELx (analog select) • WPUx (weak pull-up) Q CK VDD Data Register In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. PORTC ● ● ● PIC16(L)F1789 ● ● ● I/O pin Read PORTx To digital peripherals ANSELx VSS PORTE PORTB PIC16(L)F1788 PORTD Device Data Bus To analog peripherals PORT AVAILABILITY PER DEVICE PORTA TABLE 13-1: Write LATx Write PORTx TRISx ● ● ● The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 13-1.  2013-2015 Microchip Technology Inc. DS40001675C-page 130 PIC16(L)F1788/9 13.1 Alternate Pin Function The Alternate Pin Function Control (APFCON1 and APFCON2) registers are used to steer specific peripheral input and output functions between different pins. The APFCON1 and APFCON2 registers are shown in Register 13-1 and Register 13-2. For this device family, the following functions can be moved between different pins. • • • • • • • • • C2OUT output CCP1 output SDO output SCL/SCK output SDA/SDI output TX/RX output CCP2 output CCP3 output SS input These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS40001675C-page 131  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.2 Register Definitions: Alternate Pin Function Control REGISTER 13-1: APFCON1: ALTERNATE PIN FUNCTION CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 C2OUTSEL CCP1SEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUTSEL: C2OUT Pin Selection bit 1 = C2OUT is on pin RA6 0 = C2OUT is on pin RA5 bit 6 CCP1SEL: CCP1 Input/Output Pin Selection bit 1 = CCP1 is on pin RB0 0 = CCP1 is on pin RC2 bit 5 SDOSEL: MSSP SDO Pin Selection bit 1 = SDO is on pin RB5 0 = SDO is on pin RC5 bit 4 SCKSEL: MSSP Serial Clock (SCL/SCK) Pin Selection bit 1 = SCL/SCK is on pin RB7 0 = SCL/SCK is on pin RC3 bit 3 SDISEL: MSSP Serial Data (SDA/SDI) Output Pin Selection bit 1 = SDA/SDI is on pin RB6 0 = SDA/SDI is on pin RC4 bit 2 TXSEL: TX Pin Selection bit 1 = TX is on pin RB6 0 = TX is on pin RC6 bit 1 RXSEL: RX Pin Selection bit 1 = RX is on pin RB7 0 = RX is on pin RC7 bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 1 = CCP2 is on pin RB3 0 = CCP2 is on pin RC1  2013-2015 Microchip Technology Inc. DS40001675C-page 132 PIC16(L)F1788/9 REGISTER 13-2: APFCON2: ALTERNATE PIN FUNCTION CONTROL 2 REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/0 R/W-0/0 SSSEL R/W-0/0 CCP3SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-1 SSSEL: Slave Select Pin Selection bits 1x = SS is on pin RB4 01 = SS is on pin RA0 00 = SS is on pin RA5 bit 0 CCP3SEL: CCP3 Input/Output Pin Selection bit 1 = CCP3 is on pin RB5 PIC16(L)F1788 devices: 0 = CCP3 is on pin RC6 PIC16(L)F1789 devices: 0 = CCP3 is on pin RE0 DS40001675C-page 133  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.3 13.3.1 PORTA Registers DATA REGISTER PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 13-4). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). Example 13-1 shows how to initialize PORTA. 13.3.5 The INLVLA register (Register 13-10) controls the input voltage threshold for each of the available PORTA input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Section TABLE 31-1: “Supply Voltage” for more information on threshold levels. Note: Reading the PORTA register (Register 13-3) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 13.3.2 DIRECTION CONTROL The TRISA register (Register 13-4) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 13.3.3 OPEN-DRAIN CONTROL The ODCONA register (Register 13-8) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONA bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONA bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 13.3.4 SLEW RATE CONTROL The SLRCONA register (Register 13-9) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONA bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum rate possible.  2013-2015 Microchip Technology Inc. INPUT THRESHOLD CONTROL 13.3.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELA register (Register 13-6) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. EXAMPLE 13-1: ; ; ; ; INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA as inputs ;and set RA as ;outputs DS40001675C-page 134 PIC16(L)F1788/9 13.3.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 13-2. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, and comparator inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown in the priority list. TABLE 13-2: PORTA OUTPUT PRIORITY Pin Name Function Priority(1) RA0 RA0 RA1 OPA1OUT RA1 RA2 DAC1OUT1 RA2 RA3 RA3 RA4 C1OUT RA4 RA5 C2OUT RA5 RA6 CLKOUT C2OUT RA6 RA7 Note 1: RA7 Priority listed from highest to lowest. DS40001675C-page 135  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.4 Register Definitions: PORTA REGISTER 13-3: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RA: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 13-4: TRISA: PORTA TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISA: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output REGISTER 13-5: LATA: PORTA DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Note 1: LATA: PORTA Output Latch Value bits(1) Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values.  2013-2015 Microchip Technology Inc. DS40001675C-page 136 PIC16(L)F1788/9 REGISTER 13-6: ANSELA: PORTA ANALOG SELECT REGISTER R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 5 ANSA7: Analog Select between Analog or Digital Function on pins RA7, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 6 Unimplemented: Read as ‘0’ bit 5-0 ANSA: Analog Select between Analog or Digital Function on pins RA, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 13-7: WPUA: WEAK PULL-UP PORTA REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUA: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. DS40001675C-page 137  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 13-8: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODA: PORTA Open-Drain Enable bits For RA pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 13-9: SLRCONA: PORTA SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SLRA: PORTA Slew Rate Enable bits For RA pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 13-10: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLA: PORTA Input Level Select bits For RA pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change  2013-2015 Microchip Technology Inc. DS40001675C-page 138 PIC16(L)F1788/9 TABLE 13-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 137 INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 138 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 136 ODA2 ODA1 ODA0 Name LATA ODCONA OPTION_REG PORTA SLRCONA ODA7 ODA6 ODA5 ODA4 ODA3 WPUEN INTEDG TMR0CS TMR0SE PSA 138 PS 208 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 136 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 138 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 136 WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 137 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. TABLE 13-4: Name CONFIG1 Legend: Bits SUMMARY OF CONFIGURATION WORD WITH PORTA Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 — — FCMEN 7:0 CP MCLRE PWRTE Bit 10/2 WDTE Bit 9/1 BOREN FOSC Bit 8/0 CPD Register on Page 58 — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. DS40001675C-page 139  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.5 13.5.1 PORTB Registers DATA REGISTER PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 13-12). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 13-1 shows how to initialize an I/O port. 13.5.5 The INLVLB register (Register 13-18) controls the input voltage threshold for each of the available PORTB input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTB register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Section TABLE 31-1: “Supply Voltage” for more information on threshold levels. Note: Reading the PORTB register (Register 13-11) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB). 13.5.2 DIRECTION CONTROL The TRISB register (Register 13-12) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 13.5.3 OPEN-DRAIN CONTROL The ODCONB register (Register 13-16) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONB bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONB bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 13.5.4 INPUT THRESHOLD CONTROL 13.5.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELB register (Register 13-14) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. SLEW RATE CONTROL The SLRCONB register (Register 13-17) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONB bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONB bit is cleared, The corresponding port pin drive slews at the maximum rate possible.  2013-2015 Microchip Technology Inc. DS40001675C-page 140 PIC16(L)F1788/9 13.5.7 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 13-5. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. TABLE 13-5: PORTB OUTPUT PRIORITY Pin Name Function Priority(1) RB0 CCP1 RB0 RB1 OPA2OUT RB1 RB2 CLKR RB2 RB3 CCP2 RB3 RB4 RB4 RB5 SDO C3OUT CCP3 RB5 RB6 ICSPCLK SDA TX/CK RB6 RB7 ICSPDAT DAC1OUT2 SCL/SCK DT RB7 Note 1: Priority listed from highest to lowest. DS40001675C-page 141  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.6 Register Definitions: PORTB REGISTER 13-11: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RB: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 13-12: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISB: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output REGISTER 13-13: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: LATB: PORTB Output Latch Value bits(1) Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values.  2013-2015 Microchip Technology Inc. DS40001675C-page 142 PIC16(L)F1788/9 REGISTER 13-14: ANSELB: PORTB ANALOG SELECT REGISTER U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-0 ANSB: Analog Select between Analog or Digital Function on pins RB, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 13-15: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUB: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. DS40001675C-page 143  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 13-16: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODB: PORTB Open-Drain Enable bits For RB pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 13-17: SLRCONB: PORTB SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SLRB: PORTB Slew Rate Enable bits For RB pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 13-18: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLB: PORTB Input Level Select bits For RB pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change  2013-2015 Microchip Technology Inc. DS40001675C-page 144 PIC16(L)F1788/9 TABLE 13-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 143 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 144 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 142 ODCONB ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 144 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 142 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 144 Name ANSELB INLVLB PORTB SLRCONB TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 142 WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 143 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. DS40001675C-page 145  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.7 13.7.1 PORTC Registers DATA REGISTER PORTC is an 8-bit wide bidirectional port. The corresponding data direction register is TRISC (Register 13-20). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 13-1 shows how to initialize an I/O port. Reading the PORTC register (Register 13-19) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). 13.7.2 DIRECTION CONTROL The TRISC register (Register 13-20) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 13.7.3 OPEN-DRAIN CONTROL The ODCONC register (Register 13-23) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONC bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONC bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 13.7.4 Note: 13.7.6 INPUT THRESHOLD CONTROL The INLVLC register (Register 13-25) controls the input voltage threshold for each of the available PORTC input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTC register and also the PORTC FUNCTIONS AND OUTPUT PRIORITIES TABLE 13-7: PORTC OUTPUT PRIORITY Pin Name Function Priority(1) RC0 T1OSO PSMC1A RC0 RC1 PSMC1B CCP2 RC1 RC2 PSMC1C CCP1 RC2 RC3 PSMC1D SCL SCK RC3 RC4 PSMC1E SDA RC4 RC5 PSMC1F SDO RC5 RC6 PSMC2A TX/CK CCP3 RC6 RC7 PSMC2B DT RC7 Note 1:  2013-2015 Microchip Technology Inc. Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 13-7. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. SLEW RATE CONTROL The SLRCONC register (Register 13-24) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONC bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONC bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 13.7.5 level at which an interrupt-on-change occurs, if that feature is enabled. See Section TABLE 31-1: “Supply Voltage” for more information on threshold levels. Priority listed from highest to lowest. DS40001675C-page 146 PIC16(L)F1788/9 13.8 Register Definitions: PORTC REGISTER 13-19: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RC: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. REGISTER 13-20: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISC: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output REGISTER 13-21: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: LATC: PORTC Output Latch Value bits(1) Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. DS40001675C-page 147  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 13-22: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUC: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. REGISTER 13-23: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODC: PORTC Open-Drain Enable bits For RC pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 13-24: SLRCONC: PORTC SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SLRC: PORTC Slew Rate Enable bits For RC pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate  2013-2015 Microchip Technology Inc. DS40001675C-page 148 PIC16(L)F1788/9 REGISTER 13-25: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLC: PORTC Input Level Select bits For RC pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change TABLE 13-8: Name LATC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 147 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 147 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 147 WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 148 INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 149 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 147 ODCONC ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 148 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 147 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 148 PORTC SLRCONC Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. DS40001675C-page 149  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.9 13.9.1 PORTD Registers (PIC16(L)F1789 only) DATA REGISTER PORTD is an 8-bit wide bidirectional port. The corresponding data direction register is TRISD (Register 13-27). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 13-1 shows how to initialize an I/O port. Reading the PORTD register (Register 13-26) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATD). 13.9.2 DIRECTION CONTROL The TRISD register (Register 13-27) controls the PORTD pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISD register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 13.9.3 OPEN-DRAIN CONTROL The ODCOND register (Register 13-31) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCOND bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCOND bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 13.9.4 SLEW RATE CONTROL The SLRCOND register (Register 13-32) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCOND bit is set, the corresponding port pin drive is slew rate limited. When an SLRCOND bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 13.9.5 The INLVLD register (Register 13-33) controls the input voltage threshold for each of the available PORTD input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTD register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Section 31.3 “DC Characteristics” for more information on threshold levels. Note: 13.9.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. PORTD FUNCTIONS AND OUTPUT PRIORITIES Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 13-9. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. TABLE 13-9: PORTD OUTPUT PRIORITY Pin Name Function Priority(1) RD0 RD0 RD1 OPA3OUT RD1 RD2 RD2 RD3 PSMC4A RD3 RD4 PSMC3F RD4 RD5 PSMC3E RD5 RD6 PSMC3D C3OUT RD6 RD7 PSMC3C C4OUT RD7 Note 1:  2013-2015 Microchip Technology Inc. INPUT THRESHOLD CONTROL Priority listed from highest to lowest. DS40001675C-page 150 PIC16(L)F1788/9 13.10 Register Definitions: PORTD REGISTER 13-26: PORTD: PORTD REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RD: PORTD General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. REGISTER 13-27: TRISD: PORTD TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 TRISD: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output REGISTER 13-28: LATD: PORTD DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: LATD: PORTD Output Latch Value bits(1) Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. DS40001675C-page 151  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 13-29: ANSELD: PORTD ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — — — ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSD: Analog Select between Analog or Digital Function on pins RD, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 13-30: WPUD: WEAK PULL-UP PORTD REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: WPUD: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output.  2013-2015 Microchip Technology Inc. DS40001675C-page 152 PIC16(L)F1788/9 REGISTER 13-31: ODCOND: PORTD OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ODD: PORTD Open-Drain Enable bits For RD pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) REGISTER 13-32: SLRCOND: PORTD SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SLRD: PORTD Slew Rate Enable bits For RD pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 13-33: INLVLD: PORTD INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 INLVLD: PORTD Input Level Select bits For RD pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change DS40001675C-page 153  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 13-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — — — ANSD2 ANSD1 ANSD0 152 INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 151 ODCOND ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 153 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 151 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 153 Name ANSELD INLVLD PORTD SLRCOND INLVLD1 INLVLD0 153 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 151 WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 152 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.  2013-2015 Microchip Technology Inc. DS40001675C-page 154 PIC16(L)F1788/9 13.11 PORTE Registers RE3 is input only, and also functions as MCLR. The MCLR feature can be disabled via a configuration fuse. RE3 also supplies the programming voltage. The TRIS bit for RE3 (TRISE3) always reads ‘1’. 13.11.1 Reading the PORTE register (Register 13-34) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATE). DIRECTION CONTROL The TRISE register (Register 13-35) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 13.11.3 Note: DATA REGISTER PORTE is an 8-bit wide bidirectional port. The corresponding data direction register is TRISE (Register 13-35). Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 13-1 shows how to initialize an I/O port. 13.11.2 level at which an interrupt-on-change occurs, if that feature is enabled. See Section 31.3 “DC Characteristics” for more information on threshold levels. 13.11.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. INPUT THRESHOLD CONTROL The INLVLE register (Register 13-41) controls the input voltage threshold for each of the available PORTE input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTE register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Section TABLE 31-1: “Supply Voltage” for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. OPEN-DRAIN CONTROL The ODCONE register (Register 13-31) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONE bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONE bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 13.11.4 SLEW RATE CONTROL The SLRCOND register (Register 13-32) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCOND bit is set, the corresponding port pin drive is slew rate limited. When an SLRCOND bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 13.11.5 INPUT THRESHOLD CONTROL The INLVLD register (Register 13-33) controls the input voltage threshold for each of the available PORTD input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTD register and also the DS40001675C-page 155  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 13.11.7 PORTE FUNCTIONS AND OUTPUT PRIORITIES(1) Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 13-11. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. Note 1: Applies to 40/44-pin devices only. TABLE 13-11: PORTE OUTPUT PRIORITY Function Priority(1) Pin Name RE0 CCP3 RE0 RE1 PSMC3B RE1 RE2 PSMC3A RE2 Note 1: Priority listed from highest to lowest.  2013-2015 Microchip Technology Inc. DS40001675C-page 156 PIC16(L)F1788/9 13.12 Register Definitions: PORTE REGISTER 13-34: PORTE: PORTE REGISTER U-0 U-0 — — U-0 — U-0 — R-x/u R/W-x/u RE3 RE2(1) R/W-x/u RE1 (1) bit 7 R/W-x/u RE0(1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RE: PORTE Input Pin bit(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: RE are available on PIC16(L)F1789 only. REGISTER 13-35: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 — — U-0 — U-0 — U-1(1) R/W-1/1 R/W-1/1 R/W-1/1 — TRISE2(2) TRISE1(2) TRISE0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘1’ bit 2-0 TRISA: PORTA Tri-State Control bit(2) 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: 2: Unimplemented, read as ‘1’. TRISE are available on PIC16(L)F1789 only. DS40001675C-page 157  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 13-36: LATE: PORTE DATA LATCH REGISTER(2) U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATE: PORTE Output Latch Value bits(2) Note 1: 2: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is return of actual I/O pin values. LATE are available on PIC16(L)F1789 only. REGISTER 13-37: ANSELE: PORTE ANALOG SELECT REGISTER(2) U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — — — ANSE2 ANSE1 ANSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE: Analog Select between Analog or Digital Function on pins RE, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Note 1: 2: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. ANSELE are available on PIC16(L)F1789 only.  2013-2015 Microchip Technology Inc. DS40001675C-page 158 PIC16(L)F1788/9 REGISTER 13-38: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — — — WPUE3 WPUE2(3) WPUE1(3) WPUE0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WPUE: Weak Pull-up Register bit(3) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: 3: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. WPUSE are available on PIC16(L)F1789 only. REGISTER 13-39: ODCONE: PORTE OPEN-DRAIN CONTROL REGISTER(1) U-0 U-0 — — U-0 — U-0 — U-0 R/W-0/0 R/W-0/0 R/W-0/0 — ODE2 ODE1 ODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ODE: PORTE Open-Drain Enable bits For RE pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) Note 1: ODCONE are available on PIC16(L)F1789 only. DS40001675C-page 159  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 13-40: SLRCONE: PORTE SLEW RATE CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — SLRE2 SLRE1 SLRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 SLRE: PORTE Slew Rate Enable bits For RE pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate Note 1: SLRE are available on PIC16(L)F1789 only. REGISTER 13-41: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER U-0 U-0 — U-0 — — U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — INLVLE3 INLVLE2(1) INLVLE1(1) INLVLE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 INLVLE: PORTE Input Level Select bit(1) 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change Note 1: INLVLE are available on PIC16(L)F1789 only. TABLE 13-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 ADCON0 ADRMD ANSELE — Bit 6 Bit 5 — — Bit 4 Bit 3 Bit 2 — ANSE2 CHS — Register on Page GO/DONE ADON 177 ANSE1 ANSE0 (2) (2) (2) 158 INLVLE — — — — INLVLE3 INLVLE1 INLVLE0 160 LATE(2) — — — — — LATE2 LATE1 LATE0 158 ODCONE(2) — — — — — ODE2 ODE1 ODE0 159 PORTE — — — — RE3 RE2(2) RE1(2) RE0(2) 157 SLRCONE(2) — — — — — SLRE2 SLRE1 SLRE0 160 TRISE — — — — —(1) TRISE2(2) TRISE1(2) TRISE0(2) 157 WPUE — — — — WPUE3 WPUE2(2) WPUE1(2) WPUE0(2) 159 Legend: Note 1: 2: INLVLE2 Bit 0 Bit 1 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Unimplemented, read as ‘1’. PIC16(L)F1789 only  2013-2015 Microchip Technology Inc. DS40001675C-page 160 PIC16(L)F1788/9 14.0 INTERRUPT-ON-CHANGE All pins on the selected ports can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual pin, or combination of pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: • • • • Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags Figure 14-1 is a block diagram of the IOC module. 14.1 Enabling the Module To allow individual pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 14.3 Interrupt Flags The bits located in the IOCxF registers are status flags that correspond to the Interrupt-on-change pins of each port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCxF bits. 14.4 Clearing Interrupt Flags The individual status flags, (IOCxF register bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 14-1: 14.2 Individual Pin Configuration For each pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in both of the IOCxP and IOCxN registers. MOVLW XORWF ANDWF 14.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the affected IOCxF register will be updated prior to the first instruction executed out of Sleep.  2013-2015 Microchip Technology Inc. DS40001675C-page 161 PIC16(L)F1788/9 FIGURE 14-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx D Q4Q1 Q CK edge detect R RBx IOCBPx D data bus = 0 or 1 Q write IOCBFx CK D S Q to data bus IOCBFx CK IOCIE R Q2 from all other IOCBFx individual pin detectors Q1 Q3 Q4 Q4Q1 DS40001675C-page 162 Q1 Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 IOC interrupt to CPU core Q3 Q4 Q4 Q4Q1 Q4Q1  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 14.6 Register Definitions: Interrupt-on-Change Control REGISTER 14-1: IOCxP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCxP7 IOCxP6 IOCxP5 IOCxP4 IOCxP3 IOCxP2 IOCxP1 IOCxP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared IOCxP: Interrupt-on-Change Positive Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 7-0 Note 1: For IOCEP register, bit 3 (IOCEP3) is the only implemented bit in the register. REGISTER 14-2: IOCxN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCxN7 IOCxN6 IOCxN5 IOCxN4 IOCxN3 IOCxN2 IOCxN1 IOCxN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: IOCxN: Interrupt-on-Change Negative Edge Enable bits(1) 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. For IOCEN register, bit 3 (IOCEN3) is the only implemented bit in the register.  2013-2015 Microchip Technology Inc. DS40001675C-page 163 PIC16(L)F1788/9 REGISTER 14-3: IOCxF: INTERRUPT-ON-CHANGE FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 IOCxF7 IOCxF6 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCxF5 IOCxF4 IOCxF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCxF2 IOCxF1 IOCxF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware IOCxF: Interrupt-on-Change Flag bits(1) 1 = An enabled change was detected on the associated pin. Set when IOCxPx = 1 and a rising edge was detected RBx, or when IOCxNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. bit 7-0 Note 1: For IOCEF register, bit 3 (IOCEF3) is the only implemented bit in the register. TABLE 14-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 ANSELB — INTCON GIE IOCAF Bit 2 Bit 1 Bit 0 Register on Page ANSB3 ANSB2 ANSB1 ANSB0 143 IOCIE TMR0IF INTF IOCIF 97 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 164 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 163 Bit 5 Bit 4 Bit 3 ANSB6 ANSB5 ANSB4 PEIE TMR0IE INTE IOCAF7 IOCAF6 IOCAF5 IOCAN IOCAN7 IOCAN6 IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 163 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 164 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 163 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 163 164 IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 163 IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 163 IOCEF — — — — IOCEF3 — — — 164 IOCEN — — — — IOCEN3 — — — 163 IOCEP — — — — IOCEP3 — — — 163 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 142 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. DS40001675C-page 164  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 15.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the FVRCON register. 15.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 17.0 “Analog-to-Digital Converter (ADC) Module” for additional information. The CDAFVR bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator Section 19.0 “8-Bit module. Reference Digital-to-Analog Converter (DAC) Module” and Section 21.0 “Comparator Module” for additional information. 15.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 31.0 “Electrical Specifications” for the minimum delay requirement. 15.3 FVR Buffer Stabilization Period When either FVR Buffer1 or FVR Buffer 2 is enabled, the buffer amplifier circuits require 30 s to stabilize. This stabilization time is required even when the FVR is already operating and stable.  2013-2015 Microchip Technology Inc. DS40001675C-page 165 PIC16(L)F1788/9 FIGURE 15-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR CDAFVR 2 X1 X2 X4 FVR BUFFER1 (To ADC Module) X1 X2 X4 FVR BUFFER2 (To Comparators, DAC) 2 HFINTOSC Enable HFINTOSC To BOR, LDO FVREN + _ FVRRDY Any peripheral requiring the Fixed Reference (See Table 15-1) TABLE 15-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC Conditions Description FOSC = 100 and IRCF  000x INTOSC is active and device is not in Sleep BOREN = 11 BOR always enabled BOR BOREN = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled LDO All PIC16F1788/9 devices, when VREGPM = 1 and not in Sleep The device runs off of the ULP regulator when in Sleep mode. PSMC 64 MHz PxSRC DS40001675C-page 166 64 MHz clock forces HFINTOSC on during Sleep.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 15.4 Register Definitions: FVR Control REGISTER 15-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG R/W-0/0 R/W-0/0 R/W-0/0 CDAFVR R/W-0/0 ADFVR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR: Comparator and DAC Fixed Voltage Reference Selection bit 11 = Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 = Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 = Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 = Comparator and DAC Fixed Voltage Reference Peripheral output is off. bit 1-0 ADFVR: ADC Fixed Voltage Reference Selection bit 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 = ADC Fixed Voltage Reference Peripheral output is off. Note 1: 2: 3: FVRRDY is always ‘1’ on “F” devices only. Fixed Voltage Reference output cannot exceed VDD. See Section 16.0 “Temperature Indicator Module” for additional information. TABLE 15-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR Bit 1 Bit 0 ADFVR Register on page 167 Shaded cells are not used with the Fixed Voltage Reference.  2013-2015 Microchip Technology Inc. DS40001675C-page 167 PIC16(L)F1788/9 16.0 TEMPERATURE INDICATOR MODULE FIGURE 16-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. TEMPERATURE CIRCUIT DIAGRAM VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 16.1 Circuit Operation Figure 16-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 16-1 describes the output characteristics of the temperature indicator. EQUATION 16-1: VOUT RANGES VOUT 16.2 To ADC Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 16-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT TABLE 16-1: Low Range: VOUT = VDD - 2VT The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 15.0 “Fixed Voltage Reference (FVR)” for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for lowvoltage operation.  2013-2015 Microchip Technology Inc. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 16.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 17.0 “Analog-to-Digital Converter (ADC) Module” for detailed information. 16.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. DS40001675C-page 168 PIC16(L)F1788/9 TABLE 16-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG — — Bit 1 Bit 0 ADFVR Register on page 166 Shaded cells are unused by the temperature indicator module. DS40001675C-page 169  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 17.0 the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 17-1 shows the block diagram of the ADC. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of a single-ended and differential analog input signals to a 12-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 12-bit binary result via successive approximation and stores FIGURE 17-1: The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ADC BLOCK DIAGRAM ADPREF = 11 VDD ADPREF = 00 VREF+ AN0 00000 AN1 00001 VREF-/AN2 00010 VREF+/AN3 00011 AN4 00100 AN5(1) 00101 AN6(1) 00110 AN7(1) 00111 AN8 01000 AN9 01001 AN10 01010 AN11 01011 AN12 01100 AN13 01101 ADPREF = 01 ADNREF = 1 ADPNEF = 0 Ref+ Ref+ ADC GO/DONE 10101 DAC4_output 11000 DAC3_output 11001 DAC2_output 11100 DAC1_output Temperature Indicator 11110 1 12 0 ADRMD ADFM (1) ADON 0 = Sign Magnitude 1 = 2’s Complement 16 VSS AN21(1) 10 ADRESH ADRESL 11101 11111 FVR Buffer1 CHS(2) CHSN Note 1: 2: When ADON = 0, all multiplexer inputs are disconnected. PIC16(L)F1789 only. See ADCON0 register (Register 17-1) and ADCON2 register (Register 17-3) for detailed analog channel selection per device.  2013-2015 Microchip Technology Inc. DS40001675C-page 170 PIC16(L)F1788/9 17.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection - Single-ended - Differential • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Result formatting 17.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 13.0 “I/O Ports” for more information. Note: 17.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION There are up to 18 channel selections available: • • • • • AN pins (PIC16(L)F1788 only) AN pins (PIC16(L)F1789 only) Temperature Indicator DAC_output FVR (Fixed Voltage Reference) Output Refer to Section 15.0 “Fixed Voltage Reference (FVR)” and Section 16.0 “Temperature Indicator Module” for more information on these channel selections. When converting differential signals, the negative input for the channel is selected with the CHSN bits of the ADCON2 register. Any positive input can be paired with any negative input to determine the differential channel. 17.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provide control of the positive voltage reference. The positive voltage reference can be: • VREF+ • VDD • FVR Buffer1 The ADNREF bits of the ADCON1 register provide control of the negative voltage reference. The negative voltage reference can be: • VREF- pin • VSS See Section 15.0 “Fixed Voltage Reference (FVR)” for more details on the Fixed Voltage Reference. 17.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • • • • • • • FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal FRC oscillator) The time to complete one bit conversion is defined as TAD. One full 12-bit conversion requires 15 TAD periods as shown in Figure 17-2. For correct conversion, the appropriate TAD specification must be met. Refer to the ADC conversion requirements in Section 31.0 “Electrical Specifications” for more information. Table 17-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. The CHS bits of the ADCON0 register determine which positive channel is selected. When CHSN = 1111 then the ADC is effectively a single ended ADC converter. When changing channels, a delay is required before starting the next conversion. DS40001675C-page 171  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 17-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 125 ns (2) (2) (2) (2) FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 800 ns 010 1.0 s FOSC/64 110 FRC x11 FOSC/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 1.0 s 2.0 s 4.0 s 16.0 s(3) 1.6 s 2.0 s 4.0 s 2.0 s 3.2 s 4.0 s 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 200 ns 250 ns 500 ns 8.0 s (3) 8.0 s 16.0 s (3) (3) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 17-2: TCY - TAD TAD1 ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 sign b11 b10 b9 b8 TAD8 b7 TAD9 TAD10 TAD11 TAD12 TAD13 TAD14 TAD15 TAD16 TAD17 b6 b5 b4 Conversion starts b3 b2 b1 b0 Holding cap. discharge Holding cap disconnected from input Set GO bit Input Sample On the following cycle: GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.  2013-2015 Microchip Technology Inc. DS40001675C-page 172 PIC16(L)F1788/9 17.1.5 INTERRUPTS 17.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit and 12-bit ADC conversion results can be supplied in two formats: 2’s complement or sign-magnitude. The ADFM bit of the ADCON1 register controls the output format. Sign magnitude is left justified with the sign bit in the LSb position. Negative numbers are indicated when the sign bit is ‘1’. Two’s complement is right justified with the sign extended into the Most Significant bits. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. Figure 17-3 shows the two output formats. Table 17-2 shows conversion examples. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 17-3: ADC CONVERSION RESULT FORMAT 12-bit sign and magnitude Bit 11 Bit 10 Bit 9 ADFM = 0 ADRMD = 0 Bit 8 Bit 7 Bit 6 Bit 5 bit 7 Bit 4 Bit 3 bit 0 bit 7 Bit 2 Bit 1 Bit 0 ‘0’ ‘0’ ‘0’ Sign bit 0 12-bit ADC Result Loaded with ‘0’ 12-bit 2’s compliment ADFM = 1 ADRMD = 0 Bit 12 Bit 12 Bit 12 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 bit 7 bit 0 bit 7 Loaded with Sign bits’ Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 0 12-bit ADC Result 10-bit sign and magnitude Bit 9 ADFM = 0 ADRMD = 1 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 bit 7 Bit 2 Bit 1 bit 0 bit 7 Bit 0 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Sign bit 0 Loaded with ‘0’ 10-bit ADC Result 10-bit 2’s compliment ADFM = 1 ADRMD = 1 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 9 Bit 8 Bit 7 bit 7 bit 0 bit 7 Loaded with Sign bits’ DS40001675C-page 173 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 0 10-bit ADC Result  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 17-2: ADC OUTPUT RESULTS FORMAT Absolute ADC Value (decimal) Sign and Magnitude Result ADFM = 0, ADRMD = 0 ADRESH (ADRES) ADRESL (ADRES) 2’s Compliment Result ADFM = 1, ADRMD = 0 ADRESH (ADRES) ADRESL (ADRES) + 4095 1111 1111 1111 0000 0000 1111 1111 1111 0000 1001 0011 0011 + 2355 1001 0011 0011 0000 + 0001 0000 0000 0001 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 - 0001 0000 0000 0001 0001 - 4095 1111 1111 1111 0001 1111 0000 0000 0001 - 4096 0000 0000 0000 0001 1111 0000 0000 0000 Note 1: For the RSD ADC, the raw 13-bits from the ADC is presented in 2’s compliment format, so no data translation is required for 2’s compliment results. 2: For the SAR ADC, the raw 13-bits from the ADC is presented in sign and magnitude format, so no data translation is required for sign and magnitude results  2013-2015 Microchip Technology Inc. DS40001675C-page 174 PIC16(L)F1788/9 17.2 17.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will clear the ADRESH and ADRESL registers and start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 17.2.6 “A/D Conversion Procedure”. 17.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the conversion is complete, the ADC module will: When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit 17.2.5 17.2.2 17.2.3 COMPLETION OF A CONVERSION TERMINATING A CONVERSION When a conversion is terminated before completion by clearing the GO/DONE bit then the partial results are discarded and the results in the ADRESH and ADRESL registers from the previous conversion remain unchanged. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. AUTO-CONVERSION TRIGGER The Auto-conversion Trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the GO/DONE bit is set by hardware. The Auto-conversion Trigger source is selected with the TRIGSEL bits of the ADCON2 register. Using the Auto-conversion Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. Auto-conversion sources are: • • • • • CCP1 CCP2 CCP3 PSMC1(1) PSMC2(1) Note: The PSMC clock frequency, after the prescaler, must be less than FOSC/4 to ensure that the ADC detects the auto-conversion trigger. This limitation can be overcome by synchronizing a slave PSMC, running at the required slower clock frequency, to the first PSMC and triggering the conversion from the slave PSMC. • PSMC3 • PSMC4 DS40001675C-page 175  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 17.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) • Disable weak pull-ups either globally (Refer to the OPTION_REG register) or individually (Refer to the appropriate WPUx register) Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 17-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock MOVWF ADCON1 ;Vdd and Vss Vref MOVLW B’00001111’ ;set negative input MOVWF ADCON2 ;to negative ;reference BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL WPUA ; BCF WPUA,0 ;Disable weak pull-up on RA0 BANKSEL ADCON0 ; MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 17.4 Acquisition Requirements”.  2013-2015 Microchip Technology Inc. “ADC DS40001675C-page 176 PIC16(L)F1788/9 17.3 Register Definitions: ADC Control REGISTER 17-1: R/W-0/0 ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 ADRMD R/W-0/0 R/W-0/0 R/W-0/0 CHS R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADRMD: ADC Result Mode bit 1 = ADRESL and ADRESH provide data formatted for a 10-bit result 0 = ADRESL and ADRESH provide data formatted for a 12-bit result See Figure 17-3 for details bit 6-2 CHS: Positive Differential Input Channel Select bits 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3) 11110 = DAC_output(2) 11101 = Temperature Indicator(4) 11100 = DAC2_output(5) 11011 = Reserved 11010 = Reserved 11001 = DAC3_output(5) 11000 = DAC4_output(5) • • • 10110 = Reserved. No channel connected 10101 = AN21(1) 10100 = Reserved. No channel connected • • • 01110 = Reserved. No channel connected. 01101 = AN13 01100 = AN12 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = AN7(1) 00110 = AN6(1) 00101 = AN5(1) 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: 4: 5: PIC16(L)F1789 only. See Section 19.0 “8-Bit Digital-to-Analog Converter (DAC) Module” for more information. See Section 15.0 “Fixed Voltage Reference (FVR)” for more information. See Section 16.0 “Temperature Indicator Module” for more information. See Section 20.0 “5-bit Digital-to-Analog Converter (DAC2/3/4) Modules”for more information. DS40001675C-page 177  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 17-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS U-0 R/W-0/0 — ADNREF R/W-0/0 bit 7 R/W-0/0 ADPREF bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit (see Figure 17-3) 1 = 2’s complement format. 0 = Sign-magnitude result format. bit 6-4 ADCS: ADC Conversion Clock Select bits 111 = FRC (clock supplied from a dedicated FRC oscillator) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock supplied from a dedicated FRC oscillator) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: ADC Negative Voltage Reference Configuration bit 1 = VREF- is connected to external VREF- pin(1) 0 = VREF- is connected to VSS bit 1-0 ADPREF: ADC Positive Voltage Reference Configuration bits 11 = VREF+ is connected internally to FVR Buffer 1 10 = Reserved 01 = VREF+ is connected to VREF+ pin 00 = VREF+ is connected to VDD Note 1: When selecting the FVR or VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section 31.0 “Electrical Specifications” for details.  2013-2015 Microchip Technology Inc. DS40001675C-page 178 PIC16(L)F1788/9 REGISTER 17-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TRIGSEL R/W-0/0 R/W-0/0 R/W-0/0 CHSN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRIGSEL: ADC Auto-conversion Trigger Source Selection bits 1111 = PSMC4 Falling Match Event 1110 = PSMC4 Rising Match Event 1101 = PSMC4 Period Match Event 1001 = PSMC2 Falling Edge Event 1000 = PSMC2 Rising Edge Event 0111 = PSMC2 Period Match Event 0110 = PSMC1 Falling Edge Event 0101 = PSMC1 Rising Edge Event 0100 = PSMC1 Period Match Event 0011 = Reserved. Auto-conversion Trigger disabled. 0010 = CCP2, Auto-conversion Trigger 0001 = CCP1, Auto-conversion Trigger 0000 = Disabled bit 3-0 CHSN: Negative Differential Input Channel Select bits When ADON = 0, all multiplexer inputs are disconnected. 1111 = ADC Negative reference – selected by ADNREF 1110 = AN21(1) 1101 = AN13 1100 = AN12 1011 = AN11 1010 = AN10 1001 = AN9 1000 = AN8 0111 = AN7(1) 0110 = AN6(1) 0101 = AN5(1) 0100 = AN4 0011 = AN3 0010 = AN2 0001 = AN1 0000 = AN0 Note 1: PIC16(L)F1789 only. For PIC16(L)F1788, “Reserved. No channel connected.” DS40001675C-page 179  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 17-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u AD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD: ADC Result Register bits Upper eight bits of 12-bit conversion result REGISTER 17-5: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u AD R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — ADSIGN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 AD: ADC Result Register bits Lower four bits of 12-bit conversion result bit 3-1 Extended LSb bits: These are cleared to zero by DC conversion. bit 0 ADSIGN: ADC Result Sign bit  2013-2015 Microchip Technology Inc. DS40001675C-page 180 PIC16(L)F1788/9 REGISTER 17-6: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADSIGN R/W-x/u R/W-x/u R/W-x/u AD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 ADSIGN: Extended AD Result Sign bit bit 3-0 AD: ADC Result Register bits Most Significant four bits of 12-bit conversion result REGISTER 17-7: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u AD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 AD: ADC Result Register bits Least Significant eight bits of 12-bit conversion result DS40001675C-page 181  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 17.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 17-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 17-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 17-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (4,096 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k  5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2µs + T C +   Temperature - 25°C   0.05µs/°C   The value for TC can be approximated with the following equations: 1  = V CHOLD V AP P LI ED  1 – -------------------------n+1   2 –1 ;[1] VCHOLD charged to within 1/2 lsb –TC ----------  RC V AP P LI ED  1 – e  = V CHOLD   ;[2] VCHOLD charge response to VAPPLIED – Tc ---------  1 RC  ;combining [1] and [2] V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------n+1    2 –1 Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD  R IC + R SS + R S  ln(1/8191) = – 10pF  1k  + 7k  + 10k   ln(0.000122) = 1.62 µs Therefore: T A CQ = 2µs + 1.62µs +   50°C- 25°C   0.05 µs/°C   = 4.87µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: Maximum source impedance feeding the input pin should be considered so that the pin leakage does not cause a voltage divider, thereby limiting the absolute accuracy.  2013-2015 Microchip Technology Inc. DS40001675C-page 182 PIC16(L)F1788/9 FIGURE 17-4: ANALOG INPUT MODEL Rs VA VDD Analog Input pin VT  0.6V CPIN 5 pF VT  0.6V Sampling Switch SS Rss RIC  1k I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- Legend: CHOLD CPIN 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage RSS 5 6 7 8 9 10 11 Sampling Switch (k) Note 1: Refer to Section 31.0 “Electrical Specifications”. FIGURE 17-5: ADC TRANSFER FUNCTION Full-Scale Range FFFh FFEh ADC Output Code FFDh FFCh FFBh 03h 02h 01h 00h Analog Input Voltage (Positive input channel relative to negative 1.5 LSB input channel) 0.5 LSB VREF- DS40001675C-page 183 Zero-Scale Transition Full-Scale Transition VREF+  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 17-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 ADRMD ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 — ADNREF CHS ADCS TRIGSEL ADRESH A/D Result Register High ADRESL A/D Result Register Low Bit 1 Bit 0 Register on Page GO/DONE ADON 177 ADPREF CHSN 178 179 180, 181 180, 181 ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 137 ANSELB — ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 143 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 136 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 142 FVRCON FVREN FVRRDY TSEN TSRNG Legend: CDAFVR ADFVR 167 x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for the ADC module.  2013-2015 Microchip Technology Inc. DS40001675C-page 184 PIC16(L)F1788/9 18.0 OPERATIONAL AMPLIFIER (OPA) MODULES The Operational Amplifier (OPA) is a standard three-terminal device requiring external feedback to operate. The OPA module has the following features: • External connections to I/O ports • Low leakage inputs • Factory Calibrated Input Offset Voltage FIGURE 18-1: OPAx MODULE BLOCK DIAGRAM OPAXEN DAC4_output 111 DAC3_output 110 DAC2_output 101 DAC1_output 100 FVR_buffer2 011 Reserved 010 Reserved 001 OPAxIN+ OPAXSP(1) OPAxIN- OPA OPAXOUT 000 OPAxCH Note 1: The OPAxSP bit must be set to ‘1’. Low-Power mode is not supported.  2013-2015 Microchip Technology Inc. DS40001675C-page 185 PIC16(L)F1788/9 18.1 Effects of Reset A device Reset forces all registers to their Reset state. This disables the OPA module. 18.2 OPA Module Performance Common AC and DC performance specifications for the OPA module: • • • • • Common Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain Gain Bandwidth Product 18.3 OPAxCON Control Register The OPAxCON register, shown in Register 18-1, controls the OPA module. The OPA module is enabled by setting the OPAxEN bit of the OPAxCON register. When enabled, the OPA forces the output driver of OPAxOUT pin into tri-state to prevent contention between the driver and the OPA output. Note: When the OPA module is enabled, the OPAxOUT pin is driven by the op amp output, not by the PORT digital driver. Refer to the Electrical specifications for the op amp output drive capability. Common mode voltage range is the specified voltage range for the OPA+ and OPA- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between VSS and VDD. Behavior for Common mode voltages greater than VDD, or below VSS, are not guaranteed. Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. Input offset voltage is a measure of the voltage difference between the OPA+ and OPA- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the Common mode voltage. The OPA is factory calibrated to minimize the input offset voltage of the module. Open loop gain is the ratio of the output voltage to the differential input voltage, (OPA+) - (OPA-). The gain is greatest at DC and falls off with frequency. Gain Bandwidth Product or GBWP is the frequency at which the open loop gain falls off to 0 dB. DS40001675C-page 186  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 18.4 Register Definitions: Op Amp Control REGISTER 18-1: OPAxCON: OPERATIONAL AMPLIFIERS (OPAx) CONTROL REGISTERS R/W-0/0 R/W-0/0 U-0 U-0 U-0 OPAxEN OPAxSP — — — R/W-0/0 R/W-0/0 R/W-0/0 OPAxCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 OPAxEN: Op Amp Enable bit 1 = Op amp is enabled 0 = Op amp is disabled and consumes no active power bit 6 OPAxSP: Op Amp Speed/Power Select bit 1 = Comparator operates in high GBWP mode 0 = Reserved. Do not use. bit 5-3 Unimplemented: Read as ‘0’ bit 2-0 OPAxCH: Non-inverting Channel Selection bits 111 = Non-inverting input connects to DAC4_output 110 = Non-inverting input connects to DAC3_output 101 = Non-inverting input connects to DAC2_output 100 = Non-inverting input connects to DAC1_output 011 = Non-inverting input connects to FVR Buffer 2 output 010 = Reserved - do not use 001 = Reserved - do not use 000 = Non-inverting input connects to OPAxIN+ pin TABLE 18-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 137 ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 ANSELB — ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 143 DAC1EN — — DAC1NSS 192 OPA1CON OPA1EN OPA1SP — — — — OPA1PCH 187 OPA2CON OPA2EN OPA2SP — — — — OPA2PCH 187 OPA3CON(1) OPA3EN OPA3SP — — — — OPA3PCH 187 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 136 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 142 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 147 DAC1CON0 DAC1OE1 DAC1OE2 DAC1CON1 Legend: Note 1: DAC1PSS DAC1R 192 — = unimplemented location, read as ‘0’. Shaded cells are not used by op amps. PIC16(L)F1789 only  2013-2015 Microchip Technology Inc. DS40001675C-page 187 PIC16(L)F1788/9 NOTES: DS40001675C-page 188  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 19.0 8-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 256 selectable output levels. The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR (Fixed Voltage Reference) The Digital-to-Analog Converter (DAC) is enabled by setting the DAC1EN bit of the DAC1CON0 register. 19.1 Output Voltage Selection The DAC has 256 voltage level ranges. The 256 levels are set with the DAC1R bits of the DAC1CON1 register. The DAC output voltage is determined by Equation 19-1: The output of the DAC can be configured to supply a reference voltage to the following: • • • • • Comparator positive input Op amp positive input ADC input channel DAC1OUT1 pin DAC1OUT2 pin EQUATION 19-1: DAC OUTPUT VOLTAGE IF DACxEN = 1 DACxR  7:0  VOUT =   VSOURCE+ – VSOURCE-   -------------------------------- + VSOURCE8   2 VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 19.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section 31.0 “Electrical Specifications”. 19.3 DAC Voltage Reference Output The DAC voltage can be output to the DAC1OUT1 and DAC1OUT2 pins by setting the respective DAC1OE1 and DAC1OE2 pins of the DAC1CON0 register. Selecting the DAC reference voltage for output on either DAC1OUTX pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DAC1OUTX pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to either DAC1OUTx pin. Figure 19-2 shows an example buffering technique.  2013-2015 Microchip Technology Inc. DS40001675C-page 189 PIC16(L)F1788/9 FIGURE 19-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD 8 VREF+ DACxR R R DAC1PSS 2 R DAC1EN R 256 Steps R 32-to-1 MUX R DAC_Output R (To Comparator and ADC Modules) DAC1OUT1 R DAC1OE1 DAC1NSS DAC1OUT2 VREF- DAC1OE2 VSOURCE- VSS FIGURE 19-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS40001675C-page 190 DACXOUTX + – Buffered DAC Output  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 19.4 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DAC1CON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 19.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DAC1OUT pin. • The DAC1R range select bits are cleared.  2013-2015 Microchip Technology Inc. DS40001675C-page 191 PIC16(L)F1788/9 19.6 Register Definitions: DAC Control REGISTER 19-1: DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 DAC1EN — DAC1OE1 DAC1OE2 R/W-0/0 R/W-0/0 U-0 R/W-0/0 — DAC1NSS DAC1PSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DAC1EN: DAC1 Enable bit 1 = DAC1 is enabled 0 = DAC1 is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DAC1OE1: DAC1 Voltage Output 1 Enable bit 1 = DAC1 voltage level is also an output on the DAC1OUT1 pin 0 = DAC1 voltage level is disconnected from the DAC1OUT1 pin bit 4 DAC1OE2: DAC1 Voltage Output 2 Enable bit 1 = DAC1 voltage level is also an output on the DAC1OUT2 pin 0 = DAC1 voltage level is disconnected from the DAC1OUT2 pin bit 3-2 DAC1PSS: DAC1 Positive Source Select bits 11 = Reserved, do not use 10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD bit 1 Unimplemented: Read as ‘0’ bit 0 DAC1NSS: DAC1 Negative Source Select bits 1 = VREF- pin 0 = VSS REGISTER 19-2: R/W-0/0 DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DAC1R bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 DAC1R: DAC1 Voltage Output Select bits TABLE 19-1: Name FVRCON DAC1CON0 SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Bit 7 Bit 6 FVREN FVRRDY DAC1EN — DAC1CON1 Legend: Bit 5 Bit 4 TSEN TSRNG DAC1OE1 DAC1OE2 Bit 3 Bit 2 CDAFVR DAC1PSS Bit 1 Bit 0 ADFVR — DAC1R DAC1NSS Register on page 167 192 192 — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module. DS40001675C-page 192  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 20.0 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC2/3/4) MODULES Note: The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. Register names, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. The ‘x’ designator in DACx applies only to DAC2, DAC3, and DAC4. The input of the DAC can be connected to: 20.1 • External VREF+ pin • VDD supply voltage The output of the DAC can be configured to supply a reference voltage to the following: • • • • Comparator positive input ADC input channel DACxOUT1 pin DACxOUT2 pin Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACxR bits of the DACxCON1 register. The DAC output voltage is determined by the following equations: The Digital-to-Analog Converter (DACx) can be enabled by setting the DACxEN bit of the DACxCON0 register. EQUATION 20-1: DAC OUTPUT VOLTAGE IF DACxEN = 1 DACxR  4:0  VOUT =   VSOURCE+ – VSOURCE-   -------------------------------+ VSOURCE5   2 IF DACxEN = 0 and DACxLPS = 1 and DACxR[4:0] = 11111 V OUT = V SOURCE + IF DACxEN = 0 and DACxLPS = 0 and DACxR[4:0] = 00000 V OUT = V SOURCE – VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 20.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section 31.0 “Electrical Specifications”. 20.3 DAC Voltage Reference Output The DAC voltage can be output to the DACxOUT1 and DACxOUT2 pins by setting the respective DACxOE1 and DACxOE2 pins of the DACxCON0 register. Selecting the DAC reference voltage for output on either DACxOUTx pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACxOUTx pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to either DACxOUTx pin. Figure 20-2 shows an example buffering technique.  2013-2015 Microchip Technology Inc. DS40001675C-page 193 PIC16(L)F1788/9 FIGURE 20-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DACx) VDD VSOURCE+ VREF+ 5 DACxR R DACxPSS R DACxEN R 32-to-1 MUX R 32 Steps DACx_output To Peripherals R R DACxOUT1 DACxOE1 R DACxOUT2 VSS DS40001675C-page 194 VSOURCE- DACxOE2  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 20-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance 20.4 DACXOUTX + – Buffered DAC Output Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACxCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 20.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACxOUT pin. • The DACxR range select bits are cleared.  2013-2015 Microchip Technology Inc. DS40001675C-page 195 PIC16(L)F1788/9 20.6 Register Definitions: DACx Control REGISTER 20-1: DACxCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 DACxEN — DACxOE1 DACxOE2 R/W-0/0 R/W-0/0 U-0 U-0 — — DACxPSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACxEN: DACx Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DACxOE1: DACx Voltage Output Enable bit 1 = DACx voltage level is also an output on the DACxOUT1 pin 0 = DACx voltage level is disconnected from the DACxOUT1 pin bit 4 DACxOE2: DACx Voltage Output Enable bit 1 = DACx voltage level is also an output on the DACxOUT2 pin 0 = DACx voltage level is disconnected from the DACxOUT2 pin bit 3-2 DACxPSS: DACx Positive Source Select bits 11 = Reserved, do not use. 10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD bit 1-0 Unimplemented: Read as ‘0’ REGISTER 20-2: DACxCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DACxR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACxR: DAC Voltage Output Select bits TABLE 20-1: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC2/3/4 MODULES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FVREN FVRRDY TSEN TSRNG CDAFVR DAC2EN — DAC2OE1 DAC2OE2 DAC2PSS DAC2CON1 — — — DAC3CON0 DAC3EN — DAC3OE1 DAC3OE2 DAC3PSS DAC3CON1 — — — DAC4CON0 DAC4EN — DAC4OE1 DAC4OE2 DAC4PSS — — — DAC2CON0 DAC4CON1 Legend: Bit 1 Bit 0 ADFVR Register on page 167 — — 196 — — 196 — — 196 DAC2R 196 DAC3R 196 DAC4R 196 — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module. DS40001675C-page 196  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 21.0 COMPARATOR MODULE FIGURE 21-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • • • • • • • • • Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference 21.1 Comparator Overview SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 21-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparators available for this device are located in Table 21-1. TABLE 21-1: Device PIC16(L)F1788/9 COMPARATOR AVAILABILITY PER DEVICE C1 C2 C3 C4 ● ● ● ●  2013-2015 Microchip Technology Inc. DS40001675C-page 197 PIC16(L)F1788/9 FIGURE 21-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH CxON(1) 3 CxINTP Interrupt det CXIN0- 0 CXIN1- 1 CXIN2- 2 MUX Set CxIF CXIN3- 3 CXIN4- 4 Reserved 5 Reserved 6 CxINTN Interrupt (2) det CXPOL CxVN - 0 D Cx CxVP ZLF + 1 EN Q1 7 CxHYS AGND CxSP to CMXCON0 (CXOUT) and CM2CON1 (MCXOUT) Q CxZLF async_CxOUT CXSYNC CXOE TRIS bit CXOUT 0 CXIN0+ 0 CXIN1+ 1 DAC4_output 2 DAC3_output 3 DAC2_output 4 DAC1_Output 5 FVR Buffer2 6 D From Timer1 tmr1_clk Q 1 sync_CxOUT To Timer1 and PSMC Logic MUX (2) 7 AGND CxON CXPCH 3 Note 1: 2: When CxON = 0, the comparator will produce a ‘0’ at the output. When CxON = 0, all multiplexer inputs are disconnected. DS40001675C-page 198  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 21.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 register (see Register 21-1) contains Control and Status bits for the following: • • • • • • Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization The CMxCON1 register (see Register 21-2) contains Control bits for the following: • • • • Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 21.2.1 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 21.2.2 COMPARATOR OUTPUT SELECTION 21.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 21-2 shows the output state versus input conditions, including polarity control. TABLE 21-2: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 21.2.4 COMPARATOR SPEED/POWER SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.  2013-2015 Microchip Technology Inc. DS40001675C-page 199 PIC16(L)F1788/9 21.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. 21.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. See Section 30.0 “Electrical Specifications” for more information. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 21.4 To enable the interrupt, you must set the following bits: Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 23.6 “Timer1 Gate” for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 21.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from a comparator can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 21-2) and the Timer1 Block Diagram (Figure 23-1) for more information. • CxON, CxPOL and CxSP bits of the CMxCON0 register • CxIE bit of the PIE2 register • CxINTP bit of the CMxCON1 register (for a rising edge detection) • CxINTN bit of the CMxCON1 register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: 21.6 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. Comparator Positive Input Selection Configuring the CxPCH bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • • • • CxIN+ analog pin DAC output FVR (Fixed Voltage Reference) VSS (Ground) See Section 15.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 19.0 “8-Bit Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. DS40001675C-page 200  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 21.7 Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 31.0 “Electrical Specifications” for more details. Comparator Negative Input Selection The CxNCH bits of the CMxCON0 register direct an analog input pin or analog ground to the inverting input of the comparator: 21.9 • CxIN- pin • Analog Ground In high-speed operation, and under proper circuit conditions, it is possible for the comparator output to oscillate. This oscillation can have adverse effects on the hardware and software relying on this signal. Therefore, a digital filter has been added to the comparator output to suppress the comparator output oscillation. Once the comparator output changes, the output is prevented from reversing the change for a nominal time of 20 ns. This allows the comparator output to stabilize without affecting other dependent devices. Refer to Figure 21-3. Some inverting input selections share a pin with the operational amplifier output function. Enabling both functions at the same time will direct the operational amplifier output to the comparator inverting input. Note: 21.8 Zero Latency Filter To use CxINy+ and CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. FIGURE 21-3: COMPARATOR ZERO LATENCY FILTER OPERATION CxOUT From Comparator CxOUT From ZLF TZLF Output waiting for TZLF to expire before an output change is allowed TZLF has expired so output change of ZLF is immediate based on comparator output change  2013-2015 Microchip Technology Inc. DS40001675C-page 201 PIC16(L)F1788/9 21.10.1 21.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 21-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 13.1 “Alternate Pin Function” for more information. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 21-4: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT  0.6V RIC To Comparator VA CPIN 5 pF VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance = Source Impedance RS = Analog Voltage VA VT = Threshold Voltage Note 1: See Section 31.0 “Electrical Specifications” DS40001675C-page 202  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 21.11 Register Definitions: Comparator Control REGISTER 21-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL CxZLF CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 CxZLF: Comparator Zero Latency Filter Enable bit 1 = Comparator output is filtered 0 = Comparator output is unfiltered bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous.  2013-2015 Microchip Technology Inc. DS40001675C-page 203 PIC16(L)F1788/9 REGISTER 21-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CxPCH R/W-0/0 R/W-0/0 CxNCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-3 CxPCH: Comparator Positive Input Channel Select bits 111 = CxVP connects to AGND 110 = CxVP connects to FVR Buffer 2 101 = CxVP connects to DAC1_output 100 = CxVP connects to DAC2_output 011 = CxVP connects to DAC3_output 010 = CxVP connects to DAC4_output 001 = CxVP connects to CxIN1+ pin 000 = CxVP connects to CxIN0+ pin bit 2-0 CxNCH: Comparator Negative Input Channel Select bits 111 = CxVN connects to AGND 110 = CxVN unconnected, input floating 101 = Reserved, input floating 100 = CxVN connects to CxIN4- pin(1) 011 = CxVN connects to CxIN3- pin 010 = CxVN connects to CxIN2- pin 001 = CxVN connects to CxIN1- pin 000 = CxVN connects to CxIN0- pin Note 1: “Reserved, input floating” for PIC16(L)F1788 only. DS40001675C-page 204  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 21-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 R-0/0 R-0/0 R-0/0 R-0/0 — — — — MC4OUT MC3OUT MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 MC4OUT: Mirror Copy of C4OUT bit bit 2 MC3OUT: Mirror Copy of C3OUT bit bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit TABLE 21-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA ANSA7 — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 137 ANSELB — ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 143 CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 203 CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 203 CM1CON1 C1NTP C1INTN C1PCH C1NCH CM2CON1 C2NTP C2INTN C2PCH C2NCH CM3CON0 C3ON C3OUT CM3CON1 C3INTP C3INTN C3OE C3POL C3ZLF C3SP C3PCH CMOUT — — — — FVREN FVRRDY TSEN TSRNG CDAFVR DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS DAC1CON1 INTCON PIE2 PIR2 TRISA 204 C3SYNC C3NCH FVRCON DAC1CON0 C3HYS 204 MC4OUT MC3OUT MC2OUT 204 MC1OUT ADFVR — 203 DAC1NSS DAC1R 205 167 192 192 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 99 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 103 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 137 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 143 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 147 Note 1: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.  2013-2015 Microchip Technology Inc. DS40001675C-page 205 PIC16(L)F1788/9 22.0 22.1.2 TIMER0 MODULE 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’. 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register. Figure 22-1 is a block diagram of the Timer0 module. 22.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 22.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 22-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 2 TCY 1 TMR0 0 TMR0SE TMR0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow Overflow to Timer1 8 PS  2013-2015 Microchip Technology Inc. DS40001675C-page 206 PIC16(L)F1788/9 22.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 22.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 22.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 31.0 “Electrical Specifications”. 22.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS40001675C-page 207  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 22.2 Register Definitions: Option Register REGISTER 22-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS: Prescaler Rate Select bits TABLE 22-1: Name INTCON TRISA Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 OPTION_REG WPUEN TMR0 Bit Value INTEDG TMR0CS TMR0SE PSA PS 208 Timer0 Module Register TRISA7 TRISA6 TRISA5 206* TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 136 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information.  2013-2015 Microchip Technology Inc. DS40001675C-page 208 PIC16(L)F1788/9 23.0 • • • • TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: Figure 23-1 is a block diagram of the Timer1 module. • • • • • • • • 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Auto-conversion Trigger (with CCP) • Selectable Gate Source Polarity FIGURE 23-1: Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt TIMER1 BLOCK DIAGRAM T1GSS T1G T1GSPM 00 From Timer0 Overflow 01 sync_C1OUT 10 0 t1g_in T1GVAL 0 Single-Pulse D sync_C2OUT 11 CK Q R TMR1ON T1GPOL Q T1GTM 1 Acq. Control 1 Q1 Data Bus D Q RD T1GCON EN Interrupt T1GGO/DONE Set TMR1GIF det TMR1GE Set flag bit TMR1IF on Overflow To ADC Auto-Conversion TMR1ON To Comparator Module TMR1(2) TMR1H EN TMR1L Q D T1CLK Synchronized clock input 0 1 TMR1CS T1OSO Reserved T1OSC T1OSI T1SYNC OUT 11 1 Synchronize(3) Prescaler 1, 2, 4, 8 det 10 EN 0 T1OSCEN (1) FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 T1CKPS FOSC/2 Internal Clock Sleep input T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS40001675C-page 209  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 23.1 Timer1 Operation 23.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 23-1 displays the Timer1 enable selections. TABLE 23-1: Clock Source Selection The TMR1CS and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 23-2 displays the clock source selections. 23.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: TIMER1 ENABLE SELECTIONS Timer1 Operation • Asynchronous event on the T1G pin to Timer1 gate • C1 or C2 comparator input to Timer1 gate TMR1ON TMR1GE 0 0 Off 23.2.2 0 1 Off 1 0 Always On When the external clock source is selected, the Timer1 module may work as a timer or a counter. 1 1 Count Enabled EXTERNAL CLOCK SOURCE When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI, which can be synchronized to the microcontroller system clock or can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • • TABLE 23-2: Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. CLOCK SOURCE SELECTIONS TMR1CS T1OSCEN 11 x Reserved 10 1 Timer1 Oscillator 10 0 External Clocking on T1CKI Pin 01 x System Clock (FOSC) 00 x Instruction Clock (FOSC/4)  2013-2015 Microchip Technology Inc. Clock Source DS40001675C-page 210 PIC16(L)F1788/9 23.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 23.4 Timer1 Oscillator 23.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. 23.6 Note: 23.5 The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to using Timer1. A suitable delay similar to the OST delay can be implemented in software by clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to FC00h. The TMR1IF flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. Timer1 Operation in Asynchronous Counter Mode If the control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 23.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. DS40001675C-page 211 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 gate can also be driven by multiple selectable sources. 23.6.1 TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 23-3 for timing details. TABLE 23-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G Timer1 Operation  0 0 Counts  0 1 Holds Count  1 0 Holds Count  1 1 Counts  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 23.6.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 23-4. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 23-4: T1GSS TIMER1 GATE SOURCES Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 10 Comparator 1 Output sync_C1OUT (optionally Timer1 synchronized output) 11 Comparator 2 Output sync_C2OUT (optionally Timer1 synchronized output) 23.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 23.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 23.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 gate control. The Comparator 1 output (sync_C1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 21.4.1 “Comparator Output Synchronization”. 23.6.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1 gate control. The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 21.4.1 “Comparator Output Synchronization”. 23.6.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 23.6.4 Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is enabled by first setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure 23-5 for timing details. If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 23-6 for timing details. 23.6.5 TIMER1 GATE VALUE When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is accessible by reading the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 23.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 23-4 for timing details.  2013-2015 Microchip Technology Inc. DS40001675C-page 212 PIC16(L)F1788/9 23.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Note: 23.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured • T1OSCEN bit of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. 23.9 CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Auto-conversion Trigger. For more information, see “Capture/Compare/PWM Modules”. Section 25.0 23.10 CCP Auto-Conversion Trigger When any of the CCP’s are configured to trigger a auto-conversion, the trigger will clear the TMR1H:TMR1L register pair. This auto-conversion does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Auto-conversion Trigger. Asynchronous operation of Timer1 can cause a Auto-conversion Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Auto-conversion Trigger from the CCP, the write will take precedence. For more information, “Auto-Conversion Trigger”. see Section 25.2.4 Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 23-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001675C-page 213  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 23-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 23-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N  2013-2015 Microchip Technology Inc. N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS40001675C-page 214 PIC16(L)F1788/9 FIGURE 23-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS40001675C-page 215 N Cleared by software N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 23-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software  2013-2015 Microchip Technology Inc. N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Cleared by software DS40001675C-page 216 PIC16(L)F1788/9 23.11 Register Definitions: Timer1 Control T REGISTER 23-1: R/W-0/u T1CON: TIMER1 CONTROL REGISTER R/W-0/u TMR1CS R/W-0/u R/W-0/u T1CKPS R/W-0/u R/W-0/u U-0 R/W-0/u T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS: Timer1 Clock Source Select bits 11 = Reserved, do not use. 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop DS40001675C-page 217  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 23-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (sync_C2OUT) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 01 = Timer0 overflow output 00 = Timer1 gate pin  2013-2015 Microchip Technology Inc. DS40001675C-page 218 PIC16(L)F1788/9 TABLE 23-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 143 CCP1CON — — DC1B CCP1M CCP2CON — — DC2B CCP2M GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF Name INTCON PIE1 PIR1 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISC TRISC7 TRISC6 TRISC5 TRISC4 T1CON T1GCON Legend: * TMR1CS TMR1GE T1GPOL T1CKPS T1GTM T1GSPM TRISB3 231 231 102 209* 209* TRISB2 TRISB1 TRISB0 142 TRISC3 TRISC2 TRISC1 TRISC0 147 T1OSCEN T1SYNC — TMR1ON 217 T1GGO/ DONE T1GVAL T1GSS 218 — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. Page provides register information. DS40001675C-page 219  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 24.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 • Optional use as the shift clock for the MSSP module See Figure 24-1 for a block diagram of Timer2. FIGURE 24-1: FOSC/4 TIMER2 BLOCK DIAGRAM Prescaler 1:1, 1:4, 1:16, 1:64 2 TMR2 Comparator Reset EQ TMR2 Output Postscaler 1:1 to 1:16 Sets Flag bit TMR2IF T2CKPS PR2 4 T2OUTPS  2013-2015 Microchip Technology Inc. DS40001675C-page 220 PIC16(L)F1788/9 24.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (FOSC/4). A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output Section 24.2 “Timer2 counter/postscaler (see Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • • • • • • • • • 24.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 27.0 “Master Synchronous Serial Port (MSSP) Module” 24.4 Timer2 Operation During Sleep The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode. a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: 24.2 TMR2 is not cleared when T2CON is written. Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE, of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS, of the T2CON register. DS40001675C-page 221  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 24.5 Register Definitions: Timer2 Control REGISTER 24-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 T2OUTPS R/W-0/0 R/W-0/0 TMR2ON bit 7 R/W-0/0 T2CKPS bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS: Timer2 Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS: Timer2 Clock Prescale Select bits 11 = Prescaler is 64 10 = Prescaler is 16 01 = Prescaler is 4 00 = Prescaler is 1  2013-2015 Microchip Technology Inc. DS40001675C-page 222 PIC16(L)F1788/9 TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 CCP2CON — — GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PR2 Timer2 Module Period Register INTCON PIE1 T2CON TMR2 — Bit 5 Bit 4 Bit 3 DC2B T2OUTPS Bit 2 Bit 1 Bit 0 Register on Page Name CCP2M 231 102 220* TMR2ON T2CKPS Holding Register for the 8-bit TMR2 Register 222 220* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. DS40001675C-page 223  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 25.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/Compare/PWM modules (CCP1, CCP2 and CCP3). The Capture and Compare functions are identical for all CCP modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. 25.1 Capture Mode The Capture mode function described in this section is available and identical for all CCP modules. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCPxM bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 25-1 shows a simplified diagram of the capture operation. 25.1.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Also, the CCP2 pin function can be moved to alternative pins using the APFCON register. Refer to Section 13.1 “Alternate Pin Function” for more details. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. FIGURE 25-1: Prescaler  1, 4, 16 CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCPxIF (PIRx register) CCPx pin CCPRxH and Edge Detect CCPRxL Capture Enable TMR1H TMR1L CCPxM System Clock (FOSC)  2013-2015 Microchip Technology Inc. DS40001675C-page 224 PIC16(L)F1788/9 25.1.2 TIMER1 MODE RESOURCE 25.1.5 CAPTURE DURING SLEEP Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. See Section 23.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. 25.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: 25.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP PRESCALER There are four prescaler settings specified by the CCPxM bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Equation 25-1 demonstrates the code to perform this function. EXAMPLE 25-1: BANKSEL CCPxCON CLRF MOVLW MOVWF CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value DS40001675C-page 225 Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 25.1.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 13.1 “Alternate Pin Function” for more information. 25.2 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate an Auto-conversion Trigger Generate a Software Interrupt The action on the pin is based on the value of the CCPxM control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. Figure 25-2 shows a simplified diagram of the compare operation.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 25-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCPxM Mode Select CCPx Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL CCPx Pin Q S R Output Logic Match TRIS Output Enable Comparator TMR1H TMR1L Auto-conversion Trigger 25.2.1 CCPX PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the associated TRIS bit. The CCP2 pin function can be moved to alternate pins using the APFCON register (Register 13-1). Refer to Section 13.1 “Alternate Pin Function” for more details. Note: 25.2.2 25.2.3 • Resets Timer1 • Starts an ADC conversion if ADC is enabled The CCPx module does not assert control of the CCPx pin in this mode. The Auto-conversion Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Auto-conversion Trigger output starts an ADC conversion (if the ADC module is enabled). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. Refer to Section 17.2.5 “Auto-Conversion Trigger” for more information. Note 1: The Auto-conversion Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. TIMER1 MODE RESOURCE See Section 23.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. AUTO-CONVERSION TRIGGER When Auto-conversion Trigger mode is chosen (CCPxM = 1011), the CCPx module does the following: Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. Note: 25.2.4 25.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. 25.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 13.1 “Alternate Pin Function”for more information. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCPxM = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register).  2013-2015 Microchip Technology Inc. DS40001675C-page 226 PIC16(L)F1788/9 25.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. FIGURE 25-3: Period Pulse Width 25.3.1 TMR2 = 0 FIGURE 25-4: The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON Duty Cycle Registers CCPR1L CCPx CCPR1H(2) (Slave) CCPx R Comparator (1) TMR2 Q S TRIS Comparator STANDARD PWM OPERATION The standard PWM function described in this section is available and identical for all CCP modules. TMR2 = PR2 TMR2 = CCPRxH:CCPxCON The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 25-3 shows a typical waveform of the PWM signal. CCP PWM OUTPUT SIGNAL PR2 Note 1: 2: Clear Timer, toggle CCP1 pin and latch duty cycle The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register. PR2 registers T2CON registers CCPRxL registers CCPxCON registers Figure 25-4 shows a simplified block diagram of PWM operation. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. DS40001675C-page 227  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 25.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIRx register. See Note below. • Configure the T2CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR1 register is set. See Note below. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: 25.3.3 In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. TIMER2 TIMER RESOURCE The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period. 25.3.4 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 25-1. EQUATION 25-1: PWM PERIOD PWM Period =   PR2  + 1   4  T OSC  (TMR2 Prescale Value) Note 1: TOSC = 1/FOSC  2013-2015 Microchip Technology Inc. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: 25.3.5 The Timer postscaler (see Section 24.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 25-2 is used to calculate the PWM pulse width. Equation 25-3 is used to calculate the PWM duty cycle ratio. EQUATION 25-2: PULSE WIDTH Pulse Width =  CCPRxL:CCPxCON   T OSC  (TMR2 Prescale Value) EQUATION 25-3: DUTY CYCLE RATIO  CCPRxL:CCPxCON  Duty Cycle Ratio = ----------------------------------------------------------------------4  PR2 + 1  The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 25-4). DS40001675C-page 228 PIC16(L)F1788/9 25.3.6 PWM RESOLUTION EQUATION 25-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 25-4. TABLE 25-1: 1.22 kHz Timer Prescale PR2 Value Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Maximum Resolution (bits) EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale PR2 Value Maximum Resolution (bits) 25.3.7 log  4  PR2 + 1   Resolution = ------------------------------------------ bits log  2  EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency TABLE 25-2: PWM RESOLUTION OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 25.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 25.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. DS40001675C-page 229  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 25-3: Name APFCON1 SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 Bit 6 C2OUTSEL CC1PSEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 — — — CCP3SEL 231 APFCON2 — — CCP1CON — — DC1B CCP1M 231 CCP2CON — — DC2B CCP2M 231 CCP33CON — — DC3B CCP3M GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 97 PIE2 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 99 PIE3 — — — CCP3IE — — — — 100 102 INTCON SSSEL 231 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF PIR2 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 103 PIR3 — — — CCP3IF — — — — 104 PR2 T2CON TMR2 TRISA Timer2 Period Register — 220* T2OUTPS TMR2ON T2CKPS Timer2 Module Register TRISA7 TRISA6 222 220 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 136 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information.  2013-2015 Microchip Technology Inc. DS40001675C-page 230 PIC16(L)F1788/9 25.4 Register Definitions: CCP Control REGISTER 25-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 DCxB R/W-0/0 R/W-0/0 R/W-0/0 CCPxM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM: CCPx Mode Select bits 11xx = PWM mode 1011 = Compare mode: Auto-conversion Trigger (sets CCPxIF bit (CCP2), starts ADC conversion if ADC module is enabled)(1) 1010 = Compare mode: generate software interrupt only 1001 = Compare mode: clear output on compare match (set CCPxIF) 1000 = Compare mode: set output on compare match (set CCPxIF) 0111 = 0110 = 0101 = 0100 = Capture mode: every 16th rising edge Capture mode: every 4th rising edge Capture mode: every rising edge Capture mode: every falling edge 0011 = 0010 = 0001 = 0000 = Reserved Compare mode: toggle output on match Reserved Capture/Compare/PWM off (resets CCPx module) DS40001675C-page 231  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.0 PROGRAMMABLE SWITCH MODE CONTROL (PSMC) The Programmable Switch Mode Controller (PSMC) is a high-performance Pulse Width Modulator (PWM) that can be configured to operate in one of several modes to support single or multiple phase applications. A simplified block diagram indicating the relationship between inputs, outputs, and controls is shown in Figure 26-1. This section begins with the fundamental aspects of the PSMC operation. A more detailed description of operation for each mode is located later in Section 26.3 “Modes of Operation”  2013-2015 Microchip Technology Inc. Modes of operation include: • • • • • • • • Single-phase Complementary Single-phase Push-Pull Push-Pull 4-Bridge Complementary Push-Pull 4-Bridge Pulse Skipping Variable Frequency Fixed Duty Cycle Complementary Variable Frequency Fixed Duty Cycle • ECCP Compatible modes - Full-Bridge - Full-Bridge Reverse • 3-Phase 6-Step PWM DS40001675C-page 232 PSMC SIMPLIFIED BLOCK DIAGRAM PIC16(L)F1788/9 PXCPRE 1,2, 4, 8 CLR 0 sync_out 1 PXPRPOL PSMCXPRS XOR Falling Event PSMCXPHS PSMCXDC = PXDCPOL PSMCXDCS  2013-2015 Microchip Technology Inc. PSMCXREBS PSMCXFEBS sync_C1OUT sync_C2OUT sync_C3OUT sync_C4OUT PSMCXIN CCP1 CCP2 PSMCXMDL 0 PSMCXA S Q R PSMCXASDS PSMCXB PSMCXC PSMCXD PSMCXE PSMCXF PXMODE Shutdown Blanking 1 Latch PSMCXPH = PSMCXPOL PSMCXOEN PXPOFST Output Control PSMCXPR = FFA PSMCXTMR Mode Control psmc_clk Modulation PSMCXCLK 64 MHZ FOSC sync_in XOR Period Event PXCSRC Rising Event DS40001675CDS40001579EDS40001637C-page 233 FIGURE 26-1: PSMCXSTR PIC16(L)F1788/9 26.1 Fundamental Operation PSMC operation is based on the sequence of three events: The basic waveform generated from these events is shown in Figure 26-2. • Period Event – Determines the frequency of the active signal. • Rising Edge Event – Determines start of the active pulse. This is also referred to as the phase. • Falling Edge Event – Determines the end of the active pulse. This is also referred to as the duty cycle. FIGURE 26-2: BASIC PWM WAVEFORM GENERATION PWM Cycle Number 1 2 3 Inputs Period Event Rising Edge Event Falling Edge Event Outputs PWM output Each of the three types of events is triggered by a user selectable combination of synchronous timed and asynchronous external inputs. Asynchronous event inputs may come directly from an input pin or through the comparators. Synchronous timed events are determined from the PSMCxTMR counter, which is derived from internal clock sources. See Section 26.2.5 “PSMC Time Base Clock Sources” for more detail. PSMC operation can be quickly terminated without software intervention by the auto-shutdown control. Auto-shutdown can be triggered by any combination of the following: • • • • • PSMCxIN pin sync_C1OUT sync_C2OUT sync_C3OUT sync_C4OUT The active pulse stream can be further modulated by one of several internal or external sources: • • • • Register control bit Comparator output CCP output Input pin User selectable deadtime can be inserted in the drive outputs to prevent shoot through of configurations with two devices connected in series between the supply rails. Applications requiring very small frequency granularity control when the PWM frequency is large can do so with the fractional frequency control available in the variable frequency fixed Duty Cycle modes.  2013-2015 Microchip Technology Inc. DS40001675C-page 234 PIC16(L)F1788/9 26.1.1 PERIOD EVENT The period event determines the frequency of the active pulse. Period event sources include any combination of the following: • • • • • • PSMCxTMR counter match PSMC input pin sync_C1OUT sync_C2OUT sync_C3OUT sync_C4OUT Period event sources are selected with the PSMC Period Source (PSMCxPRS) register (Register 26-15). Section 26.2.1.2 “16-bit Period Register” contains details on configuring the PSMCxTMR counter match for synchronous period events. All period events cause the PSMCxTMR counter to reset on the counting clock edge immediately following the period event. The PSMCxTMR counter resumes counting from zero on the counting clock edge after the period event Reset. During a period, the rising event and falling event are each permitted to occur only once. Subsequent rising or falling events that may occur within the period are suppressed, thereby preventing output chatter from spurious inputs. 26.1.2 RISING EDGE EVENT The rising edge event determines the start of the active drive period. The rising edge event is also referred to as the phase because two synchronized PSMC peripherals may have different rising edge events relative to the period start, thereby creating a phase relationship between the two PSMC peripheral outputs. Depending on the PSMC mode, one or more of the PSMC outputs will change in immediate response to the rising edge event. Rising edge event sources include any combination of the following: • Synchronous: - PSMCxTMR time base counter match • Asynchronous: - PSMC input pin - sync_C1OUT - sync_C2OUT - sync_C3OUT - sync_C4OUT Rising edge event sources are selected with the PSMC Phase Source (PSMCxPHS) register (Register 26-13). For configuring the PSMCxTMR time base counter match for synchronous rising edge events, see Section 26.2.1.3 “16-bit Phase Register”. The first rising edge event in a cycle period is the only one permitted to cause action. All subsequent rising edge events in the same period are suppressed to DS40001675C-page 235 prevent the PSMC output from chattering in the presence of spurious event inputs. A rising edge event is also suppressed when it occurs after a falling edge event in the same period. The rising edge event also triggers the start of two other timers when needed: falling edge blanking and dead-band period. For more detail refer to Section 26.2.8 “Input Blanking” and Section 26.4 “Dead-Band Control”. When the rising edge event is delayed from the period start, the amount of delay subtracts from the total amount of time available for the drive duty cycle. For example, if the rising edge event is delayed by 10% of the period time, the maximum duty cycle for that period is 90%. A 100% duty cycle is still possible in this example, but duty cycles from 90% to 100% are not possible. 26.1.3 FALLING EDGE EVENT The falling edge event determines the end of the active drive period. The falling edge event is also referred to as the duty cycle because varying the falling edge event, while keeping the rising edge event and period events fixed, varies the active drive duty cycle. Depending on the PSMC mode, one or more of the PSMC outputs will change in immediate response to the falling edge event. Falling edge event sources include any combination of the following: • Synchronous: - PSMCxTMR time base counter match • Asynchronous: - PSMC input pin - sync_C1OUT - sync_C2OUT - sync_C3OUT - sync_C4OUT Falling edge event sources are selected with PSMC Duty Cycle Source (PSMCxDCS) register (Register 26-14). For configuring the PSMCxTMR time base counter match for synchronous falling edge events, see Section 26.2.1.4 “16-bit Duty Cycle Register”. The first falling edge event in a cycle period is the only one permitted to cause action. All subsequent falling edge events in the same period are suppressed to prevent the PSMC output from chattering in the presence of spurious event inputs. A falling edge event suppresses any subsequent rising edges that may occur in the same period. In other words, if an asynchronous falling event input should come late and occur early in the period, following that for which it was intended, the rising edge in that period will be suppressed. This will have a similar effect as pulse skipping. The falling edge event also triggers the start of two other timers: rising edge blanking and dead-band period. For more detail refer to Section 26.2.8 “Input Blanking” and Section 26.4 “Dead-Band Control”.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.2 Event Sources There are two main sources for the period, rising edge and falling edge events: • Synchronous input - Time base • Asynchronous Inputs - Digital Inputs - Analog inputs 26.2.1 TIME BASE The Time Base section consists of several smaller pieces. • • • • • • 16-bit time base counter 16-bit Period register 16-bit Phase register (rising edge event) 16-bit Duty Cycle register (falling edge event) Clock control Interrupt Generator An example of a fully synchronous PWM waveform generated with the time base is shown in Figure 26-2. The PSMCxLD bit of the PSMCxCON register is provided to synchronize changes to the event Count registers. Changes are withheld from taking action until the first period event Reset after the PSMCxLD bit is set. For example, to change the PWM frequency, while maintaining the same effective duty cycle, the Period and Duty Cycle registers need to be changed. The changes to all four registers take effect simultaneously on the period event Reset after the PSMCxLD bit is set. 26.2.1.1 16-bit Counter (Time Base) The PSMCxTMR is the counter used as a timing reference for each synchronous PWM period. The counter starts at 0000h and increments to FFFFh on the rising edge of the psmc_clk signal. When the counter rolls over from FFFFh to 0000h without a period event occurring, the overflow interrupt will be generated, thereby setting the PxTOVIF bit of the PSMC Time Base Interrupt Control (PSMCxINT) register (Register 26-34). The PSMCxTMR counter is reset on both synchronous and asynchronous period events. The PSMCxTMR is accessible to software as two 8-bit registers: • PSMC Time Base Counter Low (PSMCxTMRL) register (Register 26-19) • PSMC PSMC Time Base Counter High (PSMCxTMRH) register (Register 26-20) PSMCxTMR is reset to the default POR value when the PSMCxEN bit is cleared.  2013-2015 Microchip Technology Inc. 26.2.1.2 16-bit Period Register The PSMCxPR Period register is used to determine a synchronous period event referenced to the 16-bit PSMCxTMR digital counter. A match between the PSMCxTMR and PSMCxPR register values will generate a period event. The match will generate a period match interrupt, thereby setting the PxTPRIF bit of the PSMC Time Base Interrupt Control (PSMCxINT) register (Register 26-34). The 16-bit period value is accessible to software as two 8-bit registers: • PSMC Period Count Low Byte (PSMCxPRL) register (Register 26-25) • PSMC Period Count High Byte (PSMCxPRH) register (Register 26-26) The 16-bit period value is double-buffered before it is presented to the 16-bit time base for comparison. The buffered registers are updated on the first period event Reset after the PSMCxLD bit of the PSMCxCON register is set. The synchronous PWM period time can be determined from Equation 26-1. EQUATION 26-1: PWM PERIOD PSMCxPR[15:0] + 1 Period = -------------------------------------------------F psmc_clk 26.2.1.3 16-bit Phase Register The PSMCxPH Phase register is used to determine a synchronous rising edge event referenced to the 16-bit PSMCxTMR digital counter. A match between the PSMCxTMR and the PSMCxPH register values will generate a rising edge event. The match will generate a phase match interrupt, thereby setting the PxTPHIF bit of the PSMC Time Base Interrupt Control (PSMCxINT) register (Register 26-34). The 16-bit phase value is accessible to software as two 8-bit registers: • PSMC Phase Count Low Byte (PSMCxPHL) register (Register 26-34) • PSMC Phase Count High Byte (PSMCxPHH) register (Register 26-34) The 16-bit phase value is double-buffered before it is presented to the 16-bit PSMCxTMR for comparison. The buffered registers are updated on the first period event Reset after the PSMCxLD bit of the PSMCxCON register is set. DS40001675C-page 236 PIC16(L)F1788/9 26.2.1.4 16-bit Duty Cycle Register The PSMCxDC Duty Cycle register is used to determine a synchronous falling edge event referenced to the 16-bit PSMCxTMR digital counter. A match between the PSMCxTMR and PSMCxDC register values will generate a falling edge event. The match will generate a duty cycle match interrupt, thereby setting the PxTDCIF bit of the PSMC Time Base Interrupt Control (PSMCxINT) register (Register 26-34). The 16-bit duty cycle value is accessible to software as two 8-bit registers: • PSMC Duty Cycle Count Low Byte (PSMCxDCL) register (Register 26-23) • PSMC Duty Cycle Count High Byte (PSMCxDCH) register (Register 26-24) The 16-bit duty cycle value is double-buffered before it is presented to the 16-bit time base for comparison. The buffered registers are updated on the first period event Reset after the PSMCxLD bit of the PSMCxCON register is set. When the period, phase, and duty cycle are all determined from the time base, the effective PWM duty cycle can be expressed as shown in Equation 26-2. EQUATION 26-2: PWM DUTY CYCLE PSMCxDC[15:0] – PSMCxPH[15:0] DUTYCYCLE = ---------------------------------------------------------------------------------------- PSMCxPR[15:0] + 1  26.2.2 0% DUTY CYCLE OPERATION USING TIME BASE To configure the PWM for 0% duty cycle set PSMCxDC = PSMCxPH. This will trigger a falling edge event simultaneous with the rising edge event and prevent the PWM from being asserted. 26.2.3 100% DUTY CYCLE OPERATION USING TIME BASE To configure the PWM for 100% duty cycle set PSMCxDC > PSMCxPR. This will prevent a falling edge event from occurring as the PSMCxDC value and the time base value PSMCxTMR will never be equal. 26.2.4 TIME BASE INTERRUPT GENERATION The Time Base section can generate four unique interrupts: • • • • Time Base Counter Overflow Interrupt Time Base Phase Register Match Interrupt Time Base Duty Cycle Register Match Interrupt Time Base Period Register Match Interrupt DS40001675C-page 237 Each interrupt has an interrupt flag bit and an interrupt enable bit. The interrupt flag bit is set anytime a given event occurs, regardless of the status of the enable bit. Time base interrupt enables and flags are located in the PSMC Time Base Interrupt Control (PSMCxINT) register (Register 26-34). PSMC time base interrupts also require that the PSMCxTIE bit in the PIE4 register and the PEIE and GIE bits in the INTCON register be set in order to generate an interrupt. The PSMCxTIF interrupt flag in the PIR4 register will only be set by a time base interrupt when one or more of the enable bits in the PSMCxINT register is set. The interrupt flag bits need to be cleared in software. However, all PMSCx time base interrupt flags, except PSMCxTIF, are cleared when the PSMCxEN bit is cleared. Interrupt bits that are set by software will generate an interrupt provided that the corresponding interrupt is enabled. Note: 26.2.5 Interrupt flags in both the PIE4 and PSMCxINT registers must be cleared to clear the interrupt. The PSMCxINT flags must be cleared first. PSMC TIME BASE CLOCK SOURCES There are three clock sources available to the module: • Internal 64 MHz clock • Fosc system clock • External clock input pin The clock source is selected with the PxCSRC bits of the PSMCx Clock Control (PSMCxCLK) register (Register 26-7). When the Internal 64 MHz clock is selected as the source, the HFINTOSC continues to operate and clock the PSMC circuitry in Sleep. However, the system clock to other peripherals and the CPU is suppressed. Note: When the 64 MHz clock is selected, the clock continues to operate in Sleep, even when the PSMC is disabled (PSMCxEN = 0). Select a clock other than the 64 MHz clock to minimize power consumption when the PSMC is not enabled. The Internal 64 MHz clock utilizes the system clock 4x PLL. When the system clock source is external and the PSMC is using the Internal 64 MHz clock, the 4x PLL should not be used for the system clock.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.2.6 CLOCK PRESCALER The clock source is selected with the PxCPRE bits of the PSMCx Clock Control (PSMCxCLK) register (Register 26-7). There are four prescaler choices available to be applied to the selected clock: • • • • The prescaler output is psmc_clk, which is the clock used by all of the other portions of the PSMC module. Divide by 1 Divide by 2 Divide by 4 Divide by 8 FIGURE 26-3: TIME BASE WAVEFORM GENERATION 1 Period psmc_clk Counter 0030h 0000h 0001h 0002h 0003h 0027h PSMCxPH 0002h PSMCxDC 0028h PSMCxPR 0030h 0028h 0029h 0030h 0000h Inputs Period Event Rising Edge Event Falling Edge Event Output PWM Output  2013-2015 Microchip Technology Inc. DS40001675C-page 238 PIC16(L)F1788/9 26.2.7 ASYNCHRONOUS INPUTS The PSMC module supports asynchronous inputs alone or in combination with the synchronous inputs. asynchronous inputs include: • Analog - sync_C1OUT - sync_C2OUT - sync_C3OUT - sync_C4OUT • Digital - PSMCxIN pin 26.2.7.1 Comparator Inputs Rising edge and falling edge blanking are controlled independently. The following features are available for blanking: • Blanking enable • Blanking time counters • Blanking mode The following Blanking modes are available: • Blanking disabled • Immediate blanking The Falling Edge Blanking mode is set with the PxFEBM bits of the PSMCx Blanking Control (PSMCxBLNK) register (Register 26-10). The outputs of any combination of the synchronized comparators may be used to trigger any of the three events as well as auto-shutdown. The Rising Edge Blanking mode is set with the PxREBM bits of the PSMCx Blanking Control (PSMCxBLNK) register (Register 26-10). The event triggers on the rising edge of the comparator output. Except for auto-shutdown, the event input is not level sensitive. 26.2.8.1 26.2.7.2 PSMCxIN Pin Input The PSMCxIN pin may be used to trigger PSMC events. Data is passed through straight to the PSMC module without any synchronization to a system clock. This is so that input blanking may be applied to any external circuit using the module. The event triggers on the rising edge of the PSMCxIN signal. 26.2.7.3 Asynchronous Polarity Polarity control is available for the period and duty-cycle asynchronous event inputs. Polarity control is necessary when the same signal is used as the source for both events. Inverting the polarity of one event relative to the other enables starting the period on one edge of the signal and terminating the duty-cycle on the opposite edge. Polarity is controlled with the PxPRPOL and PxDCPOL bits of the PSMCxSYNC register. Inverting the asynchronous input with these controls inverts all enabled asynchronous inputs for the corresponding event. 26.2.8 INPUT BLANKING Input blanking is a function whereby the inputs from any selected asynchronous input may be driven inactive for a short period of time. This is to prevent electrical transients from the turn-on/off of power components from generating a false event. Blanking is initiated by either or both: • Rising event • Falling event Blanked inputs are suppressed from causing all asynchronous events, including: • • • • Rising Falling Period Shutdown DS40001675C-page 239 Blanking Disabled With blanking disabled, the asynchronous inputs are passed to the PSMC module without any intervention. 26.2.8.2 Immediate Blanking With Immediate blanking, a counter is used to determine the blanking period. The desired blanking time is measured in psmc_clk periods. A rising edge event will start incrementing the rising edge blanking counter. A falling edge event will start incrementing the falling edge blanking counter. The rising edge blanking time is set with the PSMC Rising Edge Blanking Time (PSMCxBLKR) register (Register 26-30). The inputs to be blanked are selected with the PSMC Rising Edge Blanked Source (PSMCxREBS) register (Register 26-11). During rising edge blanking, the selected blanked sources are suppressed for falling edge as well as rising edge, auto-shutdown and period events. The falling edge blanking time is set with the PSMC Falling Edge Blanking Time (PSMCxBLKF) register (Register 26-31). The inputs to be blanked are selected with the PSMC Falling Edge Blanked Source (PSMCxFEBS) register (Register 26-12). During falling edge blanking, the selected blanked sources are suppressed for rising edge, as well as falling edge, auto-shutdown, and period events. The blanking counters are incremented on the rising edge of psmc_clk. Blanked sources are suppressed until the counter value equals the blanking time register causing the blanking to terminate. As the rising and falling edge events are from asynchronous inputs, there may be some uncertainty in the actual blanking time implemented in each cycle. The maximum uncertainty is equal to one psmc_clk period.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.2.9 OUTPUT WAVEFORM GENERATION The PSMC PWM output waveform is generated based upon the different input events. However, there are several other factors that affect the PWM waveshapes: • Output Control - Output Enable - Output Polarity • Waveform Mode Selection • Dead-band Control • Steering control 26.2.10 26.2.10.1 OUTPUT CONTROL Output Pin Enable Each PSMC PWM output pin has individual output enable control. When the PSMC output enable control is disabled, the module asserts no control over the pin. In this state, the pin can be used for general purpose I/O or other associate peripheral use. When the PSMC output enable is enabled, the active PWM waveform is applied to the pin per the port priority selection. PSMC output enable selections are made with the PSMC Output Enable Control (PSMCxOEN) register (Register 26-8). 26.2.10.2 Output Steering PWM output will be presented only on pins for which output steering is enabled. The PSMC has up to six PWM outputs. The PWM signal in some modes can be steered to one or more of these outputs. Steering differs from output enable in the following manner: When the output is enabled but the PWM steering to the corresponding output is not enabled, then general purpose output to the pin is disabled and the pin level will remain constantly in the inactive PWM state. Output steering is controlled with the PSMCS Steering Control 0 (PSMCxSTR0) register (Register 26-32). Steering operates only in the following modes: 26.3 Modes of Operation All modes of operation use the period, rising edge, and falling edge events to generate the various PWM output waveforms. The 3-phase 6-step PWM mode makes special use of the software controlled steering to generate the required waveform. Modes of operation are selected with the PSMC Control (PSMCxCON) register (Register 26-1). 26.3.1 SINGLE-PHASE MODE The single PWM is the most basic of all the waveshapes generated by the PSMC module. It consists of a single output that uses all three events (rising edge, falling edge and period events) to generate the waveform. 26.3.1.1 Mode Features • No dead-band control available • PWM can be steered to any combination of the following PSMC outputs: - PSMCxA - PSMCxB - PSMCxC - PSMCxD - PSMCxE - PSMCxF • Identical PWM waveform is presented to all pins for which steering is enabled. 26.3.1.2 Waveform Generation Rising Edge Event • All outputs with PxSTR enabled are set to the active state Falling Edge Event • All outputs with PxSTR enabled are set to the inactive state Code for setting up the PSMC generate the single-phase waveform shown in Figure 26-4, and given in Example 26-1. • Single-phase • Complementary Single-phase • 3-phase 6-step PWM 26.2.10.3 Polarity Control Each PSMC output has individual output polarity control. Polarity is set with the PSMC Polarity Control (PSMCxPOL) register (Register 26-9).  2013-2015 Microchip Technology Inc. DS40001675C-page 240 PIC16(L)F1788/9 EXAMPLE 26-1: ; ; ; ; ; ; ; ; SINGLE-PHASE SETUP Single-phase PWM PSMC setup Fully synchronous operation Period = 10 us Duty cycle = 50% BANKSEL PSMC1CON MOVLW 0x02 ; set period MOVWF PSMC1PRH MOVLW 0x7F MOVWF PSMC1PRL MOVLW 0x01 ; set duty cycle MOVWF PSMC1DCH MOVLW 0x3F MOVWF PSMC1DCL CLRF PSMC1PHH ; no phase offset CLRF PSMC1PHL MOVLW 0x01 ; PSMC clock=64 MHz MOVWF PSMC1CLK output on A, normal polarity BSF PSMC1STR0,P1STRA BCF PSMC1POL, P1POLA BSF PSMC1OEN, P1OEA set time base as source for all events BSF PSMC1PRS, P1PRST BSF PSMC1PHS, P1PHST BSF PSMC1DCS, P1DCST enable PSMC in Single-Phase Mode this also loads steering and time buffers MOVLW B’11000000’ MOVWF PSMC1CON BANKSEL TRISC BCF TRISC, 0 ; enable pin driver FIGURE 26-4: SINGLE PWM WAVEFORM – PSMCXSTR0 = 01H PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event PSMCxA DS40001675C-page 241  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.3.2 COMPLEMENTARY PWM EXAMPLE 26-2: The complementary PWM uses the same events as the single PWM, but two waveforms are generated instead of only one. The two waveforms are opposite in polarity to each other. The two waveforms may also have dead-band control as well. 26.3.2.1 Mode Features and Controls • Dead-band control available • PWM primary output can be steered to the following pins: - PSMCxA - PSMCxC - PSMCxE • PWM complementary output can be steered to the following pins: - PSMCxB - PSMCxD - PSMCxE 26.3.2.2 ; ; ; ; ; Waveform Generation ; ; Rising Edge Event • Complementary output is set inactive • Optional rising edge dead band is activated • Primary output is set active Falling Edge Event • Primary output is set inactive • Optional falling edge dead band is activated • Complementary output is set active Code for setting up the PSMC generate the complementary single-phase waveform shown in Figure 26-5, and given in Example 26-2. FIGURE 26-5: ; ; ; ; COMPLEMENTARY SINGLE-PHASE SETUP Complementary Single-phase PWM PSMC setup Fully synchronous operation Period = 10 us Duty cycle = 50% Deadband = 93.75 +15.6/-0 ns BANKSEL PSMC1CON MOVLW 0x02 ; set period MOVWF PSMC1PRH MOVLW 0x7F MOVWF PSMC1PRL MOVLW 0x01 ; set duty cycle MOVWF PSMC1DCH MOVLW 0x3F MOVWF PSMC1DCL CLRF PSMC1PHH ; no phase offset CLRF PSMC1PHL MOVLW 0x01 ; PSMC clock=64 MHz MOVWF PSMC1CLK output on A, normal polarity MOVLW B’00000011’ ; A and B enables MOVWF PSMC1OEN MOVWF PSMC1STR0 CLRF PSMC1POL set time base as source for all events BSF PSMC1PRS, P1PRST BSF PSMC1PHS, P1PHST BSF PSMC1DCS, P1DCST set rising and falling dead-band times MOVLW D’6’ MOVWF PSMC1DBR MOVWF PSMC1DBF enable PSMC in Complementary Single Mode this also loads steering and time buffers and enables rising and falling deadbands MOVLW B’11110001’ MOVWF PSMC1CON BANKSEL TRISC BCF TRISC, 0 ; enable pin drivers BCF TRISC, 1 COMPLEMENTARY PWM WAVEFORM – PSMCXSTR0 = 03H PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event PSMCxA (Primary Output) Rising Edge Dead Band Rising Edge Dead Band Falling Edge Dead Band Falling Edge Dead Band PSMCxB (Complementary Output)  2013-2015 Microchip Technology Inc. DS40001675C-page 242 PIC16(L)F1788/9 26.3.3 PUSH-PULL PWM The push-pull PWM is used to drive transistor bridge circuits. It uses at least two outputs and generates PWM signals that alternate between the two outputs in even and odd cycles. Variations of the push-pull waveform include four outputs with two outputs being complementary or two sets of two identical outputs. Refer to Sections 26.3.4 through 26.3.6 for the other Push-Pull modes. 26.3.3.1 Code for setting up the PSMC generate the complementary single-phase waveform shown in Figure 26-6, and given in Example 26-3. EXAMPLE 26-3: ; ; ; ; Mode Features • No dead-band control available • No steering control available • Output is on the following two pins only: - PSMCxA - PSMCxB Note: This is a subset of the 6-pin output of the push-pull PWM output, which is why pin functions are fixed in these positions, so they are compatible with that mode. See Section 26.3.6 “Push-Pull PWM with Four Full-Bridge and Complementary Outputs” 26.3.3.2 Waveform Generation Odd numbered period rising edge event: • PSMCxA is set active Odd numbered period falling edge event: • PSMCxA is set inactive ; ; ; ; PUSH-PULL SETUP Push-Pull PWM PSMC setup Fully synchronous operation Period = 10 us Duty cycle = 50% (25% each phase) BANKSEL PSMC1CON MOVLW 0x02 ; set period MOVWF PSMC1PRH MOVLW 0x7F MOVWF PSMC1PRL MOVLW 0x01 ; set duty cycle MOVWF PSMC1DCH MOVLW 0x3F MOVWF PSMC1DCL CLRF PSMC1PHH ; no phase offset CLRF PSMC1PHL MOVLW 0x01 ; PSMC clock=64 MHz MOVWF PSMC1CLK output on A and B, normal polarity MOVLW B’00000011’ MOVWF PSMC1OEN CLRF PSMC1POL set time base as source for all events BSF PSMC1PRS, P1PRST BSF PSMC1PHS, P1PHST BSF PSMC1DCS, P1DCST enable PSMC in Push-Pull Mode this also loads steering and time buffers MOVLW B’11000010’ MOVWF PSMC1CON BANKSEL TRISC BCF TRISC, 0 ; enable pin drivers BCF TRISC, 1 Even numbered period rising edge event: • PSMCxB is set active Even numbered period falling edge event: • PSMCxB is set inactive FIGURE 26-6: PUSH-PULL PWM WAVEFORM PWM Period Number 1 2 A Output 3 A Output Period Event B Output Rising Edge Event Falling Edge Event PSMCxA PSMCxB DS40001675C-page 243  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.3.4 PUSH-PULL PWM WITH COMPLEMENTARY OUTPUTS The complementary push-pull PWM is used to drive transistor bridge circuits as well as synchronous switches on the secondary side of the bridge. The PWM waveform is output on four pins presented as two pairs of two-output signals with a normal and complementary output in each pair. Dead band can be inserted between the normal and complementary outputs at the transition times. 26.3.4.1 Waveform Generation Push-Pull waveforms generate alternating outputs on the output pairs. Therefore, there are two sets of rising edge events and two sets of falling edge events Odd numbered period rising edge event: • PSMCxE is set inactive • Dead-band rising is activated (if enabled) • PSMCxA is set active Odd numbered period falling edge odd event: • PSMCxA is set inactive • Dead-band falling is activated (if enabled) • PSMCxE is set active Mode Features • Dead-band control is available • No steering control available • Primary PWM output is only on: - PSMCxA - PSMCxB • Complementary PWM output is only on: - PSMCxE - PSMCxF Even numbered period rising edge event: • PSMCxF is set inactive • Dead-band rising is activated (if enabled) • PSMCxB is set active Even numbered period falling edge event: Note: This is a subset of the 6-pin output of the push-pull PWM output, which is why pin functions are fixed in these positions, so they are compatible with that mode. See Section 26.3.6 “Push-Pull PWM with Four Full-Bridge and Complementary Outputs”. FIGURE 26-7: 26.3.4.2 • PSMCxB is set inactive • Dead-band falling is activated (if enabled) • PSMCxF is set active PUSH-PULL WITH COMPLEMENTARY OUTPUTS PWM WAVEFORM 1 PWM Period Number 2 3 Period Event Rising Edge Event Falling Edge Event Rising Edge Dead Band Rising Edge Dead Band PSMCxA Falling Edge Dead Band Falling Edge Dead Band PSMCxE PSMCxB Falling Edge Dead Band Rising Edge Dead Band PSMCxF  2013-2015 Microchip Technology Inc. DS40001675C-page 244 PIC16(L)F1788/9 26.3.5 PUSH-PULL PWM WITH FOUR FULL-BRIDGE OUTPUTS The full-bridge push-pull PWM is used to drive transistor bridge circuits as well as synchronous switches on the secondary side of the bridge. 26.3.5.1 Mode Features • No Dead-band control • No Steering control available • PWM is output on the following four pins only: - PSMCxA - PSMCxB - PSMCxC - PSMCxD Note: This is a subset of the 6-pin output of the push-pull PWM output, which is why pin functions are fixed in these positions, so they are compatible with that mode. See Section 26.3.6 “Push-Pull PWM with Four Full-Bridge and Complementary Outputs”. 26.3.5.2 Waveform generation Push-pull waveforms generate alternating outputs on the output pairs. Therefore, there are two sets of rising edge events and two sets of falling edge events. Odd numbered period rising edge event: • PSMCxOUT0 and PSMCxOUT2 is set active Odd numbered period falling edge event: Note: PSMCxA and PSMCxC are identical waveforms, and PSMCxB and PSMCxD are identical waveforms. • PSMCxOUT0 and PSMCxOUT2 is set inactive Even numbered period rising edge event: • PSMCxOUT1 and PSMCxOUT3 is set active Even numbered period falling edge event: • PSMCxOUT1 and PSMCxOUT3 is set inactive FIGURE 26-8: PUSH-PULL PWM WITH 4 FULL-BRIDGE OUTPUTS PWM Period Number 1 2 3 Period Event Rising Edge Event Falling Edge Event PSMCxA PSMCxC PSMCxB PSMCxD DS40001675C-page 245  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.3.6 PUSH-PULL PWM WITH FOUR FULL-BRIDGE AND COMPLEMENTARY OUTPUTS 26.3.6.2 The push-pull PWM is used to drive transistor bridge circuits as well as synchronous switches on the secondary side of the bridge. It uses six outputs and generates PWM signals with dead band that alternate between the six outputs in even and odd cycles. 26.3.6.1 Mode Features and Controls Push-pull waveforms generate alternating outputs on two sets of pin. Therefore, there are two sets of rising edge events and two sets of falling edge events Odd numbered period rising edge event: • PSMCxE is set inactive • Dead-band rising is activated (if enabled) • PSMCxA and PSMCxC are set active Odd numbered period falling edge event: • Dead-band control is available • No steering control available • Primary PWM is output on the following four pins: - PSMCxA - PSMCxB - PSMCxC - PSMCxD • Complementary PWM is output on the following two pins: - PSMCxE - PSMCxF Note: PSMCxA and PSMCxC are identical waveforms, and PSMCxB and PSMCxD are identical waveforms. FIGURE 26-9: Waveform Generation • PSMCxA and PSMCxC are set inactive • Dead-band falling is activated (if enabled) • PSMCxE is set active Even numbered period rising edge event: • PSMCxF is set inactive • Dead-band rising is activated (if enabled) • PSMCxB and PSMCxD are set active Even numbered period falling edge event: • PSMCxB and PSMCxOUT3 are set inactive • Dead-band falling is activated (if enabled) • PSMCxF is set active PUSH-PULL 4 FULL-BRIDGE AND COMPLEMENTARY PWM 1 PWM Period Number 2 3 Period Event Rising Edge Event Falling Edge Event Rising Edge Dead Band Rising Edge Dead Band PSMCxA PSMCxC Falling Edge Dead Band Falling Edge Dead Band PSMCxE PSMCxB PSMCxD Falling Edge Dead Band Rising Edge Dead Band PSMCxF  2013-2015 Microchip Technology Inc. DS40001675C-page 246 PIC16(L)F1788/9 26.3.7 PULSE-SKIPPING PWM 26.3.7.2 Waveform Generation The pulse-skipping PWM is used to generate a series of fixed-length pulses that can be triggered at each period event. A rising edge event will be generated when any enabled asynchronous rising edge input is active when the period event occurs, otherwise no event will be generated. Rising Edge Event The rising edge event occurs based upon the value in the PSMCxPH register pair. Falling Edge Event If any enabled asynchronous rising edge event = 1 when there is a period event, then upon the next synchronous rising edge event: • PSMCxA is set active • PSMCxA is set inactive The falling edge event always occurs according to the enabled event inputs without qualification between any two inputs. 26.3.7.1 Note: To use this mode, an external source must be used for the determination of whether or not to generate the set pulse. If the phase time base is used, it will either always generate a pulse or never generate a pulse based on the PSMCxPH value. Mode Features • No dead-band control available • No steering control available • PWM is output to only one pin: - PSMCxA FIGURE 26-10: PULSE-SKIPPING PWM WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 11 12 period_event Asynchronous Rising Edge Event Synchronous Rising Edge Event Falling Edge Event PSMCxA DS40001675C-page 247  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.3.8 PULSE-SKIPPING PWM WITH COMPLEMENTARY OUTPUTS 26.3.8.2 Waveform Generation Rising Edge Event The pulse-skipping PWM is used to generate a series of fixed-length pulses that may or not be triggered at each period event. If any of the sources enabled to generate a rising edge event are high when a period event occurs, a pulse will be generated. If the rising edge sources are low at the period event, no pulse will be generated. If any enabled asynchronous rising edge event = 1 when there is a period event, then upon the next synchronous rising edge event: The rising edge occurs based upon the value in the PSMCxPH register pair. Falling Edge Event • Complementary output is set inactive • Dead-band rising is activated (if enabled) • Primary output is set active • Primary output is set inactive • Dead-band falling is activated (if enabled) • Complementary output is set active The falling edge event always occurs according to the enabled event inputs without qualification between any two inputs. 26.3.8.1 • • • • Mode Features Note: To use this mode, an external source must be used for the determination of whether or not to generate the set pulse. If the phase time base is used, it will either always generate a pulse or never generate a pulse based on the PSMCxPH value. Dead-band control is available No steering control available Primary PWM is output on only PSMCxA. Complementary PWM is output on only PSMCxB. FIGURE 26-11: PULSE-SKIPPING WITH COMPLEMENTARY OUTPUT PWM WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 Period Event Asynchronous Rising Edge Event Synchronous Rising Edge Event PSMCxA Falling Edge Dead Band Rising Edge Dead Band PSMCxB  2013-2015 Microchip Technology Inc. DS40001675C-page 248 PIC16(L)F1788/9 26.3.9 ECCP COMPATIBLE FULL-BRIDGE PWM 26.3.9.2 In this mode of operation, three of the four pins are static. PSMCxA is the only output that changes based on rising edge and falling edge events. This mode of operation is designed to match the Full-Bridge mode from the ECCP module. It is called ECCP compatible as the term “full-bridge” alone has different connotations in regards to the output waveforms. Static Signal Assignment • Outputs set to active state - PSMCxD • Outputs set to inactive state - PSMCxB - PSMCxC Full-Bridge Compatible mode uses the same waveform events as the single PWM mode to generate the output waveforms. There are both Forward and Reverse modes available for this operation, again to match the ECCP implementation. Direction is selected with the mode control bits. 26.3.9.1 Waveform Generation - Forward Rising Edge Event • PSMCxA is set active Falling Edge Event Mode Features • PSMCxA is set inactive • Dead-band control available on direction switch - Changing from forward to reverse uses the falling edge dead-band counters. - Changing from reverse to forward uses the rising edge dead-band counters. • No steering control available • PWM is output on the following four pins only: - PSMCxA - PSMCxB - PSMCxC - PSMCxD 26.3.9.3 Waveform Generation – Reverse In this mode of operation, three of the four pins are static. Only PSMCxB toggles based on rising edge and falling edge events. Static Signal Assignment • Outputs set to active state - PSMCxC • Outputs set to inactive state - PSMCxA - PSMCxD Rising Edge Event • PSMCxB is set active Falling Edge Event • PSMCxB is set inactive FIGURE 26-12: ECCP COMPATIBLE FULL-BRIDGE PWM WAVEFORM – PSMCXSTR0 = 0FH PWM Period Number 1 2 3 4 Forward mode operation 5 6 7 8 9 10 11 12 Reverse mode operation Period Event Falling Edge Event PSMCxA PSMCxB PSMCxC Rising Edge Dead Band Falling Edge Dead Band PSMCxD DS40001675C-page 249  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.3.10 VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM Note: This mode of operation is quite different from all of the other modes. It uses only the period event for waveform generation. At each period event, the PWM output is toggled. The rising edge and falling edge events are unused in this mode. 26.3.10.1 Mode Features • No dead-band control available • No steering control available • Fractional Frequency Adjust - Fine period adjustments are made with the PSMC Fractional Frequency Adjust (PSMCxFFA) register (Register 26-29) • PWM is output on the following pin only: - PSMCxA 26.3.10.2 When using Variable Frequency mode, any fine adjustments to the period event should be made using the Fractional Frequency Adjust (PSMCxFFA) register. Increasing the period event by updating the PSMC Period Count Low Byte (PSMCxPRL) register directly with a value of '1', causes the period event to be updated twice and will result in an unexpected waveform at the output. Waveform Generation Period Event • Output of PSMCxA is toggled • FFA counter is incremented by the 4-bit value in PSMCxFFA FIGURE 26-13: VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 period_event Rising Edge Event Unused in this mode Falling Edge Event Unused in this mode PSMCxA  2013-2015 Microchip Technology Inc. DS40001675C-page 250 PIC16(L)F1788/9 26.3.11 VARIABLE FREQUENCY - FIXED DUTY CYCLE PWM WITH COMPLEMENTARY OUTPUTS 26.3.11.2 Period Event When output is going inactive to active: This mode is the same as the single output Fixed Duty Cycle mode except a complementary output with dead-band control is generated. • Complementary output is set inactive • FFA counter is incremented by the 4-bit value in PSMCFFA register. • Dead-band rising is activated (if enabled) • Primary output is set active The rising edge and falling edge events are unused in this mode. Therefore, a different triggering mechanism is required for the dead-band counters. When output is going active to inactive: A period events that generate a rising edge on PSMCxA use the rising edge dead-band counters. • Primary output is set inactive • FFA counter is incremented by the 4-bit value in PSMCFFA register • Dead-band falling is activated (if enabled) • Complementary output is set active A period events that generate a falling edge on PSMCxA use the falling edge dead-band counters. 26.3.11.1 Waveform Generation Mode Features • Dead-band control is available • No steering control available • Fractional Frequency Adjust - Fine period adjustments are made with the PSMC Fractional Frequency Adjust (PSMCxFFA) register (Register 26-29) • Primary PWM is output to the following pin: - PSMCxA • Complementary PWM is output to the following pin: - PSMCxB FIGURE 26-14: VARIABLE FREQUENCY – FIXED DUTY CYCLE PWM WITH COMPLEMENTARY OUTPUTS WAVEFORM PWM Period Number 1 2 3 4 5 6 7 8 9 10 period_event Rising Edge Event Unused in this mode Falling Edge Event Unused in this mode PSMCxA Falling Edge Dead Band Rising Edge Dead Band PSMCxB DS40001675C-page 251  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.3.12 3-PHASE PWM 26.3.12.2 Waveform Generation The 3-Phase mode of operation is used in 3-phase power supply and motor drive applications configured as three half-bridges. A half-bridge configuration consists of two power driver devices in series, between the positive power rail (high side) and negative power rail (low side). The three outputs come from the junctions between the two drivers in each half-bridge. When the steering control selects a phase drive, power flows from the positive rail through a high-side power device to the load and back to the power supply through a low-side power device. 3-phase steering has a more complex waveform generation scheme than the other modes. There are several factors which go into what waveforms are created. In this mode of operation, all six PSMC outputs are used, but only two are active at a time. Phase grouping is mapped as shown in Table 26-1. There are six possible phase drive combinations. Each phase drive combination activates two of the six outputs and deactivates the other four. Phase drive is selected with the steering control as shown in Table 26-2. The PSMC outputs are grouped into three sets of drivers: one for each phase. Each phase has two associated PWM outputs: one for the high-side drive and one for the low-side drive. High Side drives are indicated by 1H, 2H and 3H. Low Side drives are indicated by 1L, 2L, 3L. The two active outputs consist of a high-side driver and low-side driver output. 26.3.12.1 Mode Features TABLE 26-1: • No dead-band control is available • PWM can be steered to the following six pairs: - PSMCxA and PSMCxD - PSMCxA and PSMCxF - PSMCxC and PSMCxF - PSMCxC and PSMCxB - PSMCxE and PSMCxB - PSMCxE and PSMCxD TABLE 26-2: PHASE GROUPING PSMC grouping PSMCxA 1H PSMCxB 1L PSMCxC 2H PSMCxD 2L PSMCxE 3H PSMCxF 3L 3-PHASE STEERING CONTROL PSMCxSTR0 Value( 1) PSMC outputs PSMCxA 1H 00h 01h 02h 04h 08h 10h 20h inactive active active inactive inactive inactive inactive PSMCxB 1L inactive inactive inactive inactive active active inactive PSMCxC 2H inactive inactive inactive active active inactive inactive PSMCxD 2L inactive active inactive inactive inactive inactive active PSMCxE 3H inactive inactive inactive inactive inactive active active 3L inactive inactive active active inactive inactive inactive PSMCxF Note 1: Steering for any value other than those shown will default to the output combination of the Least Significant steering bit that is set. High/Low Side Modulation Enable It is also possible to enable the PWM output on the low side or high side drive independently using the PxLSMEN and PXHSMEN bits of the PSMC Steering Control 1 (PSMCxSTR1) register (Register 26-33). When the PxHSMEN bit is set, the active-high side output listed in Table 26-2 is modulated using the normal rising edge and falling edge events. When the PxLSMEN bit is set, the active-low side output listed in Table 26-2 is modulated using the normal rising edge and falling edge events.  2013-2015 Microchip Technology Inc. When both the PxHSMEN and PxLSMEN bits are cleared, the active outputs listed in Table 26-2 go immediately to the rising edge event states and do not change. Rising Edge Event • Active outputs are set to their active states Falling Edge Event • Active outputs are set to their inactive state DS40001675C-page 252  2013-2015 Microchip Technology Inc. FIGURE 26-15: 3-PHASE PWM STEERING WAVEFORM (PXHSMEN = 0 AND PXLSMEN = 1) 3-Phase State 1 2 3 4 5 6 PSMCxSTR0 01h 02h 04h 08h 10h 20h Period Event Rising Edge Event Falling Edge Event PSMCxA (1H) PSMCxB (1L) PSMCxC (2H) PSMCxD (2L) PSMCxE (3H) DS40001675C-page 253 PIC16(L)F1788/9 PSMCxF (3L) PIC16(L)F1788/9 26.4 Dead-Band Control The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in series connected power switches. Dead-band control is available only in modes with complementary drive and when changing direction in the ECCP compatible Full-Bridge modes. The module contains independent 8-bit dead-band counters for rising edge and falling edge dead-band control. 26.4.1 DEAD-BAND TYPES There are two separate dead-band generators available, one for rising edge events and the other for falling edge events. 26.4.1.1 Rising Edge Dead Band Rising edge dead-band control is used to delay the turn-on of the primary switch driver from when the complementary switch driver is turned off. Rising edge dead band is initiated with the rising edge event. Rising edge dead-band time is adjusted with the PSMC Rising Edge Dead-Band Time (PSMCxDBR) register (Register 26-27). If the PSMCxDBR register value is changed when the PSMC is enabled, the new value does not take effect until the first period event after the PSMCxLD bit is set. 26.4.1.2 Falling Edge Dead Band Falling edge dead-band control is used to delay the turn-on of the complementary switch driver from when the primary switch driver is turned off. Falling edge dead band is initiated with the falling edge event. Falling edge dead-band time is adjusted with the PSMC Falling Edge Dead-Band Time (PSMCxDBF) register (Register 26-28). If the PSMCxDBF register value is changed when the PSMC is enabled, the new value does not take effect until the first period event after the PSMCxLD bit is set. 26.4.2 DEAD-BAND ENABLE When a mode is selected that may use dead-band control, dead-band timing is enabled by setting one of the enable bits in the PSMC Control (PSMCxCON) register (Register 26-1). 26.4.3 DEAD-BAND CLOCK SOURCE The dead-band counters are incremented on every rising edge of the psmc_clk signal. 26.4.4 DEAD-BAND UNCERTAINTY When the rising and falling edge events that trigger the dead-band counters come from asynchronous inputs, there will be uncertainty in the actual dead-band time of each cycle. The maximum uncertainty is equal to one psmc_clk period. The one clock of uncertainty may still be introduced, even when the dead-band count time is cleared to zero. 26.4.5 DEAD-BAND OVERLAP There are two cases of dead-band overlap and each is treated differently due to system requirements. 26.4.5.1 Rising to Falling Overlap In this case, the falling edge event occurs while the rising edge dead-band counter is still counting. The following sequence occurs: 1. 2. 3. Dead-band rising count is terminated. Dead-band falling count is initiated. Primary output is suppressed. 26.4.5.2 Falling to Rising Overlap In this case, the rising edge event occurs while the falling edge dead-band counter is still counting. The following sequence occurs: 1. 2. 3. Dead-band falling count is terminated. Dead-band rising count is initiated. Complementary output is suppressed. 26.4.5.3 Rising Edge-to-Rising Edge or Falling Edge-to-Falling Edge In cases where one of the two dead-band counters is set for a short period, or disabled all together, it is possible to get rising-to-rising or falling-to-falling overlap. When this is the case, the following sequence occurs: 1. 2. 3. 4. 5. Dead-band count is terminated. Dead-band count is restarted. Output waveform control freezes in the present state. Restarted dead-band count completes. Output control resumes normally. Rising edge dead band is enabled with the PxDBRE bit. Rising edge dead band is enabled with the PxDBFE bit. Enable changes take effect immediately.  2013-2015 Microchip Technology Inc. DS40001675C-page 254 PIC16(L)F1788/9 26.5 Output Steering Output steering allows for PWM signals generated by the PSMC module to be placed on different pins under software control. Synchronized steering will hold steering changes until the first period event after the PSMCxLD bit is set. Unsynchronized steering changes will take place immediately. Output steering is available in the following modes: • 3-phase PWM • Single PWM • Complementary PWM FIGURE 26-16: 26.5.1 3-PHASE STEERING 3-phase steering is available in the 3-Phase Modulation mode only. For more details on 3-phase steering refer to Section 26.3.12 “3-Phase PWM”. 26.5.2 SINGLE PWM STEERING In Single PWM Steering mode, the single PWM signal can be routed to any combination of the PSMC output pins. Examples of unsynchronized single PWM steering are shown in Figure 26-16. SINGLE PWM STEERING WAVEFORM (NO SYNCHRONIZATION) Base_PWM_signal PxSTRA PSMCxA PxSTRB PSMCxB PxSTRC PSMCxC PxSTRD PSMCxD PxSTRE PSMCxE PxSTRF PSMCxF With synchronization disabled, it is possible to get glitches on the PWM outputs. DS40001675C-page 255  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.5.3 COMPLEMENTARY PWM STEERING The complementary PWM signal can be steered to any of the following outputs: In Complementary PWM Steering mode, the primary PWM signal (non-complementary) and complementary signal can be steered according to their respective type. • PSMCxB • PSMCxD • PSMCxE Primary PWM signal can be steered to any of the following outputs: Examples of unsynchronized complementary steering are shown in Figure 26-17. • PSMCxA • PSMCxC • PSMCxE FIGURE 26-17: COMPLEMENTARY PWM STEERING WAVEFORM (NO SYNCHRONIZATION, ZERO DEAD-BAND TIME) Base_PWM_signal PxSTRA PSMCxA PSMCxB PxSTRB Arrows indicate where a change in the steering bit automatically forces a change in the corresponding PSMC output. PxSTRC PSMCxC PSMCxD PxSTRD PxSTRE PSMCxE PSMCxF PxSTRF  2013-2015 Microchip Technology Inc. DS40001675C-page 256 PIC16(L)F1788/9 26.5.4 SYNCHRONIZED PWM STEERING Examples of synchronized steering are shown in Figure 26-18. In Single, Complementary and 3-phase PWM modes, it is possible to synchronize changes to steering selections with the period event. This is so that PWM outputs do not change in the middle of a cycle and therefore, disrupt operation of the application. 26.5.5 If synchronized steering is to be used, special care should be taken to initialize the PSMC Steering Control 0 (PSMCxSTR0) register (Register 26-32) in a safe configuration before setting either the PSMCxEN or PSMCxLD bits. When either of those bits are set, the PSMCxSTR0 value at that time is loaded into the synchronized steering output buffer. The buffer load occurs even if the PxSSYNC bit is low. When the PxSSYNC bit is set, the outputs will immediately go to the drive states in the preloaded buffer. Steering synchronization is enabled by setting the PxSSYNC bit of the PSMC Steering Control 1 (PSMCxSTR1) register (Register 26-33). When synchronized steering is enabled while the PSMC module is enabled, steering changes do not take effect until the first period event after the PSMCxLD bit is set. FIGURE 26-18: Period Number INITIALIZING SYNCHRONIZED STEERING PWM STEERING WITH SYNCHRONIZATION WAVEFORM 1 2 3 4 5 6 7 PWM Signal PxSTRA Synchronized PxSTRA PxSTRB Synchronized PxSTRB PSMCxA PSMCxB DS40001675C-page 257  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.6 26.6.2.1 PSMC Modulation (Burst Mode) PSMC modulation is a method to stop/start PWM operation of the PSMC without having to disable the module. It also allows other modules to control the operational period of the PSMC. This is also referred to as Burst mode. This is a method to implement PWM dimming. 26.6.1 MODULATION ENABLE The modulation function is enabled by setting the PxMDLEN bit of PSMC Modulation Control (PSMCxMDL) register (Register 26-2). When modulation is enabled, the modulation source controls when the PWM signals are active and inactive. When modulation is disabled, the PWM signals operate continuously, regardless of the selected modulation source. 26.6.2 MODULATION SOURCES There are multiple sources that can be used for modulating the PSMC. However, unlike the PSMC input sources, only one modulation source can be selected at a time. Modulation sources include: • • • • PxMDLBIT Bit The PxMDLBIT bit of the PSMC Modulation Control (PSMCxMDL) register (Register 26-2) allows for software modulation control without having to enable/disable other module functions. 26.6.3 MODULATION EFFECT ON PWM SIGNALS When modulation starts, the PSMC begins operation on a new period, just as if it had rolled over from one period to another during continuous operation. When modulation stops, its operation depends on the type of waveform being generated. In operation modes other than Fixed Duty Cycle, the PSMC completes its current PWM period and then freezes the module. The PSMC output pins are forced into the default inactive state ready for use when modulation starts. In Fixed Duty Cycle mode operation, the PSMC continues to operate until the period event changes the PWM to its inactive state, at which point the PSMC module is frozen. The PSMC output pins are forced into the default inactive state ready for use when modulation starts. PSMCxIN pin Any CCP output Any Comparator output PxMDLBIT of the PSMCxMDL register FIGURE 26-19: PSMC MODULATION WAVEFORM 1 2 3 4 5 6 7 1 1 2 3 4 5 Modulation Input PWM Off PWM Period  2013-2015 Microchip Technology Inc. PWM Off PWM Off DS40001675C-page 258 PIC16(L)F1788/9 26.7 Auto-Shutdown Auto-shutdown is a method to immediately override the PSMC output levels with specific overrides that allow for safe shutdown of the application. Auto-shutdown includes a mechanism to allow the application to restart under different conditions. Auto-shutdown is enabled with the PxASDEN bit of the PSMC Auto-shutdown Control (PSMCxASDC) register (Register 26-16). All auto-shutdown features are enabled when PxASDEN is set and disabled when cleared. 26.7.1 SHUTDOWN There are two ways to generate a shutdown event: • Manual • External Input 26.7.1.1 Manual Override The auto-shutdown control register can be used to manually override the pin functions. Setting the PxASE bit of the PSMC Auto-shutdown Control (PSMCxASDC) register (Register 26-16) generates a software shut-down event. The auto-shutdown override will persist as long as PxASE remains set. 26.7.1.2 External Input Source Any of the given sources that are available for event generation are also available for system shut-down. This is so that external circuitry can monitor and force a shutdown without any software overhead. Auto-shutdown sources are selected with the PSMC Auto-shutdown Source (PSMCxASDS) register (Register 26-18). When any of the selected external auto-shutdown sources go high, the PxASE bit is set and an auto-shutdown interrupt is generated. Note: The external shutdown sources are level sensitive, not edge sensitive. The shutdown condition will persist as long as the circuit is driving the appropriate logic level. DS40001675C-page 259 26.7.2 PIN OVERRIDE LEVELS The logic levels driven to the output pins during an auto-shutdown event are determined by the PSMC Auto-shutdown Output Level (PSMCxASDL) register (Register 26-17). 26.7.2.1 PIN Override Enable Setting the PxASDOV bit of the PSMC Auto-shutdown Control (PSMCxASDC) register (Register 26-16) will also force the override levels onto the pins, exactly like what happens when the auto-shutdown is used. However, whereas setting PxASE causes an auto-shutdown interrupt, setting PxASDOV does not generate an interrupt. 26.7.3 RESTART FROM AUTO-SHUTDOWN After an auto-shutdown event has occurred, there are two ways for the module to resume operation: • Manual restart • Automatic restart The restart method is selected with the PxARSEN bit of the PSMC Auto-shutdown Control (PSMCxASDC) register (Register 26-16). 26.7.3.1 Manual Restart When PxARSEN is cleared, and once the PxASDE bit is set, it will remain set until cleared by software. The PSMC will restart on the period event after PxASDE bit is cleared in software. 26.7.3.2 Auto-Restart When PxARSEN is set, the PxASDE bit will clear automatically when the source causing the Reset and no longer asserts the shut-down condition. The PSMC will restart on the next period event after the auto-shutdown condition is removed. Examples of manual and automatic restart are shown in Figure 26-20. Note: Whether manual or auto-restart is selected, the PxASDE bit cannot be cleared in software when the auto-shutdown condition is still present.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 26-20: AUTO-SHUTDOWN AND RESTART WAVEFORM 1 2 3 4 5 Base PWM signal PxARSEN Next Period Event Auto-Shutdown Source cleared in software PSMCx Auto-shutdown int flag bit cleared in software Cleared in hardware Next Period Event PxASE Cleared in software PSMCxA PSMCxB Operating State Normal Output Autoshutdown Manual Restart  2013-2015 Microchip Technology Inc. Normal Output Autoshutdown Normal Output Auto-restart DS40001675C-page 260 PIC16(L)F1788/9 26.8 26.8.1 PSMC Synchronization It is possible to synchronize the periods of two or more PSMC modules together, provided that all modules are on the same device. Synchronization is achieved by sending a sync signal from the master PSMC module to the desired slave modules. This sync signal generates a period event in each slave module, thereby aligning all slaves with the master. This is useful when an application requires different PWM signal generation from each module but the waveforms must be consistent within a PWM period. FIGURE 26-21: SYNCHRONIZATION SOURCES The synchronization source can be any PSMC module on the same device. For example, in a device with two PSMC modules, the possible sources for each device is as shown below: • Sources for PSMC1 - PSMC2 • Sources for PSMC2 - PSMC1 PSMC SYNCHRONIZATION - SYNC OUTPUT TO PIN 1 2 3 psmc_clk Period Event Caution must be used so that glitches on the period event are not missed Rising Edge Event Falling Edge Event PSMCx Output 26.8.1.1 PSMC Internal Connections The sync signal from the master PSMC module is essentially that modules period event trigger. The slave PSMC modules reset their PSMCxTMR with the sync signal instead of their own period event. Enabling a module as a slave recipient is done with the PxSYNC bits of the PSMC Synchronization Control (PSMCxSYNC) registers; registers 26-3 and 26-4. 26.8.1.2 Phase Offset Synchronization The synchronization output signal from the PSMC module is selectable. The sync_out source may be either: • Period Event • Rising Event Source selection is made with the PxPOFST bit of the PSMCxSYNC registers, registers 26-3, 26-4 and 26-7. DS40001675C-page 261 When the PxPOFST bit is set, the sync_out signal comes from the rising event and the period event replaces the rising event as the start of the active drive period. When PxPOFST is set, duty cycles of up to 100% are achievable in both the slave and master. When PXPOFST is clear, the sync_out signal comes from the period event. When PxPOFST is clear, rising events that start after the period event remove the equivalent start delay percentage from the maximum 100% duty cycle. 26.8.1.3 Synchronization Skid When the sync_out source is the Period Event, the slave synchronous rising and falling events will lag by one psmc_clk period. When the sync_out source is the Rising Event, the synchronous events will lag by two clock periods. To compensate for this, the values in PHH:PHL and DCH:DCL registers can be reduced by the number of lag cycles.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.9 Fractional Frequency Adjust (FFA) FFA is a method by which PWM resolution can be improved on 50% fixed duty cycle signals. Higher resolution is achieved by altering the PWM period by a single count for calculated intervals. This increased resolution is based upon the PWM frequency averaged over a large number of PWM periods. For example, if the period event time is increased by one FIGURE 26-22: psmc_clk period (TPSMC_CLK) every N events, then the effective resolution of the average event period is TPSMC_CLK/N. When active, after every period event the FFA hardware adds the PSMCxFFA value with the previously accumulated result. Each time the addition causes an overflow, the period event time is increased by one. Refer to Figure 26-22. FFA BLOCK DIAGRAM. PSMCxFFA   Accumulator carry psmc_clk The FFA function is only available when using one of the two Fixed Duty Cycle modes of operation. In fixed duty cycle operation each PWM period is comprised of two period events. That is why the PWM periods in Table 26-3 example calculations are multiplied by two as opposed to the normal period calculations for normal mode operation. The extra resolution gained by the FFA is based upon the number of bits in the FFA register and the psmc_clk frequency. The parameters of interest are: • TPWM – this is the lower bound of the PWM period that will be adjusted • TPWM+1 – this is the upper bound of the PWM period that will be adjusted. This is used to help determine the step size for each increment of the FFA register • TRESOLUTION – each increment of the FFA register will add this amount of period to average PWM frequency  2013-2015 Microchip Technology Inc. PSMCxPR Comparator = Period Event PSMCxTMR TABLE 26-3: FRACTIONAL FREQUENCY ADJUST CALCULATIONS Parameter Value FPSMC_CLK 64 MHz TPSMC_CLK 15.625 ns PSMCxPR 00FFh = 255 TPWM = (PSMCxPR+1)*2*TPSMC_CLK = 256*2*15.625ns = 8 us FPWM 125 kHz TPWM+1 = (PSMCxPR+2)*2*TPSMC_CLK = 257*2*15.625ns = 8.03125 us FPWM+1 = 124.513 kHz TRESOLUTION = (TPWM+1-TPWM)/2FFA-Bits = (8.03125us - 8.0 us)/16 = 0.03125us/16 ~ 1.95 ns FRESOLUTION (FPWM+1-FPWM)/2FFA-Bits ~ -30.4 Hz DS40001675C-page 262 PIC16(L)F1788/9 TABLE 26-4: SAMPLE FFA OUTPUT PERIODS/FREQUENCIES FFA number Output Frequency (kHz) Step Size (Hz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 125.000 124.970 124.939 124.909 124.878 124.848 124.818 124.787 124.757 124.726 124.696 124.666 124.635 124.605 124.574 124.544 0 -30.4 -60.8 -91.2 -121.6 -152.0 -182.4 -212.8 -243.2 -273.6 -304.0 -334.4 -364.8 -395.2 -425.6 -456.0 DS40001675C-page 263  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 26.10 Register Updates 26.11 Operation During Sleep There are ten double-buffered registers that can be updated “on the fly”. However, due to the asynchronous nature of the potential updates, a special hardware system is used for the updates. The PSMC continues to operate in Sleep with the following clock sources: There are two operating cases for the PSMC: • Internal 64 MHz • External clock • module is enabled • module is disabled 26.10.1 DOUBLE BUFFERED REGISTERS The double-buffered registers that are affected by the special hardware update system are: • • • • • • • • • • • PSMCxPRL PSMCxPRH PSMCxDCL PSMCxDCH PSMCxPHL PSMCxPHH PSMCxDBR PSMCxDBF PSMCxBLKR PSMCxBLKF PSMCxSTR0 (when the PxSSYNC bit is set) 26.10.2 MODULE DISABLED UPDATES When the PSMC module is disabled (PSMCxEN = 0), any write to one of the buffered registers will also write directly to the buffer. This means that all buffers are loaded and ready for use when the module is enabled. 26.10.3 MODULE ENABLED UPDATES When the PSMC module is enabled (PSMCxEN = 1), the PSMCxLD bit of the PSMC Control (PSMCxCON) register (Register 26-1) must be used. When the PSMCxLD bit is set, the transfer from the register to the buffer occurs on the next period event. The PSMCxLD bit is automatically cleared by hardware after the transfer to the buffers is complete. The reason that the PSMCxLD bit is required is that depending on the customer application and operation conditions, all 10 registers may not be updated in one PSMC period. If the buffers are loaded at different times (i.e., DCL gets updated, but DCH does not OR DCL and DCL are updated by PRH and PRL are not), then unintended operation may occur. The sequence for loading the buffer registers when the PSMC module is enabled is as follows: 1. 2. 3. 4. Software updates all registers. Software sets the PSMCxLD bit. Hardware updates all buffers on the next period event. Hardware clears PSMCxLD bit.  2013-2015 Microchip Technology Inc. DS40001675C-page 264 PIC16(L)F1788/9 26.12 Register Definitions: PSMC Control REGISTER 26-1: PSMCxCON: PSMC CONTROL REGISTER R/W-0/0 R/W/HC-0/0 R/W-0/0 R/W-0/0 PSMCxEN PSMCxLD PxDBFE PxDBRE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxMODE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PSMCxEN: PSMC Module Enable bit 1 = PSMCx module is enabled 0 = PSMCx module is disabled bit 6 PSMCxLD: PSMC Load Buffer Enable bit 1 = PSMCx registers are ready to be updated with the appropriate register contents 0 = PSMCx buffer update complete bit 5 PxDBFE: PSMC Falling Edge Dead-Band Enable bit 1 = PSMCx falling edge dead band enabled 0 = PSMCx falling edge dead band disabled bit 4 PxDBRE: PSMC Rising Edge Dead-Band Enable bit 1 = PSMCx rising edge dead band enabled 0 = PSMCx rising edge dead band disabled bit 3-0 PxMODE PSMC Operating Mode bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = 3-phase steering PWM 1011 = Fixed duty cycle, variable frequency, complementary PWM 1010 = Fixed duty cycle, variable frequency, single PWM 1001 = ECCP compatible Full-Bridge forward output 1000 = ECCP compatible Full-Bridge reverse output 0111 = Pulse-skipping with complementary output 0110 = Pulse-skipping PWM output 0101 = Push-pull with four full-bridge outputs and complementary outputs 0100 = Push-pull with four full-bridge outputs 0011 = Push-pull with complementary outputs 0010 = Push-pull output 0001 = Single PWM with complementary output (with PWM steering capability) 0000 = Single PWM waveform generation (with PWM steering capability) DS40001675C-page 265  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-2: PSMCxMDL: PSMC MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxMDLEN PxMDLPOL PxMDLBIT — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxMSRC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxMDLEN: PSMC Periodic Modulation Mode Enable bit 1 = PSMCx is active when input signal selected by PxMSRC is in its active state (see PxMPOL) 0 = PSMCx module is always active bit 6 PxMDLPOL: PSMC Periodic Modulation Polarity bit 1 = PSMCx is active when the PSMCx Modulation source output equals logic ‘0’ (active-low) 0 = PSMCx is active when the PSMCx Modulation source output equals logic ‘1’ (active-high) bit 5 PxMDLBIT: PSMC Periodic Modulation Software Control bit PxMDLEN = 1 AND PxMSRC = 0000 1 = PSMCx is active when the PxMDLPOL equals logic ‘0’ 0 = PSMCx is active when the PxMDLPOL equals logic ‘1’ PxMDLEN = 0 OR (PxMDLEN = 1 and PxMSRC ‘0000’) Does not affect module operation bit 4 Unimplemented: Read as ‘0’ bit 3-0 PxMSRC PSMC Periodic Modulation Source Selection bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = PSMCx Modulation Source is PSMCxIN pin 0111 = Reserved 0110 = PSMCx Modulation Source is CCP2 0101 = PSMCx Modulation Source is CCP1 0100 = Reserved 0011 = PSMCx Modulation Source is sync_C3OUT 0010 = PSMCx Modulation Source is sync_C2OUT 0001 = PSMCx Modulation Source is sync_C1OUT 0000 = PSMCx Modulation Source is PxMDLBIT register bit  2013-2015 Microchip Technology Inc. DS40001675C-page 266 PIC16(L)F1788/9 REGISTER 26-3: PSMC1SYNC: PSMC1 SYNCHRONIZATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 P1POFST P1PRPOL P1DCPOL — — R/W-0/0 R/W-0/0 R/W-0/0 P1SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P1POFST: PSMC1 Phase Offset Control bit 1 = sync_out source is phase event and latch set source is synchronous period event 0 = sync_out source is period event and latch set source is phase event bit 6 P1PRPOL: PSMC1 Period Polarity Event Control bit 1 = Selected asynchronous period event inputs are inverted 0 = Selected asynchronous period event inputs are not inverted bit 5 P1DCPOL: PSMC1 Duty-cycle Event Polarity Control bit 1 = Selected asynchronous duty-cycle event inputs are inverted 0 = Selected asynchronous duty-cycle event inputs are not inverted bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 P1SYNC: PSMC1 Period Synchronization Mode bits 1xx = Reserved - Do not use 100 = PSMC1 is synchronized with the PSMC4 module (sync_in comes from PSMC4 sync_out) 011 = PSMC1 is synchronized with the PSMC3 module (sync_in comes from PSMC3 sync_out) 010 = PSMC1 is synchronized with the PSMC2 module (sync_in comes from PSMC3 sync_out) 001 = PSMC1 is synchronized with the PSMC1 module (sync_in comes from PSMC3 sync_out) 000 = PSMC1 is synchronized with period event REGISTER 26-4: PSMC2SYNC: PSMC2 SYNCHRONIZATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 P2POFST P2PRPOL P2DCPOL — — R/W-0/0 R/W-0/0 R/W-0/0 P2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P2POFST: PSMC2 Phase Offset Control bit 1 = sync_out source is phase event and latch set source is synchronous period event 0 = sync_out source is period event and latch set source is phase event bit 6 P2PRPOL: PSMC2 Period Polarity Event Control bit 1 = Selected asynchronous period event inputs are inverted 0 = Selected asynchronous period event inputs are not inverted bit 5 P2DCPOL: PSMC2 Duty-cycle Event Polarity Control bit 1 = Selected asynchronous duty-cycle event inputs are inverted 0 = Selected asynchronous duty-cycle event inputs are not inverted bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 P2SYNC: PSMC2 Period Synchronization Mode bits 1xx = Reserved - Do not use 100 = PSMC2 is synchronized with the PSMC4 module (sync_in comes from PSMC4 sync_out) 011 = PSMC2 is synchronized with the PSMC3 module (sync_in comes from PSMC3 sync_out) 010 = PSMC2 is synchronized with the PSMC2 module (sync_in comes from PSMC3 sync_out) 001 = PSMC2 is synchronized with the PSMC1 module (sync_in comes from PSMC3 sync_out) 000 = PSMC2 is synchronized with period event DS40001675C-page 267  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-5: PSMC3SYNC: PSMC3 SYNCHRONIZATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 P3POFST P3PRPOL P3DCPOL — — R/W-0/0 R/W-0/0 R/W-0/0 P3SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P3POFST: PSMC3 Phase Offset Control bit 1 = sync_out source is phase event and latch set source is synchronous period event 0 = sync_out source is period event and latch set source is phase event bit 6 P3PRPOL: PSMC3 Period Polarity Event Control bit 1 = Selected asynchronous period event inputs are inverted 0 = Selected asynchronous period event inputs are not inverted bit 5 P3DCPOL: PSMC3 Duty-cycle Event Polarity Control bit 1 = Selected asynchronous duty-cycle event inputs are inverted 0 = Selected asynchronous duty-cycle event inputs are not inverted bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 P3SYNC: PSMC3 Period Synchronization Mode bits 1xx = Reserved - Do not use 100 = PSMC3 is synchronized with the PSMC4 module (sync_in comes from PSMC4 sync_out) 011 = PSMC3 is synchronized with the PSMC3 module (sync_in comes from PSMC3 sync_out) 010 = PSMC3 is synchronized with the PSMC2 module (sync_in comes from PSMC3 sync_out) 001 = PSMC3 is synchronized with the PSMC1 module (sync_in comes from PSMC3 sync_out) 000 = PSMC3 is synchronized with period event  2013-2015 Microchip Technology Inc. DS40001675C-page 268 PIC16(L)F1788/9 REGISTER 26-6: PSMC4SYNC: PSMC3 SYNCHRONIZATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 P4POFST P4PRPOL P4DCPOL — — R/W-0/0 R/W-0/0 R/W-0/0 P4SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P4POFST: PSMC4 Phase Offset Control bit 1 = sync_out source is phase event and latch set source is synchronous period event 0 = sync_out source is period event and latch set source is phase event bit 6 P4PRPOL: PSMC4 Period Polarity Event Control bit 1 = Selected asynchronous period event inputs are inverted 0 = Selected asynchronous period event inputs are not inverted bit 5 P4DCPOL: PSMC4 Duty-cycle Event Polarity Control bit 1 = Selected asynchronous duty-cycle event inputs are inverted 0 = Selected asynchronous duty-cycle event inputs are not inverted bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 P4SYNC: PSMC4 Period Synchronization Mode bits 1xx = Reserved - Do not use 100 = PSMC4 is synchronized with the PSMC4 module (sync_in comes from PSMC4 sync_out) 011 = PSMC4 is synchronized with the PSMC3 module (sync_in comes from PSMC3 sync_out) 010 = PSMC4 is synchronized with the PSMC2 module (sync_in comes from PSMC3 sync_out) 001 = PSMC4 is synchronized with the PSMC1 module (sync_in comes from PSMC3 sync_out) 000 = PSMC4 is synchronized with period event DS40001675C-page 269  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-7: PSMCxCLK: PSMC CLOCK CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 PxCPRE U-0 U-0 — — R/W-0/0 R/W-0/0 PxCSRC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 PxCPRE: PSMCx Clock Prescaler Selection bits 11 = PSMCx Clock frequency/8 10 = PSMCx Clock frequency/4 01 = PSMCx Clock frequency/2 00 = PSMCx Clock frequency/1 bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 PxCSRC: PSMCx Clock Source Selection bits 11 = Reserved 10 = PSMCxCLK pin 01 = 64 MHz clock in from PLL 00 = FOSC system clock REGISTER 26-8: PSMCxOEN: PSMC OUTPUT ENABLE CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — PxOEF(1) PxOEE(1) PxOED(1) PxOEC(1) PxOEB PxOEA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PxOEy: PSMCx Output y Enable bit(1) 1 = PWM output is active on PSMCx output y pin 0 = PWM output is not active, normal port functions in control of pin Note 1: These bits are not implemented on PSMC2.  2013-2015 Microchip Technology Inc. DS40001675C-page 270 PIC16(L)F1788/9 REGISTER 26-9: U-0 PSMCxPOL: PSMC POLARITY CONTROL REGISTER R/W-0/0 — PxPOLIN R/W-0/0 PxPOLF (1) R/W-0/0 (1) PxPOLE R/W-0/0 (1) PxPOLD R/W-0/0 PxPOLC (1) R/W-0/0 R/W-0/0 PxPOLB PxPOLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 PxPOLIN: PSMCxIN Polarity bit 1 = PSMCxIN input is active-low 0 = PSMCxIN input is active-high bit 5-0 PxPOLy: PSMCx Output y Polarity bit(1) 1 = PWM PSMCx output y is active-low 0 = PWM PSMCx output y is active-high Note 1: These bits are not implemented on PSMC2. REGISTER 26-10: PSMCxBLNK: PSMC BLANKING CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — — PxFEBM1 PxFEBM0 — — PxREBM1 PxREBM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 PxFEBM PSMC Falling Edge Blanking Mode bits 11 = Reserved – do not use 10 = Reserved – do not use 01 = Immediate blanking 00 = No blanking bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 PxREBM PSMC Rising Edge Blanking Mode bits 11 = Reserved – do not use 10 = Reserved – do not use 01 = Immediate blanking 00 = No blanking DS40001675C-page 271  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-11: PSMCxREBS: PSMC RISING EDGE BLANKED SOURCE REGISTER R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxREBSIN — — PxREBSC4 PxREBSC3 PxREBSC2 PxREBSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxREBSIN: PSMCx Rising Edge Event Blanked from PSMCxIN pin 1 = PSMCxIN pin cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = PSMCxIN pin is not blanked bit 6-5 Unimplemented: Read as ‘0’ bit 4 PxREBSC4: PSMCx Rising Edge Event Blanked from sync_C4OUT 1 = sync_C4OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C4OUT is not blanked bit 3 PxREBSC3: PSMCx Rising Edge Event Blanked from sync_C3OUT 1 = sync_C3OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C3OUT is not blanked bit 2 PxREBSC2: PSMCx Rising Edge Event Blanked from sync_C2OUT 1 = sync_C2OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C2OUT is not blanked bit 1 PxREBSC1: PSMCx Rising Edge Event Blanked from sync_C1OUT 1 = sync_C1OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C1OUT is not blanked bit 0 Unimplemented: Read as ‘0’ REGISTER 26-12: PSMCxFEBS: PSMC FALLING EDGE BLANKED SOURCE REGISTER R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 PxFEBSIN — — PxFEBSC4 PxFEBSC3 PxFEBSC2 PxFEBSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxFEBSIN: PSMCx Falling Edge Event Blanked from PSMCxIN pin 1 = PSMCxIN pin cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = PSMCxIN pin is not blanked bit 6-5 Unimplemented: Read as ‘0’ bit 4 PxFEBSC4: PSMCx Falling Edge Event Blanked from sync_C4OUT 1 = sync_C4OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C4OUT is not blanked bit 3 PxFEBSC3: PSMCx Falling Edge Event Blanked from sync_C3OUT 1 = sync_C3OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C3OUT is not blanked bit 2 PxFEBSC2: PSMCx Falling Edge Event Blanked from sync_C2OUT 1 = sync_C2OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C2OUT is not blanked bit 1 PxFEBSC1: PSMCx Falling Edge Event Blanked from sync_C1OUT 1 = sync_C1OUT cannot cause a rising or falling event for the duration indicated by the PSMCxBLNK register 0 = sync_C1OUT is not blanked bit 0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS40001675C-page 272 PIC16(L)F1788/9 REGISTER 26-13: PSMCxPHS: PSMC PHASE SOURCE REGISTER(1) R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxPHSIN — — PxPHSC4 PxPHSC3 PxPHSC2 PxPHSC1 PxPHST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxPHSIN: PSMCx Rising Edge Event occurs on PSMCxIN pin 1 = Rising edge event will occur when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause rising edge event bit 6-5 Unimplemented: Read as ‘0’ bit 4 PxPHSC4: PSMCx Rising Edge Event occurs on sync_C4OUT output 1 = Rising edge event will occur when sync_C4OUT output goes true 0 = sync_C4OUT will not cause rising edge event bit 3 PxPHSC3: PSMCx Rising Edge Event occurs on sync_C3OUT output 1 = Rising edge event will occur when sync_C3OUT output goes true 0 = sync_C3OUT will not cause rising edge event bit 2 PxPHSC2: PSMCx Rising Edge Event occurs on sync_C2OUT output 1 = Rising edge event will occur when sync_C2OUT output goes true 0 = sync_C2OUT will not cause rising edge event bit 1 PxPHSC1: PSMCx Rising Edge Event occurs on sync_C1OUT output 1 = Rising edge event will occur when sync_C1OUT output goes true 0 = sync_C1OUT will not cause rising edge event bit 0 PxPHST: PSMCx Rising Edge Event occurs on Time Base match 1 = Rising edge event will occur when PSMCxTMR = PSMCxPH 0 = Time base will not cause rising edge event Note 1: Sources are not mutually exclusive: more than one source can cause a rising edge event. DS40001675C-page 273  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-14: PSMCxDCS: PSMC DUTY CYCLE SOURCE REGISTER(1) R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxDCSIN — — PxDCSC4 PxDCSC3 PxDCSC2 PxDCSC1 PxDCST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxDCSIN: PSMCx Falling Edge Event occurs on PSMCxIN pin 1 = Falling edge event will occur when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause falling edge event bit 6-5 Unimplemented: Read as ‘0’ bit 4 PxDCSC4: PSMCx Falling Edge Event occurs on sync_C4OUT output 1 = Falling edge event will occur when sync_C4OUT output goes true 0 = sync_C4OUT will not cause falling edge event bit 3 PxDCSC3: PSMCx Falling Edge Event occurs on sync_C3OUT output 1 = Falling edge event will occur when sync_C3OUT output goes true 0 = sync_C3OUT will not cause falling edge event bit 2 PxDCSC2: PSMCx Falling Edge Event occurs on sync_C2OUT output 1 = Falling edge event will occur when sync_C2OUT output goes true 0 = sync_C2OUT will not cause falling edge event bit 1 PxDCSC1: PSMCx Falling Edge Event occurs on sync_C1OUT output 1 = Falling edge event will occur when sync_C1OUT output goes true 0 = sync_C1OUT will not cause falling edge event bit 0 PxDCST: PSMCx Falling Edge Event occurs on Time Base match 1 = Falling edge event will occur when PSMCxTMR = PSMCxDC 0 = Time base will not cause falling edge event Note 1: Sources are not mutually exclusive: more than one source can cause a falling edge event.  2013-2015 Microchip Technology Inc. DS40001675C-page 274 PIC16(L)F1788/9 REGISTER 26-15: PSMCxPRS: PSMC PERIOD SOURCE REGISTER(1) R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxPRSIN — — PxPRSC4 PxPRSC3 PxPRSC2 PxPRSC1 PxPRST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxPRSIN: PSMCx Period Event occurs on PSMCxIN pin 1 = Period event will occur and PSMCxTMR will reset when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause period event bit 6-5 Unimplemented: Read as ‘0’ bit 4 PxPRSC4: PSMCx Period Event occurs on sync_C4OUT output 1 = Period event will occur and PSMCxTMR will reset when sync_C4OUT output goes true 0 = sync_C4OUT will not cause period event bit 3 PxPRSC3: PSMCx Period Event occurs on sync_C3OUT output 1 = Period event will occur and PSMCxTMR will reset when sync_C3OUT output goes true 0 = sync_C3OUT will not cause period event bit 2 PxPRSC2: PSMCx Period Event occurs on sync_C2OUT output 1 = Period event will occur and PSMCxTMR will reset when sync_C2OUT output goes true 0 = sync_C2OUT will not cause period event bit 1 PxPRSC1: PSMCx Period Event occurs on sync_C1OUT output 1 = Period event will occur and PSMCxTMR will reset when sync_C1OUT output goes true 0 = sync_C1OUT will not cause period event bit 0 PxPRST: PSMCx Period Event occurs on Time Base match 1 = Period event will occur and PSMCxTMR will reset when PSMCxTMR = PSMCxPR 0 = Time base will not cause period event Note 1: Sources are not mutually exclusive: more than one source can force the period event and reset the PSMCxTMR. DS40001675C-page 275  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-16: PSMCxASDC: PSMC AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 PxASE PxASDEN PxARSEN — — — — PxASDOV bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxASE: PWM Auto-Shutdown Event Status bit(1) 1 = A shutdown event has occurred, PWM outputs are inactive and in their shutdown states 0 = PWM outputs are operating normally bit 6 PxASDEN: PWM Auto-Shutdown Enable bit 1 = Auto-shutdown is enabled. If any of the sources in PSMCxASDS assert a logic ‘1’, then the outputs will go into their auto-shutdown state and PSMCxSIF flag will be set. 0 = Auto-shutdown is disabled bit 5 PxARSEN: PWM Auto-Restart Enable bit 1 = PWM restarts automatically when the shutdown condition is removed. 0 = The PxASE bit must be cleared in firmware to restart PWM after the auto-shutdown condition is cleared. bit 4-1 Unimplemented: Read as ‘0’ bit 0 PxASDOV: PWM Auto-Shutdown Override bit PxASDEN = 1: 1 = Force PxASDL[n] levels on the PSMCx[n] pins without causing a PSMCxSIF interrupt 0 = Normal PWM and auto-shutdown execution PxASDEN = 0: No effect Note 1: PASE bit may be set in software. When this occurs the functionality is the same as that caused by hardware.  2013-2015 Microchip Technology Inc. DS40001675C-page 276 PIC16(L)F1788/9 REGISTER 26-17: PSMCxASDL: PSMC AUTO-SHUTDOWN OUTPUT LEVEL REGISTER U-0 U-0 — — R/W-0/0 PxASDLF (1) R/W-0/0 (1) PxASDLE R/W-0/0 (1) PxASDLD R/W-0/0 (1) PxASDLC R/W-0/0 R/W-0/0 PxASDLB PxASDLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PxASDLF: PSMCx Output F Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxF will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxF will drive logic ‘0’ bit 4 PxASDLE: PSMCx Output E Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxE will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxE will drive logic ‘0’ bit 3 PxASDLD: PSMCx Output D Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxD will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxD will drive logic ‘0’ bit 2 PxASDLC: PSMCx Output C Auto-Shutdown Pin Level bit(1) 1 = When auto-shutdown is asserted, pin PSMCxC will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxC will drive logic ‘0’ bit 1 PxASDLB: PSMCx Output B Auto-Shutdown Pin Level bit 1 = When auto-shutdown is asserted, pin PSMCxB will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxB will drive logic ‘0’ bit 0 PxASDLA: PSMCx Output A Auto-Shutdown Pin Level bit 1 = When auto-shutdown is asserted, pin PSMCxA will drive logic ‘1’ 0 = When auto-shutdown is asserted, pin PSMCxA will drive logic ‘0’ Note 1: These bits are not implemented on PSMC2. DS40001675C-page 277  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-18: PSMCxASDS: PSMC AUTO-SHUTDOWN SOURCE REGISTER R/W-0/0 U-0 U-0 PxASDSIN — — R/W-0/0 R/W-0/0 PxASDSC4 PxASDSC3 R/W-0/0 R/W-0/0 U-0 PxASDSC2 PxASDSC1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxASDSIN: Auto-shutdown occurs on PSMCxIN pin 1 = Auto-shutdown will occur when PSMCxIN pin goes true 0 = PSMCxIN pin will not cause auto-shutdown bit 6-5 Unimplemented: Read as ‘0’ bit 4 PxASDSC4: Auto-shutdown occurs on sync_C4OUT output 1 = Auto-shutdown will occur when sync_C4OUT output goes true 0 = sync_C4OUT will not cause auto-shutdown bit 3 PxASDSC3: Auto-shutdown occurs on sync_C3OUT output 1 = Auto-shutdown will occur when sync_C3OUT output goes true 0 = sync_C3OUT will not cause auto-shutdown bit 2 PxASDSC2: Auto-shutdown occurs on sync_C2OUT output 1 = Auto-shutdown will occur when sync_C2OUT output goes true 0 = sync_C2OUT will not cause auto-shutdown bit 1 PxASDSC1: Auto-shutdown occurs on sync_C1OUT output 1 = Auto-shutdown will occur when sync_C1OU output goes true 0 = sync_C1OU will not cause auto-shutdown bit 0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS40001675C-page 278 PIC16(L)F1788/9 REGISTER 26-19: PSMCxTMRL: PSMC TIME BASE COUNTER LOW REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxTMRL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxTMRL: 16-bit PSMCx Time Base Counter Least Significant bits = PSMCxTMR REGISTER 26-20: PSMCxTMRH: PSMC TIME BASE COUNTER HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 PSMCxTMRH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxTMRH: 16-bit PSMCx Time Base Counter Most Significant bits = PSMCxTMR DS40001675C-page 279  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-21: PSMCxPHL: PSMC PHASE COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPHL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPHL: 16-bit Phase Count Least Significant bits = PSMCxPH REGISTER 26-22: PSMCxPHH: PSMC PHASE COUNT HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPHH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPHH: 16-bit Phase Count Most Significant bits = PSMCxPH  2013-2015 Microchip Technology Inc. DS40001675C-page 280 PIC16(L)F1788/9 REGISTER 26-23: PSMCxDCL: PSMC DUTY CYCLE COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDCL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDCL: 16-bit Duty Cycle Count Least Significant bits = PSMCxDC REGISTER 26-24: PSMCxDCH: PSMC DUTY CYCLE COUNT HIGH REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDCH: 16-bit Duty Cycle Count Most Significant bits = PSMCxDC DS40001675C-page 281  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-25: PSMCxPRL: PSMC PERIOD COUNT LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPRL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPRL: 16-bit Period Time Least Significant bits = PSMCxPR REGISTER 26-26: PSMCxPRH: PSMC PERIOD COUNT HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxPRH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxPRH: 16-bit Period Time Most Significant bits = PSMCxPR  2013-2015 Microchip Technology Inc. DS40001675C-page 282 PIC16(L)F1788/9 REGISTER 26-27: PSMCxDBR: PSMC RISING EDGE DEAD-BAND TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDBR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDBR: Rising Edge Dead-Band Time bits = Unsigned number of PSMCx psmc_clk clock periods in rising edge dead band REGISTER 26-28: PSMCxDBF: PSMC FALLING EDGE DEAD-BAND TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxDBF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxDBF: Falling Edge Dead-Band Time bits = Unsigned number of PSMCx psmc_clk clock periods in falling edge dead band REGISTER 26-29: PSMCxFFA: PSMC FRACTIONAL FREQUENCY ADJUST REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxFFA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 PSMCxFFA: Fractional Frequency Adjustment bits = Unsigned number of fractional PSMCx psmc_clk clock periods to add to each period event time. The fractional time period = 1/(16*psmc_clk) DS40001675C-page 283  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-30: PSMCxBLKR: PSMC RISING EDGE BLANKING TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxBLKR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxBLKR: Rising Edge Blanking Time bits = Unsigned number of PSMCx psmc_clk clock periods in rising edge blanking REGISTER 26-31: PSMCxBLKF: PSMC FALLING EDGE BLANKING TIME REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PSMCxBLKF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PSMCxBLKF: Falling Edge Blanking Time bits = Unsigned number of PSMCx psmc_clk clock periods in falling edge blanking  2013-2015 Microchip Technology Inc. DS40001675C-page 284 PIC16(L)F1788/9 REGISTER 26-32: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0 U-0 U-0 — — R/W-0/0 PxSTRF (2) R/W-0/0 PxSTRE (2) R/W-0/0 (2) PxSTRD R/W-0/0 PxSTRC (2) R/W-0/0 R/W-1/1 PxSTRB PxSTRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 PxSTRF: PWM Steering PSMCxF Output Enable bit(2) If PxMODE = 0000 (Single-phase PWM): 1 = Single PWM output is active on pin PSMCxF 0 = Single PWM output is not active on pin PSMCxF. PWM drive is in inactive state If PxMODE = 0001 (Complementary Single-phase PWM): 1 = Complementary PWM output is active on pin PSMCxF 0 = Complementary PWM output is not active on pin PSMCxOUT5. PWM drive is in inactive state IF PxMODE = 1100 (3-phase Steering):(1) 1 = PSMCxD and PSMCxE are high. PSMCxA, PMSCxB, PSMCxC and PMSCxF are low. 0 = 3-phase output combination is not active bit 4 PxSTRE: PWM Steering PSMCxE Output Enable bit(2) If PxMODE = 000x (single-phase PWM or Complementary PWM): 1 = Single PWM output is active on pin PSMCxE 0 = Single PWM output is not active on pin PSMCxE. PWM drive is in inactive state IF PxMODE = 1100 (3-phase Steering):(1) 1 = PSMCxB and PSMCxE are high. PSMCxA, PMSCxC, PSMCxD and PMSCxF are low. 0 = 3-phase output combination is not active bit 3 PxSTRD: PWM Steering PSMCxD Output Enable bit(2) If PxMODE = 0000 (Single-phase PWM): 1 = Single PWM output is active on pin PSMCxD 0 = Single PWM output is not active on pin PSMCxD. PWM drive is in inactive state If PxMODE = 0001 (Complementary single-phase PWM): 1 = Complementary PWM output is active on pin PSMCxD 0 = Complementary PWM output is not active on pin PSMCxD. PWM drive is in inactive state IF PxMODE = 1100 (3-phase Steering):(1) 1 = PSMCxB and PSMCxC are high. PSMCxA, PMSCxD, PSMCxE and PMSCxF are low. 0 = 3-phase output combination is not active bit 2 PxSTRC: PWM Steering PSMCxC Output Enable bit(2) If PxMODE = 000x (Single-phase PWM or Complementary PWM): 1 = Single PWM output is active on pin PSMCxC 0 = Single PWM output is not active on pin PSMCxC. PWM drive is in inactive state IF PxMODE = 1100 (3-phase Steering):(1) 1 = PSMCxC and PSMCxF are high. PSMCxA, PMSCxB, PSMCxD and PMSCxE are low. 0 = 3-phase output combination is not active DS40001675C-page 285  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-32: PSMCxSTR0: PSMC STEERING CONTROL REGISTER 0 bit 1 PxSTRB: PWM Steering PSMCxB Output Enable bit If PxMODE = 0000 (Single-phase PWM): 1 = Single PWM output is active on pin PSMCxOUT1 0 = Single PWM output is not active on pin PSMCxOUT1. PWM drive is in inactive state If PxMODE = 0001 (Complementary Single-phase PWM): 1 = Complementary PWM output is active on pin PSMCxB 0 = Complementary PWM output is not active on pin PSMCxB. PWM drive is in inactive state IF PxMODE = 1100 (3-phase Steering):(1) 1 = PSMCxA and PSMCxF are high. PSMCxB, PMSCxC, PSMCxD and PMSCxE are low. 0 = 3-phase output combination is not active PxSTRA: PWM Steering PSMCxA Output Enable bit bit 0 If PxMODE = 000x (Single-phase PWM or Complementary PWM): 1 = Single PWM output is active on pin PSMCxA 0 = Single PWM output is not active on pin PSMCxA. PWM drive is in inactive state IF PxMODE = 1100 (3-phase Steering):(1) 1 = PSMCxA and PSMCxD are high. PSMCxB, PMSCxC, PSMCxE and PMSCxF are low. 0 = 3-phase output combination is not active Note 1: 2: In 3-phase Steering mode, only one PSTRx bit should be set at a time. If more than one is set, then the lowest bit number steering combination has precedence. These bits are not implemented on PSMC2.  2013-2015 Microchip Technology Inc. DS40001675C-page 286 PIC16(L)F1788/9 REGISTER 26-33: PSMCxSTR1: PSMC STEERING CONTROL REGISTER 1 R/W-0/0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 PxSSYNC — — — — — PxLSMEN PxHSMEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxSSYNC: PWM Steering Synchronization bit 1 = PWM outputs are updated on period boundary 0 = PWM outputs are updated immediately bit 6-2 Unimplemented: Read as ‘0’ bit 1 PxLSMEN: 3-Phase Steering Low Side Modulation Enable bit PxMODE = 1100: 1 = Low side driver PSMCxB, PSMCxD and PSMCxF outputs are modulated according to PSMCxMDL when the output is high and driven low without modulation when the output is low. 0 = PSMCxB, PSMCxD, and PSMCxF outputs are driven high and low by PSMCxSTR0 control without modulation. PxMODE 1100: No effect on output bit 0 PxHSMEN: 3-Phase Steering High Side Modulation Enable bit PxMODE = 1100: 1 = High side driver PSMCxA, PSMCxC and PSMCxE outputs are modulated according to PSMCxMDL when the output is high and driven low without modulation when the output is low. 0 = PSMCxA, PSMCxC and PSMCxE outputs are driven high and low by PSMCxSTR0 control without modulation. PxMODE 1100: No effect on output DS40001675C-page 287  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 26-34: PSMCxINT: PSMC TIME BASE INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PxTOVIE PxTPHIE PxTDCIE PxTPRIE PxTOVIF PxTPHIF PxTDCIF PxTPRIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxTOVIE: PSMC Time Base Counter Overflow Interrupt Enable bit 1 = Time base counter overflow interrupts are enabled 0 = Time base counter overflow interrupts are disabled bit 6 PxTPHIE: PSMC Time Base Phase Interrupt Enable bit 1 = Time base phase match interrupts are enabled 0 = Time base phase match interrupts are disabled bit 5 PxTDCIE: PSMC Time Base Duty Cycle Interrupt Enable bit 1 = Time base duty cycle match interrupts are enabled 0 = Time base duty cycle match interrupts are disabled bit 4 PxTPRIE: PSMC Time Base Period Interrupt Enable bit 1 = Time base period match interrupts are enabled 0 = Time base period match Interrupts are disabled bit 3 PxTOVIF: PSMC Time Base Counter Overflow Interrupt Flag bit 1 = The 16-bit PSMCxTMR has overflowed from FFFFh to 0000h 0 = The 16-bit PSMCxTMR counter has not overflowed bit 2 PxTPHIF: PSMC Time Base Phase Interrupt Flag bit 1 = The 16-bit PSMCxTMR counter has matched PSMCxPH 0 = The 16-bit PSMCxTMR counter has not matched PSMCxPH bit 1 PxTDCIF: PSMC Time Base Duty Cycle Interrupt Flag bit 1 = The 16-bit PSMCxTMR counter has matched PSMCxDC 0 = The 16-bit PSMCxTMR counter has not matched PSMCxDC bit 0 PxTPRIF: PSMC Time Base Period Interrupt Flag bit 1 = The 16-bit PSMCxTMR counter has matched PSMCxPR 0 = The 16-bit PSMCxTMR counter has not matched PSMCxPR  2013-2015 Microchip Technology Inc. DS40001675C-page 288 PIC16(L)F1788/9 TABLE 26-5: Name INTCON ODCONC SUMMARY OF REGISTERS ASSOCIATED WITH PSMC Bit7 Bit6 Bit5 Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 ODC7 ODC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 148 PIE4 PSMC4TIE PSMC3TIE PSMC2TIE PSMC1TIE PSMC4SIE PSMC3SIE PSMC2SIE PSMC1SIE 101 PIR4 PSMC4TIF PSMC3TIF PSMC2TIF PSMC1TIF PSMC4SIF PSMC3SIF PSMC2SIF PSMC1SIF 105 PSMCxASDC PxASE PxASDEN PxARSEN — — — PSMCxASDL — — PSMCxASDS PxASDSIN — PxASDLF(1) PxASDLE(1) PxASDLD(1) PxASDLC(1) — PxASDSC4 PxASDSC3 PxASDSC2 — PxASDOV 276 PxASDLB PxASDLA 277 PxASDSC1 — 278 PSMCxBLKF PSMCxBLKF 284 PSMCxBLKR PSMCxBLKR 284 PSMCxBLNK — — PSMCxCLK — — PSMCxCON PSMCxEN PSMCxLD PxFEBM1 PxFEBM0 PxCPRE PxDBFE — — — — PxDBRE PxREBM1 PxREBM0 PxCSRC PxMODE 271 270 265 PSMCxDBF PSMCxDBF 283 PSMCxDBR PSMCxDBR 283 PSMCxDCH PSMCxDC 281 PSMCxDCL PSMCxDC 281 PSMCxDCS PxDCSIN — — PxDCSC4 PxDCSC3 PxDCSC2 PxDCSC1 PxDCST 274 PSMCxFEBS PxFEBSIN — — PxFEBSC4 PxFEBSC3 PxFEBSC2 PxFEBSC1 — 272 — — — — PSMCxFFA PSMCxINT PxTOVIE PxTPHIE PxTDCIE PxTPRIE PSMCxMDL PxMDLEN PxMDLPOL PxMDLBIT — — PxOEF(1) PxOEE(1) PSMCxOEN — PSMCxFFA PxTOVIF PxTPHIF PxTDCIF 283 PxTPRIF PxMSRC PxOED(1) PxOEC(1) PxOEB 288 266 PxOEA 270 PSMCxPHH PSMCxPH 280 PSMCxPHL PSMCxPH 280 PSMCxPHS PxPHSIN PSMCxPOL — — — PxPHSC4 PxPHSC3 PxPHSC2 PxPHSC1 PxPHST 273 PxPOLIN PxPOLF(1) PxPOLE(1) PxPOLD(1) PxPOLC(1) PxPOLB PxPOLA 271 PSMCxPRH PSMCxPR 282 PSMCxPRL PSMCxPR 282 PxPRSIN — — PxPRSC4 PxPRSC3 PxPRSC2 PxPRSC1 PxPRST 275 PSMCxREBS PxREBSIN — — PxREBSC4 PxREBSC3 PxREBSC2 PxREBSC1 — 272 PSMCxSTR0 — — PxSTRF(1) PxSTRE(1) PxSTRD(1) PxSTRC(1) PxSTRB PxSTRA 285 PSMCxSTR1 PxSSYNC — — — — — PxLSMEN PxHSMEN 287 PSMCxSYNC PxPOFST PxPRPOL PxDCPOL — — PSMCxPRS PxSYNC 267 PSMCxTMRH PSMCxTMR 279 PSMCxTMRL PSMCxTMR 279 SLRCONC TRISC Legend: Note 1: SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLCR2 SRC1 SLRC0 148 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 147 — = unimplemented location, read as ‘0’. Shaded cells are not used by PSMC module. Unimplemented in PSMC2. DS40001675C-page 289  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 27.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: • • • • • Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 27-1 is a block diagram of the SPI interface module. FIGURE 27-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPBUF Reg SDI SSPSR Reg SDO bit 0 SS SS Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPM 4 SCK Edge Select TRIS bit  2013-2015 Microchip Technology Inc. ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPADD) DS40001675C-page 290 PIC16(L)F1788/9 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 27-2 is a block diagram of the I2C interface module in Master mode. Figure 27-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal data bus Read [SSPM] Write SSP1BUF Shift Clock SDA in Receive Enable (RCEN) SCL SCL in Bus Collision DS40001675C-page 291 LSb Start bit, Stop bit, Acknowledge Generate (SSPCON2) Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Clock Cntl SSPSR MSb (Hold off clock source) SDA Baud Rate Generator (SSPADD) Clock arbitrate/BCOL detect FIGURE 27-2: Set/Reset: S, P, SSPSTAT, WCOL, SSPOV Reset SEN, PEN (SSPCON2) Set SSP1IF, BCL1IF  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 27-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect  2013-2015 Microchip Technology Inc. Set, Reset S, P bits (SSPSTAT Reg) DS40001675C-page 292 PIC16(L)F1788/9 27.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) Figure 27-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 27-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Master sends useful data and slave sends dummy data. • Master sends useful data and slave sends useful data. • Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 27-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. DS40001675C-page 293  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 27-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 27.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: • • • • • • MSSP STATUS register (SSPSTAT) MSSP Control register 1 (SSPCON1) MSSP Control register 3 (SSPCON3) MSSP Data Buffer register (SSPBUF) MSSP Address register (SSPADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPCON1 and SSPSTAT are the control and STATUS registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower six bits of the SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write. In one SPI master mode, SSPADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 27.7 “Baud Rate Generator”. SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR register. SSPBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSP1IF interrupt is set. During transmission, the SSPBUF is not buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.  2013-2015 Microchip Technology Inc. DS40001675C-page 294 PIC16(L)F1788/9 27.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1 and SSPSTAT). These control bits allow the following to be specified: • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set FIGURE 27-5: Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPBUF register. Then, the Buffer Full Detect bit, BF of the SSPSTAT register, and the interrupt flag bit, SSP1IF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The Buffer Full bit, BF of the SSPSTAT register, indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. SPI MASTER/SLAVE CONNECTION SPI Master SSPM = 00xx = 1010 SPI Slave SSPM = 010x SDI SDO Serial Input Buffer (BUF) LSb SCK General I/O Processor 1 DS40001675C-page 295 SDO SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPBUF) Serial Clock Slave Select (optional) Shift Register (SSPSR) MSb LSb SCK SS Processor 2  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 27-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register and the CKE bit of the SSPSTAT register. This then, would give waveforms for SPI communication as shown in Figure 27-6, Figure 27-8 and Figure 27-9, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSPADD + 1)) Figure 27-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 27-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSP1IF SSPSR to SSPBUF  2013-2015 Microchip Technology Inc. DS40001675C-page 296 PIC16(L)F1788/9 27.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSP1IF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 27.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 27-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPCON3 register will enable writes to the SSPBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 27.2.5 SLAVE SELECT SYNCHRONIZATION The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1 = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1 = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. DS40001675C-page 297  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 27-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 27-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Shift register SSPSR and bit count are reset SSPBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSPSR to SSPBUF  2013-2015 Microchip Technology Inc. DS40001675C-page 298 PIC16(L)F1788/9 FIGURE 27-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSP1IF Interrupt Flag SSPSR to SSPBUF Write Collision detection active FIGURE 27-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSPSR to SSPBUF Write Collision detection active DS40001675C-page 299  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. TABLE 27-1: Name ANSELA APFCON1 In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 ANSA7 — C2OUTSEL CCP1SEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 137 SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 INTCON SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 294* SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 342 SSP1STAT SMP CKE D/A P S R/W UA BF 338 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 136 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 147 Legend: * Note 1: SSPM 340 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Page provides register information. PIC16(L)F1789 only.  2013-2015 Microchip Technology Inc. DS40001675C-page 300 PIC16(L)F1788/9 27.3 I2C MODE OVERVIEW The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 27-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 27-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: • Master Transmit mode (master is transmitting data to a slave) • Master Receive mode (master is receiving data from a slave) • Slave Transmit mode (slave is transmitting data to a master) • Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS40001675C-page 301 I2C MASTER/ SLAVE CONNECTION FIGURE 27-11: SCL VDD Master Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; • Single message where a master writes data to a slave. • Single message where a master reads data from a slave. • Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 27.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 27.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.  2013-2015 Microchip Technology Inc. DS40001675C-page 302 PIC16(L)F1788/9 27.4 I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 27.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 27.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 27.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 27.4.4 SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS40001675C-page 303 TABLE 27-2: TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.4.5 27.4.7 START CONDITION The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 27-10 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 27.4.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. 27.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 27-12: I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 27-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition  2013-2015 Microchip Technology Inc. DS40001675C-page 304 PIC16(L)F1788/9 27.4.9 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPSTAT register or the SSPOV bit of the SSPCON1 register are set when a byte is received. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit of the SSPCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. 27.5 I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of four modes selected in the SSPM bits of SSPCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operated the same as the other modes with SSP1IF additionally getting set upon detection of a Start, Restart, or Stop condition. 27.5.1 SLAVE MODE ADDRESSES The SSPADD register (Register 27-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 27-5) affects the address matching process. See Section 27.5.9 “SSP Mask Register” for more information. 27.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 27.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPADD. Even if there is not an address match; SSP1IF and UA are set, and SCL is held low until SSPADD is updated to receive a high byte again. When SSPADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001675C-page 305  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON1 register is set. The BOEN bit of the SSPCON3 register modifies this operation. For more information see Register 27-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSP1IF, must be cleared by software. When the SEN bit of the SSPCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPCON1 register, except sometimes in 10-bit mode. See Section 27.2.3 “SPI Master Mode” for more detail. 27.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 27-13 and Figure 27-14 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPSTAT is set; SSP1IF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears the SSP1IF bit. Software reads received address from SSPBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears SSP1IF. Software reads the received byte from SSPBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPSTAT, and the bus goes idle.  2013-2015 Microchip Technology Inc. 27.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 27-15 displays a module using both address and data holding. Figure 27-16 includes the operation with the SEN bit of the SSPCON2 register set. 1. S bit of SSPSTAT is set; SSP1IF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSP1IF is set and CKP cleared after the 8th falling edge of SCL. 3. Slave clears the SSP1IF. 4. Slave can look at the ACKTIM bit of the SSPCON3 register to determine if the SSP1IF was after or before the ACK. 5. Slave reads the address value from SSPBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSP1IF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSP1IF. Note: SSP1IF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSP1IF not set 11. SSP1IF set and CKP cleared after 8th falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. DS40001675C-page 306 DS40001675C-page 307 SSPOV BF SSP1IF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master 8 D0 9 P SSP1IF set on 9th falling edge of SCL ACK = 1 FIGURE 27-14: SCL SDA Receiving Address Bus Master sends Stop condition PIC16(L)F1788/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. CKP SSPOV BF SSP1IF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPBUF 6 D2 7 D1 SSPOV set because SSPBUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to ‘1’ in software, releasing SCL 1 D7 Receive Data 8 D0 9 ACK SCL is not held low because ACK= 1 SSP1IF set on 9th falling edge of SCL P FIGURE 27-15: SDA Receive Address Bus Master sends Stop condition PIC16(L)F1788/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001675C-page 308 DS40001675C-page 309 P S ACKTIM CKP ACKDT BF SSP1IF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSP1IF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSP1IF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition FIGURE 27-16: SCL SDA Master Releases SDA to slave for ACK sequence PIC16(L)F1788/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. P S ACKTIM CKP ACKDT BF SSP1IF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSPBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSPBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 27-17: SCL SDA R/W = 0 Master releases SDA to slave for ACK sequence PIC16(L)F1788/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) DS40001675C-page 310 PIC16(L)F1788/9 27.5.3 SLAVE TRANSMISSION 27.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 27-17 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 27.5.6 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSP1IF bit must be cleared by software and the SSPSTAT register is used to determine the status of the byte. The SSP1IF bit is set on the falling edge of the ninth clock pulse. 27.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPCON3 register is set, the BCL1IF bit of the PIR register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCL1IF bit to handle a slave bus collision. DS40001675C-page 311 Master sends a Start condition on SDA and SCL. 2. S bit of SSPSTAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSP1IF bit. 4. Slave hardware generates an ACK and sets SSP1IF. 5. SSP1IF bit is cleared by user. 6. Software reads the received address from SSPBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSP1IF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSP1IF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSP1IF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed.  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. P S D/A R/W ACKSTAT CKP BF SSP1IF S Receiving Address 1 2 5 6 7 Received address is read from SSPBUF 4 Indicates an address has been received R/W is copied from the matching address byte When R/W is set SCL is always held low after 9th SCL falling edge 3 A7 A6 A5 A4 A3 A2 A1 8 9 R/W = 1 Automatic ACK Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P FIGURE 27-18: SCL SDA Master sends Stop condition PIC16(L)F1788/9 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) DS40001675C-page 312 PIC16(L)F1788/9 27.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure 27-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPSTAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSP1IF interrupt is generated. 4. Slave software clears SSP1IF. 5. Slave software reads ACKTIM bit of SSPCON3 register, and R/W and D/A of the SSPSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSP1IF after the ACK if the R/W bit is set. 11. Slave software clears SSP1IF. 12. Slave loads value to transmit to the master into SSPBUF setting the BF bit. Note: SSPBUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001675C-page 313  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSP1IF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSPBUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCL Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master’s ACK response is copied to SSPSTAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 27-19: SCL SDA Master releases SDA to slave for ACK sequence PIC16(L)F1788/9 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) DS40001675C-page 314 PIC16(L)F1788/9 27.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 27-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPSTAT is set; SSP1IF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPSTAT register is set. Slave sends ACK and SSP1IF is set. Software clears the SSP1IF bit. Software reads received address from SSPBUF clearing the BF flag. Slave loads low address into SSPADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. 27.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 27-20 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 27-21 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSP1IF is set. Note: If the low address does not match, SSP1IF and UA are still set so that the slave software can set SSPADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSP1IF. 11. Slave reads the received matching address from SSPBUF clearing BF. 12. Slave loads high address into SSPADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSP1IF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSP1IF. 16. Slave reads the received byte from SSPBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001675C-page 315  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. CKP UA BF SSP1IF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low If address matches SSPADD it is loaded into SSPBUF 3 1 Receive First Address Byte 9 ACK 1 3 4 5 6 7 8 Software updates SSPADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSPBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 27-20: SCL SDA Master sends Stop condition PIC16(L)F1788/9 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001675C-page 316 DS40001675C-page 317 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPADD is not allowed until 9th falling edge of SCL SSPBUF can be read anytime before the next received byte Cleared by software 1 A7 Receive Second Address Byte 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSPADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSPBUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 27-21: SSP1IF 1 SCL S 1 SDA Receive First Address Byte PIC16(L)F1788/9 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. D/A R/W ACKSTAT CKP UA BF SSP1IF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPADD must be updated SSPBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSPADD Received address is read from SSPBUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSPBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 27-22: SDA Master sends Restart event PIC16(L)F1788/9 I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) DS40001675C-page 318 PIC16(L)F1788/9 27.5.6 27.5.6.2 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSPCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 27.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPBUF with data to transfer to the master. If the SEN bit of SSPCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPBUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. FIGURE 27-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 27.5.6.3 Byte NACKing When AHEN bit of SSPCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCL for a received matching address byte. When DHEN bit of SSPCON3 is set; CKP is cleared after the 8th falling edge of SCL for received data. Stretching after the 8th falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 27.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 27-22). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPCON1 DS40001675C-page 319  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit of the SSPCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPBUF and respond. Figure 27-23 shows a general call reception sequence. FIGURE 27-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSP1IF BF (SSPSTAT) Cleared by software GCEN (SSPCON2) SSPBUF is read ’1’ 27.5.9 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register 27-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A. • 10-bit Address mode: address compare of A only. The SSP mask has no effect during the reception of the first (high) byte of the address.  2013-2015 Microchip Technology Inc. DS40001675C-page 320 PIC16(L)F1788/9 27.6 I2C Master Mode 27.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSP1IF, to be set (SSP interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 27.7 “Baud Rate Generator” for more detail. Note 1: Master mode suspends Start/Stop detection when sending the Start/Stop condition by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware clears the control bit. DS40001675C-page 321  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 27-25). FIGURE 27-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 27.6.3 WCOL STATUS FLAG If the user writes the SSPBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPCON2 is disabled until the Start condition is complete.  2013-2015 Microchip Technology Inc. DS40001675C-page 322 PIC16(L)F1788/9 27.6.4 I2C MASTER MODE START CONDITION TIMING Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCL1IF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. FIGURE 27-26: 2: The Philips I2C specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPSTAT) At completion of Start bit, hardware clears SEN bit and sets SSP1IF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPBUF occurs here SDA 2nd bit 1st bit TBRG SCL S DS40001675C-page 323 TBRG  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.6.5 I2C MASTER MODE REPEATED CON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPSTAT register will be set. The SSP1IF bit will not be set until the Baud Rate Generator has timed out. START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit of the SSPCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSP- FIGURE 27-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSP1IF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPBUF occurs here TBRG SCL Sr TBRG Repeated Start  2013-2015 Microchip Technology Inc. DS40001675C-page 324 PIC16(L)F1788/9 27.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSP1IF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 27-27). After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSP1IF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 27.6.6.1 BF Status Flag 27.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 27.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. The user loads the SSPBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all eight bits are shifted out. 27.6.6.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS40001675C-page 325  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. S R/W PEN SEN BF (SSPSTAT) SSP1IF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSP1IF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address From slave, clear ACKSTAT bit SSPCON2 P Cleared by software 9 ACK ACKSTAT in SSPCON2 = 1 FIGURE 27-28: SEN = 0 Write SSPCON2 SEN = 1 Start condition begins PIC16(L)F1788/9 I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS40001675C-page 326 PIC16(L)F1788/9 27.6.7 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSPCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSP1IF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPCON2 register. 27.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 27.6.7.2 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 27.6.7.3 27.6.7.4 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS40001675C-page 327 12. 13. 14. 15. Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. User writes SSPBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. User sets the RCEN bit of the SSPCON2 register and the master clocks in a byte from the slave. After the 8th falling edge of SCL, SSP1IF and BF are set. User clears the SSP1IF bit and reads the received byte from SSPUF, which clears the BF flag. The user either clears the SSPCON2 register’s ACKDT bit to receive another byte or sets the ADKDT bit to suppress further data and then initiates the acknowledge sequence by setting the ACKEN bit. Master’s ACK or ACK is clocked out to the slave and SSP1IF is set. User clears SSP1IF. Steps 8-13 are repeated for each received byte from the slave. If the ACKST bit was set in step 11 then the user can send a STOP to release the bus.  2013-2015 Microchip Technology Inc.  2013-2015 Microchip Technology Inc. RCEN ACKEN SSPOV BF (SSPSTAT) SDA = 0, SCL = 1 while CPU responds to SSP1IF SSP1IF S 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK 2 3 5 6 7 8 D0 9 ACK 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSP1IF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSP1IF at end of receive 9 ACK is not sent ACK P Set SSP1IF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPSTAT) and SSP1IF PEN bit = 1 written here SSPOV is set because SSPBUF is still full 8 D0 RCEN cleared automatically D7 D6 D5 D4 D3 D2 D1 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 Receiving Data from Slave RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 Last bit is shifted into SSPSR and contents are unloaded into SSPBUF Cleared by software Set SSP1IF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN cleared automatically Master configured as a receiver by programming SSPCON2 (RCEN = 1) A1 R/W ACK from Slave Master configured as a receiver by programming SSPCON2 (RCEN = 1) FIGURE 27-29: SCL SDA SEN = 0 Write to SSPBUF occurs here, start XMIT Write to SSPCON2 (SEN = 1), begin Start condition Write to SSPCON2 to start Acknowledge sequence SDA = ACKDT (SSPCON2) = 0 PIC16(L)F1788/9 I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS40001675C-page 328 PIC16(L)F1788/9 27.6.8 ACKNOWLEDGE SEQUENCE TIMING 27.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPSTAT register is set. A TBRG later, the PEN bit is cleared and the SSP1IF bit is set (Figure 27-30). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 27-29). 27.6.8.1 27.6.9.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 27-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA SCL D0 ACK 8 9 SSP1IF SSP1IF set at the end of receive Cleared in software Cleared in software SSP1IF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. DS40001675C-page 329  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 27-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2) is cleared by hardware and the SSP1IF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 27.6.10 SLEEP OPERATION 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 27.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 27.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCL1IF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition 27.6.13 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF and reset the I2C port to its Idle state (Figure 27-31). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSP1IF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is Idle and the S and P bits are cleared.  2013-2015 Microchip Technology Inc. DS40001675C-page 330 PIC16(L)F1788/9 FIGURE 27-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF DS40001675C-page 331  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 27-32). SCL is sampled low before SDA is asserted low (Figure 27-33). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 27-34). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCL1IF flag is set and • the MSSP module is reset to its Idle state (Figure 27-32). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 27-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSP1IF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCL1IF SDA sampled low before Start condition. Set BCL1IF. S bit and SSP1IF set because SDA = 0, SCL = 1. SSP1IF and BCL1IF are cleared by software S SSP1IF SSP1IF and BCL1IF are cleared by software  2013-2015 Microchip Technology Inc. DS40001675C-page 332 PIC16(L)F1788/9 FIGURE 27-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software ’0’ ’0’ SSP1IF ’0’ ’0’ S FIGURE 27-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA SCL TBRG SDA pulled low by other master. Reset BRG and assert SDA. S SCL pulled low after BRG time-out SEN BCL1IF Set SSP1IF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSP1IF SDA = 0, SCL = 1, set SSP1IF DS40001675C-page 333 Interrupts cleared by software  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 27-35). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 27-36. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 27-36: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL1IF Cleared by software S ’0’ SSP1IF ’0’ FIGURE 27-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCL1IF SCL goes low before SDA, set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN S ’0’ SSP1IF  2013-2015 Microchip Technology Inc. DS40001675C-page 334 PIC16(L)F1788/9 27.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 27-37). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 27-38). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. FIGURE 27-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCL1IF SDA asserted low SCL PEN BCL1IF P ’0’ SSP1IF ’0’ FIGURE 27-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCL1IF PEN BCL1IF P ’0’ SSP1IF ’0’ DS40001675C-page 335  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 27-3: Name APFCON1 SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIE2 OSFIE C2IE C1IE EEIE BCL1IE C4IE C3IE CCP2IE 99 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 PIR2 OSFIF C2IF C1IF EEIF BCL1IF C4IF C3IF CCP2IF 103 INTCON C2OUTSEL CCP1SEL Bit 5 SSP1ADD ADD SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 343 294* SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 341 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 340 SMP CKE D/A P S R/W UA BF 338 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISA0 147 SSP1MSK SSP1STAT TRISC Legend: * Note 1: SSPM 340 343 MSK — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode. Page provides register information. PIC16(L)F1789 only.  2013-2015 Microchip Technology Inc. DS40001675C-page 336 PIC16(L)F1788/9 27.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Register 27-6). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 27-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. EQUATION 27-1: Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1   4  An internal signal “Reload” in Figure 27-39 triggers the value from SSPADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module FIGURE 27-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM SSPM Reload SSPADD Reload Control SCL SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 27-4: Note 1: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical and timing specifications in Table 31-9 and Figure 31-7 to ensure the system is designed to support the I/O timing requirements. DS40001675C-page 337  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 27.8 Register Definitions: MSSP Control REGISTER 27-1: SSPSTAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 bit 4 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated  2013-2015 Microchip Technology Inc. DS40001675C-page 338 PIC16(L)F1788/9 REGISTER 27-1: bit 0 SSPSTAT: SSP STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS40001675C-page 339  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 27-2: SSPCON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDA and SCL pins must be configured as inputs. SSPADD values of 0, 1 or 2 are not supported for I2C mode. SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead.  2013-2015 Microchip Technology Inc. DS40001675C-page 340 PIC16(L)F1788/9 REGISTER 27-3: SSPCON2: SSP CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS40001675C-page 341  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 27-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the SSPCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSPCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.  2013-2015 Microchip Technology Inc. DS40001675C-page 342 PIC16(L)F1788/9 REGISTER 27-5: R/W-1/1 SSPMSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM = 0111 or 1111): 1 = The received address bit 0 is compared to SSPADD to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 27-6: R/W-0/0 SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD: Baud Rate Clock Divider bits SCL pin clock period = ((ADD + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address Byte: bit 7-0 ADD: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS40001675C-page 343  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) • • • • • • • • • • Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes • Sleep operation The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 28-1: The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 28-1 and Figure 28-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXIF TXREG Register 8 MSb TX/CK pin LSb (8) • • • 0 Pin Buffer and Control TRMT SPEN Transmit Shift Register (TSR) TXEN Baud Rate Generator FOSC ÷n +1 SPBRGH TX9 n BRG16 SPBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0  2013-2015 Microchip Technology Inc. TX9D DS40001675C-page 344 PIC16(L)F1788/9 FIGURE 28-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 +1 SPBRGH SPBRGL RSR Register MSb Pin Buffer and Control Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register 28-1, Register 28-2 and Register 28-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS40001675C-page 345  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 28-5 for examples of baud rate configurations. 28.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG. 28.1.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 28.5.1.2 “Clock Polarity”. 28.1.1 28.1.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 28-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register. 28.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG. The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set.  2013-2015 Microchip Technology Inc. DS40001675C-page 346 PIC16(L)F1788/9 28.1.1.5 TSR Status 28.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 28.1.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 28.1.2.7 “Address Detection” for more information on the address mode. FIGURE 28-3: Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) DS40001675C-page 347 4. 5. 6. 7. 8. Asynchronous Transmission Set-up: Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 28.4 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 28-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG TX/CK pin Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Transmit Buffer Reg. Empty Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Word 1 BRG Output (Shift Clock) Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 28-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON1 C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 356 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 355 Name INTCON RCSTA SPBRGL BRG 357 SPBRGH BRG 357 TRISC TXREG TXSTA Legend: * TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 EUSART Transmit Data Register CSRC TX9 TXEN 147 346* SYNC SENDB BRGH TRMT TX9D 354 — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission. Page provides register information.  2013-2015 Microchip Technology Inc. DS40001675C-page 348 PIC16(L)F1788/9 28.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 28-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 28.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 28.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 28.1.2.4 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: 28.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 28.1.2.5 “Receive Overrun Error” for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE, Interrupt Enable bit of the PIE1 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001675C-page 349  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 28.1.2.5 28.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 28.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG.  2013-2015 Microchip Technology Inc. DS40001675C-page 350 PIC16(L)F1788/9 28.1.2.8 Asynchronous Reception Set-up: 28.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 28.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 28-5: Rcv Shift Reg Rcv Buffer Reg. RCIDL This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 28.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Set-up bit 1 bit 7/8 Stop bit Start bit Word 1 RCREG bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS40001675C-page 351  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 28-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON1 C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 356 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF Name INTCON RCREG RCSTA EUSART Receive Data Register SPEN RX9 SREN SPBRGL TXSTA Legend: * ADDEN FERR OERR RX9D BRG SPBRGH TRISC CREN 102 349* 355 357 BRG 357 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 147 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 354 — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception. Page provides register information.  2013-2015 Microchip Technology Inc. DS40001675C-page 352 PIC16(L)F1788/9 28.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 6.2.2 “Internal Clock Sources” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 28.4.1 “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. DS40001675C-page 353  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.3 Register Definitions: EUSART Control REGISTER 28-1: R/W-/0 TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 CSRC TX9 R/W-0/0 TXEN (1) R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2013-2015 Microchip Technology Inc. DS40001675C-page 354 PIC16(L)F1788/9 REGISTER 28-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001675C-page 355  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 REGISTER 28-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2013-2015 Microchip Technology Inc. DS40001675C-page 356 PIC16(L)F1788/9 28.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 28-3 contains the formulas for determining the baud rate. Example 28-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 28-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. EXAMPLE 28-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -----------------------------------------------------------------------64  [SPBRGH:SPBRGL] + 1  Solving for SPBRGH:SPBRGL: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- – 1 64 16000000 -----------------------9600 = ------------------------ – 1 64 =  25.042  = 25 16000000 Calculated Baud Rate = --------------------------64  25 + 1  = 9615 Calc. Baud Rate – Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate  9615 – 9600  = ---------------------------------- = 0.16% 9600 Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. DS40001675C-page 357  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 28-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGH, SPBRGL register pair TABLE 28-4: Name BAUDCON RCSTA FOSC/[16 (n+1)] SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 356 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 355 SPBRGL BRG 357 SPBRGH BRG 357 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 354 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information.  2013-2015 Microchip Technology Inc. DS40001675C-page 358 PIC16(L)F1788/9 TABLE 28-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 DS40001675C-page 359  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 28-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate FOSC = 20.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — —  2013-2015 Microchip Technology Inc. DS40001675C-page 360 PIC16(L)F1788/9 TABLE 28-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 143 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 832 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS40001675C-page 361  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 28.4.3 “Auto-Wake-up on Break”). In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence (Figure 28-6). While the ABD sequence takes place, the EUSART state machine is held in idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 28-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRGL register did not overflow by checking for 00h in the SPBRGH register. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRGL register pair. TABLE 28-6: The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 28-6. During ABD, both the SPBRGH and SPBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH FIGURE 28-6: BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 1 FOSC/4 FOSC/32 Note: During the ABD sequence, SPBRGL and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value BRG COUNTER CLOCK RATES 0000h RX pin 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2013-2015 Microchip Technology Inc. DS40001675C-page 362 PIC16(L)F1788/9 28.4.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. The overflow condition will set the RCIF flag. The counter continues to count until the fifth rising edge is detected on the RX pin. The RCIDL bit will remain false ('0') until the fifth rising edge, at which time the RCIDL bit will be set. If the RCREG is read after the overflow occurs but before the fifth rising edge, then the fifth rising edge will set the RCIF again. Terminating the auto-baud process early to clear an overflow condition will prevent proper detection of the sync character fifth rising edge. If any falling edges of the sync character have not yet occurred when the ABDEN bit is cleared then those will be falsely detected as Start bits. The following steps are recommended to clear the overflow condition: 1. 2. 3. Read RCREG to clear RCIF. If RCIDL is zero, then wait for RCIF and repeat step 1. Clear the ABDOVF bit. 28.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) 28.4.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 28-7), and asynchronously if the device is in Sleep mode (Figure 28-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001675C-page 363  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 28-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in idle while the WUE bit is set. FIGURE 28-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in idle while the WUE bit is set.  2013-2015 Microchip Technology Inc. DS40001675C-page 364 PIC16(L)F1788/9 28.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 28-9 for the timing of the Break character sequence. 28.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 28.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; • RCIF bit is set • FERR bit is set • RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 28.4.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 28-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) DS40001675C-page 365 SENDB Sampled Here Auto Cleared  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 28.5.1 SYNCHRONOUS MASTER MODE Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 28.5.1.3 Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 28.5.1.4 Synchronous Master Transmission Set-up: The following bits are used to configure the EUSART for synchronous master operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 28.5.1.1 28.5.1.2 1. 2. 3. 4. 5. 6. Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. Synchronous Master Transmission 7. 8. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 28.4 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register. Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock.  2013-2015 Microchip Technology Inc. DS40001675C-page 366 PIC16(L)F1788/9 FIGURE 28-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 28-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 2 bit 1 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 28-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON1 C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 356 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 355 Name INTCON RCSTA SPBRGL BRG 357 SPBRGH BRG 357 TRISC TRISC7 TRISC6 TXREG TXSTA Legend: * TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB 147 346* BRGH TRMT TX9D 354 — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission. Page provides register information. DS40001675C-page 367  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: 28.5.1.6 If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: 28.5.1.7 If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. 28.5.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. 28.5.1.9 Synchronous Master Reception Set-up: 1. Initialize the SPBRGH, SPBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters  2013-2015 Microchip Technology Inc. DS40001675C-page 368 PIC16(L)F1788/9 FIGURE 28-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 28-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APFCON1 C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 356 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 SPEN RX9 SREN OERR RX9D INTCON RCREG RCSTA EUSART Receive Data Register CREN ADDEN 349* FERR 355 SPBRGL BRG 357 SPBRGH BRG 357 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 147 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 354 Legend: * — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception. Page provides register information. DS40001675C-page 369  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 28.5.2.1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 5. 28.5.2.2 1. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave Section 28.5.1.3 modes are identical (see “Synchronous Master Transmission”), except in the case of the Sleep mode. 2. 3. 4. 5. 6. 7. 8. TABLE 28-9: The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXREG register. SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON1 C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 356 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 355 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 Name INTCON TXREG TXSTA Legend: * EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB 147 346* BRGH TRMT TX9D 354 — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Page provides register information.  2013-2015 Microchip Technology Inc. DS40001675C-page 370 PIC16(L)F1788/9 28.5.2.3 EUSART Synchronous Slave Reception 28.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 28.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 28-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page APFCON1 C2OUTSEL CC1PSEL SDOSEL SCKSEL SDISEL TXSEL RXSEL CCP2SEL 132 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 356 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 97 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 98 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 102 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 355 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 147 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 354 Name INTCON RCREG Legend: * EUSART Receive Data Register 349* — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception. Page provides register information. DS40001675C-page 371  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 28.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 28.6.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: • RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 28.5.2.4 “Synchronous Slave Reception Set-up:”). • If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. • The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.  2013-2015 Microchip Technology Inc. 28.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • RCSTA and TXSTA Control registers must be configured for synchronous slave transmission (see Section 28.5.2.2 “Synchronous Slave Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. • If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. • Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. 28.6.3 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 13.1 “Alternate Pin Function” for more information. DS40001675C-page 372 PIC16(L)F1788/9 29.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16(L)F178X Memory Programming Specification” (DS41457). 29.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 29.2 Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 29.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6 connector) configuration. See Figure 29-1. FIGURE 29-1: VDD ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 29-2. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 29-3 for more information. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 5.5 “MCLR” for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode.  2013-2015 Microchip Technology Inc. DS40001675C-page 373 PIC16(L)F1788/9 FIGURE 29-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 29-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins. TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). DS40001675C-page 374  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 30.0 INSTRUCTION SET SUMMARY Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. • Byte Oriented • Bit Oriented • Literal and Control • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. The literal and control category contains the most varied instruction word format. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. Table 30-3 lists the instructions recognized by the MPASMTM assembler. 30.1 All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) TABLE 30-1: Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. OPCODE FIELD DESCRIPTIONS Field Description f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 30-2: ABBREVIATION DESCRIPTIONS Field Description PC Program Counter TO Time-Out bit C Carry bit DC Digit Carry bit Z Zero bit PD Power-Down bit  2013-2015 Microchip Technology Inc. DS40001675C-page 375 PIC16(L)F1788/9 FIGURE 30-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS40001675C-page 376  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 30-3: ENHANCED MID-RANGE INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb Status Notes Affected LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d DECFSZ INCFSZ f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS Decrement f, Skip if 0 Increment f, Skip if 0 1(2) 1(2) 00 00 1011 dfff ffff 1111 dfff ffff 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS f, b f, b BCF BSF Bit Clear f Bit Set f 1 1 00bb bfff ffff 01bb bfff ffff 2 2 01 01 10bb bfff ffff 11bb bfff ffff 1, 2 1, 2 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 01 01 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW Note 1: 2: k k k k k k k k Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W 1 1 1 1 1 1 1 1 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk C, DC, Z kkkk Z kkkk Z kkkk kkkk kkkk kkkk C, DC, Z kkkk Z If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.  2013-2015 Microchip Technology Inc. DS40001675C-page 377 PIC16(L)F1788/9 TABLE 30-4: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb Status Notes Affected LSb CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff INHERENT OPERATIONS CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W 1 1 1 1 1 1 TO, PD TO, PD C-COMPILER OPTIMIZED ADDFSR n, k MOVIW n mm k[n] n mm MOVWI k[n] Note 1: 2: 3: 30.2 Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 1 1 11 00 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm kkkk 1111 0nkk 1nmm 0000 0001 kkkk 1 11 1111 1nkk Z 2, 3 Z 2 2, 3 2 If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Table in the MOVIW and MOVWI instruction descriptions. Instruction Descriptions ADDLW ADDFSR Add Literal to FSRn Syntax: Add literal and W [ label ] ADDLW k Syntax: [ label ] ADDFSR FSRn, k Operands: 0  k  255 Operands: -32  k  31 n Î [ 0, 1] Operation: (W) + k  (W) Status Affected: C, DC, Z Operation: FSR(n) + k  FSR(n) Description: Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. DS40001675C-page 378  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 ANDWF ADDWF Syntax: Add W and f [ label ] ADDWF AND W with f Syntax: f,d [ label ] ANDWF f,d Operands: Operands: 0  f  127 d  0  f  127 d  Operation: (W) .AND. (f)  (destination) Operation: (W) + (f)  (destination) Status Affected: Z Status Affected: C, DC, Z Description: Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. AND the W register with register ‘f’. If ‘d’ is ‘’, the result is stored in the W register. If ‘d’ is ‘’, the result is stored back in register ‘f’. ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0  f  127 d  Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. f {,d} ASRF Arithmetic Right Shift Syntax: [ label ] ASRF Operands: 0  f  127 d  f {,d} Operation: (f) dest (f)  dest, (f)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0  k  255 Operation: (W) .AND. (k)  (W) Status Affected: Description: BCF Syntax:  Bit Clear f [ label ] BCF f,b Operands: 0  f  127 0b7 Z Operation: 0  (f) The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.  2013-2015 Microchip Technology Inc. DS40001675C-page 379 PIC16(L)F1788/9 BRA Relative Branch BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSC f,b Operands: Operands: -256  label - PC + 1  255 -256  k  255 0  f  127 0b7 (PC) + 1 + k  PC Operation: skip if (f) = 0 Operation: Status Affected: None Status Affected: None Description: Description: Add the signed 9-bit literal ‘k’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a 2-cycle instruction. This branch has a limited range. If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a 2-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0  f  127 0b7 f,b Operation: 1  (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. DS40001675C-page 380 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0  f  127 0b VDD) ................................................................................................... ±20 mA Total power dissipation(2) .............................................................................................................................. 800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Section 31.4 “Thermal Considerations” to calculate device specifications. Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} +  (VOL x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2013-2015 Microchip Technology Inc. DS40001675C-page 389 PIC16(L)F1788/9 31.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF1788/9 VDDMIN (Fosc  16 MHz).......................................................................................................... +1.8V VDDMIN (16 MHz < Fosc  32 MHz) ......................................................................................... +2.7V VDDMAX .................................................................................................................................... +3.6V PIC16F1788/9 VDDMIN (Fosc  16 MHz).......................................................................................................... +2.3V VDDMIN (16 MHz < Fosc  32 MHz) ......................................................................................... +2.7V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................... +85°C Extended Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................. +125°C Note 1: See Parameter D001, DC Characteristics: Supply Voltage. DS40001675C-page 390  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 PIC16F1788/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C FIGURE 31-1: VDD (V) 5.5 2.5 2.3 0 10 4 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 31-6 for each Oscillator mode’s supported frequencies. PIC16LF1788/9 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C VDD (V) FIGURE 31-2: 3.6 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 31-6 for each Oscillator mode’s supported frequencies.  2013-2015 Microchip Technology Inc. DS40001675C-page 391 PIC16(L)F1788/9 31.3 DC Characteristics TABLE 31-1: SUPPLY VOLTAGE PIC16LF1788/9 Standard Operating Conditions (unless otherwise stated) PIC16F1788/9 Param . No. D001 Sym. VDD Characteristic VDR VPOR* Power-on Reset Release Voltage VPORR* Power-on Reset Rearm Voltage VFVR D004* SVDD Max. Units Conditions 1.8 2.5 — — 3.6 3.6 V V FOSC  16 MHz: FOSC  32 MHz (Note 2) 2.3 2.5 — — 5.5 5.5 V V FOSC  16 MHz: FOSC  32 MHz (Note 2) 1.5 — — V Device in Sleep mode 1.7 — — V Device in Sleep mode — 1.6 — V — 0.8 — V Device in Sleep mode — 1.5 — V Device in Sleep mode -4 — 4 % 1.024V, VDD  2.5V -4 — 4 % 2.048V, VDD  2.5V 4.096V, VDD  4.75V RAM Data Retention Voltage(1) D002* D003 Typ† Supply Voltage (VDDMIN, VDDMAX) D001 D002* Min. Fixed Voltage Reference Voltage(3) VDD Rise Rate to ensure internal Power-on Reset signal -5 — 5 % 0.05 — — V/ms See Section 5.1 “Power-On Reset (POR)” for details. * † These parameters are characterized but not tested. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. 3: Industrial temperature range only. DS40001675C-page 392  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 31-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) Note 1: 2: 3: TPOR(2) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.  2013-2015 Microchip Technology Inc. DS40001675C-page 393 PIC16(L)F1788/9 TABLE 31-2: SUPPLY VOLTAGE (IDD)(1,2) PIC16LF1788/9 Standard Operating Conditions (unless otherwise stated) PIC16F1788/9 Param No. Device Characteristics LDO Regulator D009 D010 D010 D012 D012 Note 1: 2: 3: 4: 5: 6: Conditions Min. Typ† Max. Units Note VDD — 75 — A — High Power mode, normal operation — 15 — A — Sleep VREGCON = 0 — 0.3 — A — Sleep VREGCON = 1 FOSC = 32 kHz LP Oscillator mode (Note 4), -40°C  TA  +85°C — 8 20 A 1.8 — 12 24 A 3.0 — 18 63 A 2.3 — 20 74 A 3.0 — 22 79 A 5.0 — 160 650 A 1.8 — 320 1000 A 3.0 — 260 700 A 2.3 — 330 1100 A 3.0 — 380 1300 A 5.0 FOSC = 32 kHz LP Oscillator mode (Note 4, 5), -40°C  TA  +85°C FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode (Note 5) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k FVR and BOR are disabled. 0.1 F capacitor on VCAP. 8 MHz crystal oscillator with 4x PLL enabled. DS40001675C-page 394  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 31-2: SUPPLY VOLTAGE (IDD)(1,2) (CONTINUED) PIC16LF1788/9 Standard Operating Conditions (unless otherwise stated) PIC16F1788/9 Param No. D014 D014 D015 D015 D017 D017 D019 D019 D020 D020 D022 D022 Note 1: 2: 3: 4: 5: 6: Device Characteristics Conditions Min. Typ† Max. Units VDD — 125 550 A 1.8 — 280 1100 A 3.0 — 220 650 A 2.3 — 290 1000 A 3.0 — 350 1200 A 5.0 — 2.1 6.2 mA 3.0 — 2.5 7.5 mA 3.6 — 2.1 6.5 mA 3.0 — 2.2 7.5 mA 5.0 — 130 180 A 1.8 — 150 250 A 3.0 — 150 250 A 2.3 — 170 330 A 3.0 — 220 430 A 5.0 — 0.8 2.2 mA 1.8 — 1.2 3.7 mA 3.0 — 1.0 2.3 mA 2.3 — 1.3 3.9 mA 3.0 — 1.4 4.1 mA 5.0 — 2.1 6.2 mA 3.0 — 2.5 7.5 mA 3.6 — 2.1 6.5 mA 3.0 — 2.2 7.5 mA 5.0 — 2.1 6.2 mA 3.0 — 2.5 7.5 mA 3.6 — 2.1 6.5 mA 3.0 — 2.2 7.5 mA 5.0 Note FOSC = 4 MHz EC Oscillator mode Medium-Power mode FOSC = 4 MHz EC Oscillator mode (Note 5) Medium-Power mode FOSC = 32 MHz EC Oscillator High-Power mode FOSC = 32 MHz EC Oscillator High-Power mode (Note 5) FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode (Note 5) FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode (Note 5) FOSC = 32 MHz HFINTOSC mode FOSC = 32 MHz HFINTOSC mode FOSC = 32 MHz HS Oscillator mode (Note 6) FOSC = 32 MHz HS Oscillator mode (Note 5, 6) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k FVR and BOR are disabled. 0.1 F capacitor on VCAP. 8 MHz crystal oscillator with 4x PLL enabled.  2013-2015 Microchip Technology Inc. DS40001675C-page 395 PIC16(L)F1788/9 TABLE 31-3: POWER-DOWN CURRENTS (IPD)(1,2,4) PIC16LF1788/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1788/9 Low-Power Sleep Mode, VREGPM = 1 Param No. Device Characteristics Min. Typ† Max. +85°C Conditions Max. +125°C Units Note VDD Power-down Base Current (IPD)(2) D023 Base IPD D023 Base IPD D023A Base IPD D024 D024 D025 D025 — 0.05 1.0 8.0 A 1.8 — 0.08 2.0 9.0 A 3.0 — 0.3 3 11 A 2.3 — 0.4 4 12 A 3.0 — 0.5 6 15 A 5.0 — 10 16 18 A 2.3 — 11 18 20 A 3.0 — 12 21 26 A 5.0 — 0.5 6 14 A 1.8 — 0.8 7 17 A 3.0 — 0.8 6 15 A 2.3 — 0.9 7 20 A 3.0 — 1.0 8 22 A 5.0 — 15 28 30 A 1.8 — 18 30 33 A 3.0 — 18 33 35 A 2.3 — 19 35 37 A 3.0 WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive VREGPM = 0 LPWDT Current LPWDT Current FVR Current FVR Current — 20 37 39 A 5.0 D026 — 7.5 25 28 A 3.0 BOR Current D026 — 10 25 28 A 3.0 BOR Current — 12 28 31 A 5.0 D027 — 0.5 4 10 A 3.0 LPBOR Current D027 — 0.8 6 14 A 3.0 LPBOR Current — 1 8 17 A 5.0 — 0.5 5 9 A 1.8 — 0.8 8.5 12 A 3.0 — 1.1 6 10 A 2.3 — 1.3 8.5 20 A 3.0 — 1.4 10 25 A 5.0 D028 D028 * † Note 1: 2: 3: 4: 5: SOSC Current SOSC Current These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC oscillator source is FRC. 0.1 F capacitor on VCAP. VREGPM = 0. DS40001675C-page 396  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 31-3: POWER-DOWN CURRENTS (IPD)(1,2,4) (CONTINUED) PIC16LF1788/9 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1788/9 Low-Power Sleep Mode, VREGPM = 1 Param No. Device Characteristics Min. Power-down Base Current (IPD) D029 D029 D030 D030 D031 D032 * † Note 1: 2: 3: 4: 5: Conditions Max. +85°C Max. +125°C Units VDD Note (2) — 0.05 2 9 A — 0.08 3 10 A 3.0 — 0.3 4 12 A 2.3 — 0.4 5 13 A 3.0 — 0.5 7 16 A 5.0 — 250 — — A 1.8 — 280 — — A 3.0 — 230 — — A 2.3 — 250 — — A 3.0 5.0 1.8 ADC Current (Note 3), no conversion in progress ADC Current (Note 3), no conversion in progress ADC Current (Note 3), conversion in progress ADC Current (Note 3, Note 4, Note 5), conversion in progress — 350 — — A — 250 650 — A 3.0 Op Amp (High power) 250 650 — A 3.0 Op Amp (High power) (Note 5) D031 D032 Typ† — 350 850 — A 5.0 — 250 650 — A 1.8 — 300 700 — A 3.0 — 280 650 — A 2.3 — 300 700 — A 3.0 — 310 700 — A 5.0 Comparator, Normal-Power mode Comparator, Normal-Power mode (Note 5) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC oscillator source is FRC. 0.1 F capacitor on VCAP. VREGPM = 0.  2013-2015 Microchip Technology Inc. DS40001675C-page 397 PIC16(L)F1788/9 TABLE 31-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. VIL Characteristic Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D034 — — 0.8 V 4.5V  VDD  5.5V — — 0.15 VDD V 1.8V  VDD  4.5V with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V with I2C levels — — 0.3 VDD V with SMBus levels with TTL buffer D034A D035 D036 D036A VIH — — 0.8 V MCLR, OSC1 (RC mode)(1) — — 0.2 VDD V OSC1 (HS mode) — — 0.3 VDD V 2.7V  VDD  5.5V Input High Voltage I/O ports: D040 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V with I2C levels 0.7 VDD — — V with TTL buffer D040A D041 with SMBus levels D042 MCLR 2.1 — — V 0.8 VDD — — V 2.7V  VDD  5.5V D043A OSC1 (HS mode) 0.7 VDD — — V D043B OSC1 (RC mode) 0.9 VDD — — V (Note 1) nA IIL Input Leakage Current(2) D060 I/O ports — ±5 ± 125 ±5 ± 1000 nA VSS  VPIN  VDD, Pin at high-impedance @ 85°C 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD @ 85°C 25 25 100 140 200 300 A VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS — — 0.6 V IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V VDD - 0.7 — — V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V IPUR Weak Pull-up Current D070* VOL D080 Output Low Voltage(4) I/O ports VOH D090 Output High Voltage(4) I/O ports * † Note 1: 2: 3: 4: These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. DS40001675C-page 398  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 31-4: I/O PORTS (CONTINUED) Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units — — 15 pF — — 50 pF Conditions Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin D101A* CIO All I/O pins In XT, HS and LP modes when external clock is used to drive OSC1 VCAP Capacitor Charging D102 Charging current — 200 — A D102A Source/sink capability when charging complete — 0.0 — mA * † Note 1: 2: 3: 4: These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode.  2013-2015 Microchip Technology Inc. DS40001675C-page 399 PIC16(L)F1788/9 TABLE 31-5: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RE3 pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA VDD for Bulk Erase 2.7 — VDDMAX V D112 D113 VPEW VDDMIN — VDDMAX V D114 IPPPGM Current on MCLR/VPP during Erase/Write VDD for Write or Row Erase — — 1.0 mA D115 IDDPGM Current on VDD during Erase/Write — 5.0 mA — — E/W (Note 3) Data EEPROM Memory D116 ED Byte Endurance 100K -40C to +85C D117 VDRW VDD for Read/Write VDDMIN — VDDMAX V D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D120 TREF 100k — — E/W -40°C to +85°C D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPR VDD for Read VDDMIN — VDDMAX V D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Number of Total Erase/Write Cycles before Refresh(2) Program Flash Memory Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section 12.2 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. DS40001675C-page 400  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 31.4 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ. Units Conditions 60 C/W 28-pin SPDIP package 80 C/W 28-pin SOIC package 90 C/W 28-pin SSOP package 27.5 C/W 28-pin QFN 6x6mm package 47.2 C/W 40-pin DIP package 41 C/W 40-pin UQFN 5x5 46 C/W 44-pin TQFP package 24.4 C/W 44-pin QFN 8x8mm package 31.4 C/W 28-pin SPDIP package 24 C/W 28-pin SOIC package 24 C/W 28-pin SSOP package 24 C/W 28-pin QFN 6x6mm package 24.7 C/W 40-pin DIP package 5.5 C/W 40-pin UQFN 5x5 14.5 C/W 44-pin TQFP package 44-pin QFN 8x8mm package 20 C/W 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature 3: TJ = Junction Temperature  2013-2015 Microchip Technology Inc. DS40001675C-page 401 PIC16(L)F1788/9 31.5 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 31-4: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins DS40001675C-page 402  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 31-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 31-6: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) OS02 TOSC External CLKIN Period(1) Oscillator Period(1) OS03 TCY Instruction Cycle Time(1) OS04* TosH, TosL External CLKIN High, External CLKIN Low OS05* TosR, TosF External CLKIN Rise, External CLKIN Fall Min. Typ† Max. Units Conditions DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 20 MHz EC Oscillator mode (high) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode 1 — 20 MHz HS Oscillator mode, VDD > 2.7V DC — 4 MHz RC Oscillator mode, VDD > 2.0V 27 —  s LP Oscillator mode 250 —  ns XT Oscillator mode 50 —  ns HS Oscillator mode 50 —  ns EC Oscillator mode — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode 200 TCY DC ns TCY = 4/FOSC 2 — — s LP oscillator 100 — — ns XT oscillator 20 — — ns HS oscillator 0 —  ns LP oscillator 0 —  ns XT oscillator 0 —  ns HS oscillator * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2013-2015 Microchip Technology Inc. DS40001675C-page 403 PIC16(L)F1788/9 TABLE 31-7: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. OS08 Sym. HFOSC OS08A MFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2) Internal Calibrated MFINTOSC Frequency(2) Freq. Tolerance Min. Typ† Max. Units ±2% ±3% — — 16.0 16.0 — — MHz MHz 0°C  TA  +60°C, VDD 2.5V 60°C TA 85°C, VDD 2.5V ±5% — 16.0 — MHz -40°C  TA  +125°C ±2% ±3% — — 500 500 — — kHz kHz 0°C  TA  +60°C, VDD 2.5V 60°C TA 85°C, VDD 2.5V ±5% — 500 — kHz -40°C  TA  +125°C -40°C  TA  +125°C Conditions OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz OS10* TWARM HFINTOSC Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time — — 3.2 8 s VREGPM = 0 — — 24 35 s VREGPM = 0 * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design. FIGURE 31-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 Temperature (°C) ± 3% 60 ± 2% 25 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001675C-page 404  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 31-8: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. F10 FOSC Oscillator Frequency Range F11 FSYS On-Chip VCO System Frequency F12 TRC PLL Start-up Time (Lock Time) F13* CLK CLKOUT Stability (Jitter) Typ† Max. Units 4 — 8 MHz 16 — 32 MHz — — 2 ms -0.25% — +0.25% % Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 31-7: Cycle CLKOUT AND I/O TIMING Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19  2013-2015 Microchip Technology Inc. DS40001675C-page 405 PIC16(L)F1788/9 TABLE 31-9: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic FOSC to CLKOUT (1) OS11 TosH2ckL OS12 TosH2ckH FOSC to CLKOUT (1) OS13 TckL2ioV CLKOUT to Port out valid OS14 OS15 OS16 TioV2ckH TosH2ioV TosH2ioI OS17 TioV2osH OS18* TioR Port input valid before CLKOUT(1) Fosc (Q1 cycle) to Port out valid Fosc (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc(Q2 cycle) (I/O in setup time) Port output rise time OS19* TioF Port output fall time OS20* Tinp OS21* Tioc (1) Min. Typ† Max. Units Conditions — — 70 ns VDD = 3.3-5.0V — — 72 ns VDD = 3.3-5.0V — — 20 ns TOSC + 200 ns — 50 — 50 — — 70* — ns ns ns 20 — — ns — — — — 25 25 40 15 28 15 — — 72 32 55 30 — — ns INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. DS40001675C-page 406 ns VDD = 3.3-5.0V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V ns ns  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 31-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 31-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 TPWRT Reset (due to BOR) 33(1) Note 1: The delay, (TPWRT) releasing Reset, only occurs when the Power-up Timer is enabled, (PWRTE = 0).  2013-2015 Microchip Technology Inc. DS40001675C-page 407 PIC16(L)F1788/9 TABLE 31-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic MCLR Pulse Width (low) Min. Typ† Max. Units Conditions 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 10 16 27 ms VDD = 3.3V-5V 1:512 Prescaler used 30 TMCL 31 TWDTLP Low-Power Watchdog Timer Time-out Period 32 TOST Oscillator Start-up Timer Period(1), (2) — 1024 — 33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s 35 VBOR Brown-out Reset Voltage 2.55 2.30 1.80 2.70 2.45 1.90 2.85 2.6 2.10 V V V BORV = 0 BORV =1 (F device) BORV =1 (F device) 1.8 2.1 2.5 V LPBOR = 1 0 25 75 mV -40°C to +85°C 1 3 5 s VDD  VBOR 35A VLPBOR Low-Power Brown-out 36* VHYST 37* TBORDC Brown-out Reset DC Response Time * † Note 1: 2: 3: 4: Brown-out Reset Hysteresis Tosc (Note 3) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. DS40001675C-page 408  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 31-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 31-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler With Prescaler TT0L 41* T0CKI Low Pulse Width No Prescaler With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous TT1L 46* T1CKI Low Time Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.5 TCY + 20 — — ns 15 — — ns 30 — — ns Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Greater of: 30 or TCY + 40 N — — ns 47* TT1P T1CKI Input Synchronous Period 48 FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment Asynchronous * † Typ† 60 — — ns 32.4 32.768 33.1 kHz 2 TOSC — 7 TOSC — Conditions N = prescale value (2, 4, ..., 256) N = prescale value (1, 2, 4, 8) Timers in Sync mode These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2013-2015 Microchip Technology Inc. DS40001675C-page 409 PIC16(L)F1788/9 FIGURE 31-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 31-5 for load conditions. TABLE 31-12: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Param Sym. No. CC01* TccL Characteristic CCPx Input Low Time No Prescaler With Prescaler CC02* TccH CCPx Input High Time No Prescaler With Prescaler CC03* TccP * † CCPx Input Period Min. Typ† Max. Units 0.5TCY + 20 — — ns 20 — — ns 0.5TCY + 20 — — ns 20 — — ns 3TCY + 40 N — — ns Conditions N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001675C-page 410  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 31-13: ADC CONVERTER (ADC) 12-BIT DIFFERENTIAL CHARACTERISTICS: Operating Conditions VDD = 3V, Temp. = 25°C, Single-ended 2 s TAD, VREF+ = 3V, VREF- = VSS Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±1 ±1.6 LSb AD03 EDL Differential Error — ±1 ±1.4 LSb No missing codes AD04 EOFF Offset Error — ±1 ±3.5 LSb AD05 EGN — ±1 ±2 LSb AD06 VREF Reference Voltage(3) 1.8 — VDD V AD07 VAIN Full-Scale Range — — VREF AD08 ZAIN Recommended Impedance of Analog Voltage Source — — 10 Gain Error V k Can go higher if external 0.01F capacitor is present on input pin. AD09 NR Resolution — — 12 bit AD10 EIL Integral Error — ±2 — LSb AD11 EDL Differential Error AD12 EOFF Offset Error AD13 EGN AD14 VREF Reference Voltage(3) AD15 VAIN Full-Scale Range AD16 ZAIN Recommended Impedance of Analog Voltage Source * † Note 1: 2: 3: 4: Gain Error VREF = (VREF+ minus VREF-) — ±2 — LSb — ±1 — LSb — ±1 — LSb 1.8 — VDD V — — VREF V — — 10 VREF = (VREF+ minus VREF-) k Can go higher if external 0.01F capacitor is present on input pin. These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. TABLE 31-14: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. AD130* TAD AD131 TCNV AD132* TACQ Characteristic Min. Typ† Max. Units Conditions ADC Clock Period 1.0 — 9.0 s TOSC-based ADC Internal RC Oscillator Period 1.0 2.5 6.0 s ADCS = 11 (ADRC mode) Conversion Time (not including Acquisition Time)(1) — 15 (12-bit) 13 (10-bit) — TAD Set GO/DONE bit to conversion complete Acquisition Time — 5.0 — s * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle.  2013-2015 Microchip Technology Inc. DS40001675C-page 411 PIC16(L)F1788/9 FIGURE 31-12: ADC CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 Tcy (TOSC/2(1)) AD131 Q4 AD130 ADC CLK 7 ADC Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 Tcy ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. FIGURE 31-13: ADC CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 Tcy AD131 Q4 AD130 ADC CLK 7 ADC Data 6 5 4 OLD_DATA ADRES 2 1 0 NEW_DATA 1 Tcy ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. DS40001675C-page 412  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 31-15: OPERATIONAL AMPLIFIER (OPA) Standard Operating Conditions (unless otherwise stated): VDD = 3.0 Temperature 25°C, High-Power Mode DC CHARACTERISTICS Param No. Symbol OPA01* GBWP Parameters Min. Typ. Max. Units Gain Bandwidth Product — 3.5 — MHz OPA02* TON Turn on Time — 10 — s OPA03* PM Phase Margin — 40 — degrees OPA04* SR Slew Rate — 3 — V/s OPA05 OFF Offset — ±3 ±9 mV OPA06 CMRR Common Mode Rejection Ratio 52 70 — dB OPA07* AOL Open Loop Gain — 90 — dB OPA08 VICM Input Common Mode Voltage 0 — VDD V OPA09* PSRR Power Supply Rejection Ratio — 80 — dB * Conditions High-Power mode VDD > 2.5 These parameters are characterized but not tested. TABLE 31-16: COMPARATOR SPECIFICATIONS Operating Conditions: VDD = 3.0V, Temperature = 25°C (unless otherwise stated). Param No. Sym. Characteristics Typ. Max. Units — ±2.5 ±9 mV Comments CM01 VIOFF CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio 35 50 — dB CM04A Response Time Rising Edge — 60 125 ns Normal-Power mode measured at VDD/2 (Note 1) CM04B Response Time Falling Edge — 60 110 ns Normal-Power mode measured at VDD/2 (Note 1) Response Time Rising Edge — 85 — ns Low-Power mode measured at VDD/2 (Note 1) Response Time Falling Edge — 85 — ns Low-Power mode measured at VDD/2 (Note 1) Comparator Mode Change to Output Valid* — — 10 s 20 45 75 mV CM04C TRESP CM04D Input Offset Voltage Min. Normal-Power mode VICM = VDD/2 CM05 Tmc2ov CM06 CHYSTER Comparator Hysteresis * Note 1: These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled. 2:  2013-2015 Microchip Technology Inc. Hystersis ON, High Power measured at VDD/2 (Note 2) DS40001675C-page 413 PIC16(L)F1788/9 TABLE 31-17: 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: VDD = 3V, Temperature = 25°C (unless otherwise stated). Param No. Sym. Characteristics Min. Typ. Max. Units DAC01* CLSB5 Step Size — VDD/32 — V DAC02* CACC5 Absolute Accuracy — —  1/2 LSb DAC03* CR5 Unit Resistor Value (R) — 5K —  DAC04* CST5 Settling Time(2) — — 10 s * Note 1: 2: Comments These parameters are characterized but not tested. See Section 32.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. Settling time measured while DACR transitions from ‘00000’ to ‘01111’. TABLE 31-18: 8-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions: VDD = 3V, Temperature = 25°C (unless otherwise stated). Param No. DAC05* Sym. Characteristics CLSB8 Step Size Min. Typ. Max. Units — VDD/256 — V LSb DAC06* CACC8 Absolute Accuracy — —  1.5 DAC07* CR8 Unit Resistor Value (R) — 600 —  DAC08* CST8 Settling Time(1) — — 10 s * Note 1: Comments These parameters are characterized but not tested. Settling time measured while DACR transitions from ‘0x00’ to ‘0xFF’. FIGURE 31-14: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 31-4 for load conditions. TABLE 31-19: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Max. Units — 80 ns US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time (Master mode) 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns DS40001675C-page 414 Conditions  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 31-15: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 31-4 for load conditions. TABLE 31-20: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) US126 TCKL2DTL Data-hold after CK  (DT hold time)  2013-2015 Microchip Technology Inc. Min. Max. Units 10 — ns 15 — ns Conditions DS40001675C-page 415 PIC16(L)F1788/9 FIGURE 31-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 31-4 for load conditions. FIGURE 31-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 SP78 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 31-4 for load conditions. DS40001675C-page 416  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 FIGURE 31-18: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 31-4 for load conditions. FIGURE 31-19: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 31-4 for load conditions.  2013-2015 Microchip Technology Inc. DS40001675C-page 417 PIC16(L)F1788/9 TABLE 31-21: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Symbol Characteristic SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL Min. Typ† Max. Units Conditions 2.25*TCY — — ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns 100 — — ns 100 — — ns 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge TDIV2SCL SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge SP75* TDOR SDO data output rise time SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns — 10 25 ns — — 50 ns SP79* TSCF SCK output fall time (Master mode) SP80* TSCH2DOV, SDO data output valid after TSCL2DOV SCK edge 3.0-5.5V 1.8-5.5V SP81* TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, SS after SCK edge TSCL2SSH — — 145 ns Tcy — — ns — — 50 ns 1.5TCY + 40 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 31-20: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Start Condition Stop Condition Note: Refer to Figure 31-4 for load conditions. DS40001675C-page 418  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 TABLE 31-22: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Symbol SP90* TSU:STA SP91* THD:STA TSU:STO SP92* Characteristic 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time 400 kHz mode 600 — — 100 kHz mode 4000 — — 400 kHz mode 600 — — Hold time * Typ. Max. Units Start condition THD:STO Stop condition SP93 Min. Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 31-21: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 31-4 for load conditions.  2013-2015 Microchip Technology Inc. DS40001675C-page 419 PIC16(L)F1788/9 TABLE 31-23: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.5TCY — SSP module SP102* TR SP103* TF SP106* THD:DAT SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode — 250 ns 400 kHz mode 20 + 0.1CB 250 ns Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s — ns SP107* TSU:DAT Data input setup time 100 kHz mode 250 400 kHz mode 100 — ns SP109* TAA Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns SP110* Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF SP111 * Note 1: 2: TBUF CB Conditions Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001675C-page 420  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 NOTES:  2013-2015 Microchip Technology Inc. DS40001675C-page 421 PIC16(L)F1788/9 32.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the F and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each temperature range.  2013-2015 Microchip Technology Inc. DS40001675C-page 422 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 35 14 12 30 25 10 IDD (μA) Typical IDD (μA) Max. Max: 85°C + 3σ Typical: 25°C Max. Max: 85°C + 3σ Typical: 25°C 8 Typical 20 6 15 4 10 2 5 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 6.0 5.5 VDD (V) FIGURE 32-1: IDD, LP Oscillator Mode, Fosc = 32 kHz, PIC16LF1788/9 Only. FIGURE 32-2: IDD, LP Oscillator Mode, Fosc = 32 kHz, PIC16F1788/9 Only. 500 400 450 Typical: 25°C 350 4 MHz XT Max: 85°C + 3σ 400 4 MHz XT 300 350 IDD (μA) IDD (μA) 4 MHz EXTRC 4 MHz EXTRC 250 200 300 250 1 MHz XT 200 150 1 MHz XT 150 100 100 50 1 MHz EXTRC 1 MHz EXTRC 50 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 32-3: IDD Typical, XT and EXTRC Oscillator, PIC16LF1788/9 Only. FIGURE 32-4: IDD Maximum, XT and EXTRC Oscillator, PIC16LF1788/9 Only. 600 450 4 MHz XT 4 MHz XT Max: 85°C + 3σ Typical: 25°C 400 500 4 MHz EXTRC 350 400 250 IDD (μA) IDD (μA) 300 1 MHz XT 200 150 4 MHz EXTRC 1 MHz XT 300 200 1 MHz EXTRC 1 MHz EXTRC 100 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-5: IDD Typical, XT and EXTRC Oscillator, PIC16F1788/9 Only. DS40001675C-page 423 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-6: IDD Maximum, XT and EXTRC Oscillator, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 9 30 Max. 8 Max: 85°C + 3σ Typical: 25°C 7 Max: 85°C + 3σ Typical: 25°C 25 Max. Typical Typical 20 IDD (μA) IDD (μA) 6 5 15 4 3 10 2 5 1 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) FIGURE 32-7: IDD, EC Oscillator LP Mode, Fosc = 32 kHz, PIC16LF1788/9 Only. , , 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-8: IDD, EC Oscillator LP Mode, Fosc = 32 kHz, PIC16F1788/9 Only. , 70 60 Max. Max: 85°C + 3σ Typical: 25°C 60 Max: 85°C + 3σ Typical: 25°C 50 Max. 50 IDD (μA) IDD (μA) 40 Typical 30 Typical 40 30 20 20 10 10 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 6.0 5.5 VDD (V) VDD (V) FIGURE 32-9: IDD, EC Oscillator LP Mode, Fosc = 500 kHz, PIC16LF1788/9 Only. FIGURE 32-10: IDD, EC Oscillator LP Mode, Fosc = 500 kHz, PIC16F1788/9 Only. 350 400 300 350 4 MHz Typical: 25°C 4 MHz Max: 85°C + 3σ 300 250 IDD (μA) IDD (μA) 250 200 150 200 150 100 1 MHz 1 MHz 100 50 50 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 32-11: IDD Typical, EC Oscillator MP Mode, PIC16LF1788/9 Only.  2013-2015 Microchip Technology Inc. 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 32-12: IDD Maximum, EC Oscillator MP Mode, PIC16LF1788/9 Only. DS40001675C-page 424 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 450 400 400 350 Max: 85°C + 3σ Typical: 25°C 4 MHz 4 MHz 350 300 IDD (μA) IDD (μA) 300 250 200 250 1 MHz 200 1 MHz 150 150 100 100 50 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 FIGURE 32-13: IDD Typical, EC Oscillator MP Mode, PIC16F1788/9 Only. yp , , 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 32-14: IDD Maximum, EC Oscillator MP Mode, PIC16F1788/9 Only. g 3.5 3.0 Typical: 25°C Max: 85°C + 3σ 3.0 2.5 32 MHz 32 MHz 2.5 IDD (mA) IDD (mA) 2.0 1.5 16 MHz 2.0 1.5 16 MHz 1.0 1.0 8 MHz 8 MHz 0.5 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.6 3.8 1.8 2.0 2.2 2.4 2.6 FIGURE 32-15: IDD Typical, EC Oscillator HP Mode, PIC16LF1788/9 Only. yp , , 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 32-16: IDD Maximum, EC Oscillator HP Mode, PIC16LF1788/9 Only. g 3.0 2.5 32 MHz Max: 85°C + 3σ Typical: 25°C 32 MHz 2.5 2.0 IDD (mA) IDD (mA) 2.0 1.5 16 MHz 1.5 16 MHz 1.0 1.0 8 MHz 0.5 8 MHz 0.5 0.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-17: IDD Typical, EC Oscillator HP Mode, PIC16F1788/9 Only. DS40001675C-page 425 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-18: IDD Maximum, EC Oscillator HP Mode, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 9 30 Max. 8 Max. Max: 85°C + 3σ Typical: 25°C 25 7 Typical Typical 20 IDD (μA) IDD (μA) 6 5 15 4 3 10 2 Max: 85°C + 3σ Typical: 25°C 5 1 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 32-19: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16LF1788/9 Only. FIGURE 32-20: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16F1788/9 Only. 700 600 550 Max. Max: 85°C + 3σ Typical: 25°C 500 Max. Max: 85°C + 3σ Typical: 25°C 600 Typical 450 500 IDD (μA) IDD (μA) 400 350 Typical 400 300 300 250 200 200 150 100 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 VDD (V) FIGURE 32-21: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16LF1788/9 Only. 4.5 5.0 5.5 6.0 FIGURE 32-22: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16F1788/9 Only. 1.8 1.8 16 MHz 1.6 1.6 16 MHz Typical: 25°C Max: 85°C + 3σ 1.4 1.4 1.2 1.2 8 MHz IDD (mA) IDD (mA) 4.0 VDD (V) 1.0 0.8 4 MHz 2 MHz 0.6 0.4 8 MHz 1.0 4 MHz 0.8 2 MHz 0.6 1 MHz 0.4 1 MHz 0.2 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 32-23: IDD Typical, HFINTOSC Mode, PIC16LF1788/9 Only.  2013-2015 Microchip Technology Inc. 3.8 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 32-24: IDD Maximum, HFINTOSC Mode, PIC16LF1788/9 Only. DS40001675C-page 426 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 1.6 1.8 16 MHz 1.4 1.6 Typical: 25°C 1.2 8 MHz 1.0 1.2 8 MHz IDD (mA) IDD (mA) 16 MHz Max: 85°C + 3σ 1.4 4 MHz 0.8 2 MHz 0.6 1.0 4 MHz 0.8 2 MHz 0.6 1 MHz 0.4 1 MHz 0.4 0.2 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 6.0 2.0 2.5 3.0 3.5 4.0 VDD (V) FIGURE 32-25: IDD Typical, HFINTOSC Mode, PIC16F1788/9 Only. yp , 5.0 5.5 6.0 FIGURE 32-26: IDD Maximum, HFINTOSC Mode, PIC16F1788/9 Only. , 2.0 2.0 1.8 1.6 1.6 1.4 1.4 16 MHz 1.2 IDD (mA) 16 MHz 1.0 8 MHz 0.8 20 MHz Max: 85°C + 3σ 1.8 20 MHz 1.2 IDD (mA) 4.5 VDD (V) 1.0 8 MHz 0.8 0.6 0.6 0.4 0.4 4 MHz 4 MHz 0.2 0.2 0.0 0.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.4 3.8 2.6 2.8 3.0 3.2 3.4 3.6 FIGURE 32-27: IDD Typical, HS Oscillator, 25°C, PIC16LF1788/9 Only. FIGURE 32-28: IDD Maximum, HS Oscillator, PIC16LF1788/9 Only. 2.1 2.0 20 MHz Max: 85°C + 3σ 1.8 20 MHz 1.8 1.6 16 MHz 16 MHz 1.4 1.5 IDD (mA) 1.2 IDD (mA) 3.8 VDD (V) VDD (V) 1.0 8 MHz 0.8 1.2 8 MHz 0.9 4 MHz 0.6 0.6 0.4 4 MHz 0.3 0.2 0.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-29: IDD Typical, HS Oscillator, 25°C, PIC16F1788/9 Only. DS40001675C-page 427 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-30: IDD Maximum, HS Oscillator, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 4.0 4.0 Max. 3.5 3.5 3.0 3.0 2.5 2.5 IDD (mA) IDD (mA) Max. 2.0 Typical 1.5 1.0 2.0 Typical 1.5 1.0 Typical: 25°C Max: 85°C + 3σ 0.5 Typical: 25°C Max: 85°C + 3σ 0.5 0.0 0.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) FIGURE 32-31: IDD, HS Oscillator, 32 MHz (8 MHz + 4x PLL), PIC16LF1788/9 Only. 4.5 5.0 5.5 6.0 FIGURE 32-32: IDD, HS Oscillator, 32 MHz (8 MHz + 4x PLL), PIC16F1788/9 Only. p , 450 ( ) 1.2 400 Max. Max. 1.0 350 300 0.8 IPD (μA) IPD (nA) 4.0 VDD (V) 250 Max: 85°C + 3σ Typical: 25°C 200 150 Max: 85°C + 3σ Typical: 25°C 0.6 0.4 Typical 100 0.2 Typical 50 0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 FIGURE 32-33: IPD Base, LP Sleep Mode, PIC16LF1788/9 Only. 4.5 5.0 5.5 6.0 FIGURE 32-34: IPD Base, LP Sleep Mode (VREGPM = 1), PIC16F1788/9 Only. 2.5 3.0 Max: 85°C + 3σ Typical: 25°C 2.5 Max: 85°C + 3σ Typical: 25°C 2.0 Max. Max. IPD (μA) 2.0 IPD (μA) 4.0 VDD (V) VDD (V) 1.5 1.5 1.0 1.0 Typical Typical 0.5 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 32-35: IPD, Watchdog Timer (WDT), PIC16LF1788/9 Only.  2013-2015 Microchip Technology Inc. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-36: IPD, Watchdog Timer (WDT), PIC16F1788/9 Only. DS40001675C-page 428 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. p , g 35 ( ) 35 Max: 85°C + 3σ Typical: 25°C Max. 30 30 Max. 25 Typical IPD (nA) IPD (nA) 25 20 20 15 Typical 15 10 10 Max: 85°C + 3σ Typical: 25°C 5 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-37: IPD, Fixed Voltage Reference (FVR), PIC16LF1788/9 Only. FIGURE 32-38: IPD, Fixed Voltage Reference (FVR), PIC16F1788/9 Only. p , p , ( ), ( ), 13 11 Max: 85°C + 3σ Typical: 25°C 10 Max: 85°C + 3σ Typical: 25°C 12 Max. Max. 11 10 Typical 8 9 IPD (nA) IPD (nA) 9 7 Typical 8 7 6 6 5 5 4 4 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 2.8 3.7 3.0 3.2 3.4 3.6 3.8 4.0 FIGURE 32-39: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16LF1788/9 Only. 4.4 4.6 4.8 5.0 5.2 5.4 5.6 FIGURE 32-40: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16F1788/9 Only. Ipd, Low-Power Brown-Out Reset (LPBOR = 0) Ipd, Low-Power Brown-Out Reset (LPBOR = 0) 1.8 1.8 Max. 1.6 Max: 85°C + 3σ Typical: 25°C 1.6 1.4 Max. 1.4 1.2 1.2 Max: 85°C + 3σ Typical: 25°C 1.0 IPD (μA) IPD (nA) 4.2 VDD (V) VDD (V) 0.8 0.6 1.0 0.8 0.6 Typical Typical 0.4 0.4 0.2 0.2 0.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 FIGURE 32-41: IPD, LP Brown-Out Reset (LPBOR = 0), PIC16LF1788/9 Only. DS40001675C-page 429 3.7 0.0 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 FIGURE 32-42: IPD, LP Brown-Out Reset (LPBOR = 0), PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. p , , p , 7 12 Max: 85°C + 3σ Typical: 25°C Max: 85°C + 3σ Typical: 25°C 6 10 Max. Max. 5 4 IPD (μA) IPD (μA) 8 3 Typical 6 Typical 4 2 2 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 3.8 2.0 2.5 3.0 3.5 4.0 VDD (V) FIGURE 32-43: IPD, Timer1 Oscillator, FOSC = 32 kHz, PIC16LF1788/9 Only. p , , g ( 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-44: IPD, Timer1 Oscillator, FOSC = 32 kHz, PIC16F1788/9 Only. p , ) 700 , g ( ) 900 Max: 85°C + 3σ Typical: 25°C 600 Max: 85°C + 3σ Typical: 25°C 800 Max. 700 Max. 500 IPD (μA) IPD (μA) 600 400 Typical 300 500 Typical 400 300 200 200 100 100 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 32-45: IPD, Op Amp, High GBWP Mode (OPAxSP = 1), PIC16LF1788/9 Only. FIGURE 32-46: IPD, Op Amp, High GBWP Mode (OPAxSP = 1), PIC16F1788/9 Only. 500 1.4 Max: 85°C + 3σ Typical: 25°C 450 Max: 85°C + 3σ Typical: 25°C Max. 400 1.2 Max. 350 1.0 IPD (μA) IPD (μA) 300 250 200 0.8 0.6 150 0.4 Typical 100 Typical 0.2 50 0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 32-47: IPD, ADC Non-Converting, PIC16LF1788/9 Only.  2013-2015 Microchip Technology Inc. 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-48: IPD, ADC Non-Converting, PIC16F1788/9 Only. DS40001675C-page 430 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 800 800 Max: -40°C + 3σ Typical: 25°C 700 Max: -40°C + 3σ Typical: 25°C Max. 600 600 Typical IPD (μA) IPD (μA) Max. 700 500 Typical 500 400 400 300 300 200 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 32-49: IPD, Comparator, NP Mode (CxSP = 1), PIC16LF1788/9 Only. FIGURE 32-50: IPD, Comparator, NP Mode (CxSP = 1), PIC16F1788/9 Only. 6 5 Max: -40°C max + 3σ Typical;:statistical mean @ 25°C Min: +125°C min - 3σ 5 4 3 VOL (V) VOH (V) 4 3 Max. Typical Min. Min. Typical Max. 50 60 2 2 Max: -40°C max + 3σ Typical: statistical mean @ 25°C Min: +125°C min - 3σ 1 1 0 0 -30 -25 -20 -15 -10 -5 0 0 10 20 30 IOH (mA) FIGURE 32-51: VOH vs. IOH Over Temperature, VDD = 5.0V, PIC16F1788/9 Only. 40 IOL (mA) 70 80 FIGURE 32-52: VOL vs. IOL Over Temperature, VDD = 5.0V, PIC16F1788/9 Only. 3.0 3.5 Max: -40°C max + 3σ Typical: statistical mean @ 25°C Min: +125°C min - 3σ 3.0 Max: -40°C max + 3σ Typical: statistical mean @ 25°C Min: +125°C min - 3σ 2.5 2.5 VOL (V) VOH (V) 2.0 2.0 Max. Typical Min. 1.5 1.5 Max. Typical Min. 1.0 1.0 0.5 0.5 0.0 0.0 -14 -12 -10 -8 -6 -4 IOH (mA) FIGURE 32-53: VOH vs. IOH Over Temperature, VDD = 3.0V. DS40001675C-page 431 -2 0 0 5 10 15 20 25 30 IOL (mA) FIGURE 32-54: VOL vs. IOL Over Temperature, VDD = 3.0V.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. Voh vs. Ioh over Temperature, Vdd = 1.8V Vol vs. Iol over Temperature, Vdd = 1.8V 2.0 1.8 Max: -40°C max + 3σ Typical: statistical mean @ 25°C Min: +125°C min - 3σ 1.8 1.6 Max: -40°C max + 3σ Typical: statistical mean @ 25°C Min: +125°C min - 3σ 1.6 1.4 1.4 1.2 VOL (V) VOH (V) 1.2 1.0 Min. Typical Max. 1 Min. Typical Max. 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0 -4 -3.5 -3 -2.5 -2 -1.5 -1 0 -0.5 FIGURE 32-55: VOH vs. IOH Over Temperature, VDD = 1.8V, PIC16LF1788/9 Only. 0 1 2 3 4 5 6 7 8 9 10 FIGURE 32-56: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF1788/9 Only. q LFINTOSC Frequency y 40 38 40 Max. 36 Frequency (kHz) 34 34 Frequency (kHz) Max. 36 38 Typical 32 30 Min. 28 26 Typical 32 30 Min. 28 26 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 24 22 24 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 22 20 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 20 VDD (V) 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) FIGURE 32-57: LFINTOSC Frequency, PIC16LF1788/9 Only. FIGURE 32-58: LFINTOSC Frequency, PIC16F1788/9 Only. 24 24 22 22 Max. Max. 20 18 Time (mS) Time (mS) 20 Typical 16 18 Typical 16 Min. 14 14 Min. Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 12 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 12 10 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 32-59: WDT Time-Out Period, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. 6.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 32-60: WDT Time-Out Period, PIC16LF1788/9 Only. DS40001675C-page 432 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. g ( ) y p ( ) 70 2.00 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 60 Max. 1.95 Max. 50 Voltage (mV) Voltage (V) Typical 1.90 Min. 40 30 Typical 20 1.85 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ Min. 10 0 1.80 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 Temperature (°C) p ( 40 60 80 100 120 140 Temperature (°C) FIGURE 32-61: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16LF1788/9 Only. g , 20 FIGURE 32-62: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16LF1788/9 Only. ) 70 2.60 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 60 2.55 Max. Max. Typical 50 Voltage (mV) Voltage (V) 2.50 Min. 2.45 2.40 40 Typical 30 20 Min. Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 2.35 10 0 2.30 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 FIGURE 32-63: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16F1788/9 Only. 40 60 80 100 120 140 FIGURE 32-64: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16F1788/9 Only. 2.85 80 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 2.80 Max. 60 Voltage (mV) 2.75 Typical Min. 2.70 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 70 Max. Voltage (V) 20 Temperature (°C) Temperature (°C) 50 Typical 40 30 20 2.65 Min. 10 2.60 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 32-65: Brown-Out Reset Voltage, High Trip Point (BORV = 0). DS40001675C-page 433 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 32-66: Brown-Out Reset Hysteresis, High Trip Point (BORV = 0).  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. y 2.6 50 Max. 45 2.5 Max. 40 2.4 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 35 Voltage (mV) Voltage (V) 2.3 2.2 Typical 2.1 Max: Typical + 3σ Typical: Statistical Mean 30 25 20 Typical 2.0 15 1.9 10 Min. 1.8 5 1.7 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 Temperature (°C) FIGURE 32-67: 40 60 80 100 120 140 Temperature (°C) LPBOR Reset Voltage. FIGURE 32-68: LPBOR Reset Hysteresis. 110 100 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 90 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 100 Max. 90 Max. Time (mS) Time (mS) 80 Typical 70 80 Typical 70 Min. 60 60 50 Min. 50 40 40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 FIGURE 32-69: PWRT Period, PIC16F1788/9 Only. 3.2 3.4 3.6 3.8 FIGURE 32-70: PWRT Period, PIC16LF1788/9 Only. g g , ( ) 1.58 1.58 1.70 1.68 Max: Typical + 3σ Typical: 25°C Max. Min: Typical - 3σ 1.56 1.56 Max. 1.66 1.54 1.54 1.64 Voltage Voltage (V)(V) Typical Voltage (V) 3.0 VDD (V) VDD (V) 1.62 1.60 Min. 1.58 Typical 1.52 1.52 1.50 1.5 Min. 1.56 1.48 1.48 1.54 Max: Typical + 3σ Typical: Statistical Mean 1.46 1.46 -40 Min: Typical -20 - 3σ 0 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 1.52 -60 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 32-71: POR Release Voltage.  2013-2015 Microchip Technology Inc. 140 20 40 60 80 100 120 Temperature (°C) 1.44 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 32-72: POR Rearm Voltage, NP Mode (VREGPM = 0), PIC16F1788/9 Only. DS40001675C-page 434 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. g , 1.4 12 1.3 10 Max. 1.2 Time (μs) Voltage (V) 8 1.1 Typical 1.0 Max. 6 Typical 0.9 4 Min. 0.8 Max: Typical + 3σ Typical: Statistical Mean Min: Typical - 3σ 0.7 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C 2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 1.5 2.0 2.5 3.0 3.5 Temperature (°C) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 32-73: POR Rearm Voltage, NP Mode, PIC16LF1788/9 Only. FIGURE 32-74: VREGPM = 0. 50 Wake From Sleep, 40 45 Max: Typical + 3σ Typical: statistical mean @ 25°C 35 40 Max. Max. 35 Time (μs) Time (μs) 30 30 Typical 25 Typical 25 20 20 15 10 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C 5 Note: The FVR Stabilization Period applies when: 1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from Reset. 15 0 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 FIGURE 32-75: VREGPM = 1. Wake From Sleep, g , , FIGURE 32-76: , , 1.0 1.0 0.5 0.5 DNL (LSb) DNL (LSb) , 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (mV) VDD (V) 0.0 -0.5 FVR Stabilization Period. g , , , 0.0 -0.5 -1.0 -1.0 0 128 256 384 512 640 768 896 1024 Output Code FIGURE 32-77: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25°C. DS40001675C-page 435 0 128 256 384 512 640 768 896 1024 Output Code FIGURE 32-78: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25°C.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. g , g , , , 1.0 2.0 1.0 1.5 1.0 0.5 DNL (LSb) INL (LSb) INL (LSb) 0.5 0.0 0.5 0.0 0.0 -0.5 -1.0 -1.5 -0.5 -0.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 640 768 896 1024 Output Code -1.0 -1.0 0 128 256 384 512 640 768 0 1024 896 128 256 384 FIGURE 32-79: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25°C. , g , 512 Output Code Output Code , FIGURE 32-80: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25°C. g , 2.5 2.0 2.0 1.5 1.5 0.5 Max 125C 1.0 Max -40C Max 25C 0.5 0.0 -0.5 -1.0 INL (LSb) DNL (LSb) 1.0 0.0 Min 25C Min 25C Min 125C -0.5 Min -40C -1.0 Min 125C Min -40C -1.5 -1.5 -2.0 -2.0 -2.5 0.5 1.0 2.0 TAD (μs) 4.0 , g , , 0.5 8.0 FIGURE 32-81: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. 1.0 2.0 TAD (μs) 4.0 8.0 FIGURE 32-82: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V. , 2.0 2.0 Max 125C 1.5 1.5 Max -40C Max 125C 1.0 1.0 Max 25C Max -40C 0.5 Max 25C 0.5 0.0 Min -40C -0.5 Min 25C -1.0 INL (LSb) DNL (LSb) Max -40C Max 125C Max 25C 0.0 Min -40C -0.5 Min 25C -1.0 Min 125C -1.5 Min 125C -2.0 -1.5 -2.5 -2.0 1.8 2.3 Reference Voltage (V) 3.0 FIGURE 32-83: ADC 10-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S.  2013-2015 Microchip Technology Inc. -3.0 1.8 2.3 Reference Voltage (V) 3.0 FIGURE 32-84: ADC 10-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S. DS40001675C-page 436 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. g g 3.0 2.5 2.5 2.0 2.0 1.5 DNL (LSb) DNL (LSb) 1.5 1.0 0.5 1.0 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 500 1000 1500 2000 2500 3000 4000 3500 0 500 1000 1500 Output Code FIGURE 32-85: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25°C. 2500 3000 3500 4000 FIGURE 32-86: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25°C. , 3.5 3.0 3.0 2.5 2.5 2.0 INL (LSb) 2.0 INL (LSb) 2000 Output Code 1.5 1.0 g , , , 1.5 1.0 0.5 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 500 1000 1500 2000 2500 3000 3500 0 4000 500 1000 1500 Output Code FIGURE 32-87: ADC 12-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25°C. , g , 2000 2500 3000 4000 3500 Output Code , FIGURE 32-88: ADC 12-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25°C. , , g , , , 4.5 5.5 Max -40C Max -40C 3 Max 125C 3.5 Max 125C INL (LSb) DNL (LSb) Max 25C 1.5 0 Max 25C 1.5 -0.5 Min 25C Min -40C Min 125C -1.5 Min 25C Min -40C -2.5 Min 125C -3 -4.5 0.5 1.0 2.0 TAD (μs) 4.0 8.0 FIGURE 32-89: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. DS40001675C-page 437 0.5 1.0 2.0 TAD (μs) 4.0 8.0 FIGURE 32-90: ADC 12-bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. , g , , , 6 5 5 4 Max -40C 4 Max -40C 3 3 Max 25C Max 125C 1 2 INL (LSb) DNL (LSb) Max 25C 2 Max 125C 1 0 Min 125C -1 0 Min 125C Min 25C -2 Min -40C Min -40C -1 -3 Min 25C -4 -2 1.8 2.3 Reference Voltage (V) 1.8 3.0 FIGURE 32-91: ADC 12-bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S. , g , , 2.3 Reference Voltage (V) 3.0 FIGURE 32-92: ADC 12-bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S. , 2.5 2.5 2.0 2.0 1.5 DNL (LSb) DNL (LSb) 1.5 1.0 0.5 1.0 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.5 -1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 Output Code FIGURE 32-93: ADC 12-bit Mode, Single-Ended DNL, VDD = 5.5V, TAD = 1 S, 25°C. 2500 3000 3500 4000 FIGURE 32-94: ADC 12-bit Mode, Single-Ended DNL, VDD = 5.5V, TAD = 4 S, 25°C. 3.5 3.5 2.0 3.0 3.0 1.5 2.5 1.0 2.5 INL DNL(LSb) (LSb) INL (LSb) 2000 Output Code 2.0 1.5 0.5 2.0 0.0 1.5 -0.5 1.0 1.0 -1.0 0.5 0.5 -1.5 0.0 0.0 -2.0 0 512 1024 0 500 1000 1536 -0.5 -0.5 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code FIGURE 32-95: ADC 12-bit Mode, Single-Ended INL, VDD = 5.5V, TAD = 1 S, 25°C.  2013-2015 Microchip Technology Inc. 1500 2048 2560 Output Code 2000 2500 3072 3000 3584 3500 4096 4000 Output Code FIGURE 32-96: ADC 12-bit Mode, Single-Ended INL, VDD = 5.5V, TAD = 4 S, 25°C. DS40001675C-page 438 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. , g , , , , g , , , 4 3 Max 25C Max -40C 3 Max -40C Max 125C Max 25C 2 2 INL (LSb) DNL (LSb) Max 125C 1 0 1 0 -1 Min -40C Min 125C -2 1.0 2.0 TAD (μs) Min 25C -1 Min 25C Min -40C Min 125C -2 4.0 1.0 FIGURE 32-97: ADC 12-bit Mode, Single-Ended DNL, VDD = 5.5V, VREF = 5.5V. 2.0 TAD (μs) FIGURE 32-98: ADC 12-bit Mode, Single-Ended INL, VDD = 5.5V, VREF = 5.5V. 900 800 ADC Vref+ set to Vdd ADC Vref- set to Gnd ADC Vref+ set to Vdd ADC Vref- set to Gnd 700 Max. 800 Max. Typical ADC Output Codes 600 ADC Output Codes 4.0 500 Typical 400 300 700 Min. 600 500 Min. Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ 200 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ 100 400 300 0 2.5 3.0 3.5 4.0 4.5 5.0 2 6.0 5.5 2.4 2.8 3.2 FIGURE 32-99: Temp. Indicator Initial Offset, High Range, Temp. = 20°C, PIC16F1788/9 Only. 4 4.4 4.8 5.2 6 5.6 FIGURE 32-100: Temp. Indicator Initial Offset, Low Range, Temp. = 20°C, PIC16F1788/9 Only. 800 150 ADC Vref+ set to Vdd ADC Vref- set to Gnd ADC Vref+ set to Vdd ADC Vref- set to Gnd 125 700 Max. 100 Max. 600 ADC Output Codes ADC Output Codes 3.6 VDD (V) VDD (V) 500 Min. 400 Min. 75 50 25 0 Typical 300 -25 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ 200 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ -50 Typical 100 -75 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 32-101: Temp. Indicator Initial Offset, Low Range, Temp. = 20°C, PIC16LF1788/9 Only. DS40001675C-page 439 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 32-102: Temp. Indicator Slope Normalized to 20°C, High Range, VDD = 5.5V, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 250 150 Max. ADC Vref+ set to Vdd ADC Vref- set to Gnd 200 Max. ADC Vref+ set to Vdd ADC Vref- set to Gnd Min. 100 50 0 ADC Output Codes ADC Output Codes 100 150 Min. 50 0 -50 -50 Typical -100 Typical Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ -150 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ -100 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 Temperature (°C) 40 60 80 100 120 140 Temperature (°C) FIGURE 32-103: Temp. Indicator Slope Normalized to 20°C, High Range, VDD = 3.6V, PIC16F1788/9 Only. FIGURE 32-104: Temp. Indicator Slope Normalized to 20°C, Low Range, VDD = 3.0V, PIC16F1788/9 Only. 250 150 Max. ADC Vref+ set to Vdd ADC Vref- set to Gnd 200 ADC Vref+ set to Vdd ADC Vref- set to Gnd Max. 100 Min. 100 50 0 ADC Output Codes ADC Output Codes 150 Min. 50 0 -50 -50 Typical -100 Typical Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ -150 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ -100 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 Temperature (°C) FIGURE 32-105: Temp. Indicator Slope Normalized to 20°C, Low Range, VDD = 1.8V, PIC16LF1788/9 Only. 60 80 100 120 140 FIGURE 32-106: Temp. Indicator Slope Normalized to 20°C, Low Range, VDD = 3.0V, PIC16LF1788/9 Only. 250 80 ADC Vref+ set to Vdd ADC Vref- set to Gnd 200 Max Max. 75 150 70 Min. 100 50 CMRR (dB) ADC Output Codes 40 Temperature (°C) Typical 65 60 Min 55 0 50 -50 -100 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ Typical Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ 45 40 -150 -60 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 32-107: Temp. Indicator Slope Normalized to 20°C, High Range, VDD = 3.6V, PIC16LF1788/9 Only.  2013-2015 Microchip Technology Inc. 140 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) FIGURE 32-108: Op Amp, Common Mode Rejection Ratio (CMRR), VDD = 3.0V. DS40001675C-page 440 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. g g 35% 8 6 25% 4 20% -40°C 25°C 15% 85°C Max Typical Offset Voltage (V) Percent of Units Sample Size = 3,200 30% 2 0 Min -2 125°C 10% -4 5% -6 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ -8 0% 0.0 -7 -5 -4 -3 -2 -1 0 1 2 Offset Voltage (mV) 3 4 5 6 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 7 Common Mode Voltage (V) FIGURE 32-109: Op Amp, Output Voltage Histogram, VDD = 3.0V, VCM = VDD/2. FIGURE 32-110: Op Amp, Offset Over Common Mode Voltage, VDD = 3.0V, Temp. = 25°C. 1.2 8 Max 6 1.0 Slew Rate (V/us) Offset Voltage (V) 4 Typical 2 0 -2 0.8 0.6 0.4 -4 Min 0.2 Max: Typical + 3σ Typical; statistical mean Min: Typical - 3σ -6 0.0 -8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -60 5.0 -40 -20 0 20 40 60 80 100 FIGURE 32-111: Op Amp, Offset Over Common Mode Voltage, VDD = 5.0V, Temp. = 25°C, PIC16F1788/9 Only. 140 FIGURE 32-112: Op Amp, Output Slew Rate, Rising Edge, PIC16LF1788/9 Only. , 4.0 p , g g 3.8 Vdd = 3.6V 3.7 3.7 3.6 Slew Rate (V/us) Slew Rate (V/us) 120 Temperature (°C) Common Mode Voltage (V) 3.4 Vdd = 5.5V 3.5 3.4 Vdd = 2.3V 3.3 Vdd = 3V 3.1 3.2 3.1 2.8 3.0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 32-113: Op Amp, Output Slew Rate, Falling Edge, PIC16LF1788/9 Only. DS40001675C-page 441 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 32-114: Op Amp, Output Slew Rate, Rising Edge, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 5.4 45 5.2 43 Vdd = 2.3V -40°C 41 Hysteresis (mV) Slew Rate (V/us) 5.0 4.8 4.6 Vdd = 3.6V 4.4 39 25°C 37 85°C 35 125° 33 4.2 31 4.0 3.8 Vdd = 5.5V 29 Vdd = 3V 27 3.6 25 -60 -40 -20 0 20 40 60 80 100 120 140 0.0 0.5 Temperature (°C) 1.0 1.5 2.0 2.5 3.0 3.5 Common Mode Voltage (V) FIGURE 32-115: Op Amp, Output Slew Rate, Falling Edge, PIC16F1788/9 Only. FIGURE 32-116: Comparator Hysteresis, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values. yp 30 30 25 20 20 15 15 10 Offset Voltage (mV) Offset Voltage (mV) 25 MAX 5 0 -5 MAX 10 5 0 -5 MIN -10 -10 -15 MIN -15 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Voltage (V) -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Voltage (V) FIGURE 32-117: Comparator Offset, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25°C. FIGURE 32-118: Comparator Offset, NP Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values From -40°C to 125°C. 50 Hysteresis (mV) 45 40 25°C 125° 35 85° 30 -40°C 25 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Voltage (V) FIGURE 32-119: Comparator Hysteresis, NP Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. DS40001675C-page 442 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 40 30 25 30 20 Offset Voltage (mV) Hysteresis (mV) 15 MAX 10 5 0 -5 -10 20 MAX 10 0 -10 MIN MIN -15 -20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.0 5.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 32-120: Comparator Offset, NP Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values at 25°C, PIC16F1788/9 Only. FIGURE 32-121: Comparator Offset, NP Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values From -40°C to 125°C, PIC16F1788/9 Only. yp 90 140 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 120 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 80 70 125°C 60 125°C Time (nS) Time (nS) 100 80 25°C 60 50 25°C 40 30 40 20 -40°C -40°C 20 10 0 0 1.8 2.1 2.4 2.7 3.0 3.3 2.2 3.6 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 VDD (V) VDD (V) FIGURE 32-122: Comparator Response Time Over Voltage, NP Mode (CxSP = 1), Typical Measured Values, PIC16LF1788/9 Only. FIGURE 32-123: Comparator Response Time Over Voltage, NP Mode (CxSP = 1), Typical Measured Values, PIC16F1788/9 Only. 800 1,400 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 1,200 Max: Typical + 3σ (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3σ (-40°C to +125°C) 700 600 Time (nS) Time (nS) 1,000 800 125°C 600 500 125°C 400 300 25°C 25°C 400 200 200 100 -40°C -40°C 0 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 32-124: Comparator Output Filter Delay Time Over Temp., NP Mode (CxSP = 1), Typical Measured Values, PIC16LF1788/9 Only. DS40001675C-page 443 2.2 2.5 2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5 VDD (V) FIGURE 32-125: Comparator Output Filter Delay Time Over Temp., NP Mode (CxSP = 1), Typical Measured Values, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 0.025 0.00 0.020 -0.05 0.015 -0.10 0.010 0.005 -40°C 25°C 0.000 85°C 125°C -0.005 Absolute INL (LSb) Absolute DNL (LSb) Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. -0.15 -0.20 25°C 85°C 125°C -0.30 -0.010 -0.35 -0.015 -0.40 -0.020 -40°C -0.25 -0.45 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code 0 FIGURE 32-126: Typical DAC DNL Error, VDD = 3.0V, VREF = External 3V. 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 32-127: Typical DAC INL Error, VDD = 3.0V, VREF = External 3V. 0.020 0.00 -0.05 0.015 -0.10 Absolute INL (LSb) Absolute DNL (LSb) 0.010 0.005 -40°C 25°C 0.000 85°C 125°C -0.15 -0.20 -40°C 25°C -0.25 85°C 125°C -0.30 -0.005 -0.35 -0.010 -0.40 -0.015 -0.45 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code 0 FIGURE 32-128: Typical DAC DNL Error, VDD = 5.0V, VREF = External 5V, PIC16F1788/9 Only. FIGURE 32-129: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V, PIC16F1788/9 Only. 0.45 0.4 0.90 -2.1 0.35 Vref = Int. Vdd 0.3 0.3 Vref = Ext. 1.8V Vref = Ext. 2.0V 0.25 0.2 Vref = Int. Vdd Vref = Ext. 1.8V Vref = Ext. 2.0V 0.15 0.2 Vref = Ext. 3.0V 0.1 0.05 -50 0 50 Temperature (°C) 100 Absolute Absolute INL (LSb) INL (LSb) Absolute Absolute DNL (LSb) DNL (LSb) 0.4 0.10 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code -2.3 0.88 Vref = Int. Vdd -2.5 Vref = Ext. 1.8V Vref = Ext. 2.0V Vref = Ext. 3.0V 0.86 -2.7 -2.9 0.84 -3.1 0.0 25 85 125 -3.3 0.82 -3.5 0.0 0.80 150 -40 1.0 2.0 3.0 Temperature (°C) 4.0 5.0 0.78 -60 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 140 FIGURE 32-130: Absolute Value of DAC DNL Error, VDD = 3.0V, VREF = VDD.  2013-2015 Microchip Technology Inc. -60 -40 -20 0 FIGURE 32-131: Error, VDD = 3.0V. 20 40 60 Temperature (°C) 80 100 120 140 Absolute Value of DAC INL DS40001675C-page 444 PIC16(L)F1788/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C. 0.3 0.30 0.9 -2.1 Vref = Int. Vdd 0.26 0.2 Vref = Ext. 1.8V Vref = Ext. 2.0V Vref = Ext. 3.0V Vref = Ext. 5.0V 0.15 0.22 0.1 -40 25 85 125 0.18 0.05 Absolute Absolute INL (LSb) INL (LSb) Absolute Absolute DNL (LSb) DNL (LSb) 0.25 -2.3 0.88 Vref = Int. Vdd -2.5 Vref = Ext. 1.8V Vref = Ext. 2.0V Vref = Ext. 3.0V 0.86 -2.7 -2.9 -40 25 85 0.84 -3.1 125 -3.3 0.82 -3.5 0 0.14 0.0 1.0 2.0 3.0 4.0 Temperature (°C) 5.0 0.0 0.8 6.0 0.10 1.0 2.0 3.0 4.0 Temperature (°C) 5.0 6.0 0.78 -60 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 140 FIGURE 32-132: Absolute Value of DAC DNL Error, VDD = 5.0V, PIC16F1788/9 Only. DS40001675C-page 445 -60 -40 -20 0 20 40 60 Temperature (°C) 80 100 120 140 FIGURE 32-133: Absolute Value of DAC INL Error, VDD = 5.0V, PIC16F1788/9 Only.  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 33.0 DEVELOPMENT SUPPORT The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools 33.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2013-2015 Microchip Technology Inc. DS40001675C-page 446 PIC16(L)F1788/9 33.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 33.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 33.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 33.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001675C-page 447  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 33.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 33.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables.  2013-2015 Microchip Technology Inc. 33.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 33.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 33.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001675C-page 448 PIC16(L)F1788/9 33.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 33.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001675C-page 449  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 34.0 PACKAGING INFORMATION 34.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC16F1788 -I/SP e3 1204017 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC16F1788 -I/SO e3 1204017 1204017 Example PIC16F1788 -I/SS e3 1204017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2013-2015 Microchip Technology Inc. DS40001675C-page 450 PIC16(L)F1788/9 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) PIN 1 Example PIN 1 16F1788 -I/ML e3 XXXXXXXX XXXXXXXX YYWWNNN 120417 40-Lead PDIP (600 mil) XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F1789 -E/P e3 120417 40-Lead UQFN (5x5x0.5 mm) PIN 1 DS40001675C-page 451 Example PIN 1 PIC16 F1789 -I/MV e3 120417  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Package Marking Information (Continued) 44-Lead QFN (8x8x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F1789 -E/ML e3 120417 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC16F1789 -E/PT e3 120417  2013-2015 Microchip Technology Inc. DS40001675C-page 452 PIC16(L)F1788/9 34.2 Package Details The following sections give the technical details of the packages.                 !" 4 '("' # '  5$ +") ""'     5  & ' '$' '' 366+++(    (6  5 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 7'" (":('" 8#(* & " '  8-9/ 8 8 8; < =  2-  ''   > >  $$  5 5""   .  2"''    > > #$ '#$ ?$' /  . .. $$  5?$' /  =  ;! :'  . .@   ''  :  .  :$ 5"" =   *    *  =  2 > > 7  :$?$' :+ :$?$' ;! +  , . !"  !"#$%&'# (! )*#'(#"'* '$+''' $   ,& '-  ' "'  . (""$/$' #$($&"  ' #""$&"  ' #"""'% $0  "$  ("$'    /1 2-3 2" (" ' % '!#"++'#''  "       + -2 DS40001675C-page 453  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001675C-page 454 PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001675C-page 455  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001675C-page 456 PIC16(L)F1788/9   #$   %     &'    % !" 4 '("' # '  5$ +") ""'     5  & ' '$' '' 366+++(    (6  5 D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 7'" (":('" 8#(* & " '  ::// 8 8 8; < =  @2- ;! 9'  > >  $$  5 5""  @  = '$&&   > > ;! ?$' /  = = $$  5?$' /  . @ ;! :'     4':' :    4' ' : /4 :$ 5""  > 4'  A A  =A :$?$' *  > .= !"  !"#$%&'# (! )*#'(#"'* '$+''' $   (""$/$' #$($&"  ' #""$&"  ' #"""'% $((  "$ . ("$'    /1 2-3 2" (" ' % '!#"++'#''  " /43 &  (")#"#+'#''  )& & (' # ""       + -.2 DS40001675C-page 457  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001675C-page 458 PIC16(L)F1788/9   ( )* !  + ,  -.-   ()! /# '&&  0   +# !" 4 '("' # '  5$ +") ""'     5  & ' '$' '' 366+++(    (6  5 D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 7'" (":('" 8#(* & " '  ::// 8 8 8; < =  @2- ;! 9'  =   '$&&     -' ' 5"" . ;! ?$' / /% "$ $?$' / ;! :'  /% "$ $:' /4 @2.@ .  @2-  .@ . -' '?$' * . . . -' ':' :    -' ''/% "$ $ B  > !"  !"#$%&'# (! )*#'(#"'* '$+''' $    5""+"#'$ . ("$'    /1 2-3 2" (" ' % '!#"++'#''  " /43 &  (")#"#+'#''  )& & (' # ""  >       + -2 DS40001675C-page 459  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9   ( )* !  + ,  -.-   ()! /# '&&  0   +# !" 4 '("' # '  5$ +") ""'     5  & ' '$' '' 366+++(    (6  5  2013-2015 Microchip Technology Inc. DS40001675C-page 460 PIC16(L)F1788/9 1        -    !" 4 '("' # '  5$ +") ""'     5  & ' '$' '' 366+++(    (6  5 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 7'" (":('" 8#(* & " '  8-9/ 8 8 8; <   2-  ''   > >  $$  5 5""   >  2"''    > > #$ '#$ ?$' /  > @ $$  5?$' / = > = ;! :'  = >   ''  :  >  :$ 5"" = >  * . >  *  > . 2 > > 7  :$?$' :+ :$?$' ;! +  ,  !"  !"#$%&'# (! )*#'(#"'* '$+''' $   ,& '-  ' "'  . (""$/$' #$($&"  ' #""$&"  ' #"""'% $0  "$  ("$'    /1 2-3 2" (" ' % '!#"++'#''  "       + -@2 DS40001675C-page 461  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001675C-page 462 PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001675C-page 463  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001675C-page 464 PIC16(L)F1788/9 DS40001675C-page 465  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9  2013-2015 Microchip Technology Inc. DS40001675C-page 466 PIC16(L)F1788/9 DS40001675C-page 467  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 11  2# ( )3 2  4.4.4  * '  2() !" 4 '("' # '  5$ +") ""'     5  & ' '$' '' 366+++(    (6  5 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 7'" (":('" 8#(* &:$" ::// 8 8 8; <  :$ '   ;! 9'  > =2> $$  5 5""     '$&&   >  4':' :  @  4' ' :  /4 4'  ;! ?$' / 2- ;! :'  2- $$  5?$' / 2- $$  5:'  2- A .A A :$ 5""  >  :$?$' * . .  $ &'  A A .A $ &'2''(  A A .A !"  !"#$%&'# (! )*#'(#"'* '$+''' $   -(& "'   "  'X"Y(!  . (""$/$' #$($&"  ' #""$&"  ' #"""'% $((  "$  ("$'    /1 2-3 2" (" ' % '!#"++'#''  " /43 &  (")#"#+'#''  )& & (' # ""       + -@2  2013-2015 Microchip Technology Inc. DS40001675C-page 468 PIC16(L)F1788/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001675C-page 469  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (02/2013) Initial release. Revision B (09/2014) Change from Preliminary to Final data sheet. Corrected the following Tables: Family Types Table on page 3, Table 3-3, Table 3-8, Table 20-3, Table 22-2, Table 22-3, Table 23-1, Table 25-3, Table 30-1, Table 30-2, Table 30-3, Table 30-6, Table 30-7, Table 30-13, Table 30-14, Table 30-15, Table 30-16, Table 30-20. Corrected the following Sections: Section 3.2, Section 9.2, Section 13.3, Section 17.1.6, Section 15.1, Section 15.3, Section 17.2.5, Section 18.2, Section 18.3, Section 19.0, Section 22.6.5, Section 22.9, Section 23.0, Section 23.1, Section 24.2.4, Section 24.2.5, Section 24.2.7, Section 24.8, Section 25.0, Section 26.6.7.4, Section 30.3. Corrected the following Registers: Register 4-2, Register 8-2, Register 8-5, Register 17-3, Register 18-1, Register 24-3, Register 24-4. Corrected Equation 17-1. Corrected Figure 30-9. Removed Figure 24-21. Revision C (12/2015) Updated the following Tables: Table 1-1, Table 30-3, Table 31-17, Table 31-18. Updated the following Figures: Figure 18-1, Figure 19-1 and Figure 32-128. Updated Register 18-1 and Register 21-2. Updated the following Sections: Section 26.3.10.2, Section 28.4.2 and Section 31.1; Other minor corrections.  2013-2015 Microchip Technology Inc. DS40001675C-page 470 PIC16(L)F1788/9 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website site at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. DS40001675C-page 471  2013-2015 Microchip Technology Inc. PIC16(L)F1788/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F1788, PIC16LF1788, PIC16F1789, PIC16LF1789 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) ML MV P PT SP SO SS = = = = = = = Pattern: (Industrial) (Extended) QFN UQFN PDIP TQFP SPDIP SOIC SSOP QTP, SQTP, Code or Special Requirements (blank otherwise)  2013-2015 Microchip Technology Inc. PIC16LF1788- I/P Industrial temperature PDIP package PIC16F1789- E/SS Extended temperature, SSOP package Note 1: 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. DS40001675C-page 472 PIC16(L)F1788/9 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0058-5 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS40001675C-page 473 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2013-2015 Microchip Technology Inc. Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Germany - Dusseldorf Tel: 49-2129-3766400 Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 China - Dongguan Tel: 86-769-8702-9880 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-213-7828 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Venice Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Poland - Warsaw Tel: 48-22-3325737 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 07/14/15  2013-2015 Microchip Technology Inc. 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