PIC16F62X
Data Sheet
FLASH-Based
8-Bit CMOS Microcontroller
2003 Microchip Technology Inc.
Preliminary
DS40300C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
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use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
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Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART and PRO MATE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS40300C - page ii
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
FLASH-Based 8-Bit CMOS Microcontrollers
Devices Included in this Data Sheet:
• Universal Synchronous/Asynchronous Receiver/
Transmitter USART/SCI
• 16 Bytes of common RAM
• PIC16F627
• PIC16F628
Referred to collectively as PIC16F62X
Special Microcontroller Features:
High Performance RISC CPU:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Detect (BOD)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Multiplexed MCLR-pin
• Programmable weak pull-ups on PORTB
• Programmable code protection
• Low voltage programming
• Power saving SLEEP mode
• Selectable oscillator options
- FLASH configuration bits for oscillator
options
- ER (External Resistor) oscillator
• Reduced part count
- Dual speed INTRC
• Lower current consumption
- EC External Clock input
- XT Oscillator mode
- HS Oscillator mode
- LP Oscillator mode
• In-circuit Serial Programming™ (via two pins)
• Four user programmable ID locations
• Only 35 instructions to learn
• All single cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Memory
•
•
•
•
Device
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627
1024 x 14
224 x 8
128 x 8
PIC16F628
2048 x 14
224 x 8
128 x 8
Interrupt capability
16 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative addressing modes
Peripheral Features:
• 16 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs are externally accessible
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• Timer1: 16-bit timer/counter with external crystal/
clock capability
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM (CCP) module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
2003 Microchip Technology Inc.
CMOS Technology:
• Low power, high speed CMOS FLASH technology
• Fully static design
• Wide operating voltage range
- PIC16F627 - 3.0V to 5.5V
- PIC16F628 - 3.0V to 5.5V
- PIC16LF627 - 2.0V to 5.5V
- PIC16LF628 - 2.0V to 5.5V
• Commercial, industrial and extended temperature
range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
Preliminary
DS40300C-page 1
PIC16F62X
Pin Diagrams
PDIP, SOIC
RA5/MCLR/VPP
VSS
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
•1
2
3
4
5
6
7
8
9
PIC16F62X
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/TOCKI/CMP2
18
17
16
15
14
13
12
11
10
RA1/AN1
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5
RB4/PGM
20
19
18
17
16
15
14
13
12
11
RA1/AN1
SSOP
RA2/AN2/VREF
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
•1
2
3
4
5
6
7
8
9
10
PIC16F62X
RA3/AN3/CMP1
RA4/TOCKI/CMP2
RA5/MCLR/VPP
VSS
VSS
RB0/INT
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5
RB4/PGM
Device Differences
Device
Voltage
Range
Oscillator
Process
Technology
(Microns)
PIC16F627
3.0 - 5.5
(Note 1)
0.7
PIC16F628
3.0 - 5.5
(Note 1)
0.7
PIC16LF627
2.0 - 5.5
(Note 1)
0.7
PIC16LF628
2.0 - 5.5
(Note 1)
0.7
Note 1: If you change from this device to another device, please verify oscillator characteristics in your
application.
DS40300C-page 2
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
General Description...................................................................................................................................................................... 5
PIC16F62X Device Varieties........................................................................................................................................................ 7
Architectural Overview ................................................................................................................................................................. 9
Memory Organization ................................................................................................................................................................. 15
I/O Ports ..................................................................................................................................................................................... 29
Timer0 Module ........................................................................................................................................................................... 43
Timer1 Module ........................................................................................................................................................................... 46
Timer2 Module ........................................................................................................................................................................... 50
Comparator Module.................................................................................................................................................................... 53
Voltage Reference Module......................................................................................................................................................... 59
Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 61
Universal Synchronous/ Asynchronous Receiver/ Transmitter (USART) Module...................................................................... 67
Data EEPROM Memory ............................................................................................................................................................. 87
Special Features of the CPU...................................................................................................................................................... 91
Instruction Set Summary .......................................................................................................................................................... 107
Development Support............................................................................................................................................................... 121
Electrical Specifications............................................................................................................................................................ 127
DC and AC Characteristics Graphs and Tables....................................................................................................................... 143
Packaging Information.............................................................................................................................................................. 157
TO OUR VALUED CUSTOMERS
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2003 Microchip Technology Inc.
Preliminary
DS40300C-page 3
PIC16F62X
NOTES:
DS40300C-page 4
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
1.0
PIC16F62X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16F62X Product
Identification System section (Page 167) at the end of
this data sheet. When placing orders, please use this
page of the data sheet to specify the correct part
number.
1.1
FLASH Devices
FLASH devices can be erased and reprogrammed
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
A further advantage of the electrically-erasable FLASH
is that it can be erased and reprogrammed in-circuit, or
by device programmers, such as Microchip's
PICSTART® Plus, or PRO MATE® II programmers.
1.2
Quick-Turnaround Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a
medium-to-high quantity of units and whose code
patterns have stabilized. The devices are standard
FLASH devices but with all program locations and configuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
1.3
Serialized Quick-Turnaround
Production (SQTPsm) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 5
PIC16F62X
NOTES:
DS40300C-page 6
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
2.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16F62X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16F62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate buses. This improves
bandwidth over traditional Von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single-word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single
cycle (200 ns @ 20 MHz) except for program
branches.
The Table below lists program memory (FLASH, Data
and EEPROM).
TABLE 2-1:
DEVICE DESCRIPTION
Memory
Device
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627
1024 x 14
224 x 8
128 x 8
PIC16F628
2048 x 14
224 x 8
128 x 8
PIC16LF627
1024 x 14
224 x 8
128 x 8
PIC16LF628
2048 x 14
224 x 8
128 x 8
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 2-1, and
a description of the device pins in Table 2-1.
Two types of data memory are provided on the
PIC16F62X devices. Non-volatile EEPROM data
memory is provided for long term storage of data such
as calibration values, lookup table data, and any other
data which may require periodic updating in the field.
This data is not lost when power is removed. The other
data memory provided is regular RAM data memory.
Regular RAM data memory is provided for temporary
storage of data during normal operation. It is lost when
power is removed.
The PIC16F62X can directly or indirectly address its
register files or data memory. All Special Function
registers, including the program counter, are mapped in
the data memory. The PIC16F62X have an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation, on any register, using any
Addressing mode. This symmetrical nature, and lack of
‘special optimal situations’ make programming with the
PIC16F62X simple yet efficient. In addition, the learning
curve is reduced significantly.
The PIC16F62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 7
PIC16F62X
FIGURE 2-1:
BLOCK DIAGRAM
13
Program
Memory
RAM
File
Registers
8-Level Stack
(13-bit)
Program
Bus
14
8
Data Bus
Program Counter
FLASH
RAM Addr (1)
PORTA
9
Addr MUX
Instruction reg
Direct Addr
7
8
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
MUX
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
ALU
Power-on
Reset
8
Watchdog
Timer
Brown-out
Detect
PORTB
W reg
Low-voltage
Programming
MCLR
Comparator
Timer0
VREF
CCP1
VDD, VSS
Timer1
Timer2
USART
Data EEPROM
Note 1: Higher order bits are from the STATUS register.
DS40300C-page 8
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
TABLE 2-1:
PIC16F62X PINOUT DESCRIPTION
Name
RA0/AN0
Function
Input Type Output Type
RA0
ST
CMOS
Description
Bi-directional I/O port
AN0
AN
—
RA1/AN1
RA1
ST
CMOS
AN1
AN
—
RA2/AN2/VREF
RA2
ST
CMOS
AN2
AN
—
Analog comparator input
VREF
—
AN
VREF output
RA3
ST
CMOS
AN3
AN
—
CMP1
—
CMOS
Comparator 1 output
RA4
ST
OD
Bi-directional I/O port
T0CKI
ST
—
Timer0 clock input
CMP2
—
OD
Comparator 2 output
RA5
ST
—
Input port
MCLR
ST
—
Master clear
VPP
—
—
Programming voltage input. When configured
as MCLR, this pin is an active low RESET to
the device. Voltage on MCLR/VPP must not
exceed VDD during normal device operation.
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
Legend:
O = Output
— = Not used
TTL = TTL Input
2003 Microchip Technology Inc.
Analog comparator input
Bi-directional I/O port
Analog comparator input
Bi-directional I/O port
Bi-directional I/O port
Analog comparator input
RA6
ST
CMOS
OSC2
XTAL
—
Bi-directional I/O port
CLKOUT
—
CMOS
In ER/INTRC mode, OSC2 pin can output
CLKOUT, which has 1/4 the frequency of
OSC1
RA7
ST
CMOS
Bi-directional I/O port
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
OSC1
XTAL
—
Oscillator crystal input
CLKIN
ST
—
External clock source input. ER biasing pin.
RB0
TTL
CMOS
INT
ST
—
RB1
TTL
CMOS
Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
External interrupt.
Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
RX
ST
—
DT
ST
CMOS
Synchronous data I/O.
USART receive pin
RB2
TTL
CMOS
Bi-directional I/O port.
TX
—
CMOS
USART transmit pin
CK
ST
CMOS
Synchronous clock I/O. Can be software
programmed for internal weak pull-up.
RB3
TTL
CMOS
Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
CCP1
ST
CMOS
Capture/Compare/PWM I/O
CMOS = CMOS Output
I
= Input
OD
= Open Drain Output
Preliminary
P = Power
ST = Schmitt Trigger Input
AN = Analog
DS40300C-page 9
PIC16F62X
TABLE 2-1:
PIC16F62X PINOUT DESCRIPTION (CONTINUED)
Name
RB4/PGM
Function
Input Type Output Type
Description
RB4
TTL
CMOS
PGM
ST
—
RB5
RB5
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
RB6/T1OSO/T1CKI/PGC
RB6
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
T1OSO
—
XTAL
Timer1 oscillator output.
T1CKI
ST
—
Timer1 clock input.
PGC
ST
—
ICSP™ Programming Clock.
RB7
TTL
CMOS
T1OSI
XTAL
—
RB7/T1OSI/PGD
Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
Low voltage programming input pin. Interrupton-pin change. When low voltage programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
Timer1 oscillator input. Wake-up from SLEEP
on pin change. Can be software programmed
for internal weak pull-up.
PGD
ST
CMOS
VSS
VSS
Power
—
Ground reference for logic and I/O pins
VDD
VDD
Power
—
Positive supply for logic and I/O pins
Legend:
O = Output
— = Not used
TTL = TTL Input
DS40300C-page 10
ICSP Data I/O
CMOS = CMOS Output
I
= Input
OD
= Open Drain Output
Preliminary
P = Power
ST = Schmitt Trigger Input
AN = Analog
2003 Microchip Technology Inc.
PIC16F62X
2.1
Clocking Scheme/Instruction
Cycle
2.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change, (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 2-1).
The clock input (OSC1/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q1, Q2, Q3 and Q4.
Internally, the program counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 2-2.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 2-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC+1
PC+2
CLKOUT
Fetch INST (PC)
Execute INST (PC-1)
EXAMPLE 2-1:
2. MOVWF PORTB
SUB_1
4. BSF
PORTA, 3
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
3. CALL
Fetch INST (PC+1)
Execute INST (PC)
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 11
PIC16F62X
NOTES:
DS40300C-page 12
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
3.0
MEMORY ORGANIZATION
3.2
3.1
Program Memory Organization
The data memory (Figure 3-2) is partitioned into four
banks, which contain the general purpose registers and
the Special Function Registers (SFR). The SFR’s are
located in the first 32 locations of each Bank. Register
locations 20-7Fh, A0h-FFh, 120h-14Fh, 170h-17Fh
and 1F0h-1FFh are general purpose registers
implemented as static RAM.
The PIC16F62X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 1K x 14 (0000h - 03FFh) for the PIC16F627
and 2K x 14 (0000h - 07FFh) for the PIC16F628 are
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space (PIC16F627) or 2K x 14 space
(PIC16F628). The RESET vector is at 0000h and the
interrupt vector is at 0004h (Figure 3-1).
FIGURE 3-1:
The Table below lists how to access the four banks of
registers:
PROGRAM MEMORY MAP
AND STACK
PC
CALL, RETURN
RETFIE, RETLW
Data Memory Organization
RP1
RP0
Bank0
0
0
Bank1
0
1
Bank2
1
0
Bank3
1
1
13
Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
Stack Level 1
Stack Level 2
3.2.1
Stack Level 8
RESET Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
PIC16F627 and
PIC16F628
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 224 x 8 in the
PIC16F62X. Each is accessed either directly or
indirectly through the File Select Register FSR (See
Section 3.4).
03FFh
On-chip Program
Memory
PIC16F628 only
07FFh
1FFFh
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 13
PIC16F62X
FIGURE 3-2:
DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628
File
Address
Indirect addr.(1)
00h
Indirect addr.(1)
80h
Indirect addr.(1)
100h
Indirect addr.(1)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
04h
FSR
84h
FSR
104h
FSR
184h
PORTA
05h
TRISA
85h
PORTB
06h
TRISB
86h
PCL
PORTB
106h
185h
TRISB
186h
07h
87h
107h
187h
08h
88h
108h
188h
89h
109h
09h
PCLATH
0Ah
INTCON
0Bh
PIR1
0Ch
8Ah
10Ah
PCLATH
18Ah
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIE1
8Ch
10Ch
18Ch
8Dh
10Dh
18Dh
8Eh
10Eh
18Eh
10Fh
18Fh
PCLATH
TMR1L
0Eh
TMR1H
0Fh
8Fh
T1CON
10h
90h
TMR2
11h
T2CON
12h
PCON
91h
PR2
92h
13h
93h
14h
94h
CCPR1L
15h
95h
CCPR1H
16h
96h
CCP1CON
17h
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
99h
RCREG
1Ah
SPBRG
EEDATA
1Bh
EEADR
9Bh
1Ch
EECON1
9Ch
1Dh
EECON2(1)
9Dh
1Eh
1Fh
9Ah
9Eh
VRCON
20h
General
Purpose
Register
189h
PCLATH
0Dh
CMCON
105h
9Fh
A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
48 Bytes
11Fh
120h
14Fh
150h
80 Bytes
6Fh
70h
16 Bytes
accesses
70h-7Fh
7Fh
Bank 0
EFh
F0h
accesses
70h-7Fh
1EFh
1F0h
accesses
70h - 7Fh
17Fh
FFh
Bank 2
Bank 1
16Fh
170h
1FFh
Bank 3
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS40300C-page 14
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
3.2.2
SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of
the device (Table 3-1). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 3-1:
SPECIAL REGISTERS SUMMARY BANK 0
Bit 0
Value on
POR
Reset(1)
Details
on Page
INDF
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
xxxx xxxx
xxxx xxxx
25
43
02h
PCL
Program Counter's (PC) Least Significant Byte
03h
STATUS
04h
05h
FSR
PORTA
Indirect data memory address pointer
RA7
RA6
RA5
06h
07h
PORTB
—
RB7
RB6
Unimplemented
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bank 0
00h
01h
08h
09h
—
—
IRP
RP1
RP0
RB5
0000 0000
13
TO
PD
Z
DC
C
0001 1xxx
19
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
xxxx 0000
25
29
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
—
34
—
—
—
—
—
---0 0000
25
0000 000x
0000 -000
21
23
—
xxxx xxxx
—
46
Unimplemented
Unimplemented
0Ah
PCLATH
—
—
—
0Bh
0Ch
INTCON
PIR1
GIE
EEIF
PEIE
CMIF
T0IE
RCIF
0Dh
0Eh
—
TMR1L
Unimplemented
Holding register for the Least Significant Byte of the 16-bit TMR1
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1
10h
11h
T1CON
TMR2
—
—
T1CKPS1
TMR2 module’s register
12h
T2CON
13h
14h
—
—
15h
16h
CCPR1L
CCPR1H
17h
18h
CCP1CON
RCSTA
—
TOUTPS3
TOUTPS2
Write buffer for upper 5 bits of program counter
INTE
TXIF
RBIE
—
T0IF
CCP1IF
INTF
TMR2IF
RBIF
TMR1IF
xxxx xxxx
46
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
0000 0000
46
50
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0
-000 0000
50
—
—
—
—
xxxx xxxx
xxxx xxxx
61
61
--00 0000
0000 -00x
61
67
Unimplemented
Unimplemented
Capture/Compare/PWM register (LSB)
Capture/Compare/PWM register (MSB)
—
SPEN
—
RX9
CCP1X
SREN
CCP1Y
CREN
CCP1M3
ADEN
CCP1M2
FERR
CCP1M1
OERR
CCP1M0
RX9D
19h
TXREG
USART Transmit data register
0000 0000
74
1Ah
1Bh
RCREG
—
USART Receive data register
Unimplemented
0000 0000
—
77
—
—
—
—
—
—
0000 0000
—
53
1Ch
1Dh
1Eh
1Fh
—
—
—
CMCON
Unimplemented
Unimplemented
Unimplemented
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
Legend:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 15
PIC16F62X
TABLE 3-2:
Address
SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details on
Page
xxxx xxxx
25
1111 1111
20
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
81h
OPTION
82h
PCL
RBPU
83h
STATUS
84h
85h
FSR
TRISA
Indirect data memory address pointer
TRISA7
TRISA6
TRISA5 TRISA4
86h
87h
TRISB
—
TRISB7
TRISB6
Unimplemented
88h
—
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
89h
8Ah
—
PCLATH
8Bh
8Ch
INTCON
PIE1
IRP
RP1
RP0
TRISB5
TO
TRISB4
GIE
EEIE
PEIE
CMIE
—
T0IE
RCIE
Z
DC
C
0001 1xxx
19
TRISA3
TRISA2
TRISA1
TRISA0
xxxx xxxx
1111 1111
25
29
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
—
34
—
—
—
—
---0 0000
—
25
0000 000x
0000 -000
21
22
—
—
---- 1-0x
—
24
—
—
—
—
1111 1111
—
50
Write buffer for upper 5 bits of program counter
INTE
TXIE
25
PD
Unimplemented
Unimplemented
—
—
0000 0000
RBIE
—
T0IF
CCP1IE
INTF
TMR2IE
RBIF
TMR1IE
8Dh
—
8Eh
8Fh
PCON
—
90h
—
Unimplemented
91h
92h
—
Unimplemented
Timer2 Period Register
93h
94h
—
—
Unimplemented
Unimplemented
—
—
—
—
95h
96h
—
—
Unimplemented
Unimplemented
—
—
—
—
97h
98h
—
TXSTA
—
0000 -010
—
69
PR2
Unimplemented
—
—
Unimplemented
Unimplemented
CSRC
TX9
—
TXEN
—
SYNC
OSCF
—
—
BRGH
POR
TRMT
BOD
TX9D
99h
SPBRG
Baud Rate Generator Register
0000 0000
69
9Ah
9Bh
EEDATA
EEADR
EEPROM data register
—
EEPROM address register
xxxx xxxx
xxxx xxxx
87
87
9Ch
9Dh
EECON1
EECON2
—
—
—
—
WRERR
EEPROM control register 2 (not a physical register)
---- x000
--------
87
87
9Eh
9Fh
—
VRCON
Unimplemented
VREN
VROE
—
000- 0000
—
59
VRR
—
VR3
WREN
WR
RD
VR2
VR1
VR0
Legend:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
DS40300C-page 16
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
TABLE 3-3:
Address
SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details on
Page
xxxx xxxx
25
1111 1111
43
Bank 2
100h
INDF
101h
TMR0
102h
PCL
103h
STATUS
104h
105h
FSR
106h
107h
PORTB
—
108h
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
—
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
Unimplemented
RB7
RB6
Unimplemented
RB5
RB4
RB3
RB2
RB1
RB0
Unimplemented
109h
10Ah
—
PCLATH
Unimplemented
—
—
10Bh
10Ch
INTCON
—
GIE
PEIE
Unimplemented
—
T0IE
Write buffer for upper 5 bits of program counter
INTE
RBIE
T0IF
INTF
RBIF
0000 0000
25
0001 1xxx
19
xxxx xxxx
—
25
—
xxxx xxxx
—
34
—
—
—
—
---0 0000
—
25
0000 000x
—
21
—
10Dh
10Eh
—
—
Unimplemented
Unimplemented
—
—
—
—
10Fh
110h
—
—
Unimplemented
Unimplemented
—
—
—
—
111h
—
Unimplemented
—
—
112h
113h
—
—
Unimplemented
Unimplemented
—
—
—
—
114h
115h
—
—
Unimplemented
Unimplemented
—
—
—
—
116h
117h
—
—
Unimplemented
Unimplemented
—
—
—
—
118h
119h
—
—
Unimplemented
Unimplemented
—
—
—
—
11Ah
—
Unimplemented
—
—
11Bh
11Ch
—
—
Unimplemented
Unimplemented
—
—
—
—
11Dh
11Eh
—
—
Unimplemented
Unimplemented
—
—
—
—
11Fh
—
Unimplemented
—
—
Legend:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented.
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 17
PIC16F62X
TABLE 3-4:
Address
SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Reset(1)
Details on
Page
Bank 3
180h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
25
1111 1111
20
181h
OPTION
RBPU
182h
PCL
Program Counter's (PC) Least Significant Byte
183h
STATUS
IRP
184h
185h
FSR
Indirect data memory address pointer
Unimplemented
186h
187h
TRISB
—
188h
—
—
INTEDG
RP1
TRISB7
TRISB6
Unimplemented
T0CS
RP0
TRISB5
T0SE
TO
TRISB4
PSA
PD
TRISB3
PS2
Z
PS1
DC
TRISB2
TRISB1
PS0
C
TRISB0
Unimplemented
189h
18Ah
—
PCLATH
Unimplemented
—
—
18Bh
18Ch
INTCON
—
GIE
PEIE
Unimplemented
—
T0IE
Write buffer for upper 5 bits of program counter
INTE
RBIE
T0IF
INTF
RBIF
0000 0000
25
0001 1xxx
19
xxxx xxxx
—
25
—
1111 1111
—
34
—
—
—
—
---0 0000
—
25
0000 000x
—
21
—
18Dh
18Eh
—
—
Unimplemented
Unimplemented
—
—
—
—
18Fh
190h
—
—
Unimplemented
Unimplemented
—
—
—
—
191h
—
Unimplemented
—
—
192h
193h
—
—
Unimplemented
Unimplemented
—
—
—
—
194h
195h
—
—
Unimplemented
Unimplemented
—
—
—
—
196h
197h
—
—
Unimplemented
Unimplemented
—
—
—
—
198h
199h
—
—
Unimplemented
Unimplemented
—
—
—
—
19Ah
—
Unimplemented
—
—
19Bh
19Ch
—
—
Unimplemented
Unimplemented
—
—
—
—
19Dh
19Eh
—
—
Unimplemented
Unimplemented
—
—
—
—
19Fh
—
Unimplemented
—
—
Legend:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
DS40300C-page 18
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
3.2.2.1
STATUS Register
The STATUS register, shown in Register 3-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory (SRAM).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 3-1:
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any STATUS bit. For other instructions, not
affecting any STATUS bits, see the “Instruction Set
Summary”.
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
bit 4
TO: Timeout bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT timeout occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40300C-page 19
PIC16F62X
3.2.2.2
OPTION Register
Note:
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 3-2:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1). See Section 6.3.1
OPTION REGISTER (ADDRESS: 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS40300C-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16F62X
3.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 3.2.2.4 and Section 3.2.2.5 for a
description of the comparator enable and flag bits.
REGISTER 3-3:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40300C-page 21
PIC16F62X
3.2.2.4
PIE1 Register
This register contains interrupt enable bits.
REGISTER 3-4:
PIE1 REGISTER (ADDRESS: 8Ch)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable Bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
DS40300C-page 22
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16F62X
3.2.2.5
PIR1 Register
Note:
This register contains interrupt flag bits.
REGISTER 3-5:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0
R/W-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6
CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed
0 = Comparator output has not changed
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3
Unimplemented: Read as ‘0’
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40300C-page 23
PIC16F62X
3.2.2.6
PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR Reset,
WDT Reset or a Brown-out Detect.
REGISTER 3-6:
Note:
BOD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOD is
cleared, indicating a brown-out has
occurred. The BOD STATUS bit is a “don't
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
clearing the BODEN bit in the
Configuration word).
PCON REGISTER (ADDRESS: 0Ch)
U-0
U-0
U-0
U-0
R/W-1
U-0
R/W-q
R/W-q
—
—
—
—
OSCF
—
POR
BOD
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
OSCF: INTRC/ER oscillator frequency
1 = 4 MHz typical(1)
0 = 37 KHz typical
bit 2
Unimplemented: Read as '0'
bit 1
POR: Power-on Reset STATUS bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOD: Brown-out Detect STATUS bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: When in ER Oscillator mode, setting OSCF = 1 will cause the oscillator frequency to
change to the frequency specified by the external resistor.
Legend:
DS40300C-page 24
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16F62X
3.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 3-3 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH → PCH). The lower example in the figure shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH → PCH).
FIGURE 3-3:
12
8
7
0
8
PCLATH
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
11 10
PCL
8
7
0
GOTO, CALL
PC
2
PCLATH
11
Opcode
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actually accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a nooperation (although STATUS bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS), as
shown in Figure 3-4.
EXAMPLE 3-1:
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read” (AN556).
3.3.2
Indirect Addressing, INDF and
FSR Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 3-1.
PCLATH
3.3.1
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
3.4
PCL
PC
12
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
5
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
NEXT
movlw
movwf
clrf
incf
btfss
goto
Indirect Addressing
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
STACK
The PIC16F62X family has an 8-level deep x 13-bit
wide hardware stack (Figure 3-1 and Figure 3-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 25
PIC16F62X
FIGURE 3-4:
DIRECT/INDIRECT ADDRESSING PIC16F62X
Direct Addressing
RP1
RP0
bank select
6
from opcode
Indirect Addressing
0
IRP
7
bank select
location select
00
01
10
FSR register
0
location select
11
00h
180h
RAM
File
Registers
7Fh
1FFh
Bank 0
Note:
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 3-2.
DS40300C-page 26
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
4.0
GENERAL DESCRIPTION
The PIC16F62X are 18-Pin FLASH-based members of
the versatile PIC16CXX family of low cost, high performance, CMOS, fully static, 8-bit microcontrollers.
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC16F62X have enhanced
core features, eight-level deep stack, and multiple
internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with the separate 8bit wide data. The two-stage instruction pipeline allows
all instructions to execute in a single cycle, except for
program branches (which require two cycles). A total of
35 instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance.
PIC16F62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
PIC16F62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power consumption.
The PIC16F62X has eight oscillator configurations.
The single pin ER oscillator provides a low cost solution. The LP oscillator minimizes power consumption,
XT is a standard crystal, INTRC is a self-contained
internal oscillator. The HS is for High Speed crystals.
The EC mode is for an external clock source.
TABLE 4-1:
Clock
Memory
Table 4-1 shows the features of the PIC16F62X midrange microcontroller families.
A simplified block diagram of the PIC16F62X is shown
in Figure 2.1.
The PIC16F62X series fits in applications ranging from
battery chargers to low power remote sensors. The
FLASH technology makes customization of application
programs (detection levels, pulse generation, timers,
etc.) extremely fast and convenient. The small footprint
packages make this microcontroller series ideal for all
applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC16F62X very versatile.
4.1
Development Support
The PIC16F62X family is supported by a full featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer. A Third Party “C” compiler
support tool is also available.
PIC16F627
PIC16F628
PIC16LF627
PIC16LF628
Maximum Frequency of Operation
(MHz)
20
20
4
4
FLASH Program Memory (words)
1024
2048
1024
2048
RAM Data Memory (bytes)
224
224
224
224
EEPROM Data Memory (bytes)
128
128
128
128
TMR0, TMR1, TMR2
TMR0, TMR1, TMR2
TMR0, TMR1, TMR2
TMR0, TMR1, TMR2
Comparator(s)
2
2
2
2
Capture/Compare/PWM modules
1
1
1
1
USART
USART
USART
USART
Internal Voltage Reference
Yes
Yes
Yes
Yes
Interrupt Sources
10
10
10
10
I/O Pins
16
16
16
16
3.0-5.5
3.0-5.5
2.0-5.5
2.0-5.5
Serial Communications
Features
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
PIC16F62X FAMILY OF DEVICES
Timer Module(s)
Peripherals
The SLEEP (Power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
several external interrupts, internal interrupts, and
RESETS.
Voltage Range (Volts)
Brown-out Detect
Packages
Yes
Yes
Yes
Yes
18-pin DIP, SOIC,
20-pin SSOP
18-pin DIP, SOIC,
20-pin SSOP
18-pin DIP, SOIC,
20-pin SSOP
18-pin DIP, SOIC,
20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All
PIC16F62X Family devices use serial programming with clock pin RB6 and data pin RB7.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 27
PIC16F62X
NOTES:
DS40300C-page 28
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
5.0
I/O PORTS
The PIC16F62X have two ports, PORTA and PORTB.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1
2: TRISA is overridden by oscillator
configuration. When PORTA is
overridden, the data reads ‘0’ and the
TRISA bits are ignored.
PORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. RA5 is a Schmitt Trigger
input only and has no output drivers. All other RA port
pins have Schmitt Trigger input levels and full CMOS
output drivers. All pins have data direction bits (TRIS
registers) which can configure these pins as input or
output.
A '1' in the TRISA register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the
selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.
Note:
Note 1: On RESET, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to
ground to reduce current consumption.
RA5 shares function with VPP. When VPP
voltage levels are applied to RA5, the
device will enter Programming mode.
2003 Microchip Technology Inc.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high impedance output. The user must configure
TRISA bit as an input and use high impedance
loads.
In one of the Comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
CLRF
PORTA
MOVLW 0x07
MOVWF CMCON
Initializing PORTA
;Initialize PORTA by
;setting output data latches
;Turn comparators off and
;enable pins for I/O
;functions
BCF
STATUS, RP1
BSF
STATUS, RP0;Select Bank1
MOVLW 0x1F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA as inputs
;TRISA always
;read as ‘1’.
;TRISA
;depend on oscillator mode
Preliminary
DS40300C-page 29
PIC16F62X
FIGURE 5-1:
Data
Bus
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
D
WR
PORTA
Data
Bus
Q
CK
FIGURE 5-2:
D
VDD
WR
PORTA
Q
BLOCK DIAGRAM OF
RA2/VREF PIN
Q
CK
Q
Data Latch
Data Latch
D
D
WR
TRISA
Q
CK
VDD
Q
I/O Pin
RA2 Pin
WR
TRISA
Q
TRIS Latch
CK
Q
VSS
TRIS Latch
VSS
Analog
Input Mode
Analog
Input Mode
RD
TRISA
Schmitt Trigger
Input Buffer
Schmitt Trigger
Input Buffer
RD
TRISA
Q
Q
D
D
EN
EN
RD PORTA
RD PORTA
To Comparator
To Comparator
VROE
VREF
FIGURE 5-3:
Data
Bus
BLOCK DIAGRAM OF THE RA3/AN3 PIN
Comparator Mode = 110
D
VDD
Q
Comparator Output
WR
PORTA
1
CK
Q
Data Latch
D
0
Q
RA3 Pin
WR
TRISA
CK
Q
VSS
TRIS Latch
Analog
Input Mode
RD
TRISA
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
DS40300C-page 30
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
FIGURE 5-4:
Data
Bus
BLOCK DIAGRAM OF RA4/T0CKI PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
PORTA
VDD
1
CK
Q
0
Data Latch
D
Q
RA4 Pin
N
WR
TRISA
CK
Q
Vss
TRIS Latch
Vss
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
FIGURE 5-5:
BLOCK DIAGRAM OF THE
FIGURE 5-6:
BLOCK DIAGRAM OF
RA6/OSC2/CLKOUT PIN
RA5/MCLR/VPP PIN
From OSC1
OSC
Circuit
VDD
CLKOUT(FOSC/4)
1
MCLRE
MCLR
circuit
MCLR Filter
Q
0
CK
Q
(FOSC =
Data
Latch
(2)
101, 111)
Schmitt Trigger
Input Buffer
Program
mode
D
WR
PORTA
VSS
HV Detect
RA5/MCLR/VPP
D
WR
TRISA
Data
Bus
CK
VSS
Q
Q
TRIS Latch
RD
TRISA
RD
TRISA
FOSC =
100, 110
VSS
Schmitt
Trigger
Input Buffer
(1)
Q
Q
D
EN
RD
PORTA
2003 Microchip Technology Inc.
D
EN
RD PORTA
Note
Preliminary
1:
2:
INTRC with RA6 = I/O or ER with RA6 = I/O.
INTRC with RA6 = CLKOUT or ER with RA6 = CLKOUT.
DS40300C-page 31
PIC16F62X
FIGURE 5-7:
BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
To OSC2
Oscillator
Circuit
VDD
CLKIN to core
Data Bus
D
WR PORTA
Q
RA7/OSC1/CLKIN Pin
CK
Q
Data Latch
D
WR TRISA
CK
VSS
Q
Q
TRIS Latch
RD TRISA
FOSC = 100, 101(1)
Q
D
Schmitt Trigger
Input Buffer
EN
RD PORTA
Note
1:
DS40300C-page 32
INTRC with CLKOUT, and INTRC with I/O.
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
TABLE 5-1:
PORTA FUNCTIONS
Name
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CKI/CMP2
RA5/MCLR/VPP
Functio
n
Input
Type
Output
Type
RA0
AN0
RA1
AN1
RA2
AN2
VREF
RA3
AN3
CMP1
RA4
T0CKI
ST
AN
ST
AN
ST
AN
—
ST
AN
—
ST
ST
CMOS
—
CMOS
—
CMOS
—
AN
CMOS
—
CMOS
OD
—
CMP2
—
OD
RA5
ST
—
Bi-directional I/O port
Analog comparator input
Bi-directional I/O port
Analog comparator input
Bi-directional I/O port
Analog comparator input
VREF output
Bi-directional I/O port
Analog comparator input
Comparator 1 output
Bi-directional I/O port
External clock input for TMR0 or comparator output. Output
is open drain type
Comparator 2 output
Input port
MCLR
ST
—
Master clear
Description
Programming voltage input. When configured as MCLR,
this pin is an active low RESET to the device. Voltage on
MCLR/VPP must not exceed VDD during normal device
operation
RA6/OSC2/CLKOUT
RA6
ST
CMOS Bi-directional I/O port.
OSC2
XTAL
—
Oscillator crystal output. Connects to crystal resonator in
Crystal Oscillator mode.
CLKOUT
—
CMOS In ER/INTRC mode, OSC2 pin can output CLKOUT, which
has 1/4 the frequency of OSC1
RA7/OSC1/CLKIN
RA7
ST
CMOS Bi-directional I/O port
OSC1
XTAL
—
Oscillator crystal input
CLKIN
ST
—
External clock source input. ER biasing pin.
Legend: ST = Schmitt Trigger input
HV = High Voltage
OD = Open Drain
AN = Analog
VPP
2003 Microchip Technology Inc.
HV
—
Preliminary
DS40300C-page 33
PIC16F62X
TABLE 5-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
RA5
RA4
05h
PORTA
RA7
RA6
85h
TRISA
TRISA7
TRISA6
TRISA5 TRISA4
1Fh
CMCON
C2OUT
C1OUT
C2INV
9Fh
VRCON
VREN
VROE
VRR
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
xxxu 0000
RA3
RA2
RA1
RA0
xxxx 0000
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
C1INV
CIS
CM2
CM1
CM0
0000 0000
0000 0000
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note 1: Shaded bits are not used by PORTA.
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a Hi-impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR1 clock input/output.
The standard port functions and the alternate port
functions are shown in Table 5-3. Alternate port
functions override TRIS setting when enabled.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552)
Note:
If a change on the I/O pin should occur
when a read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB pin configured as an output is excluded from the interrupt-onchange comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
DS40300C-page 34
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
FIGURE 5-8:
BLOCK DIAGRAM OF
RB0/INT PIN
FIGURE 5-9:
BLOCK DIAGRAM OF
RB1/RX/DT PIN
VDD
VDD
RBPU
RBPU
P Weak Pull-up
PORT/PERIPHERAL
Weak
P Pull-up
VDD
Select(1)
VDD
USART Data Output
Data Bus
WR PORTB
D
WR TRISB
CK
D
Q
WR PORTB
CK
Q
Q
Data Latch
D
Data Bus
Q
RB0/INT
CK
0
WR TRISB
Q
Peripheral OE(2)
TRIS Latch
RB1/
RX/DT
VSS
Data Latch
VSS
Q
1
D
Q
CK
Q
TRIS Latch
TTL
Input
Buffer
RD TRISB
TTL
Input
Buffer
RD TRISB
Q
Q
D
EN
D
RD PORTB
EN
EN
USART Receive Input
RD PORTB
Schmitt
Trigger
INT
Schmitt
Trigger
2003 Microchip Technology Inc.
Note
1:
2:
Preliminary
Port/Peripheral select signal selects between port
data and peripheral output.
Peripheral OE (output enable) is only active if
peripheral select is active.
DS40300C-page 35
PIC16F62X
FIGURE 5-10:
BLOCK DIAGRAM OF
RB2/TX/CK PIN
VDD
Weak
P Pull-up
VDD
RBPU
PORT/PERIPHERAL Select(1)
USART TX/CK Output
D
Q
WR PORTB
CK
Q
RB2/
TX/CK
1
Q
CK
Q
WR TRISB
PORT/PERIPHERAL Select(1)
0
Data Bus
D
Q
WR PORTB
CK
Q
TRIS Latch
Peripheral OE(2)
TTL
Input
Buffer
RD TRISB
D
Q
CK
Q
VSS
TRIS Latch
TTL
Input
Buffer
RD TRISB
D
Q
EN
RD PORTB
EN
USART Slave Clock In
Schmitt
Trigger
1:
2:
D
RD PORTB
USART Slave Clock In
Note
RB3/
CCP1
1
Data Latch
WR TRISB
Q
VDD
Weak
P Pull-up
VDD
RBPU
VSS
Data Latch
D
BLOCK DIAGRAM OF
RB3/CCP1 PIN
USART TX/CK output
0
Data Bus
Peripheral OE(2)
FIGURE 5-11:
Port/Peripheral select signal selects between port
data and peripheral output.
Peripheral OE (output enable) is only active if
peripheral select is active.
DS40300C-page 36
Schmitt
Trigger
Note
1:
2:
Preliminary
Port/Peripheral select signal selects between port
data and peripheral output.
Peripheral OE (output enable) is only active if
peripheral select is active.
2003 Microchip Technology Inc.
PIC16F62X
FIGURE 5-12:
BLOCK DIAGRAM OF RB4/PGM PIN
VDD
RBPU
P weak pull-up
Data Bus
WR PORTB
D
Q
CK
Q
VDD
Data Latch
WR TRISB
D
Q
CK
Q
RB4/PGM
VSS
TRIS Latch
RD TRISB
LVP
RD PORTB
PGM input
TTL
input
buffer
Schmitt
Trigger
Q
D
EN
Q1
Set RBIF
Q
From other
RB pins
D
Q3
EN
Note 1: The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 37
PIC16F62X
FIGURE 5-13:
BLOCK DIAGRAM OF RB5 PIN
VDD
RBPU
weak VDD
P pull-up
Data Bus
D
Q
CK
Q
RB5 pin
WR PORTB
Data Latch
VSS
D
Q
CK
Q
WR TRISB
TRIS Latch
TTL
input
buffer
RD TRISB
Q
D
RD PORTB
EN
Q1
Set RBIF
Q
From other
RB pins
D
Q3
EN
DS40300C-page 38
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
FIGURE 5-14:
BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN
VDD
RBPU
P weak pull-up
Data Bus
WR PORTB
D
Q
CK
Q
VDD
Data Latch
WR TRISB
D
Q
CK
Q
RB6/
T1OSO/
T1CKI
pin
VSS
TRIS Latch
RD TRISB
T1OSCEN
TTL
input
buffer
RD PORTB
TMR1 Clock
From RB7
Schmitt
Trigger
TMR1 oscillator
Serial programming clock
Q
D
EN
Set RBIF
From other
RB pins
Q
D
Q3
EN
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 39
PIC16F62X
FIGURE 5-15:
BLOCK DIAGRAM OF THE RB7/T1OSI PIN
VDD
RBPU
P weak pull-up
TMR1 oscillator
To RB6
VDD
Data Bus
WR PORTB
D
Q
CK
Q
RB7/T1OSI
pin
Data Latch
WR TRISB
D
Q
CK
Q
VSS
TRIS Latch
RD TRISB
T10SCEN
TTL
input
buffer
RD PORTB
Serial programming input
Schmitt
Trigger
Q
D
EN
Set RBIF
From other
RB pins
Q
D
EN
DS40300C-page 40
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
TABLE 5-3:
PORTB FUNCTIONS
Name
Function Input Type
Output
Type
RB0/INT
RB0
TTL
CMOS
RB1/RX/DT
INT
RB1
ST
TTL
—
CMOS
RB2/TX/CK
RX
DT
RB2
TX
CK
RB3/CCP1
RB3
RB4/PGM
CCP1
RB4
RB5
RB6/T1OSO/T1CKI/
PGC
RB6
T1OSO
T1CKI
PGC
RB7
RB7/T1OSI/PGD
T1OSI
PGD
Legend:
O = Output
— = Not used
TTL = TTL Input
TABLE 5-4:
Address
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
External interrupt.
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
ST
—
USART Receive Pin
ST
CMOS
Synchronous data I/O
TTL
CMOS
Bi-directional I/O port
—
CMOS
USART Transmit Pin
ST
CMOS
Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
ST
CMOS
Capture/Compare/PWM/I/O
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
ST
—
Low voltage programming input pin. Interrupt-on-pin
change. When low voltage programming is enabled, the
interrupt-on-pin change and weak pull-up resistor are
disabled.
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
—
XTAL
Timer1 Oscillator Output
ST
—
Timer1 Clock Input
ST
—
ICSP Programming Clock
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
XTAL
—
Timer1 Oscillator Input
ST
CMOS
ICSP Data I/O
CMOS = CMOS Output
P = Power
I
= Input
ST = Schmitt Trigger Input
OD
= Open Drain Output
AN = Analog
PGM
RB5
Description
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB(1)
Name
Bit 7
Bit 6
06h, 106h PORTB
RB7
RB6
86h, 186h TRISB
TRISB7
TRISB6
RBPU
INTEDG
81h, 181h OPTION
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
1111 1111
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: u = unchanged, x = unknown
Note 1: Shaded bits are not used by PORTB.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 41
PIC16F62X
5.3
I/O Programming Considerations
5.3.1
EXAMPLE 5-2:
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on Bit 5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
Bit 5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., Bit 0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the Input mode, no problem occurs. However,
if Bit 0 is switched into Output mode later on, the
content of the data latch may now be unknown.
Reading a port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-2 shows the effect of two sequential readmodify-write instructions (ex., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
FIGURE 5-16:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORT settings:PORTB Inputs
;
;
PORTB Outputs
;PORTB have external pull-up and are not
;connected to other circuitry
;
;
PORT latchPORT Pins
---------- ---------BCF STATUS, RP0
;
BCF PORTB, 7
;01pp pppp 11pp pppp
BSF STATUS, RP0
;
BCF TRISB, 7
;10pp pppp 11pp pppp
BCF TRISB, 6
;10pp pppp 10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
5.3.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 516). Therefore, care must be exercised if a write
followed by a read operation is carried out on the same
I/O port. The sequence of instructions should be such
to allow the pin voltage to stabilize (load dependent)
before the next instruction which causes that file to be
read into the CPU is executed. Otherwise, the previous
state of that pin may be read into the CPU rather than
the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
PC
MOWF PORTB
Write to PORTB
PC + 1
MOWF PORTB, W
Read to PORTB
PC + 2
NOP
PC + 3
NOP
Port pin
sampled here
TPD
Execute
MOVWF
PORTB
Note
1:
2:
Execute
MOVWF
PORTB
Execute
NOP
This example shows write to PORTB followed by a read from PORTB.
Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.
Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS40300C-page 42
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
6.0
TIMER0 MODULE
6.2
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Timer mode is selected by clearing the T0CS bit
(OPTION). In Timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles. The user can work around this by writing an
adjusted value to TMR0.
Counter mode is selected by setting the T0CS bit. In
this mode Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
bit (OPTION). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4,..., 1:256 are
selectable. Section 6.3 details the operation of the
prescaler.
6.1
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
Figure 6-1 is a simplified block diagram of the Timer0
module. Additional information available in the
PICmicro™ Mid-Range MCU Family Reference
Manual, DS31010A.
Using Timer0 with External Clock
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-1). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device. See Table 17-7.
TIMER0 Interrupt
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON). The T0IF bit
(INTCON) must be cleared in software by the
Timer0 module interrupt service routine before reenabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 43
PIC16F62X
6.3
Timer0 Prescaler
The PSA and PS2:PS0 bits (OPTION) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. A prescaler assignment for the Timer0 module
means that there is no postscaler for the Watchdog
Timer, and vice-versa.
FIGURE 6-1:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction
will clear the prescaler along with the Watchdog Timer.
The prescaler is not readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT
Data Bus
FOSC/4
8
0
1
T0CKI
Pin
SYNC
2
Cycles
1
0
T0SE
T0CS
Set Flag Bit T0IF
on Overflow
PSA
Watchdog
Timer
0
WDT Postscaler/
TMR0 Prescaler
1
8
8-to-1MUX
PSA
WDT Enable bit
0
1
TMR0 reg
PS0 - PS2
PSA
WDT
Timeout
Note 1: T0SE, T0CS, PSA, .PS0-PS2 are bits in the Option Register.
DS40300C-page 44
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
6.3.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). Use the instruction sequences,
shown in Example 6-1, when changing the prescaler
assignment from Timer0 to WDT, to avoid an
unintended device RESET.
EXAMPLE 6-1:
BCF
CLRWDT
CLRF
BSF
MOVLW
TMR0
STATUS, RP0
'00101111’b
MOVWF
OPTION_REG
CLRWDT
MOVLW
MOVWF
BCF
'00101xxx’b
OPTION_REG
STATUS, RP0
Address
01h
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
CHANGING PRESCALER
(TIMER0→WDT)
STATUS, RP0
TABLE 6-1:
To change prescaler from the WDT to the TMR0
module use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
;Skip if already in
;Bank 0
;Clear WDT
;Clear TMR0 & Prescaler
;Bank 1
;These 3 lines
;(5, 6, 7)
;are required only
;if desired PS
;are
;000 or 001
;Set Postscaler to
;desired WDT rate
;Return to Bank 0
;Clear WDT and
;prescaler
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
MOVWF
BCF
OPTION_REG
STATUS, RP0
;Select TMR0, new
;prescale value and
;clock source
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
0Bh/8Bh/
INTCON
10Bh/18Bh
81h, 181h
OPTION(2)
85h
TRISA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module register
Value on
POR
Value on
All Other
RESETS
xxxx xxxx uuuu uuuu
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
TRISA2
TRISA1
TRISA7
TRISA6 TRISA5 TRISA4 TRISA3
TRISA0 1111 1111 1111 1111
Legend:
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note 1: Shaded bits are not used by TMR0 module.
2: Option is referred by OPTION_REG in MPLAB.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 45
PIC16F62X
7.0
TIMER1 MODULE
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON).
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit TMR1IF (PIR1). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1).
Timer1 can operate in one of two modes:
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON).
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 11.0). Register 7-1 shows the Timer1 Control
register.
For the PIC16F627 and PIC16F628, when the Timer1
oscillator is enabled (T1OSCEN is set), the RB7/T1OSI
and RB6/T1OSO/T1CKI pins become inputs. That is,
the TRISB value is ignored.
• As a timer
• As a counter
REGISTER 7-1:
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
U-0
—
—
R/W-0
R/W-0
T1CKPS1 T1CKPS0
R/W-0
T1OSCEN
R/W-0
R/W-0
R/W-0
T1SYNC TMR1CS TMR1ON
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off(1)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Disables Timer1
0 = Stops Timer1
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:
DS40300C-page 46
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16F62X
7.1
Timer1 Operation in Timer Mode
7.2.1
Timer mode is selected by clearing the TMR1CS
(T1CON) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON) has no effect since the internal clock is
always in sync.
7.2
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode the timer increments on every rising edge of
clock input on pin RB7/T1OSI when bit T1OSCEN is
set or pin RB6/T1OSO/T1CKI when bit T1OSCEN is
cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The
prescaler however will continue to increment.
FIGURE 7-1:
EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
When an external clock input is used for Timer1 in
Synchronized Counter mode, it must meet certain
requirements. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
is a delay in the actual incrementing of TMR1 after
synchronization.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the appropriate electrical specifications, parameters 45, 46, and 47.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripplecounter type prescaler so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple-counter must be
taken into account. Therefore, it is necessary for T1CKI
to have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of 10
ns). Refer to the appropriate electrical specifications,
parameters 40, 42, 45, 46, and 47.
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
TMR1H
Synchronized
0
TMR1
Clock Input
TMR1L
1
TMR1ON
T1SYNC
T1OSC
RB6/T1OSO/T1CKI
1
T1OSCEN
Enable
Oscillator(1)
RB7/T1OSI
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note
1:
When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 47
PIC16F62X
7.3
Timer1 Operation in
Asynchronous Counter Mode
EXAMPLE 7-1:
If control bit T1SYNC (T1CON) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow which will wake-up
the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.2).
In Asynchronous Counter mode, Timer1 can not be
used as a time-base for capture or compare
operations.
7.3.1
EXTERNAL CLOCK INPUT TIMING
WITH UNSYNCHRONIZED CLOCK
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high-time and low-time requirements.
Refer to the appropriate Electrical Specifications
section, Timing Parameters 45, 46, and 47.
7.3.2
READING A 16-BIT FREERUNNING TIMER
; All interrupts
MOVF
TMR1H,
MOVWF TMPH
MOVF
TMR1L,
MOVWF TMPL
MOVF
TMR1H,
SUBWF TMPH,
BTFSC
GOTO
are disabled
W ;Read high byte
;
W ;Read low byte
;
W ;Read high byte
W ;Sub 1st read
; with 2nd read
STATUS,Z ;Is result = 0
CONTINUE ;Good 16-bit read
;
; TMR1L may have rolled over between the read
; of the high and low bytes. Reading the high
; and low bytes now will read a good value.
;
MOVF
TMR1H, W ;Read high byte
MOVWF TMPH
;
MOVF
TMR1L, W ;Read low byte
MOVWF TMPL
;
; Re-enable the Interrupts (if required)
CONTINUE
;Continue with your code
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running,
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Example 7-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
DS40300C-page 48
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
7.4
Timer1 Oscillator
7.5
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 7-1 shows the capacitor
selection for the Timer1 oscillator.
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
Note:
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 7-1:
Osc Type
C1
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Freq
Resetting Timer1 Using a CCP
Trigger Output
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
C2
In this mode of operation, the CCPRxH:CCPRxL
registers pair effectively becomes the period register
for Timer1.
LP
32 kHz
33 pF
33 pF
100 kHz
15 pF
15 pF
200 kHz
15 pF
15 pF
Note 1: These values are for design guidance only.
Consult AN826 (DS00826A) for further
information on Crystal/Capacitor Selection.
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other RESET except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
0Bh/8Bh/
10Bh/18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
--00 0000
--uu uuuu
Legend:
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 49
PIC16F62X
8.0
TIMER2 MODULE
8.1
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON).
The Timer2 module has an 8-bit Period Register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1)).
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON) to minimize power consumption.
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 8-1:
Sets flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
output (1)
RESET
Register 8-1 shows the Timer2 Control register.
Postscaler
1:1 to 1:16
EQ
TMR2 reg
Comparator
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
T2CKPS
4
PR2 reg
TOUTPS
Note
DS40300C-page 50
Preliminary
1:
TMR2 register output can be software selected by the
SSP Module as a baud clock.
2003 Microchip Technology Inc.
PIC16F62X
REGISTER 8-1:
T2CON: TIMER CONTROL REGISTER (ADDRESS: 12h)
U-0
R/W-0
—
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1
R/W-0
R/W-0
TOUTPS0
R/W-0
R/W-0
TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale Value
0001 = 1:2 Postscale Value
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = 1:1 Prescaler Value
01 = 1:4 Prescaler Value
1x = 1:16 Prescaler Value
Legend:
TABLE 8-1:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Value on
all other
POR
RESETS
0000 000x 0000 000u
0Bh/8Bh/
10Bh/18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000 0000 -000
TMR1IE
0000 -000 0000 -000
8Ch
PIE1
11h
TMR2
12h
T2CON
92h
PR2
Legend:
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
0000 0000 0000 0000
Timer2 module’s register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
T2CKPS0 -000 0000 -000 0000
1111 1111 1111 1111
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 51
PIC16F62X
NOTES:
DS40300C-page 52
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
9.0
COMPARATOR MODULE
The Comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The Onchip Voltage Reference (Section 10.0) can also be an
input to the comparators.
REGISTER 9-1:
The CMCON register, shown in Register 9-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 9-1.
CMCON REGISTER (ADDRESS: 01Fh)
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
bit 7
bit 7
bit 0
C2OUT: Comparator 2 Output
When C2INV = 0:
1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1:
1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output
When C1INV = 0:
1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1:
1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN-
bit 5
C2INV: Comparator 2 Output Inversion
1 = C2 Output inverted
0 = C2 Output not inverted
bit 4
C1INV: Comparator 1 Output Inversion
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3
CIS: Comparator Input Switch
When CM2:CM0: = 001
Then:
1 = C1 VIN- connects to RA3
0 = C1 VIN- connects to RA0
When CM2:CM0 = 010
Then:
1 = C1 VIN- connects to RA3
C2 VIN- connects to RA2
0 = C1 VIN- connects to RA0
C2 VIN- connects to RA1
bit 2-0
CM2:CM0: Comparator Mode
Figure 9-1 shows the Comparator modes and CM2:CM0 bit settings
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40300C-page 53
PIC16F62X
9.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 9-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
FIGURE 9-1:
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 17-1.
Note:
Comparator interrupts should be disabled
during a Comparator mode change otherwise a false interrupt may occur.
COMPARATOR I/O OPERATING MODES
Comparators Off
CM2:CM0 = 111
Comparators Reset (POR Default Value)
CM2:CM0 = 000
RA0/AN0
A
VIN-
RA3/AN3/CMP1
A
VIN+
RA1/AN1
A
VIN-
RA2/AN2
A
VIN+
C1
Off (Read as '0')
RA0/AN0
D
VIN-
RA3/AN3/CMP1
D
VIN+
D
VIN-
D
VIN+
RA1/AN1
C2
Off (Read as '0')
RA2/AN2
C1
Off (Read as '0')
C2
Off (Read as '0')
VSS
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 010
Two Independent Comparators
CM2:CM0 = 100
VIN+
A
RA3/AN3/CMP1
RA0/AN0
VIN-
A
RA0/AN0
RA1/AN1
A
VIN-
RA2/AN2
A
VIN+
C1
C2
C1VOUT
A
CIS = 0
CIS = 1
RA3/AN3/CMP1 A
RA1/AN1
A
RA2/AN2
A
CIS = 0
CIS = 1
C2VOUT
VINVIN+
C1
C1VOUT
C2
C2VOUT
VINVIN+
From VREF
Module
Two Common Reference Comparators
CM2:CM0 = 011
RA0/AN0
VIN+
RA1/AN1
A
VIN-
RA2/AN2
A
VIN+
A
VIN-
RA3/AN3/CMP1
D
VIN+
RA1/AN1
A
VIN-
RA2/AN2/CMP2
A
VIN+
RA0/AN0
VIN-
A
D
RA3/AN3/CMP1
Two Common Reference Comparators with Outputs
CM2:CM0 = 110
C1
C2
C1VOUT
C2VOUT
D
VIN-
RA3/AN3/CMP1 D
VIN+
RA0/AN0
C1
Off (Read as '0')
VSS
RA1/AN1
RA2/AN2
A
VIN-
A
VIN+
C1VOUT
C2
C2VOUT
Open Drain
RA4/T0CKI/C20
One Independent Comparator
CM2:CM0 = 101
C1
Three Inputs Multiplexed to Two Comparators
CM2:CM0 = 001
This mode is disfunctional and has been corrected in the ‘A’
Revision Devices.
A
RA0/AN0
VINCIS = 0
CIS = 1
RA3/AN3/CMP1 A
C1VOUT
C1
VIN+
+
C2
C2VOUT
RA1/AN1
A
VIN-
RA2/AN2
A
VIN+
+
C2
C2VOUT
A = Analog Input, port reads zeros always.
D = Digital Input.
CIS (CMCON) is the Comparator Input Switch.
DS40300C-page 54
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
The code example in Example 9-1 depicts the steps
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 9-1:
FLAG_REG
CLRF
CLRF
MOVF
ANDLW
IORWF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
FIGURE 9-2:
SINGLE COMPARATOR
ViN+
+
VIN-
–
Result
INITIALIZING
COMPARATOR MODULE
EQU
FLAG_REG
PORTA
CMCON, W
0xC0
FLAG_REG,F
0x03
CMCON
STATUS,RP0
0x07
TRISA
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
0X20
;Init flag register
;Init PORTA
;Load comparator bits
;Mask comparator bits
;Store bits in flag register
;Init comparator mode
;CM = 011
;Select Bank1
;Initialize data direction
;Set RA as inputs
;RA as outputs
;TRISA always read ‘0’
STATUS,RP0 ;Select Bank 0
DELAY10
;10µs delay
CMCON,F
;Read CMCON to end change condition
PIR1,CMIF
;Clear pending interrupts
STATUS,RP0 ;Select Bank 1
PIE1,CMIE
;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
9.2
Comparator Operation
VINVIN+
Result
9.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the
comparators operate from the same or different
reference sources. However, threshold detector
applications may require the same reference. The
reference signal must be between VSS and VDD, and
can be applied to either pin of the comparator(s).
9.3.2
INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 9-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 9-2 represent
the uncertainty due to input offsets and response time.
The Comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 10.0, Voltage Reference Manual,
contains a detailed description of the Voltage Reference module that provides this signal. The internal
reference signal is used when the comparators are in
mode CM=010 (Figure 9-1). In this mode, the
internal voltage reference is applied to the VIN+ pin of
both comparators.
9.3
9.4
Comparator Reference
An external or internal reference signal may be used
depending on the Comparator Operating mode. The
analog signal that is present at VIN- is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 9-2).
2003 Microchip Technology Inc.
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise the
maximum delay of the comparators should be used
(Table 17-1).
Preliminary
DS40300C-page 55
PIC16F62X
9.5
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM = 110, multiplexors in the
output path of the RA3 and RA4/T0CK1 pins will switch
and the output of each pin will be the unsynchronized
output of the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications. Figure 93 shows the comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4/T0CK1 pins while in this
mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is
specified.
FIGURE 9-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
CnINV
To RA3 or RA4/T0CK1 pin
CnVOUT
To Data Bus
CMCON
Q
D
EN
RD CMCON
Q
Set CMIF bit
D
Q1
EN
CL
From other Comparator
DS40300C-page 56
RESET
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
9.6
Comparator Interrupts
9.7
The Comparator Interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that has occurred. The
CMIF bit, PIR1, is the Comparator Interrupt Flag.
The CMIF bit must be RESET by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
The CMIE bit (PIE1) and the PEIE bit
(INTCON) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1)
interrupt flag may not get set.
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Any write or read of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
2003 Microchip Technology Inc.
Comparator Operation During
SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake-up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM = 111, before entering SLEEP.
If the device wakes-up from SLEEP, the contents of the
CMCON register are not affected.
9.8
Effects of a RESET
A device RESET forces the CMCON register to its
RESET state. This forces the Comparator module to be
in the comparator RESET mode, CM2:CM0 = 000.
This ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered-down during the RESET interval.
9.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 9-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup may occur. A
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Preliminary
DS40300C-page 57
PIC16F62X
FIGURE 9-4:
ANALOG INPUT MODE
VDD
VT = 0.6V
RS < 10K
AIN
CPIN
5 pF
VA
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
CPIN
VT
ILEAKAGE
RIC
RS
VA
Legend
TABLE 9-1:
Address
1Fh
= Input Capacitance
= Threshold Voltage
= Leakage Current At The Pin
= Interconnect Resistance
= Source Impedance
= Analog Voltage
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
CMCON
Bit 7
Bit 6
C2OUT C1OUT
Value on
POR
Value on
All Other
RESETS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C2INV
C1NV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
T0IF
INTF
RBIF
0000 000x 0000 000u
0Bh/8Bh/
INTCON
10Bh/18Bh
GIE
PEIE
T0IE
INTE
RBIE
0Ch
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
PIR1
8Ch
PIE1
85h
TRISA
Legend:
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2
TRISA1
TRISA0 1111 1111 1111 1111
x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’
DS40300C-page 58
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
10.0
VOLTAGE REFERENCE
MODULE
10.1
The Voltage Reference can output 16 distinct voltage
levels for each range.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Figure 10-1. The block diagram
is given in Figure 10-1.
REGISTER 10-1:
Configuring the Voltage Reference
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR/32) x
VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 17-2). Example 10-1 shows an example of how
to configure the Voltage Reference for an output
voltage of 1.25V with VDD = 5.0V.
VRCON REGISTER (ADDRESS: 9Fh)
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
VREN: VREF Enable
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5
VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4
Unimplemented: Read as '0'
bit 3-0
VR: VREF value selection 0 ≤ VR [3:0] ≤ 15
When VRR = 1: VREF = (VR/ 24) * VDD
When VRR = 0: VREF = 1/4 * VDD + (VR/ 32) * VDD
Legend:
FIGURE 10-1:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
VREN
16 Stages
8R
R
R
R
R
8R
Vrr
VSS
VSS
Vr3
Vref
(From VRCON)
16-1 Analog Mux
Vr0
Note
1:
R is defined in Table 17-2.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 59
PIC16F62X
EXAMPLE 10-1:
10.4
VOLTAGE REFERENCE
CONFIGURATION
MOVLW
0x02
; 4 Inputs Muxed
MOVWF
BSF
CMCON
STATUS,RP0
; to 2 comps.
; go to Bank 1
MOVLW
MOVWF
0x07
TRISA
; RA3-RA0 are
; outputs
MOVLW
0xA6
; enable VREF
MOVWF
VRCON
; low range
A device RESET disables the Voltage Reference by
clearing bit VREN (VRCON). This RESET also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON) and selects the high voltage
range by clearing bit VRR (VRCON). The VREF
value select bits, VRCON, are also cleared.
10.5
STATUS,RP0
; go to Bank 0
CALL
DELAY10
; 10µs delay
10.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 10-1) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
tested absolute accuracy of the Voltage Reference can
be found in Table 17-2.
10.3
Connection Considerations
The
Voltage
Reference
module
operates
independently of the Comparator module. The output
of the reference generator may be connected to the
RA2 pin if the TRISA bit is set and the VROE bit,
VRCON, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with VREF enabled will also increase
current consumption.
; set VR=6
BCF
Effects of a RESET
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 10-2 shows an example buffering
technique.
Operation During SLEEP
When the device wakes-up from SLEEP through an
interrupt or a Watchdog Timer timeout, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 10-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
VREF
Module
R(1)
Op Amp
RA2
+
VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON and VRCON.
TABLE 10-1:
Address
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Name
Bit 7
Bit 6
VREN
VROE
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR
Value On
All Other
RESETS
9Fh
VRCON
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
1Fh
CMCON
C2OUT C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
0000 0000
85h
TRISA
TRISA7 TRISA6 TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
Note 1: — = Unimplemented, read as ‘0’.
DS40300C-page 60
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
11.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
TABLE 11-1:
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 11-1 shows the
timer resources of the CCP Module modes.
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
REGISTER 11-1:
CCP1CON REGISTER (ADDRESS: 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3
R/W-0
R/W-0
R/W-0
CCP1M2 CCP1M1 CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRxL.
bit 3-0
CCP1M3:CCP1M0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40300C-page 61
PIC16F62X
11.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
EXAMPLE 11-1:
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON). When a capture is made, the Interrupt Request Flag bit CCP1IF (PIR1) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
11.1.1
CCP PIN CONFIGURATION
If the RB3/CCP1 is configured as an output, a write to the port can cause a capture
condition.
TABLE 11-2:
CAPTURE MODE OPERATION
BLOCK DIAGRAM
Prescaler
³ 1, 4, 16
Set flag bit CCP1IF
(PIR1)
RB3/CCP1
Pin
CCPR1H
and
edge detect
CCPR1L
Capture
Enable
TMR1H
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS
MOVWF
CCP1CON
11.2
In Capture mode, the RB3/CCP1 pin should be
configured as an input by setting the TRISB bit.
Note:
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 11-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
CHANGING BETWEEN
CAPTURE PRESCALERS
;Turn CCP module off
;Load the W reg with
; the new prescaler
; mode value and CCP ON
;Load CCP1CON with this
; value
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 11-1:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Special Event Trigger will reset Timer1, but not set
interrupt flag bit TMR1IF (PIR1)
TMR1L
CCP1CON
Q’s
11.1.2
Set flag bit CCP1IF
(PIR1)
CCPR1H CCPR1L
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
11.1.3
Comparator
TMR1H
TMR1L
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
11.1.4
Q S Output
Logic
match
RB3/CCP1
R
Pin
TRISB
Output Enable CCP1CON
Mode Select
11.2.1
CCP PIN CONFIGURATION
The user must configure the RB3/CCP1 pin as an
output by clearing the TRISB bit.
Note:
CCP PRESCALER
Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the
default low level. This is not the data latch.
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
DS40300C-page 62
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
11.2.2
TIMER1 MODE SELECTION
11.2.4
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
11.2.3
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
TABLE 11-3:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBIF
Value on
POR
Value on
all other
RESETS
0Bh/8Bh/
10Bh/
18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF 0000 -000 0000 -000
8Ch
PIE1
EEIE
CMIF
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE 0000 -000 0000 -000
87h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
Legend:
—
—
—
—
0000 000x 0000 000u
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP1Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 63
PIC16F62X
11.3
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB bit must be cleared to make the CCP1
pin an output.
Note:
A PWM output (Figure 11-3) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 11-3:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
PWM OUTPUT
Period
Duty Cycle
Figure 11-2 shows a simplified block diagram of the
CCP module in PWM mode.
TMR2 = PR2
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 11.3.3.
TMR2 = Duty Cycle
TMR2 = PR2
FIGURE 11-2:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty cycle registers
CCP1CON
11.3.1
PWM PERIOD
The PWM period is specified by writing to the
PR2register. The PWM period can be calculated using
the following formula:
CCPR1L
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
CCPR1H (Slave)
PWM frequency is defined as 1 / [PWM period].
R
Comparator
TMR2
(Note 1)
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Q
RB3/CCP1
S
TRISB
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
Note
1:
8-bit timer is concatenated with the 2-bit internal
Q clock, or 2 bits of the prescaler to create 10-bit
time-base.
DS40300C-page 64
Preliminary
The Timer2 postscaler (see Section 8.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have an interrupt occur at a different frequency than the PWM output.
2003 Microchip Technology Inc.
PIC16F62X
11.3.2
PWM DUTY CYCLE
EQUATION 11-2:
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 11-1:
Note:
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
11.3.3
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
Maximum PWM resolution (bits) for a given PWM
frequency:
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISB bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
Address
bits
For an example on the PWM period and duty cycle
calculation, see the PICmicro™ Mid-Range Reference
Manual (DS33023).
CCPR1L and CCP1CON can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
TABLE 11-5:
Fosc
log (Fpwm x TMR2 Prescaler )
log (2)
PWM DUTY CYCLE
PWM duty cycle = (CCPR1L:CCP1CON) •
Tosc • (TMR2 prescale value)
TABLE 11-4:
PWM
Resolution =
MAXIMUM PWM
RESOLUTION
16
0xFF
10
4
0xFF
10
1
0xFF
10
1
0x3F
8
1
0x1F
7
1
0x17
6.5
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
0Bh/8Bh/
10Bh/18Bh
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
8Ch
PIE1
EEIE
CMIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000
0000 -000
87h
TRISB
PORTB Data Direction Register
1111 1111
1111 1111
11h
TMR2
Timer2 module’s register
0000 0000
0000 0000
92h
PR2
Timer2 module’s period register
1111 1111
1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM register1 (MSB)
17h
CCP1CON
Legend:
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
—
CCP1X
CCP1Y
CCP1M3
TMR2ON
CCP1M2
T2CKPS1 T2CKPS0
CCP1M1
CCP1M0
-000 0000
uuuu
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
--00 0000
--00 0000
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 65
PIC16F62X
NOTES:
DS40300C-page 66
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
12.0
UNIVERSAL SYNCHRONOUS/
ASYNCHRONOUS RECEIVER/
TRANSMITTER (USART)
MODULE
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA), and bits TRISB, have to
be set in order to configure pins RB2/TX/CK and RB1/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI). The USART can be
configured as a full duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be configured as a half duplex synchronous system that can
communicate with peripheral devices such as A/D or D/
A integrated circuits, Serial EEPROMs etc.
REGISTER 12-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as '0'
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1
TRMT: Transmit Shift Register STATUS bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of transmit data. Can be PARITY bit.
Note 1: SREN/CREN overrides TXEN in SYNC mode.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40300C-page 67
PIC16F62X
REGISTER 12-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB are set)
1 = Serial port enabled
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as PARITY bit
Asynchronous mode 8-bit (RX9=0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of received data (Can be PARITY bit)
Legend:
DS40300C-page 68
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16F62X
12.1
USART Baud Rate Generator
(BRG)
EXAMPLE 12-1:
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit baud rate generator. The SPBRG register controls
the period of a free running 8-bit timer. In Asynchronous mode bit BRGH (TXSTA) also controls the
baud rate. In Synchronous mode bit BRGH is ignored.
Table 12-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Desired Baud rate = FOSC / (64(X + 1))
9600 = 16000000 / (64( +1 ))X
X = î25.042°
Calculated Baud Rate = 16000000 / (64(25 + 1))
= 9615
Error = (Calculated Baud Rate = Desired Baud Rate)
Desired Baud Rate
Given the desired baud rate and Fosc, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
= (9615 - 9600)/ 9600
= 0.16%
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
Writing a new value to the SPBRG register, causes the
BRG timer to be RESET (or cleared), this ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
BRGH = 0
SYNC = 0
TABLE 12-1:
BAUD RATE FORMULA
SYNC
0
1
Legend:
BRGH = 0 (Low Speed)
Address
Baud Rate= FOSC/(16(X+1))
NA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
98h
TXSTA
18h
RCSTA
99h
SPBRG
Legend:
BRGH = 1 (High Speed)
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
X = value in SPBRG (0 to 255)
TABLE 12-2:
CALCULATING BAUD
RATE ERROR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other
RESETS
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
SPEN
RX9
SREN
CREN
ADEN
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
Baud Rate Generator Register
x = unknown, - = unimplemented read as '0'.
Shaded cells are not used by the BRG.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 69
PIC16F62X
TABLE 12-3:
BAUD
RATE (K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD
RATE (K)
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz
KBAUD
ERROR
NA
NA
NA
NA
19.53
76.92
96.15
294.1
500
5000
19.53
—
—
—
—
+1.73%
+0.16%
+0.16%
-1.96
0
—
—
FOSC = 7.15909 MHz
SPBRG 16 MHz
value
KBAUD
(decimal)
—
—
—
—
255
64
51
16
9
0
255
NA
NA
NA
NA
19.23
76.92
95.24
307.69
500
4000
15.625
SPBRG 5.0688 MHz
value
KBAUD
(decimal)
ERROR
—
—
—
—
+0.16%
+0.16%
-0.79%
+2.56%
0
—
—
—
—
—
—
207
51
41
12
7
0
255
NA
NA
NA
9.766
19.23
75.76
96.15
312.5
500
2500
9.766
SPBRG 4 MHz
value
KBAUD
(decimal)
ERROR
SPBRG
value
(decimal)
—
—
—
+1.73%
+0.16%
-1.36%
+0.16%
+4.17%
0
—
—
—
—
—
255
129
32
25
7
4
0
255
ERROR
SPBRG
value
(decimal)
KBAUD
ERROR
0.3
1.2
2.4
9.6
19.2
76.8
96
300
NA
NA
NA
9.622
19.24
77.82
94.20
298.3
—
—
—
+0.23%
+0.23%
+1.32
-1.88
-0.57
—
—
—
185
92
22
18
5
NA
NA
NA
9.6
19.2
79.2
97.48
316.8
—
—
—
0
0
+3.13%
+1.54%
5.60%
—
—
—
131
65
15
12
3
NA
NA
NA
9.615
19.231
75.923
1000
NA
500
NA
—
—
NA
—
NA
—
—
HIGH
LOW
1789.8
6.991
—
—
0
255
1267
4.950
—
—
—
0
255
100
3.906
—
—
0
255
ERROR
SPBRG
value
(decimal)
+1.14%
-2.48%
26
6
—
—
—
—
—
—
—
BAUD
RATE
(K)
FOSC = 3.579545 MHz
SPBRG 1 MHz
value
KBAUD
(decimal)
ERROR
SPBRG 10 MHz
value
KBAUD
(decimal)
KBAUD
ERROR
0.3
1.2
2.4
NA
NA
NA
—
—
—
—
—
—
NA
1.202
2.404
—
+0.16%
+0.16%
—
207
103
0.303
1.170
NA
9.6
19.2
76.8
9.622
19.04
74.57
+0.23%
-0.83%
-2.90%
92
46
11
9.615
19.24
83.34
+0.16%
+0.16%
+8.51%
25
12
2
NA
NA
NA
96
99.43
+3.57%
8
NA
298.3
NA
0.57%
2
—
NA
NA
—
—
—
NA
300
500
—
—
—
NA
—
—
—
HIGH
LOW
894.9
3.496
0
255
250
0.9766
—
—
0
255
8.192
0.032
—
—
DS40300C-page 70
—
—
—
ERROR
SPBRG 32.768 MHz
value
KBAUD
(decimal)
—
—
—
+0.16%
+0.16%
+0.16%
+4.17%
Preliminary
—
—
—
103
51
12
9
—
—
—
—
—
—
0
255
2003 Microchip Technology Inc.
PIC16F62X
TABLE 12-4:
BAUD
RATE (K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD
RATE (K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
KBAUD
ERROR
NA
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
312.5
1.221
—
+1.73%
+0.16%
-1.36%
+1.73%
+1.73%
+8.51%
+4.17%
—
—
—
FOSC = 7.15909 MHz
KBAUD
ERROR
NA
1.203
2.380
9.322
18.64
NA
NA
NA
NA
111.9
0.437
—
+0.23%
-0.83%
-2.90%
-2.90%
—
—
—
—
—
—
FOSC = 3.579545 MHz
KBAUD
ERROR
0.301
1.190
2.432
9.322
18.64
NA
NA
NA
NA
55.93
0.2185
+0.23%
-0.83%
+1.32%
-2.90%
-2.90%
—
—
—
—
—
—
2003 Microchip Technology Inc.
SPBRG 16 MHz
value
KBAUD
(decimal)
—
255
129
32
15
3
2
0
—
0
255
NA
1.202
2.404
9.615
19.23
83.33
NA
NA
NA
250
0.977
SPBRG 5.0688 MHz
value
KBAUD
(decimal)
—
92
46
11
5
—
—
—
—
0
255
0.31
1.2
2.4
9.9
19.8
79.2
NA
NA
NA
79.2
0.3094
SPBRG 1 MHz
value
KBAUD
(decimal)
185
46
22
5
2
—
—
—
—
0
255
0.300
1.202
2.232
NA
NA
NA
NA
NA
NA
15.63
0.0610
ERROR
—
+0.16%
+0.16%
+0.16%
+0.16%
+8.51%
—
—
—
—
—
ERROR
+3.13%
0
0
+3.13%
+3.13%
+3.13%
—
—
—
—
—
ERROR
+0.16%
+0.16%
-6.99%
—
—
—
—
—
—
—
—
Preliminary
SPBRG 10 MHz
value
KBAUD
(decimal)
—
207
103
25
12
2
—
—
—
0
255
NA
1.202
2.404
9.766
19.53
78.13
NA
NA
NA
156.3
0.6104
SPBRG 4 MHz
value
KBAUD
(decimal)
255
65
32
7
3
0
—
—
—
0
255
0.3005
1.202
2.404
NA
NA
NA
NA
NA
NA
62.500
3.906
SPBRG 32.768 MHz
value
KBAUD
(decimal)
51
12
6
—
—
—
—
—
—
0
255
0.256
NA
NA
NA
NA
NA
NA
NA
NA
0.512
0.0020
ERROR
SPBRG
value
(decimal)
—
+0.16%
+0.16%
+1.73%
+1.73V
+1.73%
—
—
—
—
—
—
129
64
15
7
1
—
—
—
0
255
ERROR
SPBRG
value
(decimal)
-0.17%
+1.67%
+1.67%
—
—
—
—
—
—
—
—
207
51
25
—
—
—
—
—
—
0
255
ERROR
SPBRG
value
(decimal)
-14.67%
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
0
255
DS40300C-page 71
PIC16F62X
TABLE 12-5:
BAUD
RATE (K)
9600
19200
38400
57600
115200
250000
625000
1250000
BAUD
RATE (K)
9600
19200
38400
57600
115200
250000
625000
1250000
BAUD
RATE
(K)
9600
19200
38400
57600
115200
250000
625000
1250000
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
KBAUD
ERROR
9.615
19.230
37.878
56.818
113.636
250
625
1250
+0.16%
+0.16%
-1.36%
-1.36%
-1.36%
0
0
0
FOSC = 7.16 MHz
KBAUD
ERROR
9.520
19.454
37.286
55.930
111.860
NA
NA
NA
-0.83%
+1.32%
-2.90%
-2.90%
-2.90%
—
—
—
FOSC = 3.579 MHz
KBAUD
ERROR
9725.543
18640.63
37281.25
55921.88
111243.8
223687.5
NA
NA
1.308%
-2.913%
-2.913%
-2.913%
-2.913%
-10.525%
—
—
DS40300C-page 72
SPBRG 16 MHz
value
KBAUD
(decimal)
129
64
32
21
10
4
1
0
9.615
19.230
38.461
58.823
111.111
250
NA
NA
SPBRG 5.068 MHz
value
KBAUD
(decimal)
46
22
11
7
3
—
—
—
9598.485
18632.35
39593.75
52791.67
105583.3
316750
NA
NA
SPBRG 1 MHz
value
KBAUD
(decimal)
22
11
5
3
1
0
—
—
8.928
20833.3
31250
62500
NA
NA
NA
NA
ERROR
+0.16%
+0.16%
+0.16%
+2.12%
-3.55%
0
—
—
ERROR
0.016%
-2.956%
3.109%
-8.348%
-8.348%
26.700%
—
—
ERROR
-6.994%
8.507%
-18.620%
+8.507
—
—
—
—
Preliminary
SPBRG 10 MHz
value
KBAUD
(decimal)
103
51
25
16
8
3
—
—
9.615
18.939
39.062
56.818
125
NA
625
NA
SPBRG 4 MHz
value
KBAUD
(decimal)
32
16
7
5
2
0
—
—
9615.385
19230.77
35714.29
62500
125000
250000
NA
NA
SPBRG 32.768 MHz
value
KBAUD
(decimal)
6
2
1
0
—
—
—
—
NA
NA
NA
NA
NA
NA
NA
NA
ERROR
SPBRG
value
(decimal)
+0.16%
-1.36%
+1.7%
-1.36%
+8.51%
—
0
—
64
32
15
10
4
—
0
—
ERROR
SPBRG
value
(decimal)
0.160%
0.160%
-6.994%
8.507%
8.507%
0.000%
—
—
25
12
6
3
1
0
—
—
ERROR
SPBRG
value
(decimal)
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
2003 Microchip Technology Inc.
PIC16F62X
The data on the RB1/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth
falling edges of a x16 clock (Figure 12-3). If bit BRGH
is set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
FIGURE 12-1:
RX PIN SAMPLING SCHEME. BRGH = 0
START bit
RX
(RB1/RX/DT pin)
Bit0
Baud CLK for all but START bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Samples
FIGURE 12-2:
RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
Bit0
START Bit
Bit1
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1
2
3
4
1
2
3
4
1
2
Q2, Q4 clk
Samples
FIGURE 12-3:
Samples
Samples
RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
START Bit
Bit0
Baud CLK for all but START bit
Baud CLK
First falling edge after RX pin goes low
Second rising edge
x4 CLK
1
2
3
4
Q2, Q4 CLK
Samples
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 73
PIC16F62X
FIGURE 12-4:
RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1
START bit
RX
(RB1/RX/DT pin)
Bit0
Baud CLK for all but START bit
Baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Samples
12.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return to
zero (NRZ) format (one START bit, eight or nine data
bits and one STOP bit). The most common data format
is 8 bits. A dedicated 8-bit baud rate generator is used
to derive baud rate frequencies from the oscillator. The
USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The baud rate generator produces a clock either
x16 or x64 of the bit shift rate, depending on bit BRGH
(TXSTA). Parity is not supported by the hardware,
but can be implemented in software (and stored as the
ninth data bit). Asynchronous mode is stopped during
SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA).
The USART Asynchronous module consists of the
following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
12.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-5. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in
DS40300C-page 74
software. It will RESET only when new data is loaded
into the TXREG register. While flag bit TXIF indicated
the status of the TXREG register, another bit TRMT
(TXSTA) shows the status of the TSR register.
STATUS bit TRMT is a read only bit which is set when
the TSR register is empty. No interrupt logic is tied to
this bit, so the user has to poll this bit in order to
determine if the TSR register is empty.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 12-5). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate
transfer to TSR resulting in an empty TXREG. A backto-back transfer is thus possible (Figure 12-7). Clearing
enable bit TXEN during a transmission will cause the
transmission to be aborted and will RESET the
transmitter. As a result the RB2/TX/CK pin will revert to
hi-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA) should be set and the ninth bit should be
written to TX9D (TXSTA). The ninth bit must be
written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG
register can result in an immediate transfer of the data
to the TSR register (if the TSR is empty). In such a
case, an incorrect ninth data bit may be loaded in the
TSR register.
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
FIGURE 12-5:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
8
TXIE
MSb
(8)
LSb
0
2 2 2
Pin Buffer
and Control
TSR register
RB2/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
TX9
Baud Rate Generator
TX9D
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1)
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
FIGURE 12-6:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
BRG output
(shift clock)
Word 1
RB2/TX/CK (pin)
START Bit
Bit 1
Bit 7/8
STOP Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit
(Transmit shift
reg. empty flag)
Bit 0
WORD 1
Transmit Shift Reg
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 75
PIC16F62X
FIGURE 12-7:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
WORD 1
BRG output
(shift clock)
RB2/TX/CK (pin)
START Bit
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Note
1:
Bit 1
WORD 1
Bit 7/8
STOP Bit
START Bit
Bit 0
WORD 2
WORD 2
Transmit Shift Reg.
This.timing diagram shows two consecutive transmissions.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
0Ch
18h
PIR1
RCSTA
EEIF
CMIF
RCIF
SPEN
RX9
SREN
19h
8Ch
TXREG USART Transmit Register
EEIE
CMIE
RCIE
PIE1
98h
TXSTA
99h
Bit 0
WORD 1
Transmit Shift Reg.
TABLE 12-6:
Address
WORD 2
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
0000 -000
CREN
ADEN
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 -000
0000 0000
0000 -000
0000 -010
0000 0000
0000 -010
0000 0000
Bit 4
TXIE
—
CCP1IE
TMR2IE
TMR1IE
CSRC
TX9
TXEN
SYNC
SPBRG Baud Rate Generator Register
—
BRGH
TRMT
TX9D
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
DS40300C-page 76
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
12.2.2
ADEN USART ASYNCHRONOUS
RECEIVER
It is possible for two bytes of data to be received and
transferred to the RCREG FIFO, and a third byte begin
shifting to the RSR register. On the detection of the
STOP bit of the third byte, if the RCREG register is still
full, then overrun error bit OERR (RCSTA) will be
set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhibited, so it is essential to clear error bit OERR if it is set.
Framing error bit FERR (RCSTA) is set if a STOP
bit is detected as clear. Bit FERR and the 9th receive
bit are buffered the same way as the receive data.
Reading the RCREG will load bits RX9D and FERR
with new values, therefore it is essential for the user to
read the RCSTA register before reading the RCREG
register in order not to lose the old FERR and RX9D
information.
The receiver block diagram is shown in Figure 12-8.
The data is received on the RB1/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter
operates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA).
The heart of the receiver is the Receive (serial) Shift
register (RSR). After sampling the STOP bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register ( i.e., it is a two-deep FIFO).
FIGURE 12-8:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
³ 64
or
³ 16
Baud Rate Generator
MSb
Stop (8)
7
RSR register
LSb
1
0 Start
² ² ²
RB1/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
ADEN
Enable
Load of
RX9
ADEN
RSR
Receive
Buffer
8
RX9D
RCREG register
RX9D
RCREG register
FIFO
8
Interrupt
RCIF
Data Bus
RCIE
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 77
PIC16F62X
FIGURE 12-9:
RB1/RX/DT (PIN)
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START
BIT BIT0
BIT1
BIT8 STOP
BIT
START
BIT BIT0
BIT8
STOP
BIT
RCV SHIFT REG
RCV BUFFER REG
BIT8 = 0, DATA BYTE
BIT8 = 1, ADDRESS BYTE
READ RCV
BUFFER REG
RCREG
WORD 1
RCREG
RCIF
(INTERRUPT FLAG)
'1'
ADEN = 1
(ADDRESS MATCH
ENABLE)
'1'
Note 1: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and Bit 8 = 0.
FIGURE 12-10:
RB1/RX/DT (PIN)
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START
BIT BIT0
RCV SHIFT
REG
RCV BUFFER REG
BIT1
BIT8 STOP
BIT
START
BIT BIT0
BIT8 = 1, ADDRESS BYTE WORD 1
RCREG
READ RCV
BUFFER REG
RCREG
BIT8
STOP
BIT
BIT8 = 0, DATA BYTE
RCIF
(INTERRUPT FLAG)
'1'
ADEN = 1
(ADDRESS MATCH
ENABLE)
'1'
Note 1: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.
FIGURE 12-11:
RB1/RX/DT (PIN)
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
START
BIT BIT0
RCV SHIFT
REG
RCV BUFFER REG
READ RCV
BUFFER REG
RCREG
BIT1
BIT8 STOP
BIT
START
BIT BIT0
BIT8 = 1, ADDRESS BYTE WORD 1
RCREG
BIT8
STOP
BIT
BIT8 = 0, DATA BYTE
WORD 2
RCREG
RCIF
(INTERRUPT FLAG)
ADEN
(ADDRESS MATCH
ENABLE)
Note 1: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of
the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.
DS40300C-page 78
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1).
Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
TABLE 12-7:
Address
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
EEIF
CMIF RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
0Ch
PIR1
18h
RCSTA
SPEN
RX9 SREN CREN ADEN FERR
OERR
RX9D 0000 -00x 0000 -00x
1Ah
RCREG USART Receive Register
0000 0000 0000 0000
8Ch
PIE1
EEIE
CMIE RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 79
PIC16F62X
12.3
USART Function
The USART function is similar to that on the
PIC16C74B, which includes the BRGH = 1 fix.
12.3.1
The USART Receive Block Diagram is shown in
Figure 12-8.
USART 9-BIT RECEIVER WITH
ADDRESS DETECT
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a
special provision for multiprocessor communication.
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA) along with the RX9 bit. The
port is now programmed so when the last bit is
received, the contents of the Receive Shift Register
(RSR) are transferred to the receive buffer. The ninth
bit of the RSR (RSR) is transferred to RX9D, and
the receive interrupt is set if, and only, if RSR = 1.
This feature can be used in a multiprocessor system as
follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR) to a '1'
(instead of a '0' for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling multiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
When ADEN is enabled (='1'), all data bytes are
ignored. Following the STOP bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
TABLE 12-8:
Address
Name
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = '1'). When ADEN is
disabled (='0'), all data bytes are received and the 9th
bit can be used as the PARITY bit.
Reception is
(RCSTA).
12.3.1.1
enabled
by
setting
bit
CREN
Setting up 9-bit mode with Address
Detect
Steps to follow when setting up an Asynchronous or
Synchronous Reception with Address Detect Enabled:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH.
2. Enable asynchronous or synchronous communication by setting or clearing bit SYNC and
setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. Set bit RX9 to enable 9-bit reception.
5. Set ADEN to enable address detect.
6. Enable the reception by setting enable bit CREN
or SREN.
7. Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
8. Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
9. If any error occurred, clear the error by clearing
enable bit CREN if it was already set.
10. If the device has been addressed (RSR = 1
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
EEIF
CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
0Ch
PIR1
18h
RCSTA
SPEN
RX9
SREN
CREN
ADEN FERR
OERR
RX9D 0000 -00x 0000 -00x
1Ah
RCREG
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
0000 0000 0000 0000
EEIE
CMIE
RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
8Ch
PIE1
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
DS40300C-page 80
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
12.4
USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA). In
addition, enable bit SPEN (RCSTA) is set in order
to configure the RB2/TX/CK and RB1/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA).
12.4.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART Transmitter Block Diagram is shown in
Figure 12-5. The heart of the transmitter is the Transmit
(serial) Shift register (TSR). The Shift register obtains
its data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and
interrupt bit, TXIF (PIR1) is set. The interrupt can
be enabled/disabled by setting/clearing enable bit TXIE
(PIE1). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in software. It will RESET only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA) shows the status of the TSR register.
TRMT is a read only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory
so it is not available to the user.
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will RESET
the transmitter. The DT and CK pins will revert to hiimpedance. If either bit CREN or bit SREN is set,
during a transmission, the transmission is aborted and
the DT pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
RESET although it is disconnected from the pins. In
order to RESET the transmitter, the user has to clear bit
TXEN. If bit SREN is set (to interrupt an on-going
transmission and receive a single word), then after the
single word is received, bit SREN will be cleared and
the serial port will revert back to transmitting since bit
TXEN is still set. The DT line will immediately switch
from Hi-impedance Receive mode to transmit and start
driving. To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Transmission is enabled by setting enable bit TXEN
(TXSTA). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started
by first loading the TXREG register and then setting bit
TXEN (Figure 12-13). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN, and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
2003 Microchip Technology Inc.
Preliminary
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
DS40300C-page 81
PIC16F62X
TABLE 12-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other
RESETS
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
0Ch
PIR1
18h
RCSTA
SPEN
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 -00x 0000 -00x
19h
TXREG USART Transmit Register
0000 0000 0000 0000
EEIE
CMIE RCIE TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
8Ch
PIE1
98h
TXSTA
CSRC
TX9 TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
FIGURE 12-12:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RB1/RX/DT Pin
Bit 0
Bit 1
WORD 1
Bit 2
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 7
Bit 0
Bit 1
WORD 2
Bit 7
RB2/TX/CK Pin
WRITE to
TXREG REG
Write WORD1
Write WORD2
TXIF Bit
(Interrupt Flag)
TRMTTRMT
Bit
TXEN Bit
Note
1:
'1'
'1'
Sync Master mode; SPBRG = ‘0’. Continuous transmission of two 8-bit words.
FIGURE 12-13:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RB1/RX/DT pin
Bit0
Bit1
Bit2
Bit6
Bit7
RB2/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS40300C-page 82
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
12.4.2
USART SYNCHRONOUS MASTER
RECEPTION
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA) or enable bit CREN (RCSTA). Data is
sampled on the RB1/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are
set, then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1). Flag bit RCIF is a read only bit which is
RESET by the hardware. In this case, it is RESET
when the RCREG register has been read and is empty.
The RCREG is a double buffered register (i.e., it is a
two-deep FIFO). It is possible for two bytes of data to
be received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
Value on all
other
RESETS
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
0Ch
PIR1
18h
RCSTA
SPEN
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 -00x 0000 -00x
1Ah
RCREG USART Receive Register
0000 0000 0000 0000
8Ch
PIE1
EEPIE CMIE RCIE TXIE
—
CCP1IE TMR2IE TMR1IE -000 0000 -000 -000
TX9 TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
98h
TXSTA
CSRC
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 83
PIC16F62X
FIGURE 12-14:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB1/RX/DT PIN
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
RB2/TX/CK PIN
WRITE TO
BIT SREN
SREN BIT
CREN BIT '0'
'0'
RCIF BIT
(INTERRUPT)
READ
RXREG
Note 1: Timing diagram demonstrates Sync Master mode with bit SREN = ‘1’ and bit BRG = ‘0’.
12.5
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA).
12.5.1
USART SYNCHRONOUS SLAVE
TRANSMIT
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
b)
c)
d)
e)
1.
2.
3.
4.
5.
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
a)
Steps to follow when setting up a Synchronous Slave
Transmission:
6.
7.
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the
interrupt vector (0004h).
DS40300C-page 84
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
12.5.2
USART SYNCHRONOUS SLAVE
RECEPTION
2.
The operation of the Synchronous Master and Slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in Slave mode.
3.
4.
5.
If receive is enabled, by setting bit CREN, prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
6.
7.
Steps to follow when setting up a Synchronous Slave
Reception:
1.
8.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other
RESETS
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
0Ch
PIR1
18h
RCSTA
SPEN
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 -00x 0000 -00x
19h
TXREG USART Transmit Register
0000 0000 0000 0000
8Ch
PIE1
EEIE
CMIE RCIE TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
98h
TXSTA
CSRC
TX9 TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on all
other
RESETS
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000
0Ch
PIR1
18h
RCSTA
SPEN
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 -00x 0000
1Ah
RCREG USART Receive Register
0000 0000 0000
EEIE
CMIE RCIE TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000
8Ch
PIE1
98h
TXSTA
CSRC
TX9 TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000
99h
SPBRG Baud Rate Generator Register
0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
2003 Microchip Technology Inc.
Preliminary
-000
-00x
0000
-000
-010
0000
DS40300C-page 85
PIC16F62X
NOTES:
DS40300C-page 86
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
13.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers (SFRs). There are four SFRs used to read
and write this memory. These registers are:
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
•
•
•
•
EECON1
EECON2 (Not a physically implemented register)
EEDATA
EEADR
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC16F62X devices have 128 bytes of
data EEPROM with an address range from 0h to 7Fh.
Additional information on the Data EEPROM is
available in the PICmicro™ Mid-Range Reference
Manual, (DS33023).
REGISTER 13-1:
EEADR REGISTER (ADDRESS: 9Bh)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 0
bit 7
Unimplemented Address: Must be set to ‘0’
bit 6-0
EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation
Legend:
13.1
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
EEADR
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 128 bytes of
data EEPROM are implemented and only seven of the
eight bits in the register (EEADR) are required.
The upper bit is address decoded. This means that this
bit should always be '0' to ensure that the address is in
the 128 byte memory space.
13.2
EECON1 AND EECON2
REGISTERS
EECON1 is the control register with five low order bits
physically implemented. The upper-three bits are nonexistent and read as '0's.
x = Bit is unknown
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Timeout Reset during normal
operation. In these situations, following RESET, the
user can check the WRERR bit and rewrite the
location. The data and address will be unchanged in
the EEDATA and EEADR registers.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 87
PIC16F62X
REGISTER 13-2:
EECON1 REGISTER (ADDRESS: 9Ch)
U-0
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-x
—
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7-4
Unimplemented: Read as '0'
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOD Reset)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software).
0 = Does not initiate an EEPROM read
Legend:
DS40300C-page 88
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
2003 Microchip Technology Inc.
PIC16F62X
13.3
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 13-1:
BSF
MOVLW
MOVWF
BSF
MOVF
BCF
13.4
DATA EEPROM READ
STATUS, RP0
CONFIG_ADDR
EEADR
EECON1, RD
EEDATA, W
STATUS, RP0
;
;
;
;
;
;
Bank 1
Address to read
EE Read
W = EEDATA
Bank 0
Required
Sequence
DATA EEPROM WRITE
STATUS, RP0
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1,WR
BSF
INTCON, GIE
;
;
;
;
;
;
;
;
;
;
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
BSF
MOVF
BSF
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
13.5
EXAMPLE 13-3:
WRITING TO THE EEPROM DATA
MEMORY
EXAMPLE 13-2:
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR1 registers must be cleared by software.
STATUS, RP0
EEDATA, W
EECON1, RD
;
; Is the value written
; read (in EEDATA) the
;
SUBWF EEDATA, W
BCF
STATUS, RP0
BTFSS STATUS, Z
GOTO WRITE_ERR
:
:
13.6
Bank 1
Enable write
Disable INTs.
WRITE VERIFY
; Bank 1
; Read the
; value written
(in W reg) and
same?
;
;
;
;
;
;
Bank0
Is difference 0?
NO, Write error
YES, Good write
Continue program
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
Write 55h
Write AAh
Set WR bit
begin write
Enable INTs.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
cause the data not to be written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
The write initiate sequence, and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
13.7
DATA EEPROM OPERATION
DURING CODE PROTECT
When the device is code protected, the CPU is able to
read and write unscrambled data to the Data
EEPROM.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 89
PIC16F62X
TABLE 13-1:
Address
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
9Ah
9Bh
9Ch
9Dh
Legend:
Note
Bit 1
Bit 0
EEDATA
EEPROM data register
EEADR
EEPROM address register
EECON1
—
—
—
—
WRERR WREN
WR
RD
EECON2(1) EEPROM control register 2
x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by data EEPROM.
1: EECON2 is not a physical register
DS40300C-page 90
Preliminary
Value on
Power-on
Reset
xxxx
xxxx
-------
xxxx
xxxx
x000
----
Value on all
other
RESETS
uuuu
uuuu
-------
uuuu
uuuu
q000
----
2003 Microchip Technology Inc.
PIC16F62X
14.0
SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real-time
applications are what sets a microcontroller apart from
other processors. The PIC16F62X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving Operating modes
and offer code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
14.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special configuration memory space (2000h –
3FFFh), which can be accessed only during
programming. See Programming Specification.
OSC selection
RESET
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOD)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID Locations
In-circuit Serial Programming
The PIC16F62X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in RESET while the power
supply stabilizes. There is also circuitry to RESET the
device if a Brown-out occurs, which provides at least a
72 ms RESET. With these three functions on-chip,
most applications need no external RESET circuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The ER oscillator option saves system
cost while the LP crystal option saves power. A set of
configuration bits are used to select various options.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 91
PIC16F62X
REGISTER 14-1: CONFIGURATION WORD
CP1
CP0
CP1
CP0
—
CPD
LVP
BODEN
MCLRE
FOSC2
PWRTE
WDTE
F0SC1
bit 13
bit 13-10:
F0SC0
bit 0
CP1:CP0: Code Protection bits (2)
Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFhcode protected
Code protection for 1K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
bit 9:
Unimplemented: Read as ‘0’
bit 8:
CPD: Data Code Protection bit(3)
1 = Data memory code protection off
0 = Data memory code protected
bit 7:
LVP: Low Voltage Programming Enable
1 = RB4/PGM pin has PGM function, low voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6:
BODEN: Brown-out Detect Reset Enable bit (1)
1 = BOD Reset enabled
0 = BOD Reset disabled
bit 5:
MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital Input, MCLR internally tied to VDD
bit 3:
PWRTEN: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0:
FOSC2:FOSC0: Oscillator Selection bits(4)
111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
110 = ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note
1:
2:
3:
4:
Enabling Brown-out Detect Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Detect Reset is enabled.
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
The entire data EEPROM will be erased when the code protection is turned off.
When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled.
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
1 = bit is set
0 = bit is cleared
DS40300C-page 92
Preliminary
x = bit is unknown
2003 Microchip Technology Inc.
PIC16F62X
14.2
Oscillator Configurations
14.2.1
TABLE 14-1:
OSCILLATOR TYPES
Ranges Characterized:
The PIC16F62X can be operated in eight different
oscillator options. The user can program three
configuration bits (FOSC2 thru FOSC0) to select one of
these eight modes:
•
•
•
•
•
•
LP
XT
HS
ER
INTRC
EC
14.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
External Resistor (2 modes)
Internal Resistor/Capacitor (2 modes)
External Clock In
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
22 - 100 pF
15 - 68 pF
15 - 68 pF
22 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Note
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 14-1). The PIC16F62X oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 14-4).
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
68 - 100 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
XT
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
HS
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
14.2.3
RF
SLEEP
OSC2
C2
Note
1:
2:
RS
NOTE 1
FOSC
PIC16F62X
A series resistor may be required for some crystals.
See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
2003 Microchip Technology Inc.
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Freq
C1
XTAL
Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values
are for design guidance only. Since each resonator has
its own characteristics, the user should consult the resonator manufacturer for appropriate values of external
components.
Mode
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR) (HS, XT OR
LP OSC
CONFIGURATION)
OSC1
1:
TABLE 14-2:
Note
FIGURE 14-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
1:
Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values
are for design guidance only. Rs may be required in HS
mode as well as XT mode to avoid overdriving crystals
with low drive level specification. Since each crystal
has its own characteristics, the user should consult the
crystal manufacturer for appropriate values of external
components.
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used, or a
simple oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance, or one with parallel
resonance.
Figure 14-2 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to use
the fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
Preliminary
DS40300C-page 93
PIC16F62X
FIGURE 14-2:
14.2.5
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
For timing insensitive applications, the ER (External
Resistor) Clock mode offers additional cost savings.
Only one external component, a resistor to VSS, is
needed to set the operating frequency of the internal
oscillator. The resistor draws a DC bias current which
controls the oscillation frequency. In addition to the
resistance value, the oscillator frequency will vary from
unit to unit, and as a function of supply voltage and
temperature. Since the controlling parameter is a DC
current and not a capacitance, the particular package
type and lead frame will not have a significant effect on
the resultant frequency.
+5V
TO OTHER
DEVICES
10K
4.7K
74AS04
PIC16F62X
CLKIN
74AS04
10K
XTAL
10K
C1
C2
Figure 14-3 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 14-3:
ER OSCILLATOR
Figure 14-5 shows how the controlling resistor is
connected to the PIC16F62X. For REXT values below
10k, the oscillator operation becomes sensitive to
temperature. For very high REXT values (e.g., 1M), the
oscillator becomes sensitive to leakage and may stop
completely. Thus, we recommend keeping REXT
between 10k and 1M.
FIGURE 14-5:
EXTERNAL RESISTOR
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
330 KΩ
330 KΩ
74AS04
74AS04
TO OTHER
DEVICES
PIC16F62X
74AS04
CLKIN
0.1 PF
Table 14-3 shows the relationship between the
resistance value and the operating frequency.
TABLE 14-3:
XTAL
14.2.4
EXTERNAL CLOCK IN
For applications, where a clock is already available
elsewhere, users may directly drive the PIC16F62X
provided that this external clock source meets the
AC/DC timing requirements listed in Section 17.4.
Figure 14-4 shows how an external clock circuit should
be configured.
FIGURE 14-4:
Clock From
ext. system
EXTERNAL CLOCK INPUT
OPERATION (EC, HS, XT
OR LP OSC
CONFIGURATION)
OSC1/RA7
PIC16F62X
RA6
DS40300C-page 94
OSC2/RA6
RESISTANCE AND
FREQUENCY RELATIONSHIP
Resistance
Frequency
0
10.4 MHz
1K
10 MHz
10K
7.4 MHz
20K
5.3 MHz
47K
3 MHz
100K
1.6 MHz
220K
800 kHz
470K
300 kHz
1M
200 kHz
The ER Oscillator mode has two options that control
the unused OSC2 pin. The first allows it to be used as
a general purpose I/O port. The other configures the
pin as an output providing the FOSC signal (internal
clock divided by 4) for test or external synchronization
purposes.
Preliminary
2003 Microchip Technology Inc.
PIC16F62X
14.2.6
INTERNAL 4 MHZ OSCILLATOR
14.4
The internal RC oscillator provides a fixed 4 MHz
(nominal) system clock at VDD = 5V and 25°C, see
“Electrical Specifications” section for information on
variation over voltage and temperature.
14.2.7
CLKOUT
The PIC16F62X can be configured to provide a clock
out signal by programming the configuration word. The
oscillator frequency, divided by 4 can be used for test
purposes or to synchronize other logic.
14.3
Special Feature: Dual Speed
Oscillator Modes
A software programmable Dual Speed Oscillator mode
is provided when the PIC16F62X is configured in either
ER or INTRC Oscillator modes. This feature allows
users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz. In ER mode, the 4 MHz
setting will vary depending on the value of the external
resistor. Also in ER mode, the 37 kHz operation is fixed
and does not vary with resistor value. Applications that
require low current power savings, but cannot tolerate
putting the part into SLEEP, may use this mode.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See Section 3.2.2.6, Register 3-4.
FIGURE 14-6:
RESET
The PIC16F62X differentiates between various kinds of
RESET:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
WDT Wake-up (SLEEP)
Brown-out Detect (BOD)
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset, MCLR Reset, WDT
Reset and MCLR Reset during SLEEP. They are not
affected by a WDT Wake-up, since this is viewed as the
resumption of normal operation. TO and PD bits are set
or cleared differently in different RESET situations as
indicated in Table 14-5. These bits are used in software
to determine the nature of the RESET. See Table 14-8
for a full description of RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-6 for pulse width
specification.
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
Schmitt Trigger Input
MCLR/
VPP Pin
SLEEP
WDT
Module
WDT
Timeout
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Detect Reset
S
Q
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
R
OSC1/
CLKIN
Pin
On-chip(1)
OSC
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 14-4 for timeout situations.
Enable OST
Note
1:
This is a separate oscillator from the INTRC/ER oscillator.
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 95
PIC16F62X
14.5
14.5.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Detect
(BOD)
The Power-Up Time delay will vary from chip to chip
and due to VDD, temperature and process variation.
See DC parameters for details.
14.5.3
POWER-ON RESET (POR)
The OST provides a 1024 oscillator cycle (from OSC1
input) delay after the PWRT delay is over. This ensures
that the crystal oscillator or resonator has started and
stabilized.
The on-chip POR circuit holds the chip in RESET until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, just tie the
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. See Electrical Specifications for details.
The OST timeout is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
14.5.4
The POR circuit does not produce an internal RESET
when VDD declines.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
On any RESET (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in RESET until VDD rises above
VBOD. The Power-up Timer will now be invoked and will
keep the chip in RESET an additional 72 ms.
POWER-UP TIMER (PWRT)
The PWRT provides a fixed 72 ms (nominal) timeout
on power-up only, from POR or Brown-out Detect
Reset. The PWRT operates on an internal RC oscillator. The chip is kept in RESET as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
disable (if set) or enable (if cleared or programmed) the
PWRT. The PWRT should always be enabled when
Brown-out Detect Reset is enabled.
FIGURE 14-7:
BROWN-OUT DETECT (BOD)
RESET
The PIC16F62X members have on-chip BOD circuitry.
A configuration bit, BODEN, can disable (if clear/
programmed) or enable (if set) the BOD Reset circuitry.
If VDD falls below VBOD for longer than TBOD, the
brown-out situation will RESET the chip. A RESET is
not guaranteed to occur if VDD falls below VBOD for
shorter than TBOD. VBOD and TBOD are defined in
Table 17-1 and Table 17-6, respectively.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
14.5.2
OSCILLATOR START-UP TIMER
(OST)
If VDD drops below VBOD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
Reset and the Power-up Timer will be re-initialized.
Once VDD rises above VBOD, the Power-Up Timer will
execute a 72 ms RESET. The Power-up Timer should
always be enabled when Brown-out Detect is enabled.
Figure 14-7 shows typical Brown-out situations.
BROWN-OUT SITUATIONS
VDD
VBOD
≥ TBOD
INTERNAL
RESET
72 MS
VDD
INTERNAL
RESET
VBOD
