PIC16F818/819
18/20-Pin Enhanced Flash Microcontrollers
with nanoWatt Technology
Low-Power Features:
Pin Diagram
• Power-Managed modes:
- Primary Run: XT, RC oscillator,
87 A, 1 MHz, 2V
- INTRC: 7 A, 31.25 kHz, 2V
- Sleep: 0.2 A, 2V
• Timer1 oscillator: 1.8 A, 32 kHz, 2V
• Watchdog Timer: 0.7 A, 2V
• Wide operating voltage range:
- Industrial: 2.0V to 5.5V
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
VSS
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
1
2
3
4
5
6
7
8
9
PIC16F818/819
18-Pin PDIP, SOIC
18
17
16
15
14
13
12
11
10
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
Oscillators:
Special Microcontroller Features:
• Three Crystal modes:
- LP, XT, HS: up to 20 MHz
• Two External RC modes
• One External Clock mode:
- ECIO: up to 20 MHz
• Internal oscillator block:
- 8 user selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
• 100,000 erase/write cycles Enhanced Flash
program memory typical
• 1,000,000 typical erase/write cycles EEPROM
data memory typical
• EEPROM Data Retention: > 40 years
• In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
• Processor read/write access to program memory
• Low-Voltage Programming
• In-Circuit Debugging via two pins
Peripheral Features:
•
•
•
•
•
•
•
•
16 I/O pins with individual direction control
High sink/source current: 25 mA
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler, can be
incremented during Sleep via external crystal/clock
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Capture, Compare, PWM (CCP) module:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
10-bit, 5-channel Analog-to-Digital converter
Synchronous Serial Port (SSP) with
SPI (Master/Slave) and I2C™ (Slave)
Program Memory
Device
Data Memory
SSP
EEPROM I/O Pins
(Bytes)
10-bit
A/D (ch)
CCP
(PWM)
SPI
Slave
I2C™
Timers
8/16-bit
Flash
(Bytes)
# Single-Word
Instructions
SRAM
(Bytes)
PIC16F818
1792
1024
128
128
16
5
1
Y
Y
2/1
PIC16F819
3584
2048
256
256
16
5
1
Y
Y
2/1
2001-2013 Microchip Technology Inc.
DS39598F-page 1
PIC16F818/819
Pin Diagrams
Note 1:
DS39598F-page 2
RA1/AN1
RA0/AN0
NC
23
22
NC
25
24
RA3/AN3/VREF+
RA2/AN2/VREF26
RA4/AN4/T0CKI
27
28-Pin QFN(1)
1
2
3
4
5
6
7
8
9
10
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
VSS
VSS
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
28
18
17
16
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
VDD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
RA5/MCLR/VPP
1
21
RA7/OSC1/CLKI
NC
2
20
RA6/OSC2/CLKO
VSS
3
19
VDD
NC
4
18
NC
VSS
5
17
VDD
NC
6
16
RB7/T1OSI/PGD
RB0/INT
7
15
RB6/T1OSO/T1CKI/PGC
11
12
13
14
RB5/SS
NC
10
RB3/CCP1/PGM
NC
9
RB4/SCK/SCL
8
RB1/SDI/SDA
PIC16F818/819
RB2/SDO/CCP1
1
2
3
4
5
6
7
8
9
PIC16F818/819
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
VSS
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
PIC16F818/819
20-Pin SSOP
18-Pin PDIP, SOIC
For the QFN package, it is recommended that the bottom pad be connected to VSS.
2001-2013 Microchip Technology Inc.
PIC16F818/819
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization ................................................................................................................................................................... 9
3.0 Data EEPROM and Flash Program Memory.............................................................................................................................. 25
4.0 Oscillator Configurations ............................................................................................................................................................ 33
5.0 I/O Ports ..................................................................................................................................................................................... 39
6.0 Timer0 Module ........................................................................................................................................................................... 53
7.0 Timer1 Module ........................................................................................................................................................................... 57
8.0 Timer2 Module ........................................................................................................................................................................... 63
9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 65
10.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 71
11.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 81
12.0 Special Features of the CPU...................................................................................................................................................... 89
13.0 Instruction Set Summary .......................................................................................................................................................... 103
14.0 Development Support............................................................................................................................................................... 111
15.0 Electrical Characteristics .......................................................................................................................................................... 115
16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 141
17.0 Packaging Information.............................................................................................................................................................. 155
Appendix A: Revision History............................................................................................................................................................. 165
Appendix B: Device Differences ........................................................................................................................................................ 165
INDEX ................................................................................................................................................................................................ 167
The Microchip Web Site ..................................................................................................................................................................... 173
Customer Change Notification Service .............................................................................................................................................. 173
Customer Support .............................................................................................................................................................................. 173
Reader Response .............................................................................................................................................................................. 174
PIC16F818/819 Product Identification System .................................................................................................................................. 175
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2001-2013 Microchip Technology Inc.
DS39598F-page 3
PIC16F818/819
NOTES:
DS39598F-page 4
2001-2013 Microchip Technology Inc.
PIC16F818/819
1.0
DEVICE OVERVIEW
This document contains device specific information for
the operation of the PIC16F818/819 devices. Additional
information may be found in the “PIC® Mid-Range MCU
Family Reference Manual” (DS33023) which may be
downloaded from the Microchip web site. The Reference
Manual should be considered a complementary document to this data sheet and is highly recommended
reading for a better understanding of the device architecture and operation of the peripheral modules.
The PIC16F818/819 belongs to the Mid-Range family
of the PIC® devices. The devices differ from each other
in the amount of Flash program memory, data memory
and data EEPROM (see Table 1-1). A block diagram of
the devices is shown in Figure 1-1. These devices contain features that are new to the PIC16 product line:
• Internal RC oscillator with eight selectable
frequencies, including 31.25 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz and
8 MHz. The INTRC can be configured as the
system clock via the configuration bits. Refer to
Section 4.5 “Internal Oscillator Block” and
Section 12.1 “Configuration Bits” for further
details.
• The Timer1 module current consumption has
been greatly reduced from 20 A (previous PIC16
devices) to 1.8 A typical (32 kHz at 2V), which is
ideal for real-time clock applications. Refer to
Section 6.0 “Timer0 Module” for further details.
• The amount of oscillator selections has increased.
The RC and INTRC modes can be selected with
an I/O pin configured as an I/O or a clock output
(FOSC/4). An external clock can be configured
with an I/O pin. Refer to Section 4.0 “Oscillator
Configurations” for further details.
TABLE 1-1:
Device
Program
Flash
Data
Memory
Data
EEPROM
PIC16F819
2K x14
256 x 8
256 x 8
There are 16 I/O pins that are user configurable on a
pin-to-pin basis. Some pins are multiplexed with other
device functions. These functions include:
•
•
•
•
•
•
•
•
External Interrupt
Change on PORTB Interrupt
Timer0 Clock Input
Low-Power Timer1 Clock/Oscillator
Capture/Compare/PWM
10-bit, 5-channel Analog-to-Digital Converter
SPI/I2C
MCLR (RA5) can be configured as an Input
Table 1-2 details the pinout of the devices with
descriptions and details for each pin.
AVAILABLE MEMORY IN
PIC16F818/819 DEVICES
Device
Program
Flash
Data
Memory
Data
EEPROM
PIC16F818
1K x 14
128 x 8
128 x 8
2001-2013 Microchip Technology Inc.
DS39598F-page 5
PIC16F818/819
FIGURE 1-1:
PIC16F818/819 BLOCK DIAGRAM
13
Flash
Program
Memory
1K/2K x 14
Program
Bus
RAM Addr(1)
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
RA6/OSC2/CLKO
RA7/OSC1/CLKI
9
PORTB
Addr MUX
Instruction reg
7
Direct Addr
8
Indirect
Addr
FSR reg
Status reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Brown-out
Reset
Power-on
Reset
RA7/OSC1/CLKI
RA6/OSC2/CLKO
MCLR
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
RB4/SCK/SCL
RB5/SS
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
MUX
ALU
8
W reg
VDD, VSS
Timer0
Timer1
Timer2
10-bit, 5-channel
A/D
Synchronous
Serial Port
CCP1
Note 1:
PORTA
RAM
File
Registers
128/256 x 8
8-Level Stack
(13-bit)
14
8
Data Bus
Program Counter
Data EE
128/256 Bytes
Higher order bits are from the Status register.
DS39598F-page 6
2001-2013 Microchip Technology Inc.
PIC16F818/819
TABLE 1-2:
PIC16F818/819 PINOUT DESCRIPTIONS
Pin Name
PDIP/
SSOP QFN
SOIC
Pin# Pin#
Pin#
I/O/P
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
17
RA1/AN1
RA1
AN1
18
RA2/AN2/VREFRA2
AN2
VREF-
1
RA3/AN3/VREF+
RA3
AN3
VREF+
2
RA4/AN4/T0CKI
RA4
AN4
T0CKI
3
RA5/MCLR/VPP
RA5
MCLR
4
19
20
1
2
3
4
23
15
17
16
18
Bidirectional I/O pin.
Analog input channel 0.
I/O
I
TTL
Analog
Bidirectional I/O pin.
Analog input channel 1.
I/O
I
I
TTL
Analog
Analog
Bidirectional I/O pin.
Analog input channel 2.
A/D reference voltage (low) input.
I/O
I
I
TTL
Analog
Analog
Bidirectional I/O pin.
Analog input channel 3.
A/D reference voltage (high) input.
I/O
I
I
ST
Analog
ST
Bidirectional I/O pin.
Analog input channel 4.
Clock input to the TMR0 timer/counter.
I
I
ST
ST
P
–
I/O
O
ST
–
O
–
I/O
I
I
ST
ST/CMOS(3)
–
26
27
28
1
Input pin.
Master Clear (Reset). Input/programming
voltage input. This pin is an active-low Reset
to the device.
Programming threshold voltage.
20
CLKO
RA7/OSC1/CLKI
RA7
OSC1
CLKI
TTL
Analog
24
VPP
RA6/OSC2/CLKO
RA6
OSC2
I/O
I
Bidirectional I/O pin.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, this pin outputs CLKO signal
which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
21
Bidirectional I/O pin.
Oscillator crystal input.
External clock source input.
Legend: I = Input
O = Output
I/O = Input/Output
P = Power
– = Not used
TTL = TTL Input
ST = Schmitt Trigger Input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2001-2013 Microchip Technology Inc.
DS39598F-page 7
PIC16F818/819
TABLE 1-2:
PIC16F818/819 PINOUT DESCRIPTIONS (CONTINUED)
Pin Name
PDIP/
SSOP QFN
SOIC
Pin# Pin#
Pin#
I/O/P
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-up on
all inputs.
RB0/INT
RB0
INT
6
RB1/SDI/SDA
RB1
SDI
SDA
7
RB2/SDO/CCP1
RB2
SDO
CCP1
8
RB3/CCP1/PGM
RB3
CCP1
PGM
9
RB4/SCK/SCL
RB4
SCK
SCL
10
RB5/SS
RB5
SS
11
RB6/T1OSO/T1CKI/PGC
RB6
T1OSO
T1CKI
PGC
12
RB7/T1OSI/PGD
RB7
T1OSI
PGD
13
VSS
5
VDD
14
7
8
9
10
11
12
13
14
5, 6
7
I/O
I
TTL
ST(1)
Bidirectional I/O pin.
External interrupt pin.
I/O
I
I/O
TTL
ST
ST
Bidirectional I/O pin.
SPI data in.
I2C™ data.
I/O
O
I/O
TTL
ST
ST
Bidirectional I/O pin.
SPI data out.
Capture input, Compare output, PWM output.
I/O
I/O
I
TTL
ST
ST
Bidirectional I/O pin.
Capture input, Compare output, PWM output.
Low-Voltage ICSP™ Programming enable pin.
I/O
I/O
I
TTL
ST
ST
Bidirectional I/O pin. Interrupt-on-change pin.
Synchronous serial clock input/output for SPI.
Synchronous serial clock input for I2C.
I/O
I
TTL
TTL
Bidirectional I/O pin. Interrupt-on-change pin.
Slave select for SPI in Slave mode.
I/O
O
I
I
TTL
ST
ST
ST(2)
Interrupt-on-change pin.
Timer1 Oscillator output.
Timer1 clock input.
In-circuit debugger and ICSP programming
clock pin.
I/O
I
I
TTL
ST
ST(2)
Interrupt-on-change pin.
Timer1 oscillator input.
In-circuit debugger and ICSP programming
data pin.
P
–
Ground reference for logic and I/O pins.
P
–
Positive supply for logic and I/O pins.
8
9
10
12
13
15
16
3, 5
15, 16 17, 19
Legend: I = Input
O = Output
I/O = Input/Output
P = Power
– = Not used
TTL = TTL Input
ST = Schmitt Trigger Input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS39598F-page 8
2001-2013 Microchip Technology Inc.
PIC16F818/819
2.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC16F818/819.
These are the program memory and the data memory.
Each block has its own bus, so access to each block
can occur during the same oscillator cycle.
The data memory can be further broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The PIC16F818
device’s 128 bytes of data EEPROM memory have the
address range of 00h-7Fh and the PIC16F819 device’s
256 bytes of data EEPROM memory have the address
range of 00h-FFh. More details on the EEPROM
memory can be found in Section 3.0 “Data EEPROM
and Flash Program Memory”.
2.1
Program Memory Organization
The PIC16F818/819 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16F818, the first 1K x 14
(0000h-03FFh) is physically implemented (see
Figure 2-1). For the PIC16F819, the first 2K x 14 is
located at 0000h-07FFh (see Figure 2-2). Accessing a
location above the physically implemented address will
cause a wraparound. For example, the same instruction will be accessed at locations 020h, 420h, 820h,
C20h, 1020h, 1420h, 1820h and 1C20h.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
Additional information on device memory may be found
in the “PIC® Mid-Range Reference Manual”
(DS33023).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16F818
FIGURE 2-2:
PC
PC
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
PROGRAM MEMORY MAP
AND STACK FOR
PIC16F819
CALL, RETURN
RETFIE, RETLW
13
13
Stack Level 1
Stack Level 1
Stack Level 2
Stack Level 2
Stack Level 8
Stack Level 8
Reset Vector
0000h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Interrupt Vector
0004h
0005h
Page 0
03FFh
0400h
On-Chip
Program
Memory
Page 0
07FFh
0800h
Wraps to
0000h-03FFh
Wraps to
0000h-07FFh
1FFFh
2001-2013 Microchip Technology Inc.
1FFFh
DS39598F-page 9
PIC16F818/819
2.2
Data Memory Organization
The data memory is partitioned into multiple banks that
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 (Status) and RP0
(Status) are the bank select bits.
RP1:RP0
Bank
00
0
01
1
10
2
11
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are the General Purpose Registers, implemented
as static RAM. All implemented banks contain SFRs.
Some “high use” SFRs from one bank may be mirrored
in another bank for code reduction and quicker access
(e.g., the Status register is in Banks 0-3).
Note:
2.2.1
EEPROM data memory description can be
found in Section 3.0 “Data EEPROM and
Flash Program Memory” of this data
sheet.
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly or
indirectly through the File Select Register, FSR.
DS39598F-page 10
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 2-3:
PIC16F818 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Register
File
Address
Indirect addr.(*) 80h
OPTION_REG 81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
87h
88h
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
OSCCON
8Fh
OSCTUNE
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
General
A0h
Purpose
Register
BFh
32 Bytes
C0h
Accesses
40h-7Fh
96 Bytes
7Fh
Bank 0
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
11Fh
Accesses
20h-7Fh
Accesses
20h-7Fh
17Fh
Bank 2
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
120h
FFh
Bank 1
File
Address
File
Address
1FFh
Bank 3
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
2001-2013 Microchip Technology Inc.
DS39598F-page 11
PIC16F818/819
FIGURE 2-4:
PIC16F819 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
Indirect addr.(*) 80h
OPTION_REG 81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
87h
88h
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
OSCCON
8Fh
OSCTUNE
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
A0h
120h
General
Purpose
Register
80 Bytes
General
Purpose
Register
File
Address
File
Address
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
11Fh
General
Purpose
Register
80 Bytes
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
Accesses
20h-7Fh
96 Bytes
7Fh
Bank 0
Accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
Accesses
70h-7Fh
Bank 2
16Fh
170h
17Fh
1FFh
Bank 3
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
DS39598F-page 12
2001-2013 Microchip Technology Inc.
PIC16F818/819
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
Address
Name
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
01h
TMR0
Timer0 Module Register
xxxx xxxx
53, 17
02h(1)
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
23
03h(1)
STATUS
0001 1xxx
16
04h(1)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
23
05h
PORTA
PORTA Data Latch when written; PORTA pins when read
xxx0 0000
39
PORTB Data Latch when written; PORTB pins when read
IRP
RP1
RP0
TO
PD
Z
DC
C
06h
PORTB
xxxx xxxx
43
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
---0 0000
23
0Ah(1,2)
PCLATH
—
0Bh(1)
INTCON
0Ch
PIR1
0Dh
PIR2
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
—
—
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0-- 0000
20
—
—
—
EEIF
—
—
—
—
---0 ----
21
xxxx xxxx
57
xxxx xxxx
57
—
—
T1CKPS1
Write Buffer for the upper 5 bits of the Program Counter
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Timer2 Module Register
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
WCOL
16h
CCPR1H
Capture/Compare/PWM Register (MSB)
17h
CCP1CON
—
SSPOV
—
SSPEN
CCP1X
CKP
CCP1Y
SSPM3
CCP1M3
SSPM2
CCP1M2
SSPM1
CCP1M1
SSPM0
CCP1M0
--00 0000
57
0000 0000
63
-000 0000
64
xxxx xxxx
71, 76
0000 0000
73
xxxx xxxx
66, 67, 68
xxxx xxxx
66, 67, 68
--00 0000
65
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
xxxx xxxx
81
0000 00-0
81
1Eh
ADRESH
A/D Result Register High Byte
1Fh
ADCON0
ADCS1
Legend:
Note 1:
2:
3:
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
2001-2013 Microchip Technology Inc.
DS39598F-page 13
PIC16F818/819
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Bank 1
80h(1)
INDF
81h
OPTION_REG
82h(1)
PCL
83h(1)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
0000 0000
23
PSA
PS2
PS1
PS0
1111 1111
17, 54
0000 0000
23
PD
Z
DC
C
0001 1xxx
16
xxxx xxxx
23
1111 1111
39
1111 1111
43
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
84h(1)
FSR
Indirect Data Memory Address Pointer
85h
TRISA
TRISA7
86h
TRISB
PORTB Data Direction Register
TRISA6
TRISA5(3)
PORTA Data Direction Register (TRISA
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
---0 0000
23
8Ah(1,2)
PCLATH
—
8Bh(1)
INTCON
8Ch
PIE1
8Dh
—
—
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
19
PIE2
—
—
—
EEIE
—
—
—
—
---0 ----
21
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq
22
8Fh
OSCCON
—
IRCF2
IRCF1
IRCF0
—
IOFS
—
—
-000 -0--
38
90h(1)
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
36
91h
—
Write Buffer for the upper 5 bits of the PC
Unimplemented
—
—
92h
PR2
Timer2 Period Register
1111 1111
68
93h
SSPADD
Synchronous Serial Port (I2C™ mode) Address Register
0000 0000
71, 76
94h
SSPSTAT
SMP
CKE
D/A
0000 0000
72
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
ADRESL
xxxx xxxx
81
9Fh
ADCON1
00-- 0000
82
Legend:
Note 1:
2:
3:
P
S
R/W
UA
BF
A/D Result Register Low Byte
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
DS39598F-page 14
2001-2013 Microchip Technology Inc.
PIC16F818/819
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Bank 2
100h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
101h
TMR0
Timer0 Module Register
xxxx xxxx
53
102h(1
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
23
103h(1)
STATUS
104h(1)
FSR
105h
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
106h
IRP
PORTB
Unimplemented
PORTB Data Latch when written; PORTB pins when read
0001 1xxx
16
xxxx xxxx
23
—
—
xxxx xxxx
43
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
—
Unimplemented
—
—
---0 0000
23
10Ah(1,2) PCLATH
—
—
—
GIE
PEIE
TMR0IE
Write Buffer for the upper 5 bits of the Program Counter
10Bh(1)
INTCON
0000 000x
18
10Ch
EEDATA
EEPROM/Flash Data Register Low Byte
xxxx xxxx
25
EEPROM/Flash Address Register Low Byte
xxxx xxxx
25
--xx xxxx
25
---- -xxx
25
0000 0000
23
1111 1111
17, 54
0000 0000
23
10Dh
EEADR
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
INTE
RBIE
TMR0IF
INTF
RBIF
EEPROM/Flash Data Register High Byte
—
—
—
EEPROM/Flash Address Register
High Byte
Bank 3
180h(1)
INDF
181h
OPTION_REG
182h(1)
PCL
183h(1)
STATUS
184h(1)
FSR
185h
Addressing this location uses contents of FSR to address data memory (not a physical register)
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
186h
RBPU
Program Counter’s (PC) Least Significant Byte
TRISB
Unimplemented
PORTB Data Direction Register
0001 1xxx
16
xxxx xxxx
23
—
—
1111 1111
43
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
---0 0000
23
18Ah(1,2) PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
18Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18
18Ch
EECON1
EEPGD
—
—
FREE
WRERR
WREN
WR
RD
x--x x000
26
18Dh
EECON2
EEPROM Control Register 2 (not a physical register)
---- ----
25
18Eh
—
Reserved; maintain clear
0000 0000
—
18Fh
—
Reserved; maintain clear
0000 0000
—
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
2001-2013 Microchip Technology Inc.
DS39598F-page 15
PIC16F818/819
2.2.2.1
Status Register
The Status register, shown in Register 2-1, contains the
arithmetic status of the ALU, the Reset status and the
bank select bits for data memory.
The Status register can be the destination for any
instruction, as with any other register. If the Status
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
REGISTER 2-1:
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the Status register as
‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Status register because these instructions do not affect
the Z, C or DC bits from the Status register. For other
instructions not affecting any status bits, see
Section 13.0 “Instruction Set Summary”.
Note:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5
RP: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes.
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1,2)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand.
2: For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order
bit of the source register.
Legend:
DS39598F-page 16
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
2.2.2.2
OPTION_REG Register
Note:
The OPTION_REG register is a readable and writable
register that contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external
INT interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION_REG: OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
1:2
000
1:1
1:4
001
1:2
1:8
010
1:4
1 : 16
011
1:8
1 : 32
100
1 : 16
1 : 64
101
1 : 32
1 : 128
110
1 : 64
111
1 : 256
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39598F-page 17
PIC16F818/819
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable register that contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON).
User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
DS39598F-page 18
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
2.2.2.4
PIE1 Register
This register contains the individual enable bits for the
peripheral interrupts.
Note:
Bit PEIE (INTCON) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4
Unimplemented: Read as ‘0’
bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39598F-page 19
PIC16F818/819
2.2.2.5
PIR1 Register
Note:
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON).
User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4
Unimplemented: Read as ‘0’
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before returning
from the Interrupt Service Routine. The conditions that will set this bit are a transmission/
reception has taken place.
0 = No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
DS39598F-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIE
—
—
—
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as ‘0’
bit 4
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE write interrupt
0 = Disable EE write interrupt
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
2.2.2.7
W = Writable bit
‘1’ = Bit is set
PIR2 Register
.
The PIR2 register contains the flag bit for the EEPROM
write operation interrupt.
REGISTER 2-7:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON).
User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ADDRESS 0Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIF
—
—
—
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as ‘0’
bit 4
EEIF: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE write interrupt
0 = Disable EE write interrupt
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
-n = Value at POR
2001-2013 Microchip Technology Inc.
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS39598F-page 21
PIC16F818/819
2.2.2.8
Note:
PCON Register
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON).
User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent Resets to see if BOR is
clear, indicating a brown-out has occurred.
The BOR status bit is a ‘don’t care’ and is
not necessarily predictable if the brownout circuit is disabled (by clearing the
BOREN bit in the Configuration word).
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset, an external MCLR Reset
and WDT Reset.
REGISTER 2-8:
PCON: POWER CONTROL REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-x
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
DS39598F-page 22
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
2.3
PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low
byte comes from the PCL register, which is a readable
and writable register. The upper bits (PC) are
not readable but are indirectly writable through the
PCLATH register. On any Reset, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the
figure shows how the PC is loaded on a write to PCL
(PCLATH PCH). The lower example in the
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH PCH).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
8
7
0
PC
8
PCLATH
Instruction with
PCL as
Destination
ALU
PCH
11 10
PCL
8
0
7
PC
GOTO,CALL
2
PCLATH
11
Opcode
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
application note AN556, “Implementing a Table Read”
(DS00556).
2.3.2
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
2.4
Indirect Addressing: INDF and
FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
EXAMPLE 2-1:
PCLATH
12
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
PCL
12
5
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
•
•
•
•
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although status bits may be affected).
A simple program to clear RAM locations, 20h-2Fh,
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2:
STACK
The PIC16F818/819 family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the Stack Pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an
interrupt causes a branch. The stack is POPed in the
event of a RETURN, RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
2001-2013 Microchip Technology Inc.
INDIRECT ADDRESSING
NEXT
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x20
;initialize pointer
FSR
;to RAM
INDF
;clear INDF register
FSR
;inc pointer
FSR, 4 ;all done?
NEXT
;NO, clear next
CONTINUE
:
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (Status) as
shown in Figure 2-6.
DS39598F-page 23
PIC16F818/819
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0
6
Bank Select
Indirect Addressing
From Opcode
0
IRP
7
Bank Select
Location Select
00
01
10
FSR Register
0
Location Select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory(1)
Bank 0
Note 1:
Bank 1
Bank 2
Bank 3
For register file map detail, see Figure 2-3 or Figure 2-4.
DS39598F-page 24
2001-2013 Microchip Technology Inc.
PIC16F818/819
3.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
The data EEPROM and Flash program memory are
readable and writable during normal operation (over
the full VDD range). This memory is not directly mapped
in the register file space. Instead, it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write this
memory:
•
•
•
•
•
•
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
This section focuses on reading and writing data
EEPROM and Flash program memory during normal
operation. Refer to the appropriate device programming specification document for serial programming
information.
When interfacing the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data
EEPROM, with an address range from 00h to 0FFh.
Addresses from 80h to FFh are unimplemented on the
PIC16F818 device and will read 00h. When writing to
unimplemented locations, the charge pump will be
turned off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14-bit data for read/write and the EEADR
and EEADRH registers form a two-byte word that holds
the 13-bit address of the EEPROM location being
accessed. These devices have 1K or 2K words of
program Flash, with an address range from 0000h to
03FFh for the PIC16F818 and 0000h to 07FFh for the
PIC16F819. Addresses above the range of the respective device will wraparound to the beginning of program
memory.
The EEPROM data memory allows single byte read
and write. The Flash program memory allows singleword reads and four-word block writes. Program
memory writes must first start with a 32-word block
erase, then write in 4-word blocks. A byte write in data
EEPROM memory automatically erases the location
and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
2001-2013 Microchip Technology Inc.
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory.
Depending on the settings of the write-protect bits, the
device may or may not be able to write certain blocks
of the program memory; however, reads of the program
memory are allowed. When code-protected, the device
programmer can no longer access data or program
memory; this does NOT inhibit internal reads or writes.
3.1
EEADR and EEADRH
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSB of the
address is written to the EEADR register. When selecting a program address value, the MSB of the address
is written to the EEADRH register and the LSB is
written to the EEADR register.
If the device contains less memory than the full address
reach of the address register pair, the Most Significant
bits of the registers are not implemented. For example,
if the device has 128 bytes of data EEPROM, the Most
Significant bit of EEADR is not implemented on access
to data EEPROM.
3.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Control bit, EEPGD, determines if the access will be a
program or data memory access. When clear, as it is
when Reset, any subsequent operations will operate
on the data memory. When set, any subsequent
operations will operate on the program memory.
Control bits, RD and WR, initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR or a WDT Time-out Reset
during normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
Interrupt flag bit, EEIF in the PIR2 register, is set when
the write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
DS39598F-page 25
PIC16F818/819
REGISTER 3-1:
EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch)
R/W-x
U-0
U-0
R/W-x
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
—
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-5
Unimplemented: Read as ‘0’
bit 4
FREE: EEPROM Forced Row Erase bit
1 = Erase the program memory row addressed by EEADRH:EEADR on the next WR command
0 = Perform write-only
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
operation)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
Legend:
DS39598F-page 26
R = Readable bit
W = Writable bit
S = Set only
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
3.3
Reading Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1) and then set control bit, RD
(EECON1). The data is available in the very next
cycle in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1.
2.
3.
4.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the RD bit to start the read operation.
Read the data from the EEDATA register.
EXAMPLE 3-1:
BANKSEL EEADR
MOVF
ADDR, W
MOVWF
EEADR
DATA EEPROM READ
;
;
;
;
BANKSEL EECON1
;
BCF
EECON1, EEPGD ;
BSF
EECON1, RD
;
BANKSEL EEDATA
;
MOVF
EEDATA, W
;
3.4
Select Bank of EEADR
Data Memory Address
to read
Select Bank of EECON1
Point to Data memory
EE Read
Select Bank of EEDATA
W = EEDATA
Writing to Data EEPROM Memory
The steps to write to EEPROM data memory are:
1.
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
• Write AAh to EECON2 in two steps (first to W,
then to EECON2)
• Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set
(EEIF must be cleared by firmware). If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to be clear, to indicate
the end of the program cycle.
EXAMPLE 3-2:
BANKSEL EECON1
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then, the user must follow a
specific write sequence to initiate the write for each
byte.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
2001-2013 Microchip Technology Inc.
Required
Sequence
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times except when
updating EEPROM. The WREN bit is not cleared
by hardware
DATA EEPROM WRITE
;
;
BTFSC
EECON1, WR
;
GOTO
$-1
;
BANKSEL EEADR
;
;
MOVF
ADDR, W
;
MOVWF
EEADR
;
;
MOVF
VALUE, W
;
MOVWF
EEDATA
;
;
BANKSEL EECON1
;
;
BCF
EECON1, EEPGD ;
;
BSF
EECON1, WREN ;
Select Bank of
EECON1
Wait for write
to complete
Select Bank of
EEADR
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
Disable INTs.
BSF
BCF
INTCON, GIE
EECON1, WREN
;
;
;
;
;
;
;
;
;
Data Memory
Address to write
Data Memory Value
to write
Select Bank of
EECON1
Point to DATA
memory
Enable writes
Write 55h
Write AAh
Set WR bit to
begin write
Enable INTs.
Disable writes
DS39598F-page 27
PIC16F818/819
3.5
Reading Flash Program Memory
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit
(EECON1) and then set control bit, RD
(EECON1). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle to read the data. This causes the
second instruction immediately following the
“BSF EECON1, RD” instruction to be ignored. The data
is available in the very next cycle in the EEDATA and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATA and
EEDATH registers will hold this value until another read
or until it is written to by the user (during a write
operation).
EXAMPLE 3-3:
BANKSEL EEADRH
MOVF
ADDRH, W
MOVWF
EEADRH
FLASH PROGRAM READ
;
;
;
;
MOVF
ADDRL, W
;
MOVWF
EEADR
;
;
BANKSEL EECON1
;
BSF
EECON1, EEPGD ;
;
BSF
EECON1, RD
;
;
NOP
;
;
NOP
;
;
;
BANKSEL EEDATA
;
MOVF
EEDATA, W
;
MOVWF
DATAL
;
MOVF
EEDATH, W
;
MOVWF
DATAH
;
Select Bank of EEADRH
MS Byte of Program
Address to read
LS Byte of Program
Address to read
Select Bank of EECON1
Point to PROGRAM
memory
EE Read
3.6
The minimum erase block is 32 words. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the Flash array is not supported.
When initiating an erase sequence from the microcontroller itself, a block of 32 words of program memory
is erased. The Most Significant 11 bits of the
EEADRH:EEADR point to the block being erased.
EEADR< 4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
After the “BSF EECON1, WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the erase
takes place. This is not Sleep mode, as the clocks and
peripherals will continue to run. After the erase cycle,
the processor will resume operation with the third
instruction after the EECON1 write instruction.
3.6.1
Any instructions
here are ignored as
program memory is
read in second cycle
after BSF EECON1,RD
Select Bank of EEDATA
DATAL = EEDATA
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
DATAH = EEDATH
3.
4.
5.
6.
7.
DS39598F-page 28
Erasing Flash Program Memory
Load EEADRH:EEADR with address of row
being erased.
Set EEPGD bit to point to program memory; set
WREN bit to enable writes and set FREE bit to
enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase.
2001-2013 Microchip Technology Inc.
PIC16F818/819
EXAMPLE 3-4:
ERASING A FLASH PROGRAM MEMORY ROW
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
EEADRH
ADDRH, W
EEADRH
ADDRL, W
EEADR
; Select Bank of EEADRH
;
; MS Byte of Program Address to Erase
;
; LS Byte of Program Address to Erase
BANKSEL
BSF
BSF
BSF
EECON1
EECON1, EEPGD
EECON1, WREN
EECON1, FREE
;
;
;
;
Select Bank of EECON1
Point to PROGRAM memory
Enable Write to memory
Enable Row Erase operation
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Disable interrupts (if using)
ERASE_ROW
;
NOP
BCF
BCF
BSF
EECON1, FREE
EECON1, WREN
INTCON, GIE
2001-2013 Microchip Technology Inc.
Write 55h
Write AAh
Start Erase (CPU stall)
Any instructions here are ignored as processor
halts to begin Erase sequence
processor will stop here and wait for Erase complete
after Erase processor continues with 3rd instruction
Disable Row Erase operation
Disable writes
Enable interrupts (if using)
DS39598F-page 29
PIC16F818/819
3.7
Writing to Flash Program Memory
The user must follow the same specific sequence to
initiate the write for each word in the program block by
writing each program word in sequence (00, 01, 10,
11).
Flash program memory may only be written to if the
destination address is in a segment of memory that is
not write-protected, as defined in bits WRT1:WRT0 of
the device Configuration Word (Register 12-1). Flash
program memory must be written in four-word blocks.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where EEADR = 00. At the same time,
all block writes to program memory are done as writeonly operations. The program memory must first be
erased. The write operation is edge-aligned and cannot
occur across boundaries.
There are 4 buffer register words and all four locations
MUST be written to with correct data.
After the “BSF EECON1, WR” instruction, if
EEADR xxxxxx11, then a short write will occur.
This short write-only transfers the data to the buffer
register. The WR bit will be cleared in hardware after
one cycle.
After the “BSF EECON1, WR” instruction, if
EEADR = xxxxxx11, then a long write will occur. This
will simultaneously transfer the data from
EEDATH:EEDATA to the buffer registers and begin the
write of all four words. The processor will execute the
next instruction and then ignore the subsequent
instruction. The user should place NOP instructions into
the second words. The processor will then halt internal
operations for typically 2 msec in which the write takes
place. This is not a Sleep mode, as the clocks and
peripherals will continue to run. After the write cycle,
the processor will resume operation with the 3rd
instruction after the EECON1 write instruction.
To write to the program memory, the data must first be
loaded into the buffer registers. There are four 14-bit
buffer registers and they are addressed by the low
2 bits of EEADR.
The following sequence of events illustrate how to
perform a write to program memory:
• Set the EEPGD and WREN bits in the EECON1
register
• Clear the FREE bit in EECON1
• Write address to EEADRH:EEADR
• Write data to EEDATH:EEDATA
• Write 55 to EECON2
• Write AA to EECON2
• Set WR bit in EECON 1
FIGURE 3-1:
After each long write, the 4 buffer registers will be reset
to 3FFF.
BLOCK WRITES TO FLASH PROGRAM MEMORY
7
5
0
0 7
EEDATH
EEDATA
6
8
14
14
All buffers are
transferred
to Flash
automatically
after this word
is written
First word of block
to be written
14
EEADR = 00
EEADR = 01
Buffer Register
EEADR = 10
Buffer Register
14
EEADR = 11
Buffer Register
Buffer Register
Program Memory
DS39598F-page 30
2001-2013 Microchip Technology Inc.
PIC16F818/819
An example of the complete four-word write sequence
is shown in Example 3-5. The initial address is loaded
into the EEADRH:EEADR register pair; the four words
of data are loaded using indirect addressing, assuming
that a row erase sequence has already been
performed.
EXAMPLE 3-5:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
;
;
;
;
;
;
1.
2.
3.
4.
5.
6.
The 32 words in the erase block have already been erased.
A valid starting address (the least significant bits = '00') is loaded into EEADRH:EEADR
This example is starting at 0x100, this is an application dependent setting.
The 8 bytes (4 words) of data are loaded, starting at an address in RAM called ARRAY.
This is an example only, location of data to program is application dependent.
word_block is located in data memory.
BANKSEL
BSF
BSF
BCF
EECON1
EECON1, EEPGD
EECON1, WREN
EECON1, FREE
BANKSEL word_block
MOVLW
.4
MOVWF
word_block
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
MOVLW
MOVWF
EEADRH
0x01
EEADRH
0x00
EEADR
ARRAY
ARRAY
FSR
BANKSEL
MOVF
MOVWF
INCF
MOVF
MOVWF
INCF
EEDATA
INDF, W
EEDATA
FSR, F
INDF, W
EEDATH
FSR, F
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
EECON1
0x55
EECON2
0xAA
EECON2
EECON1, WR
BANKSEL
INCF
BANKSEL
DECFSZ
GOTO
EEADR
EEADR, f
word_block
word_block, f
loop
;prepare for WRITE procedure
;point to program memory
;allow write cycles
;perform write only
;prepare for 4 words to be written
;Start writing at 0x100
;load HIGH address
;load LOW address
;initialize FSR to start of data
Required
Sequence
LOOP
BANKSEL EECON1
BCF
EECON1, WREN
BSF
INTCON, GIE
2001-2013 Microchip Technology Inc.
;indirectly load EEDATA
;increment data pointer
;indirectly load EEDATH
;increment data pointer
;required sequence
;set WR bit to begin write
;instructions here are ignored as processor
;load next word address
;have 4 words been written?
;NO, continue with writing
;YES, 4 words complete, disable writes
;enable interrupts
DS39598F-page 31
PIC16F818/819
3.8
Protection Against Spurious Write
3.9
There are conditions when the device should not write
to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents an
EEPROM write.
When the data EEPROM is code-protected, the microcontroller can read and write to the EEPROM normally.
However, all external access to the EEPROM is
disabled. External write access to the program memory
is also disabled.
When program memory is code-protected, the microcontroller can read and write to program memory
normally as well as execute instructions. Writes by the
device may be selectively inhibited to regions of
the memory depending on the setting of bits,
WRT1:WRT0, of the Configuration Word (see
Section 12.1 “Configuration Bits” for additional
information). External access to the memory is also
disabled.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
TABLE 3-1:
Address
Operation During Code-Protect
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND
FLASH PROGRAM MEMORIES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets
10Ch
EEDATA EEPROM/Flash Data Register Low Byte
xxxx xxxx uuuu uuuu
10Dh
EEADR
xxxx xxxx uuuu uuuu
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
—
—
—
18Ch
EECON1 EEPGD
—
—
FREE
WRERR
18Dh
EECON2 EEPROM Control Register 2 (not a physical register)
0Dh
PIR2
—
—
—
EEIF
—
8Dh
PIE2
—
—
—
EEIE
—
Legend:
EEPROM/Flash Address Register Low Byte
EEPROM/Flash Data Register High Byte
--xx xxxx --uu uuuu
EEPROM/Flash Address
Register High Byte
WREN
---- -xxx ---- -uuu
WR
RD
x--x x000 x--x q000
—
—
—
---0 ---- ---0 ----
—
—
—
---0 ---- ---0 ----
---- ---- ---- ----
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM or Flash program memory.
DS39598F-page 32
2001-2013 Microchip Technology Inc.
PIC16F818/819
4.0
OSCILLATOR
CONFIGURATIONS
4.1
Oscillator Types
TABLE 4-1:
The PIC16F818/819 can be operated in eight different
oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these eight
modes (modes 5-8 are new PIC16 oscillator
configurations):
1.
2.
3.
4.
LP
XT
HS
RC
5.
RCIO
6.
INTIO1
7.
INTIO2
8.
ECIO
4.2
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
External Resistor/Capacitor with
FOSC/4 output on RA6
External Resistor/Capacitor with
I/O on RA6
Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
Internal Oscillator with I/O on RA6
and RA7
External Clock with I/O on RA6
Crystal Oscillator/Ceramic
Resonators
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKI and OSC2/CLKO pins
to establish oscillation (see Figure 4-1 and Figure 4-2).
The PIC16F818/819 oscillator design requires the use
of a parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturer’s
specifications.
FIGURE 4-1:
CRYSTAL OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
OSC1
PIC16F818/819
(1)
C1
XTAL
RF(3)
Sleep
Osc Type
LP
XT
HS
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR (FOR
DESIGN GUIDANCE ONLY)
Crystal
Freq
Typical Capacitor Values
Tested:
C1
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
56 pF
56 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15 pF
15 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
were not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
2: Since each crystal has its own characteristics, the user should consult the crystal
manufacturer for appropriate values of
external components.
3: RS may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
OSC2
RS(2)
C2(1)
To Internal
Logic
Note 1: See Table 4-1 for typical values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen (typically
between 2 M to 10 M.
2001-2013 Microchip Technology Inc.
DS39598F-page 33
PIC16F818/819
FIGURE 4-2:
CERAMIC RESONATOR
OPERATION (HS OR XT
OSC CONFIGURATION)
OSC1
PIC16F818/819
C1(1)
RES
RF(3)
Sleep
OSC2
RS(2)
C2(1)
To Internal
Logic
4.3
External Clock Input
The ECIO Oscillator mode requires an external clock
source to be connected to the OSC1 pin. There is no
oscillator start-up time required after a Power-on Reset
or after an exit from Sleep mode.
In the ECIO Oscillator mode, the OSC2 pin becomes
an additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6). Figure 4-3 shows the
pin connections for the ECIO Oscillator mode.
FIGURE 4-3:
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Note 1: See Table 4-2 for typical values of C1 and C2.
2: A series resistor (RS) may be required.
3: RF varies with the resonator chosen (typically
between 2 M to 10 M.
OSC1/CLKI
Clock from
Ext. System
PIC16F818/819
RA6
TABLE 4-2:
I/O (OSC2)
CERAMIC RESONATORS (FOR
DESIGN GUIDANCE ONLY)
Typical Capacitor Values Used:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values were not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Note:
When using resonators with frequencies
above 3.5 MHz, the use of HS mode rather
than XT mode is recommended. HS mode
may be used at any VDD for which the
controller is rated. If HS is selected, it is
possible that the gain of the oscillator will
overdrive the resonator. Therefore, a
series resistor should be placed between
the OSC2 pin and the resonator. As a
good starting point, the recommended
value of RS is 330
DS39598F-page 34
2001-2013 Microchip Technology Inc.
PIC16F818/819
4.4
RC Oscillator
4.5
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT)
values and the operating temperature. In addition to
this, the oscillator frequency will vary from unit to unit
due to normal manufacturing variation. Furthermore,
the difference in lead frame capacitance between package types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 4-4 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal may
be used for test purposes or to synchronize other logic.
FIGURE 4-4:
RC OSCILLATOR MODE
VDD
REXT
Internal
Clock
OSC1
The PIC16F818/819 devices include an internal
oscillator block which generates two different clock
signals; either can be used as the system’s clock
source. This can eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the system clock. It
also drives the INTOSC postscaler which can provide a
range of clock frequencies from 125 kHz to 4 MHz.
The other clock source is the internal RC oscillator
(INTRC) which provides a 31.25 kHz (32 s nominal
period) output. The INTRC oscillator is enabled by
selecting the INTRC as the system clock source or
when any of the following are enabled:
• Power-up Timer
• Watchdog Timer
These features are discussed in greater detail in
Section 12.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 4-2).
Note:
CEXT
PIC16F818/819
VSS
FOSC/4
OSC2/CLKO
Recommended values: 3 k REXT 100 k
CEXT > 20 pF
The RCIO Oscillator mode (Figure 4-5) functions like
the RC mode except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 4-5:
RCIO OSCILLATOR MODE
VDD
REXT
Internal
Clock
OSC1
CEXT
PIC16F818/819
VSS
RA6
Internal Oscillator Block
4.5.1
Throughout this data sheet, when referring
specifically to a generic clock source, the
term “INTRC” may also be used to refer to
the clock modes using the internal
oscillator block. This is regardless of
whether the actual frequency used is
INTOSC (8 MHz), the INTOSC postscaler
or INTRC (31.25 kHz).
INTRC MODES
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
I/O (OSC2)
Recommended values: 3 k REXT 100 k
CEXT > 20 pF
2001-2013 Microchip Technology Inc.
DS39598F-page 35
PIC16F818/819
4.5.2
OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at the
factory but can be adjusted in the application. This is
done by writing to the OSCTUNE register (Register 4-1).
The tuning sensitivity is constant throughout the tuning
range. The OSCTUNE register has a tuning range of
±12.5%.
REGISTER 4-1:
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency
within 8 clock cycles (approximately 8 * 32 s = 256 s);
the INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that
the shift has occurred. Operation of features that depend
on the 31.25 kHz INTRC clock source frequency, such
as the WDT, Fail-Safe Clock Monitor and peripherals,
will also be affected by the change in frequency.
OSCTUNE: OSCILLATOR TUNING REGISTER (ADDRESS 90h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TUN: Frequency Tuning bits
011111 = Maximum frequency
011110 =
•
•
•
000001 =
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111 =
•
•
•
100000 = Minimum frequency
Legend:
R = Readable bit
-n = Value at POR
DS39598F-page 36
bit 0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
4.5.3
OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 4-2) controls several
aspects of the system clock’s operation.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source (31.25 kHz), the INTOSC source
(8 MHz) or one of the six frequencies derived from the
INTOSC postscaler (125 kHz to 4 MHz). Changing the
configuration of these bits has an immediate change on
the multiplexor’s frequency output.
4.5.4
MODIFYING THE IRCF BITS
The IRCF bits can be modified at any time regardless of
which clock source is currently being used as the
system clock. The internal oscillator allows users to
change the frequency during run time. This is achieved
by modifying the IRCF bits in the OSCCON register.
The sequence of events that occur after the IRCF bits
are modified is dependent upon the initial value of the
IRCF bits before they are modified. If the INTRC
(31.25 kHz, IRCF = 000) is running and the IRCF
bits are modified to any other value than ‘000’, a 4 ms
(approx.) clock switch delay is turned on. Code execution continues at a higher than expected frequency
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. This bit can be
monitored to ensure that the frequency is stable before
using the system clock in time critical applications.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz, IRCF 000), there is no need for a
4 ms (approx.) clock switch delay. The new INTOSC
frequency will be stable immediately after the eight
falling edges. The IOFS bit will remain set after clock
switching occurs.
Note:
Caution must be taken when modifying the
IRCF bits using BCF or BSF instructions. It
is possible to modify the IRCF bits to a
frequency that may be out of the VDD specification range; for example, VDD = 2.0V
and IRCF = 111 (8 MHz).
2001-2013 Microchip Technology Inc.
4.5.5
CLOCK TRANSITION SEQUENCE
WHEN THE IRCF BITS ARE
MODIFIED
Following are three different sequences for switching
the internal RC oscillator frequency.
• Clock before switch: 31.25 kHz (IRCF = 000)
1. IRCF bits are modified to an INTOSC/INTOSC
postscaler frequency.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. The IOFS bit is clear to indicate that the clock is
unstable and a 4 ms (approx.) delay is started.
Time dependent code should wait for IOFS to
become set.
5. Switchover is complete.
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF 000)
1. IRCF
bits
are
modified
to
INTRC
(IRCF = 000).
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. Oscillator switchover is complete.
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF 000)
1. IRCF bits are modified to a different INTOSC/
INTOSC postscaler frequency.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. The IOFS bit is set.
5. Oscillator switchover is complete.
DS39598F-page 37
PIC16F818/819
FIGURE 4-6:
PIC16F818/819 CLOCK DIAGRAM
PIC18F818/819
CONFIG (FOSC2:FOSC0)
OSC2
Sleep
LP, XT, HS, RC, EC
OSC1
8 MHz
4 MHz
Internal
Oscillator
Block
111
CPU
110
8 MHz
(INTOSC)
1 MHz
100
500 kHz
250 kHz
125 kHz
31.25 kHz
011
MUX
101
31.25 kHz
(INTRC)
REGISTER 4-2:
Internal Oscillator
2 MHz
Postscaler
31.25 kHz
Source
MUX
OSCCON
Peripherals
010
001
000
WDT
OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh)
U-0
R/W-0
R/W-0
R/W-0
U-0
R-0
U-0
U-0
—
IRCF2
IRCF1
IRCF0
—
IOFS
—
—
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31.25 kHz (INTRC source drives clock directly)
bit 3
Unimplemented: Read as ‘0’
bit 2
IOFS: INTOSC Frequency Stable bit
1 = Frequency is stable
0 = Frequency is not stable
bit 1-0
Unimplemented: Read as ‘0’
Legend:
DS39598F-page 38
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
5.0
I/O PORTS
Pin RA4 is multiplexed with the Timer0 module clock
input and with an analog input to become the RA4/AN4/
T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt
Trigger input and full CMOS output driver.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Pin RA5 is multiplexed with the Master Clear module
input. The RA5/MCLR/VPP pin is a Schmitt Trigger input.
Additional information on I/O ports may be found in the
“PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
5.1
Pin RA6 is multiplexed with the oscillator module input
and external oscillator output. Pin RA7 is multiplexed
with the oscillator module input and external oscillator
input. Pin RA6/OSC2/CLKO and pin RA7/OSC1/CLKI
are Schmitt Trigger inputs and full CMOS output drivers.
PORTA and the TRISA Register
PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
Pins RA are multiplexed with analog inputs. Pins
RA are multiplexed with analog inputs and VREF
inputs. Pins RA have TTL inputs and full CMOS
output drivers.
EXAMPLE 5-1:
BANKSEL PORTA
CLRF
PORTA
On a Power-on Reset, the pins
PORTA are configured as analog
inputs and read as ‘0’.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the port
data latch.
TABLE 5-1:
INITIALIZING PORTA
BANKSEL
MOVLW
MOVWF
MOVLW
ADCON1
0x06
ADCON1
0xFF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
select bank of PORTA
Initialize PORTA by
clearing output
data latches
Select Bank of ADCON1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA as inputs
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit 0
TTL
Input/output or analog input.
RA1/AN1
bit 1
TTL
Input/output or analog input.
RA2/AN2/VREF-
bit 2
TTL
Input/output, analog input or VREF-.
RA3/AN3/VREF+
bit 3
TTL
Input/output, analog input or VREF+.
RA4/AN4/T0CKI
bit 4
ST
Input/output, analog input or external clock input for Timer0.
RA5/MCLR/VPP
bit 5
ST
Input, Master Clear (Reset) or programming voltage input.
RA6/OSC2/CLKO
bit 6
ST
Input/output, connects to crystal or resonator, oscillator output or 1/4 the
frequency of OSC1 and denotes the instruction cycle in RC mode.
RA7/OSC1/CLKI
bit 7
ST/CMOS(1) Input/output, connects to crystal or resonator or oscillator input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
TABLE 5-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
05h
PORTA
85h
TRISA
9Fh
ADCON1
Legend:
Note 1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
TRISA7 TRISA6 TRISA5(1) PORTA Data Direction Register
ADFM
ADCS2
—
—
PCFG3 PCFG2 PCFG1
PCFG0
Value on
POR, BOR
Value on all
other Resets
xxx0 0000
uuu0 0000
1111 1111
1111 1111
00-- 0000
00-- 0000
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
2001-2013 Microchip Technology Inc.
DS39598F-page 39
PIC16F818/819
FIGURE 5-1:
Data
Bus
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-3:
Data
Bus
D
WR
PORTA
Q
CK
Q
Data Latch
D
WR
TRISA
Q
I/O pin
N
Q
WR
TRISA
Analog
Input Mode
Q
N
CK
Analog
Input Mode
TTL
Input Buffer
RD TRISA
Q
Q
I/O pin
VSS
VSS
VSS
TTL
Input Buffer
RD TRISA
Q
TRIS Latch
VSS
TRIS Latch
VDD
VDD
P
CK
Q
Data Latch
D
Q
CK
D
WR
PORTA
VDD
VDD
P
BLOCK DIAGRAM OF
RA2/AN2/VREF- PIN
D
D
EN
EN
RD PORTA
RD PORTA
To A/D Module VREF- Input
To A/D Module Channel Input
To A/D Module Channel Input
FIGURE 5-2:
Data
Bus
BLOCK DIAGRAM OF
RA3/AN3/VREF+ PIN
D
WR
PORTA
Data
Bus
Q
CK
FIGURE 5-4:
VDD
VDD
P
Q
D
WR
PORTA
WR
TRISA
VDD
VDD
P
Q
Data Latch
Q
D
I/O pin
N
CK
Q
CK
Data Latch
D
BLOCK DIAGRAM OF
RA4/AN4/T0CKI PIN
Q
VSS
TRIS Latch
VSS
WR
TRISA
Q
N
CK
Q
VSS
VSS
TRIS Latch
Analog
Input Mode
Analog
Input Mode
TTL
Input Buffer
RD TRISA
RD TRISA
Q
D
Schmitt Trigger
Input Buffer
Q
EN
D
EN
RD PORTA
RD PORTA
To A/D Module VREF+ Input
TMR0 Clock Input
To A/D Module Channel Input
To A/D Module Channel Input
DS39598F-page 40
I/O pin
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-5:
BLOCK DIAGRAM OF RA5/MCLR/VPP PIN
MCLRE
Schmitt Trigger
Buffer
MCLR Circuit
MCLR Filter
Data
Bus
RD TRIS VSS
RA5/MCLR/VPP
Schmitt Trigger
Input Buffer
Q
VSS
D
EN
MCLRE
RD Port
FIGURE 5-6:
BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN
From OSC1
CLKO (FOSC/4)
Oscillator
Circuit
VDD
VDD
P
RA6/OSC2/CLKO
Data
Bus
D
WR
PORTA
Q
CK
VSS
N
(FOSC = 1x1)
VSS
VDD
Q
P
Data Latch
D
WR
TRISA
Q
N
CK
Q
(FOSC = 1x0,011)
TRIS Latch
VSS
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
(FOSC = 1x0,011)
Note 1: I/O pins have protection diodes to VDD and VSS.
2: CLKO signal is 1/4 of the FOSC frequency.
2001-2013 Microchip Technology Inc.
DS39598F-page 41
PIC16F818/819
FIGURE 5-7:
BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN
From OSC2
Oscillator
Circuit
VDD
(FOSC = 011)
Data
Bus
D
WR
PORTA
CK
Q
VDD
Q
P
RA7/OSC1/CLKI
VSS
Data Latch
D
WR
TRISA
Q
N
CK
Q
FOSC = 10x
TRIS Latch
VSS
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
FOSC = 10x
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39598F-page 42
2001-2013 Microchip Technology Inc.
PIC16F818/819
5.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON).
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION_REG).
PORTB is multiplexed with several peripheral functions
(see Table 5-3). PORTB pins have Schmitt Trigger
input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISB as
the destination should be avoided. The user should
refer to the corresponding peripheral section for the
correct TRIS bit settings.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
2001-2013 Microchip Technology Inc.
DS39598F-page 43
PIC16F818/819
TABLE 5-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT
bit 0
TTL/ST(1) Input/output pin or external interrupt input.
Internal software programmable weak pull-up.
RB1/SDI/SDA
bit 1
TTL/ST(5) Input/output pin, SPI data input pin or I2C™ data I/O pin.
Internal software programmable weak pull-up.
RB2/SDO/CCP1
bit 2
TTL/ST(4) Input/output pin, SPI data output pin or
Capture input/Compare output/PWM output pin.
Internal software programmable weak pull-up.
RB3/CCP1/PGM(3)
bit 3
TTL/ST(2) Input/output pin, Capture input/Compare output/PWM output pin
or programming in LVP mode. Internal software programmable
weak pull-up.
RB4/SCK/SCL
bit 4
TTL/ST(5) Input/output pin or SPI and I2C clock pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/SS
bit 5
RB6/T1OSO/T1CKI/
PGC
bit 6
TTL/ST(2) Input/output pin, Timer1 oscillator output pin, Timer1 clock input pin or
serial programming clock (with interrupt-on-change).
Internal software programmable weak pull-up.
RB7/T1OSI/PGD
bit 7
TTL/ST(2) Input/output pin, Timer1 oscillator input pin or serial programming data
(with interrupt-on-change).
Internal software programmable weak pull-up.
Legend:
Note 1:
2:
3:
4:
5:
Input/output pin or SPI slave select pin (with interrupt-on-change).
Internal software programmable weak pull-up.
TTL = TTL input, ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
Low-Voltage ICSP™ Programming (LVP) is enabled by default which disables the RB3 I/O function. LVP
must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 18-pin
mid-range devices.
This buffer is a Schmitt Trigger input when configured for CCP or SSP mode.
This buffer is a Schmitt Trigger input when configured for SPI or I2C mode.
TABLE 5-4:
Address
TTL
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
06h, 106h PORTB
86h, 186h TRISB
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx uuuu uuuu
PSA
PS2
PS1
PS0 1111 1111 1111 1111
PORTB Data Direction Register
81h, 181h OPTION_REG RBPU
INTEDG
T0CS
T0SE
1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39598F-page 44
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-8:
BLOCK DIAGRAM OF RB0 PIN
VDD
RBPU(2)
Weak
P Pull-up
Data Bus
WR
PORTB
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
WR
TRISB
TTL
Input
Buffer
CK
RD TRISB
Q
D
RD PORTB
EN
To INT0 or CCP
RD PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
2001-2013 Microchip Technology Inc.
DS39598F-page 45
PIC16F818/819
FIGURE 5-9:
BLOCK DIAGRAM OF RB1 PIN
I2C™ Mode
Port/SSPEN Select
SDA Output
1
0
VDD
RBPU(2)
Data Bus
Weak
P Pull-up
D
WR
PORTB
VDD
Data Latch
Q
P
CK
N
I/O pin(1)
VSS
TRIS Latch
D
Q
WR
TRISB
CK
Q
RD TRISB
TTL
Input
Buffer
SDA Drive
Q
D
RD PORTB
EN
(3)
SDA
Schmitt Trigger
Buffer
RD PORTB
SDI
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
3: The SDA Schmitt Trigger conforms to the I2C specification.
DS39598F-page 46
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-10:
BLOCK DIAGRAM OF RB2 PIN
CCPMX
Module Select
SDO
0
0
CCP
1
1
VDD
RBPU(2)
Data Bus
WR
PORTB
WR
TRISB
Weak
P Pull-up
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
TTL
Input
Buffer
CK
RD TRISB
Q
RD PORTB
D
EN
RD PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
2001-2013 Microchip Technology Inc.
DS39598F-page 47
PIC16F818/819
FIGURE 5-11:
BLOCK DIAGRAM OF RB3 PIN
CCP1 = 1000, 1001, 11xx and CCPMX = 0
CCP1 = 0100, 0101, 0110, 0111 and CCPMX = 0
CCP
0
or LVP = 1
1
VDD
RBPU(2)
Data Bus
Weak
P Pull-up
Data Latch
D
Q
WR
PORTB
I/O pin(1)
CK
TRIS Latch
D
Q
WR
TRISB
TTL
Input
Buffer
CK
RD TRISB
Q
D
RD PORTB
EN
To PGM or CCP
RD PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
DS39598F-page 48
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-12:
BLOCK DIAGRAM OF RB4 PIN
Port/SSPEN
SCK/SCL
1
0
VDD
RBPU(2)
Weak
P Pull-up
VDD
SCL Drive
P
Data Latch
Data Bus
D
WR
PORTB
Q
TRIS Latch
D
Q
WR
TRISB
I/O pin(1)
N
CK
VSS
CK
TTL
Input
Buffer
RD TRISB
Latch
Q
D
Set RBIF
EN
RD PORTB
From other
RB7:RB4 pins
Q
Q1
D
RD PORTB
EN
Q3
SCK
SCL(3)
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
3: The SCL Schmitt Trigger conforms to the I2C™ specification.
2001-2013 Microchip Technology Inc.
DS39598F-page 49
PIC16F818/819
FIGURE 5-13:
BLOCK DIAGRAM OF RB5 PIN
RBPU(2)
VDD
Weak
P Pull-up
Port/SSPEN
Data Latch
D
Q
Data Bus
WR
PORTB
I/O pin(1)
CK
TRIS Latch
D
Q
WR
TRISB
CK
TTL
Input
Buffer
RD TRISB
Latch
Q
D
Set RBIF
EN
RD PORTB
From other
RB7:RB4 pins
Q
Q1
D
RD PORTB
EN
Q3
SS
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
DS39598F-page 50
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-14:
BLOCK DIAGRAM OF RB6 PIN
VDD
RBPU(2)
Weak
P Pull-up
Data Latch
D
Q
Data Bus
WR
PORTB
I/O pin(1)
CK
TRIS Latch
D
Q
WR
TRISB
CK
T1OSCEN
RD TRISB
T1OSCEN/ICD/
Program Mode
TTL
Input Buffer
Latch
Q
D
Set RBIF
EN
RD PORTB
From other
RB7:RB4 pins
Q
Q1
D
RD PORTB
EN
Q3
T1CKI/PGC
From T1OSO Output
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
2001-2013 Microchip Technology Inc.
DS39598F-page 51
PIC16F818/819
FIGURE 5-15:
BLOCK DIAGRAM OF RB7 PIN
Port/Program Mode/ICD
PGD
1
0
VDD
RBPU(2)
Data Bus
WR
PORTB
Weak
P Pull-up
Data Latch
D
Q
TRIS Latch
D
Q
WR
TRISB
I/O pin(1)
CK
CK
RD TRISB
T1OSCEN
PGD DRVEN
0
1
T1OSCEN
Analog
Input Mode
TTL
Input Buffer
Latch
Q
D
Set RBIF
From other
RB7:RB4 pins
EN
RD PORTB
Q
Q1
D
RD PORTB
EN
Q3
PGD
To T1OSI Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
DS39598F-page 52
2001-2013 Microchip Technology Inc.
PIC16F818/819
6.0
TIMER0 MODULE
Counter mode is selected by setting bit T0CS
(OPTION_REG). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/AN4/T0CKI. The incrementing edge is determined
by the Timer0 Source Edge Select bit, T0SE
(OPTION_REG). Clearing bit T0SE selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.3 “Using Timer0 with
an External Clock”.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt-on-overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 6.4
“Prescaler” details the operation of the prescaler.
Additional information on the Timer0 module is
available in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023).
6.2
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit, TMR0IF (INTCON). The interrupt can be
masked by clearing bit, TMR0IE (INTCON). Bit
TMR0IF must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the timer is shut-off during
Sleep.
Timer0 Operation
Timer0 operation is controlled through the
OPTION_REG register (see Register 2-2). Timer mode
is selected by clearing bit T0CS (OPTION_REG).
In Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
FIGURE 6-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKO (= FOSC/4)
Data Bus
0
8
M
U
X
1
0
1
RA4/AN4/T0CKI
pin
M
U
X
Sync
2
Cycles
TMR0 reg
T0SE
T0CS
Set Flag bit TMR0IF
on Overflow
PSA
PRESCALER
0
WDT Timer
1
M
U
X
8-bit Prescaler
8
31.25 kHz
8-to-1 MUX
WDT Enable bit
PS2:PS0
PSA
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG).
2001-2013 Microchip Technology Inc.
DS39598F-page 53
PIC16F818/819
6.3
Using Timer0 with an
External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.4
Timer0 module means that there is no prescaler for the
Watchdog Timer and vice versa. This prescaler is not
readable or writable (see Figure 6-1).
The PSA and PS2:PS0 bits (OPTION_REG)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF
1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
Note:
Prescaler
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
REGISTER 6-1:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
OPTION_REG: OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
1:2
000
1:1
1:4
001
1:2
1:8
010
1:4
1 : 16
011
1:8
1 : 32
100
1 : 16
1 : 64
101
1 : 32
1 : 128
110
1 : 64
1 : 256
111
1 : 128
Legend:
R = Readable bit
-n = Value at POR
Note:
DS39598F-page 54
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
To avoid an unintended device Reset, the instruction sequence shown in the “PIC®
Mid-Range MCU Family Reference Manual” (DS33023) must be executed when
changing the prescaler assignment from Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
2001-2013 Microchip Technology Inc.
PIC16F818/819
EXAMPLE 6-1:
BANKSEL
MOVLW
MOVWF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
CLRWDT
MOVLW
MOVWF
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
OPTION_REG
b'xx0x0xxx'
OPTION_REG
TMR0
TMR0
OPTION_REG
b'xxxx1xxx'
OPTION_REG
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
CLRWDT
BANKSEL OPTION_REG
MOVLW
b'xxxx0xxx'
MOVWF
OPTION_REG
TABLE 6-1:
01h,101h
Select Bank of OPTION_REG
Select clock source and prescale value of
other than 1:1
Select Bank of TMR0
Clear TMR0 and prescaler
Select Bank of OPTION_REG
Select WDT, do not change prescale value
; Clears WDT and prescaler
; Select new prescale value and WDT
b'xxxx1xxx'
OPTION_REG
EXAMPLE 6-2:
Address
;
;
;
;
;
;
;
;
;
;
;
Clear WDT and prescaler
Select Bank of OPTION_REG
Select TMR0, new prescale
value and clock source
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
0Bh,8Bh,
INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Timer0 Module Register
Value on
all other
Resets
xxxx xxxx
uuuu uuuu
GIE
PEIE
TMR0IE
INTE
RBIE TMR0IF
INTF
RBIF
0000 000x
0000 000u
RBPU
INTEDG
T0CS
T0SE
PSA
PS1
PS0
1111 1111
1111 1111
81h,181h
OPTION_REG
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
2001-2013 Microchip Technology Inc.
PS2
DS39598F-page 55
PIC16F818/819
NOTES:
DS39598F-page 56
2001-2013 Microchip Technology Inc.
PIC16F818/819
7.0
TIMER1 MODULE
The operating mode is determined by the clock select
bit, TMR1CS (T1CON).
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit, TMR1IF (PIR1). This interrupt can be
enabled/disabled by setting/clearing TMR1 Interrupt
Enable bit, TMR1IE (PIE1).
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
7.1
Timer1 Operation
Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON).
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP1 module as the special
event trigger (see Section 9.1 “Capture Mode”).
Register 7-1 shows the Timer1 Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB6/T1OSO/T1CKI/PGC and RB7/T1OSI/
PGD pins become inputs. That is, the TRISB
value is ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
Timer1 can operate in one of three modes:
• as a timer
• as a synchronous counter
• as an asynchronous counter
REGISTER 7-1:
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1
T1CKPS0
T1OSCEN
R/W-0
R/W-0
R/W-0
T1SYNC TMR1CS TMR1ON
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI/PGC (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39598F-page 57
PIC16F818/819
7.2
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR1CS
(T1CON) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit, T1SYNC
(T1CON), has no effect since the internal clock is
always in sync.
7.3
Timer1 Counter Operation
Timer1 may operate in Asynchronous or Synchronous
mode depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 7-1:
7.4
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RB7/T1OSI/PGD when bit
T1OSCEN is set, or on pin RB6/T1OSO/T1CKI/PGC
when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not
increment even if the external clock is present, since
the synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
TIMER1 INCREMENTING EDGE
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
FIGURE 7-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
TMR1H
Synchronized
Clock Input
0
TMR1
TMR1L
1
TMR1ON
On/Off
T1SYNC
T1OSC
1
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS1:T1CKPS0
Q Clock
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS39598F-page 58
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PIC16F818/819
7.5
Timer1 Operation in
Asynchronous Counter Mode
If control bit, T1SYNC (T1CON), is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow that will wake-up the
processor. However, special precautions in software
are needed to read/write the timer.
In Asynchronous Counter mode, Timer1 cannot be
used as a time base for capture or compare operations.
7.5.1
READING AND WRITING TIMER1
IN ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers while the
register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. The
example codes provided in Example 7-1 and
Example 7-2 demonstrate how to write to and read
Timer1 while it is running in Asynchronous mode.
EXAMPLE 7-1:
WRITING A 16-BIT FREE RUNNING TIMER
; All interrupts are disabled
CLRF
TMR1L
; Clear Low byte, Ensures no rollover into TMR1H
MOVLW
HI_BYTE
; Value to load into TMR1H
MOVWF
TMR1H, F
; Write High byte
MOVLW
LO_BYTE
; Value to load into TMR1L
MOVWF
TMR1H, F
; Write Low byte
; Re-enable the Interrupt (if required)
CONTINUE
; Continue with your code
EXAMPLE 7-2:
READING A 16-BIT FREE RUNNING TIMER
; All interrupts are disabled
MOVF
TMR1H, W
; Read high byte
MOVWF
TMPH
MOVF
TMR1L, W
; Read low byte
MOVWF
TMPL
MOVF
TMR1H, W
; Read high byte
SUBWF
TMPH, W
; Sub 1st read with 2nd read
BTFSC
STATUS, Z
; Is result = 0
GOTO
CONTINUE
; Good 16-bit read
; TMR1L may have rolled over between the read of the high and low bytes.
; Reading the high and low bytes now will read a good value.
MOVF
TMR1H, W
; Read high byte
MOVWF
TMPH
MOVF
TMR1L, W
; Read low byte
MOVWF
TMPL
; Re-enable the Interrupt (if required)
CONTINUE
; Continue with your code
2001-2013 Microchip Technology Inc.
DS39598F-page 59
PIC16F818/819
7.6
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON). The
oscillator is a low-power oscillator, rated up to
32.768 kHz. It will continue to run during Sleep. It is
primarily intended for a 32 kHz crystal. The circuit for a
typical LP oscillator is shown in Figure 7-3. Table 7-1
shows the capacitor selection for the Timer1 oscillator.
TABLE 7-1:
Osc Type
Freq
C1
C2
LP
32 kHz
33 pF
33 pF
Note 1: Microchip suggests this value as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
The user must provide a software time delay to ensure
proper oscillator start-up.
Note:
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
The Timer1 oscillator shares the T1OSI
and T1OSO pins with the PGD and PGC
pins used for programming and
debugging.
When using the Timer1 oscillator, In-Circuit
Serial Programming™ (ICSP™) may not
function correctly (high-voltage or lowvoltage) or the In-Circuit Debugger (ICD)
may not communicate with the controller.
As a result of using either ICSP or ICD, the
Timer1 crystal may be damaged.
If ICSP or ICD operations are required, the
crystal should be disconnected from the
circuit (disconnect either lead) or installed
after programming. The oscillator loading
capacitors may remain in-circuit during
ICSP or ICD operation.
FIGURE 7-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
PIC16F818/819
C1
33 pF
T1OSI
XTAL
32.768 kHz
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
4: Capacitor values are for design guidance
only.
7.7
Timer1 Oscillator Layout
Considerations
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 7-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator, a grounded guard ring around the oscillator circuit,
as shown in Figure 7-4, may be helpful when used on
a single-sided PCB or in addition to a ground plane.
FIGURE 7-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
T1OSO
C2
33 pF
Note:
See the Notes with Table 7-1 for additional
information about capacitor selection.
VSS
OSC1
OSC2
RB7
RB6
RB5
DS39598F-page 60
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PIC16F818/819
7.8
Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate
a
“special
event
trigger”
signal
(CCP1M3:CCP1M0 = 1011), the signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
7.9
Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other Reset, except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
7.10
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
2001-2013 Microchip Technology Inc.
7.11
Using Timer1 as a
Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 7.6 “Timer1 Oscillator”),
gives users the option to include RTC functionality in
their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base
and several lines of application code to calculate the
time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 7-3, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow, triggers the interrupt and calls
the routine which increments the seconds counter by
one; additional counters for minutes and hours are
incremented as the previous counter overflows.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to preload it; the simplest method is to set the MSb of TMR1H
with a BSF instruction. Note that the TMR1L register is
never preloaded or altered; doing so may introduce
cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1 = 1) as shown in the routine,
RTCinit. The Timer1 oscillator must also be enabled
and running at all times.
DS39598F-page 61
PIC16F818/819
EXAMPLE 7-3:
RTCinit
BANKSEL
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BANKSEL
BSF
RETURN
BANKSEL
BSF
BCF
INCF
MOVF
SUBLW
BTFSS
RETURN
CLRF
INCF
MOVF
SUBLW
BTFSS
RETURN
CLRF
INCF
MOVF
SUBLW
BTFSS
RETURN
CLRF
RETURN
RTCisr
TABLE 7-2:
Address
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
TMR1H
TMR1H, 7
PIR1, TMR1IF
secs, F
secs, w
.60
STATUS, Z
seconds
mins, f
mins, w
.60
STATUS, Z
mins
hours, f
hours, w
.24
STATUS, Z
hours
; Preload TMR1 register pair
; for 1 second overflow
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
; Enable Timer1 interrupt
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
;
;
;
;
60 seconds elapsed?
No, done
Clear seconds
Increment minutes
;
;
;
;
60 seconds elapsed?
No, done
Clear minutes
Increment hours
;
;
;
;
24 hours elapsed?
No, done
Clear hours
Done
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
0Bh,8Bh, INTCON
10Bh,18Bh
0Ch
TMR1H
0x80
TMR1H
TMR1L
b’00001111’
T1CON
secs
mins
.12
hours
PIE1
PIE1, TMR1IE
PIR1
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE -0-- 0000 -0-- 0000
8Ch
PIE1
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
10h
T1CON
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
DS39598F-page 62
2001-2013 Microchip Technology Inc.
PIC16F818/819
8.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP1 module. The TMR2 register is
readable and writable and is cleared on any device
Reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits,
T2CKPS1:T2CKPS0 (T2CON).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit,
TMR2IF (PIR1)).
8.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR, WDT
Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate a shift clock.
FIGURE 8-1:
Sets Flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
Output(1)
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON), to minimize power consumption.
Reset
TMR2 reg
Register 8-1 shows the Timer2 Control register.
Additional information on timer modules is available in
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
Postscaler
1:1 to 1:16
4
EQ
Comparator
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
PR2 reg
Note 1: TMR2 register output can be software
selected by the SSP module as a baud clock.
2001-2013 Microchip Technology Inc.
DS39598F-page 63
PIC16F818/819
REGISTER 8-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
TABLE 8-1:
Address
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name
0Bh, 8Bh, INTCON
10Bh, 18Bh
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE -0-- 0000 -0-- 0000
11h
TMR2
12h
T2CON
Timer2 Module Register
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h
PR2
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS39598F-page 64
Timer2 Period Register
1111 1111 1111 1111
2001-2013 Microchip Technology Inc.
PIC16F818/819
9.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP module’s input/output pin (CCP1) can be
configured as RB2 or RB3. This selection is set in bit 12
(CCPMX) of the Configuration Word register.
The Capture/Compare/PWM (CCP) module contains a
16-bit register that can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Table 9-1 shows the timer resources of the CCP
module modes.
Additional information on the CCP module is available
in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023) and in Application Note AN594, “Using
the CCP Module(s)” (DS00594).
TABLE 9-1:
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match which will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
REGISTER 9-1:
CCP MODE – TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCP1M3:CCP1M0: CCP1 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected);
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39598F-page 65
PIC16F818/819
9.1
9.1.2
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on the CCP1 pin. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB bit.
Note 1: If the CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
2: The TRISB bit (2 or 3) is dependent upon
the setting of configuration bit 12
(CCPMX).
FIGURE 9-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCP1IF
(PIR1)
Prescaler
1, 4, 16
CCPR1H
CCP1 pin
and
Edge Detect
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
9.1.3
An event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1), is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
CCPR1L
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1), clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
9.1.4
CCP PRESCALER
There are four prescaler settings specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 9-1:
CLRF
MOVLW
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
CCP1CON
;Load CCP1CON with this
;value
Capture
Enable
TMR1H
TMR1L
CCP1CON
Q’s
DS39598F-page 66
2001-2013 Microchip Technology Inc.
PIC16F818/819
9.2
9.2.1
Compare Mode
CCP PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the TRISB bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
Note 1: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the data
latch.
• Driven high
• Driven low
• Remains unchanged
2: The TRISB bit (2 or 3) is dependent upon
the setting of configuration bit 12
(CCPMX).
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
9.2.2
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
Special Event Trigger
Set Flag bit CCP1IF
(PIR1)
9.2.3
Q
S
R
TRISB
Output Enable
Output
Logic
Match
Comparator
TMR1H
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
CCPR1H CCPR1L
CCP1 pin
TIMER1 MODE SELECTION
9.2.4
TMR1L
CCP1CON
Mode Select
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
Special event trigger will:
• Reset Timer1 but not set interrupt flag bit, TMR1IF
(PIR1)
• Set GO/DONE bit (ADCON0) which starts an A/D
conversion
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1.
Note:
TABLE 9-2:
The special event trigger from the CCP1
module will not set interrupt flag bit,
TMR1IF (PIR1).
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh,8Bh
INTCON
10BH,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
Legend:
—
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
2001-2013 Microchip Technology Inc.
DS39598F-page 67
PIC16F818/819
9.3
9.3.1
PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3 “Setup
for PWM Operation”.
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
EQUATION 9-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON
Duty Cycle Registers
CCPR1L
CCPR1H (Slave)
9.3.2
R
Comparator
Q
CCP1 pin
TMR2
(Note 1)
S
TRISB
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
PWM PERIOD
The Timer2 postscaler (see Section 8.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON. The following equation is
used to calculate the PWM duty cycle in time.
EQUATION 9-2:
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time base.
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 9-4:
PWM OUTPUT
PWM Duty Cycle = (CCPR1L:CCP1CON) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON can be written to at any
time but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
Period
Duty Cycle
TMR2 = PR2
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
TMR2 = Duty Cycle
TMR2 = PR2
DS39598F-page 68
2001-2013 Microchip Technology Inc.
PIC16F818/819
9.3.3
The maximum PWM resolution (bits) for a given PWM
frequency is given by the following formula.
The following steps should be taken when configuring
the CCP module for PWM operation:
EQUATION 9-3:
FOSC
log FPWM
(
Resolution =
Note:
log(2)
SETUP FOR PWM OPERATION
1.
2.
)
bits
3.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
4.
5.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON bits.
Make the CCP1 pin an output by clearing the
TRISB bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
Note:
TABLE 9-3:
The TRISB bit (2 or 3) is dependant upon
the setting of configuration bit 12
(CCPMX).
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 9-4:
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
5.5
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh,8Bh
INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE -0-- 0000 -0-- 0000
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 Module Register
0000 0000 0000 0000
92h
PR2
Timer2 Module Period Register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
—
2001-2013 Microchip Technology Inc.
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
DS39598F-page 69
PIC16F818/819
NOTES:
DS39598F-page 70
2001-2013 Microchip Technology Inc.
PIC16F818/819
10.0
10.1
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The SSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional information on the SSP module can be found in the “PIC® MidRange MCU Family Reference Manual” (DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the I2C™ Multi-Master Environment”
(DS00578).
10.2
SPI Mode
This section contains register definitions
operational characteristics of the SPI module.
and
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
RB2/SDO/CCP1
RB1/SDI/SDA
RB4/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
RB5/SS
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON)
and the SSPSTAT register (SSPSTAT). These
control bits allow the following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock Edge (output data on rising/falling
edge of SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Note:
2001-2013 Microchip Technology Inc.
Before enabling the module in SPI Slave
mode, the state of the clock line (SCK)
must match the polarity selected for the
Idle state. The clock line can be observed
by reading the SCK pin. The polarity of the
Idle state is determined by the CKP bit
(SSPCON).
DS39598F-page 71
PIC16F818/819
REGISTER 10-1:
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
This bit must be cleared when SPI is used in Slave mode.
I2 C mode:
This bit must be maintained clear.
bit 6
CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON).
2C
I mode:
This bit must be maintained clear.
bit 5
D/A: Data/Address bit (I2C mode only)
In I2 C Slave mode:
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was address
bit 4
P: Stop bit(1) (I2C mode only)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3
S: Start bit(1) (I2C mode only)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2
R/W: Read/Write Information bit (I2C mode only)
Holds the R/W bit information following the last address match and is only valid from address
match to the next Start bit, Stop bit or ACK bit.
1 = Read
0 = Write
bit 1
UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (In I2 C mode only):
1 = Transmit in progress, SSPBUF is full (8 bits)
0 = Transmit complete, SSPBUF is empty
Note 1: This bit is cleared when the SSP module is disabled (i.e., the SSPEN bit is cleared).
Legend:
DS39598F-page 72
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
REGISTER 10-2:
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER 1 (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
1 = An attempt to write the SSPBUF register failed because the SSP module is busy
(must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master
mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
“don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit(1)
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note 1: In both modes, when enabled, these pins must be properly configured as input or
output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Transmit happens on falling edge, receive on rising edge. Idle state for clock is a high level.
0 = Transmit happens on rising edge, receive on falling edge. Idle state for clock is a low level.
In I2 C Slave mode:
SCK release control.
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = OSC/4
0001 = SPI Master mode, clock = OSC/16
0010 = SPI Master mode, clock = OSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1000, 1001, 1010, 1100, 1101 = Reserved
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39598F-page 73
PIC16F818/819
FIGURE 10-1:
SSP BLOCK DIAGRAM
(SPI MODE)
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, reinitialize the SSPCON
register and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISB register)
appropriately programmed. That is:
Internal
Data Bus
Read
Write
SSPBUF reg
•
•
•
•
•
SSPSR reg
RB1/SDI/SDA
Shift
Clock
bit 0
Note 1: When the SPI is in Slave mode
with the SS pin control enabled
(SSPCON = 0100), the SPI module
will reset if the SS pin is set to VDD.
RB2/SDO/
CCP1
SS Control
Enable
RB5/SS
2: If the SPI is used in Slave mode with
CKE = 1, then the SS pin control must be
enabled.
Edge
Select
3: When the SPI is in Slave mode
with the SS pin control enabled
(SSPCON = 0100), the state of the
SS pin can affect the state read back from
the TRISB bit. The peripheral OE
signal from the SSP module into PORTB
controls the state that is read back from
the TRISB bit. If read-modify-write
instructions, such as BSF are performed
on the TRISB register while the SS pin is
high, this will cause the TRISB bit to
be set, thus disabling the SDO output.
2
Clock Select
SSPM3:SSPM0
4
Edge
Select
RB4/SCK/
SCL
TMR2 Output
2
Prescaler TCY
4, 16, 64
TRISB
TABLE 10-1:
SDI must have TRISB set
SDO must have TRISB cleared
SCK (Master mode) must have TRISB cleared
SCK (Slave mode) must have TRISB set
SS must have TRISB set
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh,8Bh
INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h
TRISB
PORTB Data Direction Register
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
WCOL SSPOV SSPEN
94h
SSPSTAT
Legend:
SMP
CKE
D/A
1111 1111 1111 1111
CKP
P
SSPM3 SSPM2
S
R/W
xxxx xxxx uuuu uuuu
SSPM1
UA
SSPM0 0000 0000 0000 0000
BF
0000 0000 0000 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
DS39598F-page 74
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 10-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit 7
SDO
bit 6
bit 5
bit 2
bit 3
bit 4
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SDI (SMP = 1)
bit 7
bit 0
SSPIF
FIGURE 10-3:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (Optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit 7
SDO
bit 6
bit 5
bit 2
bit 3
bit 4
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SSPIF
FIGURE 10-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SSPIF
2001-2013 Microchip Technology Inc.
DS39598F-page 75
PIC16F818/819
10.3
SSP I 2C Mode Operation
The SSP module in I 2C mode fully implements all slave
functions, except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RB4/SCK/SCL pin, which is the clock (SCL) and the
RB1/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISB bits.
To ensure proper communication of the I2C Slave mode,
the TRIS bits (TRISx [SDA, SCL]) corresponding to the
I2C pins must be set to ‘1’. If any TRIS bits (TRISx)
of the port containing the I2C pins (PORTx [SDA, SCL])
are changed in software during I2C communication
using a Read-Modify-Write instruction (BSF, BCF), then
the I2C mode may stop functioning properly and I2C
communication may suspend. Do not change any of the
TRISx bits (TRIS bits of the port containing the I2C pins)
using the instruction BSF or BCF during I2C communication. If it is absolutely necessary to change the TRISx
bits during communication, the following method can be
used:
EXAMPLE 10-1:
MOVF
IORLW
ANDLW
TRISC, W
0x18
B’11111001’
MOVWF
TRISC
;
;
;
;
Example for an 18-pin part such as the PIC16F818/819
Ensures bits are ‘11’
Sets as output, but will not alter other bits
User can use their own logic here, such as IORLW, XORLW and ANDLW
The SSP module functions are enabled by setting SSP
Enable bit, SSPEN (SSPCON).
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON) allow
one of the following I 2C modes to be selected:
FIGURE 10-5:
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I 2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I 2C Firmware Controlled Master mode with Start
and Stop bit interrupts enabled, slave is Idle
SSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
Data Bus
Read
Write
RB4/SCK/
SCL
SSPBUF Reg
Shift
Clock
SSPSR Reg
RB1/
SDI/
SDA
MSb
LSb
Match Detect
Addr Match
SSPADD Reg
Start and
Stop Bit Detect
Set, Reset
S, P Bits
(SSPSTAT Reg)
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. Pull-up resistors
must be provided externally to the SCL and SDA pins
for proper operation of the I2C module.
Additional information on SSP I2C operation may be
found in the “PIC® Mid-Range MCU Family Reference
Manual” (DS33023).
The SSP module has five registers for I2C operation:
•
•
•
•
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) – Not directly
accessible
• SSP Address Register (SSPADD)
DS39598F-page 76
2001-2013 Microchip Technology Inc.
PIC16F818/819
10.3.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISB set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
The sequence of events for 10-bit address is as
follows, with steps 7-9 for slave-transmitter:
1.
2.
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and
then load the SSPBUF register with the received value
currently in the SSPSR register.
3.
Either or both of the following conditions will cause the
SSP module not to give this ACK pulse:
5.
a)
b)
The Buffer Full bit, BF (SSPSTAT), was set
before the transfer was received.
The overflow bit, SSPOV (SSPCON), was
set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF but bit, SSPIF (PIR1), is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the SSP
module, are shown in timing parameter #100 and
parameter #101.
10.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the eight bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF, is set.
An ACK pulse is generated.
SSP Interrupt Flag bit, SSPIF (PIR1), is set
(interrupt is generated if enabled) – on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave device. The five Most Significant
bits (MSbs) of the first address byte specify if this is a
10-bit address. Bit R/W (SSPSTAT) must specify a
write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘1111 0 A9 A8 0’, where A9 and A8 are the
two MSbs of the address.
2001-2013 Microchip Technology Inc.
4.
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address; if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
10.3.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
a no Acknowledge (ACK) pulse is given. An overflow
condition is indicated if either bit, BF (SSPSTAT), is
set or bit, SSPOV (SSPCON), is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
10.3.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RB4/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register which also loads the SSPSR register.
Then pin RB4/SCK/SCL should be enabled by setting
bit, CKP (SSPCON). The master device must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
device by stretching the clock. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 10-7).
DS39598F-page 77
PIC16F818/819
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
the data transfer is complete. When the ACK is latched
by the slave device, the slave logic is reset (resets
SSPSTAT register) and the slave device then monitors
for another occurrence of the Start bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register which also loads the SSPSR
register. Then pin RB4/SCK/SCL should be enabled by
setting bit, CKP.
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
TABLE 10-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR SSPBUF
Generate ACK Pulse
Set bit SSPIF
(SSP interrupt occurs if enabled)
BF
SSPOV
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
1
No
No
Yes
Note 1:
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
I 2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 10-6:
Receiving Address R/W = 0
Receiving Data
Receiving Data
ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
1
S
3
2
4
5
6
7
8
9
1
2
SSPIF (PIR1)
3
4
5
6
7
8
9
1
2
3
5
4
8
7
6
9
Cleared in software
BF (SSPSTAT)
P
Bus master
terminates
transfer
SSPBUF register is read
SSPOV (SSPCON)
Bit SSPOV is set because the SSPBUF register is still full
ACK is not sent
I 2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 10-7:
Receiving Address
A7
SDA
SCL
S
A6
1
2
Data is
Sampled
SSPIF (PIR1)
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
Cleared in software
BF (SSPSTAT)
CKP (SSPCON)
SSPBUF is written in software
From SSP Interrupt
Service Routine
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS39598F-page 78
2001-2013 Microchip Technology Inc.
PIC16F818/819
10.3.2
MASTER MODE OPERATION
10.3.3
Master mode operation is supported in firmware using
interrupt generation on the detection of the Start and
Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based
on the Start and Stop conditions. Control of the I 2C bus
may be taken when the P bit is set or the bus is Idle and
both the S and P bits are clear.
MULTI-MASTER MODE OPERATION
In Multi-Master mode operation, the interrupt generation on the detection of the Start and Stop conditions
allows the determination of when the bus is free. The
Stop (P) and Start (S) bits are cleared from a Reset or
when the SSP module is disabled. The Stop (P) and
Start (S) bits will toggle based on the Start and Stop
conditions. Control of the I 2C bus may be taken when
bit P (SSPSTAT) is set or the bus is Idle and both
the S and P bits clear. When the bus is busy, enabling
the SSP interrupt will generate the interrupt when the
Stop condition occurs.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB bit(s). The output level is always low,
irrespective of the value(s) in PORTB. So when
transmitting data, a ‘1’ data bit must have the
TRISB bit set (input) and a ‘0’ data bit must have
the TRISB bit cleared (output). The same scenario
is true for the SCL line with the TRISB bit. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I2C module.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISB). There are two stages
where this arbitration can be lost:
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt if enabled):
• Address Transfer
• Data Transfer
• Start condition
• Stop condition
• Data transfer byte transmitted/received
When the slave logic is enabled, the Slave device
continues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data
transfer stage, the device will need to retransfer the
data at a later time.
Master mode operation can be done with either the
Slave mode Idle (SSPM3:SSPM0 = 1011) or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Multi-Master mode operation,
see AN578, “Use of the SSP Module in the I2C™
Multi-Master Environment” (DS00578).
For more information on Master mode operation, see
AN554, “Software Implementation of I2C™ Bus
Master” (DS00554).
TABLE 10-3:
REGISTERS ASSOCIATED WITH I2C™ OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF CCP1IF TMR2IF TMR1IF
-0-- 0000
-0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE CCP1IE TMR2IE TMR1IE
-0-- 0000
-0-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD
Synchronous Serial Port (I2C™ mode) Address Register
0000 0000
0000 0000
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
94h
SSPSTAT
SMP(1)
CKE(1)
D/A
P
86h
TRISB
Legend:
Note 1:
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
PORTB Data Direction Register
UA
BF
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI mode.
Maintain these bits clear in I2C mode.
2001-2013 Microchip Technology Inc.
DS39598F-page 79
PIC16F818/819
NOTES:
DS39598F-page 80
2001-2013 Microchip Technology Inc.
PIC16F818/819
11.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has four registers:
The Analog-to-Digital (A/D) converter module has five
inputs for 18/20 pin devices.
The conversion of an analog input signal results in a
corresponding 10-bit digital number. The A/D module
has a high and low-voltage reference input that is
software selectable to some combination of VDD, VSS,
RA2 or RA3.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
REGISTER 11-1:
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 11-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 11-2, configures
the functions of the port pins. The port pins can be
configured as analog inputs (RA3 can also be a voltage
reference) or as digital I/Os.
Additional information on using the A/D module can be
found in the “PIC® Mid-Range MCU Family Reference
Manual” (DS33023).
ADCON0: A/D CONTROL REGISTER 0 (ADDRESS 1Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 0
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits
If ADCS2 = 0:
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
If ADCS2 = 1:
00 = FOSC/4
01 = FOSC/16
10 = FOSC/64
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (RA0/AN0)
001 = Channel 1 (RA1/AN1)
010 = Channel 2 (RA2/AN2)
011 = Channel 3 (RA3/AN3)
100 = Channel 4 (RA4/AN4)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the
A/D conversion is complete)
bit 1
Unimplemented: Read as ‘0’
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
2001-2013 Microchip Technology Inc.
x = Bit is unknown
DS39598F-page 81
PIC16F818/819
REGISTER 11-2:
ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified, 6 Most Significant bits of ADRESH are read as ‘0’
0 = Left justified, 6 Least Significant bits of ADRESL are read as ‘0’
bit 6
ADCS2: A/D Clock Divide by 2 Select bit
1 = A/D clock source is divided by 2 when system clock is used
0 = Disabled
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
PCFG: A/D Port Configuration Control bits
PCFG
AN4
AN3
AN2
AN1
AN0
VREF+
VREF-
C/R
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
AVDD
AN3
AVDD
AN3
AVDD
AN3
AVDD
AN3
AVDD
AN3
AN3
AN3
AN3
AVDD
AN3
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AN2
AVSS
AVSS
AN2
AN2
AN2
AVSS
AN2
5/0
4/1
5/0
4/1
3/0
2/1
0/0
3/2
5/0
4/1
3/2
3/2
2/2
1/0
1/2
VREF+
A
VREF+
A
VREF+
D
VREF+
A
VREF+
VREF+
VREF+
VREF+
D
VREF+
VREFA
A
VREFVREFVREFD
VREF-
A = Analog input
D = Digital I/O
C/R = Number of analog input channels/Number of A/D voltage references
Legend:
DS39598F-page 82
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
2001-2013 Microchip Technology Inc.
PIC16F818/819
The ADRESH:ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is
complete, the result is loaded into the A/D Result register
pair, the GO/DONE bit (ADCON0) is cleared and
A/D Interrupt Flag bit, ADIF, is set. The block diagram of
the A/D module is shown in Figure 11-1.
These steps should be followed for doing an A/D
conversion:
1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
2.
To determine sample time, see Section 11.1 “A/D
Acquisition Requirements”. After this sample time
has elapsed, the A/D conversion can be started.
3.
4.
5.
6.
7.
FIGURE 11-1:
Configure the A/D module:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
• Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
A/D BLOCK DIAGRAM
CHS
100
RA4/AN4/T0CKI
011
RA3/AN3/VREF+
010
RA2/AN2/VREF-
VIN
(Input Voltage)
001
RA1/AN1
AVDD
A/D
Converter
000
RA0/AN0
VREF+
(Reference
Voltage)
PCFG
VREF(Reference
Voltage)
AVSS
PCFG
2001-2013 Microchip Technology Inc.
DS39598F-page 83
PIC16F818/819
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The maximum recommended impedance for analog sources is 2.5 k. As the impedance
is decreased, the acquisition time may be decreased.
EQUATION 11-1:
TACQ
TC
TACQ
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the “PIC® Mid-Range MCU Family Reference Manual”
(DS33023).
ACQUISITION TIME
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2 s + TC + [(Temperature – 25°C)(0.05 s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
-120 pF (1 k + 7 k + 10 k) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25C)(0.05 s/C)
19.72 s
Note 1: The reference voltage (VREF) has no effect on the equation since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD
RS
VA
ANx
CPIN
5 pF
VT = 0.6V
VT = 0.6V
Sampling
Switch
RIC 1K SS RSS
CHOLD
= DAC Capacitance
= 120 pF
ILEAKAGE
± 500 nA
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
ILEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
DS39598F-page 84
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(k)
2001-2013 Microchip Technology Inc.
PIC16F818/819
11.2
Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.0 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. The seven possible options for TAD are:
•
•
•
•
•
•
•
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal A/D module RC oscillator (2-6 s)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
as small as possible, but no less than 1.6 s and not
greater than 6.4 s.
11.3
The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS bits and the TRIS bits.
Note 1: When reading the Port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to
consume current out of the device
specification.
Table 11-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 11-1:
Configuring Analog Port Pins
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (F))
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS
ADCS
2 TOSC
0
00
1.25 MHz
4 TOSC
1
00
2.5 MHz
8 TOSC
0
01
5 MHz
TOSC
1
01
10 MHz
32 TOSC
0
10
20 MHz
64 TOSC
1
10
20 MHz
RC(1,2,3)
X
11
(Note 1)
16
Note 1:
2:
3:
The RC source has a typical TAD time of 4 s but can vary between 2-6 s.
When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for Sleep operation.
For extended voltage devices (LF), please refer to Section 15.0 “Electrical Characteristics”.
2001-2013 Microchip Technology Inc.
DS39598F-page 85
PIC16F818/819
11.4
11.4.1
A/D Conversions
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16 bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result
justification. The extra bits are loaded with ‘0’s. When
an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2-TAD wait is required before the next
acquisition is started. After this 2-TAD wait, acquisition
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of TCY and a maximum of TAD.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 11-3:
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b9
b8
b7
b6
b5
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
Conversion starts
Holding Capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
FIGURE 11-4:
ADRES is loaded,
GO bit is cleared,
ADIF bit is set,
Holding Capacitor is connected to analog input
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 0
ADFM = 1
7
0
2107
7
0765
0000 00
ADRESH
0000 00
ADRESL
10-bit Result
Right Justified
DS39598F-page 86
0
ADRESH
ADRESL
10-bit Result
Left Justified
2001-2013 Microchip Technology Inc.
PIC16F818/819
11.5
A/D Operation During Sleep
11.6
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers
is not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
11.7
Turning off the A/D places the A/D module in its lowest
current consumption state.
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction immediately follows the
instruction that sets the GO/DONE bit.
TABLE 11-2:
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0
bits
(CCP1CON)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the
ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the
minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Note:
Effects of a Reset
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module but will still reset the Timer1 counter.
REGISTERS/BITS ASSOCIATED WITH A/D
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh,8Bh
INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF TMR1IF -0-- 0000
-0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE TMR1IE -0-- 0000
-0-- 0000
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
1Fh
ADCON0 ADCS1 ADCS0
0000 00-0
0000 00-0
9Fh
ADCON1
05h
PORTA
CHS2
CHS1
CHS0 GO/DONE
—
ADON
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
00-- 0000
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxx0 0000
uuu0 0000
1111 1111
1111 1111
85h
TRISA
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
TRISA7 TRISA6 TRISA5 PORTA Data Direction Register
2001-2013 Microchip Technology Inc.
DS39598F-page 87
PIC16F818/819
NOTES:
DS39598F-page 88
2001-2013 Microchip Technology Inc.
PIC16F818/819
12.0
SPECIAL FEATURES OF
THE CPU
These devices have a host of features intended to
maximize system reliability, minimize cost through elimination of external components, provide power-saving
operating modes and offer code protection:
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT)
which provides a fixed delay of 72 ms (nominal) on
power-up only. It is designed to keep the part in Reset
while the power supply stabilizes and is enabled or
disabled using a configuration bit. With these two
timers on-chip, most applications need no external
Reset circuitry.
2001-2013 Microchip Technology Inc.
Sleep mode is designed to offer a very low-current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. Configuration bits are used to select the
desired oscillator mode.
Additional information on special features is available
in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023).
12.1
Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
in program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space which can be accessed
only during programming.
DS39598F-page 89
PIC16F818/819
REGISTER 12-1:
R/P-1
R/P-1
CONFIGURATION WORD (ADDRESS 2007h)(1)
R/P-1
R/P-1
R/P-1 R/P-1 R/P-1 R/P-1
CP CCPMX DEBUG WRT1 WRT0 CPD
bit 13
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 3
bit 2
bit 4, 1-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0
bit 0
CP: Flash Program Memory Code Protection bit
1 = Code protection off
0 = All memory locations code-protected
CCPMX: CCP1 Pin Selection bit
1 = CCP1 function on RB2
0 = CCP1 function on RB3
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
WRT1:WRT0: Flash Program Memory Write Enable bits
For PIC16F818:
11 = Write protection off
10 = 000h to 01FF write-protected, 0200 to 03FF may be modified by EECON control
01 = 000h to 03FF write-protected
For PIC16F819:
11 = Write protection off
10 = 0000h to 01FFh write-protected, 0200h to 07FFh may be modified by EECON control
01 = 0000h to 03FFh write-protected, 0400h to 07FFh may be modified by EECON control
00 = 0000h to 05FFh write-protected, 0600h to 07FFh may be modified by EECON control
CPD: Data EE Memory Code Protection bit
1 = Code protection off
0 = Data EE memory locations code-protected
LVP: Low-Voltage Programming Enable bit
1 = RB3/PGM pin has PGM function, Low-Voltage Programming enabled
0 = RB3/PGM pin has digital I/O function, HV on MCLR must be used for programming
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
MCLRE: RA5/MCLR/VPP Pin Function Select bit
1 = RA5/MCLR/VPP pin function is MCLR
0 = RA5/MCLR/VPP pin function is digital I/O, MCLR internally tied to VDD
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC2:FOSC0: Oscillator Selection bits
111 = EXTRC oscillator; CLKO function on RA6/OSC2/CLKO pin
110 = EXTRC oscillator; port I/O function on RA6/OSC2/CLKO pin
101 = INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on
RA7/OSC1/CLKI pin
100 = INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin
011 = EXTCLK; port I/O function on RA6/OSC2/CLKO pin
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Note 1: The erased (unprogrammed) value of the Configuration Word is 3FFFh.
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
DS39598F-page 90
U = Unimplemented bit, read as ‘1’
u = Unchanged from programmed state
2001-2013 Microchip Technology Inc.
PIC16F818/819
12.2
Reset
The PIC16F818/819 differentiates between various
kinds of Reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset during normal operation
WDT wake-up during Sleep
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brownout Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations as indicated in
Table 12-3. These bits are used in software to
determine the nature of the Reset. Upon a POR, BOR
or wake-up from Sleep, the CPU requires
approximately 5-10 s to become ready for code
execution. This delay runs in parallel with any other
timers. See Table 12-4 for a full description of Reset
states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 12-1.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
WDT
WDT
Module
Sleep
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
BOREN
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
PWRT
INTRC
31.25 kHz
10-bit Ripple Counter
Enable PWRT
Enable OST
2001-2013 Microchip Technology Inc.
DS39598F-page 91
PIC16F818/819
12.3
MCLR
12.5
PIC16F818/819 device has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR and excessive current beyond
the device specification during the ESD event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an
RC network, as shown in Figure 12-2, is suggested.
The RA5/MCLR/VPP pin can be configured for MCLR
(default) or as an I/O pin (RA5). This is configured
through the MCLRE bit in the Configuration Word
register.
FIGURE 12-2:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC16F818/819
R1
1 k (or greater)
MCLR
C1
0.1 F
(optional, not critical)
12.4
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V-1.7V). To take
advantage of the POR, tie the MCLR pin to VDD as
described in Section 12.3 “MCLR”. A maximum rise
time for VDD is specified. See Section 15.0 “Electrical
Characteristics” for details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating conditions are
met. For more information, see Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC16F818/819 is
a counter that uses the INTRC oscillator as the clock
input. This yields a count of 72 ms. While the PWRT is
counting, the device is held in Reset.
The power-up time delay depends on the INTRC and
will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing configuration bit,
PWRTEN.
12.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (if enabled). This helps to ensure
that the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
Sleep.
12.7
Brown-out Reset (BOR)
The configuration bit, BOREN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter #D005, about 4V) for longer than TBOR
(parameter #35, about 100 s), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a Reset may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer (if enabled) will keep the device in
Reset for TPWRT (parameter #33, about 72 ms). If VDD
should fall below VBOR during TPWRT, the Brown-out
Reset process will restart when VDD rises above VBOR
with the Power-up Timer Reset. Unlike previous PIC16
devices, the PWRT is no longer automatically enabled
when the Brown-out Reset circuit is enabled. The
PWRTEN and BOREN configuration bits are
independent of each other.
12.8
Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR occurs.
Then, OST starts counting 1024 oscillator cycles when
PWRT ends (LP, XT, HS). When the OST ends, the
device comes out of Reset.
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC16F818/819 device operating in
parallel.
Table 12-3 shows the Reset conditions for the Status,
PCON and PC registers, while Table 12-4 shows the
Reset conditions for all the registers.
DS39598F-page 92
2001-2013 Microchip Technology Inc.
PIC16F818/819
12.9
Power Control/Status Register
(PCON)
bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable.
The Power Control/Status register, PCON, has two bits
to indicate the type of Reset that last occurred.
Bit 1 is Power-on Reset Status bit, POR. It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
Bit 0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent Resets to see if
TABLE 12-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator
Configuration
PWRTE = 1
Wake-up
from Sleep
TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC
1024 • TOSC
PWRTE = 0
XT, HS, LP
EXTRC, EXTCLK, INTRC
Note 1:
Brown-out Reset
TPWRT
PWRTE = 1
5-10 s(1)
PWRTE = 0
TPWRT
5-10 s(1)
5-10 s(1)
CPU start-up is always invoked on POR, BOR and wake-up from Sleep.
TABLE 12-2:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during Sleep or interrupt wake-up from Sleep
Legend: u = unchanged, x = unknown
TABLE 12-3:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
Status
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during Sleep
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --u0
uuu1 0uuu
---- --uu
Condition
WDT wake-up
Brown-out Reset
Interrupt wake-up from Sleep
(1)
PC + 1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2001-2013 Microchip Technology Inc.
DS39598F-page 93
PIC16F818/819
TABLE 12-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset
Wake-up via WDT or
Interrupt
W
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
N/A
N/A
N/A
TMR0
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000h
0000h
PC + 1(2)
STATUS
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
xxx0 0000
uuu0 0000
uuuu uuuu
PORTB
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
---0 0000
---0 0000
---u uuuu
INTCON
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
-0-- 0000
-0-- 0000
-u-- uuuu(1)
PIR2
---0 ------0 ------u ----(1)
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
--00 0000
--uu uuuu
--uu uuuu
TMR2
0000 0000
0000 0000
uuuu uuuu
T2CON
-000 0000
-000 0000
-uuu uuuu
SSPBUF
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
0000 0000
0000 0000
uuuu uuuu
CCPR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
--00 0000
--00 0000
--uu uuuu
ADRESH
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
1111 1111
1111 1111
uuuu uuuu
TRISA
1111 1111
1111 1111
uuuu uuuu
TRISB
1111 1111
1111 1111
uuuu uuuu
PIE1
-0-- 0000
-0-- 0000
-u-- uuuu
PIE2
---0 ------0 ------u ---PCON
---- --qq
---- --uu
---- --uu
OSCCON
-000 -0--000 -0--uuu -u-OSCTUNE
--00 0000
--00 0000
--uu uuuu
PR2
1111 1111
1111 1111
1111 1111
SSPADD
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
0000 0000
0000 0000
uuuu uuuu
ADRESL
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
00-- 0000
00-- 0000
uu-- uuuu
EEDATA
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATH
--xx xxxx
--uu uuuu
--uu uuuu
EEADRH
---- -xxx
---- -uuu
---- -uuu
EECON1
x--x x000
u--x u000
u--u uuuu
EECON2
---- ------- ------- ---Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition,
r = reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 12-3 for Reset value for specific conditions.
DS39598F-page 94
2001-2013 Microchip Technology Inc.
PIC16F818/819
FIGURE 12-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
PULL-UP RESISTOR)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
2001-2013 Microchip Technology Inc.
DS39598F-page 95
PIC16F818/819
FIGURE 12-6:
SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
5V
VDD
1V
0V
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
12.10 Interrupts
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The PIC16F818/819 has up to nine sources of interrupt. The Interrupt Control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
Note:
The peripheral interrupt flags are contained in the
Special Function Register, PIR1. The corresponding
interrupt enable bits are contained in Special Function
Register, PIE1 and the peripheral interrupt enable bit is
contained in Special Function Register, INTCON.
Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
When an interrupt is serviced, the GIE bit is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid
recursive interrupts.
A Global Interrupt Enable bit, GIE (INTCON),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs relative to
the current Q cycle. The latency is the same for one or
two-cycle instructions. Individual interrupt flag bits are
set regardless of the status of their corresponding
mask bit, PEIE bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-7:
INTERRUPT LOGIC
EEIF
EEIE
TMR0IF
TMR0IE
ADIF
ADIE
INTF
INTE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR1IF
TMR1IE
Wake-up (if in Sleep mode)
Interrupt to CPU
RBIF
RBIE
PEIE
GIE
TMR2IF
TMR2IE
DS39598F-page 96
2001-2013 Microchip Technology Inc.
PIC16F818/819
12.10.1
INT INTERRUPT
12.10.3
External interrupt on the RB0/INT pin is edge triggered,
either rising if bit INTEDG (OPTION_REG) is set,
or falling if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit, INTF
(INTCON), is set. This interrupt can be disabled by
clearing enable bit, INTE (INTCON). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from Sleep if bit INTE
was set prior to going into Sleep. The status of Global
Interrupt Enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 12.13 “Power-Down Mode
(Sleep)” for details on Sleep mode.
12.10.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set
flag bit, TMR0IF (INTCON). The interrupt can be
enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON) (see Section 6.0 “Timer0
Module”).
EXAMPLE 12-1:
PORTB INTCON CHANGE
An input change on PORTB sets flag bit, RBIF
(INTCON). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON). See
Section 3.2 “EECON1 and EECON2 Registers”.
12.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (i.e., W, Status registers).
This will have to be implemented in software as shown
in Example 12-1.
For PIC16F818 devices, the upper 64 bytes of each
bank are common. Temporary holding registers,
W_TEMP and STATUS_TEMP, should be placed here.
These 64 locations do not require banking and
therefore, make it easier for context save and restore.
For PIC16F819 devices, the upper 16 bytes of each
bank are common.
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
:
:(ISR)
:
SWAPF
W_TEMP
STATUS, W
STATUS
STATUS_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP, F
W_TEMP, W
;Copy
;Swap
;bank
;Save
W to TEMP register
status to be saved into W
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
;Insert user code here
STATUS_TEMP, W
2001-2013 Microchip Technology Inc.
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
DS39598F-page 97
PIC16F818/819
12.12 Watchdog Timer (WDT)
WDT time-out period values may be found in
Section 15.0 “Electrical Characteristics” under
parameter #31. Values for the WDT prescaler (actually
a postscaler but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
For PIC16F818/819 devices, the WDT is driven by the
INTRC oscillator. When the WDT is enabled, the
INTRC (31.25 kHz) oscillator is enabled. The nominal
WDT period is 16 ms and has the same accuracy as
the INTRC oscillator.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler if
assigned to the WDT and prevent it from
timing out and generating a device Reset
condition.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog
Timer wake-up). The TO bit in the Status register will be
cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared but the
prescaler assignment is not changed.
The WDT can be permanently disabled by clearing configuration bit, WDTEN (see Section 12.1 “Configuration
Bits”).
FIGURE 12-8:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
1
INTRC
31.25 kHz
Postscaler
M
U
X
8
PS2:PS0
8-to-1 MUX
PSA
WDT
Enable Bit
To TMR0 (Figure 6-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-5:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
81h,181h OPTION_REG
2007h
Configuration bits
(1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
LVP
BOREN
MCLRE
FOSC2
PWRTEN
WDTEN
FOSC1
FOSC0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
DS39598F-page 98
2001-2013 Microchip Technology Inc.
PIC16F818/819
12.13 Power-Down Mode (Sleep)
Power-Down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (Status) is cleared, the
TO (Status) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are high-impedance inputs, high or low externally,
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for
lowest current consumption. The contribution from
on-chip pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
peripheral interrupt.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the Status register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred and caused
wake-up.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the
execution of the instruction following SLEEP is not
desirable, the user should have a NOP after the SLEEP
instruction.
12.13.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in Slave mode (SPI/I2C).
A/D conversion (when A/D clock source is RC).
EEPROM write operation completion.
2001-2013 Microchip Technology Inc.
DS39598F-page 99
PIC16F818/819
FIGURE 12-9:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKO(4)
INT pin
INTF Flag
(INTCON)
Interrupt Latency
(Note 2)
GIE bit
(INTCON)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
Instruction
Inst(PC)
= Sleep
Fetched
Instruction
Inst(PC – 1)
Executed
Note
1:
2:
3:
4:
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
CLKO is not available in these oscillator modes but shown here for timing reference.
12.14 In-Circuit Debugger
When the DEBUG bit in the Configuration Word is
programmed to a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging
functions when used with MPLAB® ICD. When the
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 12-6
shows which features are consumed by the background
debugger.
TABLE 12-6:
DEBUGGER RESOURCES
I/O pins
Stack
RB6, RB7
1 level
Program Memory
Address 0000h must be NOP
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB-0x1EF
12.15 Program Verification/Code
Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
12.16 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. It is
recommended that only the four Least Significant bits
of the ID location are used.
Last 100h words
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the in-circuit
debugger module available from Microchip or one of
the third party development tool companies.
DS39598F-page 100
2001-2013 Microchip Technology Inc.
PIC16F818/819
12.17 In-Circuit Serial Programming
PIC16F818/819 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage (see Figure 12-10 for an example). This allows
customers to manufacture boards with unprogrammed
devices and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be
programmed.
For more information on serial programming, please refer
to the “PIC16F818/819 Flash Memory Programming
Specification” (DS39603).
Note:
The Timer1 oscillator shares the T1OSI
and T1OSO pins with the PGD and PGC
pins used for programming and
debugging.
When using the Timer1 oscillator, In-Circuit
Serial Programming™ (ICSP™) may not
function correctly (high voltage or low
voltage) or the In-Circuit Debugger (ICD)
may not communicate with the controller.
As a result of using either ICSP or ICD, the
Timer1 crystal may be damaged.
FIGURE 12-10:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
*
PIC16F818/819
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
RB3†
RB3/PGM
*
*
*
VDD
To Normal
Connections
* Isolation devices (as required).
†
RB3 only used in LVP mode.
If ICSP or ICD operations are required, the
crystal should be disconnected from the
circuit (disconnect either lead) or installed
after programming. The oscillator loading
capacitors may remain in-circuit during
ICSP or ICD operation.
2001-2013 Microchip Technology Inc.
DS39598F-page 101
PIC16F818/819
12.18 Low-Voltage ICSP Programming
The LVP bit of the Configuration Word register enables
Low-Voltage ICSP Programming. This mode allows the
microcontroller to be programmed via ICSP using a
VDD source in the operating voltage range. This only
means that VPP does not have to be brought to VIHH but
can instead be left at the normal operating voltage. In
this mode, the RB3/PGM pin is dedicated to the
programming function and ceases to be a general
purpose I/O pin.
If Low-Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be
programmed when Programming mode is entered with
VIHH on MCLR. The LVP bit can only be changed when
using high voltage on MCLR.
It should be noted that once the LVP bit is programmed
to ‘0’, only the High-Voltage Programming mode is
available and only this mode can be used to program
the device.
When using Low-Voltage ICSP, the part must be
supplied at 4.5V to 5.5V if a bulk erase will be executed.
This includes reprogramming of the code-protect bits
from an ON state to an OFF state. For all other cases of
Low-Voltage ICSP, the part may be programmed at the
normal operating voltage. This means calibration values,
unique user IDs or user code can be reprogrammed or
added.
Note 1: The High-Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low-Voltage ICSP mode
(LVP = 1), the RB3 pin can no longer be
used as a general purpose I/O pin.
3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
4: RB3 should not be allowed to float if LVP
is enabled. An external pull-down device
should be used to default the device to
normal operating mode. If RB3 floats
high, the PIC16F818/819 device will
enter Programming mode.
5: LVP mode is enabled by default on all
devices shipped from Microchip. It can be
disabled by clearing the LVP bit in the
Configuration Word register.
6: Disabling LVP will provide maximum
compatibility to other PIC16CXXX
devices.
The following LVP steps assume the LVP bit is set in the
Configuration Word register.
1.
2.
3.
4.
5.
Apply VDD to the VDD pin.
Drive MCLR low.
Apply VDD to the RB3/PGM pin.
Apply VDD to the MCLR pin.
Follow with the associated programming steps.
DS39598F-page 102
2001-2013 Microchip Technology Inc.
PIC16F818/819
13.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
are presented in Figure 13-1, while the various opcode
fields are summarized in Table 13-1.
Table 13-2 lists the instructions recognized by the
MPASMTM assembler. A complete description of each
instruction is also available in the “PIC® Mid-Range
MCU Family Reference Manual” (DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which
the bit is located.
For literal and control operations, ‘k’ represents an
eight or eleven-bit constant or literal value
One instruction cycle consists of four oscillator periods.
For an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions
are executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
Note:
To maintain upward compatibility with
future PIC16F818/819 products, do not
use the OPTION and TRIS instructions.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
13.1
READ-MODIFY-WRITE
OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator ‘d’. A read operation is
performed on a register even if the instruction writes to
that register.
2001-2013 Microchip Technology Inc.
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the
unintended result that the condition that sets the RBIF
flag would be cleared.
TABLE 13-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
PD
Power-Down bit
FIGURE 13-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
DS39598F-page 103
PIC16F818/819
TABLE 13-2:
PIC16F818/819 INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
1
1
1
1
1 (2)
1
1 (2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
Note 1:
2:
3:
Note:
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
Additional information on the mid-range instruction set is available in the “PIC® Mid-Range MCU Family
Reference Manual” (DS33023).
DS39598F-page 104
2001-2013 Microchip Technology Inc.
PIC16F818/819
13.2
Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
AND W with f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0 k 255
Operands:
0 f 127
d [0,1]
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Operation:
(W) .AND. (f) (destination)
Description:
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
Status Affected:
Z
Description:
AND the W register with register
‘f’. If ‘d’ = 0, the result is stored in
the W register. If ‘d’ = 1, the result
is stored back in register ‘f’.
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BCF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
0b7
Operation:
(W) + (f) (destination)
Operation:
0 (f)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ = 0, the result
is stored in the W register. If
‘d’ = 1, the result is stored back in
register ‘f’.
Description:
Bit ‘b’ in register ‘f’ is cleared.
ANDLW
AND Literal with W
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
k
f,d
f,b
Syntax:
[ label ] ANDLW
Operands:
0 k 255
Operation:
(W) .AND. (k) (W)
Status Affected:
Z
Operation:
1 (f)
Description:
The contents of W register are
ANDed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
2001-2013 Microchip Technology Inc.
k
f,d
f,b
DS39598F-page 105
PIC16F818/819
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
Operands:
0 f 127
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2001-2013 Microchip Technology Inc.
DS39598F-page 163
PIC16F818/819
NOTES:
DS39598F-page 164
2001-2013 Microchip Technology Inc.
PIC16F818/819
APPENDIX A:
REVISION HISTORY
Revision A (May 2002)
Original version of this data sheet.
Revision B (August 2002)
Added INTRC section. PWRT and BOR are independent of each other. Revised program memory text and
code routine. Added QFN package. Modified PORTB
diagrams.
Revision D (November 2003)
Updated IRCF bit modification information and changed
the INTOSC stabilization delay from 1 ms to 4 ms in
Section 4.0 “Oscillator Configurations”. Updated
Section 12.17 “In-Circuit Serial Programming” to
clarify LVP programming. In Section 15.0 “Electrical
Characteristics”, the DC Characteristics (Section 15.2
and Section 15.3) have been updated to include the
Typ, Min and Max values and Table 15-1 “External
Clock Timing Requirements” has been updated.
Revision E (September 2004)
Revision C (November 2002)
Added various new feature descriptions. Added internal RC oscillator specifications. Added low-power
Timer1 specifications and RTC application example.
This revision includes the DC and AC Characteristics
Graphs and Tables. The Electrical Specifications in
Section 16.0 “DC and AC Characteristics Graphs
and Tables” have been updated and there have been
minor corrections to the data sheet text.
Revision F (November 2011)
This revision updated Section 17.0 “Packaging Information”.
APPENDIX B:
DEVICE DIFFERENCES
The differences between the devices in this data sheet are listed in Table B-1.
TABLE B-1:
DIFFERENCES BETWEEN THE PIC16F818 AND PIC16F819
Features
PIC16F818
PIC16F819
Flash Program Memory (14-bit words)
1K
2K
Data Memory (bytes)
128
256
EEPROM Data Memory (bytes)
128
256
2001-2013 Microchip Technology Inc.
DS39598F-page 165
PIC16F818/819
NOTES:
DS39598F-page 166
2001-2013 Microchip Technology Inc.
PIC16F818/819
INDEX
A
A/D
Acquisition Requirements .......................................... 84
ADIF Bit ...................................................................... 83
Analog-to-Digital Converter ........................................ 81
Associated Registers ................................................. 87
Calculating Acquisition Time ...................................... 84
Configuring Analog Port Pins ..................................... 85
Configuring the Interrupt ............................................ 83
Configuring the Module .............................................. 83
Conversion Clock ....................................................... 85
Conversion Requirements ....................................... 140
Conversions ............................................................... 86
Converter Characteristics ........................................ 139
Delays ........................................................................ 84
Effects of a Reset ....................................................... 87
GO/DONE Bit ............................................................. 83
Internal Sampling Switch (Rss) Impedance ............... 84
Operation During Sleep ............................................. 87
Result Registers ......................................................... 86
Source Impedance ..................................................... 84
Time Delays ............................................................... 84
Use of the CCP Trigger .............................................. 87
Absolute Maximum Ratings ............................................. 115
ACK .................................................................................... 77
ADCON0 Register .............................................................. 81
ADCON1 Register .............................................................. 81
ADRESH Register ........................................................ 13, 81
ADRESH, ADRESL Register Pair ...................................... 83
ADRESL Register ........................................................ 14, 81
Application Notes
AN556 (Implementing a Table Read) ........................ 23
AN578 (Use of the SSP Module in the I2C
Multi-Master Environment) ................................. 71
AN607 (Power-up Trouble Shooting) ......................... 92
Assembler
MPASM Assembler .................................................. 112
B
BF Bit ................................................................................. 77
Block Diagrams
A/D ............................................................................. 83
Analog Input Model .................................................... 84
Capture Mode Operation ........................................... 66
Compare Mode Operation ......................................... 67
In-Circuit Serial Programming Connections ............. 101
Interrupt Logic ............................................................ 96
On-Chip Reset Circuit ................................................ 91
PIC16F818/819 ............................................................ 6
PWM .......................................................................... 68
RA0/AN0:RA1/AN1 Pins ............................................ 40
RA2/AN2/Vref- Pin ..................................................... 40
RA3/AN3/Vref+ Pin .................................................... 40
RA4/AN4/T0CKI Pin ................................................... 40
RA5/MCLR/Vpp Pin ................................................... 41
RA6/OSC2/CLKO Pin ................................................ 41
RA7/OSC1/CLKI Pin .................................................. 42
RB0 Pin ...................................................................... 45
RB1 Pin ...................................................................... 46
RB2 Pin ...................................................................... 47
RB3 Pin ...................................................................... 48
RB4 Pin ...................................................................... 49
RB5 Pin ...................................................................... 50
2001-2013 Microchip Technology Inc.
RB6 Pin ..................................................................... 51
RB7 Pin ..................................................................... 52
Recommended MCLR Circuit .................................... 92
SSP in I2C Mode ........................................................ 76
SSP in SPI Mode ....................................................... 74
System Clock ............................................................. 38
Timer0/WDT Prescaler .............................................. 53
Timer1 ....................................................................... 58
Timer2 ....................................................................... 63
Watchdog Timer (WDT) ............................................. 98
BOR. See Brown-out Reset.
Brown-out Reset (BOR) .............................. 89, 91, 92, 93, 94
C
C Compilers
MPLAB C18 ............................................................. 112
Capture/Compare/PWM (CCP) ......................................... 65
Capture Mode ............................................................ 66
CCP Prescaler ................................................... 66
Pin Configuration ............................................... 66
Software Interrupt .............................................. 66
Timer1 Mode Selection ...................................... 66
Capture, Compare and Timer1
Associated Registers ......................................... 67
CCP1IF ...................................................................... 66
CCPR1 ...................................................................... 66
CCPR1H:CCPR1L ..................................................... 66
Compare Mode .......................................................... 67
Pin Configuration ............................................... 67
Software Interrupt Mode .................................... 67
Special Event Trigger ........................................ 67
Special Event Trigger Output of CCP1 .............. 67
Timer1 Mode Selection ...................................... 67
PWM and Timer2
Associated Registers ......................................... 69
PWM Mode ................................................................ 68
Duty Cycle ......................................................... 68
Example Frequencies/Resolutions .................... 69
Period ................................................................ 68
Setup for Operation ........................................... 69
Timer Resources ....................................................... 65
CCP1M0 Bit ....................................................................... 65
CCP1M1 Bit ....................................................................... 65
CCP1M2 Bit ....................................................................... 65
CCP1M3 Bit ....................................................................... 65
CCP1X Bit .......................................................................... 65
CCP1Y Bit .......................................................................... 65
CCPR1H Register .............................................................. 65
CCPR1L Register .............................................................. 65
Code Examples
Changing Between Capture Prescalers ..................... 66
Changing Prescaler Assignment from Timer0
to WDT .............................................................. 55
Changing Prescaler Assignment from WDT
to Timer0 ........................................................... 55
Clearing RAM Using Indirect Addressing .................. 23
Erasing a Flash Program Memory Row ..................... 29
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service .................................... 62
Initializing PORTA ...................................................... 39
Reading a 16-Bit Free Running Timer ....................... 59
Reading Data EEPROM ............................................ 27
Reading Flash Program Memory ............................... 28
Saving Status and W Registers in RAM .................... 97
Writing a 16-Bit Free Running Timer ......................... 59
Writing to Data EEPROM .......................................... 27
DS39598F-page 167
PIC16F818/819
Writing to Flash Program Memory ............................. 31
Code Protection ......................................................... 89, 100
Computed GOTO ............................................................... 23
Configuration Bits ............................................................... 89
Crystal Oscillator and Ceramic Resonators ....................... 33
Customer Change Notification Service ............................ 173
Customer Notification Service .......................................... 173
Customer Support ............................................................ 173
D
Data EEPROM Memory ..................................................... 25
Associated Registers ................................................. 32
EEADR Register ........................................................ 25
EEADRH Register ...................................................... 25
EECON1 Register ...................................................... 25
EECON2 Register ...................................................... 25
EEDATA Register ...................................................... 25
EEDATH Register ...................................................... 25
Operation During Code-Protect .................................. 32
Protection Against Spurious Writes ............................ 32
Reading ...................................................................... 27
Write Interrupt Enable Flag (EEIF Bit) ........................ 25
Writing ........................................................................ 27
Data Memory
Special Function Registers ........................................ 13
DC and AC Characteristics
Graphs and Tables ................................................... 141
DC Characteristics
Internal RC Accuracy ............................................... 125
PIC16F818/819, PIC16LF818/819 ........................... 126
Power-Down and Supply Current ............................. 118
Supply Voltage ......................................................... 117
Development Support ...................................................... 111
Device Differences ........................................................... 165
Device Overview .................................................................. 5
Direct Addressing ............................................................... 24
E
EEADR Register ................................................................ 25
EEADRH Register .............................................................. 25
EECON1 Register .............................................................. 25
EECON2 Register .............................................................. 25
EEDATA Register .............................................................. 25
EEDATH Register .............................................................. 25
Electrical Characteristics .................................................. 115
Endurance ............................................................................ 1
Errata ................................................................................... 3
External Clock Input ........................................................... 34
External Interrupt Input (RB0/INT). See Interrupt Sources.
F
Flash Program Memory ...................................................... 25
Associated Registers ................................................. 32
EEADR Register ........................................................ 25
EEADRH Register ...................................................... 25
EECON1 Register ...................................................... 25
EECON2 Register ...................................................... 25
EEDATA Register ...................................................... 25
EEDATH Register ...................................................... 25
Erasing ....................................................................... 28
Reading ...................................................................... 28
Writing ........................................................................ 30
FSR Register .....................................................13, 14, 15, 23
G
General Purpose Register File ........................................... 10
DS39598F-page 168
I
I/O Ports ............................................................................. 39
I2C
Associated Registers ................................................. 79
Master Mode Operation ............................................. 79
Mode .......................................................................... 76
Mode Selection .......................................................... 76
Multi-Master Mode Operation .................................... 79
Slave Mode ................................................................ 77
Addressing ......................................................... 77
Reception .......................................................... 77
SCL, SDA Pins .................................................. 77
Transmission ..................................................... 77
ID Locations ................................................................89, 100
In-Circuit Debugger .......................................................... 100
In-Circuit Serial Programming ............................................ 89
In-Circuit Serial Programming (ICSP) .............................. 101
INDF Register .........................................................14, 15, 23
Indirect Addressing .......................................................23, 24
Instruction Format ............................................................ 103
Instruction Set .................................................................. 103
Descriptions ............................................................. 105
Read-Modify-Write Operations ................................ 103
Summary Table ....................................................... 104
ADDLW .................................................................... 105
ADDWF .................................................................... 105
ANDLW .................................................................... 105
ANDWF .................................................................... 105
BCF .......................................................................... 105
BSF .......................................................................... 105
BTFSC ..................................................................... 106
BTFSS ..................................................................... 106
CALL ........................................................................ 106
CLRF ....................................................................... 106
CLRW ...................................................................... 106
CLRWDT ................................................................. 106
COMF ...................................................................... 107
DECF ....................................................................... 107
DECFSZ .................................................................. 107
GOTO ...................................................................... 107
INCF ........................................................................ 107
INCFSZ .................................................................... 107
IORLW ..................................................................... 108
IORWF ..................................................................... 108
MOVF ...................................................................... 108
MOVLW ................................................................... 108
MOVWF ................................................................... 108
NOP ......................................................................... 108
RETFIE .................................................................... 109
RETLW .................................................................... 109
RETURN .................................................................. 109
RLF .......................................................................... 109
RRF ......................................................................... 109
SLEEP ..................................................................... 109
SUBLW .................................................................... 110
SUBWF .................................................................... 110
SWAPF .................................................................... 110
XORLW .................................................................... 110
XORWF ................................................................... 110
INT Interrupt (RB0/INT). See Interrupt Sources.
INTCON Register ............................................................... 15
GIE Bit ....................................................................... 18
INTE Bit ..................................................................... 18
INTF Bit ...................................................................... 18
RBIF Bit ..................................................................... 18
2001-2013 Microchip Technology Inc.
PIC16F818/819
TMR0IE Bit ................................................................. 18
Internal Oscillator Block ..................................................... 35
INTRC Modes ............................................................ 35
Internet Address ............................................................... 173
Interrupt Sources .......................................................... 89, 96
RB0/INT Pin, External ................................................ 97
TMR0 Overflow .......................................................... 97
Interrupts
RB7:RB4 Port Change ............................................... 43
Synchronous Serial Port Interrupt .............................. 20
Interrupts, Context Saving During ...................................... 97
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ............................... 96
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit) ........................................................... 97
RB0/INT Enable (INTE Bit) ........................................ 18
TMR0 Overflow Enable (TMR0IE Bit) ........................ 18
Interrupts, Enable bits
Global Interrupt Enable (GIE Bit) ............................... 18
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ............................................................. 18, 97
RB0/INT Flag (INTF Bit) ............................................. 18
TMR0 Overflow Flag (TMR0IF Bit) ............................. 97
INTRC Modes
Adjustment ................................................................. 36
L
Loading of PC .................................................................... 23
Low-Voltage ICSP Programming ..................................... 102
M
Master Clear (MCLR)
MCLR Reset, Normal Operation .....................91, 93, 94
MCLR Reset, Sleep ........................................91, 93, 94
Operation and ESD Protection ................................... 92
Memory Organization ........................................................... 9
Data Memory ............................................................. 10
Program Memory ......................................................... 9
Microchip Internet Web Site ............................................. 173
MPLAB ASM30 Assembler, Linker, Librarian .................. 112
MPLAB Integrated Development
Environment Software .............................................. 111
MPLAB PM3 Device Programmer .................................... 114
MPLAB REAL ICE In-Circuit Emulator System ................ 113
MPLINK Object Linker/MPLIB Object Librarian ............... 112
O
Opcode Field Descriptions ............................................... 103
OPTION_REG Register ..................................................... 15
INTEDG Bit .......................................................... 17, 54
PS2:PS0 Bits ............................................................. 17
PSA Bit ....................................................................... 17
RBPU Bit .............................................................. 17, 54
T0CS Bit ..................................................................... 17
T0SE Bit ..................................................................... 17
Oscillator Configuration ...................................................... 33
ECIO .......................................................................... 33
EXTCLK ..................................................................... 93
EXTRC ....................................................................... 93
HS ........................................................................ 33, 93
INTIO1 ....................................................................... 33
INTIO2 ....................................................................... 33
INTRC ........................................................................ 93
LP ......................................................................... 33, 93
RC ........................................................................ 33, 35
2001-2013 Microchip Technology Inc.
RCIO .......................................................................... 33
XT .........................................................................33, 93
Oscillator Control Register ................................................. 37
Modifying IRCF Bits ................................................... 37
Clock Transition Sequence ................................ 37
Oscillator Start-up Timer (OST) ....................................89, 92
Oscillator, WDT .................................................................. 98
P
Packaging Information ..................................................... 155
Marking .................................................................... 155
PCFG0 Bit .......................................................................... 82
PCFG1 Bit .......................................................................... 82
PCFG2 Bit .......................................................................... 82
PCFG3 Bit .......................................................................... 82
PCL Register .................................................... 13, 14, 15, 23
PCLATH Register ............................................. 13, 14, 15, 23
PCON Register .................................................................. 93
POR Bit ...................................................................... 22
Pinout Descriptions
PIC16F818/819 ........................................................... 7
Pointer, FSR ...................................................................... 23
POP ................................................................................... 23
POR. See Power-on Reset.
PORTA ................................................................................ 7
Associated Register Summary .................................. 39
Functions ................................................................... 39
PORTA Register ........................................................ 39
TRISA Register .......................................................... 39
PORTA Register ................................................................ 13
PORTB ................................................................................ 8
Associated Register Summary .................................. 44
Functions ................................................................... 44
PORTB Register ........................................................ 43
Pull-up Enable (RBPU Bit) ....................................17, 54
RB0/INT Edge Select (INTEDG Bit) .....................17, 54
RB0/INT Pin, External ................................................ 97
RB7:RB4 Interrupt-on-Change .................................. 97
RB7:RB4 Interrupt-on-Change Enable
(RBIE Bit) ........................................................... 97
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ......................................................18, 97
TRISB Register .......................................................... 43
PORTB Register ...........................................................13, 15
Postscaler, WDT
Assignment (PSA Bit) ................................................ 17
Rate Select (PS2:PS0 Bits) ....................................... 17
Power-Down Mode. See Sleep.
Power-on Reset (POR) ............................... 89, 91, 92, 93, 94
POR Status (POR Bit) ............................................... 22
Power Control (PCON) Register ................................ 93
Power-Down (PD Bit) ................................................. 91
Time-out (TO Bit) ..................................................16, 91
Power-up Timer (PWRT) ..............................................89, 92
PR2 Register ..................................................................... 63
Prescaler, Timer0
Assignment (PSA Bit) ................................................ 17
Rate Select (PS2:PS0 Bits) ....................................... 17
Program Counter
Reset Conditions ....................................................... 93
DS39598F-page 169
PIC16F818/819
Program Memory
Interrupt Vector ............................................................ 9
Map and Stack
PIC16F818 ........................................................... 9
PIC16F819 ........................................................... 9
Reset Vector ................................................................ 9
Program Verification ......................................................... 100
PUSH ................................................................................. 23
R
R/W Bit ............................................................................... 77
RA0/AN0 Pin ........................................................................ 7
RA1/AN1 Pin ........................................................................ 7
RA2/AN2/Vref- Pin ............................................................... 7
RA3/AN3/Vref+ Pin .............................................................. 7
RA4/AN4/T0CKI Pin ............................................................. 7
RA5/(MCLR/Vpp Pin ............................................................ 7
RA6/OSC2/CLKO Pin .......................................................... 7
RA7/OSC1/CLKI Pin ............................................................ 7
RB0/INT Pin ......................................................................... 8
RB1/SDI/SDA Pin ................................................................. 8
RB2/SDO/CCP1 Pin ............................................................. 8
RB3/CCP1/PGM Pin ............................................................ 8
RB4/SCK/SCL Pin ................................................................ 8
RB5/SS Pin .......................................................................... 8
RB6/T1OSO/T1CKI/PGC Pin ............................................... 8
RB7/T1OSI/PGD Pin ............................................................ 8
RBIF Bit .............................................................................. 43
RCIO Oscillator Mode ........................................................ 35
Reader Response ............................................................ 174
Receive Overflow Indicator Bit, SSPOV ............................. 73
Register File Map
PIC16F818 ................................................................. 11
PIC16F819 ................................................................. 12
Registers
ADCON0 (A/D Control 0) ........................................... 81
ADCON1 (A/D Control 1) ........................................... 82
CCP1CON (Capture/Compare/PWM Control 1) ........ 65
Configuration Word .................................................... 90
EECON1 (Data EEPROM Access Control 1) ............. 26
Initialization Conditions (table) ................................... 94
INTCON (Interrupt Control) ........................................ 18
OPTION_REG (Option) ........................................ 17, 54
OSCCON (Oscillator Control) .................................... 38
OSCTUNE (Oscillator Tuning) ................................... 36
PCON (Power Control) ............................................... 22
PIE1 (Peripheral Interrupt Enable 1) .......................... 19
PIE2 (Peripheral Interrupt Enable 2) .......................... 21
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 20
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 21
SSPCON (Synchronous Serial Port Control 1) .......... 73
SSPSTAT (Synchronous Serial Port Status) ............. 72
Status ......................................................................... 16
T1CON (Timer1 Control) ............................................ 57
T2CON (Timer2 Control) ............................................ 64
Reset ............................................................................ 89, 91
Brown-out Reset (BOR). See Brown-out
Reset (BOR).
MCLR Reset. See MCLR.
Power-on Reset (POR). See Power-on
Reset (POR).
Reset Conditions for All Registers ............................. 94
Reset Conditions for PCON Register ......................... 93
Reset Conditions for Program Counter ...................... 93
Reset Conditions for Status Register ......................... 93
WDT Reset. See Watchdog Timer (WDT).
DS39598F-page 170
Revision History ............................................................... 165
RP0 Bit ............................................................................... 10
RP1 Bit ............................................................................... 10
S
Sales and Support ........................................................... 175
SCL Clock .......................................................................... 77
Sleep .......................................................................89, 91, 99
Software Simulator (MPLAB SIM) .................................... 113
Special Event Trigger ......................................................... 87
Special Features of the CPU ............................................. 89
Special Function Register Summary .................................. 13
Special Function Registers ................................................ 13
SPI Mode
Associated Registers ................................................. 74
Serial Clock ................................................................ 71
Serial Data In ............................................................. 71
Serial Data Out .......................................................... 71
Slave Select ............................................................... 71
SSP
ACK ........................................................................... 77
I2C
I2C Operation ..................................................... 76
SSPADD Register .............................................................. 14
SSPIF ................................................................................ 20
SSPOV .............................................................................. 73
SSPOV Bit ......................................................................... 77
SSPSTAT Register ............................................................ 14
Stack .................................................................................. 23
Overflow ..................................................................... 23
Underflow ................................................................... 23
Status Register .............................................................13, 15
DC Bit ........................................................................ 16
IRP Bit ........................................................................ 16
PD Bit ......................................................................... 91
TO Bit ....................................................................16, 91
Z Bit ........................................................................... 16
Synchronous Serial Port (SSP) .......................................... 71
Overview .................................................................... 71
SPI Mode ................................................................... 71
Synchronous Serial Port Interrupt ...................................... 20
T
T1CKPS0 Bit ...................................................................... 57
T1CKPS1 Bit ...................................................................... 57
T1OSCEN Bit ..................................................................... 57
T1SYNC Bit ....................................................................... 57
T2CKPS0 Bit ...................................................................... 64
T2CKPS1 Bit ...................................................................... 64
Tad ..................................................................................... 85
Time-out Sequence ........................................................... 92
Timer0 ................................................................................ 53
Associated Registers ................................................. 55
Clock Source Edge Select (T0SE Bit) ....................... 17
Clock Source Select (T0CS Bit) ................................. 17
External Clock ............................................................ 54
Interrupt ..................................................................... 53
Operation ................................................................... 53
Overflow Enable (TMR0IE Bit) ................................... 18
Overflow Flag (TMR0IF Bit) ....................................... 97
Overflow Interrupt ...................................................... 97
Prescaler .................................................................... 54
T0CKI ......................................................................... 54
2001-2013 Microchip Technology Inc.
PIC16F818/819
Timer1 ................................................................................ 57
Associated Registers ................................................. 62
Capacitor Selection .................................................... 60
Counter Operation ..................................................... 58
Operation ................................................................... 57
Operation in Asynchronous Counter Mode ................ 59
Operation in Synchronized Counter Mode ................. 58
Operation in Timer Mode ........................................... 58
Oscillator .................................................................... 60
Oscillator Layout Considerations ............................... 60
Prescaler .................................................................... 61
Resetting Register Pair (TMR1H, TMR1L) ................. 61
Resetting Using a CCP Trigger Output ...................... 61
TMR1H ....................................................................... 59
TMR1L ....................................................................... 59
Use as a Real-Time Clock ......................................... 61
Timer2 ................................................................................ 63
Associated Registers ................................................. 64
Output ........................................................................ 63
Postscaler .................................................................. 63
Prescaler .................................................................... 63
Prescaler and Postscaler ........................................... 63
Timing Diagrams
A/D Conversion ........................................................ 140
Brown-out Reset ...................................................... 131
Capture/Compare/PWM (CCP1) .............................. 133
CLKO and I/O .......................................................... 130
External Clock .......................................................... 129
I2C Bus Data ............................................................ 137
I2C Bus Start/Stop Bits ............................................. 136
I2C Reception (7-Bit Address) .................................... 78
I2C Transmission (7-Bit Address) .............................. 78
PWM Output .............................................................. 68
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer .............................. 131
Slow Rise Time (MCLR Tied to Vdd
Through RC Network) ........................................ 96
SPI Master Mode ....................................................... 75
SPI Master Mode (CKE = 0, SMP = 0) .................... 134
SPI Master Mode (CKE = 1, SMP = 1) .................... 134
SPI Slave Mode (CKE = 0) ................................ 75, 135
SPI Slave Mode (CKE = 1) ................................ 75, 135
Time-out Sequence on Power-up (MCLR
Tied to Vdd Through Pull-up Resistor) ............... 95
Time-out Sequence on Power-up (MCLR
Tied to Vdd Through RC Network): Case 1 ....... 95
Time-out Sequence on Power-up (MCLR
Tied to Vdd Through RC Network): Case 2 ....... 95
Timer0 and Timer1 External Clock .......................... 132
Timer1 Incrementing Edge ......................................... 58
Wake-up from Sleep through Interrupt ..................... 100
Timing Parameter Symbology .......................................... 128
Timing Requirements
External Clock .......................................................... 129
TMR0 Register ................................................................... 15
TMR1CS Bit ....................................................................... 57
TMR1H Register ................................................................ 13
TMR1L Register ................................................................. 13
TMR1ON Bit ....................................................................... 57
TMR2 Register ................................................................... 13
TMR2ON Bit ....................................................................... 64
TOUTPS0 Bit ..................................................................... 64
TOUTPS1 Bit ..................................................................... 64
TOUTPS2 Bit ..................................................................... 64
TOUTPS3 Bit ..................................................................... 64
2001-2013 Microchip Technology Inc.
TRISA Register .................................................................. 14
TRISB Register .............................................................14, 15
V
Vdd Pin ................................................................................ 8
Vss Pin ................................................................................. 8
W
Wake-up from Sleep .....................................................89, 99
Interrupts ..............................................................93, 94
MCLR Reset .............................................................. 94
WDT Reset ................................................................ 94
Wake-up Using Interrupts .................................................. 99
Watchdog Timer (WDT) ................................................89, 98
Associated Registers ................................................. 98
Enable (WDTEN Bit) .................................................. 98
INTRC Oscillator ........................................................ 98
Postscaler. See Postscaler, WDT.
Programming Considerations .................................... 98
Time-out Period ......................................................... 98
WDT Reset, Normal Operation ....................... 91, 93, 94
WDT Reset, Sleep ................................................91, 94
WDT Wake-up ........................................................... 93
WCOL ................................................................................ 73
Write Collision Detect Bit, WCOL ...................................... 73
WWW Address ................................................................ 173
WWW, On-Line Support ...................................................... 3
DS39598F-page 171
PIC16F818/819
NOTES:
DS39598F-page 172
2001-2013 Microchip Technology Inc.
PIC16F818/819
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2001-2013 Microchip Technology Inc.
DS39598F-page 173
PIC16F818/819
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
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Application (optional):
Would you like a reply?
Y
N
Device: PIC16F818/819
Literature Number: DS39598F
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39598F-page 174
2001-2013 Microchip Technology Inc.
PIC16F818/819
PIC16F818/819 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
Temperature
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device
PIC16F818: Standard VDD range
PIC16F818T: (Tape and Reel)
PIC16LF818: Extended VDD range
Temperature Range
- =
I =
E =
Package
P
SO
SS
ML
PIC16LF818-I/P = Industrial temp., PDIP
package, Extended VDD limits.
PIC16F818-I/SO = Industrial temp., SOIC
package, normal VDD limits.
0°C to +70°C
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
=
=
=
=
PDIP
SOIC
SSOP
QFN
Note 1:
2:
Pattern
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices.
2001-2013 Microchip Technology Inc.
F = CMOS Flash
LF = Low-Power CMOS Flash
T = in tape and reel – SOIC, SSOP
packages only.
DS39598F-page 175
PIC16F818/819
NOTES:
DS39598F-page 176
2001-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2001-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769393
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2001-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39598F-page 177
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